IEMAllCImplSvmInstr.cpp.h@ 92500

Last change on this file since 92500 was 92493, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Purge VINF_PGM_CHANGE_MODE, no longer used.
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1	/* $Id: IEMAllCImplSvmInstr.cpp.h 92493 2021-11-18 14:01:56Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Defined Constants And Macros *
21	*********************************************************************************************************************************/
22	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
23	/**
24	* Check the common SVM instruction preconditions.
25	*/
26	# define IEM_SVM_INSTR_COMMON_CHECKS(a_pVCpu, a_Instr) \
27	do { \
28	if (!CPUMIsGuestSvmEnabled(IEM_GET_CTX(a_pVCpu))) \
29	{ \
30	Log((RT_STR(a_Instr) ": EFER.SVME not enabled -> #UD\n")); \
31	return iemRaiseUndefinedOpcode(a_pVCpu); \
32	} \
33	if (IEM_IS_REAL_OR_V86_MODE(a_pVCpu)) \
34	{ \
35	Log((RT_STR(a_Instr) ": Real or v8086 mode -> #UD\n")); \
36	return iemRaiseUndefinedOpcode(a_pVCpu); \
37	} \
38	if ((a_pVCpu)->iem.s.uCpl != 0) \
39	{ \
40	Log((RT_STR(a_Instr) ": CPL != 0 -> #GP(0)\n")); \
41	return iemRaiseGeneralProtectionFault0(a_pVCpu); \
42	} \
43	} while (0)
44
45
46	/**
47	* Converts an IEM exception event type to an SVM event type.
48	*
49	* @returns The SVM event type.
50	* @retval UINT8_MAX if the specified type of event isn't among the set
51	* of recognized IEM event types.
52	*
53	* @param uVector The vector of the event.
54	* @param fIemXcptFlags The IEM exception / interrupt flags.
55	*/
56	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
57	{
58	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
59	{
60	if (uVector != X86_XCPT_NMI)
61	return SVM_EVENT_EXCEPTION;
62	return SVM_EVENT_NMI;
63	}
64
65	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
66	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
67	return SVM_EVENT_EXCEPTION;
68
69	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
70	return SVM_EVENT_EXTERNAL_IRQ;
71
72	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
73	return SVM_EVENT_SOFTWARE_INT;
74
75	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
76	return UINT8_MAX;
77	}
78
79
80	/**
81	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
82	*
83	* @returns Strict VBox status code.
84	* @param pVCpu The cross context virtual CPU structure.
85	* @param fPdpesMapped Whether the PAE PDPEs (and PDPT) have been mapped.
86	*/
87	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPUCC pVCpu, bool fPdpesMapped)
88	{
89	/*
90	* Inform PGM about paging mode changes.
91	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
92	* see comment in iemMemPageTranslateAndCheckAccess().
93	*/
94	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 \| X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
95	AssertRCReturn(rc, rc);
96
97	/* Inform CPUM (recompiler), can later be removed. */
98	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
99
100	/*
101	* Flush the TLB with new CR3. This is required in case the PGM mode change
102	* above doesn't actually change anything.
103	*/
104	if (rc == VINF_SUCCESS)
105	{
106	rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
107	AssertRCReturn(rc, rc);
108	}
109
110	/* Re-initialize IEM cache/state after the drastic mode switch. */
111	iemReInitExec(pVCpu);
112	return rc;
113	}
114
115
116	/**
117	* SVM \#VMEXIT handler.
118	*
119	* @returns Strict VBox status code.
120	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
121	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
122	* "host state" and a shutdown is required.
123	*
124	* @param pVCpu The cross context virtual CPU structure.
125	* @param uExitCode The exit code.
126	* @param uExitInfo1 The exit info. 1 field.
127	* @param uExitInfo2 The exit info. 2 field.
128	*/
129	IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
130	{
131	VBOXSTRICTRC rcStrict;
132	if ( CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu))
133	\|\| uExitCode == SVM_EXIT_INVALID)
134	{
135	LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n",
136	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uExitCode, uExitInfo1, uExitInfo2));
137
138	/*
139	* Disable the global-interrupt flag to prevent interrupts during the 'atomic' world switch.
140	*/
141	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, false);
142
143	/*
144	* Map the nested-guest VMCB from its location in guest memory.
145	* Write exactly what the CPU does on #VMEXIT thereby preserving most other bits in the
146	* guest's VMCB in memory, see @bugref{7243#c113} and related comment on iemSvmVmrun().
147	*/
148	PSVMVMCB pVmcbMem;
149	PGMPAGEMAPLOCK PgLockMem;
150	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
151	rcStrict = iemMemPageMap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, (void **)&pVmcbMem,
152	&PgLockMem);
153	if (rcStrict == VINF_SUCCESS)
154	{
155	/*
156	* Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
157	* would have modified some VMCB state) that might need to be restored on #VMEXIT before
158	* writing the VMCB back to guest memory.
159	*/
160	HMNotifySvmNstGstVmexit(pVCpu, IEM_GET_CTX(pVCpu));
161
162	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.es));
163	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.cs));
164	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
165	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ds));
166
167	/*
168	* Save the nested-guest state into the VMCB state-save area.
169	*/
170	PSVMVMCBSTATESAVE pVmcbMemState = &pVmcbMem->guest;
171	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, ES, es);
172	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, CS, cs);
173	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, SS, ss);
174	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, DS, ds);
175	pVmcbMemState->GDTR.u32Limit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
176	pVmcbMemState->GDTR.u64Base = pVCpu->cpum.GstCtx.gdtr.pGdt;
177	pVmcbMemState->IDTR.u32Limit = pVCpu->cpum.GstCtx.idtr.cbIdt;
178	pVmcbMemState->IDTR.u64Base = pVCpu->cpum.GstCtx.idtr.pIdt;
179	pVmcbMemState->u64EFER = pVCpu->cpum.GstCtx.msrEFER;
180	pVmcbMemState->u64CR4 = pVCpu->cpum.GstCtx.cr4;
181	pVmcbMemState->u64CR3 = pVCpu->cpum.GstCtx.cr3;
182	pVmcbMemState->u64CR2 = pVCpu->cpum.GstCtx.cr2;
183	pVmcbMemState->u64CR0 = pVCpu->cpum.GstCtx.cr0;
184	/** @todo Nested paging. */
185	pVmcbMemState->u64RFlags = pVCpu->cpum.GstCtx.rflags.u64;
186	pVmcbMemState->u64RIP = pVCpu->cpum.GstCtx.rip;
187	pVmcbMemState->u64RSP = pVCpu->cpum.GstCtx.rsp;
188	pVmcbMemState->u64RAX = pVCpu->cpum.GstCtx.rax;
189	pVmcbMemState->u64DR7 = pVCpu->cpum.GstCtx.dr[7];
190	pVmcbMemState->u64DR6 = pVCpu->cpum.GstCtx.dr[6];
191	pVmcbMemState->u8CPL = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
192	Assert(CPUMGetGuestCPL(pVCpu) == pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl);
193	if (CPUMIsGuestSvmNestedPagingEnabled(pVCpu, IEM_GET_CTX(pVCpu)))
194	pVmcbMemState->u64PAT = pVCpu->cpum.GstCtx.msrPAT;
195
196	/*
197	* Save additional state and intercept information.
198	*
199	* - V_IRQ: Tracked using VMCPU_FF_INTERRUPT_NESTED_GUEST force-flag and updated below.
200	* - V_TPR: Updated by iemCImpl_load_CrX or by the physical CPU for hardware-assisted
201	* SVM execution.
202	* - Interrupt shadow: Tracked using VMCPU_FF_INHIBIT_INTERRUPTS and RIP.
203	*/
204	PSVMVMCBCTRL pVmcbMemCtrl = &pVmcbMem->ctrl;
205	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)) /* V_IRQ. */
206	pVmcbMemCtrl->IntCtrl.n.u1VIrqPending = 0;
207	else
208	{
209	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
210	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
211	}
212
213	pVmcbMemCtrl->IntCtrl.n.u8VTPR = pVmcbCtrl->IntCtrl.n.u8VTPR; /* V_TPR. */
214
215	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) /* Interrupt shadow. */
216	&& EMGetInhibitInterruptsPC(pVCpu) == pVCpu->cpum.GstCtx.rip)
217	{
218	pVmcbMemCtrl->IntShadow.n.u1IntShadow = 1;
219	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
220	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pVCpu->cpum.GstCtx.rip));
221	}
222	else
223	pVmcbMemCtrl->IntShadow.n.u1IntShadow = 0;
224
225	/*
226	* Save nRIP, instruction length and byte fields.
227	*/
228	pVmcbMemCtrl->u64NextRIP = pVmcbCtrl->u64NextRIP;
229	pVmcbMemCtrl->cbInstrFetched = pVmcbCtrl->cbInstrFetched;
230	memcpy(&pVmcbMemCtrl->abInstr[0], &pVmcbCtrl->abInstr[0], sizeof(pVmcbMemCtrl->abInstr));
231
232	/*
233	* Save exit information.
234	*/
235	pVmcbMemCtrl->u64ExitCode = uExitCode;
236	pVmcbMemCtrl->u64ExitInfo1 = uExitInfo1;
237	pVmcbMemCtrl->u64ExitInfo2 = uExitInfo2;
238
239	/*
240	* Update the exit interrupt-information field if this #VMEXIT happened as a result
241	* of delivering an event through IEM.
242	*
243	* Don't update the exit interrupt-information field if the event wasn't being injected
244	* through IEM, as it would have been updated by real hardware if the nested-guest was
245	* executed using hardware-assisted SVM.
246	*/
247	{
248	uint8_t uExitIntVector;
249	uint32_t uExitIntErr;
250	uint32_t fExitIntFlags;
251	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
252	NULL /* uExitIntCr2 */);
253	if (fRaisingEvent)
254	{
255	pVmcbCtrl->ExitIntInfo.n.u1Valid = 1;
256	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
257	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
258	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
259	{
260	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
261	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
262	}
263	}
264	}
265
266	/*
267	* Save the exit interrupt-information field.
268	*
269	* We write the whole field including overwriting reserved bits as it was observed on an
270	* AMD Ryzen 5 Pro 1500 that the CPU does not preserve reserved bits in EXITINTINFO.
271	*/
272	pVmcbMemCtrl->ExitIntInfo = pVmcbCtrl->ExitIntInfo;
273
274	/*
275	* Clear event injection.
276	*/
277	pVmcbMemCtrl->EventInject.n.u1Valid = 0;
278
279	iemMemPageUnmap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, pVmcbMem, &PgLockMem);
280	}
281
282	/*
283	* Prepare for guest's "host mode" by clearing internal processor state bits.
284	*
285	* We don't need to zero out the state-save area, just the controls should be
286	* sufficient because it has the critical bit of indicating whether we're inside
287	* the nested-guest or not.
288	*/
289	memset(pVmcbCtrl, 0, sizeof(*pVmcbCtrl));
290	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
291
292	/*
293	* Restore the subset of force-flags that were preserved.
294	*/
295	if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
296	{
297	VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
298	pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
299	}
300
301	if (rcStrict == VINF_SUCCESS)
302	{
303	/** @todo Nested paging. */
304	/** @todo ASID. */
305
306	/*
307	* If we are switching to PAE mode host, validate the PDPEs first.
308	* Any invalid PDPEs here causes a VCPU shutdown.
309	*/
310	PCSVMHOSTSTATE pHostState = &pVCpu->cpum.GstCtx.hwvirt.svm.HostState;
311	bool const fHostInPaeMode = CPUMIsPaePagingEnabled(pHostState->uCr0, pHostState->uCr4, pHostState->uEferMsr);
312	if (fHostInPaeMode)
313	rcStrict = PGMGstMapPaePdpesAtCr3(pVCpu, pHostState->uCr3);
314	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
315	{
316	/*
317	* Reload the host state.
318	*/
319	CPUMSvmVmExitRestoreHostState(pVCpu, IEM_GET_CTX(pVCpu));
320
321	/*
322	* Update PGM, IEM and others of a world-switch.
323	*/
324	rcStrict = iemSvmWorldSwitch(pVCpu, fHostInPaeMode);
325	if (rcStrict == VINF_SUCCESS)
326	rcStrict = VINF_SVM_VMEXIT;
327	else if (RT_SUCCESS(rcStrict))
328	{
329	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
330	iemSetPassUpStatus(pVCpu, rcStrict);
331	rcStrict = VINF_SVM_VMEXIT;
332	}
333	else
334	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
335	}
336	else
337	{
338	Log(("iemSvmVmexit: PAE PDPEs invalid while restoring host state. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
339	rcStrict = VINF_EM_TRIPLE_FAULT;
340	}
341	}
342	else
343	{
344	AssertMsgFailed(("iemSvmVmexit: Mapping VMCB at %#RGp failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, VBOXSTRICTRC_VAL(rcStrict)));
345	rcStrict = VINF_EM_TRIPLE_FAULT;
346	}
347	}
348	else
349	{
350	AssertMsgFailed(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode, uExitInfo1, uExitInfo2));
351	rcStrict = VERR_SVM_IPE_3;
352	}
353
354	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
355	/* CLGI/STGI may not have been intercepted and thus not executed in IEM. */
356	if ( HMIsEnabled(pVCpu->CTX_SUFF(pVM))
357	&& HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM)))
358	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
359	# endif
360	return rcStrict;
361	}
362
363
364	/**
365	* Performs the operations necessary that are part of the vmrun instruction
366	* execution in the guest.
367	*
368	* @returns Strict VBox status code (i.e. informational status codes too).
369	* @retval VINF_SUCCESS successfully executed VMRUN and entered nested-guest
370	* code execution.
371	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
372	* (SVM_EXIT_INVALID most likely).
373	*
374	* @param pVCpu The cross context virtual CPU structure.
375	* @param cbInstr The length of the VMRUN instruction.
376	* @param GCPhysVmcb Guest physical address of the VMCB to run.
377	*/
378	IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
379	{
380	LogFlow(("iemSvmVmrun\n"));
381
382	/*
383	* Cache the physical address of the VMCB for #VMEXIT exceptions.
384	*/
385	pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
386
387	/*
388	* Save the host state.
389	*/
390	CPUMSvmVmRunSaveHostState(IEM_GET_CTX(pVCpu), cbInstr);
391
392	/*
393	* Read the guest VMCB.
394	*/
395	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
396	int rc = PGMPhysSimpleReadGCPhys(pVM, &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb, GCPhysVmcb, sizeof(SVMVMCB));
397	if (RT_SUCCESS(rc))
398	{
399	/*
400	* AMD-V seems to preserve reserved fields and only writes back selected, recognized
401	* fields on #VMEXIT. However, not all reserved bits are preserved (e.g, EXITINTINFO)
402	* but in our implementation we try to preserve as much as we possibly can.
403	*
404	* We could read the entire page here and only write back the relevant fields on
405	* #VMEXIT but since our internal VMCB is also being used by HM during hardware-assisted
406	* SVM execution, it creates a potential for a nested-hypervisor to set bits that are
407	* currently reserved but may be recognized as features bits in future CPUs causing
408	* unexpected & undesired results. Hence, we zero out unrecognized fields here as we
409	* typically enter hardware-assisted SVM soon anyway, see @bugref{7243#c113}.
410	*/
411	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
412	PSVMVMCBSTATESAVE pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.guest;
413
414	RT_ZERO(pVmcbCtrl->u8Reserved0);
415	RT_ZERO(pVmcbCtrl->u8Reserved1);
416	RT_ZERO(pVmcbCtrl->u8Reserved2);
417	RT_ZERO(pVmcbNstGst->u8Reserved0);
418	RT_ZERO(pVmcbNstGst->u8Reserved1);
419	RT_ZERO(pVmcbNstGst->u8Reserved2);
420	RT_ZERO(pVmcbNstGst->u8Reserved3);
421	RT_ZERO(pVmcbNstGst->u8Reserved4);
422	RT_ZERO(pVmcbNstGst->u8Reserved5);
423	pVmcbCtrl->u32Reserved0 = 0;
424	pVmcbCtrl->TLBCtrl.n.u24Reserved = 0;
425	pVmcbCtrl->IntCtrl.n.u6Reserved = 0;
426	pVmcbCtrl->IntCtrl.n.u3Reserved = 0;
427	pVmcbCtrl->IntCtrl.n.u5Reserved = 0;
428	pVmcbCtrl->IntCtrl.n.u24Reserved = 0;
429	pVmcbCtrl->IntShadow.n.u30Reserved = 0;
430	pVmcbCtrl->ExitIntInfo.n.u19Reserved = 0;
431	pVmcbCtrl->NestedPagingCtrl.n.u29Reserved = 0;
432	pVmcbCtrl->EventInject.n.u19Reserved = 0;
433	pVmcbCtrl->LbrVirt.n.u30Reserved = 0;
434
435	/*
436	* Validate guest-state and controls.
437	*/
438	/* VMRUN must always be intercepted. */
439	if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_VMRUN))
440	{
441	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
442	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
443	}
444
445	/* Nested paging. */
446	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
447	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
448	{
449	Log(("iemSvmVmrun: Nested paging not supported -> Disabling\n"));
450	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = 0;
451	}
452
453	/* AVIC. */
454	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
455	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
456	{
457	Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
458	pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
459	}
460
461	/* Last branch record (LBR) virtualization. */
462	if ( pVmcbCtrl->LbrVirt.n.u1LbrVirt
463	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
464	{
465	Log(("iemSvmVmrun: LBR virtualization not supported -> Disabling\n"));
466	pVmcbCtrl->LbrVirt.n.u1LbrVirt = 0;
467	}
468
469	/* Virtualized VMSAVE/VMLOAD. */
470	if ( pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload
471	&& !pVM->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
472	{
473	Log(("iemSvmVmrun: Virtualized VMSAVE/VMLOAD not supported -> Disabling\n"));
474	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = 0;
475	}
476
477	/* Virtual GIF. */
478	if ( pVmcbCtrl->IntCtrl.n.u1VGifEnable
479	&& !pVM->cpum.ro.GuestFeatures.fSvmVGif)
480	{
481	Log(("iemSvmVmrun: Virtual GIF not supported -> Disabling\n"));
482	pVmcbCtrl->IntCtrl.n.u1VGifEnable = 0;
483	}
484
485	/* Guest ASID. */
486	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
487	{
488	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
489	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
490	}
491
492	/* Guest AVIC. */
493	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
494	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
495	{
496	Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
497	pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
498	}
499
500	/* Guest Secure Encrypted Virtualization. */
501	if ( ( pVmcbCtrl->NestedPagingCtrl.n.u1Sev
502	\|\| pVmcbCtrl->NestedPagingCtrl.n.u1SevEs)
503	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
504	{
505	Log(("iemSvmVmrun: SEV not supported -> Disabling\n"));
506	pVmcbCtrl->NestedPagingCtrl.n.u1Sev = 0;
507	pVmcbCtrl->NestedPagingCtrl.n.u1SevEs = 0;
508	}
509
510	/* Flush by ASID. */
511	if ( !pVM->cpum.ro.GuestFeatures.fSvmFlusbByAsid
512	&& pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_NOTHING
513	&& pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_ENTIRE)
514	{
515	Log(("iemSvmVmrun: Flush-by-ASID not supported -> #VMEXIT\n"));
516	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
517	}
518
519	/* IO permission bitmap. */
520	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
521	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
522	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
523	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
524	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
525	{
526	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
527	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
528	}
529
530	/* MSR permission bitmap. */
531	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
532	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
533	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
534	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
535	{
536	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
537	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
538	}
539
540	/* CR0. */
541	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
542	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
543	{
544	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
545	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
546	}
547	if (pVmcbNstGst->u64CR0 >> 32)
548	{
549	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
550	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
551	}
552	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
553
554	/* DR6 and DR7. */
555	if ( pVmcbNstGst->u64DR6 >> 32
556	\|\| pVmcbNstGst->u64DR7 >> 32)
557	{
558	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
559	pVmcbNstGst->u64DR6));
560	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
561	}
562
563	/*
564	* PAT (Page Attribute Table) MSR.
565	*
566	* The CPU only validates and loads it when nested-paging is enabled.
567	* See AMD spec. "15.25.4 Nested Paging and VMRUN/#VMEXIT".
568	*/
569	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
570	&& !CPUMIsPatMsrValid(pVmcbNstGst->u64PAT))
571	{
572	Log(("iemSvmVmrun: PAT invalid. u64PAT=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64PAT));
573	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
574	}
575
576	/*
577	* Copy the IO permission bitmap into the cache.
578	*/
579	AssertCompile(sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
580	rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap, GCPhysIOBitmap,
581	sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap));
582	if (RT_FAILURE(rc))
583	{
584	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
585	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
586	}
587
588	/*
589	* Copy the MSR permission bitmap into the cache.
590	*/
591	AssertCompile(sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
592	rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap, GCPhysMsrBitmap,
593	sizeof(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap));
594	if (RT_FAILURE(rc))
595	{
596	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
597	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
598	}
599
600	/*
601	* Copy segments from nested-guest VMCB state to the guest-CPU state.
602	*
603	* We do this here as we need to use the CS attributes and it's easier this way
604	* then using the VMCB format selectors. It doesn't really matter where we copy
605	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
606	*/
607	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, ES, es);
608	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, CS, cs);
609	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, SS, ss);
610	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, DS, ds);
611
612	/** @todo Segment attribute overrides by VMRUN. */
613
614	/*
615	* CPL adjustments and overrides.
616	*
617	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
618	* We shall thus adjust both CS.DPL and SS.DPL here.
619	*/
620	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
621	if (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(pVCpu)))
622	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 3;
623	if (CPUMIsGuestInRealModeEx(IEM_GET_CTX(pVCpu)))
624	pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 0;
625	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
626
627	/*
628	* Continue validating guest-state and controls.
629	*
630	* We pass CR0 as 0 to CPUMIsGuestEferMsrWriteValid() below to skip the illegal
631	* EFER.LME bit transition check. We pass the nested-guest's EFER as both the
632	* old and new EFER value to not have any guest EFER bits influence the new
633	* nested-guest EFER.
634	*/
635	uint64_t uValidEfer;
636	rc = CPUMIsGuestEferMsrWriteValid(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
637	if (RT_FAILURE(rc))
638	{
639	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
640	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
641	}
642
643	/* Validate paging and CPU mode bits. */
644	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
645	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
646	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
647	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
648	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
649	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
650	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
651	bool const fLongModeConformCS = pVCpu->cpum.GstCtx.cs.Attr.n.u1Long && pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig;
652	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
653	if (fLongModeWithPaging)
654	uValidEfer \|= MSR_K6_EFER_LMA;
655	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
656	if ( !fSvm
657	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
658	\|\| (fLongModeWithPaging && !fPae)
659	\|\| (fLongModeWithPaging && !fProtMode)
660	\|\| ( fLongModeEnabled
661	&& fPaging
662	&& fPae
663	&& fLongModeConformCS))
664	{
665	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
666	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
667	}
668
669	/*
670	* Preserve the required force-flags.
671	*
672	* We only preserve the force-flags that would affect the execution of the
673	* nested-guest (or the guest).
674	*
675	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
676	* execution of a subsequent IRET instruction in the guest.
677	*
678	* The remaining FFs (e.g. timers) can stay in place so that we will be able to
679	* generate interrupts that should cause #VMEXITs for the nested-guest.
680	*
681	* VMRUN has implicit GIF (Global Interrupt Flag) handling, we don't need to
682	* preserve VMCPU_FF_INHIBIT_INTERRUPTS.
683	*/
684	pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
685	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
686
687	/*
688	* Pause filter.
689	*/
690	if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilter)
691	{
692	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = pVmcbCtrl->u16PauseFilterCount;
693	if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilterThreshold)
694	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold = pVmcbCtrl->u16PauseFilterCount;
695	}
696
697	/*
698	* Interrupt shadow.
699	*/
700	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
701	{
702	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
703	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
704	EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
705	}
706
707	/*
708	* TLB flush control.
709	* Currently disabled since it's redundant as we unconditionally flush the TLB
710	* in iemSvmWorldSwitch() below.
711	*/
712	# if 0
713	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
714	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
715	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
716	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
717	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
718	# endif
719
720	/*
721	* Validate and map PAE PDPEs if the guest will be using PAE paging.
722	* Invalid PAE PDPEs here causes a #VMEXIT.
723	*/
724	bool fPdpesMapped;
725	if ( !pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
726	&& CPUMIsPaePagingEnabled(pVmcbNstGst->u64CR0, pVmcbNstGst->u64CR4, uValidEfer))
727	{
728	rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcbNstGst->u64CR3);
729	if (RT_SUCCESS(rc))
730	fPdpesMapped = true;
731	else
732	{
733	Log(("iemSvmVmrun: PAE PDPEs invalid -> #VMEXIT\n"));
734	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
735	}
736	}
737	else
738	fPdpesMapped = false;
739
740	/*
741	* Copy the remaining guest state from the VMCB to the guest-CPU context.
742	*/
743	pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
744	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
745	pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
746	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
747	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
748	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
749	pVCpu->cpum.GstCtx.cr3 = pVmcbNstGst->u64CR3;
750	pVCpu->cpum.GstCtx.cr2 = pVmcbNstGst->u64CR2;
751	pVCpu->cpum.GstCtx.dr[6] = pVmcbNstGst->u64DR6;
752	pVCpu->cpum.GstCtx.dr[7] = pVmcbNstGst->u64DR7;
753	pVCpu->cpum.GstCtx.rflags.u64 = pVmcbNstGst->u64RFlags;
754	pVCpu->cpum.GstCtx.rax = pVmcbNstGst->u64RAX;
755	pVCpu->cpum.GstCtx.rsp = pVmcbNstGst->u64RSP;
756	pVCpu->cpum.GstCtx.rip = pVmcbNstGst->u64RIP;
757	CPUMSetGuestEferMsrNoChecks(pVCpu, pVCpu->cpum.GstCtx.msrEFER, uValidEfer);
758	if (pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging)
759	pVCpu->cpum.GstCtx.msrPAT = pVmcbNstGst->u64PAT;
760
761	/* Mask DR6, DR7 bits mandatory set/clear bits. */
762	pVCpu->cpum.GstCtx.dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
763	pVCpu->cpum.GstCtx.dr[6] \|= X86_DR6_RA1_MASK;
764	pVCpu->cpum.GstCtx.dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
765	pVCpu->cpum.GstCtx.dr[7] \|= X86_DR7_RA1_MASK;
766
767	/*
768	* Check for pending virtual interrupts.
769	*/
770	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
771	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
772	else
773	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
774
775	/*
776	* Update PGM, IEM and others of a world-switch.
777	*/
778	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu, fPdpesMapped);
779	if (rcStrict == VINF_SUCCESS)
780	{ /* likely */ }
781	else if (RT_SUCCESS(rcStrict))
782	{
783	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
784	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
785	}
786	else
787	{
788	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
789	return rcStrict;
790	}
791
792	/*
793	* Set the global-interrupt flag to allow interrupts in the guest.
794	*/
795	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, true);
796
797	/*
798	* Event injection.
799	*/
800	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
801	pVCpu->cpum.GstCtx.hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
802	if (pEventInject->n.u1Valid)
803	{
804	uint8_t const uVector = pEventInject->n.u8Vector;
805	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject, uVector);
806	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
807
808	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
809	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
810	{
811	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
812	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
813	}
814	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
815	{
816	if ( uVector == X86_XCPT_NMI
817	\|\| uVector > X86_XCPT_LAST)
818	{
819	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
820	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
821	}
822	if ( uVector == X86_XCPT_BR
823	&& CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
824	{
825	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
826	return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
827	}
828	/** @todo any others? */
829	}
830
831	/*
832	* Invalidate the exit interrupt-information field here. This field is fully updated
833	* on #VMEXIT as events other than the one below can also cause intercepts during
834	* their injection (e.g. exceptions).
835	*/
836	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
837
838	/*
839	* Clear the event injection valid bit here. While the AMD spec. mentions that the CPU
840	* clears this bit from the VMCB unconditionally on #VMEXIT, internally the CPU could be
841	* clearing it at any time, most likely before/after injecting the event. Since VirtualBox
842	* doesn't have any virtual-CPU internal representation of this bit, we clear/update the
843	* VMCB here. This also has the added benefit that we avoid the risk of injecting the event
844	* twice if we fallback to executing the nested-guest using hardware-assisted SVM after
845	* injecting the event through IEM here.
846	*/
847	pVmcbCtrl->EventInject.n.u1Valid = 0;
848
849	/** @todo NRIP: Software interrupts can only be pushed properly if we support
850	* NRIP for the nested-guest to calculate the instruction length
851	* below. */
852	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 vec=%#x type=%d uErr=%u cr2=%#RX64 cr3=%#RX64 efer=%#RX64\n",
853	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uVector, enmType, uErrorCode, pVCpu->cpum.GstCtx.cr2,
854	pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.msrEFER));
855
856	/*
857	* We shall not inject the event here right away. There may be paging mode related updates
858	* as a result of the world-switch above that are yet to be honored. Instead flag the event
859	* as pending for injection.
860	*/
861	TRPMAssertTrap(pVCpu, uVector, enmType);
862	if (pEventInject->n.u1ErrorCodeValid)
863	TRPMSetErrorCode(pVCpu, uErrorCode);
864	if ( enmType == TRPM_TRAP
865	&& uVector == X86_XCPT_PF)
866	TRPMSetFaultAddress(pVCpu, pVCpu->cpum.GstCtx.cr2);
867	}
868	else
869	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
870	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3,
871	pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER, pVCpu->cpum.GstCtx.rflags.u64));
872
873	LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
874
875	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
876	/* If CLGI/STGI isn't intercepted we force IEM-only nested-guest execution here. */
877	if ( HMIsEnabled(pVM)
878	&& HMIsSvmVGifActive(pVM))
879	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
880	# endif
881
882	return rcStrict;
883	}
884
885	/* Shouldn't really happen as the caller should've validated the physical address already. */
886	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
887	return rc;
888	}
889
890
891	/**
892	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
893	* intercept is active.
894	*
895	* @returns Strict VBox status code.
896	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
897	* we're not executing a nested-guest.
898	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
899	* successfully.
900	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
901	* failed and a shutdown needs to be initiated for the guest.
902	*
903	* @returns VBox strict status code.
904	* @param pVCpu The cross context virtual CPU structure of the calling thread.
905	* @param u8Vector The interrupt or exception vector.
906	* @param fFlags The exception flags (see IEM_XCPT_FLAGS_XXX).
907	* @param uErr The error-code associated with the exception.
908	* @param uCr2 The CR2 value in case of a \#PF exception.
909	*/
910	IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2)
911	{
912	Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
913
914	/*
915	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
916	*
917	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_XCPT_2 #VMEXITs.
918	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
919	* even when they use a vector in the range 0 to 31.
920	* - ICEBP should not trigger #DB intercept, but its own intercept.
921	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
922	*/
923	/* Check NMI intercept */
924	if ( u8Vector == X86_XCPT_NMI
925	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
926	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
927	{
928	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
929	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
930	}
931
932	/* Check ICEBP intercept. */
933	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
934	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
935	{
936	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
937	IEM_SVM_UPDATE_NRIP(pVCpu);
938	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
939	}
940
941	/* Check CPU exception intercepts. */
942	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
943	&& IEM_SVM_IS_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
944	{
945	Assert(u8Vector <= X86_XCPT_LAST);
946	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
947	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
948	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
949	&& u8Vector == X86_XCPT_PF
950	&& !(uErr & X86_TRAP_PF_ID))
951	{
952	PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
953	# ifdef IEM_WITH_CODE_TLB
954	uint8_t const *pbInstrBuf = pVCpu->iem.s.pbInstrBuf;
955	uint8_t const cbInstrBuf = pVCpu->iem.s.cbInstrBuf;
956	pVmcbCtrl->cbInstrFetched = RT_MIN(cbInstrBuf, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
957	if ( pbInstrBuf
958	&& cbInstrBuf > 0)
959	memcpy(&pVmcbCtrl->abInstr[0], pbInstrBuf, pVmcbCtrl->cbInstrFetched);
960	# else
961	uint8_t const cbOpcode = pVCpu->iem.s.cbOpcode;
962	pVmcbCtrl->cbInstrFetched = RT_MIN(cbOpcode, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
963	if (cbOpcode > 0)
964	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[0], pVmcbCtrl->cbInstrFetched);
965	# endif
966	}
967	if (u8Vector == X86_XCPT_BR)
968	IEM_SVM_UPDATE_NRIP(pVCpu);
969	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
970	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt,
971	u8Vector, uExitInfo1, uExitInfo2));
972	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XCPT_0 + u8Vector, uExitInfo1, uExitInfo2);
973	}
974
975	/* Check software interrupt (INTn) intercepts. */
976	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
977	\| IEM_XCPT_FLAGS_BP_INSTR
978	\| IEM_XCPT_FLAGS_ICEBP_INSTR
979	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
980	&& IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
981	{
982	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
983	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
984	IEM_SVM_UPDATE_NRIP(pVCpu);
985	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
986	}
987
988	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
989	}
990
991
992	/**
993	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
994	* corresponding intercept is active.
995	*
996	* @returns Strict VBox status code.
997	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
998	* we're not executing a nested-guest.
999	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1000	* successfully.
1001	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1002	* failed and a shutdown needs to be initiated for the guest.
1003	*
1004	* @returns VBox strict status code.
1005	* @param pVCpu The cross context virtual CPU structure of the calling thread.
1006	* @param u16Port The IO port being accessed.
1007	* @param enmIoType The type of IO access.
1008	* @param cbReg The IO operand size in bytes.
1009	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
1010	* @param iEffSeg The effective segment number.
1011	* @param fRep Whether this is a repeating IO instruction (REP prefix).
1012	* @param fStrIo Whether this is a string IO instruction.
1013	* @param cbInstr The length of the IO instruction in bytes.
1014	*/
1015	IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1016	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
1017	{
1018	Assert(IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
1019	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
1020	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
1021
1022	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
1023
1024	SVMIOIOEXITINFO IoExitInfo;
1025	bool const fIntercept = CPUMIsSvmIoInterceptSet(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap, u16Port, enmIoType, cbReg,
1026	cAddrSizeBits, iEffSeg, fRep, fStrIo, &IoExitInfo);
1027	if (fIntercept)
1028	{
1029	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
1030	IEM_SVM_UPDATE_NRIP(pVCpu);
1031	return iemSvmVmexit(pVCpu, SVM_EXIT_IOIO, IoExitInfo.u, pVCpu->cpum.GstCtx.rip + cbInstr);
1032	}
1033
1034	/** @todo remove later (for debugging as VirtualBox always traps all IO
1035	* intercepts). */
1036	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
1037	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
1038	}
1039
1040
1041	/**
1042	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
1043	* corresponding intercept is active.
1044	*
1045	* @returns Strict VBox status code.
1046	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1047	* specify interception of the accessed MSR @a idMsr.
1048	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1049	* successfully.
1050	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1051	* failed and a shutdown needs to be initiated for the guest.
1052	*
1053	* @param pVCpu The cross context virtual CPU structure.
1054	* @param idMsr The MSR being accessed in the nested-guest.
1055	* @param fWrite Whether this is an MSR write access, @c false implies an
1056	* MSR read.
1057	* @param cbInstr The length of the MSR read/write instruction in bytes.
1058	*/
1059	IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite)
1060	{
1061	/*
1062	* Check if any MSRs are being intercepted.
1063	*/
1064	Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_MSR_PROT));
1065	Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1066
1067	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1068
1069	/*
1070	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1071	*/
1072	uint16_t offMsrpm;
1073	uint8_t uMsrpmBit;
1074	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1075	if (RT_SUCCESS(rc))
1076	{
1077	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
1078	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1079	if (fWrite)
1080	++uMsrpmBit;
1081
1082	/*
1083	* Check if the bit is set, if so, trigger a #VMEXIT.
1084	*/
1085	if (pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm] & RT_BIT(uMsrpmBit))
1086	{
1087	IEM_SVM_UPDATE_NRIP(pVCpu);
1088	return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1089	}
1090	}
1091	else
1092	{
1093	/*
1094	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (nested hypervisor) deal with it.
1095	*/
1096	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1097	return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1098	}
1099	return VINF_SVM_INTERCEPT_NOT_ACTIVE;
1100	}
1101
1102
1103
1104	/**
1105	* Implements 'VMRUN'.
1106	*/
1107	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1108	{
1109	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1110	RT_NOREF2(pVCpu, cbInstr);
1111	return VINF_EM_RAW_EMULATE_INSTR;
1112	# else
1113	LogFlow(("iemCImpl_vmrun\n"));
1114	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1115
1116	/** @todo Check effective address size using address size prefix. */
1117	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1118	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1119	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1120	{
1121	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1122	return iemRaiseGeneralProtectionFault0(pVCpu);
1123	}
1124
1125	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1126	{
1127	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1128	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1129	}
1130
1131	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, cbInstr, GCPhysVmcb);
1132	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1133	{
1134	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1135	rcStrict = VINF_EM_TRIPLE_FAULT;
1136	}
1137	return rcStrict;
1138	# endif
1139	}
1140
1141
1142	/**
1143	* Implements 'VMLOAD'.
1144	*/
1145	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1146	{
1147	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1148	RT_NOREF2(pVCpu, cbInstr);
1149	return VINF_EM_RAW_EMULATE_INSTR;
1150	# else
1151	LogFlow(("iemCImpl_vmload\n"));
1152	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1153
1154	/** @todo Check effective address size using address size prefix. */
1155	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1156	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1157	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1158	{
1159	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1160	return iemRaiseGeneralProtectionFault0(pVCpu);
1161	}
1162
1163	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1164	{
1165	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1166	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1167	}
1168
1169	SVMVMCBSTATESAVE VmcbNstGst;
1170	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest),
1171	sizeof(SVMVMCBSTATESAVE));
1172	if (rcStrict == VINF_SUCCESS)
1173	{
1174	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1175	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1176	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1177	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1178	HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1179
1180	pVCpu->cpum.GstCtx.msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1181	pVCpu->cpum.GstCtx.msrSTAR = VmcbNstGst.u64STAR;
1182	pVCpu->cpum.GstCtx.msrLSTAR = VmcbNstGst.u64LSTAR;
1183	pVCpu->cpum.GstCtx.msrCSTAR = VmcbNstGst.u64CSTAR;
1184	pVCpu->cpum.GstCtx.msrSFMASK = VmcbNstGst.u64SFMASK;
1185
1186	pVCpu->cpum.GstCtx.SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1187	pVCpu->cpum.GstCtx.SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1188	pVCpu->cpum.GstCtx.SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1189
1190	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1191	}
1192	return rcStrict;
1193	# endif
1194	}
1195
1196
1197	/**
1198	* Implements 'VMSAVE'.
1199	*/
1200	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1201	{
1202	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1203	RT_NOREF2(pVCpu, cbInstr);
1204	return VINF_EM_RAW_EMULATE_INSTR;
1205	# else
1206	LogFlow(("iemCImpl_vmsave\n"));
1207	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1208
1209	/** @todo Check effective address size using address size prefix. */
1210	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1211	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1212	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1213	{
1214	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1215	return iemRaiseGeneralProtectionFault0(pVCpu);
1216	}
1217
1218	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1219	{
1220	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1221	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1222	}
1223
1224	SVMVMCBSTATESAVE VmcbNstGst;
1225	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest),
1226	sizeof(SVMVMCBSTATESAVE));
1227	if (rcStrict == VINF_SUCCESS)
1228	{
1229	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1230	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR
1231	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS);
1232
1233	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1234	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1235	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1236	HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1237
1238	VmcbNstGst.u64KernelGSBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
1239	VmcbNstGst.u64STAR = pVCpu->cpum.GstCtx.msrSTAR;
1240	VmcbNstGst.u64LSTAR = pVCpu->cpum.GstCtx.msrLSTAR;
1241	VmcbNstGst.u64CSTAR = pVCpu->cpum.GstCtx.msrCSTAR;
1242	VmcbNstGst.u64SFMASK = pVCpu->cpum.GstCtx.msrSFMASK;
1243
1244	VmcbNstGst.u64SysEnterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1245	VmcbNstGst.u64SysEnterESP = pVCpu->cpum.GstCtx.SysEnter.esp;
1246	VmcbNstGst.u64SysEnterEIP = pVCpu->cpum.GstCtx.SysEnter.eip;
1247
1248	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_UOFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1249	sizeof(SVMVMCBSTATESAVE));
1250	if (rcStrict == VINF_SUCCESS)
1251	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1252	}
1253	return rcStrict;
1254	# endif
1255	}
1256
1257
1258	/**
1259	* Implements 'CLGI'.
1260	*/
1261	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1262	{
1263	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1264	RT_NOREF2(pVCpu, cbInstr);
1265	return VINF_EM_RAW_EMULATE_INSTR;
1266	# else
1267	LogFlow(("iemCImpl_clgi\n"));
1268	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1269	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1270	{
1271	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1272	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1273	}
1274
1275	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, false);
1276	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1277
1278	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1279	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1280	# else
1281	return VINF_SUCCESS;
1282	# endif
1283	# endif
1284	}
1285
1286
1287	/**
1288	* Implements 'STGI'.
1289	*/
1290	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1291	{
1292	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1293	RT_NOREF2(pVCpu, cbInstr);
1294	return VINF_EM_RAW_EMULATE_INSTR;
1295	# else
1296	LogFlow(("iemCImpl_stgi\n"));
1297	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1298	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1299	{
1300	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1301	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1302	}
1303
1304	CPUMSetGuestGif(&pVCpu->cpum.GstCtx, true);
1305	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1306
1307	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1308	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1309	# else
1310	return VINF_SUCCESS;
1311	# endif
1312	# endif
1313	}
1314
1315
1316	/**
1317	* Implements 'INVLPGA'.
1318	*/
1319	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1320	{
1321	/** @todo Check effective address size using address size prefix. */
1322	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1323	/** @todo PGM needs virtual ASID support. */
1324	# if 0
1325	uint32_t const uAsid = pVCpu->cpum.GstCtx.ecx;
1326	# endif
1327
1328	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1329	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1330	{
1331	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1332	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1333	}
1334
1335	PGMInvalidatePage(pVCpu, GCPtrPage);
1336	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1337	return VINF_SUCCESS;
1338	}
1339
1340
1341	/**
1342	* Implements 'SKINIT'.
1343	*/
1344	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1345	{
1346	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1347
1348	uint32_t uIgnore;
1349	uint32_t fFeaturesECX;
1350	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1351	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1352	return iemRaiseUndefinedOpcode(pVCpu);
1353
1354	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1355	{
1356	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1357	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1358	}
1359
1360	RT_NOREF(cbInstr);
1361	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1362	}
1363
1364
1365	/**
1366	* Implements SVM's implementation of PAUSE.
1367	*/
1368	IEM_CIMPL_DEF_0(iemCImpl_svm_pause)
1369	{
1370	bool fCheckIntercept = true;
1371	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilter)
1372	{
1373	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1374
1375	/* TSC based pause-filter thresholding. */
1376	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilterThreshold
1377	&& pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold > 0)
1378	{
1379	uint64_t const uTick = TMCpuTickGet(pVCpu);
1380	if (uTick - pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick > pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold)
1381	pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = CPUMGetGuestSvmPauseFilterCount(pVCpu, IEM_GET_CTX(pVCpu));
1382	pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick = uTick;
1383	}
1384
1385	/* Simple pause-filter counter. */
1386	if (pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter > 0)
1387	{
1388	--pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter;
1389	fCheckIntercept = false;
1390	}
1391	}
1392
1393	if (fCheckIntercept)
1394	IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0);
1395
1396	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1397	return VINF_SUCCESS;
1398	}
1399
1400	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
1401
1402	/**
1403	* Common code for iemCImpl_vmmcall and iemCImpl_vmcall (latter in IEMAllCImplVmxInstr.cpp.h).
1404	*/
1405	IEM_CIMPL_DEF_1(iemCImpl_Hypercall, uint16_t, uDisOpcode)
1406	{
1407	if (EMAreHypercallInstructionsEnabled(pVCpu))
1408	{
1409	NOREF(uDisOpcode);
1410	VBOXSTRICTRC rcStrict = GIMHypercallEx(pVCpu, IEM_GET_CTX(pVCpu), uDisOpcode, cbInstr);
1411	if (RT_SUCCESS(rcStrict))
1412	{
1413	if (rcStrict == VINF_SUCCESS)
1414	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1415	if ( rcStrict == VINF_SUCCESS
1416	\|\| rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
1417	return VINF_SUCCESS;
1418	AssertMsgReturn(rcStrict == VINF_GIM_R3_HYPERCALL, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1419	return rcStrict;
1420	}
1421	AssertMsgReturn( rcStrict == VERR_GIM_HYPERCALL_ACCESS_DENIED
1422	\|\| rcStrict == VERR_GIM_HYPERCALLS_NOT_AVAILABLE
1423	\|\| rcStrict == VERR_GIM_NOT_ENABLED
1424	\|\| rcStrict == VERR_GIM_HYPERCALL_MEMORY_READ_FAILED
1425	\|\| rcStrict == VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED,
1426	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1427
1428	/* Raise #UD on all failures. */
1429	}
1430	return iemRaiseUndefinedOpcode(pVCpu);
1431	}
1432
1433
1434	/**
1435	* Implements 'VMMCALL'.
1436	*/
1437	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1438	{
1439	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1440	{
1441	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1442	IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1443	}
1444
1445	/* This is a little bit more complicated than the VT-x version because HM/SVM may
1446	patch MOV CR8 instructions to speed up APIC.TPR access for 32-bit windows guests. */
1447	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1448	if (VM_IS_HM_ENABLED(pVM))
1449	{
1450	int rc = HMHCMaybeMovTprSvmHypercall(pVM, pVCpu);
1451	if (RT_SUCCESS(rc))
1452	{
1453	Log(("vmmcall: MovTpr\n"));
1454	return VINF_SUCCESS;
1455	}
1456	}
1457
1458	/* Join forces with vmcall. */
1459	return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMMCALL);
1460	}
1461

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 92500

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