VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 75142

Last change on this file since 75142 was 75135, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Setup VMX preemption timer, remove verbose comment later if needed.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 75135 2018-10-29 04:27:39Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
20/** @todo NSTVMX: The following VM-exit intercepts are pending:
21 * VMX_EXIT_INIT_SIGNAL
22 * VMX_EXIT_SIPI
23 * VMX_EXIT_IO_SMI
24 * VMX_EXIT_SMI
25 * VMX_EXIT_INT_WINDOW
26 * VMX_EXIT_NMI_WINDOW
27 * VMX_EXIT_GETSEC
28 * VMX_EXIT_RSM
29 * VMX_EXIT_MTF
30 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
31 * VMX_EXIT_ERR_MACHINE_CHECK
32 * VMX_EXIT_TPR_BELOW_THRESHOLD
33 * VMX_EXIT_APIC_ACCESS
34 * VMX_EXIT_VIRTUALIZED_EOI
35 * VMX_EXIT_EPT_VIOLATION
36 * VMX_EXIT_EPT_MISCONFIG
37 * VMX_EXIT_INVEPT
38 * VMX_EXIT_PREEMPT_TIMER
39 * VMX_EXIT_INVVPID
40 * VMX_EXIT_APIC_WRITE
41 * VMX_EXIT_RDRAND
42 * VMX_EXIT_VMFUNC
43 * VMX_EXIT_ENCLS
44 * VMX_EXIT_RDSEED
45 * VMX_EXIT_PML_FULL
46 * VMX_EXIT_XSAVES
47 * VMX_EXIT_XRSTORS
48 */
49
50/**
51 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
52 *
53 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
54 * second dimension is the Index, see VMXVMCSFIELDENC.
55 */
56uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
57{
58 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
59 {
60 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
61 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
62 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
63 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
64 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
65 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
66 },
67 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
68 {
69 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
70 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
71 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
72 /* 24-25 */ UINT16_MAX, UINT16_MAX
73 },
74 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
75 {
76 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
77 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
78 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
79 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
80 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
81 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
82 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
83 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
84 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
85 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
86 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
87 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
88 },
89 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
90 {
91 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
92 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
93 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
94 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
95 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
96 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
97 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
98 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
99 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
100 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
101 },
102 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
103 {
104 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
105 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
106 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
107 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
108 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
109 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
110 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
111 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
112 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
113 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
114 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
115 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
116 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
117 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
118 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
119 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
120 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
121 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
122 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
123 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
124 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
125 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
126 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
127 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
128 /* 24 */ UINT16_MAX,
129 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
130 },
131 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
132 {
133 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
134 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
135 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
136 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
137 /* 25 */ UINT16_MAX
138 },
139 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
140 {
141 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
142 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
143 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
144 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
145 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
146 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
147 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
148 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
149 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
150 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
151 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
152 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
153 },
154 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
155 {
156 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
157 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
158 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
159 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
160 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
161 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
162 },
163 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
164 {
165 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
166 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
167 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
168 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
169 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
170 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
171 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
172 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
173 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
174 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
175 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
176 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
177 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
178 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
179 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
180 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
181 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
182 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
183 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
184 },
185 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
186 {
187 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
188 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
189 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
190 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
191 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
192 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
193 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
194 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
195 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
196 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
197 /* 24-25 */ UINT16_MAX, UINT16_MAX
198 },
199 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
200 {
201 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
202 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
203 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
204 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
205 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
206 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
207 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
208 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
209 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
210 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
211 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
212 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
213 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
214 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
215 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
216 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
217 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
218 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
219 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
220 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
221 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
222 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
223 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
224 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
225 /* 24-25 */ UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
230 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 25 */ UINT16_MAX
234 },
235 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
244 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
245 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
247 /* 24-25 */ UINT16_MAX, UINT16_MAX
248 },
249 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
250 {
251 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
252 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
253 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
254 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
255 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
256 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
257 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
260 },
261 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
262 {
263 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
264 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
265 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
266 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
267 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
268 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
269 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
270 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
271 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
272 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
273 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
274 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
275 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
276 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
277 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
278 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
279 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
280 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
281 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
282 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
283 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
284 },
285 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
297 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
298 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
299 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 }
302};
303
304
305/**
306 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
307 * relative offsets.
308 */
309# ifdef IEM_WITH_CODE_TLB
310# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
311# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
312# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
313# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
314# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
315# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
316# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
317# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
318# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
319# else /* !IEM_WITH_CODE_TLB */
320# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
321 do \
322 { \
323 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
324 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
325 } while (0)
326
327# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
328
329# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
330 do \
331 { \
332 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
333 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
334 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
335 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
336 } while (0)
337
338# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
339 do \
340 { \
341 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
342 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
343 } while (0)
344
345# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
346 do \
347 { \
348 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
349 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
350 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
351 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
352 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
353 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
354 } while (0)
355
356# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
357 do \
358 { \
359 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
360 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
361 } while (0)
362
363# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
364 do \
365 { \
366 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
367 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
368 } while (0)
369
370# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
371 do \
372 { \
373 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
374 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
375 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
376 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
377 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
378 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
379 } while (0)
380# endif /* !IEM_WITH_CODE_TLB */
381
382/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
383#define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
384
385/** Whether a shadow VMCS is present for the given VCPU. */
386#define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
387
388/** Gets the VMXON region pointer. */
389#define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
390
391/** Gets the guest-physical address of the current VMCS for the given VCPU. */
392#define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
393
394/** Whether a current VMCS is present for the given VCPU. */
395#define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
396
397/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
398#define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
399 do \
400 { \
401 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
402 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
403 } while (0)
404
405/** Clears any current VMCS for the given VCPU. */
406#define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
407 do \
408 { \
409 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
410 } while (0)
411
412/** Check for VMX instructions requiring to be in VMX operation.
413 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
414#define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
415 do \
416 { \
417 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
418 { /* likely */ } \
419 else \
420 { \
421 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
422 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
423 return iemRaiseUndefinedOpcode(a_pVCpu); \
424 } \
425 } while (0)
426
427/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
428#define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
429 do \
430 { \
431 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
432 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
433 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
434 return VERR_VMX_VMENTRY_FAILED; \
435 } while (0)
436
437/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
438#define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
439 do \
440 { \
441 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
442 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
443 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
444 return VERR_VMX_VMEXIT_FAILED; \
445 } while (0)
446
447
448/**
449 * Returns whether the given VMCS field is valid and supported by our emulation.
450 *
451 * @param pVCpu The cross context virtual CPU structure.
452 * @param u64FieldEnc The VMCS field encoding.
453 *
454 * @remarks This takes into account the CPU features exposed to the guest.
455 */
456IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
457{
458 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
459 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
460 if (!uFieldEncHi)
461 { /* likely */ }
462 else
463 return false;
464
465 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
466 switch (uFieldEncLo)
467 {
468 /*
469 * 16-bit fields.
470 */
471 /* Control fields. */
472 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
473 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
474 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
475
476 /* Guest-state fields. */
477 case VMX_VMCS16_GUEST_ES_SEL:
478 case VMX_VMCS16_GUEST_CS_SEL:
479 case VMX_VMCS16_GUEST_SS_SEL:
480 case VMX_VMCS16_GUEST_DS_SEL:
481 case VMX_VMCS16_GUEST_FS_SEL:
482 case VMX_VMCS16_GUEST_GS_SEL:
483 case VMX_VMCS16_GUEST_LDTR_SEL:
484 case VMX_VMCS16_GUEST_TR_SEL:
485 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
486 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
487
488 /* Host-state fields. */
489 case VMX_VMCS16_HOST_ES_SEL:
490 case VMX_VMCS16_HOST_CS_SEL:
491 case VMX_VMCS16_HOST_SS_SEL:
492 case VMX_VMCS16_HOST_DS_SEL:
493 case VMX_VMCS16_HOST_FS_SEL:
494 case VMX_VMCS16_HOST_GS_SEL:
495 case VMX_VMCS16_HOST_TR_SEL: return true;
496
497 /*
498 * 64-bit fields.
499 */
500 /* Control fields. */
501 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
502 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
503 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
504 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
505 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
506 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
507 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
508 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
509 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
510 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
511 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
512 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
513 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
514 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
515 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
516 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
517 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
518 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
519 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
520 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
521 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
522 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
523 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
524 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
525 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
526 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
527 case VMX_VMCS64_CTRL_EPTP_FULL:
528 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
529 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
532 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
533 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
534 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
535 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
536 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
537 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
538 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
539 {
540 uint64_t const uVmFuncMsr = CPUMGetGuestIa32VmxVmFunc(pVCpu);
541 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
542 }
543 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
545 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
547 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
548 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
549 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
550 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
551 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
552 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
553 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
554 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
555
556 /* Read-only data fields. */
557 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
558 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
559
560 /* Guest-state fields. */
561 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
562 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
563 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
564 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
565 case VMX_VMCS64_GUEST_PAT_FULL:
566 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
567 case VMX_VMCS64_GUEST_EFER_FULL:
568 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
569 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
570 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
571 case VMX_VMCS64_GUEST_PDPTE0_FULL:
572 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
573 case VMX_VMCS64_GUEST_PDPTE1_FULL:
574 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
575 case VMX_VMCS64_GUEST_PDPTE2_FULL:
576 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
577 case VMX_VMCS64_GUEST_PDPTE3_FULL:
578 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
579 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
580 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
581
582 /* Host-state fields. */
583 case VMX_VMCS64_HOST_PAT_FULL:
584 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
585 case VMX_VMCS64_HOST_EFER_FULL:
586 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
587 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
588 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
589
590 /*
591 * 32-bit fields.
592 */
593 /* Control fields. */
594 case VMX_VMCS32_CTRL_PIN_EXEC:
595 case VMX_VMCS32_CTRL_PROC_EXEC:
596 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
597 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
598 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
599 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
600 case VMX_VMCS32_CTRL_EXIT:
601 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
602 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
603 case VMX_VMCS32_CTRL_ENTRY:
604 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
605 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
606 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
607 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
608 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
609 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
610 case VMX_VMCS32_CTRL_PLE_GAP:
611 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
612
613 /* Read-only data fields. */
614 case VMX_VMCS32_RO_VM_INSTR_ERROR:
615 case VMX_VMCS32_RO_EXIT_REASON:
616 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
617 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
618 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
619 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
620 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
621 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
622
623 /* Guest-state fields. */
624 case VMX_VMCS32_GUEST_ES_LIMIT:
625 case VMX_VMCS32_GUEST_CS_LIMIT:
626 case VMX_VMCS32_GUEST_SS_LIMIT:
627 case VMX_VMCS32_GUEST_DS_LIMIT:
628 case VMX_VMCS32_GUEST_FS_LIMIT:
629 case VMX_VMCS32_GUEST_GS_LIMIT:
630 case VMX_VMCS32_GUEST_LDTR_LIMIT:
631 case VMX_VMCS32_GUEST_TR_LIMIT:
632 case VMX_VMCS32_GUEST_GDTR_LIMIT:
633 case VMX_VMCS32_GUEST_IDTR_LIMIT:
634 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
638 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
639 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
640 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
641 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
642 case VMX_VMCS32_GUEST_INT_STATE:
643 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
644 case VMX_VMCS32_GUEST_SMBASE:
645 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
646 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
647
648 /* Host-state fields. */
649 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
650
651 /*
652 * Natural-width fields.
653 */
654 /* Control fields. */
655 case VMX_VMCS_CTRL_CR0_MASK:
656 case VMX_VMCS_CTRL_CR4_MASK:
657 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
658 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
659 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
660 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
661 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
662 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
663
664 /* Read-only data fields. */
665 case VMX_VMCS_RO_EXIT_QUALIFICATION:
666 case VMX_VMCS_RO_IO_RCX:
667 case VMX_VMCS_RO_IO_RSX:
668 case VMX_VMCS_RO_IO_RDI:
669 case VMX_VMCS_RO_IO_RIP:
670 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
671
672 /* Guest-state fields. */
673 case VMX_VMCS_GUEST_CR0:
674 case VMX_VMCS_GUEST_CR3:
675 case VMX_VMCS_GUEST_CR4:
676 case VMX_VMCS_GUEST_ES_BASE:
677 case VMX_VMCS_GUEST_CS_BASE:
678 case VMX_VMCS_GUEST_SS_BASE:
679 case VMX_VMCS_GUEST_DS_BASE:
680 case VMX_VMCS_GUEST_FS_BASE:
681 case VMX_VMCS_GUEST_GS_BASE:
682 case VMX_VMCS_GUEST_LDTR_BASE:
683 case VMX_VMCS_GUEST_TR_BASE:
684 case VMX_VMCS_GUEST_GDTR_BASE:
685 case VMX_VMCS_GUEST_IDTR_BASE:
686 case VMX_VMCS_GUEST_DR7:
687 case VMX_VMCS_GUEST_RSP:
688 case VMX_VMCS_GUEST_RIP:
689 case VMX_VMCS_GUEST_RFLAGS:
690 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
691 case VMX_VMCS_GUEST_SYSENTER_ESP:
692 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
693
694 /* Host-state fields. */
695 case VMX_VMCS_HOST_CR0:
696 case VMX_VMCS_HOST_CR3:
697 case VMX_VMCS_HOST_CR4:
698 case VMX_VMCS_HOST_FS_BASE:
699 case VMX_VMCS_HOST_GS_BASE:
700 case VMX_VMCS_HOST_TR_BASE:
701 case VMX_VMCS_HOST_GDTR_BASE:
702 case VMX_VMCS_HOST_IDTR_BASE:
703 case VMX_VMCS_HOST_SYSENTER_ESP:
704 case VMX_VMCS_HOST_SYSENTER_EIP:
705 case VMX_VMCS_HOST_RSP:
706 case VMX_VMCS_HOST_RIP: return true;
707 }
708
709 return false;
710}
711
712
713/**
714 * Gets a host selector from the VMCS.
715 *
716 * @param pVmcs Pointer to the virtual VMCS.
717 * @param iSelReg The index of the segment register (X86_SREG_XXX).
718 */
719DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
720{
721 Assert(iSegReg < X86_SREG_COUNT);
722 RTSEL HostSel;
723 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
724 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
725 uint8_t const uWidthType = (uWidth << 2) | uType;
726 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
727 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
728 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
729 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
730 uint8_t const *pbField = pbVmcs + offField;
731 HostSel = *(uint16_t *)pbField;
732 return HostSel;
733}
734
735
736/**
737 * Sets a guest segment register in the VMCS.
738 *
739 * @param pVmcs Pointer to the virtual VMCS.
740 * @param iSegReg The index of the segment register (X86_SREG_XXX).
741 * @param pSelReg Pointer to the segment register.
742 */
743IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
744{
745 Assert(pSelReg);
746 Assert(iSegReg < X86_SREG_COUNT);
747
748 /* Selector. */
749 {
750 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
751 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
752 uint8_t const uWidthType = (uWidth << 2) | uType;
753 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
754 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
755 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
756 uint8_t *pbVmcs = (uint8_t *)pVmcs;
757 uint8_t *pbField = pbVmcs + offField;
758 *(uint16_t *)pbField = pSelReg->Sel;
759 }
760
761 /* Limit. */
762 {
763 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
764 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
765 uint8_t const uWidthType = (uWidth << 2) | uType;
766 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
767 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
768 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
769 uint8_t *pbVmcs = (uint8_t *)pVmcs;
770 uint8_t *pbField = pbVmcs + offField;
771 *(uint32_t *)pbField = pSelReg->u32Limit;
772 }
773
774 /* Base. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t const *pbField = pbVmcs + offField;
784 *(uint64_t *)pbField = pSelReg->u64Base;
785 }
786
787 /* Attributes. */
788 {
789 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
790 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
791 | X86DESCATTR_UNUSABLE;
792 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
793 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
794 uint8_t const uWidthType = (uWidth << 2) | uType;
795 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
796 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
797 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
798 uint8_t *pbVmcs = (uint8_t *)pVmcs;
799 uint8_t *pbField = pbVmcs + offField;
800 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
801 }
802}
803
804
805/**
806 * Gets a guest segment register from the VMCS.
807 *
808 * @returns VBox status code.
809 * @param pVmcs Pointer to the virtual VMCS.
810 * @param iSegReg The index of the segment register (X86_SREG_XXX).
811 * @param pSelReg Where to store the segment register (only updated when
812 * VINF_SUCCESS is returned).
813 *
814 * @remarks Warning! This does not validate the contents of the retrieved segment
815 * register.
816 */
817IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
818{
819 Assert(pSelReg);
820 Assert(iSegReg < X86_SREG_COUNT);
821
822 /* Selector. */
823 uint16_t u16Sel;
824 {
825 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
826 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
827 uint8_t const uWidthType = (uWidth << 2) | uType;
828 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
829 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
830 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
831 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
832 uint8_t const *pbField = pbVmcs + offField;
833 u16Sel = *(uint16_t *)pbField;
834 }
835
836 /* Limit. */
837 uint32_t u32Limit;
838 {
839 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
840 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
841 uint8_t const uWidthType = (uWidth << 2) | uType;
842 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
843 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
844 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
845 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
846 uint8_t const *pbField = pbVmcs + offField;
847 u32Limit = *(uint32_t *)pbField;
848 }
849
850 /* Base. */
851 uint64_t u64Base;
852 {
853 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
854 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
855 uint8_t const uWidthType = (uWidth << 2) | uType;
856 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
857 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
858 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
859 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
860 uint8_t const *pbField = pbVmcs + offField;
861 u64Base = *(uint64_t *)pbField;
862 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
863 }
864
865 /* Attributes. */
866 uint32_t u32Attr;
867 {
868 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
869 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
870 uint8_t const uWidthType = (uWidth << 2) | uType;
871 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
872 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
873 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
874 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
875 uint8_t const *pbField = pbVmcs + offField;
876 u32Attr = *(uint32_t *)pbField;
877 }
878
879 pSelReg->Sel = u16Sel;
880 pSelReg->ValidSel = u16Sel;
881 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
882 pSelReg->u32Limit = u32Limit;
883 pSelReg->u64Base = u64Base;
884 pSelReg->Attr.u = u32Attr;
885 return VINF_SUCCESS;
886}
887
888
889/**
890 * Gets a CR3 target value from the VMCS.
891 *
892 * @returns VBox status code.
893 * @param pVmcs Pointer to the virtual VMCS.
894 * @param idxCr3Target The index of the CR3-target value to retrieve.
895 * @param puValue Where to store the CR3-target value.
896 */
897DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
898{
899 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
900 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
901 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
902 uint8_t const uWidthType = (uWidth << 2) | uType;
903 uint8_t const uIndex = (idxCr3Target << 1) + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
904 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
905 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
906 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
907 uint8_t const *pbField = pbVmcs + offField;
908 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
909
910 return uCr3TargetValue;
911}
912
913
914/**
915 * Reads a 32-bit register from the virtual-APIC page at the given offset.
916 *
917 * @returns The register from the virtual-APIC page.
918 * @param pVCpu The cross context virtual CPU structure.
919 * @param offReg The offset of the register being read.
920 */
921DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint8_t offReg)
922{
923 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
924 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
925 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
926 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
927 return uReg;
928}
929
930
931/**
932 * Writes a 32-bit register to the virtual-APIC page at the given offset.
933 *
934 * @param pVCpu The cross context virtual CPU structure.
935 * @param uReg The register value to write.
936 * @param offReg The offset of the register being written.
937 */
938DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint32_t uReg, uint8_t offReg)
939{
940 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
941 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
942 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
943 *(uint32_t *)(pbVirtApic + offReg) = uReg;
944}
945
946
947/**
948 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
949 * mask and the read-shadow (CR0/CR4 read).
950 *
951 * @returns The masked CR0/CR4.
952 * @param pVCpu The cross context virtual CPU structure.
953 * @param iCrReg The control register (either CR0 or CR4).
954 * @param uGuestCrX The current guest CR0 or guest CR4.
955 */
956IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
957{
958 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
959 Assert(iCrReg == 0 || iCrReg == 4);
960
961 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
962 Assert(pVmcs);
963
964 /*
965 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
966 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
967 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
968 *
969 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
970 */
971 uint64_t fGstHostMask;
972 uint64_t fReadShadow;
973 if (iCrReg == 0)
974 {
975 fGstHostMask = pVmcs->u64Cr0Mask.u;
976 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
977 }
978 else
979 {
980 fGstHostMask = pVmcs->u64Cr4Mask.u;
981 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
982 }
983
984 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
985 return fMaskedCrX;
986}
987
988
989/**
990 * Gets VM-exit instruction information along with any displacement for an
991 * instruction VM-exit.
992 *
993 * @returns The VM-exit instruction information.
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uExitReason The VM-exit reason.
996 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
997 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
998 * NULL.
999 */
1000IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
1001{
1002 RTGCPTR GCPtrDisp;
1003 VMXEXITINSTRINFO ExitInstrInfo;
1004 ExitInstrInfo.u = 0;
1005
1006 /*
1007 * Get and parse the ModR/M byte from our decoded opcodes.
1008 */
1009 uint8_t bRm;
1010 uint8_t const offModRm = pVCpu->iem.s.offModRm;
1011 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
1012 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1013 {
1014 /*
1015 * ModR/M indicates register addressing.
1016 *
1017 * The primary/secondary register operands are reported in the iReg1 or iReg2
1018 * fields depending on whether it is a read/write form.
1019 */
1020 uint8_t idxReg1;
1021 uint8_t idxReg2;
1022 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1023 {
1024 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1025 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1026 }
1027 else
1028 {
1029 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1030 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1031 }
1032 ExitInstrInfo.All.u2Scaling = 0;
1033 ExitInstrInfo.All.iReg1 = idxReg1;
1034 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1035 ExitInstrInfo.All.fIsRegOperand = 1;
1036 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1037 ExitInstrInfo.All.iSegReg = 0;
1038 ExitInstrInfo.All.iIdxReg = 0;
1039 ExitInstrInfo.All.fIdxRegInvalid = 1;
1040 ExitInstrInfo.All.iBaseReg = 0;
1041 ExitInstrInfo.All.fBaseRegInvalid = 1;
1042 ExitInstrInfo.All.iReg2 = idxReg2;
1043
1044 /* Displacement not applicable for register addressing. */
1045 GCPtrDisp = 0;
1046 }
1047 else
1048 {
1049 /*
1050 * ModR/M indicates memory addressing.
1051 */
1052 uint8_t uScale = 0;
1053 bool fBaseRegValid = false;
1054 bool fIdxRegValid = false;
1055 uint8_t iBaseReg = 0;
1056 uint8_t iIdxReg = 0;
1057 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
1058 {
1059 /*
1060 * Parse the ModR/M, displacement for 16-bit addressing mode.
1061 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
1062 */
1063 uint16_t u16Disp = 0;
1064 uint8_t const offDisp = offModRm + sizeof(bRm);
1065 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
1066 {
1067 /* Displacement without any registers. */
1068 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
1069 }
1070 else
1071 {
1072 /* Register (index and base). */
1073 switch (bRm & X86_MODRM_RM_MASK)
1074 {
1075 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1076 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1077 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1078 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1079 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1080 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1081 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
1082 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
1083 }
1084
1085 /* Register + displacement. */
1086 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1087 {
1088 case 0: break;
1089 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
1090 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
1091 default:
1092 {
1093 /* Register addressing, handled at the beginning. */
1094 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1095 break;
1096 }
1097 }
1098 }
1099
1100 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
1101 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
1102 }
1103 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
1104 {
1105 /*
1106 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
1107 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
1108 */
1109 uint32_t u32Disp = 0;
1110 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
1111 {
1112 /* Displacement without any registers. */
1113 uint8_t const offDisp = offModRm + sizeof(bRm);
1114 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1115 }
1116 else
1117 {
1118 /* Register (and perhaps scale, index and base). */
1119 uint8_t offDisp = offModRm + sizeof(bRm);
1120 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1121 if (iBaseReg == 4)
1122 {
1123 /* An SIB byte follows the ModR/M byte, parse it. */
1124 uint8_t bSib;
1125 uint8_t const offSib = offModRm + sizeof(bRm);
1126 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1127
1128 /* A displacement may follow SIB, update its offset. */
1129 offDisp += sizeof(bSib);
1130
1131 /* Get the scale. */
1132 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1133
1134 /* Get the index register. */
1135 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
1136 fIdxRegValid = RT_BOOL(iIdxReg != 4);
1137
1138 /* Get the base register. */
1139 iBaseReg = bSib & X86_SIB_BASE_MASK;
1140 fBaseRegValid = true;
1141 if (iBaseReg == 5)
1142 {
1143 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1144 {
1145 /* Mod is 0 implies a 32-bit displacement with no base. */
1146 fBaseRegValid = false;
1147 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1148 }
1149 else
1150 {
1151 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
1152 iBaseReg = X86_GREG_xBP;
1153 }
1154 }
1155 }
1156
1157 /* Register + displacement. */
1158 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1159 {
1160 case 0: /* Handled above */ break;
1161 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
1162 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
1163 default:
1164 {
1165 /* Register addressing, handled at the beginning. */
1166 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1167 break;
1168 }
1169 }
1170 }
1171
1172 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
1173 }
1174 else
1175 {
1176 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
1177
1178 /*
1179 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
1180 * See Intel instruction spec. 2.2 "IA-32e Mode".
1181 */
1182 uint64_t u64Disp = 0;
1183 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
1184 if (fRipRelativeAddr)
1185 {
1186 /*
1187 * RIP-relative addressing mode.
1188 *
1189 * The displacement is 32-bit signed implying an offset range of +/-2G.
1190 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
1191 */
1192 uint8_t const offDisp = offModRm + sizeof(bRm);
1193 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1194 }
1195 else
1196 {
1197 uint8_t offDisp = offModRm + sizeof(bRm);
1198
1199 /*
1200 * Register (and perhaps scale, index and base).
1201 *
1202 * REX.B extends the most-significant bit of the base register. However, REX.B
1203 * is ignored while determining whether an SIB follows the opcode. Hence, we
1204 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
1205 *
1206 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
1207 */
1208 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1209 if (iBaseReg == 4)
1210 {
1211 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
1212 uint8_t bSib;
1213 uint8_t const offSib = offModRm + sizeof(bRm);
1214 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1215
1216 /* Displacement may follow SIB, update its offset. */
1217 offDisp += sizeof(bSib);
1218
1219 /* Get the scale. */
1220 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1221
1222 /* Get the index. */
1223 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
1224 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
1225
1226 /* Get the base. */
1227 iBaseReg = (bSib & X86_SIB_BASE_MASK);
1228 fBaseRegValid = true;
1229 if (iBaseReg == 5)
1230 {
1231 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1232 {
1233 /* Mod is 0 implies a signed 32-bit displacement with no base. */
1234 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1235 }
1236 else
1237 {
1238 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
1239 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
1240 }
1241 }
1242 }
1243 iBaseReg |= pVCpu->iem.s.uRexB;
1244
1245 /* Register + displacement. */
1246 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1247 {
1248 case 0: /* Handled above */ break;
1249 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
1250 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
1251 default:
1252 {
1253 /* Register addressing, handled at the beginning. */
1254 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1255 break;
1256 }
1257 }
1258 }
1259
1260 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
1261 }
1262
1263 /*
1264 * The primary or secondary register operand is reported in iReg2 depending
1265 * on whether the primary operand is in read/write form.
1266 */
1267 uint8_t idxReg2;
1268 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1269 {
1270 idxReg2 = bRm & X86_MODRM_RM_MASK;
1271 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1272 idxReg2 |= pVCpu->iem.s.uRexB;
1273 }
1274 else
1275 {
1276 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
1277 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1278 idxReg2 |= pVCpu->iem.s.uRexReg;
1279 }
1280 ExitInstrInfo.All.u2Scaling = uScale;
1281 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
1282 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1283 ExitInstrInfo.All.fIsRegOperand = 0;
1284 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1285 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
1286 ExitInstrInfo.All.iIdxReg = iIdxReg;
1287 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
1288 ExitInstrInfo.All.iBaseReg = iBaseReg;
1289 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
1290 ExitInstrInfo.All.iReg2 = idxReg2;
1291 }
1292
1293 /*
1294 * Handle exceptions to the norm for certain instructions.
1295 * (e.g. some instructions convey an instruction identity in place of iReg2).
1296 */
1297 switch (uExitReason)
1298 {
1299 case VMX_EXIT_GDTR_IDTR_ACCESS:
1300 {
1301 Assert(VMXINSTRID_IS_VALID(uInstrId));
1302 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1303 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1304 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
1305 break;
1306 }
1307
1308 case VMX_EXIT_LDTR_TR_ACCESS:
1309 {
1310 Assert(VMXINSTRID_IS_VALID(uInstrId));
1311 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1312 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1313 ExitInstrInfo.LdtTr.u2Undef0 = 0;
1314 break;
1315 }
1316
1317 case VMX_EXIT_RDRAND:
1318 case VMX_EXIT_RDSEED:
1319 {
1320 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
1321 break;
1322 }
1323 }
1324
1325 /* Update displacement and return the constructed VM-exit instruction information field. */
1326 if (pGCPtrDisp)
1327 *pGCPtrDisp = GCPtrDisp;
1328
1329 return ExitInstrInfo.u;
1330}
1331
1332
1333/**
1334 * Converts an IEM exception event type to a VMX event type.
1335 *
1336 * @returns The VMX event type.
1337 * @param uVector The interrupt / exception vector.
1338 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
1339 */
1340DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
1341{
1342 /* Paranoia (callers may use these interchangeably). */
1343 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
1344 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
1345 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
1346 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
1347 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
1348 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
1349 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
1350 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
1351 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
1352 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
1353 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
1354 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
1355
1356 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
1357 {
1358 if (uVector == X86_XCPT_NMI)
1359 return VMX_EXIT_INT_INFO_TYPE_NMI;
1360 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
1361 }
1362
1363 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
1364 {
1365 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
1366 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
1367 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
1368 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
1369 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
1370 }
1371
1372 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
1373 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
1374}
1375
1376
1377/**
1378 * Sets the VM-instruction error VMCS field.
1379 *
1380 * @param pVCpu The cross context virtual CPU structure.
1381 * @param enmInsErr The VM-instruction error.
1382 */
1383DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1384{
1385 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1386 pVmcs->u32RoVmInstrError = enmInsErr;
1387}
1388
1389
1390/**
1391 * Sets the VM-exit qualification VMCS field.
1392 *
1393 * @param pVCpu The cross context virtual CPU structure.
1394 * @param uExitQual The VM-exit qualification.
1395 */
1396DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
1397{
1398 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1399 pVmcs->u64RoExitQual.u = uExitQual;
1400}
1401
1402
1403/**
1404 * Sets the VM-exit interruption information field.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param uExitQual The VM-exit interruption information.
1408 */
1409DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1410{
1411 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1412 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1413}
1414
1415
1416/**
1417 * Sets the VM-exit interruption error code.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uErrCode The error code.
1421 */
1422DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1423{
1424 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1425 pVmcs->u32RoExitIntErrCode = uErrCode;
1426}
1427
1428
1429/**
1430 * Sets the IDT-vectoring information field.
1431 *
1432 * @param pVCpu The cross context virtual CPU structure.
1433 * @param uIdtVectorInfo The IDT-vectoring information.
1434 */
1435DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1436{
1437 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1438 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1439}
1440
1441
1442/**
1443 * Sets the IDT-vectoring error code field.
1444 *
1445 * @param pVCpu The cross context virtual CPU structure.
1446 * @param uErrCode The error code.
1447 */
1448DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1449{
1450 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1451 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1452}
1453
1454
1455/**
1456 * Sets the VM-exit guest-linear address VMCS field.
1457 *
1458 * @param pVCpu The cross context virtual CPU structure.
1459 * @param uGuestLinearAddr The VM-exit guest-linear address.
1460 */
1461DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1462{
1463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1464 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1465}
1466
1467
1468/**
1469 * Sets the VM-exit guest-physical address VMCS field.
1470 *
1471 * @param pVCpu The cross context virtual CPU structure.
1472 * @param uGuestPhysAddr The VM-exit guest-physical address.
1473 */
1474DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1475{
1476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1477 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1478}
1479
1480
1481/**
1482 * Sets the VM-exit instruction length VMCS field.
1483 *
1484 * @param pVCpu The cross context virtual CPU structure.
1485 * @param cbInstr The VM-exit instruction length in bytes.
1486 *
1487 * @remarks Callers may clear this field to 0. Hence, this function does not check
1488 * the validity of the instruction length.
1489 */
1490DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1491{
1492 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1493 pVmcs->u32RoExitInstrLen = cbInstr;
1494}
1495
1496
1497/**
1498 * Sets the VM-exit instruction info. VMCS field.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 * @param uExitInstrInfo The VM-exit instruction information.
1502 */
1503DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1504{
1505 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1506 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1507}
1508
1509
1510/**
1511 * Implements VMSucceed for VMX instruction success.
1512 *
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1516{
1517 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1518}
1519
1520
1521/**
1522 * Implements VMFailInvalid for VMX instruction failure.
1523 *
1524 * @param pVCpu The cross context virtual CPU structure.
1525 */
1526DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1527{
1528 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1529 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1530}
1531
1532
1533/**
1534 * Implements VMFailValid for VMX instruction failure.
1535 *
1536 * @param pVCpu The cross context virtual CPU structure.
1537 * @param enmInsErr The VM instruction error.
1538 */
1539DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1540{
1541 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1542 {
1543 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1544 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1545 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1546 }
1547}
1548
1549
1550/**
1551 * Implements VMFail for VMX instruction failure.
1552 *
1553 * @param pVCpu The cross context virtual CPU structure.
1554 * @param enmInsErr The VM instruction error.
1555 */
1556DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1557{
1558 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1559 iemVmxVmFailValid(pVCpu, enmInsErr);
1560 else
1561 iemVmxVmFailInvalid(pVCpu);
1562}
1563
1564
1565/**
1566 * Checks if the given auto-load/store MSR area count is valid for the
1567 * implementation.
1568 *
1569 * @returns @c true if it's within the valid limit, @c false otherwise.
1570 * @param pVCpu The cross context virtual CPU structure.
1571 * @param uMsrCount The MSR area count to check.
1572 */
1573DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1574{
1575 uint64_t const u64VmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
1576 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1577 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1578 if (uMsrCount <= cMaxSupportedMsrs)
1579 return true;
1580 return false;
1581}
1582
1583
1584/**
1585 * Flushes the current VMCS contents back to guest memory.
1586 *
1587 * @returns VBox status code.
1588 * @param pVCpu The cross context virtual CPU structure.
1589 */
1590DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1591{
1592 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1593 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1594 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1595 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1596 return rc;
1597}
1598
1599
1600/**
1601 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1602 *
1603 * @param pVCpu The cross context virtual CPU structure.
1604 */
1605DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1606{
1607 iemVmxVmSucceed(pVCpu);
1608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1609}
1610
1611
1612/**
1613 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1614 * nested-guest.
1615 *
1616 * @param iSegReg The segment index (X86_SREG_XXX).
1617 */
1618IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1619{
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1623 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1624 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1625 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1626 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1627 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1628 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1629 }
1630}
1631
1632
1633/**
1634 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1635 * nested-guest that is in Virtual-8086 mode.
1636 *
1637 * @param iSegReg The segment index (X86_SREG_XXX).
1638 */
1639IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1640{
1641 switch (iSegReg)
1642 {
1643 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1644 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1645 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1646 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1647 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1648 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1649 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1650 }
1651}
1652
1653
1654/**
1655 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1656 * nested-guest that is in Virtual-8086 mode.
1657 *
1658 * @param iSegReg The segment index (X86_SREG_XXX).
1659 */
1660IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1661{
1662 switch (iSegReg)
1663 {
1664 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1665 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1666 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1667 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1668 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1669 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1670 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1671 }
1672}
1673
1674
1675/**
1676 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1677 * nested-guest that is in Virtual-8086 mode.
1678 *
1679 * @param iSegReg The segment index (X86_SREG_XXX).
1680 */
1681IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1682{
1683 switch (iSegReg)
1684 {
1685 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1686 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1687 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1688 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1689 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1690 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1691 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1692 }
1693}
1694
1695
1696/**
1697 * Gets the instruction diagnostic for segment attributes reserved bits failure
1698 * during VM-entry of a nested-guest.
1699 *
1700 * @param iSegReg The segment index (X86_SREG_XXX).
1701 */
1702IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1703{
1704 switch (iSegReg)
1705 {
1706 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1707 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1708 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1709 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1710 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1711 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1712 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1713 }
1714}
1715
1716
1717/**
1718 * Gets the instruction diagnostic for segment attributes descriptor-type
1719 * (code/segment or system) failure during VM-entry of a nested-guest.
1720 *
1721 * @param iSegReg The segment index (X86_SREG_XXX).
1722 */
1723IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1724{
1725 switch (iSegReg)
1726 {
1727 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1728 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1729 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1730 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1731 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1732 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1733 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1734 }
1735}
1736
1737
1738/**
1739 * Gets the instruction diagnostic for segment attributes descriptor-type
1740 * (code/segment or system) failure during VM-entry of a nested-guest.
1741 *
1742 * @param iSegReg The segment index (X86_SREG_XXX).
1743 */
1744IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1745{
1746 switch (iSegReg)
1747 {
1748 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1749 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1750 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1751 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1752 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1753 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1754 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1755 }
1756}
1757
1758
1759/**
1760 * Gets the instruction diagnostic for segment attribute granularity failure during
1761 * VM-entry of a nested-guest.
1762 *
1763 * @param iSegReg The segment index (X86_SREG_XXX).
1764 */
1765IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1766{
1767 switch (iSegReg)
1768 {
1769 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1770 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1771 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1772 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1773 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1774 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1775 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1776 }
1777}
1778
1779/**
1780 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1781 * VM-entry of a nested-guest.
1782 *
1783 * @param iSegReg The segment index (X86_SREG_XXX).
1784 */
1785IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1786{
1787 switch (iSegReg)
1788 {
1789 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1790 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1791 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1792 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1793 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1794 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1795 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1796 }
1797}
1798
1799
1800/**
1801 * Gets the instruction diagnostic for segment attribute type accessed failure
1802 * during VM-entry of a nested-guest.
1803 *
1804 * @param iSegReg The segment index (X86_SREG_XXX).
1805 */
1806IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1807{
1808 switch (iSegReg)
1809 {
1810 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1811 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1812 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1813 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1814 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1815 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1816 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1817 }
1818}
1819
1820
1821/**
1822 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1823 * failure during VM-entry of a nested-guest.
1824 *
1825 * @param iSegReg The PDPTE entry index.
1826 */
1827IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1828{
1829 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1830 switch (iPdpte)
1831 {
1832 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1833 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1834 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1835 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1836 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1837 }
1838}
1839
1840
1841/**
1842 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1843 * failure during VM-exit of a nested-guest.
1844 *
1845 * @param iSegReg The PDPTE entry index.
1846 */
1847IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1848{
1849 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1850 switch (iPdpte)
1851 {
1852 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1853 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1854 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1855 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1856 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1857 }
1858}
1859
1860
1861/**
1862 * Saves the guest control registers, debug registers and some MSRs are part of
1863 * VM-exit.
1864 *
1865 * @param pVCpu The cross context virtual CPU structure.
1866 */
1867IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1868{
1869 /*
1870 * Saves the guest control registers, debug registers and some MSRs.
1871 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1872 */
1873 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1874
1875 /* Save control registers. */
1876 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1877 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1878 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1879
1880 /* Save SYSENTER CS, ESP, EIP. */
1881 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1882 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1883 {
1884 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1885 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1886 }
1887 else
1888 {
1889 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1890 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1891 }
1892
1893 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1894 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1895 {
1896 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1897 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1898 }
1899
1900 /* Save PAT MSR. */
1901 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1902 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1903
1904 /* Save EFER MSR. */
1905 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1906 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1907
1908 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1909 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1910
1911 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1912}
1913
1914
1915/**
1916 * Saves the guest force-flags in preparation of entering the nested-guest.
1917 *
1918 * @param pVCpu The cross context virtual CPU structure.
1919 */
1920IEM_STATIC void iemVmxVmentrySaveForceFlags(PVMCPU pVCpu)
1921{
1922 /* We shouldn't be called multiple times during VM-entry. */
1923 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1924
1925 /* MTF should not be set outside VMX non-root mode. */
1926 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_MTF));
1927
1928 /*
1929 * Preserve the required force-flags.
1930 *
1931 * We cache and clear force-flags that would affect the execution of the
1932 * nested-guest. Cached flags are then restored while returning to the guest
1933 * if necessary.
1934 *
1935 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1936 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1937 * instruction. Interrupt inhibition for any nested-guest instruction
1938 * will be set later while loading the guest-interruptibility state.
1939 *
1940 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1941 * successful VM-entry needs to continue blocking NMIs if it was in effect
1942 * during VM-entry.
1943 *
1944 * - MTF need not be preserved as it's used only in VMX non-root mode and
1945 * is supplied on VM-entry through the VM-execution controls.
1946 *
1947 * The remaining FFs (e.g. timers, APIC updates) must stay in place so that
1948 * we will be able to generate interrupts that may cause VM-exits for
1949 * the nested-guest.
1950 */
1951 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1952
1953 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS))
1954 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS);
1955}
1956
1957
1958/**
1959 * Restores the guest force-flags in preparation of exiting the nested-guest.
1960 *
1961 * @param pVCpu The cross context virtual CPU structure.
1962 */
1963IEM_STATIC void iemVmxVmexitRestoreForceFlags(PVMCPU pVCpu)
1964{
1965 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1966 {
1967 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1968 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1969 }
1970}
1971
1972
1973/**
1974 * Perform a VMX transition updated PGM, IEM and CPUM.
1975 *
1976 * @param pVCpu The cross context virtual CPU structure.
1977 */
1978IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1979{
1980 /*
1981 * Inform PGM about paging mode changes.
1982 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1983 * see comment in iemMemPageTranslateAndCheckAccess().
1984 */
1985 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1986# ifdef IN_RING3
1987 Assert(rc != VINF_PGM_CHANGE_MODE);
1988# endif
1989 AssertRCReturn(rc, rc);
1990
1991 /* Inform CPUM (recompiler), can later be removed. */
1992 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1993
1994 /*
1995 * Flush the TLB with new CR3. This is required in case the PGM mode change
1996 * above doesn't actually change anything.
1997 */
1998 if (rc == VINF_SUCCESS)
1999 {
2000 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
2001 AssertRCReturn(rc, rc);
2002 }
2003
2004 /* Re-initialize IEM cache/state after the drastic mode switch. */
2005 iemReInitExec(pVCpu);
2006 return rc;
2007}
2008
2009
2010/**
2011 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
2012 *
2013 * @param pVCpu The cross context virtual CPU structure.
2014 */
2015IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
2016{
2017 /*
2018 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
2019 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
2020 */
2021 /* CS, SS, ES, DS, FS, GS. */
2022 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2023 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2024 {
2025 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2026 if (!pSelReg->Attr.n.u1Unusable)
2027 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
2028 else
2029 {
2030 /*
2031 * For unusable segments the attributes are undefined except for CS and SS.
2032 * For the rest we don't bother preserving anything but the unusable bit.
2033 */
2034 switch (iSegReg)
2035 {
2036 case X86_SREG_CS:
2037 pVmcs->GuestCs = pSelReg->Sel;
2038 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
2039 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
2040 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
2041 | X86DESCATTR_UNUSABLE);
2042 break;
2043
2044 case X86_SREG_SS:
2045 pVmcs->GuestSs = pSelReg->Sel;
2046 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2047 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
2048 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
2049 break;
2050
2051 case X86_SREG_DS:
2052 pVmcs->GuestDs = pSelReg->Sel;
2053 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2054 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
2055 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
2056 break;
2057
2058 case X86_SREG_ES:
2059 pVmcs->GuestEs = pSelReg->Sel;
2060 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2061 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
2062 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
2063 break;
2064
2065 case X86_SREG_FS:
2066 pVmcs->GuestFs = pSelReg->Sel;
2067 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
2068 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
2069 break;
2070
2071 case X86_SREG_GS:
2072 pVmcs->GuestGs = pSelReg->Sel;
2073 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
2074 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
2075 break;
2076 }
2077 }
2078 }
2079
2080 /* Segment attribute bits 31:7 and 11:8 MBZ. */
2081 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
2082 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
2083 /* LDTR. */
2084 {
2085 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
2086 pVmcs->GuestLdtr = pSelReg->Sel;
2087 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
2088 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
2089 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
2090 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
2091 }
2092
2093 /* TR. */
2094 {
2095 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
2096 pVmcs->GuestTr = pSelReg->Sel;
2097 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
2098 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
2099 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
2100 }
2101
2102 /* GDTR. */
2103 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
2104 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
2105
2106 /* IDTR. */
2107 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
2108 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
2109}
2110
2111
2112/**
2113 * Saves guest non-register state as part of VM-exit.
2114 *
2115 * @param pVCpu The cross context virtual CPU structure.
2116 * @param uExitReason The VM-exit reason.
2117 */
2118IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
2119{
2120 /*
2121 * Save guest non-register state.
2122 * See Intel spec. 27.3.4 "Saving Non-Register State".
2123 */
2124 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2125
2126 /* Activity-state: VM-exits occur before changing the activity state, nothing further to do */
2127
2128 /* Interruptibility-state. */
2129 pVmcs->u32GuestIntrState = 0;
2130 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
2131 { /** @todo NSTVMX: Virtual-NMI blocking. */ }
2132 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2133 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
2134
2135 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2136 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
2137 {
2138 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
2139 * currently. */
2140 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
2141 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2142 }
2143 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
2144
2145 /* Pending debug exceptions. */
2146 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
2147 && uExitReason != VMX_EXIT_SMI
2148 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
2149 && !HMVmxIsTrapLikeVmexit(uExitReason))
2150 {
2151 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
2152 * block-by-MovSS is in effect. */
2153 pVmcs->u64GuestPendingDbgXcpt.u = 0;
2154 }
2155
2156 /* Save VMX-preemption timer value. */
2157 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
2158 {
2159 uint32_t uPreemptTimer;
2160 if (uExitReason == VMX_EXIT_PREEMPT_TIMER)
2161 uPreemptTimer = 0;
2162 else
2163 {
2164 /*
2165 * Assume the following:
2166 * PreemptTimerShift = 5
2167 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
2168 * VmentryTick = 50000 (TSC at time of VM-entry)
2169 *
2170 * CurTick Delta PreemptTimerVal
2171 * ----------------------------------
2172 * 60000 10000 2
2173 * 80000 30000 1
2174 * 90000 40000 0 -> VM-exit.
2175 *
2176 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
2177 *
2178 * The saved VMX-preemption timer value is calculated as follows:
2179 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
2180 * E.g.:
2181 * Delta = 10000
2182 * Tmp = 10000 / (2 * 10000) = 0.5
2183 * NewPt = 2 - 0.5 = 2
2184 * Delta = 30000
2185 * Tmp = 30000 / (2 * 10000) = 1.5
2186 * NewPt = 2 - 1.5 = 1
2187 * Delta = 40000
2188 * Tmp = 40000 / 20000 = 2
2189 * NewPt = 2 - 2 = 0
2190 */
2191 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
2192 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
2193 uint64_t const uDelta = uCurTick - uVmentryTick;
2194 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
2195 uPreemptTimer = uVmcsPreemptVal - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
2196 }
2197
2198 pVmcs->u32PreemptTimer = uPreemptTimer;
2199 }
2200
2201
2202 /* PDPTEs. */
2203 /* We don't support EPT yet. */
2204 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
2205 pVmcs->u64GuestPdpte0.u = 0;
2206 pVmcs->u64GuestPdpte1.u = 0;
2207 pVmcs->u64GuestPdpte2.u = 0;
2208 pVmcs->u64GuestPdpte3.u = 0;
2209}
2210
2211
2212/**
2213 * Saves the guest-state as part of VM-exit.
2214 *
2215 * @returns VBox status code.
2216 * @param pVCpu The cross context virtual CPU structure.
2217 * @param uExitReason The VM-exit reason.
2218 */
2219IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
2220{
2221 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2222 Assert(pVmcs);
2223
2224 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
2225 iemVmxVmexitSaveGuestSegRegs(pVCpu);
2226
2227 /*
2228 * Save guest RIP, RSP and RFLAGS.
2229 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
2230 *
2231 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
2232 * Callers must pass the instruction length in the VM-exit instruction length
2233 * field though it is undefined for such VM-exits. After updating RIP here, we clear
2234 * the VM-exit instruction length field.
2235 *
2236 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
2237 */
2238 if (HMVmxIsTrapLikeVmexit(uExitReason))
2239 {
2240 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
2241 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
2242 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2243 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
2244 }
2245
2246 /* We don't support enclave mode yet. */
2247 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
2248 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
2249 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
2250
2251 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
2252}
2253
2254
2255/**
2256 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
2257 *
2258 * @returns VBox status code.
2259 * @param pVCpu The cross context virtual CPU structure.
2260 * @param uExitReason The VM-exit reason (for diagnostic purposes).
2261 */
2262IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2263{
2264 /*
2265 * Save guest MSRs.
2266 * See Intel spec. 27.4 "Saving MSRs".
2267 */
2268 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2269 const char *const pszFailure = "VMX-abort";
2270
2271 /*
2272 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
2273 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
2274 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2275 */
2276 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
2277 if (!cMsrs)
2278 return VINF_SUCCESS;
2279
2280 /*
2281 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
2282 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2283 * implementation causes a VMX-abort followed by a triple-fault.
2284 */
2285 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2286 if (fIsMsrCountValid)
2287 { /* likely */ }
2288 else
2289 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
2290
2291 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2292 Assert(pMsr);
2293 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2294 {
2295 if ( !pMsr->u32Reserved
2296 && pMsr->u32Msr != MSR_IA32_SMBASE
2297 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2298 {
2299 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
2300 if (rcStrict == VINF_SUCCESS)
2301 continue;
2302
2303 /*
2304 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2305 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2306 * recording the MSR index in the auxiliary info. field and indicated further by our
2307 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2308 * if possible, or come up with a better, generic solution.
2309 */
2310 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2311 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2312 ? kVmxVDiag_Vmexit_MsrStoreRing3
2313 : kVmxVDiag_Vmexit_MsrStore;
2314 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2315 }
2316 else
2317 {
2318 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2319 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2320 }
2321 }
2322
2323 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2324 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2325 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), VMX_V_AUTOMSR_AREA_SIZE);
2326 if (RT_SUCCESS(rc))
2327 { /* likely */ }
2328 else
2329 {
2330 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2331 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2332 }
2333
2334 NOREF(uExitReason);
2335 NOREF(pszFailure);
2336 return VINF_SUCCESS;
2337}
2338
2339
2340/**
2341 * Performs a VMX abort (due to an fatal error during VM-exit).
2342 *
2343 * @returns Strict VBox status code.
2344 * @param pVCpu The cross context virtual CPU structure.
2345 * @param enmAbort The VMX abort reason.
2346 */
2347IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2348{
2349 /*
2350 * Perform the VMX abort.
2351 * See Intel spec. 27.7 "VMX Aborts".
2352 */
2353 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2354
2355 /* We don't support SMX yet. */
2356 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2357 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2358 {
2359 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2360 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, u32VmxAbortId);
2361 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2362 }
2363
2364 return VINF_EM_TRIPLE_FAULT;
2365}
2366
2367
2368/**
2369 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2370 *
2371 * @param pVCpu The cross context virtual CPU structure.
2372 */
2373IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2374{
2375 /*
2376 * Load host control registers, debug registers and MSRs.
2377 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2378 */
2379 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2380 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2381
2382 /* CR0. */
2383 {
2384 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2385 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
2386 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2387 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2388 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2389 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2390 CPUMSetGuestCR0(pVCpu, uValidCr0);
2391 }
2392
2393 /* CR4. */
2394 {
2395 /* CR4 MB1 bits are not modified. */
2396 uint64_t const fCr4IgnMask = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
2397 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2398 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2399 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2400 if (fHostInLongMode)
2401 uValidCr4 |= X86_CR4_PAE;
2402 else
2403 uValidCr4 &= ~X86_CR4_PCIDE;
2404 CPUMSetGuestCR4(pVCpu, uValidCr4);
2405 }
2406
2407 /* CR3 (host value validated while checking host-state during VM-entry). */
2408 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2409
2410 /* DR7. */
2411 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2412
2413 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2414
2415 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2416 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2417 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2418 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2419
2420 /* FS, GS bases are loaded later while we load host segment registers. */
2421
2422 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2423 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2424 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2425 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2426 {
2427 if (fHostInLongMode)
2428 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2429 else
2430 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2431 }
2432
2433 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2434
2435 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2436 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2437 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2438
2439 /* We don't support IA32_BNDCFGS MSR yet. */
2440}
2441
2442
2443/**
2444 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2445 *
2446 * @param pVCpu The cross context virtual CPU structure.
2447 */
2448IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2449{
2450 /*
2451 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2452 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2453 *
2454 * Warning! Be careful to not touch fields that are reserved by VT-x,
2455 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2456 */
2457 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2458 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2459
2460 /* CS, SS, ES, DS, FS, GS. */
2461 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2462 {
2463 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2464 bool const fUnusable = RT_BOOL(HostSel == 0);
2465
2466 /* Selector. */
2467 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel = HostSel;
2468 pVCpu->cpum.GstCtx.aSRegs[iSegReg].ValidSel = HostSel;
2469 pVCpu->cpum.GstCtx.aSRegs[iSegReg].fFlags = CPUMSELREG_FLAGS_VALID;
2470
2471 /* Limit. */
2472 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u32Limit = 0xffffffff;
2473
2474 /* Base and Attributes. */
2475 switch (iSegReg)
2476 {
2477 case X86_SREG_CS:
2478 {
2479 pVCpu->cpum.GstCtx.cs.u64Base = 0;
2480 pVCpu->cpum.GstCtx.cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2481 pVCpu->cpum.GstCtx.ss.Attr.n.u1DescType = 1;
2482 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = 0;
2483 pVCpu->cpum.GstCtx.cs.Attr.n.u1Present = 1;
2484 pVCpu->cpum.GstCtx.cs.Attr.n.u1Long = fHostInLongMode;
2485 pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig = !fHostInLongMode;
2486 pVCpu->cpum.GstCtx.cs.Attr.n.u1Granularity = 1;
2487 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Unusable);
2488 Assert(!fUnusable);
2489 break;
2490 }
2491
2492 case X86_SREG_SS:
2493 case X86_SREG_ES:
2494 case X86_SREG_DS:
2495 {
2496 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base = 0;
2497 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2498 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DescType = 1;
2499 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u2Dpl = 0;
2500 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Present = 1;
2501 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DefBig = 1;
2502 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Granularity = 1;
2503 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable = fUnusable;
2504 break;
2505 }
2506
2507 case X86_SREG_FS:
2508 {
2509 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2510 pVCpu->cpum.GstCtx.fs.u64Base = !fUnusable ? pVmcs->u64HostFsBase.u : 0;
2511 pVCpu->cpum.GstCtx.fs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2512 pVCpu->cpum.GstCtx.fs.Attr.n.u1DescType = 1;
2513 pVCpu->cpum.GstCtx.fs.Attr.n.u2Dpl = 0;
2514 pVCpu->cpum.GstCtx.fs.Attr.n.u1Present = 1;
2515 pVCpu->cpum.GstCtx.fs.Attr.n.u1DefBig = 1;
2516 pVCpu->cpum.GstCtx.fs.Attr.n.u1Granularity = 1;
2517 pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable = fUnusable;
2518 break;
2519 }
2520
2521 case X86_SREG_GS:
2522 {
2523 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2524 pVCpu->cpum.GstCtx.gs.u64Base = !fUnusable ? pVmcs->u64HostGsBase.u : 0;
2525 pVCpu->cpum.GstCtx.gs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2526 pVCpu->cpum.GstCtx.gs.Attr.n.u1DescType = 1;
2527 pVCpu->cpum.GstCtx.gs.Attr.n.u2Dpl = 0;
2528 pVCpu->cpum.GstCtx.gs.Attr.n.u1Present = 1;
2529 pVCpu->cpum.GstCtx.gs.Attr.n.u1DefBig = 1;
2530 pVCpu->cpum.GstCtx.gs.Attr.n.u1Granularity = 1;
2531 pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable = fUnusable;
2532 break;
2533 }
2534 }
2535 }
2536
2537 /* TR. */
2538 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2539 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2540 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2541 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2542 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2543 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2544 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2545 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2546 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2547 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2548 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2549 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2550 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2551
2552 /* LDTR. */
2553 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2554 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2555 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2556 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
2557 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
2558 pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Unusable = 1;
2559
2560 /* GDTR. */
2561 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2562 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2563 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xfff;
2564
2565 /* IDTR.*/
2566 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2567 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2568 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xfff;
2569}
2570
2571
2572/**
2573 * Checks host PDPTes as part of VM-exit.
2574 *
2575 * @param pVCpu The cross context virtual CPU structure.
2576 * @param uExitReason The VM-exit reason (for logging purposes).
2577 */
2578IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2579{
2580 /*
2581 * Check host PDPTEs.
2582 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2583 */
2584 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2585 const char *const pszFailure = "VMX-abort";
2586 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2587
2588 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2589 && !fHostInLongMode)
2590 {
2591 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2592 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2593 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2594 if (RT_SUCCESS(rc))
2595 {
2596 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2597 {
2598 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2599 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2600 { /* likely */ }
2601 else
2602 {
2603 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2604 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2605 }
2606 }
2607 }
2608 else
2609 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2610 }
2611
2612 NOREF(pszFailure);
2613 NOREF(uExitReason);
2614 return VINF_SUCCESS;
2615}
2616
2617
2618/**
2619 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2620 *
2621 * @returns VBox status code.
2622 * @param pVCpu The cross context virtual CPU structure.
2623 * @param pszInstr The VMX instruction name (for logging purposes).
2624 */
2625IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2626{
2627 /*
2628 * Load host MSRs.
2629 * See Intel spec. 27.6 "Loading MSRs".
2630 */
2631 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2632 const char *const pszFailure = "VMX-abort";
2633
2634 /*
2635 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2636 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2637 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2638 */
2639 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2640 if (!cMsrs)
2641 return VINF_SUCCESS;
2642
2643 /*
2644 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2645 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2646 * implementation causes a VMX-abort followed by a triple-fault.
2647 */
2648 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2649 if (fIsMsrCountValid)
2650 { /* likely */ }
2651 else
2652 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2653
2654 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2655 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2656 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
2657 if (RT_SUCCESS(rc))
2658 {
2659 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2660 Assert(pMsr);
2661 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2662 {
2663 if ( !pMsr->u32Reserved
2664 && pMsr->u32Msr != MSR_K8_FS_BASE
2665 && pMsr->u32Msr != MSR_K8_GS_BASE
2666 && pMsr->u32Msr != MSR_K6_EFER
2667 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2668 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2669 {
2670 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2671 if (rcStrict == VINF_SUCCESS)
2672 continue;
2673
2674 /*
2675 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2676 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2677 * recording the MSR index in the auxiliary info. field and indicated further by our
2678 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2679 * if possible, or come up with a better, generic solution.
2680 */
2681 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2682 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2683 ? kVmxVDiag_Vmexit_MsrLoadRing3
2684 : kVmxVDiag_Vmexit_MsrLoad;
2685 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2686 }
2687 else
2688 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2689 }
2690 }
2691 else
2692 {
2693 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2694 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2695 }
2696
2697 NOREF(uExitReason);
2698 NOREF(pszFailure);
2699 return VINF_SUCCESS;
2700}
2701
2702
2703/**
2704 * Loads the host state as part of VM-exit.
2705 *
2706 * @returns Strict VBox status code.
2707 * @param pVCpu The cross context virtual CPU structure.
2708 * @param uExitReason The VM-exit reason (for logging purposes).
2709 */
2710IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2711{
2712 /*
2713 * Load host state.
2714 * See Intel spec. 27.5 "Loading Host State".
2715 */
2716 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2717 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2718
2719 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2720 if ( CPUMIsGuestInLongMode(pVCpu)
2721 && !fHostInLongMode)
2722 {
2723 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2724 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2725 }
2726
2727 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2728 iemVmxVmexitLoadHostSegRegs(pVCpu);
2729
2730 /*
2731 * Load host RIP, RSP and RFLAGS.
2732 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2733 */
2734 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2735 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2736 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2737
2738 /* Update non-register state. */
2739 iemVmxVmexitRestoreForceFlags(pVCpu);
2740
2741 /* Clear address range monitoring. */
2742 EMMonitorWaitClear(pVCpu);
2743
2744 /* Perform the VMX transition (PGM updates). */
2745 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2746 if (rcStrict == VINF_SUCCESS)
2747 {
2748 /* Check host PDPTEs (only when we've fully switched page tables_. */
2749 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2750 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2751 if (RT_FAILURE(rc))
2752 {
2753 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2754 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2755 }
2756 }
2757 else if (RT_SUCCESS(rcStrict))
2758 {
2759 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2760 uExitReason));
2761 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2762 }
2763 else
2764 {
2765 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2766 return VBOXSTRICTRC_VAL(rcStrict);
2767 }
2768
2769 Assert(rcStrict == VINF_SUCCESS);
2770
2771 /* Load MSRs from the VM-exit auto-load MSR area. */
2772 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2773 if (RT_FAILURE(rc))
2774 {
2775 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2776 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2777 }
2778
2779 return rcStrict;
2780}
2781
2782
2783/**
2784 * VMX VM-exit handler.
2785 *
2786 * @returns Strict VBox status code.
2787 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2788 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2789 * triple-fault.
2790 *
2791 * @param pVCpu The cross context virtual CPU structure.
2792 * @param uExitReason The VM-exit reason.
2793 *
2794 * @remarks Make sure VM-exit qualification is updated before calling this
2795 * function!
2796 */
2797IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2798{
2799 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2800 Assert(pVmcs);
2801
2802 pVmcs->u32RoExitReason = uExitReason;
2803
2804 /** @todo NSTVMX: IEMGetCurrentXcpt will be VM-exit interruption info. */
2805 /** @todo NSTVMX: The source event should be recorded in IDT-vectoring info
2806 * during injection. */
2807
2808 /*
2809 * Save the guest state back into the VMCS.
2810 * We only need to save the state when the VM-entry was successful.
2811 */
2812 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2813 if (!fVmentryFailed)
2814 {
2815 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2816 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2817 if (RT_SUCCESS(rc))
2818 { /* likely */ }
2819 else
2820 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2821 }
2822
2823 /*
2824 * The high bits of the VM-exit reason are only relevant when the VM-exit occurs in
2825 * enclave mode/SMM which we don't support yet. If we ever add support for it, we can
2826 * pass just the lower bits, till then an assert should suffice.
2827 */
2828 Assert(!RT_HI_U16(uExitReason));
2829
2830 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2831 if (RT_FAILURE(rcStrict))
2832 LogFunc(("Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2833
2834 /* We're no longer in nested-guest execution mode. */
2835 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2836
2837 Assert(rcStrict == VINF_SUCCESS);
2838 return VINF_VMX_VMEXIT;
2839}
2840
2841
2842/**
2843 * VMX VM-exit handler for VM-exits due to instruction execution.
2844 *
2845 * This is intended for instructions where the caller provides all the relevant
2846 * VM-exit information.
2847 *
2848 * @returns Strict VBox status code.
2849 * @param pVCpu The cross context virtual CPU structure.
2850 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2851 */
2852DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2853{
2854 /*
2855 * For instructions where any of the following fields are not applicable:
2856 * - VM-exit instruction info. is undefined.
2857 * - VM-exit qualification must be cleared.
2858 * - VM-exit guest-linear address is undefined.
2859 * - VM-exit guest-physical address is undefined.
2860 *
2861 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2862 * instruction execution. For VM-exits that are not due to instruction execution this
2863 * field is undefined.
2864 *
2865 * In our implementation in IEM, all undefined fields are generally cleared. However,
2866 * if the caller supplies information (from say the physical CPU directly) it is
2867 * then possible that the undefined fields not cleared.
2868 *
2869 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2870 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2871 */
2872 Assert(pExitInfo);
2873 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2874 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2875 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2876
2877 /* Update all the relevant fields from the VM-exit instruction information struct. */
2878 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2879 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2880 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2881 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2882 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2883
2884 /* Perform the VM-exit. */
2885 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2886}
2887
2888
2889/**
2890 * VMX VM-exit handler for VM-exits due to instruction execution.
2891 *
2892 * This is intended for instructions that only provide the VM-exit instruction
2893 * length.
2894 *
2895 * @param pVCpu The cross context virtual CPU structure.
2896 * @param uExitReason The VM-exit reason.
2897 * @param cbInstr The instruction length in bytes.
2898 */
2899IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2900{
2901 VMXVEXITINFO ExitInfo;
2902 RT_ZERO(ExitInfo);
2903 ExitInfo.uReason = uExitReason;
2904 ExitInfo.cbInstr = cbInstr;
2905
2906#ifdef VBOX_STRICT
2907 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2908 switch (uExitReason)
2909 {
2910 case VMX_EXIT_INVEPT:
2911 case VMX_EXIT_INVPCID:
2912 case VMX_EXIT_LDTR_TR_ACCESS:
2913 case VMX_EXIT_GDTR_IDTR_ACCESS:
2914 case VMX_EXIT_VMCLEAR:
2915 case VMX_EXIT_VMPTRLD:
2916 case VMX_EXIT_VMPTRST:
2917 case VMX_EXIT_VMREAD:
2918 case VMX_EXIT_VMWRITE:
2919 case VMX_EXIT_VMXON:
2920 case VMX_EXIT_XRSTORS:
2921 case VMX_EXIT_XSAVES:
2922 case VMX_EXIT_RDRAND:
2923 case VMX_EXIT_RDSEED:
2924 case VMX_EXIT_IO_INSTR:
2925 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2926 break;
2927 }
2928#endif
2929
2930 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2931}
2932
2933
2934/**
2935 * VMX VM-exit handler for VM-exits due to instruction execution.
2936 *
2937 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2938 * instruction information and VM-exit qualification fields.
2939 *
2940 * @param pVCpu The cross context virtual CPU structure.
2941 * @param uExitReason The VM-exit reason.
2942 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2943 * @param cbInstr The instruction length in bytes.
2944 *
2945 * @remarks Do not use this for INS/OUTS instruction.
2946 */
2947IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2948{
2949 VMXVEXITINFO ExitInfo;
2950 RT_ZERO(ExitInfo);
2951 ExitInfo.uReason = uExitReason;
2952 ExitInfo.cbInstr = cbInstr;
2953
2954 /*
2955 * Update the VM-exit qualification field with displacement bytes.
2956 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2957 */
2958 switch (uExitReason)
2959 {
2960 case VMX_EXIT_INVEPT:
2961 case VMX_EXIT_INVPCID:
2962 case VMX_EXIT_LDTR_TR_ACCESS:
2963 case VMX_EXIT_GDTR_IDTR_ACCESS:
2964 case VMX_EXIT_VMCLEAR:
2965 case VMX_EXIT_VMPTRLD:
2966 case VMX_EXIT_VMPTRST:
2967 case VMX_EXIT_VMREAD:
2968 case VMX_EXIT_VMWRITE:
2969 case VMX_EXIT_VMXON:
2970 case VMX_EXIT_XRSTORS:
2971 case VMX_EXIT_XSAVES:
2972 case VMX_EXIT_RDRAND:
2973 case VMX_EXIT_RDSEED:
2974 {
2975 /* Construct the VM-exit instruction information. */
2976 RTGCPTR GCPtrDisp;
2977 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2978
2979 /* Update the VM-exit instruction information. */
2980 ExitInfo.InstrInfo.u = uInstrInfo;
2981
2982 /* Update the VM-exit qualification. */
2983 ExitInfo.u64Qual = GCPtrDisp;
2984 break;
2985 }
2986
2987 default:
2988 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2989 break;
2990 }
2991
2992 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2993}
2994
2995
2996/**
2997 * Checks whether an I/O instruction for the given port is intercepted (causes a
2998 * VM-exit) or not.
2999 *
3000 * @returns @c true if the instruction is intercepted, @c false otherwise.
3001 * @param pVCpu The cross context virtual CPU structure.
3002 * @param u16Port The I/O port being accessed by the instruction.
3003 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3004 */
3005IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3006{
3007 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3008 Assert(pVmcs);
3009
3010 /*
3011 * Check whether the I/O instruction must cause a VM-exit or not.
3012 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3013 */
3014 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3015 return true;
3016
3017 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3018 {
3019 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3020 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3021 Assert(pbIoBitmapA);
3022 Assert(pbIoBitmapB);
3023 return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3024 }
3025
3026 return false;
3027}
3028
3029
3030/**
3031 * VMX VM-exit handler for VM-exits due to INVLPG.
3032 *
3033 * @param pVCpu The cross context virtual CPU structure.
3034 * @param GCPtrPage The guest-linear address of the page being invalidated.
3035 * @param cbInstr The instruction length in bytes.
3036 */
3037IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3038{
3039 VMXVEXITINFO ExitInfo;
3040 RT_ZERO(ExitInfo);
3041 ExitInfo.uReason = VMX_EXIT_INVLPG;
3042 ExitInfo.cbInstr = cbInstr;
3043 ExitInfo.u64Qual = GCPtrPage;
3044 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3045
3046 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3047}
3048
3049
3050/**
3051 * VMX VM-exit handler for VM-exits due to LMSW.
3052 *
3053 * @returns Strict VBox status code.
3054 * @param pVCpu The cross context virtual CPU structure.
3055 * @param uGuestCr0 The current guest CR0.
3056 * @param pu16NewMsw The machine-status word specified in LMSW's source
3057 * operand. This will be updated depending on the VMX
3058 * guest/host CR0 mask if LMSW is not intercepted.
3059 * @param GCPtrEffDst The guest-linear address of the source operand in case
3060 * of a memory operand. For register operand, pass
3061 * NIL_RTGCPTR.
3062 * @param cbInstr The instruction length in bytes.
3063 */
3064IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3065 uint8_t cbInstr)
3066{
3067 /*
3068 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3069 *
3070 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3071 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3072 */
3073 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3074 Assert(pVmcs);
3075 Assert(pu16NewMsw);
3076
3077 bool fIntercept = false;
3078 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3079 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3080
3081 /*
3082 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3083 * CR0.PE case first, before the rest of the bits in the MSW.
3084 *
3085 * If CR0.PE is owned by the host and CR0.PE differs between the
3086 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3087 */
3088 if ( (fGstHostMask & X86_CR0_PE)
3089 && (*pu16NewMsw & X86_CR0_PE)
3090 && !(fReadShadow & X86_CR0_PE))
3091 fIntercept = true;
3092
3093 /*
3094 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3095 * bits differ between the MSW (source operand) and the read-shadow, we must
3096 * cause a VM-exit.
3097 */
3098 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3099 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3100 fIntercept = true;
3101
3102 if (fIntercept)
3103 {
3104 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3105
3106 VMXVEXITINFO ExitInfo;
3107 RT_ZERO(ExitInfo);
3108 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3109 ExitInfo.cbInstr = cbInstr;
3110
3111 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3112 if (fMemOperand)
3113 {
3114 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3115 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3116 }
3117
3118 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3119 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3120 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3121 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3122
3123 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3124 }
3125
3126 /*
3127 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3128 * CR0 guest/host mask must be left unmodified.
3129 *
3130 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3131 */
3132 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3133 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3134
3135 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3136}
3137
3138
3139/**
3140 * VMX VM-exit handler for VM-exits due to CLTS.
3141 *
3142 * @returns Strict VBox status code.
3143 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3144 * VM-exit but must not modify the guest CR0.TS bit.
3145 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3146 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3147 * CR0 fixed bits in VMX operation).
3148 * @param pVCpu The cross context virtual CPU structure.
3149 * @param cbInstr The instruction length in bytes.
3150 */
3151IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3152{
3153 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3154 Assert(pVmcs);
3155
3156 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3157 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3158
3159 /*
3160 * If CR0.TS is owned by the host:
3161 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3162 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3163 * CLTS instruction completes without clearing CR0.TS.
3164 *
3165 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3166 */
3167 if (fGstHostMask & X86_CR0_TS)
3168 {
3169 if (fReadShadow & X86_CR0_TS)
3170 {
3171 Log2(("clts: Guest intercept -> VM-exit\n"));
3172
3173 VMXVEXITINFO ExitInfo;
3174 RT_ZERO(ExitInfo);
3175 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3176 ExitInfo.cbInstr = cbInstr;
3177
3178 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3179 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3180 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3181 }
3182
3183 return VINF_VMX_MODIFIES_BEHAVIOR;
3184 }
3185
3186 /*
3187 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3188 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3189 */
3190 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3191}
3192
3193
3194/**
3195 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3196 * (CR0/CR4 write).
3197 *
3198 * @returns Strict VBox status code.
3199 * @param pVCpu The cross context virtual CPU structure.
3200 * @param iCrReg The control register (either CR0 or CR4).
3201 * @param uGuestCrX The current guest CR0/CR4.
3202 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3203 * if no VM-exit is caused.
3204 * @param iGReg The general register from which the CR0/CR4 value is
3205 * being loaded.
3206 * @param cbInstr The instruction length in bytes.
3207 */
3208IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3209 uint8_t cbInstr)
3210{
3211 Assert(puNewCrX);
3212 Assert(iCrReg == 0 || iCrReg == 4);
3213
3214 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3215 Assert(pVmcs);
3216
3217 uint64_t uGuestCrX;
3218 uint64_t fGstHostMask;
3219 uint64_t fReadShadow;
3220 if (iCrReg == 0)
3221 {
3222 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3223 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3224 fGstHostMask = pVmcs->u64Cr0Mask.u;
3225 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3226 }
3227 else
3228 {
3229 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3230 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3231 fGstHostMask = pVmcs->u64Cr4Mask.u;
3232 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3233 }
3234
3235 /*
3236 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3237 * corresponding bits differ between the source operand and the read-shadow,
3238 * we must cause a VM-exit.
3239 *
3240 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3241 */
3242 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3243 {
3244 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3245
3246 VMXVEXITINFO ExitInfo;
3247 RT_ZERO(ExitInfo);
3248 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3249 ExitInfo.cbInstr = cbInstr;
3250
3251 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3252 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3254 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3255 }
3256
3257 /*
3258 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3259 * must not be modified the instruction.
3260 *
3261 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3262 */
3263 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3264
3265 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3266}
3267
3268
3269/**
3270 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3271 *
3272 * @returns VBox strict status code.
3273 * @param pVCpu The cross context virtual CPU structure.
3274 * @param iGReg The general register to which the CR3 value is being stored.
3275 * @param cbInstr The instruction length in bytes.
3276 */
3277IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3278{
3279 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3280 Assert(pVmcs);
3281 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3282
3283 /*
3284 * If the CR3-store exiting control is set, we must cause a VM-exit.
3285 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3286 */
3287 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3288 {
3289 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3290
3291 VMXVEXITINFO ExitInfo;
3292 RT_ZERO(ExitInfo);
3293 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3294 ExitInfo.cbInstr = cbInstr;
3295
3296 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3297 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3298 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3299 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3300 }
3301
3302 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3303}
3304
3305
3306/**
3307 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3308 *
3309 * @returns VBox strict status code.
3310 * @param pVCpu The cross context virtual CPU structure.
3311 * @param uNewCr3 The new CR3 value.
3312 * @param iGReg The general register from which the CR3 value is being
3313 * loaded.
3314 * @param cbInstr The instruction length in bytes.
3315 */
3316IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3317{
3318 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3319 Assert(pVmcs);
3320
3321 /*
3322 * If the CR3-load exiting control is set and the new CR3 value does not
3323 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3324 *
3325 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3326 */
3327 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3328 {
3329 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3330 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3331
3332 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3333 {
3334 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3335 if (uNewCr3 != uCr3TargetValue)
3336 {
3337 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3338
3339 VMXVEXITINFO ExitInfo;
3340 RT_ZERO(ExitInfo);
3341 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3342 ExitInfo.cbInstr = cbInstr;
3343
3344 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3345 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3346 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3347 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3348 }
3349 }
3350 }
3351
3352 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3353}
3354
3355
3356/**
3357 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3358 *
3359 * @returns VBox strict status code.
3360 * @param pVCpu The cross context virtual CPU structure.
3361 * @param iGReg The general register to which the CR8 value is being stored.
3362 * @param cbInstr The instruction length in bytes.
3363 */
3364IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3365{
3366 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3367 Assert(pVmcs);
3368
3369 /*
3370 * If the CR8-store exiting control is set, we must cause a VM-exit.
3371 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3372 */
3373 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3374 {
3375 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3376
3377 VMXVEXITINFO ExitInfo;
3378 RT_ZERO(ExitInfo);
3379 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3380 ExitInfo.cbInstr = cbInstr;
3381
3382 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3383 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3384 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3385 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3386 }
3387
3388 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3389}
3390
3391
3392/**
3393 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3394 *
3395 * @returns VBox strict status code.
3396 * @param pVCpu The cross context virtual CPU structure.
3397 * @param iGReg The general register from which the CR8 value is being
3398 * loaded.
3399 * @param cbInstr The instruction length in bytes.
3400 */
3401IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3402{
3403 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3404 Assert(pVmcs);
3405
3406 /*
3407 * If the CR8-load exiting control is set, we must cause a VM-exit.
3408 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3409 */
3410 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3411 {
3412 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3413
3414 VMXVEXITINFO ExitInfo;
3415 RT_ZERO(ExitInfo);
3416 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3417 ExitInfo.cbInstr = cbInstr;
3418
3419 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3420 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3421 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3422 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3423 }
3424
3425 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3426}
3427
3428
3429/**
3430 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3431 * GReg,DRx' (DRx read).
3432 *
3433 * @returns VBox strict status code.
3434 * @param pVCpu The cross context virtual CPU structure.
3435 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3436 * VMXINSTRID_MOV_FROM_DRX).
3437 * @param iDrReg The debug register being accessed.
3438 * @param iGReg The general register to/from which the DRx value is being
3439 * store/loaded.
3440 * @param cbInstr The instruction length in bytes.
3441 */
3442IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3443 uint8_t cbInstr)
3444{
3445 Assert(iDrReg <= 7);
3446 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3447
3448 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3449 Assert(pVmcs);
3450
3451 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3452 {
3453 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3454 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3455 VMXVEXITINFO ExitInfo;
3456 RT_ZERO(ExitInfo);
3457 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3458 ExitInfo.cbInstr = cbInstr;
3459 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3460 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3461 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3462 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3463 }
3464
3465 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3466}
3467
3468
3469/**
3470 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3471 *
3472 * @returns VBox strict status code.
3473 * @param pVCpu The cross context virtual CPU structure.
3474 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3475 * VMXINSTRID_IO_OUT).
3476 * @param u16Port The I/O port being accessed.
3477 * @param fImm Whether the I/O port was encoded using an immediate operand
3478 * or the implicit DX register.
3479 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3480 * @param cbInstr The instruction length in bytes.
3481 */
3482IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3483 uint8_t cbInstr)
3484{
3485 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3486 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3487
3488 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3489 if (fIntercept)
3490 {
3491 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3492 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3493 VMXVEXITINFO ExitInfo;
3494 RT_ZERO(ExitInfo);
3495 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3496 ExitInfo.cbInstr = cbInstr;
3497 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3498 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3499 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3500 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3501 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3502 }
3503
3504 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3505}
3506
3507
3508/**
3509 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3510 *
3511 * @returns VBox strict status code.
3512 * @param pVCpu The cross context virtual CPU structure.
3513 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3514 * VMXINSTRID_IO_OUTS).
3515 * @param u16Port The I/O port being accessed.
3516 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3517 * @param fRep Whether the instruction has a REP prefix or not.
3518 * @param ExitInstrInfo The VM-exit instruction info. field.
3519 * @param cbInstr The instruction length in bytes.
3520 */
3521IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3522 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3523{
3524 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3525 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3526 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3527 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3528 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3529
3530 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3531 if (fIntercept)
3532 {
3533 /*
3534 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3535 */
3536 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3537 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3538 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3539 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3540 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3541
3542 uint32_t uDirection;
3543 uint64_t uGuestLinearAddr;
3544 if (uInstrId == VMXINSTRID_IO_INS)
3545 {
3546 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3547 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3548 }
3549 else
3550 {
3551 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3552 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3553 }
3554
3555 /*
3556 * If the segment is ununsable, the guest-linear address in undefined.
3557 * We shall clear it for consistency.
3558 *
3559 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3560 */
3561 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3562 uGuestLinearAddr = 0;
3563
3564 VMXVEXITINFO ExitInfo;
3565 RT_ZERO(ExitInfo);
3566 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3567 ExitInfo.cbInstr = cbInstr;
3568 ExitInfo.InstrInfo = ExitInstrInfo;
3569 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3570 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3571 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3572 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3573 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3574 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3575 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3576 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3577 }
3578
3579 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3580}
3581
3582
3583/**
3584 * VMX VM-exit handler for VM-exits due to MWAIT.
3585 *
3586 * @returns VBox strict status code.
3587 * @param pVCpu The cross context virtual CPU structure.
3588 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3589 * @param cbInstr The instruction length in bytes.
3590 */
3591IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3592{
3593 VMXVEXITINFO ExitInfo;
3594 RT_ZERO(ExitInfo);
3595 ExitInfo.uReason = VMX_EXIT_MWAIT;
3596 ExitInfo.cbInstr = cbInstr;
3597 ExitInfo.u64Qual = fMonitorHwArmed;
3598 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3599}
3600
3601
3602/**
3603 * VMX VM-exit handler for VM-exits due to PAUSE.
3604 *
3605 * @returns VBox strict status code.
3606 * @param pVCpu The cross context virtual CPU structure.
3607 * @param cbInstr The instruction length in bytes.
3608 */
3609IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3610{
3611 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3612 Assert(pVmcs);
3613
3614 /*
3615 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3616 * "PAUSE-loop exiting" control.
3617 *
3618 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3619 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3620 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3621 * a VM-exit.
3622 *
3623 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3624 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3625 */
3626 bool fIntercept = false;
3627 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3628 fIntercept = true;
3629 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3630 && pVCpu->iem.s.uCpl == 0)
3631 {
3632 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3633
3634 /*
3635 * A previous-PAUSE-tick value of 0 is used to identify the first time
3636 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3637 * consider this to be the first execution of PAUSE in a loop according
3638 * to the Intel.
3639 *
3640 * All subsequent records for the previous-PAUSE-tick we ensure that it
3641 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3642 */
3643 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3644 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3645 uint64_t const uTick = TMCpuTickGet(pVCpu);
3646 uint32_t const uPleGap = pVmcs->u32PleGap;
3647 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3648 if ( *puPrevPauseTick == 0
3649 || uTick - *puPrevPauseTick > uPleGap)
3650 *puFirstPauseLoopTick = uTick;
3651 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3652 fIntercept = true;
3653
3654 *puPrevPauseTick = uTick | 1;
3655 }
3656
3657 if (fIntercept)
3658 {
3659 VMXVEXITINFO ExitInfo;
3660 RT_ZERO(ExitInfo);
3661 ExitInfo.uReason = VMX_EXIT_PAUSE;
3662 ExitInfo.cbInstr = cbInstr;
3663 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3664 }
3665
3666 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3667}
3668
3669
3670/**
3671 * VMX VM-exit handler for VM-exits due to task switches.
3672 *
3673 * @returns VBox strict status code.
3674 * @param pVCpu The cross context virtual CPU structure.
3675 * @param enmTaskSwitch The cause of the task switch.
3676 * @param SelNewTss The selector of the new TSS.
3677 * @param cbInstr The instruction length in bytes.
3678 */
3679IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3680{
3681 /*
3682 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3683 *
3684 * If the the cause of the task switch is due to execution of CALL, IRET or the JMP
3685 * instruction or delivery of the exception generated by one of these instructions
3686 * lead to a task switch through a task gate in the IDT, we need to provide the
3687 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3688 * leaves the VM-exit instruction length field undefined.
3689 *
3690 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3691 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3692 */
3693 Assert(cbInstr <= 15);
3694
3695 uint8_t uType;
3696 switch (enmTaskSwitch)
3697 {
3698 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3699 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3700 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3701 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3702 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3703 }
3704
3705 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3706 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3707 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3708 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3709 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3710}
3711
3712
3713/**
3714 * VMX VM-exit handler for VM-exits due to external interrupts.
3715 *
3716 * @returns VBox strict status code.
3717 * @param pVCpu The cross context virtual CPU structure.
3718 * @param uVector The external interrupt vector.
3719 * @param fIntPending Whether the external interrupt is pending or
3720 * acknowdledged in the interrupt controller.
3721 */
3722IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3723{
3724 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3725 Assert(pVmcs);
3726
3727 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3728 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3729 {
3730 if (fIntPending)
3731 {
3732 /*
3733 * If the interrupt is pending and we don't need to acknowledge the
3734 * interrupt on VM-exit, cause the VM-exit immediately.
3735 *
3736 * See Intel spec 25.2 "Other Causes Of VM Exits".
3737 */
3738 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3739 {
3740 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3741 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3742 iemVmxVmcsSetExitQual(pVCpu, 0);
3743 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3744 }
3745
3746 /*
3747 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3748 * on VM-exit, postpone VM-exit til after the interrupt controller has been
3749 * acknowledged that the interrupt has been consumed.
3750 */
3751 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3752 }
3753
3754 /*
3755 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3756 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3757 * all set, we cause the VM-exit now. We need to record the external interrupt that
3758 * just occurred in the VM-exit interruption information field.
3759 *
3760 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3761 */
3762 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3763 {
3764 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3765 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3766 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3767 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3768 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3769 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3770 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3771 iemVmxVmcsSetExitQual(pVCpu, 0);
3772 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3773 }
3774 }
3775
3776 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3777}
3778
3779
3780/**
3781 * VMX VM-exit handler for interrupt-window VM-exits.
3782 *
3783 * @returns VBox strict status code.
3784 * @param pVCpu The cross context virtual CPU structure.
3785 */
3786IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3787{
3788 iemVmxVmcsSetExitQual(pVCpu, 0);
3789 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3790}
3791
3792
3793/**
3794 * VMX VM-exit handler for VM-exits due to delivery of an event.
3795 *
3796 * @returns VBox strict status code.
3797 * @param pVCpu The cross context virtual CPU structure.
3798 * @param uVector The interrupt / exception vector.
3799 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3800 * @param uErrCode The error code associated with the event.
3801 * @param uCr2 The CR2 value in case of a \#PF exception.
3802 * @param cbInstr The instruction length in bytes.
3803 */
3804IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3805 uint8_t cbInstr)
3806{
3807 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3808 Assert(pVmcs);
3809
3810 /*
3811 * If the event is being injected as part of VM-entry, it isn't subject to event
3812 * intercepts in the nested-guest. However, secondary exceptions that occur during
3813 * injection of any event -are- subject to event interception.
3814 *
3815 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3816 */
3817 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3818 {
3819 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3820 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3821 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3822 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3823 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3824 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3825 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3826 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3827 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3828
3829 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3830 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3831 }
3832
3833 /*
3834 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3835 * If not, the caller will continue delivery of the external interrupt as it would
3836 * normally.
3837 */
3838 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3839 {
3840 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3841 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3842 }
3843
3844 /*
3845 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3846 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3847 */
3848 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3849 bool fIntercept = false;
3850 bool fIsHwXcpt = false;
3851 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3852 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3853 {
3854 fIsHwXcpt = true;
3855 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3856 if (uVector == X86_XCPT_NMI)
3857 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3858 else
3859 {
3860 /* Page-faults are subject to masking using its error code. */
3861 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3862 if (uVector == X86_XCPT_PF)
3863 {
3864 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
3865 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
3866 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
3867 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
3868 }
3869
3870 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
3871 if (fXcptBitmap & RT_BIT(uVector))
3872 fIntercept = true;
3873 }
3874 }
3875 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3876
3877 /*
3878 * Now that we've determined whether the software interrupt or hardware exception
3879 * causes a VM-exit, we need to construct the relevant VM-exit information and
3880 * cause the VM-exit.
3881 */
3882 if (fIntercept)
3883 {
3884 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3885
3886 /* Construct the rest of the event related information fields and cause the VM-exit. */
3887 uint64_t uExitQual = 0;
3888 if (fIsHwXcpt)
3889 {
3890 if (uVector == X86_XCPT_PF)
3891 uExitQual = uCr2;
3892 else if (uVector == X86_XCPT_DB)
3893 {
3894 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
3895 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3896 }
3897 }
3898
3899 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3900 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3901 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3902 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3903 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3904 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3905 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3906 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3907 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3908 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3909 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3910
3911 /*
3912 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
3913 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3914 * length.
3915 */
3916 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3917 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3918 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3919 else
3920 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3921
3922 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3923 }
3924
3925 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3926}
3927
3928
3929/**
3930 * VMX VM-exit handler for VM-exits due to a triple fault.
3931 *
3932 * @returns VBox strict status code.
3933 * @param pVCpu The cross context virtual CPU structure.
3934 */
3935IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3936{
3937 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3938 Assert(pVmcs);
3939 iemVmxVmcsSetExitQual(pVCpu, 0);
3940 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
3941}
3942
3943
3944/**
3945 * VMX VM-exit handler for TPR virtualization.
3946 *
3947 * @returns VBox strict status code.
3948 * @param pVCpu The cross context virtual CPU structure.
3949 * @param cbInstr The instruction length in bytes.
3950 */
3951IEM_STATIC VBOXSTRICTRC iemVmxVmexitTprVirtualization(PVMCPU pVCpu, uint8_t cbInstr)
3952{
3953 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3954 Assert(pVmcs);
3955
3956 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
3957 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)); /* We don't support virtual-interrupt delivery yet. */
3958
3959 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
3960 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
3961
3962 /*
3963 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
3964 * See Intel spec. 29.1.2 "TPR Virtualization".
3965 */
3966 if (((uVTpr >> 4) & 0xf) < uTprThreshold)
3967 {
3968 Log2(("tpr_virt: uVTpr=%u uTprThreshold=%u -> VM-exit\n", uVTpr, uTprThreshold));
3969
3970 /*
3971 * This is a trap-like VM-exit. We pass the instruction length along in the VM-exit
3972 * instruction length field and let the VM-exit handler update the RIP when appropriate.
3973 * It will then clear the VM-exit instruction length field before completing the VM-exit.
3974 *
3975 * The VM-exit qualification must be cleared.
3976 */
3977 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3978 iemVmxVmcsSetExitQual(pVCpu, 0);
3979 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
3980 }
3981
3982 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3983}
3984
3985
3986/**
3987 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
3988 *
3989 * @param pVCpu The cross context virtual CPU structure.
3990 * @param pszInstr The VMX instruction name (for logging purposes).
3991 */
3992IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
3993{
3994 /*
3995 * Guest Control Registers, Debug Registers, and MSRs.
3996 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
3997 */
3998 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3999 const char *const pszFailure = "VM-exit";
4000 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4001
4002 /* CR0 reserved bits. */
4003 {
4004 /* CR0 MB1 bits. */
4005 uint64_t u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
4006 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4007 if (fUnrestrictedGuest)
4008 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4009 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
4010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4011
4012 /* CR0 MBZ bits. */
4013 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
4014 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
4015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4016
4017 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4018 if ( !fUnrestrictedGuest
4019 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4020 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4021 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4022 }
4023
4024 /* CR4 reserved bits. */
4025 {
4026 /* CR4 MB1 bits. */
4027 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
4028 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
4029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4030
4031 /* CR4 MBZ bits. */
4032 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
4033 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
4034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4035 }
4036
4037 /* DEBUGCTL MSR. */
4038 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4039 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4041
4042 /* 64-bit CPU checks. */
4043 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4044 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4045 {
4046 if (fGstInLongMode)
4047 {
4048 /* PAE must be set. */
4049 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4050 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4051 { /* likely */ }
4052 else
4053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4054 }
4055 else
4056 {
4057 /* PCIDE should not be set. */
4058 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4059 { /* likely */ }
4060 else
4061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4062 }
4063
4064 /* CR3. */
4065 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4066 { /* likely */ }
4067 else
4068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4069
4070 /* DR7. */
4071 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4072 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4073 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4074
4075 /* SYSENTER ESP and SYSENTER EIP. */
4076 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4077 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4078 { /* likely */ }
4079 else
4080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4081 }
4082
4083 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4084 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4085
4086 /* PAT MSR. */
4087 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4088 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4090
4091 /* EFER MSR. */
4092 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4093 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4094 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4096
4097 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
4098 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
4099 if ( fGstInLongMode == fGstLma
4100 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4101 || fGstLma == fGstLme))
4102 { /* likely */ }
4103 else
4104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4105
4106 /* We don't support IA32_BNDCFGS MSR yet. */
4107 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4108
4109 NOREF(pszInstr);
4110 NOREF(pszFailure);
4111 return VINF_SUCCESS;
4112}
4113
4114
4115/**
4116 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4117 *
4118 * @param pVCpu The cross context virtual CPU structure.
4119 * @param pszInstr The VMX instruction name (for logging purposes).
4120 */
4121IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4122{
4123 /*
4124 * Segment registers.
4125 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4126 */
4127 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4128 const char *const pszFailure = "VM-exit";
4129 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4130 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4131 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4132
4133 /* Selectors. */
4134 if ( !fGstInV86Mode
4135 && !fUnrestrictedGuest
4136 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4137 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4138
4139 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4140 {
4141 CPUMSELREG SelReg;
4142 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4143 if (RT_LIKELY(rc == VINF_SUCCESS))
4144 { /* likely */ }
4145 else
4146 return rc;
4147
4148 /*
4149 * Virtual-8086 mode checks.
4150 */
4151 if (fGstInV86Mode)
4152 {
4153 /* Base address. */
4154 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4155 { /* likely */ }
4156 else
4157 {
4158 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4160 }
4161
4162 /* Limit. */
4163 if (SelReg.u32Limit == 0xffff)
4164 { /* likely */ }
4165 else
4166 {
4167 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4169 }
4170
4171 /* Attribute. */
4172 if (SelReg.Attr.u == 0xf3)
4173 { /* likely */ }
4174 else
4175 {
4176 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4178 }
4179
4180 /* We're done; move to checking the next segment. */
4181 continue;
4182 }
4183
4184 /* Checks done by 64-bit CPUs. */
4185 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4186 {
4187 /* Base address. */
4188 if ( iSegReg == X86_SREG_FS
4189 || iSegReg == X86_SREG_GS)
4190 {
4191 if (X86_IS_CANONICAL(SelReg.u64Base))
4192 { /* likely */ }
4193 else
4194 {
4195 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4197 }
4198 }
4199 else if (iSegReg == X86_SREG_CS)
4200 {
4201 if (!RT_HI_U32(SelReg.u64Base))
4202 { /* likely */ }
4203 else
4204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4205 }
4206 else
4207 {
4208 if ( SelReg.Attr.n.u1Unusable
4209 || !RT_HI_U32(SelReg.u64Base))
4210 { /* likely */ }
4211 else
4212 {
4213 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4215 }
4216 }
4217 }
4218
4219 /*
4220 * Checks outside Virtual-8086 mode.
4221 */
4222 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4223 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4224 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4225 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4226 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4227 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4228 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4229 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4230
4231 /* Code or usable segment. */
4232 if ( iSegReg == X86_SREG_CS
4233 || fUsable)
4234 {
4235 /* Reserved bits (bits 31:17 and bits 11:8). */
4236 if (!(SelReg.Attr.u & 0xfffe0f00))
4237 { /* likely */ }
4238 else
4239 {
4240 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4242 }
4243
4244 /* Descriptor type. */
4245 if (fCodeDataSeg)
4246 { /* likely */ }
4247 else
4248 {
4249 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
4250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4251 }
4252
4253 /* Present. */
4254 if (fPresent)
4255 { /* likely */ }
4256 else
4257 {
4258 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
4259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4260 }
4261
4262 /* Granularity. */
4263 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
4264 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
4265 { /* likely */ }
4266 else
4267 {
4268 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
4269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4270 }
4271 }
4272
4273 if (iSegReg == X86_SREG_CS)
4274 {
4275 /* Segment Type and DPL. */
4276 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4277 && fUnrestrictedGuest)
4278 {
4279 if (uDpl == 0)
4280 { /* likely */ }
4281 else
4282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
4283 }
4284 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4285 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4286 {
4287 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4288 if (uDpl == AttrSs.n.u2Dpl)
4289 { /* likely */ }
4290 else
4291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
4292 }
4293 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4294 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4295 {
4296 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4297 if (uDpl <= AttrSs.n.u2Dpl)
4298 { /* likely */ }
4299 else
4300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
4301 }
4302 else
4303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
4304
4305 /* Def/Big. */
4306 if ( fGstInLongMode
4307 && fSegLong)
4308 {
4309 if (uDefBig == 0)
4310 { /* likely */ }
4311 else
4312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
4313 }
4314 }
4315 else if (iSegReg == X86_SREG_SS)
4316 {
4317 /* Segment Type. */
4318 if ( !fUsable
4319 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4320 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
4321 { /* likely */ }
4322 else
4323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
4324
4325 /* DPL. */
4326 if (fUnrestrictedGuest)
4327 {
4328 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
4329 { /* likely */ }
4330 else
4331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
4332 }
4333 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4334 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4335 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
4336 {
4337 if (uDpl == 0)
4338 { /* likely */ }
4339 else
4340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
4341 }
4342 }
4343 else
4344 {
4345 /* DS, ES, FS, GS. */
4346 if (fUsable)
4347 {
4348 /* Segment type. */
4349 if (uSegType & X86_SEL_TYPE_ACCESSED)
4350 { /* likely */ }
4351 else
4352 {
4353 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
4354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4355 }
4356
4357 if ( !(uSegType & X86_SEL_TYPE_CODE)
4358 || (uSegType & X86_SEL_TYPE_READ))
4359 { /* likely */ }
4360 else
4361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
4362
4363 /* DPL. */
4364 if ( !fUnrestrictedGuest
4365 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4366 {
4367 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
4368 { /* likely */ }
4369 else
4370 {
4371 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
4372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4373 }
4374 }
4375 }
4376 }
4377 }
4378
4379 /*
4380 * LDTR.
4381 */
4382 {
4383 CPUMSELREG Ldtr;
4384 Ldtr.Sel = pVmcs->GuestLdtr;
4385 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
4386 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
4387 Ldtr.Attr.u = pVmcs->u32GuestLdtrLimit;
4388
4389 if (!Ldtr.Attr.n.u1Unusable)
4390 {
4391 /* Selector. */
4392 if (!(Ldtr.Sel & X86_SEL_LDT))
4393 { /* likely */ }
4394 else
4395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
4396
4397 /* Base. */
4398 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4399 {
4400 if (X86_IS_CANONICAL(Ldtr.u64Base))
4401 { /* likely */ }
4402 else
4403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
4404 }
4405
4406 /* Attributes. */
4407 /* Reserved bits (bits 31:17 and bits 11:8). */
4408 if (!(Ldtr.Attr.u & 0xfffe0f00))
4409 { /* likely */ }
4410 else
4411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
4412
4413 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
4414 { /* likely */ }
4415 else
4416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
4417
4418 if (!Ldtr.Attr.n.u1DescType)
4419 { /* likely */ }
4420 else
4421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
4422
4423 if (Ldtr.Attr.n.u1Present)
4424 { /* likely */ }
4425 else
4426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
4427
4428 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
4429 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
4430 { /* likely */ }
4431 else
4432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
4433 }
4434 }
4435
4436 /*
4437 * TR.
4438 */
4439 {
4440 CPUMSELREG Tr;
4441 Tr.Sel = pVmcs->GuestTr;
4442 Tr.u32Limit = pVmcs->u32GuestTrLimit;
4443 Tr.u64Base = pVmcs->u64GuestTrBase.u;
4444 Tr.Attr.u = pVmcs->u32GuestTrLimit;
4445
4446 /* Selector. */
4447 if (!(Tr.Sel & X86_SEL_LDT))
4448 { /* likely */ }
4449 else
4450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
4451
4452 /* Base. */
4453 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4454 {
4455 if (X86_IS_CANONICAL(Tr.u64Base))
4456 { /* likely */ }
4457 else
4458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
4459 }
4460
4461 /* Attributes. */
4462 /* Reserved bits (bits 31:17 and bits 11:8). */
4463 if (!(Tr.Attr.u & 0xfffe0f00))
4464 { /* likely */ }
4465 else
4466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
4467
4468 if (!Tr.Attr.n.u1Unusable)
4469 { /* likely */ }
4470 else
4471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
4472
4473 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
4474 || ( !fGstInLongMode
4475 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
4476 { /* likely */ }
4477 else
4478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
4479
4480 if (!Tr.Attr.n.u1DescType)
4481 { /* likely */ }
4482 else
4483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
4484
4485 if (Tr.Attr.n.u1Present)
4486 { /* likely */ }
4487 else
4488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
4489
4490 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
4491 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
4492 { /* likely */ }
4493 else
4494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
4495 }
4496
4497 NOREF(pszInstr);
4498 NOREF(pszFailure);
4499 return VINF_SUCCESS;
4500}
4501
4502
4503/**
4504 * Checks guest GDTR and IDTR as part of VM-entry.
4505 *
4506 * @param pVCpu The cross context virtual CPU structure.
4507 * @param pszInstr The VMX instruction name (for logging purposes).
4508 */
4509IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
4510{
4511 /*
4512 * GDTR and IDTR.
4513 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
4514 */
4515 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4516 const char *const pszFailure = "VM-exit";
4517
4518 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4519 {
4520 /* Base. */
4521 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
4522 { /* likely */ }
4523 else
4524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
4525
4526 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
4527 { /* likely */ }
4528 else
4529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
4530 }
4531
4532 /* Limit. */
4533 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
4534 { /* likely */ }
4535 else
4536 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
4537
4538 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
4539 { /* likely */ }
4540 else
4541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
4542
4543 NOREF(pszInstr);
4544 NOREF(pszFailure);
4545 return VINF_SUCCESS;
4546}
4547
4548
4549/**
4550 * Checks guest RIP and RFLAGS as part of VM-entry.
4551 *
4552 * @param pVCpu The cross context virtual CPU structure.
4553 * @param pszInstr The VMX instruction name (for logging purposes).
4554 */
4555IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
4556{
4557 /*
4558 * RIP and RFLAGS.
4559 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
4560 */
4561 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4562 const char *const pszFailure = "VM-exit";
4563 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4564
4565 /* RIP. */
4566 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4567 {
4568 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4569 if ( !fGstInLongMode
4570 || !AttrCs.n.u1Long)
4571 {
4572 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
4573 { /* likely */ }
4574 else
4575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
4576 }
4577
4578 if ( fGstInLongMode
4579 && AttrCs.n.u1Long)
4580 {
4581 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
4582 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
4583 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
4584 { /* likely */ }
4585 else
4586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
4587 }
4588 }
4589
4590 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
4591 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
4592 : pVmcs->u64GuestRFlags.s.Lo;
4593 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
4594 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
4595 { /* likely */ }
4596 else
4597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
4598
4599 if ( fGstInLongMode
4600 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4601 {
4602 if (!(uGuestRFlags & X86_EFL_VM))
4603 { /* likely */ }
4604 else
4605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
4606 }
4607
4608 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
4609 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4610 {
4611 if (uGuestRFlags & X86_EFL_IF)
4612 { /* likely */ }
4613 else
4614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
4615 }
4616
4617 NOREF(pszInstr);
4618 NOREF(pszFailure);
4619 return VINF_SUCCESS;
4620}
4621
4622
4623/**
4624 * Checks guest non-register state as part of VM-entry.
4625 *
4626 * @param pVCpu The cross context virtual CPU structure.
4627 * @param pszInstr The VMX instruction name (for logging purposes).
4628 */
4629IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
4630{
4631 /*
4632 * Guest non-register state.
4633 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
4634 */
4635 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4636 const char *const pszFailure = "VM-exit";
4637
4638 /*
4639 * Activity state.
4640 */
4641 uint64_t const u64GuestVmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
4642 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
4643 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
4644 { /* likely */ }
4645 else
4646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
4647
4648 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4649 if ( !AttrSs.n.u2Dpl
4650 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
4651 { /* likely */ }
4652 else
4653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
4654
4655 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
4656 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
4657 {
4658 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
4659 { /* likely */ }
4660 else
4661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
4662 }
4663
4664 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4665 {
4666 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4667 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
4668 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
4669 switch (pVmcs->u32GuestActivityState)
4670 {
4671 case VMX_VMCS_GUEST_ACTIVITY_HLT:
4672 {
4673 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
4674 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4675 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4676 && ( uVector == X86_XCPT_DB
4677 || uVector == X86_XCPT_MC))
4678 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
4679 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
4680 { /* likely */ }
4681 else
4682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
4683 break;
4684 }
4685
4686 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
4687 {
4688 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4689 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4690 && uVector == X86_XCPT_MC))
4691 { /* likely */ }
4692 else
4693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
4694 break;
4695 }
4696
4697 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
4698 default:
4699 break;
4700 }
4701 }
4702
4703 /*
4704 * Interruptibility state.
4705 */
4706 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
4707 { /* likely */ }
4708 else
4709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
4710
4711 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4712 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4713 { /* likely */ }
4714 else
4715 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
4716
4717 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
4718 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4719 { /* likely */ }
4720 else
4721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
4722
4723 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4724 {
4725 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4726 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4727 {
4728 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4729 { /* likely */ }
4730 else
4731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
4732 }
4733 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
4734 {
4735 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4736 { /* likely */ }
4737 else
4738 {
4739 /*
4740 * We don't support injecting NMIs when blocking-by-STI would be in effect.
4741 * We update the VM-exit qualification only when blocking-by-STI is set
4742 * without blocking-by-MovSS being set. Although in practise it does not
4743 * make much difference since the order of checks are implementation defined.
4744 */
4745 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
4746 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
4747 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
4748 }
4749
4750 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
4751 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
4752 { /* likely */ }
4753 else
4754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
4755 }
4756 }
4757
4758 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
4759 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
4760 { /* likely */ }
4761 else
4762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
4763
4764 /* We don't support SGX yet. So enclave-interruption must not be set. */
4765 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
4766 { /* likely */ }
4767 else
4768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
4769
4770 /*
4771 * Pending debug exceptions.
4772 */
4773 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
4774 ? pVmcs->u64GuestPendingDbgXcpt.u
4775 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
4776 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
4777 { /* likely */ }
4778 else
4779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
4780
4781 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4782 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
4783 {
4784 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4785 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
4786 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4787 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
4788
4789 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4790 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
4791 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4792 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
4793 }
4794
4795 /* We don't support RTM (Real-time Transactional Memory) yet. */
4796 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
4797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
4798
4799 /*
4800 * VMCS link pointer.
4801 */
4802 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
4803 {
4804 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
4805 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
4806 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
4807 { /* likely */ }
4808 else
4809 {
4810 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
4812 }
4813
4814 /* Validate the address. */
4815 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
4816 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
4817 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
4818 {
4819 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
4821 }
4822
4823 /* Read the VMCS-link pointer from guest memory. */
4824 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
4825 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
4826 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
4827 if (RT_FAILURE(rc))
4828 {
4829 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4830 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
4831 }
4832
4833 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
4834 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
4835 { /* likely */ }
4836 else
4837 {
4838 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
4840 }
4841
4842 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
4843 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
4844 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
4845 { /* likely */ }
4846 else
4847 {
4848 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
4850 }
4851
4852 /* Finally update our cache of the guest physical address of the shadow VMCS. */
4853 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
4854 }
4855
4856 NOREF(pszInstr);
4857 NOREF(pszFailure);
4858 return VINF_SUCCESS;
4859}
4860
4861
4862/**
4863 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
4864 * VM-entry.
4865 *
4866 * @returns @c true if all PDPTEs are valid, @c false otherwise.
4867 * @param pVCpu The cross context virtual CPU structure.
4868 * @param pszInstr The VMX instruction name (for logging purposes).
4869 * @param pVmcs Pointer to the virtual VMCS.
4870 */
4871IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
4872{
4873 /*
4874 * Check PDPTEs.
4875 * See Intel spec. 4.4.1 "PDPTE Registers".
4876 */
4877 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
4878 const char *const pszFailure = "VM-exit";
4879
4880 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
4881 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
4882 if (RT_SUCCESS(rc))
4883 {
4884 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
4885 {
4886 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
4887 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
4888 { /* likely */ }
4889 else
4890 {
4891 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4892 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4894 }
4895 }
4896 }
4897 else
4898 {
4899 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4900 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
4901 }
4902
4903 NOREF(pszFailure);
4904 return rc;
4905}
4906
4907
4908/**
4909 * Checks guest PDPTEs as part of VM-entry.
4910 *
4911 * @param pVCpu The cross context virtual CPU structure.
4912 * @param pszInstr The VMX instruction name (for logging purposes).
4913 */
4914IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
4915{
4916 /*
4917 * Guest PDPTEs.
4918 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
4919 */
4920 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4921 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4922
4923 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
4924 int rc;
4925 if ( !fGstInLongMode
4926 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
4927 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
4928 {
4929 /*
4930 * We don't support nested-paging for nested-guests yet.
4931 *
4932 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
4933 * rather we need to check the PDPTEs referenced by the guest CR3.
4934 */
4935 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
4936 }
4937 else
4938 rc = VINF_SUCCESS;
4939 return rc;
4940}
4941
4942
4943/**
4944 * Checks guest-state as part of VM-entry.
4945 *
4946 * @returns VBox status code.
4947 * @param pVCpu The cross context virtual CPU structure.
4948 * @param pszInstr The VMX instruction name (for logging purposes).
4949 */
4950IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
4951{
4952 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
4953 if (RT_SUCCESS(rc))
4954 {
4955 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
4956 if (RT_SUCCESS(rc))
4957 {
4958 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
4959 if (RT_SUCCESS(rc))
4960 {
4961 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
4962 if (RT_SUCCESS(rc))
4963 {
4964 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
4965 if (RT_SUCCESS(rc))
4966 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
4967 }
4968 }
4969 }
4970 }
4971 return rc;
4972}
4973
4974
4975/**
4976 * Checks host-state as part of VM-entry.
4977 *
4978 * @returns VBox status code.
4979 * @param pVCpu The cross context virtual CPU structure.
4980 * @param pszInstr The VMX instruction name (for logging purposes).
4981 */
4982IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
4983{
4984 /*
4985 * Host Control Registers and MSRs.
4986 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
4987 */
4988 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4989 const char * const pszFailure = "VMFail";
4990
4991 /* CR0 reserved bits. */
4992 {
4993 /* CR0 MB1 bits. */
4994 uint64_t const u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
4995 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
4996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
4997
4998 /* CR0 MBZ bits. */
4999 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
5000 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
5001 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5002 }
5003
5004 /* CR4 reserved bits. */
5005 {
5006 /* CR4 MB1 bits. */
5007 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
5008 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
5009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5010
5011 /* CR4 MBZ bits. */
5012 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
5013 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
5014 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5015 }
5016
5017 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5018 {
5019 /* CR3 reserved bits. */
5020 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5021 { /* likely */ }
5022 else
5023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5024
5025 /* SYSENTER ESP and SYSENTER EIP. */
5026 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5027 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5028 { /* likely */ }
5029 else
5030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5031 }
5032
5033 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5034 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5035
5036 /* PAT MSR. */
5037 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5038 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5039 { /* likely */ }
5040 else
5041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5042
5043 /* EFER MSR. */
5044 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5045 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5046 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5047 { /* likely */ }
5048 else
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5050
5051 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5052 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5053 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5054 if ( fHostInLongMode == fHostLma
5055 && fHostInLongMode == fHostLme)
5056 { /* likely */ }
5057 else
5058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5059
5060 /*
5061 * Host Segment and Descriptor-Table Registers.
5062 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5063 */
5064 /* Selector RPL and TI. */
5065 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5066 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5067 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5068 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5069 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5070 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5071 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5072 { /* likely */ }
5073 else
5074 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5075
5076 /* CS and TR selectors cannot be 0. */
5077 if ( pVmcs->HostCs
5078 && pVmcs->HostTr)
5079 { /* likely */ }
5080 else
5081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5082
5083 /* SS cannot be 0 if 32-bit host. */
5084 if ( fHostInLongMode
5085 || pVmcs->HostSs)
5086 { /* likely */ }
5087 else
5088 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5089
5090 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5091 {
5092 /* FS, GS, GDTR, IDTR, TR base address. */
5093 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5094 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5095 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5096 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5097 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5098 { /* likely */ }
5099 else
5100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5101 }
5102
5103 /*
5104 * Host address-space size for 64-bit CPUs.
5105 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5106 */
5107 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5108 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5109 {
5110 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5111
5112 /* Logical processor in IA-32e mode. */
5113 if (fCpuInLongMode)
5114 {
5115 if (fHostInLongMode)
5116 {
5117 /* PAE must be set. */
5118 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5122
5123 /* RIP must be canonical. */
5124 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5125 { /* likely */ }
5126 else
5127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5128 }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5131 }
5132 else
5133 {
5134 /* Logical processor is outside IA-32e mode. */
5135 if ( !fGstInLongMode
5136 && !fHostInLongMode)
5137 {
5138 /* PCIDE should not be set. */
5139 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5140 { /* likely */ }
5141 else
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5143
5144 /* The high 32-bits of RIP MBZ. */
5145 if (!pVmcs->u64HostRip.s.Hi)
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5149 }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5152 }
5153 }
5154 else
5155 {
5156 /* Host address-space size for 32-bit CPUs. */
5157 if ( !fGstInLongMode
5158 && !fHostInLongMode)
5159 { /* likely */ }
5160 else
5161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5162 }
5163
5164 NOREF(pszInstr);
5165 NOREF(pszFailure);
5166 return VINF_SUCCESS;
5167}
5168
5169
5170/**
5171 * Checks VM-entry controls fields as part of VM-entry.
5172 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
5173 *
5174 * @returns VBox status code.
5175 * @param pVCpu The cross context virtual CPU structure.
5176 * @param pszInstr The VMX instruction name (for logging purposes).
5177 */
5178IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
5179{
5180 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5181 const char * const pszFailure = "VMFail";
5182
5183 /* VM-entry controls. */
5184 VMXCTLSMSR EntryCtls;
5185 EntryCtls.u = CPUMGetGuestIa32VmxEntryCtls(pVCpu);
5186 if (~pVmcs->u32EntryCtls & EntryCtls.n.disallowed0)
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
5188
5189 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
5191
5192 /* Event injection. */
5193 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
5194 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
5195 {
5196 /* Type and vector. */
5197 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
5198 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
5199 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
5200 if ( !uRsvd
5201 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
5202 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
5203 { /* likely */ }
5204 else
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
5206
5207 /* Exception error code. */
5208 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
5209 {
5210 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
5211 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
5212 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
5216
5217 /* Exceptions that provide an error code. */
5218 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5219 && ( uVector == X86_XCPT_DF
5220 || uVector == X86_XCPT_TS
5221 || uVector == X86_XCPT_NP
5222 || uVector == X86_XCPT_SS
5223 || uVector == X86_XCPT_GP
5224 || uVector == X86_XCPT_PF
5225 || uVector == X86_XCPT_AC))
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
5229
5230 /* Exception error-code reserved bits. */
5231 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
5232 { /* likely */ }
5233 else
5234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
5235
5236 /* Injecting a software interrupt, software exception or privileged software exception. */
5237 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
5238 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
5239 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
5240 {
5241 /* Instruction length must be in the range 0-15. */
5242 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
5243 { /* likely */ }
5244 else
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
5246
5247 /* Instruction length of 0 is allowed only when its CPU feature is present. */
5248 if ( pVmcs->u32EntryInstrLen == 0
5249 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
5251 }
5252 }
5253 }
5254
5255 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
5256 if (pVmcs->u32EntryMsrLoadCount)
5257 {
5258 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5259 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5260 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
5262 }
5263
5264 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
5265 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
5266
5267 NOREF(pszInstr);
5268 NOREF(pszFailure);
5269 return VINF_SUCCESS;
5270}
5271
5272
5273/**
5274 * Checks VM-exit controls fields as part of VM-entry.
5275 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
5276 *
5277 * @returns VBox status code.
5278 * @param pVCpu The cross context virtual CPU structure.
5279 * @param pszInstr The VMX instruction name (for logging purposes).
5280 */
5281IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
5282{
5283 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5284 const char * const pszFailure = "VMFail";
5285
5286 /* VM-exit controls. */
5287 VMXCTLSMSR ExitCtls;
5288 ExitCtls.u = CPUMGetGuestIa32VmxExitCtls(pVCpu);
5289 if (~pVmcs->u32ExitCtls & ExitCtls.n.disallowed0)
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
5291
5292 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
5294
5295 /* Save preemption timer without activating it. */
5296 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
5297 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
5299
5300 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
5301 if (pVmcs->u32ExitMsrStoreCount)
5302 {
5303 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
5304 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5305 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
5306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
5307 }
5308
5309 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
5310 if (pVmcs->u32ExitMsrLoadCount)
5311 {
5312 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5313 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5314 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
5315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
5316 }
5317
5318 NOREF(pszInstr);
5319 NOREF(pszFailure);
5320 return VINF_SUCCESS;
5321}
5322
5323
5324/**
5325 * Checks VM-execution controls fields as part of VM-entry.
5326 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5327 *
5328 * @returns VBox status code.
5329 * @param pVCpu The cross context virtual CPU structure.
5330 * @param pszInstr The VMX instruction name (for logging purposes).
5331 *
5332 * @remarks This may update secondary-processor based VM-execution control fields
5333 * in the current VMCS if necessary.
5334 */
5335IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
5336{
5337 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5338 const char * const pszFailure = "VMFail";
5339
5340 /* Pin-based VM-execution controls. */
5341 {
5342 VMXCTLSMSR PinCtls;
5343 PinCtls.u = CPUMGetGuestIa32VmxPinbasedCtls(pVCpu);
5344 if (~pVmcs->u32PinCtls & PinCtls.n.disallowed0)
5345 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5346
5347 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
5348 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5349 }
5350
5351 /* Processor-based VM-execution controls. */
5352 {
5353 VMXCTLSMSR ProcCtls;
5354 ProcCtls.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
5355 if (~pVmcs->u32ProcCtls & ProcCtls.n.disallowed0)
5356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5357
5358 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
5359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5360 }
5361
5362 /* Secondary processor-based VM-execution controls. */
5363 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5364 {
5365 VMXCTLSMSR ProcCtls2;
5366 ProcCtls2.u = CPUMGetGuestIa32VmxProcbasedCtls2(pVCpu);
5367 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.disallowed0)
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5369
5370 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
5371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
5372 }
5373 else
5374 Assert(!pVmcs->u32ProcCtls2);
5375
5376 /* CR3-target count. */
5377 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
5378 { /* likely */ }
5379 else
5380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
5381
5382 /* I/O bitmaps physical addresses. */
5383 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
5384 {
5385 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
5386 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5387 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
5389
5390 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
5391 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5392 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
5393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
5394 }
5395
5396 /* MSR bitmap physical address. */
5397 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
5398 {
5399 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
5400 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
5401 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5402 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
5403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
5404
5405 /* Read the MSR bitmap. */
5406 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
5407 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
5408 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
5409 if (RT_FAILURE(rc))
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
5411 }
5412
5413 /* TPR shadow related controls. */
5414 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5415 {
5416 /* Virtual-APIC page physical address. */
5417 RTGCPHYS GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
5418 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
5419 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5420 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
5421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
5422
5423 /* Read the Virtual-APIC page. */
5424 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
5425 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
5426 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
5427 if (RT_FAILURE(rc))
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
5429
5430 /* TPR threshold without virtual-interrupt delivery. */
5431 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5432 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
5434
5435 /* TPR threshold and VTPR. */
5436 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
5437 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
5438 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5439 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5440 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
5442 }
5443 else
5444 {
5445 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5446 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5447 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
5448 { /* likely */ }
5449 else
5450 {
5451 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
5453 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
5455 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5456 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
5457 }
5458 }
5459
5460 /* NMI exiting and virtual-NMIs. */
5461 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
5462 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
5464
5465 /* Virtual-NMIs and NMI-window exiting. */
5466 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5467 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
5468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
5469
5470 /* Virtualize APIC accesses. */
5471 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5472 {
5473 /* APIC-access physical address. */
5474 RTGCPHYS GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
5475 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
5476 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5477 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
5479 }
5480
5481 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
5482 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5483 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
5484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5485
5486 /* Virtual-interrupt delivery requires external interrupt exiting. */
5487 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5488 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
5489 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5490
5491 /* VPID. */
5492 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
5493 || pVmcs->u16Vpid != 0)
5494 { /* likely */ }
5495 else
5496 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
5497
5498 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
5499 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
5500 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
5501 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
5502 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
5503 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
5504 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
5505
5506 /* VMCS shadowing. */
5507 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5508 {
5509 /* VMREAD-bitmap physical address. */
5510 RTGCPHYS GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
5511 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
5512 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5513 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
5515
5516 /* VMWRITE-bitmap physical address. */
5517 RTGCPHYS GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
5518 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
5519 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5520 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
5522
5523 /* Read the VMREAD-bitmap. */
5524 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
5525 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
5526 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5527 if (RT_FAILURE(rc))
5528 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
5529
5530 /* Read the VMWRITE-bitmap. */
5531 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
5532 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
5533 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5534 if (RT_FAILURE(rc))
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
5536 }
5537
5538 NOREF(pszInstr);
5539 NOREF(pszFailure);
5540 return VINF_SUCCESS;
5541}
5542
5543
5544/**
5545 * Loads the guest control registers, debug register and some MSRs as part of
5546 * VM-entry.
5547 *
5548 * @param pVCpu The cross context virtual CPU structure.
5549 */
5550IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
5551{
5552 /*
5553 * Load guest control registers, debug registers and MSRs.
5554 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
5555 */
5556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5557 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
5558 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
5559 CPUMSetGuestCR0(pVCpu, uGstCr0);
5560 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
5561 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
5562
5563 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5564 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
5565
5566 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
5567 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
5568 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
5569
5570 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5571 {
5572 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
5573
5574 /* EFER MSR. */
5575 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
5576 {
5577 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5578 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
5579 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
5580 if (fGstInLongMode)
5581 {
5582 /* If the nested-guest is in long mode, LMA and LME are both set. */
5583 Assert(fGstPaging);
5584 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
5585 }
5586 else
5587 {
5588 /*
5589 * If the nested-guest is outside long mode:
5590 * - With paging: LMA is cleared, LME is cleared.
5591 * - Without paging: LMA is cleared, LME is left unmodified.
5592 */
5593 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
5594 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
5595 }
5596 }
5597 /* else: see below. */
5598 }
5599
5600 /* PAT MSR. */
5601 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5602 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
5603
5604 /* EFER MSR. */
5605 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5606 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
5607
5608 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5609 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5610
5611 /* We don't support IA32_BNDCFGS MSR yet. */
5612 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5613
5614 /* Nothing to do for SMBASE register - We don't support SMM yet. */
5615}
5616
5617
5618/**
5619 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
5620 *
5621 * @param pVCpu The cross context virtual CPU structure.
5622 */
5623IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
5624{
5625 /*
5626 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
5627 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
5628 */
5629 /* CS, SS, ES, DS, FS, GS. */
5630 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5631 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5632 {
5633 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5634 CPUMSELREG VmcsSelReg;
5635 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
5636 AssertRC(rc); NOREF(rc);
5637 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
5638 {
5639 pGstSelReg->Sel = VmcsSelReg.Sel;
5640 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5641 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5642 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5643 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5644 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5645 }
5646 else
5647 {
5648 pGstSelReg->Sel = VmcsSelReg.Sel;
5649 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5650 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5651 switch (iSegReg)
5652 {
5653 case X86_SREG_CS:
5654 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5655 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5656 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5657 break;
5658
5659 case X86_SREG_SS:
5660 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
5661 pGstSelReg->u32Limit = 0;
5662 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
5663 break;
5664
5665 case X86_SREG_ES:
5666 case X86_SREG_DS:
5667 pGstSelReg->u64Base = 0;
5668 pGstSelReg->u32Limit = 0;
5669 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5670 break;
5671
5672 case X86_SREG_FS:
5673 case X86_SREG_GS:
5674 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5675 pGstSelReg->u32Limit = 0;
5676 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5677 break;
5678 }
5679 Assert(pGstSelReg->Attr.n.u1Unusable);
5680 }
5681 }
5682
5683 /* LDTR. */
5684 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
5685 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
5686 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5687 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
5688 {
5689 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5690 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5691 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5692 }
5693 else
5694 {
5695 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5696 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
5697 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5698 }
5699
5700 /* TR. */
5701 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
5702 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
5703 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
5704 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5705 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
5706 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
5707 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
5708
5709 /* GDTR. */
5710 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
5711 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
5712
5713 /* IDTR. */
5714 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
5715 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
5716}
5717
5718
5719/**
5720 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
5721 *
5722 * @returns VBox status code.
5723 * @param pVCpu The cross context virtual CPU structure.
5724 * @param pszInstr The VMX instruction name (for logging purposes).
5725 */
5726IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
5727{
5728 /*
5729 * Load guest MSRs.
5730 * See Intel spec. 26.4 "Loading MSRs".
5731 */
5732 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5733 const char *const pszFailure = "VM-exit";
5734
5735 /*
5736 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
5737 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
5738 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
5739 */
5740 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
5741 if (!cMsrs)
5742 return VINF_SUCCESS;
5743
5744 /*
5745 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
5746 * exceeded including possibly raising #MC exceptions during VMX transition. Our
5747 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
5748 */
5749 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
5750 if (fIsMsrCountValid)
5751 { /* likely */ }
5752 else
5753 {
5754 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
5755 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
5756 }
5757
5758 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
5759 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
5760 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
5761 if (RT_SUCCESS(rc))
5762 {
5763 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
5764 Assert(pMsr);
5765 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
5766 {
5767 if ( !pMsr->u32Reserved
5768 && pMsr->u32Msr != MSR_K8_FS_BASE
5769 && pMsr->u32Msr != MSR_K8_GS_BASE
5770 && pMsr->u32Msr != MSR_K6_EFER
5771 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
5772 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
5773 {
5774 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
5775 if (rcStrict == VINF_SUCCESS)
5776 continue;
5777
5778 /*
5779 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
5780 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
5781 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
5782 * further by our own, specific diagnostic code. Later, we can try implement handling of the
5783 * MSR in ring-0 if possible, or come up with a better, generic solution.
5784 */
5785 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5786 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
5787 ? kVmxVDiag_Vmentry_MsrLoadRing3
5788 : kVmxVDiag_Vmentry_MsrLoad;
5789 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5790 }
5791 else
5792 {
5793 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5794 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
5795 }
5796 }
5797 }
5798 else
5799 {
5800 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
5802 }
5803
5804 NOREF(pszInstr);
5805 NOREF(pszFailure);
5806 return VINF_SUCCESS;
5807}
5808
5809
5810/**
5811 * Loads the guest-state non-register state as part of VM-entry.
5812 *
5813 * @returns VBox status code.
5814 * @param pVCpu The cross context virtual CPU structure.
5815 *
5816 * @remarks This must be called only after loading the nested-guest register state
5817 * (especially nested-guest RIP).
5818 */
5819IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
5820{
5821 /*
5822 * Load guest non-register state.
5823 * See Intel spec. 26.6 "Special Features of VM Entry"
5824 */
5825 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5826 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
5827 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5828 {
5829 /** @todo NSTVMX: Pending debug exceptions. */
5830 Assert(!(pVmcs->u64GuestPendingDbgXcpt.u));
5831
5832 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
5833 {
5834 /** @todo NSTVMX: Virtual-NMIs doesn't affect NMI blocking in the normal sense.
5835 * We probably need a different force flag for virtual-NMI
5836 * pending/blocking. */
5837 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI));
5838 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
5839 }
5840 else
5841 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
5842
5843 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5844 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
5845 else
5846 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
5847
5848 /* SMI blocking is irrelevant. We don't support SMIs yet. */
5849 }
5850
5851 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
5852 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
5853
5854 /* VPID is irrelevant. We don't support VPID yet. */
5855
5856 /* Clear address-range monitoring. */
5857 EMMonitorWaitClear(pVCpu);
5858}
5859
5860
5861/**
5862 * Loads the guest-state as part of VM-entry.
5863 *
5864 * @returns VBox status code.
5865 * @param pVCpu The cross context virtual CPU structure.
5866 * @param pszInstr The VMX instruction name (for logging purposes).
5867 *
5868 * @remarks This must be done after all the necessary steps prior to loading of
5869 * guest-state (e.g. checking various VMCS state).
5870 */
5871IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
5872{
5873 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
5874 iemVmxVmentryLoadGuestSegRegs(pVCpu);
5875
5876 /*
5877 * Load guest RIP, RSP and RFLAGS.
5878 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
5879 */
5880 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5881 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
5882 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
5883 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
5884
5885 /* Initialize the PAUSE-loop controls as part of VM-entry. */
5886 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
5887 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
5888
5889 iemVmxVmentryLoadGuestNonRegState(pVCpu);
5890
5891 NOREF(pszInstr);
5892 return VINF_SUCCESS;
5893}
5894
5895
5896/**
5897 * Set up the VMX-preemption timer.
5898 *
5899 * @param pVCpu The cross context virtual CPU structure.
5900 * @param pszInstr The VMX instruction name (for logging purposes).
5901 */
5902IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
5903{
5904 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5905 Assert(pVmcs);
5906 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
5907 {
5908 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
5909 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
5910 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
5911
5912 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
5913 }
5914 else
5915 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
5916
5917 NOREF(pszInstr);
5918}
5919
5920
5921/**
5922 * Performs event injection (if any) as part of VM-entry.
5923 *
5924 * @param pVCpu The cross context virtual CPU structure.
5925 * @param pszInstr The VMX instruction name (for logging purposes).
5926 */
5927IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
5928{
5929 /*
5930 * Inject events.
5931 * See Intel spec. 26.5 "Event Injection".
5932 */
5933 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5934 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
5935 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5936 {
5937 /*
5938 * The event that is going to be made pending for injection is not subject to VMX intercepts,
5939 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
5940 * of the current event -are- subject to intercepts, hence this flag will be flipped during
5941 * the actually delivery of this event.
5942 */
5943 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = false;
5944
5945 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
5946 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
5947 {
5948 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
5949 VMCPU_FF_SET(pVCpu, VMCPU_FF_MTF);
5950 return VINF_SUCCESS;
5951 }
5952
5953 int rc = HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
5954 pVCpu->cpum.GstCtx.cr2);
5955 AssertRCReturn(rc, rc);
5956 }
5957
5958 NOREF(pszInstr);
5959 return VINF_SUCCESS;
5960}
5961
5962
5963/**
5964 * VMLAUNCH/VMRESUME instruction execution worker.
5965 *
5966 * @returns Strict VBox status code.
5967 * @param pVCpu The cross context virtual CPU structure.
5968 * @param cbInstr The instruction length in bytes.
5969 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
5970 * VMXINSTRID_VMRESUME).
5971 * @param pExitInfo Pointer to the VM-exit instruction information struct.
5972 * Optional, can be NULL.
5973 *
5974 * @remarks Common VMX instruction checks are already expected to by the caller,
5975 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
5976 */
5977IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId, PCVMXVEXITINFO pExitInfo)
5978{
5979 Assert( uInstrId == VMXINSTRID_VMLAUNCH
5980 || uInstrId == VMXINSTRID_VMRESUME);
5981 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
5982
5983 /* Nested-guest intercept. */
5984 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5985 {
5986 if (pExitInfo)
5987 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
5988 uint32_t const uExitReason = uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH;
5989 return iemVmxVmexitInstrNeedsInfo(pVCpu, uExitReason, uInstrId, cbInstr);
5990 }
5991
5992 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
5993
5994 /* CPL. */
5995 if (pVCpu->iem.s.uCpl > 0)
5996 {
5997 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
5998 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
5999 return iemRaiseGeneralProtectionFault0(pVCpu);
6000 }
6001
6002 /* Current VMCS valid. */
6003 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6004 {
6005 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6006 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
6007 iemVmxVmFailInvalid(pVCpu);
6008 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6009 return VINF_SUCCESS;
6010 }
6011
6012 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
6013 * use block-by-STI here which is not quite correct. */
6014 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
6015 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
6016 {
6017 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
6018 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
6019 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
6020 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6021 return VINF_SUCCESS;
6022 }
6023
6024 if (uInstrId == VMXINSTRID_VMLAUNCH)
6025 {
6026 /* VMLAUNCH with non-clear VMCS. */
6027 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
6028 { /* likely */ }
6029 else
6030 {
6031 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
6032 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
6033 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
6034 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6035 return VINF_SUCCESS;
6036 }
6037 }
6038 else
6039 {
6040 /* VMRESUME with non-launched VMCS. */
6041 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
6042 { /* likely */ }
6043 else
6044 {
6045 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
6046 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
6047 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
6048 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6049 return VINF_SUCCESS;
6050 }
6051 }
6052
6053 /*
6054 * Load the current VMCS.
6055 */
6056 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6057 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
6058 IEM_VMX_GET_CURRENT_VMCS(pVCpu), VMX_V_VMCS_SIZE);
6059 if (RT_FAILURE(rc))
6060 {
6061 Log(("%s: Failed to read VMCS at %#RGp, rc=%Rrc\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu), rc));
6062 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrReadPhys;
6063 return rc;
6064 }
6065
6066 /*
6067 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
6068 * while entering VMX non-root mode. We do some of this while checking VM-execution
6069 * controls. The guest hypervisor should not make assumptions and cannot expect
6070 * predictable behavior if changes to these structures are made in guest memory while
6071 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
6072 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
6073 *
6074 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6075 */
6076 rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
6077 if (RT_SUCCESS(rc))
6078 {
6079 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
6080 if (RT_SUCCESS(rc))
6081 {
6082 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
6083 if (RT_SUCCESS(rc))
6084 {
6085 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
6086 if (RT_SUCCESS(rc))
6087 {
6088 /* Save the guest force-flags as VM-exits can occur from this point on. */
6089 iemVmxVmentrySaveForceFlags(pVCpu);
6090
6091 /* Initialize the VM-exit qualification field as it MBZ for VM-exits where it isn't specified. */
6092 iemVmxVmcsSetExitQual(pVCpu, 0);
6093
6094 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
6095 if (RT_SUCCESS(rc))
6096 {
6097 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
6098 if (RT_SUCCESS(rc))
6099 {
6100 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
6101 if (RT_SUCCESS(rc))
6102 {
6103 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
6104
6105 /* VMLAUNCH instruction must update the VMCS launch state. */
6106 if (uInstrId == VMXINSTRID_VMLAUNCH)
6107 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
6108
6109 /* Perform the VMX transition (PGM updates). */
6110 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
6111 if (rcStrict == VINF_SUCCESS)
6112 { /* likely */ }
6113 else if (RT_SUCCESS(rcStrict))
6114 {
6115 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
6116 VBOXSTRICTRC_VAL(rcStrict)));
6117 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6118 }
6119 else
6120 {
6121 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
6122 return rcStrict;
6123 }
6124
6125 /* We've now entered nested-guest execution. */
6126 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
6127
6128 /*
6129 * The priority of potential VM-exits during VM-entry is important.
6130 * The priorities are listed from highest to lowest as follows:
6131 *
6132 * 1. Debug exceptions.
6133 * 2. VMX-preemption timer.
6134 * 3. NMI-window exit.
6135 * 4. NMI injection.
6136 * 5. Interrupt-window exit.
6137 * 6. Interrupt injection.
6138 * 7. MTF exit.
6139 */
6140
6141 /* Setup the VMX-preemption timer. */
6142 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
6143
6144 /* Now that we've switched page tables, we can inject events if any. */
6145 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
6146
6147 return VINF_SUCCESS;
6148 }
6149 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
6150 }
6151 }
6152 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
6153 }
6154
6155 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
6156 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6157 return VINF_SUCCESS;
6158 }
6159 }
6160 }
6161
6162 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
6163 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6164 return VINF_SUCCESS;
6165}
6166
6167
6168/**
6169 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
6170 * (causes a VM-exit) or not.
6171 *
6172 * @returns @c true if the instruction is intercepted, @c false otherwise.
6173 * @param pVCpu The cross context virtual CPU structure.
6174 * @param uExitReason The VM-exit exit reason (VMX_EXIT_RDMSR or
6175 * VMX_EXIT_WRMSR).
6176 * @param idMsr The MSR.
6177 */
6178IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
6179{
6180 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6181 Assert( uExitReason == VMX_EXIT_RDMSR
6182 || uExitReason == VMX_EXIT_WRMSR);
6183
6184 /* Consult the MSR bitmap if the feature is supported. */
6185 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6186 Assert(pVmcs);
6187 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6188 {
6189 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6190 if (uExitReason == VMX_EXIT_RDMSR)
6191 {
6192 VMXMSREXITREAD enmRead;
6193 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
6194 NULL /* penmWrite */);
6195 AssertRC(rc);
6196 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
6197 return true;
6198 }
6199 else
6200 {
6201 VMXMSREXITWRITE enmWrite;
6202 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
6203 &enmWrite);
6204 AssertRC(rc);
6205 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
6206 return true;
6207 }
6208 return false;
6209 }
6210
6211 /* Without MSR bitmaps, all MSR accesses are intercepted. */
6212 return true;
6213}
6214
6215
6216/**
6217 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
6218 * intercepted (causes a VM-exit) or not.
6219 *
6220 * @returns @c true if the instruction is intercepted, @c false otherwise.
6221 * @param pVCpu The cross context virtual CPU structure.
6222 * @param u64FieldEnc The VMCS field encoding.
6223 * @param uExitReason The VM-exit exit reason (VMX_EXIT_VMREAD or
6224 * VMX_EXIT_VMREAD).
6225 */
6226IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
6227{
6228 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6229 Assert( uExitReason == VMX_EXIT_VMREAD
6230 || uExitReason == VMX_EXIT_VMWRITE);
6231
6232 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
6233 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
6234 return true;
6235
6236 /*
6237 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
6238 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
6239 */
6240 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
6241 return true;
6242
6243 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
6244 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
6245 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6246 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6247 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
6248 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
6249 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
6250 pbBitmap += (u32FieldEnc >> 3);
6251 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
6252 return true;
6253
6254 return false;
6255}
6256
6257
6258/**
6259 * VMREAD common (memory/register) instruction execution worker
6260 *
6261 * @returns Strict VBox status code.
6262 * @param pVCpu The cross context virtual CPU structure.
6263 * @param cbInstr The instruction length in bytes.
6264 * @param pu64Dst Where to write the VMCS value (only updated when
6265 * VINF_SUCCESS is returned).
6266 * @param u64FieldEnc The VMCS field encoding.
6267 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6268 * be NULL.
6269 */
6270IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6271 PCVMXVEXITINFO pExitInfo)
6272{
6273 /* Nested-guest intercept. */
6274 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6275 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
6276 {
6277 if (pExitInfo)
6278 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6279 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
6280 }
6281
6282 /* CPL. */
6283 if (pVCpu->iem.s.uCpl > 0)
6284 {
6285 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6286 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
6287 return iemRaiseGeneralProtectionFault0(pVCpu);
6288 }
6289
6290 /* VMCS pointer in root mode. */
6291 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6292 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6293 {
6294 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6295 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
6296 iemVmxVmFailInvalid(pVCpu);
6297 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6298 return VINF_SUCCESS;
6299 }
6300
6301 /* VMCS-link pointer in non-root mode. */
6302 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6303 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6304 {
6305 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6306 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
6307 iemVmxVmFailInvalid(pVCpu);
6308 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6309 return VINF_SUCCESS;
6310 }
6311
6312 /* Supported VMCS field. */
6313 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6314 {
6315 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6316 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
6317 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
6318 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6319 return VINF_SUCCESS;
6320 }
6321
6322 /*
6323 * Setup reading from the current or shadow VMCS.
6324 */
6325 uint8_t *pbVmcs;
6326 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6327 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6328 else
6329 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6330 Assert(pbVmcs);
6331
6332 VMXVMCSFIELDENC FieldEnc;
6333 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6334 uint8_t const uWidth = FieldEnc.n.u2Width;
6335 uint8_t const uType = FieldEnc.n.u2Type;
6336 uint8_t const uWidthType = (uWidth << 2) | uType;
6337 uint8_t const uIndex = FieldEnc.n.u8Index;
6338 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6339 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6340
6341 /*
6342 * Read the VMCS component based on the field's effective width.
6343 *
6344 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6345 * indicates high bits (little endian).
6346 *
6347 * Note! The caller is responsible to trim the result and update registers
6348 * or memory locations are required. Here we just zero-extend to the largest
6349 * type (i.e. 64-bits).
6350 */
6351 uint8_t *pbField = pbVmcs + offField;
6352 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6353 switch (uEffWidth)
6354 {
6355 case VMX_VMCS_ENC_WIDTH_64BIT:
6356 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
6357 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
6358 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
6359 }
6360 return VINF_SUCCESS;
6361}
6362
6363
6364/**
6365 * VMREAD (64-bit register) instruction execution worker.
6366 *
6367 * @returns Strict VBox status code.
6368 * @param pVCpu The cross context virtual CPU structure.
6369 * @param cbInstr The instruction length in bytes.
6370 * @param pu64Dst Where to store the VMCS field's value.
6371 * @param u64FieldEnc The VMCS field encoding.
6372 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6373 * be NULL.
6374 */
6375IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6376 PCVMXVEXITINFO pExitInfo)
6377{
6378 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
6379 if (rcStrict == VINF_SUCCESS)
6380 {
6381 iemVmxVmreadSuccess(pVCpu, cbInstr);
6382 return VINF_SUCCESS;
6383 }
6384
6385 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6386 return rcStrict;
6387}
6388
6389
6390/**
6391 * VMREAD (32-bit register) instruction execution worker.
6392 *
6393 * @returns Strict VBox status code.
6394 * @param pVCpu The cross context virtual CPU structure.
6395 * @param cbInstr The instruction length in bytes.
6396 * @param pu32Dst Where to store the VMCS field's value.
6397 * @param u32FieldEnc The VMCS field encoding.
6398 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6399 * be NULL.
6400 */
6401IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
6402 PCVMXVEXITINFO pExitInfo)
6403{
6404 uint64_t u64Dst;
6405 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
6406 if (rcStrict == VINF_SUCCESS)
6407 {
6408 *pu32Dst = u64Dst;
6409 iemVmxVmreadSuccess(pVCpu, cbInstr);
6410 return VINF_SUCCESS;
6411 }
6412
6413 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6414 return rcStrict;
6415}
6416
6417
6418/**
6419 * VMREAD (memory) instruction execution worker.
6420 *
6421 * @returns Strict VBox status code.
6422 * @param pVCpu The cross context virtual CPU structure.
6423 * @param cbInstr The instruction length in bytes.
6424 * @param iEffSeg The effective segment register to use with @a u64Val.
6425 * Pass UINT8_MAX if it is a register access.
6426 * @param enmEffAddrMode The effective addressing mode (only used with memory
6427 * operand).
6428 * @param GCPtrDst The guest linear address to store the VMCS field's
6429 * value.
6430 * @param u64FieldEnc The VMCS field encoding.
6431 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6432 * be NULL.
6433 */
6434IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
6435 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6436{
6437 uint64_t u64Dst;
6438 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
6439 if (rcStrict == VINF_SUCCESS)
6440 {
6441 /*
6442 * Write the VMCS field's value to the location specified in guest-memory.
6443 *
6444 * The pointer size depends on the address size (address-size prefix allowed).
6445 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
6446 */
6447 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6448 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6449 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
6450
6451 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6452 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6453 else
6454 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6455 if (rcStrict == VINF_SUCCESS)
6456 {
6457 iemVmxVmreadSuccess(pVCpu, cbInstr);
6458 return VINF_SUCCESS;
6459 }
6460
6461 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
6462 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
6463 return rcStrict;
6464 }
6465
6466 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6467 return rcStrict;
6468}
6469
6470
6471/**
6472 * VMWRITE instruction execution worker.
6473 *
6474 * @returns Strict VBox status code.
6475 * @param pVCpu The cross context virtual CPU structure.
6476 * @param cbInstr The instruction length in bytes.
6477 * @param iEffSeg The effective segment register to use with @a u64Val.
6478 * Pass UINT8_MAX if it is a register access.
6479 * @param enmEffAddrMode The effective addressing mode (only used with memory
6480 * operand).
6481 * @param u64Val The value to write (or guest linear address to the
6482 * value), @a iEffSeg will indicate if it's a memory
6483 * operand.
6484 * @param u64FieldEnc The VMCS field encoding.
6485 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6486 * be NULL.
6487 */
6488IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
6489 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6490{
6491 /* Nested-guest intercept. */
6492 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6493 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
6494 {
6495 if (pExitInfo)
6496 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6497 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
6498 }
6499
6500 /* CPL. */
6501 if (pVCpu->iem.s.uCpl > 0)
6502 {
6503 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
6505 return iemRaiseGeneralProtectionFault0(pVCpu);
6506 }
6507
6508 /* VMCS pointer in root mode. */
6509 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6510 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6511 {
6512 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6513 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
6514 iemVmxVmFailInvalid(pVCpu);
6515 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6516 return VINF_SUCCESS;
6517 }
6518
6519 /* VMCS-link pointer in non-root mode. */
6520 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6521 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6522 {
6523 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
6525 iemVmxVmFailInvalid(pVCpu);
6526 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6527 return VINF_SUCCESS;
6528 }
6529
6530 /* If the VMWRITE instruction references memory, access the specified memory operand. */
6531 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
6532 if (!fIsRegOperand)
6533 {
6534 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6535 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6536 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
6537
6538 /* Read the value from the specified guest memory location. */
6539 VBOXSTRICTRC rcStrict;
6540 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6541 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
6542 else
6543 {
6544 uint32_t u32Val;
6545 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
6546 u64Val = u32Val;
6547 }
6548 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6549 {
6550 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
6551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
6552 return rcStrict;
6553 }
6554 }
6555 else
6556 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
6557
6558 /* Supported VMCS field. */
6559 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6560 {
6561 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
6563 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
6564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6565 return VINF_SUCCESS;
6566 }
6567
6568 /* Read-only VMCS field. */
6569 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
6570 if ( fIsFieldReadOnly
6571 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
6572 {
6573 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
6574 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
6575 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
6576 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6577 return VINF_SUCCESS;
6578 }
6579
6580 /*
6581 * Setup writing to the current or shadow VMCS.
6582 */
6583 uint8_t *pbVmcs;
6584 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6585 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6586 else
6587 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6588 Assert(pbVmcs);
6589
6590 VMXVMCSFIELDENC FieldEnc;
6591 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6592 uint8_t const uWidth = FieldEnc.n.u2Width;
6593 uint8_t const uType = FieldEnc.n.u2Type;
6594 uint8_t const uWidthType = (uWidth << 2) | uType;
6595 uint8_t const uIndex = FieldEnc.n.u8Index;
6596 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6597 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6598
6599 /*
6600 * Write the VMCS component based on the field's effective width.
6601 *
6602 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6603 * indicates high bits (little endian).
6604 */
6605 uint8_t *pbField = pbVmcs + offField;
6606 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6607 switch (uEffWidth)
6608 {
6609 case VMX_VMCS_ENC_WIDTH_64BIT:
6610 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
6611 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
6612 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
6613 }
6614
6615 iemVmxVmSucceed(pVCpu);
6616 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6617 return VINF_SUCCESS;
6618}
6619
6620
6621/**
6622 * VMCLEAR instruction execution worker.
6623 *
6624 * @returns Strict VBox status code.
6625 * @param pVCpu The cross context virtual CPU structure.
6626 * @param cbInstr The instruction length in bytes.
6627 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6628 * @param GCPtrVmcs The linear address of the VMCS pointer.
6629 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6630 * be NULL.
6631 *
6632 * @remarks Common VMX instruction checks are already expected to by the caller,
6633 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6634 */
6635IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6636 PCVMXVEXITINFO pExitInfo)
6637{
6638 /* Nested-guest intercept. */
6639 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6640 {
6641 if (pExitInfo)
6642 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6643 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
6644 }
6645
6646 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6647
6648 /* CPL. */
6649 if (pVCpu->iem.s.uCpl > 0)
6650 {
6651 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6652 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
6653 return iemRaiseGeneralProtectionFault0(pVCpu);
6654 }
6655
6656 /* Get the VMCS pointer from the location specified by the source memory operand. */
6657 RTGCPHYS GCPhysVmcs;
6658 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6659 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6660 {
6661 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6662 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
6663 return rcStrict;
6664 }
6665
6666 /* VMCS pointer alignment. */
6667 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6668 {
6669 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
6670 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
6671 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6672 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6673 return VINF_SUCCESS;
6674 }
6675
6676 /* VMCS physical-address width limits. */
6677 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6678 {
6679 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
6681 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6683 return VINF_SUCCESS;
6684 }
6685
6686 /* VMCS is not the VMXON region. */
6687 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6688 {
6689 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6690 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
6691 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
6692 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6693 return VINF_SUCCESS;
6694 }
6695
6696 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6697 restriction imposed by our implementation. */
6698 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6699 {
6700 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
6701 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
6702 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6704 return VINF_SUCCESS;
6705 }
6706
6707 /*
6708 * VMCLEAR allows committing and clearing any valid VMCS pointer.
6709 *
6710 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
6711 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
6712 * to 'clear'.
6713 */
6714 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
6715 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
6716 {
6717 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
6718 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6719 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
6720 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6721 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
6722 }
6723 else
6724 {
6725 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPtrVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
6726 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
6727 }
6728
6729 iemVmxVmSucceed(pVCpu);
6730 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6731 return rcStrict;
6732}
6733
6734
6735/**
6736 * VMPTRST instruction execution worker.
6737 *
6738 * @returns Strict VBox status code.
6739 * @param pVCpu The cross context virtual CPU structure.
6740 * @param cbInstr The instruction length in bytes.
6741 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6742 * @param GCPtrVmcs The linear address of where to store the current VMCS
6743 * pointer.
6744 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6745 * be NULL.
6746 *
6747 * @remarks Common VMX instruction checks are already expected to by the caller,
6748 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6749 */
6750IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6751 PCVMXVEXITINFO pExitInfo)
6752{
6753 /* Nested-guest intercept. */
6754 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6755 {
6756 if (pExitInfo)
6757 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6758 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
6759 }
6760
6761 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6762
6763 /* CPL. */
6764 if (pVCpu->iem.s.uCpl > 0)
6765 {
6766 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6767 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
6768 return iemRaiseGeneralProtectionFault0(pVCpu);
6769 }
6770
6771 /* Set the VMCS pointer to the location specified by the destination memory operand. */
6772 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
6773 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
6774 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6775 {
6776 iemVmxVmSucceed(pVCpu);
6777 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6778 return rcStrict;
6779 }
6780
6781 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
6783 return rcStrict;
6784}
6785
6786
6787/**
6788 * VMPTRLD instruction execution worker.
6789 *
6790 * @returns Strict VBox status code.
6791 * @param pVCpu The cross context virtual CPU structure.
6792 * @param cbInstr The instruction length in bytes.
6793 * @param GCPtrVmcs The linear address of the current VMCS pointer.
6794 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6795 * be NULL.
6796 *
6797 * @remarks Common VMX instruction checks are already expected to by the caller,
6798 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6799 */
6800IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6801 PCVMXVEXITINFO pExitInfo)
6802{
6803 /* Nested-guest intercept. */
6804 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6805 {
6806 if (pExitInfo)
6807 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6808 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
6809 }
6810
6811 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6812
6813 /* CPL. */
6814 if (pVCpu->iem.s.uCpl > 0)
6815 {
6816 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6817 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
6818 return iemRaiseGeneralProtectionFault0(pVCpu);
6819 }
6820
6821 /* Get the VMCS pointer from the location specified by the source memory operand. */
6822 RTGCPHYS GCPhysVmcs;
6823 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6824 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6825 {
6826 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
6828 return rcStrict;
6829 }
6830
6831 /* VMCS pointer alignment. */
6832 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6833 {
6834 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
6835 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
6836 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6837 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6838 return VINF_SUCCESS;
6839 }
6840
6841 /* VMCS physical-address width limits. */
6842 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6843 {
6844 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
6846 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6847 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6848 return VINF_SUCCESS;
6849 }
6850
6851 /* VMCS is not the VMXON region. */
6852 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6853 {
6854 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6855 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
6856 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
6857 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6858 return VINF_SUCCESS;
6859 }
6860
6861 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6862 restriction imposed by our implementation. */
6863 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6864 {
6865 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
6866 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
6867 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6868 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6869 return VINF_SUCCESS;
6870 }
6871
6872 /* Read the VMCS revision ID from the VMCS. */
6873 VMXVMCSREVID VmcsRevId;
6874 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
6875 if (RT_FAILURE(rc))
6876 {
6877 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
6878 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
6879 return rc;
6880 }
6881
6882 /* Verify the VMCS revision specified by the guest matches what we reported to the guest,
6883 also check VMCS shadowing feature. */
6884 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
6885 || ( VmcsRevId.n.fIsShadowVmcs
6886 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
6887 {
6888 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
6889 {
6890 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFail()\n", VMX_V_VMCS_REVISION_ID,
6891 VmcsRevId.n.u31RevisionId));
6892 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
6893 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6894 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6895 return VINF_SUCCESS;
6896 }
6897
6898 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
6899 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
6900 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6901 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6902 return VINF_SUCCESS;
6903 }
6904
6905 /*
6906 * We only maintain only the current VMCS in our virtual CPU context (CPUMCTX). Therefore,
6907 * VMPTRLD shall always flush any existing current VMCS back to guest memory before loading
6908 * a new VMCS as current.
6909 */
6910 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
6911 {
6912 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6913 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
6914 }
6915
6916 iemVmxVmSucceed(pVCpu);
6917 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6918 return VINF_SUCCESS;
6919}
6920
6921
6922/**
6923 * VMXON instruction execution worker.
6924 *
6925 * @returns Strict VBox status code.
6926 * @param pVCpu The cross context virtual CPU structure.
6927 * @param cbInstr The instruction length in bytes.
6928 * @param iEffSeg The effective segment register to use with @a
6929 * GCPtrVmxon.
6930 * @param GCPtrVmxon The linear address of the VMXON pointer.
6931 * @param pExitInfo Pointer to the VM-exit instruction information struct.
6932 * Optional, can be NULL.
6933 *
6934 * @remarks Common VMX instruction checks are already expected to by the caller,
6935 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6936 */
6937IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
6938 PCVMXVEXITINFO pExitInfo)
6939{
6940#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
6941 RT_NOREF5(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
6942 return VINF_EM_RAW_EMULATE_INSTR;
6943#else
6944 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
6945 {
6946 /* CPL. */
6947 if (pVCpu->iem.s.uCpl > 0)
6948 {
6949 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6950 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
6951 return iemRaiseGeneralProtectionFault0(pVCpu);
6952 }
6953
6954 /* A20M (A20 Masked) mode. */
6955 if (!PGMPhysIsA20Enabled(pVCpu))
6956 {
6957 Log(("vmxon: A20M mode -> #GP(0)\n"));
6958 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
6959 return iemRaiseGeneralProtectionFault0(pVCpu);
6960 }
6961
6962 /* CR0. */
6963 {
6964 /* CR0 MB1 bits. */
6965 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
6966 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
6967 {
6968 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
6969 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
6970 return iemRaiseGeneralProtectionFault0(pVCpu);
6971 }
6972
6973 /* CR0 MBZ bits. */
6974 uint64_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
6975 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
6976 {
6977 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
6978 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
6979 return iemRaiseGeneralProtectionFault0(pVCpu);
6980 }
6981 }
6982
6983 /* CR4. */
6984 {
6985 /* CR4 MB1 bits. */
6986 uint64_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
6987 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
6988 {
6989 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
6990 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
6991 return iemRaiseGeneralProtectionFault0(pVCpu);
6992 }
6993
6994 /* CR4 MBZ bits. */
6995 uint64_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
6996 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
6997 {
6998 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
6999 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
7000 return iemRaiseGeneralProtectionFault0(pVCpu);
7001 }
7002 }
7003
7004 /* Feature control MSR's LOCK and VMXON bits. */
7005 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatureControl(pVCpu);
7006 if (!(uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON)))
7007 {
7008 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
7009 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
7010 return iemRaiseGeneralProtectionFault0(pVCpu);
7011 }
7012
7013 /* Get the VMXON pointer from the location specified by the source memory operand. */
7014 RTGCPHYS GCPhysVmxon;
7015 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
7016 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7017 {
7018 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
7019 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
7020 return rcStrict;
7021 }
7022
7023 /* VMXON region pointer alignment. */
7024 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
7025 {
7026 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
7027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
7028 iemVmxVmFailInvalid(pVCpu);
7029 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7030 return VINF_SUCCESS;
7031 }
7032
7033 /* VMXON physical-address width limits. */
7034 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7035 {
7036 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
7037 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
7038 iemVmxVmFailInvalid(pVCpu);
7039 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7040 return VINF_SUCCESS;
7041 }
7042
7043 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
7044 restriction imposed by our implementation. */
7045 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
7046 {
7047 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
7048 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
7049 iemVmxVmFailInvalid(pVCpu);
7050 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7051 return VINF_SUCCESS;
7052 }
7053
7054 /* Read the VMCS revision ID from the VMXON region. */
7055 VMXVMCSREVID VmcsRevId;
7056 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
7057 if (RT_FAILURE(rc))
7058 {
7059 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
7060 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
7061 return rc;
7062 }
7063
7064 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7065 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
7066 {
7067 /* Revision ID mismatch. */
7068 if (!VmcsRevId.n.fIsShadowVmcs)
7069 {
7070 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
7071 VmcsRevId.n.u31RevisionId));
7072 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
7073 iemVmxVmFailInvalid(pVCpu);
7074 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7075 return VINF_SUCCESS;
7076 }
7077
7078 /* Shadow VMCS disallowed. */
7079 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
7080 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
7081 iemVmxVmFailInvalid(pVCpu);
7082 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7083 return VINF_SUCCESS;
7084 }
7085
7086 /*
7087 * Record that we're in VMX operation, block INIT, block and disable A20M.
7088 */
7089 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
7090 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7091 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
7092
7093 /* Clear address-range monitoring. */
7094 EMMonitorWaitClear(pVCpu);
7095 /** @todo NSTVMX: Intel PT. */
7096
7097 iemVmxVmSucceed(pVCpu);
7098 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7099# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7100 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7101# else
7102 return VINF_SUCCESS;
7103# endif
7104 }
7105 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7106 {
7107 /* Nested-guest intercept. */
7108 if (pExitInfo)
7109 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7110 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
7111 }
7112
7113 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7114
7115 /* CPL. */
7116 if (pVCpu->iem.s.uCpl > 0)
7117 {
7118 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7119 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
7120 return iemRaiseGeneralProtectionFault0(pVCpu);
7121 }
7122
7123 /* VMXON when already in VMX root mode. */
7124 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
7125 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
7126 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7127 return VINF_SUCCESS;
7128#endif
7129}
7130
7131
7132/**
7133 * Implements 'VMXOFF'.
7134 *
7135 * @remarks Common VMX instruction checks are already expected to by the caller,
7136 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7137 */
7138IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
7139{
7140# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7141 RT_NOREF2(pVCpu, cbInstr);
7142 return VINF_EM_RAW_EMULATE_INSTR;
7143# else
7144 /* Nested-guest intercept. */
7145 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7146 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
7147
7148 /* CPL. */
7149 if (pVCpu->iem.s.uCpl > 0)
7150 {
7151 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7152 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
7153 return iemRaiseGeneralProtectionFault0(pVCpu);
7154 }
7155
7156 /* Dual monitor treatment of SMIs and SMM. */
7157 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
7158 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
7159 {
7160 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
7161 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7162 return VINF_SUCCESS;
7163 }
7164
7165 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
7166 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
7167 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
7168
7169 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
7170 { /** @todo NSTVMX: Unblock SMI. */ }
7171
7172 EMMonitorWaitClear(pVCpu);
7173 /** @todo NSTVMX: Unblock and enable A20M. */
7174
7175 iemVmxVmSucceed(pVCpu);
7176 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7177# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7178 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
7179# else
7180 return VINF_SUCCESS;
7181# endif
7182# endif
7183}
7184
7185
7186/**
7187 * Implements 'VMXON'.
7188 */
7189IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
7190{
7191 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
7192}
7193
7194
7195/**
7196 * Implements 'VMLAUNCH'.
7197 */
7198IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
7199{
7200 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH, NULL /* pExitInfo */);
7201}
7202
7203
7204/**
7205 * Implements 'VMRESUME'.
7206 */
7207IEM_CIMPL_DEF_0(iemCImpl_vmresume)
7208{
7209 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME, NULL /* pExitInfo */);
7210}
7211
7212
7213/**
7214 * Implements 'VMPTRLD'.
7215 */
7216IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7217{
7218 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7219}
7220
7221
7222/**
7223 * Implements 'VMPTRST'.
7224 */
7225IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7226{
7227 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7228}
7229
7230
7231/**
7232 * Implements 'VMCLEAR'.
7233 */
7234IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7235{
7236 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7237}
7238
7239
7240/**
7241 * Implements 'VMWRITE' register.
7242 */
7243IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
7244{
7245 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
7246 NULL /* pExitInfo */);
7247}
7248
7249
7250/**
7251 * Implements 'VMWRITE' memory.
7252 */
7253IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
7254{
7255 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
7256}
7257
7258
7259/**
7260 * Implements 'VMREAD' 64-bit register.
7261 */
7262IEM_CIMPL_DEF_2(iemCImpl_vmread64_reg, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
7263{
7264 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
7265}
7266
7267
7268/**
7269 * Implements 'VMREAD' 32-bit register.
7270 */
7271IEM_CIMPL_DEF_2(iemCImpl_vmread32_reg, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
7272{
7273 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
7274}
7275
7276
7277/**
7278 * Implements 'VMREAD' memory.
7279 */
7280IEM_CIMPL_DEF_4(iemCImpl_vmread_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
7281{
7282 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
7283}
7284
7285
7286/**
7287 * Implements VMX's implementation of PAUSE.
7288 */
7289IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
7290{
7291 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7292 {
7293 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
7294 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7295 return rcStrict;
7296 }
7297
7298 /*
7299 * Outside VMX non-root operation or if the PAUSE instruction does not cause
7300 * a VM-exit, the instruction operates normally.
7301 */
7302 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7303 return VINF_SUCCESS;
7304}
7305
7306#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
7307
7308
7309/**
7310 * Implements 'VMCALL'.
7311 */
7312IEM_CIMPL_DEF_0(iemCImpl_vmcall)
7313{
7314#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7315 /* Nested-guest intercept. */
7316 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7317 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
7318#endif
7319
7320 /* Join forces with vmmcall. */
7321 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
7322}
7323
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