VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 76763

Last change on this file since 76763 was 76743, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Fix typos (duplicate GuestEs field in the VMCS map, local LDTR/TR limit/attribute mixup, read/store strictly only the number of MSRs specified in the VMCS, after limit checks ofc, rather than the entire 2 pages every time). Reading the second page could easily lead to a page-fault and therefore is wrong.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 339.2 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp.h 76743 2019-01-09 16:28:43Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 return EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 } while (0)
172
173# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE(a_pVCpu, a_pszLogPrefix) \
174 do { \
175 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
176 EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
177 } while (0)
178# else
179# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix) do { return VINF_SUCCESS; } while (0)
180# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE(a_pVCpu, a_pszLogPrefix) do { } while (0)
181# endif
182
183
184/*********************************************************************************************************************************
185* Global Variables *
186*********************************************************************************************************************************/
187/** @todo NSTVMX: The following VM-exit intercepts are pending:
188 * VMX_EXIT_IO_SMI
189 * VMX_EXIT_SMI
190 * VMX_EXIT_INT_WINDOW
191 * VMX_EXIT_NMI_WINDOW
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MTF
195 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
196 * VMX_EXIT_ERR_MACHINE_CHECK
197 * VMX_EXIT_TPR_BELOW_THRESHOLD
198 * VMX_EXIT_APIC_ACCESS
199 * VMX_EXIT_VIRTUALIZED_EOI
200 * VMX_EXIT_EPT_VIOLATION
201 * VMX_EXIT_EPT_MISCONFIG
202 * VMX_EXIT_INVEPT
203 * VMX_EXIT_PREEMPT_TIMER
204 * VMX_EXIT_INVVPID
205 * VMX_EXIT_APIC_WRITE
206 * VMX_EXIT_RDRAND
207 * VMX_EXIT_VMFUNC
208 * VMX_EXIT_ENCLS
209 * VMX_EXIT_RDSEED
210 * VMX_EXIT_PML_FULL
211 * VMX_EXIT_XSAVES
212 * VMX_EXIT_XRSTORS
213 */
214/**
215 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
216 *
217 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
218 * second dimension is the Index, see VMXVMCSFIELDENC.
219 */
220uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
221{
222 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
223 {
224 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
225 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
226 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
227 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
232 {
233 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
236 /* 24-25 */ UINT16_MAX, UINT16_MAX
237 },
238 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
239 {
240 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
241 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
242 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
243 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
244 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
245 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
246 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
247 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
248 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
249 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
250 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
251 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
252 },
253 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
254 {
255 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
256 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
257 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
258 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
259 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
260 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
261 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
262 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
263 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
264 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
265 },
266 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
267 {
268 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
269 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
270 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
271 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
272 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
273 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
274 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
275 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
276 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
277 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
278 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
279 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
280 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
281 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
282 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
283 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
284 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
285 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
286 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
287 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
288 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
289 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
290 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
291 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
292 /* 24 */ UINT16_MAX,
293 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
294 },
295 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
296 {
297 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
298 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
301 /* 25 */ UINT16_MAX
302 },
303 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
304 {
305 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
306 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
307 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
308 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
309 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
310 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
311 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
312 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
313 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
314 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
315 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
316 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
317 },
318 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
319 {
320 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
321 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
322 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
323 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
324 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
326 },
327 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
328 {
329 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
330 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
331 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
332 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
333 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
334 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
335 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
336 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
337 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
338 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
339 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
340 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
341 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
342 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
343 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
344 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
345 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
346 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
347 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
348 },
349 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
350 {
351 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
352 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
353 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
354 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
355 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
356 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
357 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
358 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
359 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 24-25 */ UINT16_MAX, UINT16_MAX
362 },
363 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
373 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
374 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
375 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
376 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
377 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
378 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
379 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
380 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
381 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
382 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
383 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
384 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
385 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
386 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
387 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
388 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
389 },
390 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
391 {
392 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
393 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
394 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 25 */ UINT16_MAX
397 },
398 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
399 {
400 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
401 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
402 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
403 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
404 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
405 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
406 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
407 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
408 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
410 /* 24-25 */ UINT16_MAX, UINT16_MAX
411 },
412 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
413 {
414 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
415 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
416 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
417 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
418 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
419 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
420 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
422 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
423 },
424 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
425 {
426 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
427 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
428 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
429 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
430 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
431 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
432 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
433 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
434 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
435 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
436 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
437 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
438 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
439 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
440 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
441 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
442 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
443 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
444 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
445 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
446 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
447 },
448 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
449 {
450 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
451 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
452 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
453 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
454 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
455 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
456 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
457 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
458 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
459 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
460 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
461 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
462 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
463 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
464 }
465};
466
467
468/**
469 * Returns whether the given VMCS field is valid and supported by our emulation.
470 *
471 * @param pVCpu The cross context virtual CPU structure.
472 * @param u64FieldEnc The VMCS field encoding.
473 *
474 * @remarks This takes into account the CPU features exposed to the guest.
475 */
476IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
477{
478 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
479 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
480 if (!uFieldEncHi)
481 { /* likely */ }
482 else
483 return false;
484
485 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
486 switch (uFieldEncLo)
487 {
488 /*
489 * 16-bit fields.
490 */
491 /* Control fields. */
492 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
493 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
494 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
495
496 /* Guest-state fields. */
497 case VMX_VMCS16_GUEST_ES_SEL:
498 case VMX_VMCS16_GUEST_CS_SEL:
499 case VMX_VMCS16_GUEST_SS_SEL:
500 case VMX_VMCS16_GUEST_DS_SEL:
501 case VMX_VMCS16_GUEST_FS_SEL:
502 case VMX_VMCS16_GUEST_GS_SEL:
503 case VMX_VMCS16_GUEST_LDTR_SEL:
504 case VMX_VMCS16_GUEST_TR_SEL: return true;
505 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
506 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
507
508 /* Host-state fields. */
509 case VMX_VMCS16_HOST_ES_SEL:
510 case VMX_VMCS16_HOST_CS_SEL:
511 case VMX_VMCS16_HOST_SS_SEL:
512 case VMX_VMCS16_HOST_DS_SEL:
513 case VMX_VMCS16_HOST_FS_SEL:
514 case VMX_VMCS16_HOST_GS_SEL:
515 case VMX_VMCS16_HOST_TR_SEL: return true;
516
517 /*
518 * 64-bit fields.
519 */
520 /* Control fields. */
521 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
522 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
523 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
524 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
525 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
526 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
527 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
528 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
529 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
530 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
531 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
532 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
533 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
534 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
535 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
536 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
537 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
538 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
539 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
540 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
541 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
542 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
543 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
544 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
545 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
546 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
547 case VMX_VMCS64_CTRL_EPTP_FULL:
548 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
549 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
550 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
551 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
552 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
553 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
554 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
555 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
557 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
558 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
559 {
560 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
561 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
562 }
563 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
564 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
565 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
566 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
567 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
568 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
569 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
571 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
573 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
574 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
575
576 /* Read-only data fields. */
577 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
578 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
579
580 /* Guest-state fields. */
581 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
582 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
583 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
584 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
585 case VMX_VMCS64_GUEST_PAT_FULL:
586 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
587 case VMX_VMCS64_GUEST_EFER_FULL:
588 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
589 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
590 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
591 case VMX_VMCS64_GUEST_PDPTE0_FULL:
592 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
593 case VMX_VMCS64_GUEST_PDPTE1_FULL:
594 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
595 case VMX_VMCS64_GUEST_PDPTE2_FULL:
596 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
597 case VMX_VMCS64_GUEST_PDPTE3_FULL:
598 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
599 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
600 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
601
602 /* Host-state fields. */
603 case VMX_VMCS64_HOST_PAT_FULL:
604 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
605 case VMX_VMCS64_HOST_EFER_FULL:
606 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
607 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
608 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
609
610 /*
611 * 32-bit fields.
612 */
613 /* Control fields. */
614 case VMX_VMCS32_CTRL_PIN_EXEC:
615 case VMX_VMCS32_CTRL_PROC_EXEC:
616 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
617 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
618 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
619 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
620 case VMX_VMCS32_CTRL_EXIT:
621 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
622 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
623 case VMX_VMCS32_CTRL_ENTRY:
624 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
625 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
626 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
627 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
628 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
629 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
630 case VMX_VMCS32_CTRL_PLE_GAP:
631 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
632
633 /* Read-only data fields. */
634 case VMX_VMCS32_RO_VM_INSTR_ERROR:
635 case VMX_VMCS32_RO_EXIT_REASON:
636 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
637 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
638 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
639 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
640 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
641 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
642
643 /* Guest-state fields. */
644 case VMX_VMCS32_GUEST_ES_LIMIT:
645 case VMX_VMCS32_GUEST_CS_LIMIT:
646 case VMX_VMCS32_GUEST_SS_LIMIT:
647 case VMX_VMCS32_GUEST_DS_LIMIT:
648 case VMX_VMCS32_GUEST_FS_LIMIT:
649 case VMX_VMCS32_GUEST_GS_LIMIT:
650 case VMX_VMCS32_GUEST_LDTR_LIMIT:
651 case VMX_VMCS32_GUEST_TR_LIMIT:
652 case VMX_VMCS32_GUEST_GDTR_LIMIT:
653 case VMX_VMCS32_GUEST_IDTR_LIMIT:
654 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
655 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
656 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
657 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
658 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
659 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
660 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_INT_STATE:
663 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
664 case VMX_VMCS32_GUEST_SMBASE:
665 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
666 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
667
668 /* Host-state fields. */
669 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
670
671 /*
672 * Natural-width fields.
673 */
674 /* Control fields. */
675 case VMX_VMCS_CTRL_CR0_MASK:
676 case VMX_VMCS_CTRL_CR4_MASK:
677 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
678 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
679 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
680 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
681 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
682 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
683
684 /* Read-only data fields. */
685 case VMX_VMCS_RO_EXIT_QUALIFICATION:
686 case VMX_VMCS_RO_IO_RCX:
687 case VMX_VMCS_RO_IO_RSX:
688 case VMX_VMCS_RO_IO_RDI:
689 case VMX_VMCS_RO_IO_RIP:
690 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
691
692 /* Guest-state fields. */
693 case VMX_VMCS_GUEST_CR0:
694 case VMX_VMCS_GUEST_CR3:
695 case VMX_VMCS_GUEST_CR4:
696 case VMX_VMCS_GUEST_ES_BASE:
697 case VMX_VMCS_GUEST_CS_BASE:
698 case VMX_VMCS_GUEST_SS_BASE:
699 case VMX_VMCS_GUEST_DS_BASE:
700 case VMX_VMCS_GUEST_FS_BASE:
701 case VMX_VMCS_GUEST_GS_BASE:
702 case VMX_VMCS_GUEST_LDTR_BASE:
703 case VMX_VMCS_GUEST_TR_BASE:
704 case VMX_VMCS_GUEST_GDTR_BASE:
705 case VMX_VMCS_GUEST_IDTR_BASE:
706 case VMX_VMCS_GUEST_DR7:
707 case VMX_VMCS_GUEST_RSP:
708 case VMX_VMCS_GUEST_RIP:
709 case VMX_VMCS_GUEST_RFLAGS:
710 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
711 case VMX_VMCS_GUEST_SYSENTER_ESP:
712 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
713
714 /* Host-state fields. */
715 case VMX_VMCS_HOST_CR0:
716 case VMX_VMCS_HOST_CR3:
717 case VMX_VMCS_HOST_CR4:
718 case VMX_VMCS_HOST_FS_BASE:
719 case VMX_VMCS_HOST_GS_BASE:
720 case VMX_VMCS_HOST_TR_BASE:
721 case VMX_VMCS_HOST_GDTR_BASE:
722 case VMX_VMCS_HOST_IDTR_BASE:
723 case VMX_VMCS_HOST_SYSENTER_ESP:
724 case VMX_VMCS_HOST_SYSENTER_EIP:
725 case VMX_VMCS_HOST_RSP:
726 case VMX_VMCS_HOST_RIP: return true;
727 }
728
729 return false;
730}
731
732
733/**
734 * Gets a host selector from the VMCS.
735 *
736 * @param pVmcs Pointer to the virtual VMCS.
737 * @param iSelReg The index of the segment register (X86_SREG_XXX).
738 */
739DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
740{
741 Assert(iSegReg < X86_SREG_COUNT);
742 RTSEL HostSel;
743 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
744 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
745 uint8_t const uWidthType = (uWidth << 2) | uType;
746 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
747 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
748 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
749 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
750 uint8_t const *pbField = pbVmcs + offField;
751 HostSel = *(uint16_t *)pbField;
752 return HostSel;
753}
754
755
756/**
757 * Sets a guest segment register in the VMCS.
758 *
759 * @param pVmcs Pointer to the virtual VMCS.
760 * @param iSegReg The index of the segment register (X86_SREG_XXX).
761 * @param pSelReg Pointer to the segment register.
762 */
763IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
764{
765 Assert(pSelReg);
766 Assert(iSegReg < X86_SREG_COUNT);
767
768 /* Selector. */
769 {
770 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
771 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
772 uint8_t const uWidthType = (uWidth << 2) | uType;
773 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
774 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
775 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
776 uint8_t *pbVmcs = (uint8_t *)pVmcs;
777 uint8_t *pbField = pbVmcs + offField;
778 *(uint16_t *)pbField = pSelReg->Sel;
779 }
780
781 /* Limit. */
782 {
783 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
784 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
785 uint8_t const uWidthType = (uWidth << 2) | uType;
786 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
787 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
788 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
789 uint8_t *pbVmcs = (uint8_t *)pVmcs;
790 uint8_t *pbField = pbVmcs + offField;
791 *(uint32_t *)pbField = pSelReg->u32Limit;
792 }
793
794 /* Base. */
795 {
796 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
797 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
798 uint8_t const uWidthType = (uWidth << 2) | uType;
799 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
800 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
801 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
802 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
803 uint8_t const *pbField = pbVmcs + offField;
804 *(uint64_t *)pbField = pSelReg->u64Base;
805 }
806
807 /* Attributes. */
808 {
809 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
810 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
811 | X86DESCATTR_UNUSABLE;
812 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
813 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
814 uint8_t const uWidthType = (uWidth << 2) | uType;
815 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
816 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
817 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
818 uint8_t *pbVmcs = (uint8_t *)pVmcs;
819 uint8_t *pbField = pbVmcs + offField;
820 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
821 }
822}
823
824
825/**
826 * Gets a guest segment register from the VMCS.
827 *
828 * @returns VBox status code.
829 * @param pVmcs Pointer to the virtual VMCS.
830 * @param iSegReg The index of the segment register (X86_SREG_XXX).
831 * @param pSelReg Where to store the segment register (only updated when
832 * VINF_SUCCESS is returned).
833 *
834 * @remarks Warning! This does not validate the contents of the retrieved segment
835 * register.
836 */
837IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
838{
839 Assert(pSelReg);
840 Assert(iSegReg < X86_SREG_COUNT);
841
842 /* Selector. */
843 uint16_t u16Sel;
844 {
845 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
846 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
847 uint8_t const uWidthType = (uWidth << 2) | uType;
848 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
849 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
850 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
851 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
852 uint8_t const *pbField = pbVmcs + offField;
853 u16Sel = *(uint16_t *)pbField;
854 }
855
856 /* Limit. */
857 uint32_t u32Limit;
858 {
859 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
860 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
861 uint8_t const uWidthType = (uWidth << 2) | uType;
862 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
863 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
864 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
865 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
866 uint8_t const *pbField = pbVmcs + offField;
867 u32Limit = *(uint32_t *)pbField;
868 }
869
870 /* Base. */
871 uint64_t u64Base;
872 {
873 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
874 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
875 uint8_t const uWidthType = (uWidth << 2) | uType;
876 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
877 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
878 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
879 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
880 uint8_t const *pbField = pbVmcs + offField;
881 u64Base = *(uint64_t *)pbField;
882 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
883 }
884
885 /* Attributes. */
886 uint32_t u32Attr;
887 {
888 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
889 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
890 uint8_t const uWidthType = (uWidth << 2) | uType;
891 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
892 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
893 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
894 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
895 uint8_t const *pbField = pbVmcs + offField;
896 u32Attr = *(uint32_t *)pbField;
897 }
898
899 pSelReg->Sel = u16Sel;
900 pSelReg->ValidSel = u16Sel;
901 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
902 pSelReg->u32Limit = u32Limit;
903 pSelReg->u64Base = u64Base;
904 pSelReg->Attr.u = u32Attr;
905 return VINF_SUCCESS;
906}
907
908
909/**
910 * Gets a CR3 target value from the VMCS.
911 *
912 * @returns VBox status code.
913 * @param pVmcs Pointer to the virtual VMCS.
914 * @param idxCr3Target The index of the CR3-target value to retrieve.
915 * @param puValue Where to store the CR3-target value.
916 */
917DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
918{
919 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
920 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
921 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
922 uint8_t const uWidthType = (uWidth << 2) | uType;
923 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
924 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
925 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
926 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
927 uint8_t const *pbField = pbVmcs + offField;
928 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
929
930 return uCr3TargetValue;
931}
932
933
934/**
935 * Converts an IEM exception event type to a VMX event type.
936 *
937 * @returns The VMX event type.
938 * @param uVector The interrupt / exception vector.
939 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
940 */
941DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
942{
943 /* Paranoia (callers may use these interchangeably). */
944 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
945 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
946 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
947 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
948 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
956
957 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
958 {
959 if (uVector == X86_XCPT_NMI)
960 return VMX_EXIT_INT_INFO_TYPE_NMI;
961 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
962 }
963
964 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
965 {
966 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
967 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
968 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
969 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
970 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
971 }
972
973 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
974 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
975}
976
977
978/**
979 * Sets the VM-instruction error VMCS field.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param enmInsErr The VM-instruction error.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoVmInstrError = enmInsErr;
988}
989
990
991/**
992 * Sets the VM-exit qualification VMCS field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uExitQual The VM-exit qualification.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u64RoExitQual.u = uExitQual;
1001}
1002
1003
1004/**
1005 * Sets the VM-exit interruption information field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uExitQual The VM-exit interruption information.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit interruption error code.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uErrCode The error code.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u32RoExitIntErrCode = uErrCode;
1027}
1028
1029
1030/**
1031 * Sets the IDT-vectoring information field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uIdtVectorInfo The IDT-vectoring information.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1040}
1041
1042
1043/**
1044 * Sets the IDT-vectoring error code field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param uErrCode The error code.
1048 */
1049DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1050{
1051 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1052 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1053}
1054
1055
1056/**
1057 * Sets the VM-exit guest-linear address VMCS field.
1058 *
1059 * @param pVCpu The cross context virtual CPU structure.
1060 * @param uGuestLinearAddr The VM-exit guest-linear address.
1061 */
1062DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1063{
1064 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1065 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1066}
1067
1068
1069/**
1070 * Sets the VM-exit guest-physical address VMCS field.
1071 *
1072 * @param pVCpu The cross context virtual CPU structure.
1073 * @param uGuestPhysAddr The VM-exit guest-physical address.
1074 */
1075DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1076{
1077 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1078 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1079}
1080
1081
1082/**
1083 * Sets the VM-exit instruction length VMCS field.
1084 *
1085 * @param pVCpu The cross context virtual CPU structure.
1086 * @param cbInstr The VM-exit instruction length in bytes.
1087 *
1088 * @remarks Callers may clear this field to 0. Hence, this function does not check
1089 * the validity of the instruction length.
1090 */
1091DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1092{
1093 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1094 pVmcs->u32RoExitInstrLen = cbInstr;
1095}
1096
1097
1098/**
1099 * Sets the VM-exit instruction info. VMCS field.
1100 *
1101 * @param pVCpu The cross context virtual CPU structure.
1102 * @param uExitInstrInfo The VM-exit instruction information.
1103 */
1104DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1105{
1106 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1107 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1108}
1109
1110
1111/**
1112 * Implements VMSucceed for VMX instruction success.
1113 *
1114 * @param pVCpu The cross context virtual CPU structure.
1115 */
1116DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1117{
1118 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1119}
1120
1121
1122/**
1123 * Implements VMFailInvalid for VMX instruction failure.
1124 *
1125 * @param pVCpu The cross context virtual CPU structure.
1126 */
1127DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1128{
1129 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1130 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1131}
1132
1133
1134/**
1135 * Implements VMFailValid for VMX instruction failure.
1136 *
1137 * @param pVCpu The cross context virtual CPU structure.
1138 * @param enmInsErr The VM instruction error.
1139 */
1140DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1141{
1142 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1143 {
1144 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1145 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1146 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1147 }
1148}
1149
1150
1151/**
1152 * Implements VMFail for VMX instruction failure.
1153 *
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param enmInsErr The VM instruction error.
1156 */
1157DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1158{
1159 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1160 iemVmxVmFailValid(pVCpu, enmInsErr);
1161 else
1162 iemVmxVmFailInvalid(pVCpu);
1163}
1164
1165
1166/**
1167 * Checks if the given auto-load/store MSR area count is valid for the
1168 * implementation.
1169 *
1170 * @returns @c true if it's within the valid limit, @c false otherwise.
1171 * @param pVCpu The cross context virtual CPU structure.
1172 * @param uMsrCount The MSR area count to check.
1173 */
1174DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1175{
1176 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1177 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1178 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1179 if (uMsrCount <= cMaxSupportedMsrs)
1180 return true;
1181 return false;
1182}
1183
1184
1185/**
1186 * Flushes the current VMCS contents back to guest memory.
1187 *
1188 * @returns VBox status code.
1189 * @param pVCpu The cross context virtual CPU structure.
1190 */
1191DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1192{
1193 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1194 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1195 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1196 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1197 return rc;
1198}
1199
1200
1201/**
1202 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1203 *
1204 * @param pVCpu The cross context virtual CPU structure.
1205 */
1206DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1207{
1208 iemVmxVmSucceed(pVCpu);
1209 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1210}
1211
1212
1213/**
1214 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1215 * nested-guest.
1216 *
1217 * @param iSegReg The segment index (X86_SREG_XXX).
1218 */
1219IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1220{
1221 switch (iSegReg)
1222 {
1223 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1224 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1225 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1226 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1227 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1228 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1229 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1230 }
1231}
1232
1233
1234/**
1235 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1236 * nested-guest that is in Virtual-8086 mode.
1237 *
1238 * @param iSegReg The segment index (X86_SREG_XXX).
1239 */
1240IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1241{
1242 switch (iSegReg)
1243 {
1244 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1245 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1246 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1247 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1248 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1249 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1250 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1251 }
1252}
1253
1254
1255/**
1256 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1257 * nested-guest that is in Virtual-8086 mode.
1258 *
1259 * @param iSegReg The segment index (X86_SREG_XXX).
1260 */
1261IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1262{
1263 switch (iSegReg)
1264 {
1265 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1266 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1267 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1268 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1269 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1270 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1271 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1272 }
1273}
1274
1275
1276/**
1277 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1278 * nested-guest that is in Virtual-8086 mode.
1279 *
1280 * @param iSegReg The segment index (X86_SREG_XXX).
1281 */
1282IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1283{
1284 switch (iSegReg)
1285 {
1286 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1287 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1288 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1289 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1290 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1291 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1292 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1293 }
1294}
1295
1296
1297/**
1298 * Gets the instruction diagnostic for segment attributes reserved bits failure
1299 * during VM-entry of a nested-guest.
1300 *
1301 * @param iSegReg The segment index (X86_SREG_XXX).
1302 */
1303IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1304{
1305 switch (iSegReg)
1306 {
1307 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1308 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1309 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1310 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1311 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1312 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1313 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1314 }
1315}
1316
1317
1318/**
1319 * Gets the instruction diagnostic for segment attributes descriptor-type
1320 * (code/segment or system) failure during VM-entry of a nested-guest.
1321 *
1322 * @param iSegReg The segment index (X86_SREG_XXX).
1323 */
1324IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1325{
1326 switch (iSegReg)
1327 {
1328 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1329 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1330 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1331 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1332 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1333 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1334 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1335 }
1336}
1337
1338
1339/**
1340 * Gets the instruction diagnostic for segment attributes descriptor-type
1341 * (code/segment or system) failure during VM-entry of a nested-guest.
1342 *
1343 * @param iSegReg The segment index (X86_SREG_XXX).
1344 */
1345IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1346{
1347 switch (iSegReg)
1348 {
1349 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1350 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1351 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1352 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1353 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1354 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1355 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1356 }
1357}
1358
1359
1360/**
1361 * Gets the instruction diagnostic for segment attribute granularity failure during
1362 * VM-entry of a nested-guest.
1363 *
1364 * @param iSegReg The segment index (X86_SREG_XXX).
1365 */
1366IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1367{
1368 switch (iSegReg)
1369 {
1370 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1371 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1372 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1373 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1374 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1375 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1376 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1377 }
1378}
1379
1380/**
1381 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1382 * VM-entry of a nested-guest.
1383 *
1384 * @param iSegReg The segment index (X86_SREG_XXX).
1385 */
1386IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1387{
1388 switch (iSegReg)
1389 {
1390 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1391 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1392 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1393 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1394 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1395 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1396 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1397 }
1398}
1399
1400
1401/**
1402 * Gets the instruction diagnostic for segment attribute type accessed failure
1403 * during VM-entry of a nested-guest.
1404 *
1405 * @param iSegReg The segment index (X86_SREG_XXX).
1406 */
1407IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1408{
1409 switch (iSegReg)
1410 {
1411 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1412 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1413 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1414 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1415 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1416 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1417 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1418 }
1419}
1420
1421
1422/**
1423 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1424 * failure during VM-entry of a nested-guest.
1425 *
1426 * @param iSegReg The PDPTE entry index.
1427 */
1428IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1429{
1430 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1431 switch (iPdpte)
1432 {
1433 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1434 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1435 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1436 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1437 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1438 }
1439}
1440
1441
1442/**
1443 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1444 * failure during VM-exit of a nested-guest.
1445 *
1446 * @param iSegReg The PDPTE entry index.
1447 */
1448IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1449{
1450 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1451 switch (iPdpte)
1452 {
1453 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1454 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1455 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1456 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1457 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1458 }
1459}
1460
1461
1462/**
1463 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1464 * mask and the read-shadow (CR0/CR4 read).
1465 *
1466 * @returns The masked CR0/CR4.
1467 * @param pVCpu The cross context virtual CPU structure.
1468 * @param iCrReg The control register (either CR0 or CR4).
1469 * @param uGuestCrX The current guest CR0 or guest CR4.
1470 */
1471IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1472{
1473 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1474 Assert(iCrReg == 0 || iCrReg == 4);
1475
1476 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1477 Assert(pVmcs);
1478
1479 /*
1480 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1481 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1482 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1483 *
1484 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1485 */
1486 uint64_t fGstHostMask;
1487 uint64_t fReadShadow;
1488 if (iCrReg == 0)
1489 {
1490 fGstHostMask = pVmcs->u64Cr0Mask.u;
1491 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1492 }
1493 else
1494 {
1495 fGstHostMask = pVmcs->u64Cr4Mask.u;
1496 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1497 }
1498
1499 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1500 return fMaskedCrX;
1501}
1502
1503
1504/**
1505 * Saves the guest control registers, debug registers and some MSRs are part of
1506 * VM-exit.
1507 *
1508 * @param pVCpu The cross context virtual CPU structure.
1509 */
1510IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1511{
1512 /*
1513 * Saves the guest control registers, debug registers and some MSRs.
1514 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1515 */
1516 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1517
1518 /* Save control registers. */
1519 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1520 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1521 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1522
1523 /* Save SYSENTER CS, ESP, EIP. */
1524 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1525 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1526 {
1527 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1528 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1529 }
1530 else
1531 {
1532 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1533 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1534 }
1535
1536 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1537 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1538 {
1539 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1540 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1541 }
1542
1543 /* Save PAT MSR. */
1544 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1545 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1546
1547 /* Save EFER MSR. */
1548 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1549 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1550
1551 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1552 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1553
1554 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1555}
1556
1557
1558/**
1559 * Saves the guest force-flags in preparation of entering the nested-guest.
1560 *
1561 * @param pVCpu The cross context virtual CPU structure.
1562 */
1563IEM_STATIC void iemVmxVmentrySaveForceFlags(PVMCPU pVCpu)
1564{
1565 /* We shouldn't be called multiple times during VM-entry. */
1566 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1567
1568 /* MTF should not be set outside VMX non-root mode. */
1569 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1570
1571 /*
1572 * Preserve the required force-flags.
1573 *
1574 * We cache and clear force-flags that would affect the execution of the
1575 * nested-guest. Cached flags are then restored while returning to the guest
1576 * if necessary.
1577 *
1578 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1579 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1580 * instruction. Interrupt inhibition for any nested-guest instruction
1581 * is supplied by the guest-interruptibility state VMCS field and will
1582 * be set up as part of loading the guest state.
1583 *
1584 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1585 * successful VM-entry (due to invalid guest-state) need to continue
1586 * blocking NMIs if it was in effect before VM-entry.
1587 *
1588 * - MTF need not be preserved as it's used only in VMX non-root mode and
1589 * is supplied through the VM-execution controls.
1590 *
1591 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1592 * we will be able to generate interrupts that may cause VM-exits for
1593 * the nested-guest.
1594 */
1595 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1596}
1597
1598
1599/**
1600 * Restores the guest force-flags in preparation of exiting the nested-guest.
1601 *
1602 * @param pVCpu The cross context virtual CPU structure.
1603 */
1604IEM_STATIC void iemVmxVmexitRestoreForceFlags(PVMCPU pVCpu)
1605{
1606 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1607 {
1608 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1609 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1610 }
1611}
1612
1613
1614/**
1615 * Perform a VMX transition updated PGM, IEM and CPUM.
1616 *
1617 * @param pVCpu The cross context virtual CPU structure.
1618 */
1619IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1620{
1621 /*
1622 * Inform PGM about paging mode changes.
1623 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1624 * see comment in iemMemPageTranslateAndCheckAccess().
1625 */
1626 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1627# ifdef IN_RING3
1628 Assert(rc != VINF_PGM_CHANGE_MODE);
1629# endif
1630 AssertRCReturn(rc, rc);
1631
1632 /* Inform CPUM (recompiler), can later be removed. */
1633 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1634
1635 /*
1636 * Flush the TLB with new CR3. This is required in case the PGM mode change
1637 * above doesn't actually change anything.
1638 */
1639 if (rc == VINF_SUCCESS)
1640 {
1641 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1642 AssertRCReturn(rc, rc);
1643 }
1644
1645 /* Re-initialize IEM cache/state after the drastic mode switch. */
1646 iemReInitExec(pVCpu);
1647 return rc;
1648}
1649
1650
1651/**
1652 * Calculates the current VMX-preemption timer value.
1653 *
1654 * @param pVCpu The cross context virtual CPU structure.
1655 */
1656IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1657{
1658 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1659 Assert(pVmcs);
1660
1661 /*
1662 * Assume the following:
1663 * PreemptTimerShift = 5
1664 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1665 * VmentryTick = 50000 (TSC at time of VM-entry)
1666 *
1667 * CurTick Delta PreemptTimerVal
1668 * ----------------------------------
1669 * 60000 10000 2
1670 * 80000 30000 1
1671 * 90000 40000 0 -> VM-exit.
1672 *
1673 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1674 * The saved VMX-preemption timer value is calculated as follows:
1675 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1676 * E.g.:
1677 * Delta = 10000
1678 * Tmp = 10000 / (2 * 10000) = 0.5
1679 * NewPt = 2 - 0.5 = 2
1680 * Delta = 30000
1681 * Tmp = 30000 / (2 * 10000) = 1.5
1682 * NewPt = 2 - 1.5 = 1
1683 * Delta = 40000
1684 * Tmp = 40000 / 20000 = 2
1685 * NewPt = 2 - 2 = 0
1686 */
1687 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1688 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1689 uint64_t const uDelta = uCurTick - uVmentryTick;
1690 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1691 uint32_t const uPreemptTimer = uVmcsPreemptVal
1692 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1693 return uPreemptTimer;
1694}
1695
1696
1697/**
1698 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1699 *
1700 * @param pVCpu The cross context virtual CPU structure.
1701 */
1702IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1703{
1704 /*
1705 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1706 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1707 */
1708 /* CS, SS, ES, DS, FS, GS. */
1709 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1710 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1711 {
1712 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1713 if (!pSelReg->Attr.n.u1Unusable)
1714 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1715 else
1716 {
1717 /*
1718 * For unusable segments the attributes are undefined except for CS and SS.
1719 * For the rest we don't bother preserving anything but the unusable bit.
1720 */
1721 switch (iSegReg)
1722 {
1723 case X86_SREG_CS:
1724 pVmcs->GuestCs = pSelReg->Sel;
1725 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1726 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1727 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1728 | X86DESCATTR_UNUSABLE);
1729 break;
1730
1731 case X86_SREG_SS:
1732 pVmcs->GuestSs = pSelReg->Sel;
1733 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1734 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1735 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1736 break;
1737
1738 case X86_SREG_DS:
1739 pVmcs->GuestDs = pSelReg->Sel;
1740 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1741 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1742 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1743 break;
1744
1745 case X86_SREG_ES:
1746 pVmcs->GuestEs = pSelReg->Sel;
1747 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1748 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1749 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1750 break;
1751
1752 case X86_SREG_FS:
1753 pVmcs->GuestFs = pSelReg->Sel;
1754 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1755 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1756 break;
1757
1758 case X86_SREG_GS:
1759 pVmcs->GuestGs = pSelReg->Sel;
1760 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1761 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1762 break;
1763 }
1764 }
1765 }
1766
1767 /* Segment attribute bits 31:7 and 11:8 MBZ. */
1768 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1769 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
1770 /* LDTR. */
1771 {
1772 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1773 pVmcs->GuestLdtr = pSelReg->Sel;
1774 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1775 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1776 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1777 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1778 }
1779
1780 /* TR. */
1781 {
1782 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1783 pVmcs->GuestTr = pSelReg->Sel;
1784 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1785 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1786 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1787 }
1788
1789 /* GDTR. */
1790 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1791 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1792
1793 /* IDTR. */
1794 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1795 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1796}
1797
1798
1799/**
1800 * Saves guest non-register state as part of VM-exit.
1801 *
1802 * @param pVCpu The cross context virtual CPU structure.
1803 * @param uExitReason The VM-exit reason.
1804 */
1805IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1806{
1807 /*
1808 * Save guest non-register state.
1809 * See Intel spec. 27.3.4 "Saving Non-Register State".
1810 */
1811 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1812
1813 /*
1814 * Activity state.
1815 * Most VM-exits will occur in the active state. However, if the first instruction
1816 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1817 * the VM-exit will be from the HLT activity state.
1818 *
1819 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1820 */
1821 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1822 * not? */
1823 EMSTATE enmActivityState = EMGetState(pVCpu);
1824 switch (enmActivityState)
1825 {
1826 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1827 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1828 }
1829
1830 /* Interruptibility-state. */
1831 pVmcs->u32GuestIntrState = 0;
1832 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1833 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1834
1835 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1836 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1837 {
1838 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1839 * currently. */
1840 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1841 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1842 }
1843 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1844
1845 /*
1846 * Pending debug exceptions.
1847 */
1848 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1849 && uExitReason != VMX_EXIT_SMI
1850 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1851 && !HMVmxIsVmexitTrapLike(uExitReason))
1852 {
1853 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1854 * block-by-MovSS is in effect. */
1855 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1856 }
1857 else
1858 {
1859 /*
1860 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1861 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1862 *
1863 * See Intel spec. 24.4.2 "Guest Non-Register State".
1864 */
1865 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1866 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1867 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1868 if (fPendingDbgMask & fBpHitMask)
1869 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1870 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1871 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1872 }
1873
1874 /*
1875 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1876 *
1877 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1878 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1879 */
1880 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1881 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1882 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1883
1884 /* PDPTEs. */
1885 /* We don't support EPT yet. */
1886 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1887 pVmcs->u64GuestPdpte0.u = 0;
1888 pVmcs->u64GuestPdpte1.u = 0;
1889 pVmcs->u64GuestPdpte2.u = 0;
1890 pVmcs->u64GuestPdpte3.u = 0;
1891}
1892
1893
1894/**
1895 * Saves the guest-state as part of VM-exit.
1896 *
1897 * @returns VBox status code.
1898 * @param pVCpu The cross context virtual CPU structure.
1899 * @param uExitReason The VM-exit reason.
1900 */
1901IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1902{
1903 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1904 Assert(pVmcs);
1905
1906 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1907 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1908
1909 /** @todo r=ramshankar: The below hack is no longer necessary because we invoke the
1910 * VM-exit after updating RIP. I'm leaving it in-place temporarily in case
1911 * we need to fix missing exit information or callers still setting
1912 * instruction-length field when it is not necessary. */
1913#if 0
1914 /*
1915 * Save guest RIP, RSP and RFLAGS.
1916 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
1917 *
1918 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
1919 * Callers must pass the instruction length in the VM-exit instruction length
1920 * field though it is undefined for such VM-exits. After updating RIP here, we clear
1921 * the VM-exit instruction length field.
1922 *
1923 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
1924 */
1925 if (HMVmxIsTrapLikeVmexit(uExitReason))
1926 {
1927 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
1928 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
1929 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1930 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
1931 }
1932#endif
1933
1934 /* We don't support enclave mode yet. */
1935 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1936 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1937 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1938
1939 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1940}
1941
1942
1943/**
1944 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1945 *
1946 * @returns VBox status code.
1947 * @param pVCpu The cross context virtual CPU structure.
1948 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1949 */
1950IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1951{
1952 /*
1953 * Save guest MSRs.
1954 * See Intel spec. 27.4 "Saving MSRs".
1955 */
1956 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1957 const char *const pszFailure = "VMX-abort";
1958
1959 /*
1960 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1961 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1962 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1963 */
1964 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1965 if (!cMsrs)
1966 return VINF_SUCCESS;
1967
1968 /*
1969 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1970 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1971 * implementation causes a VMX-abort followed by a triple-fault.
1972 */
1973 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1974 if (fIsMsrCountValid)
1975 { /* likely */ }
1976 else
1977 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1978
1979 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1980 Assert(pMsr);
1981 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1982 {
1983 if ( !pMsr->u32Reserved
1984 && pMsr->u32Msr != MSR_IA32_SMBASE
1985 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1986 {
1987 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1988 if (rcStrict == VINF_SUCCESS)
1989 continue;
1990
1991 /*
1992 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1993 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1994 * recording the MSR index in the auxiliary info. field and indicated further by our
1995 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1996 * if possible, or come up with a better, generic solution.
1997 */
1998 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1999 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2000 ? kVmxVDiag_Vmexit_MsrStoreRing3
2001 : kVmxVDiag_Vmexit_MsrStore;
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2003 }
2004 else
2005 {
2006 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2007 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2008 }
2009 }
2010
2011 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2012 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2013 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
2014 if (RT_SUCCESS(rc))
2015 { /* likely */ }
2016 else
2017 {
2018 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2019 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2020 }
2021
2022 NOREF(uExitReason);
2023 NOREF(pszFailure);
2024 return VINF_SUCCESS;
2025}
2026
2027
2028/**
2029 * Performs a VMX abort (due to an fatal error during VM-exit).
2030 *
2031 * @returns Strict VBox status code.
2032 * @param pVCpu The cross context virtual CPU structure.
2033 * @param enmAbort The VMX abort reason.
2034 */
2035IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2036{
2037 /*
2038 * Perform the VMX abort.
2039 * See Intel spec. 27.7 "VMX Aborts".
2040 */
2041 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2042
2043 /* We don't support SMX yet. */
2044 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2045 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2046 {
2047 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2048 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, u32VmxAbortId);
2049 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2050 }
2051
2052 return VINF_EM_TRIPLE_FAULT;
2053}
2054
2055
2056/**
2057 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2058 *
2059 * @param pVCpu The cross context virtual CPU structure.
2060 */
2061IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2062{
2063 /*
2064 * Load host control registers, debug registers and MSRs.
2065 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2066 */
2067 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2068 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2069
2070 /* CR0. */
2071 {
2072 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2073 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2074 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2075 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2076 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2077 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2078 CPUMSetGuestCR0(pVCpu, uValidCr0);
2079 }
2080
2081 /* CR4. */
2082 {
2083 /* CR4 MB1 bits are not modified. */
2084 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2085 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2086 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2087 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2088 if (fHostInLongMode)
2089 uValidCr4 |= X86_CR4_PAE;
2090 else
2091 uValidCr4 &= ~X86_CR4_PCIDE;
2092 CPUMSetGuestCR4(pVCpu, uValidCr4);
2093 }
2094
2095 /* CR3 (host value validated while checking host-state during VM-entry). */
2096 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2097
2098 /* DR7. */
2099 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2100
2101 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2102
2103 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2104 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2105 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2106 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2107
2108 /* FS, GS bases are loaded later while we load host segment registers. */
2109
2110 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2111 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2112 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2113 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2114 {
2115 if (fHostInLongMode)
2116 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2117 else
2118 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2119 }
2120
2121 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2122
2123 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2124 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2125 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2126
2127 /* We don't support IA32_BNDCFGS MSR yet. */
2128}
2129
2130
2131/**
2132 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2133 *
2134 * @param pVCpu The cross context virtual CPU structure.
2135 */
2136IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2137{
2138 /*
2139 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2140 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2141 *
2142 * Warning! Be careful to not touch fields that are reserved by VT-x,
2143 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2144 */
2145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2146 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2147
2148 /* CS, SS, ES, DS, FS, GS. */
2149 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2150 {
2151 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2152 bool const fUnusable = RT_BOOL(HostSel == 0);
2153
2154 /* Selector. */
2155 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel = HostSel;
2156 pVCpu->cpum.GstCtx.aSRegs[iSegReg].ValidSel = HostSel;
2157 pVCpu->cpum.GstCtx.aSRegs[iSegReg].fFlags = CPUMSELREG_FLAGS_VALID;
2158
2159 /* Limit. */
2160 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u32Limit = 0xffffffff;
2161
2162 /* Base and Attributes. */
2163 switch (iSegReg)
2164 {
2165 case X86_SREG_CS:
2166 {
2167 pVCpu->cpum.GstCtx.cs.u64Base = 0;
2168 pVCpu->cpum.GstCtx.cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2169 pVCpu->cpum.GstCtx.ss.Attr.n.u1DescType = 1;
2170 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = 0;
2171 pVCpu->cpum.GstCtx.cs.Attr.n.u1Present = 1;
2172 pVCpu->cpum.GstCtx.cs.Attr.n.u1Long = fHostInLongMode;
2173 pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig = !fHostInLongMode;
2174 pVCpu->cpum.GstCtx.cs.Attr.n.u1Granularity = 1;
2175 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Unusable);
2176 Assert(!fUnusable);
2177 break;
2178 }
2179
2180 case X86_SREG_SS:
2181 case X86_SREG_ES:
2182 case X86_SREG_DS:
2183 {
2184 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base = 0;
2185 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2186 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DescType = 1;
2187 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u2Dpl = 0;
2188 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Present = 1;
2189 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DefBig = 1;
2190 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Granularity = 1;
2191 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable = fUnusable;
2192 break;
2193 }
2194
2195 case X86_SREG_FS:
2196 {
2197 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2198 pVCpu->cpum.GstCtx.fs.u64Base = !fUnusable ? pVmcs->u64HostFsBase.u : 0;
2199 pVCpu->cpum.GstCtx.fs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2200 pVCpu->cpum.GstCtx.fs.Attr.n.u1DescType = 1;
2201 pVCpu->cpum.GstCtx.fs.Attr.n.u2Dpl = 0;
2202 pVCpu->cpum.GstCtx.fs.Attr.n.u1Present = 1;
2203 pVCpu->cpum.GstCtx.fs.Attr.n.u1DefBig = 1;
2204 pVCpu->cpum.GstCtx.fs.Attr.n.u1Granularity = 1;
2205 pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable = fUnusable;
2206 break;
2207 }
2208
2209 case X86_SREG_GS:
2210 {
2211 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2212 pVCpu->cpum.GstCtx.gs.u64Base = !fUnusable ? pVmcs->u64HostGsBase.u : 0;
2213 pVCpu->cpum.GstCtx.gs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2214 pVCpu->cpum.GstCtx.gs.Attr.n.u1DescType = 1;
2215 pVCpu->cpum.GstCtx.gs.Attr.n.u2Dpl = 0;
2216 pVCpu->cpum.GstCtx.gs.Attr.n.u1Present = 1;
2217 pVCpu->cpum.GstCtx.gs.Attr.n.u1DefBig = 1;
2218 pVCpu->cpum.GstCtx.gs.Attr.n.u1Granularity = 1;
2219 pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable = fUnusable;
2220 break;
2221 }
2222 }
2223 }
2224
2225 /* TR. */
2226 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2227 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2228 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2229 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2230 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2231 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2232 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2233 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2234 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2235 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2236 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2237 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2238 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2239
2240 /* LDTR. */
2241 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2242 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2243 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2244 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
2245 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
2246 pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Unusable = 1;
2247
2248 /* GDTR. */
2249 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2250 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2251 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xfff;
2252
2253 /* IDTR.*/
2254 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2255 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2256 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xfff;
2257}
2258
2259
2260/**
2261 * Checks host PDPTes as part of VM-exit.
2262 *
2263 * @param pVCpu The cross context virtual CPU structure.
2264 * @param uExitReason The VM-exit reason (for logging purposes).
2265 */
2266IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2267{
2268 /*
2269 * Check host PDPTEs.
2270 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2271 */
2272 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2273 const char *const pszFailure = "VMX-abort";
2274 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2275
2276 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2277 && !fHostInLongMode)
2278 {
2279 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2280 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2281 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2282 if (RT_SUCCESS(rc))
2283 {
2284 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2285 {
2286 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2287 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2288 { /* likely */ }
2289 else
2290 {
2291 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2292 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2293 }
2294 }
2295 }
2296 else
2297 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2298 }
2299
2300 NOREF(pszFailure);
2301 NOREF(uExitReason);
2302 return VINF_SUCCESS;
2303}
2304
2305
2306/**
2307 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2308 *
2309 * @returns VBox status code.
2310 * @param pVCpu The cross context virtual CPU structure.
2311 * @param pszInstr The VMX instruction name (for logging purposes).
2312 */
2313IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2314{
2315 /*
2316 * Load host MSRs.
2317 * See Intel spec. 27.6 "Loading MSRs".
2318 */
2319 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2320 const char *const pszFailure = "VMX-abort";
2321
2322 /*
2323 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2324 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2325 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2326 */
2327 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2328 if (!cMsrs)
2329 return VINF_SUCCESS;
2330
2331 /*
2332 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2333 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2334 * implementation causes a VMX-abort followed by a triple-fault.
2335 */
2336 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2337 if (fIsMsrCountValid)
2338 { /* likely */ }
2339 else
2340 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2341
2342 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2343 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2344 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2345 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2346 if (RT_SUCCESS(rc))
2347 {
2348 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2349 Assert(pMsr);
2350 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2351 {
2352 if ( !pMsr->u32Reserved
2353 && pMsr->u32Msr != MSR_K8_FS_BASE
2354 && pMsr->u32Msr != MSR_K8_GS_BASE
2355 && pMsr->u32Msr != MSR_K6_EFER
2356 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2357 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2358 {
2359 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2360 if (rcStrict == VINF_SUCCESS)
2361 continue;
2362
2363 /*
2364 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2365 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2366 * recording the MSR index in the auxiliary info. field and indicated further by our
2367 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2368 * if possible, or come up with a better, generic solution.
2369 */
2370 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2371 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2372 ? kVmxVDiag_Vmexit_MsrLoadRing3
2373 : kVmxVDiag_Vmexit_MsrLoad;
2374 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2375 }
2376 else
2377 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2378 }
2379 }
2380 else
2381 {
2382 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2383 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2384 }
2385
2386 NOREF(uExitReason);
2387 NOREF(pszFailure);
2388 return VINF_SUCCESS;
2389}
2390
2391
2392/**
2393 * Loads the host state as part of VM-exit.
2394 *
2395 * @returns Strict VBox status code.
2396 * @param pVCpu The cross context virtual CPU structure.
2397 * @param uExitReason The VM-exit reason (for logging purposes).
2398 */
2399IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2400{
2401 /*
2402 * Load host state.
2403 * See Intel spec. 27.5 "Loading Host State".
2404 */
2405 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2406 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2407
2408 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2409 if ( CPUMIsGuestInLongMode(pVCpu)
2410 && !fHostInLongMode)
2411 {
2412 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2413 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2414 }
2415
2416 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2417 iemVmxVmexitLoadHostSegRegs(pVCpu);
2418
2419 /*
2420 * Load host RIP, RSP and RFLAGS.
2421 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2422 */
2423 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2424 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2425 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2426
2427 /* Clear address range monitoring. */
2428 EMMonitorWaitClear(pVCpu);
2429
2430 /* Perform the VMX transition (PGM updates). */
2431 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2432 if (rcStrict == VINF_SUCCESS)
2433 {
2434 /* Check host PDPTEs (only when we've fully switched page tables_. */
2435 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2436 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2437 if (RT_FAILURE(rc))
2438 {
2439 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2440 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2441 }
2442 }
2443 else if (RT_SUCCESS(rcStrict))
2444 {
2445 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2446 uExitReason));
2447 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2448 }
2449 else
2450 {
2451 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2452 return VBOXSTRICTRC_VAL(rcStrict);
2453 }
2454
2455 Assert(rcStrict == VINF_SUCCESS);
2456
2457 /* Load MSRs from the VM-exit auto-load MSR area. */
2458 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2459 if (RT_FAILURE(rc))
2460 {
2461 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2462 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2463 }
2464
2465 return rcStrict;
2466}
2467
2468
2469/**
2470 * Gets VM-exit instruction information along with any displacement for an
2471 * instruction VM-exit.
2472 *
2473 * @returns The VM-exit instruction information.
2474 * @param pVCpu The cross context virtual CPU structure.
2475 * @param uExitReason The VM-exit reason.
2476 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2477 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2478 * NULL.
2479 */
2480IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2481{
2482 RTGCPTR GCPtrDisp;
2483 VMXEXITINSTRINFO ExitInstrInfo;
2484 ExitInstrInfo.u = 0;
2485
2486 /*
2487 * Get and parse the ModR/M byte from our decoded opcodes.
2488 */
2489 uint8_t bRm;
2490 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2491 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2492 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2493 {
2494 /*
2495 * ModR/M indicates register addressing.
2496 *
2497 * The primary/secondary register operands are reported in the iReg1 or iReg2
2498 * fields depending on whether it is a read/write form.
2499 */
2500 uint8_t idxReg1;
2501 uint8_t idxReg2;
2502 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2503 {
2504 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2505 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2506 }
2507 else
2508 {
2509 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2510 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2511 }
2512 ExitInstrInfo.All.u2Scaling = 0;
2513 ExitInstrInfo.All.iReg1 = idxReg1;
2514 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2515 ExitInstrInfo.All.fIsRegOperand = 1;
2516 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2517 ExitInstrInfo.All.iSegReg = 0;
2518 ExitInstrInfo.All.iIdxReg = 0;
2519 ExitInstrInfo.All.fIdxRegInvalid = 1;
2520 ExitInstrInfo.All.iBaseReg = 0;
2521 ExitInstrInfo.All.fBaseRegInvalid = 1;
2522 ExitInstrInfo.All.iReg2 = idxReg2;
2523
2524 /* Displacement not applicable for register addressing. */
2525 GCPtrDisp = 0;
2526 }
2527 else
2528 {
2529 /*
2530 * ModR/M indicates memory addressing.
2531 */
2532 uint8_t uScale = 0;
2533 bool fBaseRegValid = false;
2534 bool fIdxRegValid = false;
2535 uint8_t iBaseReg = 0;
2536 uint8_t iIdxReg = 0;
2537 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2538 {
2539 /*
2540 * Parse the ModR/M, displacement for 16-bit addressing mode.
2541 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2542 */
2543 uint16_t u16Disp = 0;
2544 uint8_t const offDisp = offModRm + sizeof(bRm);
2545 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2546 {
2547 /* Displacement without any registers. */
2548 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2549 }
2550 else
2551 {
2552 /* Register (index and base). */
2553 switch (bRm & X86_MODRM_RM_MASK)
2554 {
2555 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2556 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2557 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2558 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2559 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2560 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2561 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2562 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2563 }
2564
2565 /* Register + displacement. */
2566 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2567 {
2568 case 0: break;
2569 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2570 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2571 default:
2572 {
2573 /* Register addressing, handled at the beginning. */
2574 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2575 break;
2576 }
2577 }
2578 }
2579
2580 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2581 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2582 }
2583 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2584 {
2585 /*
2586 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2587 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2588 */
2589 uint32_t u32Disp = 0;
2590 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2591 {
2592 /* Displacement without any registers. */
2593 uint8_t const offDisp = offModRm + sizeof(bRm);
2594 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2595 }
2596 else
2597 {
2598 /* Register (and perhaps scale, index and base). */
2599 uint8_t offDisp = offModRm + sizeof(bRm);
2600 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2601 if (iBaseReg == 4)
2602 {
2603 /* An SIB byte follows the ModR/M byte, parse it. */
2604 uint8_t bSib;
2605 uint8_t const offSib = offModRm + sizeof(bRm);
2606 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2607
2608 /* A displacement may follow SIB, update its offset. */
2609 offDisp += sizeof(bSib);
2610
2611 /* Get the scale. */
2612 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2613
2614 /* Get the index register. */
2615 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2616 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2617
2618 /* Get the base register. */
2619 iBaseReg = bSib & X86_SIB_BASE_MASK;
2620 fBaseRegValid = true;
2621 if (iBaseReg == 5)
2622 {
2623 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2624 {
2625 /* Mod is 0 implies a 32-bit displacement with no base. */
2626 fBaseRegValid = false;
2627 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2628 }
2629 else
2630 {
2631 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2632 iBaseReg = X86_GREG_xBP;
2633 }
2634 }
2635 }
2636
2637 /* Register + displacement. */
2638 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2639 {
2640 case 0: /* Handled above */ break;
2641 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2642 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2643 default:
2644 {
2645 /* Register addressing, handled at the beginning. */
2646 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2647 break;
2648 }
2649 }
2650 }
2651
2652 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2653 }
2654 else
2655 {
2656 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2657
2658 /*
2659 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2660 * See Intel instruction spec. 2.2 "IA-32e Mode".
2661 */
2662 uint64_t u64Disp = 0;
2663 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2664 if (fRipRelativeAddr)
2665 {
2666 /*
2667 * RIP-relative addressing mode.
2668 *
2669 * The displacement is 32-bit signed implying an offset range of +/-2G.
2670 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2671 */
2672 uint8_t const offDisp = offModRm + sizeof(bRm);
2673 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2674 }
2675 else
2676 {
2677 uint8_t offDisp = offModRm + sizeof(bRm);
2678
2679 /*
2680 * Register (and perhaps scale, index and base).
2681 *
2682 * REX.B extends the most-significant bit of the base register. However, REX.B
2683 * is ignored while determining whether an SIB follows the opcode. Hence, we
2684 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2685 *
2686 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2687 */
2688 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2689 if (iBaseReg == 4)
2690 {
2691 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2692 uint8_t bSib;
2693 uint8_t const offSib = offModRm + sizeof(bRm);
2694 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2695
2696 /* Displacement may follow SIB, update its offset. */
2697 offDisp += sizeof(bSib);
2698
2699 /* Get the scale. */
2700 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2701
2702 /* Get the index. */
2703 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2704 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2705
2706 /* Get the base. */
2707 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2708 fBaseRegValid = true;
2709 if (iBaseReg == 5)
2710 {
2711 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2712 {
2713 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2714 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2715 }
2716 else
2717 {
2718 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2719 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2720 }
2721 }
2722 }
2723 iBaseReg |= pVCpu->iem.s.uRexB;
2724
2725 /* Register + displacement. */
2726 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2727 {
2728 case 0: /* Handled above */ break;
2729 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2730 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2731 default:
2732 {
2733 /* Register addressing, handled at the beginning. */
2734 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2735 break;
2736 }
2737 }
2738 }
2739
2740 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2741 }
2742
2743 /*
2744 * The primary or secondary register operand is reported in iReg2 depending
2745 * on whether the primary operand is in read/write form.
2746 */
2747 uint8_t idxReg2;
2748 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2749 {
2750 idxReg2 = bRm & X86_MODRM_RM_MASK;
2751 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2752 idxReg2 |= pVCpu->iem.s.uRexB;
2753 }
2754 else
2755 {
2756 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2757 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2758 idxReg2 |= pVCpu->iem.s.uRexReg;
2759 }
2760 ExitInstrInfo.All.u2Scaling = uScale;
2761 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2762 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2763 ExitInstrInfo.All.fIsRegOperand = 0;
2764 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2765 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2766 ExitInstrInfo.All.iIdxReg = iIdxReg;
2767 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2768 ExitInstrInfo.All.iBaseReg = iBaseReg;
2769 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2770 ExitInstrInfo.All.iReg2 = idxReg2;
2771 }
2772
2773 /*
2774 * Handle exceptions to the norm for certain instructions.
2775 * (e.g. some instructions convey an instruction identity in place of iReg2).
2776 */
2777 switch (uExitReason)
2778 {
2779 case VMX_EXIT_GDTR_IDTR_ACCESS:
2780 {
2781 Assert(VMXINSTRID_IS_VALID(uInstrId));
2782 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2783 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2784 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2785 break;
2786 }
2787
2788 case VMX_EXIT_LDTR_TR_ACCESS:
2789 {
2790 Assert(VMXINSTRID_IS_VALID(uInstrId));
2791 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2792 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2793 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2794 break;
2795 }
2796
2797 case VMX_EXIT_RDRAND:
2798 case VMX_EXIT_RDSEED:
2799 {
2800 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2801 break;
2802 }
2803 }
2804
2805 /* Update displacement and return the constructed VM-exit instruction information field. */
2806 if (pGCPtrDisp)
2807 *pGCPtrDisp = GCPtrDisp;
2808
2809 return ExitInstrInfo.u;
2810}
2811
2812
2813/**
2814 * VMX VM-exit handler.
2815 *
2816 * @returns Strict VBox status code.
2817 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2818 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2819 * triple-fault.
2820 *
2821 * @param pVCpu The cross context virtual CPU structure.
2822 * @param uExitReason The VM-exit reason.
2823 *
2824 * @remarks Make sure VM-exit qualification is updated before calling this
2825 * function!
2826 */
2827IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2828{
2829# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2830 RT_NOREF2(pVCpu, uExitReason);
2831 return VINF_EM_RAW_EMULATE_INSTR;
2832# else
2833 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
2834
2835 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2836 Assert(pVmcs);
2837
2838 pVmcs->u32RoExitReason = uExitReason;
2839
2840 /** @todo NSTVMX: IEMGetCurrentXcpt will be VM-exit interruption info. */
2841 /** @todo NSTVMX: The source event should be recorded in IDT-vectoring info
2842 * during injection. */
2843
2844 /*
2845 * Save the guest state back into the VMCS.
2846 * We only need to save the state when the VM-entry was successful.
2847 */
2848 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2849 if (!fVmentryFailed)
2850 {
2851 /*
2852 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2853 * occurs in enclave mode/SMM which we don't support yet.
2854 *
2855 * If we ever add support for it, we can pass just the lower bits, till then an assert
2856 * should suffice.
2857 */
2858 Assert(!RT_HI_U16(uExitReason));
2859
2860 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2861 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2862 if (RT_SUCCESS(rc))
2863 { /* likely */ }
2864 else
2865 {
2866 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE(pVCpu, "VMX-Abort");
2867 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2868 }
2869 }
2870 else
2871 {
2872 /* Restore force-flags that may or may not have been cleared as part of the failed VM-entry. */
2873 iemVmxVmexitRestoreForceFlags(pVCpu);
2874 }
2875
2876 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2877 if (RT_FAILURE(rcStrict))
2878 LogFunc(("Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2879
2880 /* We're no longer in nested-guest execution mode. */
2881 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2882
2883 Assert(rcStrict == VINF_SUCCESS);
2884 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE(pVCpu, "VM-exit");
2885 return VINF_VMX_VMEXIT;
2886# endif
2887}
2888
2889
2890/**
2891 * VMX VM-exit handler for VM-exits due to instruction execution.
2892 *
2893 * This is intended for instructions where the caller provides all the relevant
2894 * VM-exit information.
2895 *
2896 * @returns Strict VBox status code.
2897 * @param pVCpu The cross context virtual CPU structure.
2898 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2899 */
2900DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2901{
2902 /*
2903 * For instructions where any of the following fields are not applicable:
2904 * - VM-exit instruction info. is undefined.
2905 * - VM-exit qualification must be cleared.
2906 * - VM-exit guest-linear address is undefined.
2907 * - VM-exit guest-physical address is undefined.
2908 *
2909 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2910 * instruction execution. For VM-exits that are not due to instruction execution this
2911 * field is undefined.
2912 *
2913 * In our implementation in IEM, all undefined fields are generally cleared. However,
2914 * if the caller supplies information (from say the physical CPU directly) it is
2915 * then possible that the undefined fields are not cleared.
2916 *
2917 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2918 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2919 */
2920 Assert(pExitInfo);
2921 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2922 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2923 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2924
2925 /* Update all the relevant fields from the VM-exit instruction information struct. */
2926 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2927 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2928 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2929 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2930 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2931
2932 /* Perform the VM-exit. */
2933 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2934}
2935
2936
2937/**
2938 * VMX VM-exit handler for VM-exits due to instruction execution.
2939 *
2940 * This is intended for instructions that only provide the VM-exit instruction
2941 * length.
2942 *
2943 * @param pVCpu The cross context virtual CPU structure.
2944 * @param uExitReason The VM-exit reason.
2945 * @param cbInstr The instruction length in bytes.
2946 */
2947IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2948{
2949 VMXVEXITINFO ExitInfo;
2950 RT_ZERO(ExitInfo);
2951 ExitInfo.uReason = uExitReason;
2952 ExitInfo.cbInstr = cbInstr;
2953
2954#ifdef VBOX_STRICT
2955 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2956 switch (uExitReason)
2957 {
2958 case VMX_EXIT_INVEPT:
2959 case VMX_EXIT_INVPCID:
2960 case VMX_EXIT_LDTR_TR_ACCESS:
2961 case VMX_EXIT_GDTR_IDTR_ACCESS:
2962 case VMX_EXIT_VMCLEAR:
2963 case VMX_EXIT_VMPTRLD:
2964 case VMX_EXIT_VMPTRST:
2965 case VMX_EXIT_VMREAD:
2966 case VMX_EXIT_VMWRITE:
2967 case VMX_EXIT_VMXON:
2968 case VMX_EXIT_XRSTORS:
2969 case VMX_EXIT_XSAVES:
2970 case VMX_EXIT_RDRAND:
2971 case VMX_EXIT_RDSEED:
2972 case VMX_EXIT_IO_INSTR:
2973 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2974 break;
2975 }
2976#endif
2977
2978 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2979}
2980
2981
2982/**
2983 * VMX VM-exit handler for VM-exits due to instruction execution.
2984 *
2985 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2986 * instruction information and VM-exit qualification fields.
2987 *
2988 * @param pVCpu The cross context virtual CPU structure.
2989 * @param uExitReason The VM-exit reason.
2990 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2991 * @param cbInstr The instruction length in bytes.
2992 *
2993 * @remarks Do not use this for INS/OUTS instruction.
2994 */
2995IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2996{
2997 VMXVEXITINFO ExitInfo;
2998 RT_ZERO(ExitInfo);
2999 ExitInfo.uReason = uExitReason;
3000 ExitInfo.cbInstr = cbInstr;
3001
3002 /*
3003 * Update the VM-exit qualification field with displacement bytes.
3004 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3005 */
3006 switch (uExitReason)
3007 {
3008 case VMX_EXIT_INVEPT:
3009 case VMX_EXIT_INVPCID:
3010 case VMX_EXIT_LDTR_TR_ACCESS:
3011 case VMX_EXIT_GDTR_IDTR_ACCESS:
3012 case VMX_EXIT_VMCLEAR:
3013 case VMX_EXIT_VMPTRLD:
3014 case VMX_EXIT_VMPTRST:
3015 case VMX_EXIT_VMREAD:
3016 case VMX_EXIT_VMWRITE:
3017 case VMX_EXIT_VMXON:
3018 case VMX_EXIT_XRSTORS:
3019 case VMX_EXIT_XSAVES:
3020 case VMX_EXIT_RDRAND:
3021 case VMX_EXIT_RDSEED:
3022 {
3023 /* Construct the VM-exit instruction information. */
3024 RTGCPTR GCPtrDisp;
3025 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3026
3027 /* Update the VM-exit instruction information. */
3028 ExitInfo.InstrInfo.u = uInstrInfo;
3029
3030 /* Update the VM-exit qualification. */
3031 ExitInfo.u64Qual = GCPtrDisp;
3032 break;
3033 }
3034
3035 default:
3036 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3037 break;
3038 }
3039
3040 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3041}
3042
3043
3044/**
3045 * Checks whether an I/O instruction for the given port is intercepted (causes a
3046 * VM-exit) or not.
3047 *
3048 * @returns @c true if the instruction is intercepted, @c false otherwise.
3049 * @param pVCpu The cross context virtual CPU structure.
3050 * @param u16Port The I/O port being accessed by the instruction.
3051 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3052 */
3053IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3054{
3055 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3056 Assert(pVmcs);
3057
3058 /*
3059 * Check whether the I/O instruction must cause a VM-exit or not.
3060 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3061 */
3062 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3063 return true;
3064
3065 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3066 {
3067 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3068 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3069 Assert(pbIoBitmapA);
3070 Assert(pbIoBitmapB);
3071 return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3072 }
3073
3074 return false;
3075}
3076
3077
3078/**
3079 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3080 *
3081 * @returns Strict VBox status code.
3082 * @param pVCpu The cross context virtual CPU structure.
3083 */
3084IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3085{
3086 /*
3087 * The MTF VM-exit can occur even when the MTF VM-execution control is
3088 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3089 * check for it here.
3090 */
3091
3092 /* Clear the force-flag indicating that monitor-trap flag is no longer active. */
3093 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3094
3095 /* Cause the MTF VM-exit. The VM-exit qualification MBZ. */
3096 iemVmxVmcsSetExitQual(pVCpu, 0);
3097 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3098}
3099
3100
3101/**
3102 * VMX VM-exit handler for VM-exits due to INVLPG.
3103 *
3104 * @returns Strict VBox status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 * @param GCPtrPage The guest-linear address of the page being invalidated.
3107 * @param cbInstr The instruction length in bytes.
3108 */
3109IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3110{
3111 VMXVEXITINFO ExitInfo;
3112 RT_ZERO(ExitInfo);
3113 ExitInfo.uReason = VMX_EXIT_INVLPG;
3114 ExitInfo.cbInstr = cbInstr;
3115 ExitInfo.u64Qual = GCPtrPage;
3116 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3117
3118 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3119}
3120
3121
3122/**
3123 * VMX VM-exit handler for VM-exits due to LMSW.
3124 *
3125 * @returns Strict VBox status code.
3126 * @param pVCpu The cross context virtual CPU structure.
3127 * @param uGuestCr0 The current guest CR0.
3128 * @param pu16NewMsw The machine-status word specified in LMSW's source
3129 * operand. This will be updated depending on the VMX
3130 * guest/host CR0 mask if LMSW is not intercepted.
3131 * @param GCPtrEffDst The guest-linear address of the source operand in case
3132 * of a memory operand. For register operand, pass
3133 * NIL_RTGCPTR.
3134 * @param cbInstr The instruction length in bytes.
3135 */
3136IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3137 uint8_t cbInstr)
3138{
3139 /*
3140 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3141 *
3142 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3143 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3144 */
3145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3146 Assert(pVmcs);
3147 Assert(pu16NewMsw);
3148
3149 bool fIntercept = false;
3150 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3151 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3152
3153 /*
3154 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3155 * CR0.PE case first, before the rest of the bits in the MSW.
3156 *
3157 * If CR0.PE is owned by the host and CR0.PE differs between the
3158 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3159 */
3160 if ( (fGstHostMask & X86_CR0_PE)
3161 && (*pu16NewMsw & X86_CR0_PE)
3162 && !(fReadShadow & X86_CR0_PE))
3163 fIntercept = true;
3164
3165 /*
3166 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3167 * bits differ between the MSW (source operand) and the read-shadow, we must
3168 * cause a VM-exit.
3169 */
3170 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3171 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3172 fIntercept = true;
3173
3174 if (fIntercept)
3175 {
3176 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3177
3178 VMXVEXITINFO ExitInfo;
3179 RT_ZERO(ExitInfo);
3180 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3181 ExitInfo.cbInstr = cbInstr;
3182
3183 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3184 if (fMemOperand)
3185 {
3186 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3187 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3188 }
3189
3190 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3191 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3192 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3193 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3194
3195 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3196 }
3197
3198 /*
3199 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3200 * CR0 guest/host mask must be left unmodified.
3201 *
3202 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3203 */
3204 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3205 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3206
3207 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3208}
3209
3210
3211/**
3212 * VMX VM-exit handler for VM-exits due to CLTS.
3213 *
3214 * @returns Strict VBox status code.
3215 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3216 * VM-exit but must not modify the guest CR0.TS bit.
3217 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3218 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3219 * CR0 fixed bits in VMX operation).
3220 * @param pVCpu The cross context virtual CPU structure.
3221 * @param cbInstr The instruction length in bytes.
3222 */
3223IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3224{
3225 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3226 Assert(pVmcs);
3227
3228 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3229 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3230
3231 /*
3232 * If CR0.TS is owned by the host:
3233 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3234 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3235 * CLTS instruction completes without clearing CR0.TS.
3236 *
3237 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3238 */
3239 if (fGstHostMask & X86_CR0_TS)
3240 {
3241 if (fReadShadow & X86_CR0_TS)
3242 {
3243 Log2(("clts: Guest intercept -> VM-exit\n"));
3244
3245 VMXVEXITINFO ExitInfo;
3246 RT_ZERO(ExitInfo);
3247 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3248 ExitInfo.cbInstr = cbInstr;
3249
3250 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3251 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3252 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3253 }
3254
3255 return VINF_VMX_MODIFIES_BEHAVIOR;
3256 }
3257
3258 /*
3259 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3260 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3261 */
3262 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3263}
3264
3265
3266/**
3267 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3268 * (CR0/CR4 write).
3269 *
3270 * @returns Strict VBox status code.
3271 * @param pVCpu The cross context virtual CPU structure.
3272 * @param iCrReg The control register (either CR0 or CR4).
3273 * @param uGuestCrX The current guest CR0/CR4.
3274 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3275 * if no VM-exit is caused.
3276 * @param iGReg The general register from which the CR0/CR4 value is
3277 * being loaded.
3278 * @param cbInstr The instruction length in bytes.
3279 */
3280IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3281 uint8_t cbInstr)
3282{
3283 Assert(puNewCrX);
3284 Assert(iCrReg == 0 || iCrReg == 4);
3285
3286 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3287 Assert(pVmcs);
3288
3289 uint64_t uGuestCrX;
3290 uint64_t fGstHostMask;
3291 uint64_t fReadShadow;
3292 if (iCrReg == 0)
3293 {
3294 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3295 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3296 fGstHostMask = pVmcs->u64Cr0Mask.u;
3297 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3298 }
3299 else
3300 {
3301 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3302 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3303 fGstHostMask = pVmcs->u64Cr4Mask.u;
3304 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3305 }
3306
3307 /*
3308 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3309 * corresponding bits differ between the source operand and the read-shadow,
3310 * we must cause a VM-exit.
3311 *
3312 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3313 */
3314 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3315 {
3316 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3317
3318 VMXVEXITINFO ExitInfo;
3319 RT_ZERO(ExitInfo);
3320 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3321 ExitInfo.cbInstr = cbInstr;
3322
3323 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3324 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3325 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3326 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3327 }
3328
3329 /*
3330 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3331 * must not be modified the instruction.
3332 *
3333 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3334 */
3335 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3336
3337 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3338}
3339
3340
3341/**
3342 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3343 *
3344 * @returns VBox strict status code.
3345 * @param pVCpu The cross context virtual CPU structure.
3346 * @param iGReg The general register to which the CR3 value is being stored.
3347 * @param cbInstr The instruction length in bytes.
3348 */
3349IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3350{
3351 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3352 Assert(pVmcs);
3353 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3354
3355 /*
3356 * If the CR3-store exiting control is set, we must cause a VM-exit.
3357 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3358 */
3359 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3360 {
3361 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3362
3363 VMXVEXITINFO ExitInfo;
3364 RT_ZERO(ExitInfo);
3365 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3366 ExitInfo.cbInstr = cbInstr;
3367
3368 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3369 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3370 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3371 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3372 }
3373
3374 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3375}
3376
3377
3378/**
3379 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3380 *
3381 * @returns VBox strict status code.
3382 * @param pVCpu The cross context virtual CPU structure.
3383 * @param uNewCr3 The new CR3 value.
3384 * @param iGReg The general register from which the CR3 value is being
3385 * loaded.
3386 * @param cbInstr The instruction length in bytes.
3387 */
3388IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3389{
3390 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3391 Assert(pVmcs);
3392
3393 /*
3394 * If the CR3-load exiting control is set and the new CR3 value does not
3395 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3396 *
3397 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3398 */
3399 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3400 {
3401 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3402 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3403
3404 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3405 {
3406 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3407 if (uNewCr3 != uCr3TargetValue)
3408 {
3409 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3410
3411 VMXVEXITINFO ExitInfo;
3412 RT_ZERO(ExitInfo);
3413 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3414 ExitInfo.cbInstr = cbInstr;
3415
3416 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3417 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3418 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3419 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3420 }
3421 }
3422 }
3423
3424 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3425}
3426
3427
3428/**
3429 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3430 *
3431 * @returns VBox strict status code.
3432 * @param pVCpu The cross context virtual CPU structure.
3433 * @param iGReg The general register to which the CR8 value is being stored.
3434 * @param cbInstr The instruction length in bytes.
3435 */
3436IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3437{
3438 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3439 Assert(pVmcs);
3440
3441 /*
3442 * If the CR8-store exiting control is set, we must cause a VM-exit.
3443 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3444 */
3445 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3446 {
3447 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3448
3449 VMXVEXITINFO ExitInfo;
3450 RT_ZERO(ExitInfo);
3451 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3452 ExitInfo.cbInstr = cbInstr;
3453
3454 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3455 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3456 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3457 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3458 }
3459
3460 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3461}
3462
3463
3464/**
3465 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3466 *
3467 * @returns VBox strict status code.
3468 * @param pVCpu The cross context virtual CPU structure.
3469 * @param iGReg The general register from which the CR8 value is being
3470 * loaded.
3471 * @param cbInstr The instruction length in bytes.
3472 */
3473IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3474{
3475 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3476 Assert(pVmcs);
3477
3478 /*
3479 * If the CR8-load exiting control is set, we must cause a VM-exit.
3480 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3481 */
3482 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3483 {
3484 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3485
3486 VMXVEXITINFO ExitInfo;
3487 RT_ZERO(ExitInfo);
3488 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3489 ExitInfo.cbInstr = cbInstr;
3490
3491 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3492 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3493 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3494 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3495 }
3496
3497 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3498}
3499
3500
3501/**
3502 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3503 * GReg,DRx' (DRx read).
3504 *
3505 * @returns VBox strict status code.
3506 * @param pVCpu The cross context virtual CPU structure.
3507 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3508 * VMXINSTRID_MOV_FROM_DRX).
3509 * @param iDrReg The debug register being accessed.
3510 * @param iGReg The general register to/from which the DRx value is being
3511 * store/loaded.
3512 * @param cbInstr The instruction length in bytes.
3513 */
3514IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3515 uint8_t cbInstr)
3516{
3517 Assert(iDrReg <= 7);
3518 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3519
3520 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3521 Assert(pVmcs);
3522
3523 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3524 {
3525 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3526 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3527 VMXVEXITINFO ExitInfo;
3528 RT_ZERO(ExitInfo);
3529 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3530 ExitInfo.cbInstr = cbInstr;
3531 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3532 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3533 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3534 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3535 }
3536
3537 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3538}
3539
3540
3541/**
3542 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3543 *
3544 * @returns VBox strict status code.
3545 * @param pVCpu The cross context virtual CPU structure.
3546 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3547 * VMXINSTRID_IO_OUT).
3548 * @param u16Port The I/O port being accessed.
3549 * @param fImm Whether the I/O port was encoded using an immediate operand
3550 * or the implicit DX register.
3551 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3552 * @param cbInstr The instruction length in bytes.
3553 */
3554IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3555 uint8_t cbInstr)
3556{
3557 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3558 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3559
3560 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3561 if (fIntercept)
3562 {
3563 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3564 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3565 VMXVEXITINFO ExitInfo;
3566 RT_ZERO(ExitInfo);
3567 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3568 ExitInfo.cbInstr = cbInstr;
3569 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3570 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3571 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3572 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3573 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3574 }
3575
3576 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3577}
3578
3579
3580/**
3581 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3582 *
3583 * @returns VBox strict status code.
3584 * @param pVCpu The cross context virtual CPU structure.
3585 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3586 * VMXINSTRID_IO_OUTS).
3587 * @param u16Port The I/O port being accessed.
3588 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3589 * @param fRep Whether the instruction has a REP prefix or not.
3590 * @param ExitInstrInfo The VM-exit instruction info. field.
3591 * @param cbInstr The instruction length in bytes.
3592 */
3593IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3594 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3595{
3596 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3597 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3598 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3599 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3600 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3601
3602 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3603 if (fIntercept)
3604 {
3605 /*
3606 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3607 */
3608 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3609 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3610 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3611 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3612 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3613
3614 uint32_t uDirection;
3615 uint64_t uGuestLinearAddr;
3616 if (uInstrId == VMXINSTRID_IO_INS)
3617 {
3618 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3619 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3620 }
3621 else
3622 {
3623 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3624 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3625 }
3626
3627 /*
3628 * If the segment is ununsable, the guest-linear address in undefined.
3629 * We shall clear it for consistency.
3630 *
3631 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3632 */
3633 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3634 uGuestLinearAddr = 0;
3635
3636 VMXVEXITINFO ExitInfo;
3637 RT_ZERO(ExitInfo);
3638 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3639 ExitInfo.cbInstr = cbInstr;
3640 ExitInfo.InstrInfo = ExitInstrInfo;
3641 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3642 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3643 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3644 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3645 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3646 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3647 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3648 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3649 }
3650
3651 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3652}
3653
3654
3655/**
3656 * VMX VM-exit handler for VM-exits due to MWAIT.
3657 *
3658 * @returns VBox strict status code.
3659 * @param pVCpu The cross context virtual CPU structure.
3660 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3661 * @param cbInstr The instruction length in bytes.
3662 */
3663IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3664{
3665 VMXVEXITINFO ExitInfo;
3666 RT_ZERO(ExitInfo);
3667 ExitInfo.uReason = VMX_EXIT_MWAIT;
3668 ExitInfo.cbInstr = cbInstr;
3669 ExitInfo.u64Qual = fMonitorHwArmed;
3670 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3671}
3672
3673
3674/**
3675 * VMX VM-exit handler for VM-exits due to PAUSE.
3676 *
3677 * @returns VBox strict status code.
3678 * @param pVCpu The cross context virtual CPU structure.
3679 * @param cbInstr The instruction length in bytes.
3680 */
3681IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3682{
3683 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3684 Assert(pVmcs);
3685
3686 /*
3687 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3688 * "PAUSE-loop exiting" control.
3689 *
3690 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3691 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3692 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3693 * a VM-exit.
3694 *
3695 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3696 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3697 */
3698 bool fIntercept = false;
3699 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3700 fIntercept = true;
3701 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3702 && pVCpu->iem.s.uCpl == 0)
3703 {
3704 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3705
3706 /*
3707 * A previous-PAUSE-tick value of 0 is used to identify the first time
3708 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3709 * consider this to be the first execution of PAUSE in a loop according
3710 * to the Intel.
3711 *
3712 * All subsequent records for the previous-PAUSE-tick we ensure that it
3713 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3714 */
3715 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3716 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3717 uint64_t const uTick = TMCpuTickGet(pVCpu);
3718 uint32_t const uPleGap = pVmcs->u32PleGap;
3719 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3720 if ( *puPrevPauseTick == 0
3721 || uTick - *puPrevPauseTick > uPleGap)
3722 *puFirstPauseLoopTick = uTick;
3723 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3724 fIntercept = true;
3725
3726 *puPrevPauseTick = uTick | 1;
3727 }
3728
3729 if (fIntercept)
3730 {
3731 VMXVEXITINFO ExitInfo;
3732 RT_ZERO(ExitInfo);
3733 ExitInfo.uReason = VMX_EXIT_PAUSE;
3734 ExitInfo.cbInstr = cbInstr;
3735 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3736 }
3737
3738 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3739}
3740
3741
3742/**
3743 * VMX VM-exit handler for VM-exits due to task switches.
3744 *
3745 * @returns VBox strict status code.
3746 * @param pVCpu The cross context virtual CPU structure.
3747 * @param enmTaskSwitch The cause of the task switch.
3748 * @param SelNewTss The selector of the new TSS.
3749 * @param cbInstr The instruction length in bytes.
3750 */
3751IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3752{
3753 /*
3754 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3755 *
3756 * If the the cause of the task switch is due to execution of CALL, IRET or the JMP
3757 * instruction or delivery of the exception generated by one of these instructions
3758 * lead to a task switch through a task gate in the IDT, we need to provide the
3759 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3760 * leaves the VM-exit instruction length field undefined.
3761 *
3762 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3763 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3764 */
3765 Assert(cbInstr <= 15);
3766
3767 uint8_t uType;
3768 switch (enmTaskSwitch)
3769 {
3770 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3771 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3772 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3773 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3774 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3775 }
3776
3777 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3778 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3779 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3780 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3781 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3782}
3783
3784
3785/**
3786 * VMX VM-exit handler for VM-exits due to expiry of the preemption timer.
3787 *
3788 * @returns VBox strict status code.
3789 * @param pVCpu The cross context virtual CPU structure.
3790 */
3791IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3792{
3793 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3794 Assert(pVmcs);
3795
3796 /* Check if the guest has enabled VMX-preemption timers in the first place. */
3797 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3798 {
3799 /*
3800 * Calculate the current VMX-preemption timer value.
3801 * Only if the value has reached zero, we cause the VM-exit.
3802 */
3803 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3804 if (!uPreemptTimer)
3805 {
3806 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3807 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3808 pVmcs->u32PreemptTimer = 0;
3809
3810 /* Clear the force-flag indicating the VMX-preemption timer no longer active. */
3811 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3812
3813 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3814 iemVmxVmcsSetExitQual(pVCpu, 0);
3815 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3816 }
3817 }
3818
3819 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3820}
3821
3822
3823/**
3824 * VMX VM-exit handler for VM-exits due to external interrupts.
3825 *
3826 * @returns VBox strict status code.
3827 * @param pVCpu The cross context virtual CPU structure.
3828 * @param uVector The external interrupt vector.
3829 * @param fIntPending Whether the external interrupt is pending or
3830 * acknowdledged in the interrupt controller.
3831 */
3832IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3833{
3834 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3835 Assert(pVmcs);
3836
3837 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3838 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3839 {
3840 if (fIntPending)
3841 {
3842 /*
3843 * If the interrupt is pending and we don't need to acknowledge the
3844 * interrupt on VM-exit, cause the VM-exit immediately.
3845 *
3846 * See Intel spec 25.2 "Other Causes Of VM Exits".
3847 */
3848 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3849 {
3850 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3851 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3852 iemVmxVmcsSetExitQual(pVCpu, 0);
3853 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3854 }
3855
3856 /*
3857 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3858 * on VM-exit, postpone VM-exit til after the interrupt controller has been
3859 * acknowledged that the interrupt has been consumed.
3860 */
3861 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3862 }
3863
3864 /*
3865 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3866 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3867 * all set, we cause the VM-exit now. We need to record the external interrupt that
3868 * just occurred in the VM-exit interruption information field.
3869 *
3870 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3871 */
3872 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3873 {
3874 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3875 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3876 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3877 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3878 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3879 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3880 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3881 iemVmxVmcsSetExitQual(pVCpu, 0);
3882 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3883 }
3884 }
3885
3886 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3887}
3888
3889
3890/**
3891 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3892 *
3893 * @returns VBox strict status code.
3894 * @param pVCpu The cross context virtual CPU structure.
3895 * @param uVector The SIPI vector.
3896 */
3897IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3898{
3899 iemVmxVmcsSetExitQual(pVCpu, uVector);
3900 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3901}
3902
3903
3904/**
3905 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3906 *
3907 * @returns VBox strict status code.
3908 * @param pVCpu The cross context virtual CPU structure.
3909 */
3910IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3911{
3912 iemVmxVmcsSetExitQual(pVCpu, 0);
3913 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3914}
3915
3916
3917/**
3918 * VMX VM-exit handler for interrupt-window VM-exits.
3919 *
3920 * @returns VBox strict status code.
3921 * @param pVCpu The cross context virtual CPU structure.
3922 */
3923IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3924{
3925 iemVmxVmcsSetExitQual(pVCpu, 0);
3926 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3927}
3928
3929
3930/**
3931 * VMX VM-exit handler for VM-exits due to delivery of an event.
3932 *
3933 * @returns VBox strict status code.
3934 * @param pVCpu The cross context virtual CPU structure.
3935 * @param uVector The interrupt / exception vector.
3936 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3937 * @param uErrCode The error code associated with the event.
3938 * @param uCr2 The CR2 value in case of a \#PF exception.
3939 * @param cbInstr The instruction length in bytes.
3940 */
3941IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3942 uint8_t cbInstr)
3943{
3944 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3945 Assert(pVmcs);
3946
3947 /*
3948 * If the event is being injected as part of VM-entry, it isn't subject to event
3949 * intercepts in the nested-guest. However, secondary exceptions that occur during
3950 * injection of any event -are- subject to event interception.
3951 *
3952 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3953 */
3954 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3955 {
3956 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3957 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3958 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3959 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3960 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3961 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3962 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3963 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3964 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3965
3966 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3967 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3968 }
3969
3970 /*
3971 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3972 * If not, the caller will continue delivery of the external interrupt as it would
3973 * normally.
3974 */
3975 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3976 {
3977 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3978 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3979 }
3980
3981 /*
3982 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3983 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3984 */
3985 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3986 bool fIntercept = false;
3987 bool fIsHwXcpt = false;
3988 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3989 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3990 {
3991 fIsHwXcpt = true;
3992 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3993 if (uVector == X86_XCPT_NMI)
3994 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3995 else
3996 {
3997 /* Page-faults are subject to masking using its error code. */
3998 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3999 if (uVector == X86_XCPT_PF)
4000 {
4001 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4002 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4003 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4004 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4005 }
4006
4007 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4008 if (fXcptBitmap & RT_BIT(uVector))
4009 fIntercept = true;
4010 }
4011 }
4012 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4013
4014 /*
4015 * Now that we've determined whether the software interrupt or hardware exception
4016 * causes a VM-exit, we need to construct the relevant VM-exit information and
4017 * cause the VM-exit.
4018 */
4019 if (fIntercept)
4020 {
4021 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4022
4023 /* Construct the rest of the event related information fields and cause the VM-exit. */
4024 uint64_t uExitQual = 0;
4025 if (fIsHwXcpt)
4026 {
4027 if (uVector == X86_XCPT_PF)
4028 uExitQual = uCr2;
4029 else if (uVector == X86_XCPT_DB)
4030 {
4031 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
4032 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4033 }
4034 }
4035
4036 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4037 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
4038 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4039 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4040 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4041 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4042 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4043 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4044 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4045 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4046 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4047
4048 /*
4049 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4050 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4051 * length.
4052 */
4053 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4054 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4055 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4056 else
4057 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4058
4059 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4060 }
4061
4062 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4063}
4064
4065
4066/**
4067 * VMX VM-exit handler for VM-exits due to a triple fault.
4068 *
4069 * @returns VBox strict status code.
4070 * @param pVCpu The cross context virtual CPU structure.
4071 */
4072IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4073{
4074 iemVmxVmcsSetExitQual(pVCpu, 0);
4075 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4076}
4077
4078
4079/**
4080 * VMX VM-exit handler for APIC-accesses.
4081 *
4082 * @param pVCpu The cross context virtual CPU structure.
4083 * @param offAccess The offset of the register being accessed.
4084 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4085 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4086 */
4087IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4088{
4089 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4090
4091 VMXAPICACCESS enmAccess;
4092 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4093 if (fInEventDelivery)
4094 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4095 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4096 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4097 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4098 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4099 else
4100 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4101
4102 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4103 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4104 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4105 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4106}
4107
4108
4109/**
4110 * VMX VM-exit handler for APIC-write VM-exits.
4111 *
4112 * @param pVCpu The cross context virtual CPU structure.
4113 * @param offApic The write to the virtual-APIC page offset that caused this
4114 * VM-exit.
4115 */
4116IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4117{
4118 Assert(offApic < XAPIC_OFF_END + 4);
4119
4120 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4121 offApic &= UINT16_C(0xfff);
4122 iemVmxVmcsSetExitQual(pVCpu, offApic);
4123 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4124}
4125
4126
4127/**
4128 * VMX VM-exit handler for virtualized-EOIs.
4129 *
4130 * @param pVCpu The cross context virtual CPU structure.
4131 */
4132IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4133{
4134 iemVmxVmcsSetExitQual(pVCpu, uVector);
4135 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4136}
4137
4138
4139/**
4140 * Sets virtual-APIC write emulation as pending.
4141 *
4142 * @param pVCpu The cross context virtual CPU structure.
4143 * @param offApic The offset in the virtual-APIC page that was written.
4144 */
4145DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4146{
4147 Assert(offApic < XAPIC_OFF_END + 4);
4148
4149 /*
4150 * Record the currently updated APIC offset, as we need this later for figuring
4151 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4152 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4153 */
4154 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4155
4156 /*
4157 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4158 * virtualization or APIC-write emulation).
4159 */
4160 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4161 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4162}
4163
4164
4165/**
4166 * Clears any pending virtual-APIC write emulation.
4167 *
4168 * @returns The virtual-APIC offset that was written before clearing it.
4169 * @param pVCpu The cross context virtual CPU structure.
4170 */
4171DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4172{
4173 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4174 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4175 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4176 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4177 return offVirtApicWrite;
4178}
4179
4180
4181/**
4182 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4183 *
4184 * @returns The register from the virtual-APIC page.
4185 * @param pVCpu The cross context virtual CPU structure.
4186 * @param offReg The offset of the register being read.
4187 */
4188DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4189{
4190 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4191 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4192 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4193 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4194 return uReg;
4195}
4196
4197
4198/**
4199 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4200 *
4201 * @returns The register from the virtual-APIC page.
4202 * @param pVCpu The cross context virtual CPU structure.
4203 * @param offReg The offset of the register being read.
4204 */
4205DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4206{
4207 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4208 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4209 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4210 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4211 return uReg;
4212}
4213
4214
4215/**
4216 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4217 *
4218 * @param pVCpu The cross context virtual CPU structure.
4219 * @param offReg The offset of the register being written.
4220 * @param uReg The register value to write.
4221 */
4222DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4223{
4224 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4225 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4226 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4227 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4228}
4229
4230
4231/**
4232 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4233 *
4234 * @param pVCpu The cross context virtual CPU structure.
4235 * @param offReg The offset of the register being written.
4236 * @param uReg The register value to write.
4237 */
4238DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4239{
4240 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4241 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4242 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4243 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4244}
4245
4246
4247/**
4248 * Sets the vector in a virtual-APIC 256-bit sparse register.
4249 *
4250 * @param pVCpu The cross context virtual CPU structure.
4251 * @param offReg The offset of the 256-bit spare register.
4252 * @param uVector The vector to set.
4253 *
4254 * @remarks This is based on our APIC device code.
4255 */
4256DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4257{
4258 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4259 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4260 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4261 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4262 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4263}
4264
4265
4266/**
4267 * Clears the vector in a virtual-APIC 256-bit sparse register.
4268 *
4269 * @param pVCpu The cross context virtual CPU structure.
4270 * @param offReg The offset of the 256-bit spare register.
4271 * @param uVector The vector to clear.
4272 *
4273 * @remarks This is based on our APIC device code.
4274 */
4275DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4276{
4277 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4278 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4279 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4280 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4281 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4282}
4283
4284
4285/**
4286 * Checks if a memory access to the APIC-access page must causes an APIC-access
4287 * VM-exit.
4288 *
4289 * @param pVCpu The cross context virtual CPU structure.
4290 * @param offAccess The offset of the register being accessed.
4291 * @param cbAccess The size of the access in bytes.
4292 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4293 * IEM_ACCESS_TYPE_WRITE).
4294 *
4295 * @remarks This must not be used for MSR-based APIC-access page accesses!
4296 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4297 */
4298IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4299{
4300 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4301 Assert(pVmcs);
4302 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4303
4304 /*
4305 * We must cause a VM-exit if any of the following are true:
4306 * - TPR shadowing isn't active.
4307 * - The access size exceeds 32-bits.
4308 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4309 *
4310 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4311 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4312 */
4313 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4314 || cbAccess > sizeof(uint32_t)
4315 || ((offAccess + cbAccess - 1) & 0xc)
4316 || offAccess >= XAPIC_OFF_END + 4)
4317 return true;
4318
4319 /*
4320 * If the access is part of an operation where we have already
4321 * virtualized a virtual-APIC write, we must cause a VM-exit.
4322 */
4323 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4324 return true;
4325
4326 /*
4327 * Check write accesses to the APIC-access page that cause VM-exits.
4328 */
4329 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4330 {
4331 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4332 {
4333 /*
4334 * With APIC-register virtualization, a write access to any of the
4335 * following registers are virtualized. Accessing any other register
4336 * causes a VM-exit.
4337 */
4338 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4339 switch (offAlignedAccess)
4340 {
4341 case XAPIC_OFF_ID:
4342 case XAPIC_OFF_TPR:
4343 case XAPIC_OFF_EOI:
4344 case XAPIC_OFF_LDR:
4345 case XAPIC_OFF_DFR:
4346 case XAPIC_OFF_SVR:
4347 case XAPIC_OFF_ESR:
4348 case XAPIC_OFF_ICR_LO:
4349 case XAPIC_OFF_ICR_HI:
4350 case XAPIC_OFF_LVT_TIMER:
4351 case XAPIC_OFF_LVT_THERMAL:
4352 case XAPIC_OFF_LVT_PERF:
4353 case XAPIC_OFF_LVT_LINT0:
4354 case XAPIC_OFF_LVT_LINT1:
4355 case XAPIC_OFF_LVT_ERROR:
4356 case XAPIC_OFF_TIMER_ICR:
4357 case XAPIC_OFF_TIMER_DCR:
4358 break;
4359 default:
4360 return true;
4361 }
4362 }
4363 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4364 {
4365 /*
4366 * With virtual-interrupt delivery, a write access to any of the
4367 * following registers are virtualized. Accessing any other register
4368 * causes a VM-exit.
4369 *
4370 * Note! The specification does not allow writing to offsets in-between
4371 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4372 */
4373 switch (offAccess)
4374 {
4375 case XAPIC_OFF_TPR:
4376 case XAPIC_OFF_EOI:
4377 case XAPIC_OFF_ICR_LO:
4378 break;
4379 default:
4380 return true;
4381 }
4382 }
4383 else
4384 {
4385 /*
4386 * Without APIC-register virtualization or virtual-interrupt delivery,
4387 * only TPR accesses are virtualized.
4388 */
4389 if (offAccess == XAPIC_OFF_TPR)
4390 { /* likely */ }
4391 else
4392 return true;
4393 }
4394 }
4395 else
4396 {
4397 /*
4398 * Check read accesses to the APIC-access page that cause VM-exits.
4399 */
4400 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4401 {
4402 /*
4403 * With APIC-register virtualization, a read access to any of the
4404 * following registers are virtualized. Accessing any other register
4405 * causes a VM-exit.
4406 */
4407 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4408 switch (offAlignedAccess)
4409 {
4410 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4411 case XAPIC_OFF_ID:
4412 case XAPIC_OFF_VERSION:
4413 case XAPIC_OFF_TPR:
4414 case XAPIC_OFF_EOI:
4415 case XAPIC_OFF_LDR:
4416 case XAPIC_OFF_DFR:
4417 case XAPIC_OFF_SVR:
4418 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4419 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4420 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4421 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4422 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4423 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4424 case XAPIC_OFF_ESR:
4425 case XAPIC_OFF_ICR_LO:
4426 case XAPIC_OFF_ICR_HI:
4427 case XAPIC_OFF_LVT_TIMER:
4428 case XAPIC_OFF_LVT_THERMAL:
4429 case XAPIC_OFF_LVT_PERF:
4430 case XAPIC_OFF_LVT_LINT0:
4431 case XAPIC_OFF_LVT_LINT1:
4432 case XAPIC_OFF_LVT_ERROR:
4433 case XAPIC_OFF_TIMER_ICR:
4434 case XAPIC_OFF_TIMER_DCR:
4435 break;
4436 default:
4437 return true;
4438 }
4439 }
4440 else
4441 {
4442 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4443 if (offAccess == XAPIC_OFF_TPR)
4444 { /* likely */ }
4445 else
4446 return true;
4447 }
4448 }
4449
4450 /* The APIC-access is virtualized, does not cause a VM-exit. */
4451 return false;
4452}
4453
4454
4455/**
4456 * Virtualizes a memory-based APIC-access where the address is not used to access
4457 * memory.
4458 *
4459 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4460 * page-faults but do not use the address to access memory.
4461 *
4462 * @param pVCpu The cross context virtual CPU structure.
4463 * @param pGCPhysAccess Pointer to the guest-physical address used.
4464 */
4465IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4466{
4467 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4468 Assert(pVmcs);
4469 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4470 Assert(pGCPhysAccess);
4471
4472 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4473 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4474 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4475
4476 if (GCPhysAccess == GCPhysApic)
4477 {
4478 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4479 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4480 uint16_t const cbAccess = 1;
4481 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4482 if (fIntercept)
4483 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4484
4485 *pGCPhysAccess = GCPhysApic | offAccess;
4486 return VINF_VMX_MODIFIES_BEHAVIOR;
4487 }
4488
4489 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4490}
4491
4492
4493/**
4494 * Virtualizes a memory-based APIC-access.
4495 *
4496 * @returns VBox strict status code.
4497 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4498 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4499 *
4500 * @param pVCpu The cross context virtual CPU structure.
4501 * @param offAccess The offset of the register being accessed (within the
4502 * APIC-access page).
4503 * @param cbAccess The size of the access in bytes.
4504 * @param pvData Pointer to the data being written or where to store the data
4505 * being read.
4506 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4507 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4508 */
4509IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4510 uint32_t fAccess)
4511{
4512 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4513 Assert(pVmcs);
4514 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4515 Assert(pvData);
4516 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4517 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4518 || (fAccess & IEM_ACCESS_INSTRUCTION));
4519
4520 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4521 if (fIntercept)
4522 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4523
4524 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4525 {
4526 /*
4527 * A write access to the APIC-access page that is virtualized (rather than
4528 * causing a VM-exit) writes data to the virtual-APIC page.
4529 */
4530 uint32_t const u32Data = *(uint32_t *)pvData;
4531 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4532
4533 /*
4534 * Record the currently updated APIC offset, as we need this later for figuring
4535 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4536 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4537 *
4538 * After completion of the current operation, we need to perform TPR virtualization,
4539 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4540 *
4541 * The current operation may be a REP-prefixed string instruction, execution of any
4542 * other instruction, or delivery of an event through the IDT.
4543 *
4544 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4545 * performed now but later after completion of the current operation.
4546 *
4547 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4548 */
4549 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4550 }
4551 else
4552 {
4553 /*
4554 * A read access from the APIC-access page that is virtualized (rather than
4555 * causing a VM-exit) returns data from the virtual-APIC page.
4556 *
4557 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4558 */
4559 Assert(cbAccess <= 4);
4560 Assert(offAccess < XAPIC_OFF_END + 4);
4561 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4562
4563 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4564 u32Data &= s_auAccessSizeMasks[cbAccess];
4565 *(uint32_t *)pvData = u32Data;
4566 }
4567
4568 return VINF_VMX_MODIFIES_BEHAVIOR;
4569}
4570
4571
4572/**
4573 * Virtualizes an MSR-based APIC read access.
4574 *
4575 * @returns VBox strict status code.
4576 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4577 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4578 * handled by the x2APIC device.
4579 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4580 * not within the range of valid MSRs, caller must raise \#GP(0).
4581 * @param pVCpu The cross context virtual CPU structure.
4582 * @param idMsr The x2APIC MSR being read.
4583 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4584 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4585 */
4586IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4587{
4588 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4589 Assert(pVmcs);
4590 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4591 Assert(pu64Value);
4592
4593 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4594 {
4595 /*
4596 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4597 * what the end of the valid x2APIC MSR range is. Hence the use of different
4598 * macros here.
4599 *
4600 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4601 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4602 */
4603 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4604 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4605 {
4606 uint16_t const offReg = (idMsr & 0xff) << 4;
4607 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4608 *pu64Value = u64Value;
4609 return VINF_VMX_MODIFIES_BEHAVIOR;
4610 }
4611 return VERR_OUT_OF_RANGE;
4612 }
4613
4614 if (idMsr == MSR_IA32_X2APIC_TPR)
4615 {
4616 uint16_t const offReg = (idMsr & 0xff) << 4;
4617 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4618 *pu64Value = u64Value;
4619 return VINF_VMX_MODIFIES_BEHAVIOR;
4620 }
4621
4622 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4623}
4624
4625
4626/**
4627 * Virtualizes an MSR-based APIC write access.
4628 *
4629 * @returns VBox strict status code.
4630 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4631 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4632 * not within the range of valid MSRs, caller must raise \#GP(0).
4633 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4634 *
4635 * @param pVCpu The cross context virtual CPU structure.
4636 * @param idMsr The x2APIC MSR being written.
4637 * @param u64Value The value of the x2APIC MSR being written.
4638 */
4639IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4640{
4641 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4642 Assert(pVmcs);
4643
4644 /*
4645 * Check if the access is to be virtualized.
4646 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4647 */
4648 if ( idMsr == MSR_IA32_X2APIC_TPR
4649 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4650 && ( idMsr == MSR_IA32_X2APIC_EOI
4651 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4652 {
4653 /* Validate the MSR write depending on the register. */
4654 switch (idMsr)
4655 {
4656 case MSR_IA32_X2APIC_TPR:
4657 case MSR_IA32_X2APIC_SELF_IPI:
4658 {
4659 if (u64Value & UINT64_C(0xffffffffffffff00))
4660 return VERR_OUT_OF_RANGE;
4661 break;
4662 }
4663 case MSR_IA32_X2APIC_EOI:
4664 {
4665 if (u64Value != 0)
4666 return VERR_OUT_OF_RANGE;
4667 break;
4668 }
4669 }
4670
4671 /* Write the MSR to the virtual-APIC page. */
4672 uint16_t const offReg = (idMsr & 0xff) << 4;
4673 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4674
4675 /*
4676 * Record the currently updated APIC offset, as we need this later for figuring
4677 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4678 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4679 */
4680 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4681
4682 return VINF_VMX_MODIFIES_BEHAVIOR;
4683 }
4684
4685 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4686}
4687
4688
4689/**
4690 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4691 *
4692 * @returns VBox status code.
4693 * @retval VINF_SUCCES when the highest set bit is found.
4694 * @retval VERR_NOT_FOUND when no bit is set.
4695 *
4696 * @param pVCpu The cross context virtual CPU structure.
4697 * @param offReg The offset of the APIC 256-bit sparse register.
4698 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4699 * set in the register. Only valid when VINF_SUCCESS is
4700 * returned.
4701 *
4702 * @remarks The format of the 256-bit sparse register here mirrors that found in
4703 * real APIC hardware.
4704 */
4705static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4706{
4707 Assert(offReg < XAPIC_OFF_END + 4);
4708 Assert(pidxHighestBit);
4709
4710 /*
4711 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4712 * However, in each fragment only the first 4 bytes are used.
4713 */
4714 uint8_t const cFrags = 8;
4715 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4716 {
4717 uint16_t const offFrag = iFrag * 16;
4718 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4719 if (!u32Frag)
4720 continue;
4721
4722 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4723 Assert(idxHighestBit > 0);
4724 --idxHighestBit;
4725 Assert(idxHighestBit <= UINT8_MAX);
4726 *pidxHighestBit = idxHighestBit;
4727 return VINF_SUCCESS;
4728 }
4729 return VERR_NOT_FOUND;
4730}
4731
4732
4733/**
4734 * Evaluates pending virtual interrupts.
4735 *
4736 * @param pVCpu The cross context virtual CPU structure.
4737 */
4738IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4739{
4740 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4741 Assert(pVmcs);
4742 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4743
4744 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4745 {
4746 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4747 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4748
4749 if ((uRvi >> 4) > (uPpr >> 4))
4750 {
4751 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4752 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4753 }
4754 else
4755 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4756 }
4757}
4758
4759
4760/**
4761 * Performs PPR virtualization.
4762 *
4763 * @returns VBox strict status code.
4764 * @param pVCpu The cross context virtual CPU structure.
4765 */
4766IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4767{
4768 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4769 Assert(pVmcs);
4770 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4771 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4772
4773 /*
4774 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4775 * or EOI-virtualization.
4776 *
4777 * See Intel spec. 29.1.3 "PPR Virtualization".
4778 */
4779 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4780 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4781
4782 uint32_t uPpr;
4783 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4784 uPpr = uTpr & 0xff;
4785 else
4786 uPpr = uSvi & 0xf0;
4787
4788 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4789 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4790}
4791
4792
4793/**
4794 * Performs VMX TPR virtualization.
4795 *
4796 * @returns VBox strict status code.
4797 * @param pVCpu The cross context virtual CPU structure.
4798 */
4799IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4800{
4801 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4802 Assert(pVmcs);
4803 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4804
4805 /*
4806 * We should have already performed the virtual-APIC write to the TPR offset
4807 * in the virtual-APIC page. We now perform TPR virtualization.
4808 *
4809 * See Intel spec. 29.1.2 "TPR Virtualization".
4810 */
4811 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4812 {
4813 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4814 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4815
4816 /*
4817 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4818 * See Intel spec. 29.1.2 "TPR Virtualization".
4819 */
4820 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4821 {
4822 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4823 iemVmxVmcsSetExitQual(pVCpu, 0);
4824 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4825 }
4826 }
4827 else
4828 {
4829 iemVmxPprVirtualization(pVCpu);
4830 iemVmxEvalPendingVirtIntrs(pVCpu);
4831 }
4832
4833 return VINF_SUCCESS;
4834}
4835
4836
4837/**
4838 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4839 * not.
4840 *
4841 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4842 * @param pVCpu The cross context virtual CPU structure.
4843 * @param uVector The interrupt that was acknowledged using an EOI.
4844 */
4845IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4846{
4847 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4848 Assert(pVmcs);
4849 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4850
4851 if (uVector < 64)
4852 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4853 if (uVector < 128)
4854 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4855 if (uVector < 192)
4856 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4857 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4858}
4859
4860
4861/**
4862 * Performs EOI virtualization.
4863 *
4864 * @returns VBox strict status code.
4865 * @param pVCpu The cross context virtual CPU structure.
4866 */
4867IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4868{
4869 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4870 Assert(pVmcs);
4871 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4872
4873 /*
4874 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4875 * and get the next guest-interrupt that's in-service (if any).
4876 *
4877 * See Intel spec. 29.1.4 "EOI Virtualization".
4878 */
4879 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4880 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4881 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4882
4883 uint8_t uVector = uSvi;
4884 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4885
4886 uVector = 0;
4887 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4888
4889 if (uVector)
4890 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4891 else
4892 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4893
4894 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4895 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4896
4897 iemVmxPprVirtualization(pVCpu);
4898 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4899 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4900 iemVmxEvalPendingVirtIntrs(pVCpu);
4901 return VINF_SUCCESS;
4902}
4903
4904
4905/**
4906 * Performs self-IPI virtualization.
4907 *
4908 * @returns VBox strict status code.
4909 * @param pVCpu The cross context virtual CPU structure.
4910 */
4911IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4912{
4913 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4914 Assert(pVmcs);
4915 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4916
4917 /*
4918 * We should have already performed the virtual-APIC write to the self-IPI offset
4919 * in the virtual-APIC page. We now perform self-IPI virtualization.
4920 *
4921 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4922 */
4923 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4924 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4925 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
4926 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4927 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4928 if (uVector > uRvi)
4929 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4930 iemVmxEvalPendingVirtIntrs(pVCpu);
4931 return VINF_SUCCESS;
4932}
4933
4934
4935/**
4936 * Performs VMX APIC-write emulation.
4937 *
4938 * @returns VBox strict status code.
4939 * @param pVCpu The cross context virtual CPU structure.
4940 */
4941IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4942{
4943 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4944 Assert(pVmcs);
4945
4946 /*
4947 * Perform APIC-write emulation based on the virtual-APIC register written.
4948 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4949 */
4950 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4951 VBOXSTRICTRC rcStrict;
4952 switch (offApicWrite)
4953 {
4954 case XAPIC_OFF_TPR:
4955 {
4956 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4957 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4958 uTpr &= UINT32_C(0x000000ff);
4959 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4960 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4961 rcStrict = iemVmxTprVirtualization(pVCpu);
4962 break;
4963 }
4964
4965 case XAPIC_OFF_EOI:
4966 {
4967 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4968 {
4969 /* Clear VEOI and perform EOI virtualization. */
4970 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4971 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4972 rcStrict = iemVmxEoiVirtualization(pVCpu);
4973 }
4974 else
4975 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4976 break;
4977 }
4978
4979 case XAPIC_OFF_ICR_LO:
4980 {
4981 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4982 {
4983 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4984 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4985 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4986 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4987 if ( !(uIcrLo & fIcrLoMb0)
4988 && (uIcrLo & fIcrLoMb1))
4989 {
4990 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4991 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4992 }
4993 else
4994 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4995 }
4996 else
4997 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4998 break;
4999 }
5000
5001 case XAPIC_OFF_ICR_HI:
5002 {
5003 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5004 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5005 uIcrHi &= UINT32_C(0xff000000);
5006 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5007 rcStrict = VINF_SUCCESS;
5008 break;
5009 }
5010
5011 default:
5012 {
5013 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5014 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5015 break;
5016 }
5017 }
5018
5019 return rcStrict;
5020}
5021
5022
5023/**
5024 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5025 *
5026 * @param pVCpu The cross context virtual CPU structure.
5027 * @param pszInstr The VMX instruction name (for logging purposes).
5028 */
5029IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5030{
5031 /*
5032 * Guest Control Registers, Debug Registers, and MSRs.
5033 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5034 */
5035 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5036 const char *const pszFailure = "VM-exit";
5037 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5038
5039 /* CR0 reserved bits. */
5040 {
5041 /* CR0 MB1 bits. */
5042 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5043 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5044 if (fUnrestrictedGuest)
5045 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5046 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
5047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5048
5049 /* CR0 MBZ bits. */
5050 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5051 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
5052 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5053
5054 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5055 if ( !fUnrestrictedGuest
5056 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5057 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5059 }
5060
5061 /* CR4 reserved bits. */
5062 {
5063 /* CR4 MB1 bits. */
5064 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5065 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
5066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5067
5068 /* CR4 MBZ bits. */
5069 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5070 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
5071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5072 }
5073
5074 /* DEBUGCTL MSR. */
5075 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5076 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5077 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5078
5079 /* 64-bit CPU checks. */
5080 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5081 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5082 {
5083 if (fGstInLongMode)
5084 {
5085 /* PAE must be set. */
5086 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5087 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5091 }
5092 else
5093 {
5094 /* PCIDE should not be set. */
5095 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5096 { /* likely */ }
5097 else
5098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5099 }
5100
5101 /* CR3. */
5102 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5103 { /* likely */ }
5104 else
5105 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5106
5107 /* DR7. */
5108 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5109 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5111
5112 /* SYSENTER ESP and SYSENTER EIP. */
5113 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5114 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5115 { /* likely */ }
5116 else
5117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5118 }
5119
5120 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5121 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5122
5123 /* PAT MSR. */
5124 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5125 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5127
5128 /* EFER MSR. */
5129 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5130 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5131 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5133
5134 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5135 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5136 if ( fGstInLongMode == fGstLma
5137 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5138 || fGstLma == fGstLme))
5139 { /* likely */ }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5142
5143 /* We don't support IA32_BNDCFGS MSR yet. */
5144 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5145
5146 NOREF(pszInstr);
5147 NOREF(pszFailure);
5148 return VINF_SUCCESS;
5149}
5150
5151
5152/**
5153 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5154 *
5155 * @param pVCpu The cross context virtual CPU structure.
5156 * @param pszInstr The VMX instruction name (for logging purposes).
5157 */
5158IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5159{
5160 /*
5161 * Segment registers.
5162 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5163 */
5164 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5165 const char *const pszFailure = "VM-exit";
5166 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5167 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5168 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5169
5170 /* Selectors. */
5171 if ( !fGstInV86Mode
5172 && !fUnrestrictedGuest
5173 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5175
5176 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5177 {
5178 CPUMSELREG SelReg;
5179 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5180 if (RT_LIKELY(rc == VINF_SUCCESS))
5181 { /* likely */ }
5182 else
5183 return rc;
5184
5185 /*
5186 * Virtual-8086 mode checks.
5187 */
5188 if (fGstInV86Mode)
5189 {
5190 /* Base address. */
5191 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5192 { /* likely */ }
5193 else
5194 {
5195 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5197 }
5198
5199 /* Limit. */
5200 if (SelReg.u32Limit == 0xffff)
5201 { /* likely */ }
5202 else
5203 {
5204 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5206 }
5207
5208 /* Attribute. */
5209 if (SelReg.Attr.u == 0xf3)
5210 { /* likely */ }
5211 else
5212 {
5213 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5215 }
5216
5217 /* We're done; move to checking the next segment. */
5218 continue;
5219 }
5220
5221 /* Checks done by 64-bit CPUs. */
5222 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5223 {
5224 /* Base address. */
5225 if ( iSegReg == X86_SREG_FS
5226 || iSegReg == X86_SREG_GS)
5227 {
5228 if (X86_IS_CANONICAL(SelReg.u64Base))
5229 { /* likely */ }
5230 else
5231 {
5232 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5234 }
5235 }
5236 else if (iSegReg == X86_SREG_CS)
5237 {
5238 if (!RT_HI_U32(SelReg.u64Base))
5239 { /* likely */ }
5240 else
5241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5242 }
5243 else
5244 {
5245 if ( SelReg.Attr.n.u1Unusable
5246 || !RT_HI_U32(SelReg.u64Base))
5247 { /* likely */ }
5248 else
5249 {
5250 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5252 }
5253 }
5254 }
5255
5256 /*
5257 * Checks outside Virtual-8086 mode.
5258 */
5259 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5260 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5261 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5262 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5263 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5264 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5265 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5266 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5267
5268 /* Code or usable segment. */
5269 if ( iSegReg == X86_SREG_CS
5270 || fUsable)
5271 {
5272 /* Reserved bits (bits 31:17 and bits 11:8). */
5273 if (!(SelReg.Attr.u & 0xfffe0f00))
5274 { /* likely */ }
5275 else
5276 {
5277 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5279 }
5280
5281 /* Descriptor type. */
5282 if (fCodeDataSeg)
5283 { /* likely */ }
5284 else
5285 {
5286 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5288 }
5289
5290 /* Present. */
5291 if (fPresent)
5292 { /* likely */ }
5293 else
5294 {
5295 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5297 }
5298
5299 /* Granularity. */
5300 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5301 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5302 { /* likely */ }
5303 else
5304 {
5305 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5307 }
5308 }
5309
5310 if (iSegReg == X86_SREG_CS)
5311 {
5312 /* Segment Type and DPL. */
5313 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5314 && fUnrestrictedGuest)
5315 {
5316 if (uDpl == 0)
5317 { /* likely */ }
5318 else
5319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5320 }
5321 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5322 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5323 {
5324 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5325 if (uDpl == AttrSs.n.u2Dpl)
5326 { /* likely */ }
5327 else
5328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5329 }
5330 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5331 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5332 {
5333 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5334 if (uDpl <= AttrSs.n.u2Dpl)
5335 { /* likely */ }
5336 else
5337 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5338 }
5339 else
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5341
5342 /* Def/Big. */
5343 if ( fGstInLongMode
5344 && fSegLong)
5345 {
5346 if (uDefBig == 0)
5347 { /* likely */ }
5348 else
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5350 }
5351 }
5352 else if (iSegReg == X86_SREG_SS)
5353 {
5354 /* Segment Type. */
5355 if ( !fUsable
5356 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5357 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5358 { /* likely */ }
5359 else
5360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5361
5362 /* DPL. */
5363 if (fUnrestrictedGuest)
5364 {
5365 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5366 { /* likely */ }
5367 else
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5369 }
5370 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5371 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5372 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
5373 {
5374 if (uDpl == 0)
5375 { /* likely */ }
5376 else
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5378 }
5379 }
5380 else
5381 {
5382 /* DS, ES, FS, GS. */
5383 if (fUsable)
5384 {
5385 /* Segment type. */
5386 if (uSegType & X86_SEL_TYPE_ACCESSED)
5387 { /* likely */ }
5388 else
5389 {
5390 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5392 }
5393
5394 if ( !(uSegType & X86_SEL_TYPE_CODE)
5395 || (uSegType & X86_SEL_TYPE_READ))
5396 { /* likely */ }
5397 else
5398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5399
5400 /* DPL. */
5401 if ( !fUnrestrictedGuest
5402 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5403 {
5404 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5405 { /* likely */ }
5406 else
5407 {
5408 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5410 }
5411 }
5412 }
5413 }
5414 }
5415
5416 /*
5417 * LDTR.
5418 */
5419 {
5420 CPUMSELREG Ldtr;
5421 Ldtr.Sel = pVmcs->GuestLdtr;
5422 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5423 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5424 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5425
5426 if (!Ldtr.Attr.n.u1Unusable)
5427 {
5428 /* Selector. */
5429 if (!(Ldtr.Sel & X86_SEL_LDT))
5430 { /* likely */ }
5431 else
5432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5433
5434 /* Base. */
5435 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5436 {
5437 if (X86_IS_CANONICAL(Ldtr.u64Base))
5438 { /* likely */ }
5439 else
5440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5441 }
5442
5443 /* Attributes. */
5444 /* Reserved bits (bits 31:17 and bits 11:8). */
5445 if (!(Ldtr.Attr.u & 0xfffe0f00))
5446 { /* likely */ }
5447 else
5448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5449
5450 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5451 { /* likely */ }
5452 else
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5454
5455 if (!Ldtr.Attr.n.u1DescType)
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5459
5460 if (Ldtr.Attr.n.u1Present)
5461 { /* likely */ }
5462 else
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5464
5465 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5466 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5470 }
5471 }
5472
5473 /*
5474 * TR.
5475 */
5476 {
5477 CPUMSELREG Tr;
5478 Tr.Sel = pVmcs->GuestTr;
5479 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5480 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5481 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5482
5483 /* Selector. */
5484 if (!(Tr.Sel & X86_SEL_LDT))
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5488
5489 /* Base. */
5490 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5491 {
5492 if (X86_IS_CANONICAL(Tr.u64Base))
5493 { /* likely */ }
5494 else
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5496 }
5497
5498 /* Attributes. */
5499 /* Reserved bits (bits 31:17 and bits 11:8). */
5500 if (!(Tr.Attr.u & 0xfffe0f00))
5501 { /* likely */ }
5502 else
5503 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5504
5505 if (!Tr.Attr.n.u1Unusable)
5506 { /* likely */ }
5507 else
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5509
5510 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5511 || ( !fGstInLongMode
5512 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5513 { /* likely */ }
5514 else
5515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5516
5517 if (!Tr.Attr.n.u1DescType)
5518 { /* likely */ }
5519 else
5520 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5521
5522 if (Tr.Attr.n.u1Present)
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5526
5527 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5528 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5529 { /* likely */ }
5530 else
5531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5532 }
5533
5534 NOREF(pszInstr);
5535 NOREF(pszFailure);
5536 return VINF_SUCCESS;
5537}
5538
5539
5540/**
5541 * Checks guest GDTR and IDTR as part of VM-entry.
5542 *
5543 * @param pVCpu The cross context virtual CPU structure.
5544 * @param pszInstr The VMX instruction name (for logging purposes).
5545 */
5546IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5547{
5548 /*
5549 * GDTR and IDTR.
5550 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5551 */
5552 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5553 const char *const pszFailure = "VM-exit";
5554
5555 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5556 {
5557 /* Base. */
5558 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5562
5563 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5567 }
5568
5569 /* Limit. */
5570 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5574
5575 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5579
5580 NOREF(pszInstr);
5581 NOREF(pszFailure);
5582 return VINF_SUCCESS;
5583}
5584
5585
5586/**
5587 * Checks guest RIP and RFLAGS as part of VM-entry.
5588 *
5589 * @param pVCpu The cross context virtual CPU structure.
5590 * @param pszInstr The VMX instruction name (for logging purposes).
5591 */
5592IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5593{
5594 /*
5595 * RIP and RFLAGS.
5596 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5597 */
5598 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5599 const char *const pszFailure = "VM-exit";
5600 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5601
5602 /* RIP. */
5603 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5604 {
5605 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5606 if ( !fGstInLongMode
5607 || !AttrCs.n.u1Long)
5608 {
5609 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5610 { /* likely */ }
5611 else
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5613 }
5614
5615 if ( fGstInLongMode
5616 && AttrCs.n.u1Long)
5617 {
5618 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5619 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5620 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5624 }
5625 }
5626
5627 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5628 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5629 : pVmcs->u64GuestRFlags.s.Lo;
5630 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5631 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5635
5636 if ( fGstInLongMode
5637 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5638 {
5639 if (!(uGuestRFlags & X86_EFL_VM))
5640 { /* likely */ }
5641 else
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5643 }
5644
5645 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5646 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5647 {
5648 if (uGuestRFlags & X86_EFL_IF)
5649 { /* likely */ }
5650 else
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5652 }
5653
5654 NOREF(pszInstr);
5655 NOREF(pszFailure);
5656 return VINF_SUCCESS;
5657}
5658
5659
5660/**
5661 * Checks guest non-register state as part of VM-entry.
5662 *
5663 * @param pVCpu The cross context virtual CPU structure.
5664 * @param pszInstr The VMX instruction name (for logging purposes).
5665 */
5666IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5667{
5668 /*
5669 * Guest non-register state.
5670 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5671 */
5672 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5673 const char *const pszFailure = "VM-exit";
5674
5675 /*
5676 * Activity state.
5677 */
5678 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5679 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5680 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5681 { /* likely */ }
5682 else
5683 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5684
5685 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5686 if ( !AttrSs.n.u2Dpl
5687 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5688 { /* likely */ }
5689 else
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5691
5692 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5693 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5694 {
5695 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5696 { /* likely */ }
5697 else
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5699 }
5700
5701 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5702 {
5703 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5704 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5705 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5706 switch (pVmcs->u32GuestActivityState)
5707 {
5708 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5709 {
5710 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5711 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5712 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5713 && ( uVector == X86_XCPT_DB
5714 || uVector == X86_XCPT_MC))
5715 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5716 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5717 { /* likely */ }
5718 else
5719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5720 break;
5721 }
5722
5723 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5724 {
5725 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5726 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5727 && uVector == X86_XCPT_MC))
5728 { /* likely */ }
5729 else
5730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5731 break;
5732 }
5733
5734 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5735 default:
5736 break;
5737 }
5738 }
5739
5740 /*
5741 * Interruptibility state.
5742 */
5743 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5744 { /* likely */ }
5745 else
5746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5747
5748 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5749 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5750 { /* likely */ }
5751 else
5752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5753
5754 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5755 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5756 { /* likely */ }
5757 else
5758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5759
5760 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5761 {
5762 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5763 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5764 {
5765 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5766 { /* likely */ }
5767 else
5768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5769 }
5770 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5771 {
5772 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5773 { /* likely */ }
5774 else
5775 {
5776 /*
5777 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5778 * We update the VM-exit qualification only when blocking-by-STI is set
5779 * without blocking-by-MovSS being set. Although in practise it does not
5780 * make much difference since the order of checks are implementation defined.
5781 */
5782 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5783 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5785 }
5786
5787 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5788 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5789 { /* likely */ }
5790 else
5791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5792 }
5793 }
5794
5795 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5796 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5797 { /* likely */ }
5798 else
5799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5800
5801 /* We don't support SGX yet. So enclave-interruption must not be set. */
5802 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5803 { /* likely */ }
5804 else
5805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5806
5807 /*
5808 * Pending debug exceptions.
5809 */
5810 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5811 ? pVmcs->u64GuestPendingDbgXcpt.u
5812 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5813 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5814 { /* likely */ }
5815 else
5816 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5817
5818 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5819 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5820 {
5821 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5822 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5823 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5825
5826 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5827 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5828 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5830 }
5831
5832 /* We don't support RTM (Real-time Transactional Memory) yet. */
5833 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5835
5836 /*
5837 * VMCS link pointer.
5838 */
5839 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5840 {
5841 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5842 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5843 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5844 { /* likely */ }
5845 else
5846 {
5847 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5849 }
5850
5851 /* Validate the address. */
5852 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5853 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5854 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5855 {
5856 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5858 }
5859
5860 /* Read the VMCS-link pointer from guest memory. */
5861 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5862 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5863 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5864 if (RT_FAILURE(rc))
5865 {
5866 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5868 }
5869
5870 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5871 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5872 { /* likely */ }
5873 else
5874 {
5875 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5877 }
5878
5879 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5880 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5881 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5882 { /* likely */ }
5883 else
5884 {
5885 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5887 }
5888
5889 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5890 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5891 }
5892
5893 NOREF(pszInstr);
5894 NOREF(pszFailure);
5895 return VINF_SUCCESS;
5896}
5897
5898
5899/**
5900 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5901 * VM-entry.
5902 *
5903 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5904 * @param pVCpu The cross context virtual CPU structure.
5905 * @param pszInstr The VMX instruction name (for logging purposes).
5906 * @param pVmcs Pointer to the virtual VMCS.
5907 */
5908IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5909{
5910 /*
5911 * Check PDPTEs.
5912 * See Intel spec. 4.4.1 "PDPTE Registers".
5913 */
5914 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5915 const char *const pszFailure = "VM-exit";
5916
5917 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5918 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5919 if (RT_SUCCESS(rc))
5920 {
5921 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5922 {
5923 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5924 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5925 { /* likely */ }
5926 else
5927 {
5928 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5929 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5931 }
5932 }
5933 }
5934 else
5935 {
5936 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5938 }
5939
5940 NOREF(pszFailure);
5941 NOREF(pszInstr);
5942 return rc;
5943}
5944
5945
5946/**
5947 * Checks guest PDPTEs as part of VM-entry.
5948 *
5949 * @param pVCpu The cross context virtual CPU structure.
5950 * @param pszInstr The VMX instruction name (for logging purposes).
5951 */
5952IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5953{
5954 /*
5955 * Guest PDPTEs.
5956 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5957 */
5958 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5959 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5960
5961 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5962 int rc;
5963 if ( !fGstInLongMode
5964 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5965 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5966 {
5967 /*
5968 * We don't support nested-paging for nested-guests yet.
5969 *
5970 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5971 * rather we need to check the PDPTEs referenced by the guest CR3.
5972 */
5973 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5974 }
5975 else
5976 rc = VINF_SUCCESS;
5977 return rc;
5978}
5979
5980
5981/**
5982 * Checks guest-state as part of VM-entry.
5983 *
5984 * @returns VBox status code.
5985 * @param pVCpu The cross context virtual CPU structure.
5986 * @param pszInstr The VMX instruction name (for logging purposes).
5987 */
5988IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5989{
5990 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5991 if (RT_SUCCESS(rc))
5992 {
5993 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5994 if (RT_SUCCESS(rc))
5995 {
5996 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5997 if (RT_SUCCESS(rc))
5998 {
5999 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6000 if (RT_SUCCESS(rc))
6001 {
6002 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6003 if (RT_SUCCESS(rc))
6004 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6005 }
6006 }
6007 }
6008 }
6009 return rc;
6010}
6011
6012
6013/**
6014 * Checks host-state as part of VM-entry.
6015 *
6016 * @returns VBox status code.
6017 * @param pVCpu The cross context virtual CPU structure.
6018 * @param pszInstr The VMX instruction name (for logging purposes).
6019 */
6020IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6021{
6022 /*
6023 * Host Control Registers and MSRs.
6024 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6025 */
6026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6027 const char * const pszFailure = "VMFail";
6028
6029 /* CR0 reserved bits. */
6030 {
6031 /* CR0 MB1 bits. */
6032 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6033 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
6034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6035
6036 /* CR0 MBZ bits. */
6037 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6038 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
6039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6040 }
6041
6042 /* CR4 reserved bits. */
6043 {
6044 /* CR4 MB1 bits. */
6045 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6046 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
6047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6048
6049 /* CR4 MBZ bits. */
6050 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6051 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
6052 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6053 }
6054
6055 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6056 {
6057 /* CR3 reserved bits. */
6058 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6059 { /* likely */ }
6060 else
6061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6062
6063 /* SYSENTER ESP and SYSENTER EIP. */
6064 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6065 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6066 { /* likely */ }
6067 else
6068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6069 }
6070
6071 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6072 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6073
6074 /* PAT MSR. */
6075 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6076 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6077 { /* likely */ }
6078 else
6079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6080
6081 /* EFER MSR. */
6082 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6083 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6084 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6085 { /* likely */ }
6086 else
6087 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6088
6089 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6090 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6091 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6092 if ( fHostInLongMode == fHostLma
6093 && fHostInLongMode == fHostLme)
6094 { /* likely */ }
6095 else
6096 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6097
6098 /*
6099 * Host Segment and Descriptor-Table Registers.
6100 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6101 */
6102 /* Selector RPL and TI. */
6103 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6104 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6105 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6106 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6107 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6108 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6109 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6110 { /* likely */ }
6111 else
6112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6113
6114 /* CS and TR selectors cannot be 0. */
6115 if ( pVmcs->HostCs
6116 && pVmcs->HostTr)
6117 { /* likely */ }
6118 else
6119 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6120
6121 /* SS cannot be 0 if 32-bit host. */
6122 if ( fHostInLongMode
6123 || pVmcs->HostSs)
6124 { /* likely */ }
6125 else
6126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6127
6128 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6129 {
6130 /* FS, GS, GDTR, IDTR, TR base address. */
6131 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6132 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6133 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6134 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6135 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6139 }
6140
6141 /*
6142 * Host address-space size for 64-bit CPUs.
6143 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6144 */
6145 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6146 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6147 {
6148 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6149
6150 /* Logical processor in IA-32e mode. */
6151 if (fCpuInLongMode)
6152 {
6153 if (fHostInLongMode)
6154 {
6155 /* PAE must be set. */
6156 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6157 { /* likely */ }
6158 else
6159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6160
6161 /* RIP must be canonical. */
6162 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6163 { /* likely */ }
6164 else
6165 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6166 }
6167 else
6168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6169 }
6170 else
6171 {
6172 /* Logical processor is outside IA-32e mode. */
6173 if ( !fGstInLongMode
6174 && !fHostInLongMode)
6175 {
6176 /* PCIDE should not be set. */
6177 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6181
6182 /* The high 32-bits of RIP MBZ. */
6183 if (!pVmcs->u64HostRip.s.Hi)
6184 { /* likely */ }
6185 else
6186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6187 }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6190 }
6191 }
6192 else
6193 {
6194 /* Host address-space size for 32-bit CPUs. */
6195 if ( !fGstInLongMode
6196 && !fHostInLongMode)
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6200 }
6201
6202 NOREF(pszInstr);
6203 NOREF(pszFailure);
6204 return VINF_SUCCESS;
6205}
6206
6207
6208/**
6209 * Checks VM-entry controls fields as part of VM-entry.
6210 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6211 *
6212 * @returns VBox status code.
6213 * @param pVCpu The cross context virtual CPU structure.
6214 * @param pszInstr The VMX instruction name (for logging purposes).
6215 */
6216IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6217{
6218 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6219 const char * const pszFailure = "VMFail";
6220
6221 /* VM-entry controls. */
6222 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6223 if (~pVmcs->u32EntryCtls & EntryCtls.n.allowed0)
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6225
6226 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
6227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6228
6229 /* Event injection. */
6230 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6231 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6232 {
6233 /* Type and vector. */
6234 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6235 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6236 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6237 if ( !uRsvd
6238 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6239 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6243
6244 /* Exception error code. */
6245 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6246 {
6247 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6248 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6249 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6250 { /* likely */ }
6251 else
6252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6253
6254 /* Exceptions that provide an error code. */
6255 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6256 && ( uVector == X86_XCPT_DF
6257 || uVector == X86_XCPT_TS
6258 || uVector == X86_XCPT_NP
6259 || uVector == X86_XCPT_SS
6260 || uVector == X86_XCPT_GP
6261 || uVector == X86_XCPT_PF
6262 || uVector == X86_XCPT_AC))
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6266
6267 /* Exception error-code reserved bits. */
6268 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6269 { /* likely */ }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6272
6273 /* Injecting a software interrupt, software exception or privileged software exception. */
6274 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6275 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6276 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6277 {
6278 /* Instruction length must be in the range 0-15. */
6279 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6280 { /* likely */ }
6281 else
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6283
6284 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6285 if ( pVmcs->u32EntryInstrLen == 0
6286 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6288 }
6289 }
6290 }
6291
6292 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6293 if (pVmcs->u32EntryMsrLoadCount)
6294 {
6295 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6296 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6297 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6299 }
6300
6301 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6302 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6303
6304 NOREF(pszInstr);
6305 NOREF(pszFailure);
6306 return VINF_SUCCESS;
6307}
6308
6309
6310/**
6311 * Checks VM-exit controls fields as part of VM-entry.
6312 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6313 *
6314 * @returns VBox status code.
6315 * @param pVCpu The cross context virtual CPU structure.
6316 * @param pszInstr The VMX instruction name (for logging purposes).
6317 */
6318IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6319{
6320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6321 const char * const pszFailure = "VMFail";
6322
6323 /* VM-exit controls. */
6324 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6325 if (~pVmcs->u32ExitCtls & ExitCtls.n.allowed0)
6326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6327
6328 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
6329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6330
6331 /* Save preemption timer without activating it. */
6332 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6333 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6334 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6335
6336 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6337 if (pVmcs->u32ExitMsrStoreCount)
6338 {
6339 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6340 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6341 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6343 }
6344
6345 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6346 if (pVmcs->u32ExitMsrLoadCount)
6347 {
6348 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6349 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6350 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6352 }
6353
6354 NOREF(pszInstr);
6355 NOREF(pszFailure);
6356 return VINF_SUCCESS;
6357}
6358
6359
6360/**
6361 * Checks VM-execution controls fields as part of VM-entry.
6362 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6363 *
6364 * @returns VBox status code.
6365 * @param pVCpu The cross context virtual CPU structure.
6366 * @param pszInstr The VMX instruction name (for logging purposes).
6367 *
6368 * @remarks This may update secondary-processor based VM-execution control fields
6369 * in the current VMCS if necessary.
6370 */
6371IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6372{
6373 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6374 const char * const pszFailure = "VMFail";
6375
6376 /* Pin-based VM-execution controls. */
6377 {
6378 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6379 if (~pVmcs->u32PinCtls & PinCtls.n.allowed0)
6380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6381
6382 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6384 }
6385
6386 /* Processor-based VM-execution controls. */
6387 {
6388 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6389 if (~pVmcs->u32ProcCtls & ProcCtls.n.allowed0)
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6391
6392 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
6393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6394 }
6395
6396 /* Secondary processor-based VM-execution controls. */
6397 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6398 {
6399 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6400 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0)
6401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6402
6403 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
6404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6405 }
6406 else
6407 Assert(!pVmcs->u32ProcCtls2);
6408
6409 /* CR3-target count. */
6410 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6411 { /* likely */ }
6412 else
6413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6414
6415 /* I/O bitmaps physical addresses. */
6416 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6417 {
6418 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6419 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6420 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6422
6423 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6424 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6425 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6427 }
6428
6429 /* MSR bitmap physical address. */
6430 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6431 {
6432 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6433 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6434 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6435 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6437
6438 /* Read the MSR bitmap. */
6439 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6440 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6441 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6442 if (RT_FAILURE(rc))
6443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6444 }
6445
6446 /* TPR shadow related controls. */
6447 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6448 {
6449 /* Virtual-APIC page physical address. */
6450 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6451 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6452 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6453 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6455
6456 /* Read the Virtual-APIC page. */
6457 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6458 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6459 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6460 if (RT_FAILURE(rc))
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6462
6463 /* TPR threshold without virtual-interrupt delivery. */
6464 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6465 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6467
6468 /* TPR threshold and VTPR. */
6469 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6470 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6471 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6472 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6473 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6475 }
6476 else
6477 {
6478 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6479 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6480 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6481 { /* likely */ }
6482 else
6483 {
6484 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6486 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6488 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6489 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6490 }
6491 }
6492
6493 /* NMI exiting and virtual-NMIs. */
6494 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6495 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6496 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6497
6498 /* Virtual-NMIs and NMI-window exiting. */
6499 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6500 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6502
6503 /* Virtualize APIC accesses. */
6504 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6505 {
6506 /* APIC-access physical address. */
6507 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6508 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6509 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6510 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6512
6513 /*
6514 * Disallow APIC-access page and virtual-APIC page from being the same address.
6515 * Note! This is not an Intel requirement, but one imposed by our implementation.
6516 */
6517 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6518 * redirecting accesses between the APIC-access page and the virtual-APIC
6519 * page. If any nested hypervisor requires this, we can implement it later. */
6520 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6521 {
6522 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6523 if (GCPhysVirtApic == GCPhysApicAccess)
6524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6525 }
6526
6527 /*
6528 * Register the handler for the APIC-access page.
6529 *
6530 * We don't deregister the APIC-access page handler during the VM-exit as a different
6531 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6532 *
6533 * We leave the page registered until the first access that happens outside VMX non-root
6534 * mode. Guest software is allowed to access structures such as the APIC-access page
6535 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6536 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6537 *
6538 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6539 */
6540 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6541 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6542 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6543 if (RT_FAILURE(rc))
6544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6545 }
6546
6547 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6548 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6549 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6551
6552 /* Virtual-interrupt delivery requires external interrupt exiting. */
6553 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6554 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6556
6557 /* VPID. */
6558 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6559 || pVmcs->u16Vpid != 0)
6560 { /* likely */ }
6561 else
6562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6563
6564 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6565 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6566 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6567 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6568 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6569 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6570 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6571
6572 /* VMCS shadowing. */
6573 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6574 {
6575 /* VMREAD-bitmap physical address. */
6576 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6577 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6578 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6579 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6581
6582 /* VMWRITE-bitmap physical address. */
6583 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6584 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6585 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6586 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6588
6589 /* Read the VMREAD-bitmap. */
6590 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6591 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6592 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6593 if (RT_FAILURE(rc))
6594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6595
6596 /* Read the VMWRITE-bitmap. */
6597 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6598 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6599 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6600 if (RT_FAILURE(rc))
6601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6602 }
6603
6604 NOREF(pszInstr);
6605 NOREF(pszFailure);
6606 return VINF_SUCCESS;
6607}
6608
6609
6610/**
6611 * Loads the guest control registers, debug register and some MSRs as part of
6612 * VM-entry.
6613 *
6614 * @param pVCpu The cross context virtual CPU structure.
6615 */
6616IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6617{
6618 /*
6619 * Load guest control registers, debug registers and MSRs.
6620 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6621 */
6622 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6623 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6624 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6625 CPUMSetGuestCR0(pVCpu, uGstCr0);
6626 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6627 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6628
6629 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6630 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6631
6632 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6633 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6634 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6635
6636 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6637 {
6638 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6639
6640 /* EFER MSR. */
6641 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6642 {
6643 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6644 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6645 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6646 if (fGstInLongMode)
6647 {
6648 /* If the nested-guest is in long mode, LMA and LME are both set. */
6649 Assert(fGstPaging);
6650 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6651 }
6652 else
6653 {
6654 /*
6655 * If the nested-guest is outside long mode:
6656 * - With paging: LMA is cleared, LME is cleared.
6657 * - Without paging: LMA is cleared, LME is left unmodified.
6658 */
6659 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6660 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6661 }
6662 }
6663 /* else: see below. */
6664 }
6665
6666 /* PAT MSR. */
6667 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6668 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6669
6670 /* EFER MSR. */
6671 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6672 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6673
6674 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6675 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6676
6677 /* We don't support IA32_BNDCFGS MSR yet. */
6678 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6679
6680 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6681}
6682
6683
6684/**
6685 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6686 *
6687 * @param pVCpu The cross context virtual CPU structure.
6688 */
6689IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6690{
6691 /*
6692 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6693 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6694 */
6695 /* CS, SS, ES, DS, FS, GS. */
6696 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6697 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6698 {
6699 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6700 CPUMSELREG VmcsSelReg;
6701 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6702 AssertRC(rc); NOREF(rc);
6703 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6704 {
6705 pGstSelReg->Sel = VmcsSelReg.Sel;
6706 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6707 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6708 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6709 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6710 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6711 }
6712 else
6713 {
6714 pGstSelReg->Sel = VmcsSelReg.Sel;
6715 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6716 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6717 switch (iSegReg)
6718 {
6719 case X86_SREG_CS:
6720 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6721 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6722 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6723 break;
6724
6725 case X86_SREG_SS:
6726 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6727 pGstSelReg->u32Limit = 0;
6728 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6729 break;
6730
6731 case X86_SREG_ES:
6732 case X86_SREG_DS:
6733 pGstSelReg->u64Base = 0;
6734 pGstSelReg->u32Limit = 0;
6735 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6736 break;
6737
6738 case X86_SREG_FS:
6739 case X86_SREG_GS:
6740 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6741 pGstSelReg->u32Limit = 0;
6742 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6743 break;
6744 }
6745 Assert(pGstSelReg->Attr.n.u1Unusable);
6746 }
6747 }
6748
6749 /* LDTR. */
6750 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6751 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6752 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6753 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6754 {
6755 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6756 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6757 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6758 }
6759 else
6760 {
6761 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6762 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6763 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6764 }
6765
6766 /* TR. */
6767 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6768 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6769 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6770 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6771 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6772 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6773 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6774
6775 /* GDTR. */
6776 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6777 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6778
6779 /* IDTR. */
6780 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6781 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6782}
6783
6784
6785/**
6786 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6787 *
6788 * @returns VBox status code.
6789 * @param pVCpu The cross context virtual CPU structure.
6790 * @param pszInstr The VMX instruction name (for logging purposes).
6791 */
6792IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6793{
6794 /*
6795 * Load guest MSRs.
6796 * See Intel spec. 26.4 "Loading MSRs".
6797 */
6798 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6799 const char *const pszFailure = "VM-exit";
6800
6801 /*
6802 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6803 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6804 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6805 */
6806 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6807 if (!cMsrs)
6808 return VINF_SUCCESS;
6809
6810 /*
6811 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6812 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6813 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6814 */
6815 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6816 if (fIsMsrCountValid)
6817 { /* likely */ }
6818 else
6819 {
6820 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6822 }
6823
6824 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
6825 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
6826 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
6827 if (RT_SUCCESS(rc))
6828 {
6829 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
6830 Assert(pMsr);
6831 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6832 {
6833 if ( !pMsr->u32Reserved
6834 && pMsr->u32Msr != MSR_K8_FS_BASE
6835 && pMsr->u32Msr != MSR_K8_GS_BASE
6836 && pMsr->u32Msr != MSR_K6_EFER
6837 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6838 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6839 {
6840 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6841 if (rcStrict == VINF_SUCCESS)
6842 continue;
6843
6844 /*
6845 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6846 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6847 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
6848 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6849 * MSR in ring-0 if possible, or come up with a better, generic solution.
6850 */
6851 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6852 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6853 ? kVmxVDiag_Vmentry_MsrLoadRing3
6854 : kVmxVDiag_Vmentry_MsrLoad;
6855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6856 }
6857 else
6858 {
6859 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6861 }
6862 }
6863 }
6864 else
6865 {
6866 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
6867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6868 }
6869
6870 NOREF(pszInstr);
6871 NOREF(pszFailure);
6872 return VINF_SUCCESS;
6873}
6874
6875
6876/**
6877 * Loads the guest-state non-register state as part of VM-entry.
6878 *
6879 * @returns VBox status code.
6880 * @param pVCpu The cross context virtual CPU structure.
6881 *
6882 * @remarks This must be called only after loading the nested-guest register state
6883 * (especially nested-guest RIP).
6884 */
6885IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6886{
6887 /*
6888 * Load guest non-register state.
6889 * See Intel spec. 26.6 "Special Features of VM Entry"
6890 */
6891 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6892 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6893 if (!fEntryVectoring)
6894 {
6895 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6896 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
6897 else
6898 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6899
6900 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6901 }
6902 else
6903 {
6904 /* When the VM-entry is not vectoring, there is no blocking by STI or Mov-SS. */
6905 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6906 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6907 }
6908
6909 /* NMI blocking. */
6910 if ( (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6911 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6912 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6913
6914 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6915 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6916
6917 /* VPID is irrelevant. We don't support VPID yet. */
6918
6919 /* Clear address-range monitoring. */
6920 EMMonitorWaitClear(pVCpu);
6921}
6922
6923
6924/**
6925 * Loads the guest-state as part of VM-entry.
6926 *
6927 * @returns VBox status code.
6928 * @param pVCpu The cross context virtual CPU structure.
6929 * @param pszInstr The VMX instruction name (for logging purposes).
6930 *
6931 * @remarks This must be done after all the necessary steps prior to loading of
6932 * guest-state (e.g. checking various VMCS state).
6933 */
6934IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6935{
6936 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6937 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6938
6939 /*
6940 * Load guest RIP, RSP and RFLAGS.
6941 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6942 */
6943 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6944 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6945 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6946 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6947
6948 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6949 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6950 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6951
6952 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6953
6954 NOREF(pszInstr);
6955 return VINF_SUCCESS;
6956}
6957
6958
6959/**
6960 * Returns whether there are is a pending debug exception on VM-entry.
6961 *
6962 * @param pVCpu The cross context virtual CPU structure.
6963 * @param pszInstr The VMX instruction name (for logging purposes).
6964 */
6965IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6966{
6967 /*
6968 * Pending debug exceptions.
6969 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6970 */
6971 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6972 Assert(pVmcs);
6973
6974 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6975 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6976 if (fPendingDbgXcpt)
6977 {
6978 uint8_t uEntryIntInfoType;
6979 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6980 if (fEntryVectoring)
6981 {
6982 switch (uEntryIntInfoType)
6983 {
6984 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6985 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6986 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6987 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6988 fPendingDbgXcpt = false;
6989 break;
6990
6991 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6992 {
6993 /*
6994 * Whether the pending debug exception for software exceptions other than
6995 * #BP and #OF is delivered after injecting the exception or is discard
6996 * is CPU implementation specific. We will discard them (easier).
6997 */
6998 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6999 if ( uVector != X86_XCPT_BP
7000 && uVector != X86_XCPT_OF)
7001 fPendingDbgXcpt = false;
7002 RT_FALL_THRU();
7003 }
7004 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7005 {
7006 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7007 fPendingDbgXcpt = false;
7008 break;
7009 }
7010 }
7011 }
7012 else
7013 {
7014 /*
7015 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7016 * pending debug exception is held pending or is discarded is CPU implementation
7017 * specific. We will discard them (easier).
7018 */
7019 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7020 fPendingDbgXcpt = false;
7021
7022 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7023 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7024 fPendingDbgXcpt = false;
7025 }
7026 }
7027
7028 NOREF(pszInstr);
7029 return fPendingDbgXcpt;
7030}
7031
7032
7033/**
7034 * Set up the monitor-trap flag (MTF).
7035 *
7036 * @param pVCpu The cross context virtual CPU structure.
7037 * @param pszInstr The VMX instruction name (for logging purposes).
7038 */
7039IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7040{
7041 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7042 Assert(pVmcs);
7043 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7044 {
7045 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7046 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7047 }
7048 else
7049 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7050 NOREF(pszInstr);
7051}
7052
7053
7054/**
7055 * Set up the VMX-preemption timer.
7056 *
7057 * @param pVCpu The cross context virtual CPU structure.
7058 * @param pszInstr The VMX instruction name (for logging purposes).
7059 */
7060IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7061{
7062 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7063 Assert(pVmcs);
7064 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7065 {
7066 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7067 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7068 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7069
7070 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7071 }
7072 else
7073 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7074
7075 NOREF(pszInstr);
7076}
7077
7078
7079/**
7080 * Performs event injection (if any) as part of VM-entry.
7081 *
7082 * @param pVCpu The cross context virtual CPU structure.
7083 * @param pszInstr The VMX instruction name (for logging purposes).
7084 */
7085IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7086{
7087 /*
7088 * Inject events.
7089 * See Intel spec. 26.5 "Event Injection".
7090 */
7091 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7092 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7093 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
7094 {
7095 /*
7096 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7097 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7098 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7099 * the actually delivery of this event.
7100 */
7101 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = false;
7102
7103 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7104 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7105 {
7106 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7107 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7108 return VINF_SUCCESS;
7109 }
7110
7111 return HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7112 pVCpu->cpum.GstCtx.cr2);
7113 }
7114
7115 /*
7116 * Inject any pending guest debug exception.
7117 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7118 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7119 */
7120 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7121 if (fPendingDbgXcpt)
7122 {
7123 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
7124 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7125 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7126 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7127 return HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7128 0 /* GCPtrFaultAddress */);
7129 }
7130
7131 NOREF(pszInstr);
7132 return VINF_SUCCESS;
7133}
7134
7135
7136/**
7137 * VMLAUNCH/VMRESUME instruction execution worker.
7138 *
7139 * @returns Strict VBox status code.
7140 * @param pVCpu The cross context virtual CPU structure.
7141 * @param cbInstr The instruction length in bytes.
7142 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7143 * VMXINSTRID_VMRESUME).
7144 *
7145 * @remarks Common VMX instruction checks are already expected to by the caller,
7146 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7147 */
7148IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7149{
7150# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7151 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7152 return VINF_EM_RAW_EMULATE_INSTR;
7153# else
7154 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7155 || uInstrId == VMXINSTRID_VMRESUME);
7156 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7157
7158 /* Nested-guest intercept. */
7159 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7160 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7161
7162 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7163
7164 /* CPL. */
7165 if (pVCpu->iem.s.uCpl > 0)
7166 {
7167 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7168 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7169 return iemRaiseGeneralProtectionFault0(pVCpu);
7170 }
7171
7172 /* Current VMCS valid. */
7173 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7174 {
7175 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7176 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7177 iemVmxVmFailInvalid(pVCpu);
7178 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7179 return VINF_SUCCESS;
7180 }
7181
7182 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
7183 * use block-by-STI here which is not quite correct. */
7184 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7185 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
7186 {
7187 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7188 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7189 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7190 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7191 return VINF_SUCCESS;
7192 }
7193
7194 if (uInstrId == VMXINSTRID_VMLAUNCH)
7195 {
7196 /* VMLAUNCH with non-clear VMCS. */
7197 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
7198 { /* likely */ }
7199 else
7200 {
7201 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7202 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7203 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7204 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7205 return VINF_SUCCESS;
7206 }
7207 }
7208 else
7209 {
7210 /* VMRESUME with non-launched VMCS. */
7211 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
7212 { /* likely */ }
7213 else
7214 {
7215 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7216 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7217 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7218 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7219 return VINF_SUCCESS;
7220 }
7221 }
7222
7223 /*
7224 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7225 * while entering VMX non-root mode. We do some of this while checking VM-execution
7226 * controls. The guest hypervisor should not make assumptions and cannot expect
7227 * predictable behavior if changes to these structures are made in guest memory while
7228 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7229 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7230 *
7231 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7232 */
7233 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7234 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7235 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7236 if (RT_SUCCESS(rc))
7237 {
7238 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7239 if (RT_SUCCESS(rc))
7240 {
7241 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7242 if (RT_SUCCESS(rc))
7243 {
7244 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7245 if (RT_SUCCESS(rc))
7246 {
7247 /* Initialize the VM-exit qualification field as it MBZ for VM-exits where it isn't specified. */
7248 iemVmxVmcsSetExitQual(pVCpu, 0);
7249
7250 /*
7251 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7252 * So we save the required force flags here (currently only VMCPU_FF_BLOCK_NMI) so we
7253 * can restore it on VM-exit when required.
7254 */
7255 iemVmxVmentrySaveForceFlags(pVCpu);
7256
7257 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7258 if (RT_SUCCESS(rc))
7259 {
7260 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7261 if (RT_SUCCESS(rc))
7262 {
7263 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7264 if (RT_SUCCESS(rc))
7265 {
7266 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7267
7268 /* VMLAUNCH instruction must update the VMCS launch state. */
7269 if (uInstrId == VMXINSTRID_VMLAUNCH)
7270 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
7271
7272 /* Perform the VMX transition (PGM updates). */
7273 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7274 if (rcStrict == VINF_SUCCESS)
7275 { /* likely */ }
7276 else if (RT_SUCCESS(rcStrict))
7277 {
7278 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7279 VBOXSTRICTRC_VAL(rcStrict)));
7280 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7281 }
7282 else
7283 {
7284 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7285 return rcStrict;
7286 }
7287
7288 /* We've now entered nested-guest execution. */
7289 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7290
7291 /*
7292 * The priority of potential VM-exits during VM-entry is important.
7293 * The priorities of VM-exits and events are listed from highest
7294 * to lowest as follows:
7295 *
7296 * 1. Event injection.
7297 * 2. Trap on task-switch (T flag set in TSS).
7298 * 3. TPR below threshold / APIC-write.
7299 * 4. SMI, INIT.
7300 * 5. MTF exit.
7301 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7302 * 7. VMX-preemption timer.
7303 * 9. NMI-window exit.
7304 * 10. NMI injection.
7305 * 11. Interrupt-window exit.
7306 * 12. Virtual-interrupt injection.
7307 * 13. Interrupt injection.
7308 * 14. Process next instruction (fetch, decode, execute).
7309 */
7310
7311 /* Setup the VMX-preemption timer. */
7312 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7313
7314 /* Setup monitor-trap flag. */
7315 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7316
7317 /* Now that we've switched page tables, we can inject events if any. */
7318 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7319
7320 /*
7321 * We've successfully entered nested-guest execution at this point.
7322 * Return after setting nested-guest EM execution policy as necessary.
7323 */
7324 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr);
7325 }
7326 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7327 }
7328 }
7329 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7330 }
7331
7332 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7333 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7334 return VINF_SUCCESS;
7335 }
7336 }
7337 }
7338
7339 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7340 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7341 return VINF_SUCCESS;
7342# endif
7343}
7344
7345
7346/**
7347 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7348 * (causes a VM-exit) or not.
7349 *
7350 * @returns @c true if the instruction is intercepted, @c false otherwise.
7351 * @param pVCpu The cross context virtual CPU structure.
7352 * @param uExitReason The VM-exit exit reason (VMX_EXIT_RDMSR or
7353 * VMX_EXIT_WRMSR).
7354 * @param idMsr The MSR.
7355 */
7356IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7357{
7358 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7359 Assert( uExitReason == VMX_EXIT_RDMSR
7360 || uExitReason == VMX_EXIT_WRMSR);
7361
7362 /* Consult the MSR bitmap if the feature is supported. */
7363 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7364 Assert(pVmcs);
7365 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7366 {
7367 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7368 if (uExitReason == VMX_EXIT_RDMSR)
7369 {
7370 VMXMSREXITREAD enmRead;
7371 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7372 NULL /* penmWrite */);
7373 AssertRC(rc);
7374 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7375 return true;
7376 }
7377 else
7378 {
7379 VMXMSREXITWRITE enmWrite;
7380 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7381 &enmWrite);
7382 AssertRC(rc);
7383 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7384 return true;
7385 }
7386 return false;
7387 }
7388
7389 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7390 return true;
7391}
7392
7393
7394/**
7395 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7396 * intercepted (causes a VM-exit) or not.
7397 *
7398 * @returns @c true if the instruction is intercepted, @c false otherwise.
7399 * @param pVCpu The cross context virtual CPU structure.
7400 * @param u64FieldEnc The VMCS field encoding.
7401 * @param uExitReason The VM-exit exit reason (VMX_EXIT_VMREAD or
7402 * VMX_EXIT_VMREAD).
7403 */
7404IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7405{
7406 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7407 Assert( uExitReason == VMX_EXIT_VMREAD
7408 || uExitReason == VMX_EXIT_VMWRITE);
7409
7410 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7411 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7412 return true;
7413
7414 /*
7415 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7416 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7417 */
7418 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7419 return true;
7420
7421 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7422 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
7423 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7424 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7425 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7426 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7427 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7428 pbBitmap += (u32FieldEnc >> 3);
7429 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7430 return true;
7431
7432 return false;
7433}
7434
7435
7436/**
7437 * VMREAD common (memory/register) instruction execution worker
7438 *
7439 * @returns Strict VBox status code.
7440 * @param pVCpu The cross context virtual CPU structure.
7441 * @param cbInstr The instruction length in bytes.
7442 * @param pu64Dst Where to write the VMCS value (only updated when
7443 * VINF_SUCCESS is returned).
7444 * @param u64FieldEnc The VMCS field encoding.
7445 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7446 * be NULL.
7447 */
7448IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7449 PCVMXVEXITINFO pExitInfo)
7450{
7451 /* Nested-guest intercept. */
7452 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7453 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7454 {
7455 if (pExitInfo)
7456 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7457 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7458 }
7459
7460 /* CPL. */
7461 if (pVCpu->iem.s.uCpl > 0)
7462 {
7463 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7464 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7465 return iemRaiseGeneralProtectionFault0(pVCpu);
7466 }
7467
7468 /* VMCS pointer in root mode. */
7469 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7470 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7471 {
7472 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7473 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7474 iemVmxVmFailInvalid(pVCpu);
7475 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7476 return VINF_SUCCESS;
7477 }
7478
7479 /* VMCS-link pointer in non-root mode. */
7480 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7481 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7482 {
7483 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7484 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7485 iemVmxVmFailInvalid(pVCpu);
7486 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7487 return VINF_SUCCESS;
7488 }
7489
7490 /* Supported VMCS field. */
7491 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7492 {
7493 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7494 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7495 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7496 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7497 return VINF_SUCCESS;
7498 }
7499
7500 /*
7501 * Setup reading from the current or shadow VMCS.
7502 */
7503 uint8_t *pbVmcs;
7504 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7505 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7506 else
7507 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7508 Assert(pbVmcs);
7509
7510 VMXVMCSFIELDENC FieldEnc;
7511 FieldEnc.u = u64FieldEnc;
7512 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7513 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7514 uint8_t const uWidthType = (uWidth << 2) | uType;
7515 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7516 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7517 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7518 Assert(offField < VMX_V_VMCS_SIZE);
7519
7520 /*
7521 * Read the VMCS component based on the field's effective width.
7522 *
7523 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7524 * indicates high bits (little endian).
7525 *
7526 * Note! The caller is responsible to trim the result and update registers
7527 * or memory locations are required. Here we just zero-extend to the largest
7528 * type (i.e. 64-bits).
7529 */
7530 uint8_t *pbField = pbVmcs + offField;
7531 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7532 switch (uEffWidth)
7533 {
7534 case VMX_VMCS_ENC_WIDTH_64BIT:
7535 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7536 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7537 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7538 }
7539 return VINF_SUCCESS;
7540}
7541
7542
7543/**
7544 * VMREAD (64-bit register) instruction execution worker.
7545 *
7546 * @returns Strict VBox status code.
7547 * @param pVCpu The cross context virtual CPU structure.
7548 * @param cbInstr The instruction length in bytes.
7549 * @param pu64Dst Where to store the VMCS field's value.
7550 * @param u64FieldEnc The VMCS field encoding.
7551 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7552 * be NULL.
7553 */
7554IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7555 PCVMXVEXITINFO pExitInfo)
7556{
7557 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7558 if (rcStrict == VINF_SUCCESS)
7559 {
7560 iemVmxVmreadSuccess(pVCpu, cbInstr);
7561 return VINF_SUCCESS;
7562 }
7563
7564 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7565 return rcStrict;
7566}
7567
7568
7569/**
7570 * VMREAD (32-bit register) instruction execution worker.
7571 *
7572 * @returns Strict VBox status code.
7573 * @param pVCpu The cross context virtual CPU structure.
7574 * @param cbInstr The instruction length in bytes.
7575 * @param pu32Dst Where to store the VMCS field's value.
7576 * @param u32FieldEnc The VMCS field encoding.
7577 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7578 * be NULL.
7579 */
7580IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7581 PCVMXVEXITINFO pExitInfo)
7582{
7583 uint64_t u64Dst;
7584 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7585 if (rcStrict == VINF_SUCCESS)
7586 {
7587 *pu32Dst = u64Dst;
7588 iemVmxVmreadSuccess(pVCpu, cbInstr);
7589 return VINF_SUCCESS;
7590 }
7591
7592 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7593 return rcStrict;
7594}
7595
7596
7597/**
7598 * VMREAD (memory) instruction execution worker.
7599 *
7600 * @returns Strict VBox status code.
7601 * @param pVCpu The cross context virtual CPU structure.
7602 * @param cbInstr The instruction length in bytes.
7603 * @param iEffSeg The effective segment register to use with @a u64Val.
7604 * Pass UINT8_MAX if it is a register access.
7605 * @param enmEffAddrMode The effective addressing mode (only used with memory
7606 * operand).
7607 * @param GCPtrDst The guest linear address to store the VMCS field's
7608 * value.
7609 * @param u64FieldEnc The VMCS field encoding.
7610 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7611 * be NULL.
7612 */
7613IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7614 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7615{
7616 uint64_t u64Dst;
7617 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7618 if (rcStrict == VINF_SUCCESS)
7619 {
7620 /*
7621 * Write the VMCS field's value to the location specified in guest-memory.
7622 *
7623 * The pointer size depends on the address size (address-size prefix allowed).
7624 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7625 */
7626 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7627 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7628 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7629
7630 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7631 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7632 else
7633 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7634 if (rcStrict == VINF_SUCCESS)
7635 {
7636 iemVmxVmreadSuccess(pVCpu, cbInstr);
7637 return VINF_SUCCESS;
7638 }
7639
7640 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7641 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7642 return rcStrict;
7643 }
7644
7645 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7646 return rcStrict;
7647}
7648
7649
7650/**
7651 * VMWRITE instruction execution worker.
7652 *
7653 * @returns Strict VBox status code.
7654 * @param pVCpu The cross context virtual CPU structure.
7655 * @param cbInstr The instruction length in bytes.
7656 * @param iEffSeg The effective segment register to use with @a u64Val.
7657 * Pass UINT8_MAX if it is a register access.
7658 * @param enmEffAddrMode The effective addressing mode (only used with memory
7659 * operand).
7660 * @param u64Val The value to write (or guest linear address to the
7661 * value), @a iEffSeg will indicate if it's a memory
7662 * operand.
7663 * @param u64FieldEnc The VMCS field encoding.
7664 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7665 * be NULL.
7666 */
7667IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7668 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7669{
7670 /* Nested-guest intercept. */
7671 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7672 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7673 {
7674 if (pExitInfo)
7675 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7676 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7677 }
7678
7679 /* CPL. */
7680 if (pVCpu->iem.s.uCpl > 0)
7681 {
7682 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7684 return iemRaiseGeneralProtectionFault0(pVCpu);
7685 }
7686
7687 /* VMCS pointer in root mode. */
7688 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7689 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7690 {
7691 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7693 iemVmxVmFailInvalid(pVCpu);
7694 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7695 return VINF_SUCCESS;
7696 }
7697
7698 /* VMCS-link pointer in non-root mode. */
7699 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7700 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7701 {
7702 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7703 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7704 iemVmxVmFailInvalid(pVCpu);
7705 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7706 return VINF_SUCCESS;
7707 }
7708
7709 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7710 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7711 if (!fIsRegOperand)
7712 {
7713 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7714 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7715 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
7716
7717 /* Read the value from the specified guest memory location. */
7718 VBOXSTRICTRC rcStrict;
7719 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7720 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7721 else
7722 {
7723 uint32_t u32Val;
7724 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7725 u64Val = u32Val;
7726 }
7727 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7728 {
7729 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7730 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7731 return rcStrict;
7732 }
7733 }
7734 else
7735 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7736
7737 /* Supported VMCS field. */
7738 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7739 {
7740 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7741 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7742 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7743 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7744 return VINF_SUCCESS;
7745 }
7746
7747 /* Read-only VMCS field. */
7748 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
7749 if ( fIsFieldReadOnly
7750 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7751 {
7752 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
7753 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7754 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7755 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7756 return VINF_SUCCESS;
7757 }
7758
7759 /*
7760 * Setup writing to the current or shadow VMCS.
7761 */
7762 uint8_t *pbVmcs;
7763 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7764 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7765 else
7766 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7767 Assert(pbVmcs);
7768
7769 VMXVMCSFIELDENC FieldEnc;
7770 FieldEnc.u = u64FieldEnc;
7771 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7772 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7773 uint8_t const uWidthType = (uWidth << 2) | uType;
7774 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7775 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7777 Assert(offField < VMX_V_VMCS_SIZE);
7778
7779 /*
7780 * Write the VMCS component based on the field's effective width.
7781 *
7782 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7783 * indicates high bits (little endian).
7784 */
7785 uint8_t *pbField = pbVmcs + offField;
7786 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7787 switch (uEffWidth)
7788 {
7789 case VMX_VMCS_ENC_WIDTH_64BIT:
7790 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7791 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7792 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7793 }
7794
7795 iemVmxVmSucceed(pVCpu);
7796 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7797 return VINF_SUCCESS;
7798}
7799
7800
7801/**
7802 * VMCLEAR instruction execution worker.
7803 *
7804 * @returns Strict VBox status code.
7805 * @param pVCpu The cross context virtual CPU structure.
7806 * @param cbInstr The instruction length in bytes.
7807 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7808 * @param GCPtrVmcs The linear address of the VMCS pointer.
7809 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7810 * be NULL.
7811 *
7812 * @remarks Common VMX instruction checks are already expected to by the caller,
7813 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7814 */
7815IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7816 PCVMXVEXITINFO pExitInfo)
7817{
7818 /* Nested-guest intercept. */
7819 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7820 {
7821 if (pExitInfo)
7822 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7823 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7824 }
7825
7826 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7827
7828 /* CPL. */
7829 if (pVCpu->iem.s.uCpl > 0)
7830 {
7831 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7832 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7833 return iemRaiseGeneralProtectionFault0(pVCpu);
7834 }
7835
7836 /* Get the VMCS pointer from the location specified by the source memory operand. */
7837 RTGCPHYS GCPhysVmcs;
7838 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7839 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7840 {
7841 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7843 return rcStrict;
7844 }
7845
7846 /* VMCS pointer alignment. */
7847 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
7848 {
7849 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7850 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7851 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7852 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7853 return VINF_SUCCESS;
7854 }
7855
7856 /* VMCS physical-address width limits. */
7857 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7858 {
7859 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7860 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7861 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7862 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7863 return VINF_SUCCESS;
7864 }
7865
7866 /* VMCS is not the VMXON region. */
7867 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7868 {
7869 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7870 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7871 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7872 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7873 return VINF_SUCCESS;
7874 }
7875
7876 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7877 restriction imposed by our implementation. */
7878 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7879 {
7880 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7881 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7882 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7883 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7884 return VINF_SUCCESS;
7885 }
7886
7887 /*
7888 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7889 *
7890 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7891 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7892 * to 'clear'.
7893 */
7894 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
7895 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7896 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7897 {
7898 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
7899 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7900 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
7901 iemVmxCommitCurrentVmcsToMemory(pVCpu);
7902 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7903 }
7904 else
7905 {
7906 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsStateClear));
7907 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7908 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
7909 if (RT_FAILURE(rcStrict))
7910 return rcStrict;
7911 }
7912
7913 iemVmxVmSucceed(pVCpu);
7914 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7915 return VINF_SUCCESS;
7916}
7917
7918
7919/**
7920 * VMPTRST instruction execution worker.
7921 *
7922 * @returns Strict VBox status code.
7923 * @param pVCpu The cross context virtual CPU structure.
7924 * @param cbInstr The instruction length in bytes.
7925 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7926 * @param GCPtrVmcs The linear address of where to store the current VMCS
7927 * pointer.
7928 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7929 * be NULL.
7930 *
7931 * @remarks Common VMX instruction checks are already expected to by the caller,
7932 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7933 */
7934IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7935 PCVMXVEXITINFO pExitInfo)
7936{
7937 /* Nested-guest intercept. */
7938 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7939 {
7940 if (pExitInfo)
7941 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7942 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
7943 }
7944
7945 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7946
7947 /* CPL. */
7948 if (pVCpu->iem.s.uCpl > 0)
7949 {
7950 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
7952 return iemRaiseGeneralProtectionFault0(pVCpu);
7953 }
7954
7955 /* Set the VMCS pointer to the location specified by the destination memory operand. */
7956 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
7957 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
7958 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7959 {
7960 iemVmxVmSucceed(pVCpu);
7961 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7962 return rcStrict;
7963 }
7964
7965 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7966 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
7967 return rcStrict;
7968}
7969
7970
7971/**
7972 * VMPTRLD instruction execution worker.
7973 *
7974 * @returns Strict VBox status code.
7975 * @param pVCpu The cross context virtual CPU structure.
7976 * @param cbInstr The instruction length in bytes.
7977 * @param GCPtrVmcs The linear address of the current VMCS pointer.
7978 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7979 * be NULL.
7980 *
7981 * @remarks Common VMX instruction checks are already expected to by the caller,
7982 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7983 */
7984IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7985 PCVMXVEXITINFO pExitInfo)
7986{
7987 /* Nested-guest intercept. */
7988 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7989 {
7990 if (pExitInfo)
7991 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7992 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
7993 }
7994
7995 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7996
7997 /* CPL. */
7998 if (pVCpu->iem.s.uCpl > 0)
7999 {
8000 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8001 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8002 return iemRaiseGeneralProtectionFault0(pVCpu);
8003 }
8004
8005 /* Get the VMCS pointer from the location specified by the source memory operand. */
8006 RTGCPHYS GCPhysVmcs;
8007 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8008 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8009 {
8010 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8011 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8012 return rcStrict;
8013 }
8014
8015 /* VMCS pointer alignment. */
8016 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
8017 {
8018 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8019 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8020 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8021 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8022 return VINF_SUCCESS;
8023 }
8024
8025 /* VMCS physical-address width limits. */
8026 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
8027 {
8028 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8029 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8030 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8031 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8032 return VINF_SUCCESS;
8033 }
8034
8035 /* VMCS is not the VMXON region. */
8036 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8037 {
8038 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8039 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8040 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8041 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8042 return VINF_SUCCESS;
8043 }
8044
8045 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8046 restriction imposed by our implementation. */
8047 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8048 {
8049 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8050 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8051 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8052 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8053 return VINF_SUCCESS;
8054 }
8055
8056 /* Read just the VMCS revision from the VMCS. */
8057 VMXVMCSREVID VmcsRevId;
8058 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8059 if (RT_FAILURE(rc))
8060 {
8061 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8062 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8063 return rc;
8064 }
8065
8066 /*
8067 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8068 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8069 */
8070 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
8071 || ( VmcsRevId.n.fIsShadowVmcs
8072 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8073 {
8074 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8075 {
8076 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8077 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8078 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8079 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8080 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8081 return VINF_SUCCESS;
8082 }
8083
8084 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8085 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8086 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8088 return VINF_SUCCESS;
8089 }
8090
8091 /*
8092 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8093 * the cache of an existing, current VMCS back to guest memory before loading a new,
8094 * different current VMCS.
8095 */
8096 bool fLoadVmcsFromMem;
8097 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8098 {
8099 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8100 {
8101 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8102 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8103 fLoadVmcsFromMem = true;
8104 }
8105 else
8106 fLoadVmcsFromMem = false;
8107 }
8108 else
8109 fLoadVmcsFromMem = true;
8110
8111 if (fLoadVmcsFromMem)
8112 {
8113 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8114 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8115 sizeof(VMXVVMCS));
8116 if (RT_FAILURE(rc))
8117 {
8118 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8119 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8120 return rc;
8121 }
8122 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8123 }
8124
8125 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8126 iemVmxVmSucceed(pVCpu);
8127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8128 return VINF_SUCCESS;
8129}
8130
8131
8132/**
8133 * VMXON instruction execution worker.
8134 *
8135 * @returns Strict VBox status code.
8136 * @param pVCpu The cross context virtual CPU structure.
8137 * @param cbInstr The instruction length in bytes.
8138 * @param iEffSeg The effective segment register to use with @a
8139 * GCPtrVmxon.
8140 * @param GCPtrVmxon The linear address of the VMXON pointer.
8141 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8142 * Optional, can be NULL.
8143 *
8144 * @remarks Common VMX instruction checks are already expected to by the caller,
8145 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8146 */
8147IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8148 PCVMXVEXITINFO pExitInfo)
8149{
8150 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8151 {
8152 /* CPL. */
8153 if (pVCpu->iem.s.uCpl > 0)
8154 {
8155 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8157 return iemRaiseGeneralProtectionFault0(pVCpu);
8158 }
8159
8160 /* A20M (A20 Masked) mode. */
8161 if (!PGMPhysIsA20Enabled(pVCpu))
8162 {
8163 Log(("vmxon: A20M mode -> #GP(0)\n"));
8164 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8165 return iemRaiseGeneralProtectionFault0(pVCpu);
8166 }
8167
8168 /* CR0. */
8169 {
8170 /* CR0 MB1 bits. */
8171 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8172 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
8173 {
8174 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8175 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8176 return iemRaiseGeneralProtectionFault0(pVCpu);
8177 }
8178
8179 /* CR0 MBZ bits. */
8180 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8181 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
8182 {
8183 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8185 return iemRaiseGeneralProtectionFault0(pVCpu);
8186 }
8187 }
8188
8189 /* CR4. */
8190 {
8191 /* CR4 MB1 bits. */
8192 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8193 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
8194 {
8195 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8196 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8197 return iemRaiseGeneralProtectionFault0(pVCpu);
8198 }
8199
8200 /* CR4 MBZ bits. */
8201 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8202 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
8203 {
8204 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8205 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8206 return iemRaiseGeneralProtectionFault0(pVCpu);
8207 }
8208 }
8209
8210 /* Feature control MSR's LOCK and VMXON bits. */
8211 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8212 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8213 != (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8214 {
8215 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8216 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8217 return iemRaiseGeneralProtectionFault0(pVCpu);
8218 }
8219
8220 /* Get the VMXON pointer from the location specified by the source memory operand. */
8221 RTGCPHYS GCPhysVmxon;
8222 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8223 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8224 {
8225 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8226 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8227 return rcStrict;
8228 }
8229
8230 /* VMXON region pointer alignment. */
8231 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
8232 {
8233 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8234 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8235 iemVmxVmFailInvalid(pVCpu);
8236 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8237 return VINF_SUCCESS;
8238 }
8239
8240 /* VMXON physical-address width limits. */
8241 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
8242 {
8243 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8244 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8245 iemVmxVmFailInvalid(pVCpu);
8246 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8247 return VINF_SUCCESS;
8248 }
8249
8250 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8251 restriction imposed by our implementation. */
8252 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8253 {
8254 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8256 iemVmxVmFailInvalid(pVCpu);
8257 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8258 return VINF_SUCCESS;
8259 }
8260
8261 /* Read the VMCS revision ID from the VMXON region. */
8262 VMXVMCSREVID VmcsRevId;
8263 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8264 if (RT_FAILURE(rc))
8265 {
8266 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8267 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8268 return rc;
8269 }
8270
8271 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8272 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
8273 {
8274 /* Revision ID mismatch. */
8275 if (!VmcsRevId.n.fIsShadowVmcs)
8276 {
8277 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8278 VmcsRevId.n.u31RevisionId));
8279 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8280 iemVmxVmFailInvalid(pVCpu);
8281 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8282 return VINF_SUCCESS;
8283 }
8284
8285 /* Shadow VMCS disallowed. */
8286 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8287 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8288 iemVmxVmFailInvalid(pVCpu);
8289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8290 return VINF_SUCCESS;
8291 }
8292
8293 /*
8294 * Record that we're in VMX operation, block INIT, block and disable A20M.
8295 */
8296 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8297 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8298 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8299
8300 /* Clear address-range monitoring. */
8301 EMMonitorWaitClear(pVCpu);
8302 /** @todo NSTVMX: Intel PT. */
8303
8304 iemVmxVmSucceed(pVCpu);
8305 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8306 return VINF_SUCCESS;
8307 }
8308 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8309 {
8310 /* Nested-guest intercept. */
8311 if (pExitInfo)
8312 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8313 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8314 }
8315
8316 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8317
8318 /* CPL. */
8319 if (pVCpu->iem.s.uCpl > 0)
8320 {
8321 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8322 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8323 return iemRaiseGeneralProtectionFault0(pVCpu);
8324 }
8325
8326 /* VMXON when already in VMX root mode. */
8327 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8329 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8330 return VINF_SUCCESS;
8331}
8332
8333
8334/**
8335 * Implements 'VMXOFF'.
8336 *
8337 * @remarks Common VMX instruction checks are already expected to by the caller,
8338 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8339 */
8340IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8341{
8342 /* Nested-guest intercept. */
8343 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8344 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8345
8346 /* CPL. */
8347 if (pVCpu->iem.s.uCpl > 0)
8348 {
8349 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8350 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8351 return iemRaiseGeneralProtectionFault0(pVCpu);
8352 }
8353
8354 /* Dual monitor treatment of SMIs and SMM. */
8355 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8356 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
8357 {
8358 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8359 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8360 return VINF_SUCCESS;
8361 }
8362
8363 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8364 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8365 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8366
8367 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8368 { /** @todo NSTVMX: Unblock SMI. */ }
8369
8370 EMMonitorWaitClear(pVCpu);
8371 /** @todo NSTVMX: Unblock and enable A20M. */
8372
8373 iemVmxVmSucceed(pVCpu);
8374 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8375 return VINF_SUCCESS;
8376}
8377
8378
8379/**
8380 * Implements 'VMXON'.
8381 */
8382IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8383{
8384 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8385}
8386
8387
8388/**
8389 * Implements 'VMLAUNCH'.
8390 */
8391IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8392{
8393 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8394}
8395
8396
8397/**
8398 * Implements 'VMRESUME'.
8399 */
8400IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8401{
8402 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8403}
8404
8405
8406/**
8407 * Implements 'VMPTRLD'.
8408 */
8409IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8410{
8411 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8412}
8413
8414
8415/**
8416 * Implements 'VMPTRST'.
8417 */
8418IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8419{
8420 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8421}
8422
8423
8424/**
8425 * Implements 'VMCLEAR'.
8426 */
8427IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8428{
8429 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8430}
8431
8432
8433/**
8434 * Implements 'VMWRITE' register.
8435 */
8436IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8437{
8438 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8439 NULL /* pExitInfo */);
8440}
8441
8442
8443/**
8444 * Implements 'VMWRITE' memory.
8445 */
8446IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8447{
8448 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8449}
8450
8451
8452/**
8453 * Implements 'VMREAD' register (64-bit).
8454 */
8455IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8456{
8457 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8458}
8459
8460
8461/**
8462 * Implements 'VMREAD' register (32-bit).
8463 */
8464IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8465{
8466 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8467}
8468
8469
8470/**
8471 * Implements 'VMREAD' memory, 64-bit register.
8472 */
8473IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8474{
8475 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8476}
8477
8478
8479/**
8480 * Implements 'VMREAD' memory, 32-bit register.
8481 */
8482IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8483{
8484 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8485}
8486
8487
8488/**
8489 * Implements VMX's implementation of PAUSE.
8490 */
8491IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8492{
8493 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8494 {
8495 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8496 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8497 return rcStrict;
8498 }
8499
8500 /*
8501 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8502 * a VM-exit, the instruction operates normally.
8503 */
8504 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8505 return VINF_SUCCESS;
8506}
8507
8508#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8509
8510
8511/**
8512 * Implements 'VMCALL'.
8513 */
8514IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8515{
8516#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8517 /* Nested-guest intercept. */
8518 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8519 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8520#endif
8521
8522 /* Join forces with vmmcall. */
8523 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8524}
8525
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette