VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79178

Last change on this file since 79178 was 79143, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Fix loading host CR0/CR4 on VM-exit (both MB0, MB1 bits must be ignored).
Import the entire guest-CPU state on VM-exit, more explanation in the comments.
Comments.
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File size: 359.9 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79143 2019-06-14 04:56:11Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64VmcsField The VMCS field.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64VmcsField)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the Exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param u64ExitQual The Exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = u64ExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitIntInfo The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1984 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1986 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1987 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1988 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1989 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1990 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1991 }
1992
1993 /* CR4. */
1994 {
1995 /* Fixed CR4 bits are not modified. */
1996 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1997 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1998 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1999 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2000 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2001 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2002 if (fHostInLongMode)
2003 uValidHostCr4 |= X86_CR4_PAE;
2004 else
2005 uValidHostCr4 &= ~X86_CR4_PCIDE;
2006 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
2007 }
2008
2009 /* CR3 (host value validated while checking host-state during VM-entry). */
2010 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2011
2012 /* DR7. */
2013 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2014
2015 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2016
2017 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2018 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2019 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2020 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2021
2022 /* FS, GS bases are loaded later while we load host segment registers. */
2023
2024 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2025 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2026 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2027 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2028 {
2029 if (fHostInLongMode)
2030 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2031 else
2032 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2033 }
2034
2035 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2036
2037 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2038 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2039 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2040
2041 /* We don't support IA32_BNDCFGS MSR yet. */
2042}
2043
2044
2045/**
2046 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2047 *
2048 * @param pVCpu The cross context virtual CPU structure.
2049 */
2050IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2051{
2052 /*
2053 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2054 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2055 *
2056 * Warning! Be careful to not touch fields that are reserved by VT-x,
2057 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2058 */
2059 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2060 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2061
2062 /* CS, SS, ES, DS, FS, GS. */
2063 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2064 {
2065 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2066 bool const fUnusable = RT_BOOL(HostSel == 0);
2067 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2068
2069 /* Selector. */
2070 pSelReg->Sel = HostSel;
2071 pSelReg->ValidSel = HostSel;
2072 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2073
2074 /* Limit. */
2075 pSelReg->u32Limit = 0xffffffff;
2076
2077 /* Base. */
2078 pSelReg->u64Base = 0;
2079
2080 /* Attributes. */
2081 if (iSegReg == X86_SREG_CS)
2082 {
2083 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2084 pSelReg->Attr.n.u1DescType = 1;
2085 pSelReg->Attr.n.u2Dpl = 0;
2086 pSelReg->Attr.n.u1Present = 1;
2087 pSelReg->Attr.n.u1Long = fHostInLongMode;
2088 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2089 pSelReg->Attr.n.u1Granularity = 1;
2090 Assert(!pSelReg->Attr.n.u1Unusable);
2091 Assert(!fUnusable);
2092 }
2093 else
2094 {
2095 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2096 pSelReg->Attr.n.u1DescType = 1;
2097 pSelReg->Attr.n.u2Dpl = 0;
2098 pSelReg->Attr.n.u1Present = 1;
2099 pSelReg->Attr.n.u1DefBig = 1;
2100 pSelReg->Attr.n.u1Granularity = 1;
2101 pSelReg->Attr.n.u1Unusable = fUnusable;
2102 }
2103 }
2104
2105 /* FS base. */
2106 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2107 || fHostInLongMode)
2108 {
2109 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2110 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2111 }
2112
2113 /* GS base. */
2114 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2115 || fHostInLongMode)
2116 {
2117 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2118 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2119 }
2120
2121 /* TR. */
2122 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2123 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2124 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2125 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2126 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2127 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2128 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2132 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2133 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2134 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2135
2136 /* LDTR (Warning! do not touch the base and limits here). */
2137 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2138 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2139 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2140 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2141
2142 /* GDTR. */
2143 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2144 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2145 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2146
2147 /* IDTR.*/
2148 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2149 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2150 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2151}
2152
2153
2154/**
2155 * Checks host PDPTes as part of VM-exit.
2156 *
2157 * @param pVCpu The cross context virtual CPU structure.
2158 * @param uExitReason The VM-exit reason (for logging purposes).
2159 */
2160IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2161{
2162 /*
2163 * Check host PDPTEs.
2164 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2165 */
2166 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2167 const char *const pszFailure = "VMX-abort";
2168 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2169
2170 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2171 && !fHostInLongMode)
2172 {
2173 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2174 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2175 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2176 if (RT_SUCCESS(rc))
2177 {
2178 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2179 {
2180 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2181 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2182 { /* likely */ }
2183 else
2184 {
2185 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2186 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2187 }
2188 }
2189 }
2190 else
2191 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2192 }
2193
2194 NOREF(pszFailure);
2195 NOREF(uExitReason);
2196 return VINF_SUCCESS;
2197}
2198
2199
2200/**
2201 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2202 *
2203 * @returns VBox status code.
2204 * @param pVCpu The cross context virtual CPU structure.
2205 * @param pszInstr The VMX instruction name (for logging purposes).
2206 */
2207IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2208{
2209 /*
2210 * Load host MSRs.
2211 * See Intel spec. 27.6 "Loading MSRs".
2212 */
2213 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2214 const char *const pszFailure = "VMX-abort";
2215
2216 /*
2217 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2218 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2219 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2220 */
2221 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2222 if (!cMsrs)
2223 return VINF_SUCCESS;
2224
2225 /*
2226 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2227 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2228 * implementation causes a VMX-abort followed by a triple-fault.
2229 */
2230 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2231 if (fIsMsrCountValid)
2232 { /* likely */ }
2233 else
2234 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2235
2236 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2237 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2238 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2239 if (RT_SUCCESS(rc))
2240 {
2241 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2242 Assert(pMsr);
2243 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2244 {
2245 if ( !pMsr->u32Reserved
2246 && pMsr->u32Msr != MSR_K8_FS_BASE
2247 && pMsr->u32Msr != MSR_K8_GS_BASE
2248 && pMsr->u32Msr != MSR_K6_EFER
2249 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2250 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2251 {
2252 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2253 if (rcStrict == VINF_SUCCESS)
2254 continue;
2255
2256 /*
2257 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2258 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2259 * recording the MSR index in the auxiliary info. field and indicated further by our
2260 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2261 * if possible, or come up with a better, generic solution.
2262 */
2263 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2264 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2265 ? kVmxVDiag_Vmexit_MsrLoadRing3
2266 : kVmxVDiag_Vmexit_MsrLoad;
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2268 }
2269 else
2270 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2271 }
2272 }
2273 else
2274 {
2275 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2276 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2277 }
2278
2279 NOREF(uExitReason);
2280 NOREF(pszFailure);
2281 return VINF_SUCCESS;
2282}
2283
2284
2285/**
2286 * Loads the host state as part of VM-exit.
2287 *
2288 * @returns Strict VBox status code.
2289 * @param pVCpu The cross context virtual CPU structure.
2290 * @param uExitReason The VM-exit reason (for logging purposes).
2291 */
2292IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2293{
2294 /*
2295 * Load host state.
2296 * See Intel spec. 27.5 "Loading Host State".
2297 */
2298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2299 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2300
2301 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2302 if ( CPUMIsGuestInLongMode(pVCpu)
2303 && !fHostInLongMode)
2304 {
2305 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2306 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2307 }
2308
2309 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2310 iemVmxVmexitLoadHostSegRegs(pVCpu);
2311
2312 /*
2313 * Load host RIP, RSP and RFLAGS.
2314 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2315 */
2316 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2317 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2318 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2319
2320 /* Clear address range monitoring. */
2321 EMMonitorWaitClear(pVCpu);
2322
2323 /* Perform the VMX transition (PGM updates). */
2324 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2325 if (rcStrict == VINF_SUCCESS)
2326 {
2327 /* Check host PDPTEs (only when we've fully switched page tables_. */
2328 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2329 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2330 if (RT_FAILURE(rc))
2331 {
2332 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2333 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2334 }
2335 }
2336 else if (RT_SUCCESS(rcStrict))
2337 {
2338 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2339 uExitReason));
2340 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2341 }
2342 else
2343 {
2344 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2345 return VBOXSTRICTRC_VAL(rcStrict);
2346 }
2347
2348 Assert(rcStrict == VINF_SUCCESS);
2349
2350 /* Load MSRs from the VM-exit auto-load MSR area. */
2351 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2352 if (RT_FAILURE(rc))
2353 {
2354 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2355 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2356 }
2357 return VINF_SUCCESS;
2358}
2359
2360
2361/**
2362 * Gets VM-exit instruction information along with any displacement for an
2363 * instruction VM-exit.
2364 *
2365 * @returns The VM-exit instruction information.
2366 * @param pVCpu The cross context virtual CPU structure.
2367 * @param uExitReason The VM-exit reason.
2368 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2369 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2370 * NULL.
2371 */
2372IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2373{
2374 RTGCPTR GCPtrDisp;
2375 VMXEXITINSTRINFO ExitInstrInfo;
2376 ExitInstrInfo.u = 0;
2377
2378 /*
2379 * Get and parse the ModR/M byte from our decoded opcodes.
2380 */
2381 uint8_t bRm;
2382 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2383 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2384 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2385 {
2386 /*
2387 * ModR/M indicates register addressing.
2388 *
2389 * The primary/secondary register operands are reported in the iReg1 or iReg2
2390 * fields depending on whether it is a read/write form.
2391 */
2392 uint8_t idxReg1;
2393 uint8_t idxReg2;
2394 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2395 {
2396 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2397 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2398 }
2399 else
2400 {
2401 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2402 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2403 }
2404 ExitInstrInfo.All.u2Scaling = 0;
2405 ExitInstrInfo.All.iReg1 = idxReg1;
2406 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2407 ExitInstrInfo.All.fIsRegOperand = 1;
2408 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2409 ExitInstrInfo.All.iSegReg = 0;
2410 ExitInstrInfo.All.iIdxReg = 0;
2411 ExitInstrInfo.All.fIdxRegInvalid = 1;
2412 ExitInstrInfo.All.iBaseReg = 0;
2413 ExitInstrInfo.All.fBaseRegInvalid = 1;
2414 ExitInstrInfo.All.iReg2 = idxReg2;
2415
2416 /* Displacement not applicable for register addressing. */
2417 GCPtrDisp = 0;
2418 }
2419 else
2420 {
2421 /*
2422 * ModR/M indicates memory addressing.
2423 */
2424 uint8_t uScale = 0;
2425 bool fBaseRegValid = false;
2426 bool fIdxRegValid = false;
2427 uint8_t iBaseReg = 0;
2428 uint8_t iIdxReg = 0;
2429 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2430 {
2431 /*
2432 * Parse the ModR/M, displacement for 16-bit addressing mode.
2433 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2434 */
2435 uint16_t u16Disp = 0;
2436 uint8_t const offDisp = offModRm + sizeof(bRm);
2437 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2438 {
2439 /* Displacement without any registers. */
2440 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2441 }
2442 else
2443 {
2444 /* Register (index and base). */
2445 switch (bRm & X86_MODRM_RM_MASK)
2446 {
2447 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2448 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2449 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2450 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2451 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2452 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2453 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2454 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2455 }
2456
2457 /* Register + displacement. */
2458 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2459 {
2460 case 0: break;
2461 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2462 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2463 default:
2464 {
2465 /* Register addressing, handled at the beginning. */
2466 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2467 break;
2468 }
2469 }
2470 }
2471
2472 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2473 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2474 }
2475 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2476 {
2477 /*
2478 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2479 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2480 */
2481 uint32_t u32Disp = 0;
2482 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2483 {
2484 /* Displacement without any registers. */
2485 uint8_t const offDisp = offModRm + sizeof(bRm);
2486 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2487 }
2488 else
2489 {
2490 /* Register (and perhaps scale, index and base). */
2491 uint8_t offDisp = offModRm + sizeof(bRm);
2492 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2493 if (iBaseReg == 4)
2494 {
2495 /* An SIB byte follows the ModR/M byte, parse it. */
2496 uint8_t bSib;
2497 uint8_t const offSib = offModRm + sizeof(bRm);
2498 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2499
2500 /* A displacement may follow SIB, update its offset. */
2501 offDisp += sizeof(bSib);
2502
2503 /* Get the scale. */
2504 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2505
2506 /* Get the index register. */
2507 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2508 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2509
2510 /* Get the base register. */
2511 iBaseReg = bSib & X86_SIB_BASE_MASK;
2512 fBaseRegValid = true;
2513 if (iBaseReg == 5)
2514 {
2515 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2516 {
2517 /* Mod is 0 implies a 32-bit displacement with no base. */
2518 fBaseRegValid = false;
2519 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2520 }
2521 else
2522 {
2523 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2524 iBaseReg = X86_GREG_xBP;
2525 }
2526 }
2527 }
2528
2529 /* Register + displacement. */
2530 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2531 {
2532 case 0: /* Handled above */ break;
2533 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2534 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2535 default:
2536 {
2537 /* Register addressing, handled at the beginning. */
2538 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2539 break;
2540 }
2541 }
2542 }
2543
2544 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2545 }
2546 else
2547 {
2548 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2549
2550 /*
2551 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2552 * See Intel instruction spec. 2.2 "IA-32e Mode".
2553 */
2554 uint64_t u64Disp = 0;
2555 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2556 if (fRipRelativeAddr)
2557 {
2558 /*
2559 * RIP-relative addressing mode.
2560 *
2561 * The displacement is 32-bit signed implying an offset range of +/-2G.
2562 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2563 */
2564 uint8_t const offDisp = offModRm + sizeof(bRm);
2565 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2566 }
2567 else
2568 {
2569 uint8_t offDisp = offModRm + sizeof(bRm);
2570
2571 /*
2572 * Register (and perhaps scale, index and base).
2573 *
2574 * REX.B extends the most-significant bit of the base register. However, REX.B
2575 * is ignored while determining whether an SIB follows the opcode. Hence, we
2576 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2577 *
2578 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2579 */
2580 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2581 if (iBaseReg == 4)
2582 {
2583 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2584 uint8_t bSib;
2585 uint8_t const offSib = offModRm + sizeof(bRm);
2586 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2587
2588 /* Displacement may follow SIB, update its offset. */
2589 offDisp += sizeof(bSib);
2590
2591 /* Get the scale. */
2592 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2593
2594 /* Get the index. */
2595 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2596 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2597
2598 /* Get the base. */
2599 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2600 fBaseRegValid = true;
2601 if (iBaseReg == 5)
2602 {
2603 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2604 {
2605 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2606 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2607 }
2608 else
2609 {
2610 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2611 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2612 }
2613 }
2614 }
2615 iBaseReg |= pVCpu->iem.s.uRexB;
2616
2617 /* Register + displacement. */
2618 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2619 {
2620 case 0: /* Handled above */ break;
2621 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2622 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2623 default:
2624 {
2625 /* Register addressing, handled at the beginning. */
2626 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2627 break;
2628 }
2629 }
2630 }
2631
2632 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2633 }
2634
2635 /*
2636 * The primary or secondary register operand is reported in iReg2 depending
2637 * on whether the primary operand is in read/write form.
2638 */
2639 uint8_t idxReg2;
2640 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2641 {
2642 idxReg2 = bRm & X86_MODRM_RM_MASK;
2643 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2644 idxReg2 |= pVCpu->iem.s.uRexB;
2645 }
2646 else
2647 {
2648 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2649 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2650 idxReg2 |= pVCpu->iem.s.uRexReg;
2651 }
2652 ExitInstrInfo.All.u2Scaling = uScale;
2653 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2654 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2655 ExitInstrInfo.All.fIsRegOperand = 0;
2656 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2657 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2658 ExitInstrInfo.All.iIdxReg = iIdxReg;
2659 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2660 ExitInstrInfo.All.iBaseReg = iBaseReg;
2661 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2662 ExitInstrInfo.All.iReg2 = idxReg2;
2663 }
2664
2665 /*
2666 * Handle exceptions to the norm for certain instructions.
2667 * (e.g. some instructions convey an instruction identity in place of iReg2).
2668 */
2669 switch (uExitReason)
2670 {
2671 case VMX_EXIT_GDTR_IDTR_ACCESS:
2672 {
2673 Assert(VMXINSTRID_IS_VALID(uInstrId));
2674 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2675 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2676 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2677 break;
2678 }
2679
2680 case VMX_EXIT_LDTR_TR_ACCESS:
2681 {
2682 Assert(VMXINSTRID_IS_VALID(uInstrId));
2683 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2684 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2685 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2686 break;
2687 }
2688
2689 case VMX_EXIT_RDRAND:
2690 case VMX_EXIT_RDSEED:
2691 {
2692 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2693 break;
2694 }
2695 }
2696
2697 /* Update displacement and return the constructed VM-exit instruction information field. */
2698 if (pGCPtrDisp)
2699 *pGCPtrDisp = GCPtrDisp;
2700
2701 return ExitInstrInfo.u;
2702}
2703
2704
2705/**
2706 * VMX VM-exit handler.
2707 *
2708 * @returns Strict VBox status code.
2709 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2710 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2711 * triple-fault.
2712 *
2713 * @param pVCpu The cross context virtual CPU structure.
2714 * @param uExitReason The VM-exit reason.
2715 * @param u64ExitQual The Exit qualification.
2716 */
2717IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2718{
2719# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2720 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2721 return VINF_EM_RAW_EMULATE_INSTR;
2722# else
2723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2724 Assert(pVmcs);
2725
2726 /*
2727 * Import all the guest-CPU state.
2728 *
2729 * HM on returning to guest execution would have to reset up a whole lot of state
2730 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2731 * the state and flag reloading the entire state on re-entry. So import the entire
2732 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2733 */
2734 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2735
2736 /* Ensure VM-entry interruption information valid bit isn't set. */
2737 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2738
2739 /*
2740 * Update the VM-exit reason and Exit qualification.
2741 * Other VMCS read-only data fields are expected to be updated by the caller already.
2742 */
2743 pVmcs->u32RoExitReason = uExitReason;
2744 pVmcs->u64RoExitQual.u = u64ExitQual;
2745 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2746 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2747
2748 /*
2749 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2750 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2751 */
2752 {
2753 uint8_t uVector;
2754 uint32_t fFlags;
2755 uint32_t uErrCode;
2756 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2757 if (fInEventDelivery)
2758 {
2759 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2760 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2761 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2762 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2763 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2764 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2765 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2766 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2767 }
2768 }
2769
2770 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2771 Assert(pVmcs->u64RoIoRcx.u == 0);
2772 Assert(pVmcs->u64RoIoRsi.u == 0);
2773 Assert(pVmcs->u64RoIoRdi.u == 0);
2774 Assert(pVmcs->u64RoIoRip.u == 0);
2775
2776 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2777 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2778 {
2779 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2780 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2781 }
2782
2783 /*
2784 * Save the guest state back into the VMCS.
2785 * We only need to save the state when the VM-entry was successful.
2786 */
2787 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2788 if (!fVmentryFailed)
2789 {
2790 /*
2791 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2792 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2793 *
2794 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2795 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2796 * as guest-CPU state would not been modified. Hence for now, we do this only when
2797 * the VM-entry succeeded.
2798 */
2799 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2800 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2801 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2802 {
2803 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2804 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2805 else
2806 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2807 }
2808
2809 /*
2810 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2811 * occurs in enclave mode/SMM which we don't support yet.
2812 *
2813 * If we ever add support for it, we can pass just the lower bits to the functions
2814 * below, till then an assert should suffice.
2815 */
2816 Assert(!RT_HI_U16(uExitReason));
2817
2818 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2819 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2820 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2821 if (RT_SUCCESS(rc))
2822 { /* likely */ }
2823 else
2824 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2825
2826 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2827 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2828 }
2829 else
2830 {
2831 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2832 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2833 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2834 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2835 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2836 }
2837
2838 /*
2839 * Clear any pending VMX nested-guest force-flags.
2840 * These force-flags have no effect on guest execution and will
2841 * be re-evaluated and setup on the next nested-guest VM-entry.
2842 */
2843 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2844 | VMCPU_FF_VMX_MTF
2845 | VMCPU_FF_VMX_APIC_WRITE
2846 | VMCPU_FF_VMX_INT_WINDOW
2847 | VMCPU_FF_VMX_NMI_WINDOW);
2848
2849 /* Restore the host (outer guest) state. */
2850 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2851 if (RT_SUCCESS(rcStrict))
2852 {
2853 Assert(rcStrict == VINF_SUCCESS);
2854 rcStrict = VINF_VMX_VMEXIT;
2855 }
2856 else
2857 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2858
2859 /* Notify HM that we've completed the VM-exit. */
2860 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2861
2862 /* We're no longer in nested-guest execution mode. */
2863 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2864
2865# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2866 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2867 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2868 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2869 if (rcSched != VINF_SUCCESS)
2870 iemSetPassUpStatus(pVCpu, rcSched);
2871# endif
2872 return rcStrict;
2873# endif
2874}
2875
2876
2877/**
2878 * VMX VM-exit handler for VM-exits due to instruction execution.
2879 *
2880 * This is intended for instructions where the caller provides all the relevant
2881 * VM-exit information.
2882 *
2883 * @returns Strict VBox status code.
2884 * @param pVCpu The cross context virtual CPU structure.
2885 * @param pExitInfo Pointer to the VM-exit information.
2886 */
2887IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2888{
2889 /*
2890 * For instructions where any of the following fields are not applicable:
2891 * - Exit qualification must be cleared.
2892 * - VM-exit instruction info. is undefined.
2893 * - Guest-linear address is undefined.
2894 * - Guest-physical address is undefined.
2895 *
2896 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2897 * instruction execution. For VM-exits that are not due to instruction execution this
2898 * field is undefined.
2899 *
2900 * In our implementation in IEM, all undefined fields are generally cleared. However,
2901 * if the caller supplies information (from say the physical CPU directly) it is
2902 * then possible that the undefined fields are not cleared.
2903 *
2904 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2905 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2906 */
2907 Assert(pExitInfo);
2908 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2909 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2910 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2911
2912 /* Update all the relevant fields from the VM-exit instruction information struct. */
2913 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2914 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2915 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2916 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2917
2918 /* Perform the VM-exit. */
2919 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2920}
2921
2922
2923/**
2924 * VMX VM-exit handler for VM-exits due to instruction execution.
2925 *
2926 * This is intended for instructions that only provide the VM-exit instruction
2927 * length.
2928 *
2929 * @param pVCpu The cross context virtual CPU structure.
2930 * @param uExitReason The VM-exit reason.
2931 * @param cbInstr The instruction length in bytes.
2932 */
2933IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2934{
2935 VMXVEXITINFO ExitInfo;
2936 RT_ZERO(ExitInfo);
2937 ExitInfo.uReason = uExitReason;
2938 ExitInfo.cbInstr = cbInstr;
2939
2940#ifdef VBOX_STRICT
2941 /*
2942 * To prevent us from shooting ourselves in the foot.
2943 * The follow instructions should convey more than just the instruction length.
2944 */
2945 switch (uExitReason)
2946 {
2947 case VMX_EXIT_INVEPT:
2948 case VMX_EXIT_INVPCID:
2949 case VMX_EXIT_INVVPID:
2950 case VMX_EXIT_LDTR_TR_ACCESS:
2951 case VMX_EXIT_GDTR_IDTR_ACCESS:
2952 case VMX_EXIT_VMCLEAR:
2953 case VMX_EXIT_VMPTRLD:
2954 case VMX_EXIT_VMPTRST:
2955 case VMX_EXIT_VMREAD:
2956 case VMX_EXIT_VMWRITE:
2957 case VMX_EXIT_VMXON:
2958 case VMX_EXIT_XRSTORS:
2959 case VMX_EXIT_XSAVES:
2960 case VMX_EXIT_RDRAND:
2961 case VMX_EXIT_RDSEED:
2962 case VMX_EXIT_IO_INSTR:
2963 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2964 break;
2965 }
2966#endif
2967
2968 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2969}
2970
2971
2972/**
2973 * VMX VM-exit handler for VM-exits due to instruction execution.
2974 *
2975 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2976 * instruction information and Exit qualification fields.
2977 *
2978 * @param pVCpu The cross context virtual CPU structure.
2979 * @param uExitReason The VM-exit reason.
2980 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2981 * @param cbInstr The instruction length in bytes.
2982 *
2983 * @remarks Do not use this for INS/OUTS instruction.
2984 */
2985IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2986{
2987 VMXVEXITINFO ExitInfo;
2988 RT_ZERO(ExitInfo);
2989 ExitInfo.uReason = uExitReason;
2990 ExitInfo.cbInstr = cbInstr;
2991
2992 /*
2993 * Update the Exit qualification field with displacement bytes.
2994 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2995 */
2996 switch (uExitReason)
2997 {
2998 case VMX_EXIT_INVEPT:
2999 case VMX_EXIT_INVPCID:
3000 case VMX_EXIT_INVVPID:
3001 case VMX_EXIT_LDTR_TR_ACCESS:
3002 case VMX_EXIT_GDTR_IDTR_ACCESS:
3003 case VMX_EXIT_VMCLEAR:
3004 case VMX_EXIT_VMPTRLD:
3005 case VMX_EXIT_VMPTRST:
3006 case VMX_EXIT_VMREAD:
3007 case VMX_EXIT_VMWRITE:
3008 case VMX_EXIT_VMXON:
3009 case VMX_EXIT_XRSTORS:
3010 case VMX_EXIT_XSAVES:
3011 case VMX_EXIT_RDRAND:
3012 case VMX_EXIT_RDSEED:
3013 {
3014 /* Construct the VM-exit instruction information. */
3015 RTGCPTR GCPtrDisp;
3016 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3017
3018 /* Update the VM-exit instruction information. */
3019 ExitInfo.InstrInfo.u = uInstrInfo;
3020
3021 /* Update the Exit qualification. */
3022 ExitInfo.u64Qual = GCPtrDisp;
3023 break;
3024 }
3025
3026 default:
3027 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3028 break;
3029 }
3030
3031 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3032}
3033
3034
3035/**
3036 * VMX VM-exit handler for VM-exits due to INVLPG.
3037 *
3038 * @returns Strict VBox status code.
3039 * @param pVCpu The cross context virtual CPU structure.
3040 * @param GCPtrPage The guest-linear address of the page being invalidated.
3041 * @param cbInstr The instruction length in bytes.
3042 */
3043IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3044{
3045 VMXVEXITINFO ExitInfo;
3046 RT_ZERO(ExitInfo);
3047 ExitInfo.uReason = VMX_EXIT_INVLPG;
3048 ExitInfo.cbInstr = cbInstr;
3049 ExitInfo.u64Qual = GCPtrPage;
3050 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3051
3052 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3053}
3054
3055
3056/**
3057 * VMX VM-exit handler for VM-exits due to LMSW.
3058 *
3059 * @returns Strict VBox status code.
3060 * @param pVCpu The cross context virtual CPU structure.
3061 * @param uGuestCr0 The current guest CR0.
3062 * @param pu16NewMsw The machine-status word specified in LMSW's source
3063 * operand. This will be updated depending on the VMX
3064 * guest/host CR0 mask if LMSW is not intercepted.
3065 * @param GCPtrEffDst The guest-linear address of the source operand in case
3066 * of a memory operand. For register operand, pass
3067 * NIL_RTGCPTR.
3068 * @param cbInstr The instruction length in bytes.
3069 */
3070IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3071 uint8_t cbInstr)
3072{
3073 Assert(pu16NewMsw);
3074
3075 uint16_t const uNewMsw = *pu16NewMsw;
3076 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3077 {
3078 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3079
3080 VMXVEXITINFO ExitInfo;
3081 RT_ZERO(ExitInfo);
3082 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3083 ExitInfo.cbInstr = cbInstr;
3084
3085 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3086 if (fMemOperand)
3087 {
3088 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3089 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3090 }
3091
3092 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3094 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3095 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3096
3097 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3098 }
3099
3100 /*
3101 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3102 * CR0 guest/host mask must be left unmodified.
3103 *
3104 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3105 */
3106 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3107 Assert(pVmcs);
3108 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3109 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3110 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3111
3112 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3113}
3114
3115
3116/**
3117 * VMX VM-exit handler for VM-exits due to CLTS.
3118 *
3119 * @returns Strict VBox status code.
3120 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3121 * VM-exit but must not modify the guest CR0.TS bit.
3122 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3123 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3124 * CR0 fixed bits in VMX operation).
3125 * @param pVCpu The cross context virtual CPU structure.
3126 * @param cbInstr The instruction length in bytes.
3127 */
3128IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3129{
3130 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3131 Assert(pVmcs);
3132
3133 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3134 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3135
3136 /*
3137 * If CR0.TS is owned by the host:
3138 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3139 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3140 * CLTS instruction completes without clearing CR0.TS.
3141 *
3142 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3143 */
3144 if (fGstHostMask & X86_CR0_TS)
3145 {
3146 if (fReadShadow & X86_CR0_TS)
3147 {
3148 Log2(("clts: Guest intercept -> VM-exit\n"));
3149
3150 VMXVEXITINFO ExitInfo;
3151 RT_ZERO(ExitInfo);
3152 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3153 ExitInfo.cbInstr = cbInstr;
3154 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3155 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3156 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3157 }
3158
3159 return VINF_VMX_MODIFIES_BEHAVIOR;
3160 }
3161
3162 /*
3163 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3164 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3165 */
3166 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3167}
3168
3169
3170/**
3171 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3172 * (CR0/CR4 write).
3173 *
3174 * @returns Strict VBox status code.
3175 * @param pVCpu The cross context virtual CPU structure.
3176 * @param iCrReg The control register (either CR0 or CR4).
3177 * @param uGuestCrX The current guest CR0/CR4.
3178 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3179 * if no VM-exit is caused.
3180 * @param iGReg The general register from which the CR0/CR4 value is
3181 * being loaded.
3182 * @param cbInstr The instruction length in bytes.
3183 */
3184IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3185 uint8_t cbInstr)
3186{
3187 Assert(puNewCrX);
3188 Assert(iCrReg == 0 || iCrReg == 4);
3189 Assert(iGReg < X86_GREG_COUNT);
3190
3191 uint64_t const uNewCrX = *puNewCrX;
3192 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3193 {
3194 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3195
3196 VMXVEXITINFO ExitInfo;
3197 RT_ZERO(ExitInfo);
3198 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3199 ExitInfo.cbInstr = cbInstr;
3200 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3201 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3202 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3203 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3204 }
3205
3206 /*
3207 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3208 * must not be modified the instruction.
3209 *
3210 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3211 */
3212 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3213 Assert(pVmcs);
3214 uint64_t uGuestCrX;
3215 uint64_t fGstHostMask;
3216 if (iCrReg == 0)
3217 {
3218 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3219 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3220 fGstHostMask = pVmcs->u64Cr0Mask.u;
3221 }
3222 else
3223 {
3224 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3225 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3226 fGstHostMask = pVmcs->u64Cr4Mask.u;
3227 }
3228
3229 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3230 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3231}
3232
3233
3234/**
3235 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3236 *
3237 * @returns VBox strict status code.
3238 * @param pVCpu The cross context virtual CPU structure.
3239 * @param iGReg The general register to which the CR3 value is being stored.
3240 * @param cbInstr The instruction length in bytes.
3241 */
3242IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3243{
3244 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3245 Assert(pVmcs);
3246 Assert(iGReg < X86_GREG_COUNT);
3247 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3248
3249 /*
3250 * If the CR3-store exiting control is set, we must cause a VM-exit.
3251 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3252 */
3253 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3254 {
3255 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3256
3257 VMXVEXITINFO ExitInfo;
3258 RT_ZERO(ExitInfo);
3259 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3260 ExitInfo.cbInstr = cbInstr;
3261 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3262 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3263 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3264 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3265 }
3266
3267 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3268}
3269
3270
3271/**
3272 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3273 *
3274 * @returns VBox strict status code.
3275 * @param pVCpu The cross context virtual CPU structure.
3276 * @param uNewCr3 The new CR3 value.
3277 * @param iGReg The general register from which the CR3 value is being
3278 * loaded.
3279 * @param cbInstr The instruction length in bytes.
3280 */
3281IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3282{
3283 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3284 Assert(pVmcs);
3285 Assert(iGReg < X86_GREG_COUNT);
3286
3287 /*
3288 * If the CR3-load exiting control is set and the new CR3 value does not
3289 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3290 *
3291 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3292 */
3293 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3294 {
3295 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3296 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3297
3298 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3299 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3300 if (!fIntercept)
3301 {
3302 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3303 {
3304 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3305 if (uNewCr3 != uCr3TargetValue)
3306 {
3307 fIntercept = true;
3308 break;
3309 }
3310 }
3311 }
3312
3313 if (fIntercept)
3314 {
3315 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3316
3317 VMXVEXITINFO ExitInfo;
3318 RT_ZERO(ExitInfo);
3319 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3320 ExitInfo.cbInstr = cbInstr;
3321 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3322 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3323 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3324 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3325 }
3326 }
3327
3328 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3329}
3330
3331
3332/**
3333 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3334 *
3335 * @returns VBox strict status code.
3336 * @param pVCpu The cross context virtual CPU structure.
3337 * @param iGReg The general register to which the CR8 value is being stored.
3338 * @param cbInstr The instruction length in bytes.
3339 */
3340IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3341{
3342 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3343 Assert(pVmcs);
3344 Assert(iGReg < X86_GREG_COUNT);
3345
3346 /*
3347 * If the CR8-store exiting control is set, we must cause a VM-exit.
3348 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3349 */
3350 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3351 {
3352 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3353
3354 VMXVEXITINFO ExitInfo;
3355 RT_ZERO(ExitInfo);
3356 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3357 ExitInfo.cbInstr = cbInstr;
3358 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3359 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3360 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3361 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3362 }
3363
3364 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3365}
3366
3367
3368/**
3369 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3370 *
3371 * @returns VBox strict status code.
3372 * @param pVCpu The cross context virtual CPU structure.
3373 * @param iGReg The general register from which the CR8 value is being
3374 * loaded.
3375 * @param cbInstr The instruction length in bytes.
3376 */
3377IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3378{
3379 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3380 Assert(pVmcs);
3381 Assert(iGReg < X86_GREG_COUNT);
3382
3383 /*
3384 * If the CR8-load exiting control is set, we must cause a VM-exit.
3385 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3386 */
3387 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3388 {
3389 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3390
3391 VMXVEXITINFO ExitInfo;
3392 RT_ZERO(ExitInfo);
3393 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3394 ExitInfo.cbInstr = cbInstr;
3395 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3396 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3397 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3398 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3399 }
3400
3401 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3402}
3403
3404
3405/**
3406 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3407 * GReg,DRx' (DRx read).
3408 *
3409 * @returns VBox strict status code.
3410 * @param pVCpu The cross context virtual CPU structure.
3411 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3412 * VMXINSTRID_MOV_FROM_DRX).
3413 * @param iDrReg The debug register being accessed.
3414 * @param iGReg The general register to/from which the DRx value is being
3415 * store/loaded.
3416 * @param cbInstr The instruction length in bytes.
3417 */
3418IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3419 uint8_t cbInstr)
3420{
3421 Assert(iDrReg <= 7);
3422 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3423 Assert(iGReg < X86_GREG_COUNT);
3424
3425 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3426 Assert(pVmcs);
3427
3428 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3429 {
3430 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3431 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3432 VMXVEXITINFO ExitInfo;
3433 RT_ZERO(ExitInfo);
3434 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3435 ExitInfo.cbInstr = cbInstr;
3436 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3437 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3438 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3439 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3440 }
3441
3442 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3443}
3444
3445
3446/**
3447 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3448 *
3449 * @returns VBox strict status code.
3450 * @param pVCpu The cross context virtual CPU structure.
3451 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3452 * VMXINSTRID_IO_OUT).
3453 * @param u16Port The I/O port being accessed.
3454 * @param fImm Whether the I/O port was encoded using an immediate operand
3455 * or the implicit DX register.
3456 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3457 * @param cbInstr The instruction length in bytes.
3458 */
3459IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3460 uint8_t cbInstr)
3461{
3462 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3463 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3464
3465 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3466 if (fIntercept)
3467 {
3468 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3469 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3470 VMXVEXITINFO ExitInfo;
3471 RT_ZERO(ExitInfo);
3472 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3473 ExitInfo.cbInstr = cbInstr;
3474 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3476 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3477 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3478 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3479 }
3480
3481 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3482}
3483
3484
3485/**
3486 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3487 *
3488 * @returns VBox strict status code.
3489 * @param pVCpu The cross context virtual CPU structure.
3490 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3491 * VMXINSTRID_IO_OUTS).
3492 * @param u16Port The I/O port being accessed.
3493 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3494 * @param fRep Whether the instruction has a REP prefix or not.
3495 * @param ExitInstrInfo The VM-exit instruction info. field.
3496 * @param cbInstr The instruction length in bytes.
3497 */
3498IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3499 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3500{
3501 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3502 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3503 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3504 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3505 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3506
3507 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3508 if (fIntercept)
3509 {
3510 /*
3511 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3512 */
3513 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3514 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3515 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3516 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3517 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3518
3519 uint32_t uDirection;
3520 uint64_t uGuestLinearAddr;
3521 if (uInstrId == VMXINSTRID_IO_INS)
3522 {
3523 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3524 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3525 }
3526 else
3527 {
3528 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3529 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3530 }
3531
3532 /*
3533 * If the segment is unusable, the guest-linear address in undefined.
3534 * We shall clear it for consistency.
3535 *
3536 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3537 */
3538 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3539 uGuestLinearAddr = 0;
3540
3541 VMXVEXITINFO ExitInfo;
3542 RT_ZERO(ExitInfo);
3543 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3544 ExitInfo.cbInstr = cbInstr;
3545 ExitInfo.InstrInfo = ExitInstrInfo;
3546 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3547 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3548 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3549 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3550 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3551 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3552 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3553 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3554 }
3555
3556 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3557}
3558
3559
3560/**
3561 * VMX VM-exit handler for VM-exits due to MWAIT.
3562 *
3563 * @returns VBox strict status code.
3564 * @param pVCpu The cross context virtual CPU structure.
3565 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3566 * @param cbInstr The instruction length in bytes.
3567 */
3568IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3569{
3570 VMXVEXITINFO ExitInfo;
3571 RT_ZERO(ExitInfo);
3572 ExitInfo.uReason = VMX_EXIT_MWAIT;
3573 ExitInfo.cbInstr = cbInstr;
3574 ExitInfo.u64Qual = fMonitorHwArmed;
3575 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3576}
3577
3578
3579/**
3580 * VMX VM-exit handler for VM-exits due to PAUSE.
3581 *
3582 * @returns VBox strict status code.
3583 * @param pVCpu The cross context virtual CPU structure.
3584 * @param cbInstr The instruction length in bytes.
3585 */
3586IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3587{
3588 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3589 Assert(pVmcs);
3590
3591 /*
3592 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3593 * "PAUSE-loop exiting" control.
3594 *
3595 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3596 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3597 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3598 * a VM-exit.
3599 *
3600 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3601 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3602 */
3603 bool fIntercept = false;
3604 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3605 fIntercept = true;
3606 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3607 && pVCpu->iem.s.uCpl == 0)
3608 {
3609 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3610
3611 /*
3612 * A previous-PAUSE-tick value of 0 is used to identify the first time
3613 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3614 * consider this to be the first execution of PAUSE in a loop according
3615 * to the Intel.
3616 *
3617 * All subsequent records for the previous-PAUSE-tick we ensure that it
3618 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3619 */
3620 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3621 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3622 uint64_t const uTick = TMCpuTickGet(pVCpu);
3623 uint32_t const uPleGap = pVmcs->u32PleGap;
3624 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3625 if ( *puPrevPauseTick == 0
3626 || uTick - *puPrevPauseTick > uPleGap)
3627 *puFirstPauseLoopTick = uTick;
3628 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3629 fIntercept = true;
3630
3631 *puPrevPauseTick = uTick | 1;
3632 }
3633
3634 if (fIntercept)
3635 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3636
3637 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3638}
3639
3640
3641/**
3642 * VMX VM-exit handler for VM-exits due to task switches.
3643 *
3644 * @returns VBox strict status code.
3645 * @param pVCpu The cross context virtual CPU structure.
3646 * @param enmTaskSwitch The cause of the task switch.
3647 * @param SelNewTss The selector of the new TSS.
3648 * @param cbInstr The instruction length in bytes.
3649 */
3650IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3651{
3652 /*
3653 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3654 *
3655 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3656 * instruction or delivery of the exception generated by one of these instructions
3657 * lead to a task switch through a task gate in the IDT, we need to provide the
3658 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3659 * leaves the VM-exit instruction length field undefined.
3660 *
3661 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3662 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3663 */
3664 Assert(cbInstr <= 15);
3665
3666 uint8_t uType;
3667 switch (enmTaskSwitch)
3668 {
3669 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3670 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3671 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3672 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3673 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3674 }
3675
3676 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3677 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3678 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3679 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3680}
3681
3682
3683/**
3684 * VMX VM-exit handler for VM-exits due to task switches.
3685 *
3686 * This is intended for task switches where the caller provides all the relevant
3687 * VM-exit information.
3688 *
3689 * @returns VBox strict status code.
3690 * @param pVCpu The cross context virtual CPU structure.
3691 * @param pExitInfo Pointer to the VM-exit information.
3692 * @param pExitEventInfo Pointer to the VM-exit event information.
3693 */
3694IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3695 PCVMXVEXITEVENTINFO pExitEventInfo)
3696{
3697 Assert(pExitInfo);
3698 Assert(pExitEventInfo);
3699
3700 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3701 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3702 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3703
3704 /*
3705 * Figure out if an instruction was the source of the task switch.
3706 *
3707 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3708 * of an event generated by a software interrupt (INT-N), privileged software
3709 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3710 * the instruction length.
3711 */
3712 bool fHasInstrLen;
3713 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3714 {
3715 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3716 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3717 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3718 if (fIdtVectInfoValid)
3719 {
3720 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3721 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3722 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3723
3724 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3725 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3726 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3727 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3728 fHasInstrLen = true;
3729 else
3730 fHasInstrLen = false;
3731 }
3732 else
3733 fHasInstrLen = false;
3734 }
3735 else
3736 {
3737 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3738 fHasInstrLen = true;
3739 }
3740
3741 if (fHasInstrLen)
3742 {
3743 Assert(pExitInfo->cbInstr > 0);
3744 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3745 }
3746 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3747}
3748
3749
3750/**
3751 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3752 *
3753 * @returns VBox strict status code.
3754 * @param pVCpu The cross context virtual CPU structure.
3755 */
3756IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3757{
3758 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3759 Assert(pVmcs);
3760
3761 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3762 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3763 {
3764 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3765 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3766
3767 /*
3768 * Calculate the current VMX-preemption timer value.
3769 * Only if the value has reached zero, we cause the VM-exit.
3770 */
3771 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3772 if (!uPreemptTimer)
3773 {
3774 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3775 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3776 pVmcs->u32PreemptTimer = 0;
3777
3778 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3779 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3780 }
3781 }
3782
3783 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3784}
3785
3786
3787/**
3788 * VMX VM-exit handler for VM-exits due to external interrupts.
3789 *
3790 * @returns VBox strict status code.
3791 * @param pVCpu The cross context virtual CPU structure.
3792 * @param uVector The external interrupt vector (pass 0 if the interrupt
3793 * is still pending since we typically won't know the
3794 * vector).
3795 * @param fIntPending Whether the external interrupt is pending or
3796 * acknowledged in the interrupt controller.
3797 */
3798IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3799{
3800 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3801 Assert(pVmcs);
3802 Assert(fIntPending || uVector == 0);
3803
3804 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3805 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3806 * functions require prior checking of a blanket intercept and which don't.
3807 * It is better for the caller to check a blanket intercept performance wise
3808 * than making a function call. Leaving this as a todo because it is more
3809 * a performance issue. */
3810
3811 /* The VM-exit is subject to "External interrupt exiting" being set. */
3812 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3813 {
3814 if (fIntPending)
3815 {
3816 /*
3817 * If the interrupt is pending and we don't need to acknowledge the
3818 * interrupt on VM-exit, cause the VM-exit immediately.
3819 *
3820 * See Intel spec 25.2 "Other Causes Of VM Exits".
3821 */
3822 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3823 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3824
3825 /*
3826 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3827 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3828 * acknowledged that the interrupt has been consumed.
3829 */
3830 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3831 }
3832
3833 /*
3834 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3835 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3836 * all set, we cause the VM-exit now. We need to record the external interrupt that
3837 * just occurred in the VM-exit interruption information field.
3838 *
3839 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3840 */
3841 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3842 {
3843 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3844 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3845 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3846 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3847 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3848 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3849 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3850 }
3851 }
3852
3853 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3854}
3855
3856
3857/**
3858 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3859 * an event.
3860 *
3861 * @returns VBox strict status code.
3862 * @param pVCpu The cross context virtual CPU structure.
3863 */
3864IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3865{
3866 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3867 Assert(pVmcs);
3868
3869 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3870 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3871 {
3872 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3873 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3874 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3875 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3876 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3877 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3878 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3879 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3880 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3881
3882 /*
3883 * A VM-exit is not considered to occur during event delivery when the original
3884 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3885 * using the exception bitmap).
3886 *
3887 * Therefore, we must clear the original event from the IDT-vectoring fields which
3888 * would've been recorded before causing the VM-exit.
3889 *
3890 * 27.2.3 "Information for VM Exits During Event Delivery"
3891 */
3892 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3893 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3894 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3895 }
3896
3897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3898}
3899
3900
3901/**
3902 * VMX VM-exit handler for VM-exit due to delivery of an events.
3903 *
3904 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3905 * all the relevant VM-exit information.
3906 *
3907 * @returns VBox strict status code.
3908 * @param pVCpu The cross context virtual CPU structure.
3909 * @param pExitInfo Pointer to the VM-exit information.
3910 * @param pExitEventInfo Pointer to the VM-exit event information.
3911 */
3912IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3913{
3914 Assert(pExitInfo);
3915 Assert(pExitEventInfo);
3916 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3917
3918 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3919 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3920 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3921 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3922 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3923 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3924}
3925
3926
3927/**
3928 * VMX VM-exit handler for VM-exits due to delivery of an event.
3929 *
3930 * @returns VBox strict status code.
3931 * @param pVCpu The cross context virtual CPU structure.
3932 * @param uVector The interrupt / exception vector.
3933 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3934 * @param uErrCode The error code associated with the event.
3935 * @param uCr2 The CR2 value in case of a \#PF exception.
3936 * @param cbInstr The instruction length in bytes.
3937 */
3938IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3939 uint8_t cbInstr)
3940{
3941 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3942 Assert(pVmcs);
3943
3944 /*
3945 * If the event is being injected as part of VM-entry, it is -not- subject to event
3946 * intercepts in the nested-guest. However, secondary exceptions that occur during
3947 * injection of any event -are- subject to event interception.
3948 *
3949 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3950 */
3951 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3952 {
3953 /*
3954 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3955 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3956 *
3957 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3958 */
3959 if ( uVector == X86_XCPT_NMI
3960 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3961 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3962 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3963 else
3964 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3965
3966 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3967 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3968 }
3969
3970 /*
3971 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3972 * If not, the caller will continue delivery of the external interrupt as it would
3973 * normally. The interrupt is no longer pending in the interrupt controller at this
3974 * point.
3975 */
3976 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3977 {
3978 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3979 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3980 }
3981
3982 /*
3983 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3984 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3985 * interrupts.
3986 */
3987 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3988 bool fIntercept;
3989 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3990 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3991 {
3992 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3993 }
3994 else
3995 {
3996 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3997 fIntercept = false;
3998 }
3999
4000 /*
4001 * Now that we've determined whether the event causes a VM-exit, we need to construct the
4002 * relevant VM-exit information and cause the VM-exit.
4003 */
4004 if (fIntercept)
4005 {
4006 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4007
4008 /* Construct the rest of the event related information fields and cause the VM-exit. */
4009 uint64_t u64ExitQual;
4010 if (uVector == X86_XCPT_PF)
4011 {
4012 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4013 u64ExitQual = uCr2;
4014 }
4015 else if (uVector == X86_XCPT_DB)
4016 {
4017 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4018 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4019 }
4020 else
4021 u64ExitQual = 0;
4022
4023 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4024 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4025 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4026 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4027 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4028 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4029 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4030 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4031 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4032 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4033
4034 /*
4035 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
4036 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4037 * length.
4038 */
4039 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4040 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4041 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4042 else
4043 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4044
4045 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
4046 }
4047
4048 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4049}
4050
4051
4052/**
4053 * VMX VM-exit handler for VM-exits due to a triple fault.
4054 *
4055 * @returns VBox strict status code.
4056 * @param pVCpu The cross context virtual CPU structure.
4057 */
4058IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4059{
4060 /*
4061 * A VM-exit is not considered to occur during event delivery when the original
4062 * event results in a triple-fault.
4063 *
4064 * Therefore, we must clear the original event from the IDT-vectoring fields which
4065 * would've been recorded before causing the VM-exit.
4066 *
4067 * 27.2.3 "Information for VM Exits During Event Delivery"
4068 */
4069 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4070 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4071
4072 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
4073}
4074
4075
4076/**
4077 * VMX VM-exit handler for APIC accesses.
4078 *
4079 * @param pVCpu The cross context virtual CPU structure.
4080 * @param offAccess The offset of the register being accessed.
4081 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4082 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4083 */
4084IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4085{
4086 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4087
4088 VMXAPICACCESS enmAccess;
4089 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4090 if (fInEventDelivery)
4091 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4092 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4093 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4094 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4095 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4096 else
4097 enmAccess = VMXAPICACCESS_LINEAR_READ;
4098
4099 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4100 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4101 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4102}
4103
4104
4105/**
4106 * VMX VM-exit handler for APIC accesses.
4107 *
4108 * This is intended for APIC accesses where the caller provides all the
4109 * relevant VM-exit information.
4110 *
4111 * @returns VBox strict status code.
4112 * @param pVCpu The cross context virtual CPU structure.
4113 * @param pExitInfo Pointer to the VM-exit information.
4114 * @param pExitEventInfo Pointer to the VM-exit event information.
4115 */
4116IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
4117 PCVMXVEXITEVENTINFO pExitEventInfo)
4118{
4119 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4120 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4121 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4122 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4123 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4124 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4125 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4126}
4127
4128
4129/**
4130 * VMX VM-exit handler for APIC-write VM-exits.
4131 *
4132 * @param pVCpu The cross context virtual CPU structure.
4133 * @param offApic The write to the virtual-APIC page offset that caused this
4134 * VM-exit.
4135 */
4136IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4137{
4138 Assert(offApic < XAPIC_OFF_END + 4);
4139 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4140 offApic &= UINT16_C(0xfff);
4141 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4142}
4143
4144
4145/**
4146 * Sets virtual-APIC write emulation as pending.
4147 *
4148 * @param pVCpu The cross context virtual CPU structure.
4149 * @param offApic The offset in the virtual-APIC page that was written.
4150 */
4151DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4152{
4153 Assert(offApic < XAPIC_OFF_END + 4);
4154
4155 /*
4156 * Record the currently updated APIC offset, as we need this later for figuring
4157 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4158 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4159 */
4160 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4161
4162 /*
4163 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4164 * virtualization or APIC-write emulation).
4165 */
4166 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4167 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4168}
4169
4170
4171/**
4172 * Clears any pending virtual-APIC write emulation.
4173 *
4174 * @returns The virtual-APIC offset that was written before clearing it.
4175 * @param pVCpu The cross context virtual CPU structure.
4176 */
4177DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4178{
4179 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4180 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4181 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4182 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4183 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4184 return offVirtApicWrite;
4185}
4186
4187
4188/**
4189 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4190 *
4191 * @returns The register from the virtual-APIC page.
4192 * @param pVCpu The cross context virtual CPU structure.
4193 * @param offReg The offset of the register being read.
4194 */
4195IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4196{
4197 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4198 Assert(pVmcs);
4199
4200 uint32_t uReg;
4201 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4202 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4203 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4204 if (RT_FAILURE(rc))
4205 {
4206 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4207 GCPhysVirtApic));
4208 uReg = 0;
4209 }
4210 return uReg;
4211}
4212
4213
4214/**
4215 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4216 *
4217 * @returns The register from the virtual-APIC page.
4218 * @param pVCpu The cross context virtual CPU structure.
4219 * @param offReg The offset of the register being read.
4220 */
4221IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4222{
4223 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4224 Assert(pVmcs);
4225
4226 uint64_t uReg;
4227 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4228 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4229 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4230 if (RT_FAILURE(rc))
4231 {
4232 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4233 GCPhysVirtApic));
4234 uReg = 0;
4235 }
4236 return uReg;
4237}
4238
4239
4240/**
4241 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4242 *
4243 * @param pVCpu The cross context virtual CPU structure.
4244 * @param offReg The offset of the register being written.
4245 * @param uReg The register value to write.
4246 */
4247IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4248{
4249 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4250 Assert(pVmcs);
4251 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4252 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4253 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4254 if (RT_FAILURE(rc))
4255 {
4256 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4257 GCPhysVirtApic));
4258 }
4259}
4260
4261
4262/**
4263 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4264 *
4265 * @param pVCpu The cross context virtual CPU structure.
4266 * @param offReg The offset of the register being written.
4267 * @param uReg The register value to write.
4268 */
4269IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4270{
4271 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4272 Assert(pVmcs);
4273 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4274 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4275 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4276 if (RT_FAILURE(rc))
4277 {
4278 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4279 GCPhysVirtApic));
4280 }
4281}
4282
4283
4284/**
4285 * Sets the vector in a virtual-APIC 256-bit sparse register.
4286 *
4287 * @param pVCpu The cross context virtual CPU structure.
4288 * @param offReg The offset of the 256-bit spare register.
4289 * @param uVector The vector to set.
4290 *
4291 * @remarks This is based on our APIC device code.
4292 */
4293IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4294{
4295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4296 Assert(pVmcs);
4297 uint32_t uReg;
4298 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4299 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4300 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4301 if (RT_SUCCESS(rc))
4302 {
4303 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4304 uReg |= RT_BIT(idxVectorBit);
4305 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4306 if (RT_FAILURE(rc))
4307 {
4308 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4309 uVector, offReg, GCPhysVirtApic));
4310 }
4311 }
4312 else
4313 {
4314 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4315 uVector, offReg, GCPhysVirtApic));
4316 }
4317}
4318
4319
4320/**
4321 * Clears the vector in a virtual-APIC 256-bit sparse register.
4322 *
4323 * @param pVCpu The cross context virtual CPU structure.
4324 * @param offReg The offset of the 256-bit spare register.
4325 * @param uVector The vector to clear.
4326 *
4327 * @remarks This is based on our APIC device code.
4328 */
4329IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4330{
4331 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4332 Assert(pVmcs);
4333 uint32_t uReg;
4334 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4335 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4336 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4337 if (RT_SUCCESS(rc))
4338 {
4339 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4340 uReg &= ~RT_BIT(idxVectorBit);
4341 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4342 if (RT_FAILURE(rc))
4343 {
4344 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4345 uVector, offReg, GCPhysVirtApic));
4346 }
4347 }
4348 else
4349 {
4350 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4351 uVector, offReg, GCPhysVirtApic));
4352 }
4353}
4354
4355
4356/**
4357 * Checks if a memory access to the APIC-access page must causes an APIC-access
4358 * VM-exit.
4359 *
4360 * @param pVCpu The cross context virtual CPU structure.
4361 * @param offAccess The offset of the register being accessed.
4362 * @param cbAccess The size of the access in bytes.
4363 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4364 * IEM_ACCESS_TYPE_WRITE).
4365 *
4366 * @remarks This must not be used for MSR-based APIC-access page accesses!
4367 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4368 */
4369IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4370{
4371 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4372 Assert(pVmcs);
4373 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4374
4375 /*
4376 * We must cause a VM-exit if any of the following are true:
4377 * - TPR shadowing isn't active.
4378 * - The access size exceeds 32-bits.
4379 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4380 *
4381 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4382 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4383 */
4384 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4385 || cbAccess > sizeof(uint32_t)
4386 || ((offAccess + cbAccess - 1) & 0xc)
4387 || offAccess >= XAPIC_OFF_END + 4)
4388 return true;
4389
4390 /*
4391 * If the access is part of an operation where we have already
4392 * virtualized a virtual-APIC write, we must cause a VM-exit.
4393 */
4394 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4395 return true;
4396
4397 /*
4398 * Check write accesses to the APIC-access page that cause VM-exits.
4399 */
4400 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4401 {
4402 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4403 {
4404 /*
4405 * With APIC-register virtualization, a write access to any of the
4406 * following registers are virtualized. Accessing any other register
4407 * causes a VM-exit.
4408 */
4409 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4410 switch (offAlignedAccess)
4411 {
4412 case XAPIC_OFF_ID:
4413 case XAPIC_OFF_TPR:
4414 case XAPIC_OFF_EOI:
4415 case XAPIC_OFF_LDR:
4416 case XAPIC_OFF_DFR:
4417 case XAPIC_OFF_SVR:
4418 case XAPIC_OFF_ESR:
4419 case XAPIC_OFF_ICR_LO:
4420 case XAPIC_OFF_ICR_HI:
4421 case XAPIC_OFF_LVT_TIMER:
4422 case XAPIC_OFF_LVT_THERMAL:
4423 case XAPIC_OFF_LVT_PERF:
4424 case XAPIC_OFF_LVT_LINT0:
4425 case XAPIC_OFF_LVT_LINT1:
4426 case XAPIC_OFF_LVT_ERROR:
4427 case XAPIC_OFF_TIMER_ICR:
4428 case XAPIC_OFF_TIMER_DCR:
4429 break;
4430 default:
4431 return true;
4432 }
4433 }
4434 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4435 {
4436 /*
4437 * With virtual-interrupt delivery, a write access to any of the
4438 * following registers are virtualized. Accessing any other register
4439 * causes a VM-exit.
4440 *
4441 * Note! The specification does not allow writing to offsets in-between
4442 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4443 */
4444 switch (offAccess)
4445 {
4446 case XAPIC_OFF_TPR:
4447 case XAPIC_OFF_EOI:
4448 case XAPIC_OFF_ICR_LO:
4449 break;
4450 default:
4451 return true;
4452 }
4453 }
4454 else
4455 {
4456 /*
4457 * Without APIC-register virtualization or virtual-interrupt delivery,
4458 * only TPR accesses are virtualized.
4459 */
4460 if (offAccess == XAPIC_OFF_TPR)
4461 { /* likely */ }
4462 else
4463 return true;
4464 }
4465 }
4466 else
4467 {
4468 /*
4469 * Check read accesses to the APIC-access page that cause VM-exits.
4470 */
4471 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4472 {
4473 /*
4474 * With APIC-register virtualization, a read access to any of the
4475 * following registers are virtualized. Accessing any other register
4476 * causes a VM-exit.
4477 */
4478 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4479 switch (offAlignedAccess)
4480 {
4481 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4482 case XAPIC_OFF_ID:
4483 case XAPIC_OFF_VERSION:
4484 case XAPIC_OFF_TPR:
4485 case XAPIC_OFF_EOI:
4486 case XAPIC_OFF_LDR:
4487 case XAPIC_OFF_DFR:
4488 case XAPIC_OFF_SVR:
4489 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4490 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4491 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4492 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4493 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4494 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4495 case XAPIC_OFF_ESR:
4496 case XAPIC_OFF_ICR_LO:
4497 case XAPIC_OFF_ICR_HI:
4498 case XAPIC_OFF_LVT_TIMER:
4499 case XAPIC_OFF_LVT_THERMAL:
4500 case XAPIC_OFF_LVT_PERF:
4501 case XAPIC_OFF_LVT_LINT0:
4502 case XAPIC_OFF_LVT_LINT1:
4503 case XAPIC_OFF_LVT_ERROR:
4504 case XAPIC_OFF_TIMER_ICR:
4505 case XAPIC_OFF_TIMER_DCR:
4506 break;
4507 default:
4508 return true;
4509 }
4510 }
4511 else
4512 {
4513 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4514 if (offAccess == XAPIC_OFF_TPR)
4515 { /* likely */ }
4516 else
4517 return true;
4518 }
4519 }
4520
4521 /* The APIC access is virtualized, does not cause a VM-exit. */
4522 return false;
4523}
4524
4525
4526/**
4527 * Virtualizes a memory-based APIC access where the address is not used to access
4528 * memory.
4529 *
4530 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4531 * page-faults but do not use the address to access memory.
4532 *
4533 * @param pVCpu The cross context virtual CPU structure.
4534 * @param pGCPhysAccess Pointer to the guest-physical address used.
4535 */
4536IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4537{
4538 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4539 Assert(pVmcs);
4540 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4541 Assert(pGCPhysAccess);
4542
4543 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4544 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4545 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4546
4547 if (GCPhysAccess == GCPhysApic)
4548 {
4549 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4550 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4551 uint16_t const cbAccess = 1;
4552 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4553 if (fIntercept)
4554 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4555
4556 *pGCPhysAccess = GCPhysApic | offAccess;
4557 return VINF_VMX_MODIFIES_BEHAVIOR;
4558 }
4559
4560 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4561}
4562
4563
4564/**
4565 * Virtualizes a memory-based APIC access.
4566 *
4567 * @returns VBox strict status code.
4568 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4569 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4570 *
4571 * @param pVCpu The cross context virtual CPU structure.
4572 * @param offAccess The offset of the register being accessed (within the
4573 * APIC-access page).
4574 * @param cbAccess The size of the access in bytes.
4575 * @param pvData Pointer to the data being written or where to store the data
4576 * being read.
4577 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4578 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4579 */
4580IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4581 uint32_t fAccess)
4582{
4583 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4584 Assert(pVmcs);
4585 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4586 Assert(pvData);
4587 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4588 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4589 || (fAccess & IEM_ACCESS_INSTRUCTION));
4590
4591 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4592 if (fIntercept)
4593 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4594
4595 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4596 {
4597 /*
4598 * A write access to the APIC-access page that is virtualized (rather than
4599 * causing a VM-exit) writes data to the virtual-APIC page.
4600 */
4601 uint32_t const u32Data = *(uint32_t *)pvData;
4602 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4603
4604 /*
4605 * Record the currently updated APIC offset, as we need this later for figuring
4606 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4607 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4608 *
4609 * After completion of the current operation, we need to perform TPR virtualization,
4610 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4611 *
4612 * The current operation may be a REP-prefixed string instruction, execution of any
4613 * other instruction, or delivery of an event through the IDT.
4614 *
4615 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4616 * performed now but later after completion of the current operation.
4617 *
4618 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4619 */
4620 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4621 }
4622 else
4623 {
4624 /*
4625 * A read access from the APIC-access page that is virtualized (rather than
4626 * causing a VM-exit) returns data from the virtual-APIC page.
4627 *
4628 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4629 */
4630 Assert(cbAccess <= 4);
4631 Assert(offAccess < XAPIC_OFF_END + 4);
4632 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4633
4634 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4635 u32Data &= s_auAccessSizeMasks[cbAccess];
4636 *(uint32_t *)pvData = u32Data;
4637 }
4638
4639 return VINF_VMX_MODIFIES_BEHAVIOR;
4640}
4641
4642
4643/**
4644 * Virtualizes an MSR-based APIC read access.
4645 *
4646 * @returns VBox strict status code.
4647 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4648 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4649 * handled by the x2APIC device.
4650 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4651 * not within the range of valid MSRs, caller must raise \#GP(0).
4652 * @param pVCpu The cross context virtual CPU structure.
4653 * @param idMsr The x2APIC MSR being read.
4654 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4655 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4656 */
4657IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4658{
4659 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4660 Assert(pVmcs);
4661 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4662 Assert(pu64Value);
4663
4664 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4665 {
4666 /*
4667 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4668 * what the end of the valid x2APIC MSR range is. Hence the use of different
4669 * macros here.
4670 *
4671 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4672 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4673 */
4674 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4675 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4676 {
4677 uint16_t const offReg = (idMsr & 0xff) << 4;
4678 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4679 *pu64Value = u64Value;
4680 return VINF_VMX_MODIFIES_BEHAVIOR;
4681 }
4682 return VERR_OUT_OF_RANGE;
4683 }
4684
4685 if (idMsr == MSR_IA32_X2APIC_TPR)
4686 {
4687 uint16_t const offReg = (idMsr & 0xff) << 4;
4688 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4689 *pu64Value = u64Value;
4690 return VINF_VMX_MODIFIES_BEHAVIOR;
4691 }
4692
4693 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4694}
4695
4696
4697/**
4698 * Virtualizes an MSR-based APIC write access.
4699 *
4700 * @returns VBox strict status code.
4701 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4702 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4703 * not within the range of valid MSRs, caller must raise \#GP(0).
4704 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4705 *
4706 * @param pVCpu The cross context virtual CPU structure.
4707 * @param idMsr The x2APIC MSR being written.
4708 * @param u64Value The value of the x2APIC MSR being written.
4709 */
4710IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4711{
4712 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4713 Assert(pVmcs);
4714
4715 /*
4716 * Check if the access is to be virtualized.
4717 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4718 */
4719 if ( idMsr == MSR_IA32_X2APIC_TPR
4720 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4721 && ( idMsr == MSR_IA32_X2APIC_EOI
4722 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4723 {
4724 /* Validate the MSR write depending on the register. */
4725 switch (idMsr)
4726 {
4727 case MSR_IA32_X2APIC_TPR:
4728 case MSR_IA32_X2APIC_SELF_IPI:
4729 {
4730 if (u64Value & UINT64_C(0xffffffffffffff00))
4731 return VERR_OUT_OF_RANGE;
4732 break;
4733 }
4734 case MSR_IA32_X2APIC_EOI:
4735 {
4736 if (u64Value != 0)
4737 return VERR_OUT_OF_RANGE;
4738 break;
4739 }
4740 }
4741
4742 /* Write the MSR to the virtual-APIC page. */
4743 uint16_t const offReg = (idMsr & 0xff) << 4;
4744 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4745
4746 /*
4747 * Record the currently updated APIC offset, as we need this later for figuring
4748 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4749 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4750 */
4751 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4752
4753 return VINF_VMX_MODIFIES_BEHAVIOR;
4754 }
4755
4756 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4757}
4758
4759
4760/**
4761 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4762 *
4763 * @returns VBox status code.
4764 * @retval VINF_SUCCESS when the highest set bit is found.
4765 * @retval VERR_NOT_FOUND when no bit is set.
4766 *
4767 * @param pVCpu The cross context virtual CPU structure.
4768 * @param offReg The offset of the APIC 256-bit sparse register.
4769 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4770 * set in the register. Only valid when VINF_SUCCESS is
4771 * returned.
4772 *
4773 * @remarks The format of the 256-bit sparse register here mirrors that found in
4774 * real APIC hardware.
4775 */
4776static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4777{
4778 Assert(offReg < XAPIC_OFF_END + 4);
4779 Assert(pidxHighestBit);
4780 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4781
4782 /*
4783 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4784 * However, in each fragment only the first 4 bytes are used.
4785 */
4786 uint8_t const cFrags = 8;
4787 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4788 {
4789 uint16_t const offFrag = iFrag * 16;
4790 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4791 if (!u32Frag)
4792 continue;
4793
4794 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4795 Assert(idxHighestBit > 0);
4796 --idxHighestBit;
4797 Assert(idxHighestBit <= UINT8_MAX);
4798 *pidxHighestBit = idxHighestBit;
4799 return VINF_SUCCESS;
4800 }
4801 return VERR_NOT_FOUND;
4802}
4803
4804
4805/**
4806 * Evaluates pending virtual interrupts.
4807 *
4808 * @param pVCpu The cross context virtual CPU structure.
4809 */
4810IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4811{
4812 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4813 Assert(pVmcs);
4814 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4815
4816 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4817 {
4818 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4819 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4820
4821 if ((uRvi >> 4) > (uPpr >> 4))
4822 {
4823 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4824 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4825 }
4826 else
4827 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4828 }
4829}
4830
4831
4832/**
4833 * Performs PPR virtualization.
4834 *
4835 * @returns VBox strict status code.
4836 * @param pVCpu The cross context virtual CPU structure.
4837 */
4838IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4839{
4840 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4841 Assert(pVmcs);
4842 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4843 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4844
4845 /*
4846 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4847 * or EOI-virtualization.
4848 *
4849 * See Intel spec. 29.1.3 "PPR Virtualization".
4850 */
4851 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4852 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4853
4854 uint32_t uPpr;
4855 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4856 uPpr = uTpr & 0xff;
4857 else
4858 uPpr = uSvi & 0xf0;
4859
4860 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4861 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4862}
4863
4864
4865/**
4866 * Performs VMX TPR virtualization.
4867 *
4868 * @returns VBox strict status code.
4869 * @param pVCpu The cross context virtual CPU structure.
4870 */
4871IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4872{
4873 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4874 Assert(pVmcs);
4875 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4876
4877 /*
4878 * We should have already performed the virtual-APIC write to the TPR offset
4879 * in the virtual-APIC page. We now perform TPR virtualization.
4880 *
4881 * See Intel spec. 29.1.2 "TPR Virtualization".
4882 */
4883 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4884 {
4885 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4886 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4887
4888 /*
4889 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4890 * See Intel spec. 29.1.2 "TPR Virtualization".
4891 */
4892 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4893 {
4894 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4895 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4896 }
4897 }
4898 else
4899 {
4900 iemVmxPprVirtualization(pVCpu);
4901 iemVmxEvalPendingVirtIntrs(pVCpu);
4902 }
4903
4904 return VINF_SUCCESS;
4905}
4906
4907
4908/**
4909 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4910 * not.
4911 *
4912 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4913 * @param pVCpu The cross context virtual CPU structure.
4914 * @param uVector The interrupt that was acknowledged using an EOI.
4915 */
4916IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4917{
4918 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4919 Assert(pVmcs);
4920 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4921
4922 if (uVector < 64)
4923 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4924 if (uVector < 128)
4925 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4926 if (uVector < 192)
4927 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4928 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4929}
4930
4931
4932/**
4933 * Performs EOI virtualization.
4934 *
4935 * @returns VBox strict status code.
4936 * @param pVCpu The cross context virtual CPU structure.
4937 */
4938IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4939{
4940 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4941 Assert(pVmcs);
4942 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4943
4944 /*
4945 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4946 * and get the next guest-interrupt that's in-service (if any).
4947 *
4948 * See Intel spec. 29.1.4 "EOI Virtualization".
4949 */
4950 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4951 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4952 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4953
4954 uint8_t uVector = uSvi;
4955 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4956
4957 uVector = 0;
4958 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4959
4960 if (uVector)
4961 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4962 else
4963 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4964
4965 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4966 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4967
4968 iemVmxPprVirtualization(pVCpu);
4969 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4970 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4971 iemVmxEvalPendingVirtIntrs(pVCpu);
4972 return VINF_SUCCESS;
4973}
4974
4975
4976/**
4977 * Performs self-IPI virtualization.
4978 *
4979 * @returns VBox strict status code.
4980 * @param pVCpu The cross context virtual CPU structure.
4981 */
4982IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4983{
4984 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4985 Assert(pVmcs);
4986 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4987
4988 /*
4989 * We should have already performed the virtual-APIC write to the self-IPI offset
4990 * in the virtual-APIC page. We now perform self-IPI virtualization.
4991 *
4992 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4993 */
4994 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4995 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4996 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4997 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4998 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4999 if (uVector > uRvi)
5000 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5001 iemVmxEvalPendingVirtIntrs(pVCpu);
5002 return VINF_SUCCESS;
5003}
5004
5005
5006/**
5007 * Performs VMX APIC-write emulation.
5008 *
5009 * @returns VBox strict status code.
5010 * @param pVCpu The cross context virtual CPU structure.
5011 */
5012IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5013{
5014 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5015 Assert(pVmcs);
5016
5017 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5018 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5019
5020 /*
5021 * Perform APIC-write emulation based on the virtual-APIC register written.
5022 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5023 */
5024 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5025 VBOXSTRICTRC rcStrict;
5026 switch (offApicWrite)
5027 {
5028 case XAPIC_OFF_TPR:
5029 {
5030 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5031 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5032 uTpr &= UINT32_C(0x000000ff);
5033 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5034 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5035 rcStrict = iemVmxTprVirtualization(pVCpu);
5036 break;
5037 }
5038
5039 case XAPIC_OFF_EOI:
5040 {
5041 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5042 {
5043 /* Clear VEOI and perform EOI virtualization. */
5044 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5045 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5046 rcStrict = iemVmxEoiVirtualization(pVCpu);
5047 }
5048 else
5049 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5050 break;
5051 }
5052
5053 case XAPIC_OFF_ICR_LO:
5054 {
5055 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5056 {
5057 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5058 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5059 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5060 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5061 if ( !(uIcrLo & fIcrLoMb0)
5062 && (uIcrLo & fIcrLoMb1))
5063 {
5064 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5065 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5066 }
5067 else
5068 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5069 }
5070 else
5071 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5072 break;
5073 }
5074
5075 case XAPIC_OFF_ICR_HI:
5076 {
5077 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5078 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5079 uIcrHi &= UINT32_C(0xff000000);
5080 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5081 rcStrict = VINF_SUCCESS;
5082 break;
5083 }
5084
5085 default:
5086 {
5087 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5088 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5089 break;
5090 }
5091 }
5092
5093 return rcStrict;
5094}
5095
5096
5097/**
5098 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5099 *
5100 * @param pVCpu The cross context virtual CPU structure.
5101 * @param pszInstr The VMX instruction name (for logging purposes).
5102 */
5103IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5104{
5105 /*
5106 * Guest Control Registers, Debug Registers, and MSRs.
5107 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5108 */
5109 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5110 const char *const pszFailure = "VM-exit";
5111 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5112
5113 /* CR0 reserved bits. */
5114 {
5115 /* CR0 MB1 bits. */
5116 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5117 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5118 if (fUnrestrictedGuest)
5119 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5120 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5121 { /* likely */ }
5122 else
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5124
5125 /* CR0 MBZ bits. */
5126 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5127 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5131
5132 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5133 if ( !fUnrestrictedGuest
5134 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5135 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5137 }
5138
5139 /* CR4 reserved bits. */
5140 {
5141 /* CR4 MB1 bits. */
5142 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5143 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5144 { /* likely */ }
5145 else
5146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5147
5148 /* CR4 MBZ bits. */
5149 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5150 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5151 { /* likely */ }
5152 else
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5154 }
5155
5156 /* DEBUGCTL MSR. */
5157 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5158 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5159 { /* likely */ }
5160 else
5161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5162
5163 /* 64-bit CPU checks. */
5164 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5165 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5166 {
5167 if (fGstInLongMode)
5168 {
5169 /* PAE must be set. */
5170 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5171 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5172 { /* likely */ }
5173 else
5174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5175 }
5176 else
5177 {
5178 /* PCIDE should not be set. */
5179 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5180 { /* likely */ }
5181 else
5182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5183 }
5184
5185 /* CR3. */
5186 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5190
5191 /* DR7. */
5192 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5193 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5194 { /* likely */ }
5195 else
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5197
5198 /* SYSENTER ESP and SYSENTER EIP. */
5199 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5200 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5201 { /* likely */ }
5202 else
5203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5204 }
5205
5206 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5207 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5208
5209 /* PAT MSR. */
5210 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5211 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5215
5216 /* EFER MSR. */
5217 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5218 {
5219 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5220 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5221 { /* likely */ }
5222 else
5223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5224
5225 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5226 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5227 if ( fGstLma == fGstInLongMode
5228 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5229 || fGstLma == fGstLme))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5233 }
5234
5235 /* We don't support IA32_BNDCFGS MSR yet. */
5236 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5237
5238 NOREF(pszInstr);
5239 NOREF(pszFailure);
5240 return VINF_SUCCESS;
5241}
5242
5243
5244/**
5245 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5246 *
5247 * @param pVCpu The cross context virtual CPU structure.
5248 * @param pszInstr The VMX instruction name (for logging purposes).
5249 */
5250IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5251{
5252 /*
5253 * Segment registers.
5254 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5255 */
5256 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5257 const char *const pszFailure = "VM-exit";
5258 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5259 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5260 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5261
5262 /* Selectors. */
5263 if ( !fGstInV86Mode
5264 && !fUnrestrictedGuest
5265 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5267
5268 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5269 {
5270 CPUMSELREG SelReg;
5271 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5272 if (RT_LIKELY(rc == VINF_SUCCESS))
5273 { /* likely */ }
5274 else
5275 return rc;
5276
5277 /*
5278 * Virtual-8086 mode checks.
5279 */
5280 if (fGstInV86Mode)
5281 {
5282 /* Base address. */
5283 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5284 { /* likely */ }
5285 else
5286 {
5287 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5289 }
5290
5291 /* Limit. */
5292 if (SelReg.u32Limit == 0xffff)
5293 { /* likely */ }
5294 else
5295 {
5296 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5298 }
5299
5300 /* Attribute. */
5301 if (SelReg.Attr.u == 0xf3)
5302 { /* likely */ }
5303 else
5304 {
5305 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5307 }
5308
5309 /* We're done; move to checking the next segment. */
5310 continue;
5311 }
5312
5313 /* Checks done by 64-bit CPUs. */
5314 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5315 {
5316 /* Base address. */
5317 if ( iSegReg == X86_SREG_FS
5318 || iSegReg == X86_SREG_GS)
5319 {
5320 if (X86_IS_CANONICAL(SelReg.u64Base))
5321 { /* likely */ }
5322 else
5323 {
5324 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5326 }
5327 }
5328 else if (iSegReg == X86_SREG_CS)
5329 {
5330 if (!RT_HI_U32(SelReg.u64Base))
5331 { /* likely */ }
5332 else
5333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5334 }
5335 else
5336 {
5337 if ( SelReg.Attr.n.u1Unusable
5338 || !RT_HI_U32(SelReg.u64Base))
5339 { /* likely */ }
5340 else
5341 {
5342 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5344 }
5345 }
5346 }
5347
5348 /*
5349 * Checks outside Virtual-8086 mode.
5350 */
5351 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5352 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5353 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5354 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5355 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5356 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5357 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5358 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5359
5360 /* Code or usable segment. */
5361 if ( iSegReg == X86_SREG_CS
5362 || fUsable)
5363 {
5364 /* Reserved bits (bits 31:17 and bits 11:8). */
5365 if (!(SelReg.Attr.u & 0xfffe0f00))
5366 { /* likely */ }
5367 else
5368 {
5369 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5371 }
5372
5373 /* Descriptor type. */
5374 if (fCodeDataSeg)
5375 { /* likely */ }
5376 else
5377 {
5378 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5380 }
5381
5382 /* Present. */
5383 if (fPresent)
5384 { /* likely */ }
5385 else
5386 {
5387 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5389 }
5390
5391 /* Granularity. */
5392 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5393 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5394 { /* likely */ }
5395 else
5396 {
5397 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5399 }
5400 }
5401
5402 if (iSegReg == X86_SREG_CS)
5403 {
5404 /* Segment Type and DPL. */
5405 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5406 && fUnrestrictedGuest)
5407 {
5408 if (uDpl == 0)
5409 { /* likely */ }
5410 else
5411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5412 }
5413 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5414 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5415 {
5416 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5417 if (uDpl == AttrSs.n.u2Dpl)
5418 { /* likely */ }
5419 else
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5421 }
5422 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5423 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5424 {
5425 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5426 if (uDpl <= AttrSs.n.u2Dpl)
5427 { /* likely */ }
5428 else
5429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5430 }
5431 else
5432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5433
5434 /* Def/Big. */
5435 if ( fGstInLongMode
5436 && fSegLong)
5437 {
5438 if (uDefBig == 0)
5439 { /* likely */ }
5440 else
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5442 }
5443 }
5444 else if (iSegReg == X86_SREG_SS)
5445 {
5446 /* Segment Type. */
5447 if ( !fUsable
5448 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5449 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5450 { /* likely */ }
5451 else
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5453
5454 /* DPL. */
5455 if (!fUnrestrictedGuest)
5456 {
5457 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5458 { /* likely */ }
5459 else
5460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5461 }
5462 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5463 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5464 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5465 {
5466 if (uDpl == 0)
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5470 }
5471 }
5472 else
5473 {
5474 /* DS, ES, FS, GS. */
5475 if (fUsable)
5476 {
5477 /* Segment type. */
5478 if (uSegType & X86_SEL_TYPE_ACCESSED)
5479 { /* likely */ }
5480 else
5481 {
5482 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5484 }
5485
5486 if ( !(uSegType & X86_SEL_TYPE_CODE)
5487 || (uSegType & X86_SEL_TYPE_READ))
5488 { /* likely */ }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5491
5492 /* DPL. */
5493 if ( !fUnrestrictedGuest
5494 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5495 {
5496 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5497 { /* likely */ }
5498 else
5499 {
5500 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5502 }
5503 }
5504 }
5505 }
5506 }
5507
5508 /*
5509 * LDTR.
5510 */
5511 {
5512 CPUMSELREG Ldtr;
5513 Ldtr.Sel = pVmcs->GuestLdtr;
5514 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5515 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5516 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5517
5518 if (!Ldtr.Attr.n.u1Unusable)
5519 {
5520 /* Selector. */
5521 if (!(Ldtr.Sel & X86_SEL_LDT))
5522 { /* likely */ }
5523 else
5524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5525
5526 /* Base. */
5527 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5528 {
5529 if (X86_IS_CANONICAL(Ldtr.u64Base))
5530 { /* likely */ }
5531 else
5532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5533 }
5534
5535 /* Attributes. */
5536 /* Reserved bits (bits 31:17 and bits 11:8). */
5537 if (!(Ldtr.Attr.u & 0xfffe0f00))
5538 { /* likely */ }
5539 else
5540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5541
5542 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5543 { /* likely */ }
5544 else
5545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5546
5547 if (!Ldtr.Attr.n.u1DescType)
5548 { /* likely */ }
5549 else
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5551
5552 if (Ldtr.Attr.n.u1Present)
5553 { /* likely */ }
5554 else
5555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5556
5557 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5558 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5562 }
5563 }
5564
5565 /*
5566 * TR.
5567 */
5568 {
5569 CPUMSELREG Tr;
5570 Tr.Sel = pVmcs->GuestTr;
5571 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5572 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5573 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5574
5575 /* Selector. */
5576 if (!(Tr.Sel & X86_SEL_LDT))
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5580
5581 /* Base. */
5582 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5583 {
5584 if (X86_IS_CANONICAL(Tr.u64Base))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5588 }
5589
5590 /* Attributes. */
5591 /* Reserved bits (bits 31:17 and bits 11:8). */
5592 if (!(Tr.Attr.u & 0xfffe0f00))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5596
5597 if (!Tr.Attr.n.u1Unusable)
5598 { /* likely */ }
5599 else
5600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5601
5602 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5603 || ( !fGstInLongMode
5604 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5605 { /* likely */ }
5606 else
5607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5608
5609 if (!Tr.Attr.n.u1DescType)
5610 { /* likely */ }
5611 else
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5613
5614 if (Tr.Attr.n.u1Present)
5615 { /* likely */ }
5616 else
5617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5618
5619 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5620 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5624 }
5625
5626 NOREF(pszInstr);
5627 NOREF(pszFailure);
5628 return VINF_SUCCESS;
5629}
5630
5631
5632/**
5633 * Checks guest GDTR and IDTR as part of VM-entry.
5634 *
5635 * @param pVCpu The cross context virtual CPU structure.
5636 * @param pszInstr The VMX instruction name (for logging purposes).
5637 */
5638IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5639{
5640 /*
5641 * GDTR and IDTR.
5642 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5643 */
5644 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5645 const char *const pszFailure = "VM-exit";
5646
5647 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5648 {
5649 /* Base. */
5650 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5651 { /* likely */ }
5652 else
5653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5654
5655 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5656 { /* likely */ }
5657 else
5658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5659 }
5660
5661 /* Limit. */
5662 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5663 { /* likely */ }
5664 else
5665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5666
5667 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5668 { /* likely */ }
5669 else
5670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5671
5672 NOREF(pszInstr);
5673 NOREF(pszFailure);
5674 return VINF_SUCCESS;
5675}
5676
5677
5678/**
5679 * Checks guest RIP and RFLAGS as part of VM-entry.
5680 *
5681 * @param pVCpu The cross context virtual CPU structure.
5682 * @param pszInstr The VMX instruction name (for logging purposes).
5683 */
5684IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5685{
5686 /*
5687 * RIP and RFLAGS.
5688 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5689 */
5690 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5691 const char *const pszFailure = "VM-exit";
5692 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5693
5694 /* RIP. */
5695 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5696 {
5697 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5698 if ( !fGstInLongMode
5699 || !AttrCs.n.u1Long)
5700 {
5701 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5702 { /* likely */ }
5703 else
5704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5705 }
5706
5707 if ( fGstInLongMode
5708 && AttrCs.n.u1Long)
5709 {
5710 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5711 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5712 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5713 { /* likely */ }
5714 else
5715 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5716 }
5717 }
5718
5719 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5720 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5721 : pVmcs->u64GuestRFlags.s.Lo;
5722 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5723 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5724 { /* likely */ }
5725 else
5726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5727
5728 if ( fGstInLongMode
5729 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5730 {
5731 if (!(uGuestRFlags & X86_EFL_VM))
5732 { /* likely */ }
5733 else
5734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5735 }
5736
5737 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5738 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5739 {
5740 if (uGuestRFlags & X86_EFL_IF)
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5744 }
5745
5746 NOREF(pszInstr);
5747 NOREF(pszFailure);
5748 return VINF_SUCCESS;
5749}
5750
5751
5752/**
5753 * Checks guest non-register state as part of VM-entry.
5754 *
5755 * @param pVCpu The cross context virtual CPU structure.
5756 * @param pszInstr The VMX instruction name (for logging purposes).
5757 */
5758IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5759{
5760 /*
5761 * Guest non-register state.
5762 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5763 */
5764 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5765 const char *const pszFailure = "VM-exit";
5766
5767 /*
5768 * Activity state.
5769 */
5770 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5771 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5772 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5773 { /* likely */ }
5774 else
5775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5776
5777 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5778 if ( !AttrSs.n.u2Dpl
5779 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5780 { /* likely */ }
5781 else
5782 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5783
5784 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5785 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5786 {
5787 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5788 { /* likely */ }
5789 else
5790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5791 }
5792
5793 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5794 {
5795 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5796 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5797 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5798 switch (pVmcs->u32GuestActivityState)
5799 {
5800 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5801 {
5802 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5803 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5804 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5805 && ( uVector == X86_XCPT_DB
5806 || uVector == X86_XCPT_MC))
5807 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5808 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5812 break;
5813 }
5814
5815 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5816 {
5817 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5818 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5819 && uVector == X86_XCPT_MC))
5820 { /* likely */ }
5821 else
5822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5823 break;
5824 }
5825
5826 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5827 default:
5828 break;
5829 }
5830 }
5831
5832 /*
5833 * Interruptibility state.
5834 */
5835 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5836 { /* likely */ }
5837 else
5838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5839
5840 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5841 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5845
5846 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5847 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5851
5852 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5853 {
5854 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5855 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5856 {
5857 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5858 { /* likely */ }
5859 else
5860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5861 }
5862 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5863 {
5864 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5865 { /* likely */ }
5866 else
5867 {
5868 /*
5869 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5870 * We update the Exit qualification only when blocking-by-STI is set
5871 * without blocking-by-MovSS being set. Although in practise it does not
5872 * make much difference since the order of checks are implementation defined.
5873 */
5874 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5875 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5877 }
5878
5879 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5880 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5881 { /* likely */ }
5882 else
5883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5884 }
5885 }
5886
5887 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5888 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5889 { /* likely */ }
5890 else
5891 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5892
5893 /* We don't support SGX yet. So enclave-interruption must not be set. */
5894 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5895 { /* likely */ }
5896 else
5897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5898
5899 /*
5900 * Pending debug exceptions.
5901 */
5902 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5903 ? pVmcs->u64GuestPendingDbgXcpt.u
5904 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5905 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5909
5910 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5911 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5912 {
5913 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5914 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5915 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5917
5918 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5919 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5920 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5921 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5922 }
5923
5924 /* We don't support RTM (Real-time Transactional Memory) yet. */
5925 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5926 { /* likely */ }
5927 else
5928 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5929
5930 /*
5931 * VMCS link pointer.
5932 */
5933 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5934 {
5935 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5936 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5937 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5938 { /* likely */ }
5939 else
5940 {
5941 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5943 }
5944
5945 /* Validate the address. */
5946 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5947 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5948 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5949 { /* likely */ }
5950 else
5951 {
5952 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5953 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5954 }
5955
5956 /* Read the VMCS-link pointer from guest memory. */
5957 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5958 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5959 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5960 if (RT_SUCCESS(rc))
5961 { /* likely */ }
5962 else
5963 {
5964 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5966 }
5967
5968 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5969 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5970 { /* likely */ }
5971 else
5972 {
5973 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5975 }
5976
5977 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5978 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5979 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5980 { /* likely */ }
5981 else
5982 {
5983 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5984 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5985 }
5986
5987 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5988 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5989 }
5990
5991 NOREF(pszInstr);
5992 NOREF(pszFailure);
5993 return VINF_SUCCESS;
5994}
5995
5996
5997/**
5998 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5999 * VM-entry.
6000 *
6001 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6002 * @param pVCpu The cross context virtual CPU structure.
6003 * @param pszInstr The VMX instruction name (for logging purposes).
6004 * @param pVmcs Pointer to the virtual VMCS.
6005 */
6006IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6007{
6008 /*
6009 * Check PDPTEs.
6010 * See Intel spec. 4.4.1 "PDPTE Registers".
6011 */
6012 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6013 const char *const pszFailure = "VM-exit";
6014
6015 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6016 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6017 if (RT_SUCCESS(rc))
6018 {
6019 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6020 {
6021 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6022 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6023 { /* likely */ }
6024 else
6025 {
6026 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6027 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6029 }
6030 }
6031 }
6032 else
6033 {
6034 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6036 }
6037
6038 NOREF(pszFailure);
6039 NOREF(pszInstr);
6040 return rc;
6041}
6042
6043
6044/**
6045 * Checks guest PDPTEs as part of VM-entry.
6046 *
6047 * @param pVCpu The cross context virtual CPU structure.
6048 * @param pszInstr The VMX instruction name (for logging purposes).
6049 */
6050IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6051{
6052 /*
6053 * Guest PDPTEs.
6054 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6055 */
6056 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6057 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6058
6059 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6060 int rc;
6061 if ( !fGstInLongMode
6062 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6063 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6064 {
6065 /*
6066 * We don't support nested-paging for nested-guests yet.
6067 *
6068 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6069 * rather we need to check the PDPTEs referenced by the guest CR3.
6070 */
6071 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6072 }
6073 else
6074 rc = VINF_SUCCESS;
6075 return rc;
6076}
6077
6078
6079/**
6080 * Checks guest-state as part of VM-entry.
6081 *
6082 * @returns VBox status code.
6083 * @param pVCpu The cross context virtual CPU structure.
6084 * @param pszInstr The VMX instruction name (for logging purposes).
6085 */
6086IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6087{
6088 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6089 if (RT_SUCCESS(rc))
6090 {
6091 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6092 if (RT_SUCCESS(rc))
6093 {
6094 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6095 if (RT_SUCCESS(rc))
6096 {
6097 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6098 if (RT_SUCCESS(rc))
6099 {
6100 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6101 if (RT_SUCCESS(rc))
6102 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6103 }
6104 }
6105 }
6106 }
6107 return rc;
6108}
6109
6110
6111/**
6112 * Checks host-state as part of VM-entry.
6113 *
6114 * @returns VBox status code.
6115 * @param pVCpu The cross context virtual CPU structure.
6116 * @param pszInstr The VMX instruction name (for logging purposes).
6117 */
6118IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6119{
6120 /*
6121 * Host Control Registers and MSRs.
6122 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6123 */
6124 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6125 const char * const pszFailure = "VMFail";
6126
6127 /* CR0 reserved bits. */
6128 {
6129 /* CR0 MB1 bits. */
6130 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6131 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6132 { /* likely */ }
6133 else
6134 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6135
6136 /* CR0 MBZ bits. */
6137 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6138 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6142 }
6143
6144 /* CR4 reserved bits. */
6145 {
6146 /* CR4 MB1 bits. */
6147 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6148 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6152
6153 /* CR4 MBZ bits. */
6154 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6155 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6156 { /* likely */ }
6157 else
6158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6159 }
6160
6161 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6162 {
6163 /* CR3 reserved bits. */
6164 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6165 { /* likely */ }
6166 else
6167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6168
6169 /* SYSENTER ESP and SYSENTER EIP. */
6170 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6171 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6172 { /* likely */ }
6173 else
6174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6175 }
6176
6177 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6178 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6179
6180 /* PAT MSR. */
6181 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6182 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6183 { /* likely */ }
6184 else
6185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6186
6187 /* EFER MSR. */
6188 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6189 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6190 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6191 { /* likely */ }
6192 else
6193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6194
6195 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6196 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6197 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6198 if ( fHostInLongMode == fHostLma
6199 && fHostInLongMode == fHostLme)
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6203
6204 /*
6205 * Host Segment and Descriptor-Table Registers.
6206 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6207 */
6208 /* Selector RPL and TI. */
6209 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6210 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6211 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6212 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6213 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6214 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6215 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6219
6220 /* CS and TR selectors cannot be 0. */
6221 if ( pVmcs->HostCs
6222 && pVmcs->HostTr)
6223 { /* likely */ }
6224 else
6225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6226
6227 /* SS cannot be 0 if 32-bit host. */
6228 if ( fHostInLongMode
6229 || pVmcs->HostSs)
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6233
6234 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6235 {
6236 /* FS, GS, GDTR, IDTR, TR base address. */
6237 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6238 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6239 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6240 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6241 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6242 { /* likely */ }
6243 else
6244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6245 }
6246
6247 /*
6248 * Host address-space size for 64-bit CPUs.
6249 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6250 */
6251 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6252 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6253 {
6254 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6255
6256 /* Logical processor in IA-32e mode. */
6257 if (fCpuInLongMode)
6258 {
6259 if (fHostInLongMode)
6260 {
6261 /* PAE must be set. */
6262 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6266
6267 /* RIP must be canonical. */
6268 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6269 { /* likely */ }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6272 }
6273 else
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6275 }
6276 else
6277 {
6278 /* Logical processor is outside IA-32e mode. */
6279 if ( !fGstInLongMode
6280 && !fHostInLongMode)
6281 {
6282 /* PCIDE should not be set. */
6283 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6284 { /* likely */ }
6285 else
6286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6287
6288 /* The high 32-bits of RIP MBZ. */
6289 if (!pVmcs->u64HostRip.s.Hi)
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6293 }
6294 else
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6296 }
6297 }
6298 else
6299 {
6300 /* Host address-space size for 32-bit CPUs. */
6301 if ( !fGstInLongMode
6302 && !fHostInLongMode)
6303 { /* likely */ }
6304 else
6305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6306 }
6307
6308 NOREF(pszInstr);
6309 NOREF(pszFailure);
6310 return VINF_SUCCESS;
6311}
6312
6313
6314/**
6315 * Checks VM-entry controls fields as part of VM-entry.
6316 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6317 *
6318 * @returns VBox status code.
6319 * @param pVCpu The cross context virtual CPU structure.
6320 * @param pszInstr The VMX instruction name (for logging purposes).
6321 */
6322IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6323{
6324 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6325 const char * const pszFailure = "VMFail";
6326
6327 /* VM-entry controls. */
6328 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6329 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6330 { /* likely */ }
6331 else
6332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6333
6334 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6335 { /* likely */ }
6336 else
6337 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6338
6339 /* Event injection. */
6340 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6341 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6342 {
6343 /* Type and vector. */
6344 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6345 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6346 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6347 if ( !uRsvd
6348 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6349 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6353
6354 /* Exception error code. */
6355 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6356 {
6357 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6358 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6359 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6360 { /* likely */ }
6361 else
6362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6363
6364 /* Exceptions that provide an error code. */
6365 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6366 && ( uVector == X86_XCPT_DF
6367 || uVector == X86_XCPT_TS
6368 || uVector == X86_XCPT_NP
6369 || uVector == X86_XCPT_SS
6370 || uVector == X86_XCPT_GP
6371 || uVector == X86_XCPT_PF
6372 || uVector == X86_XCPT_AC))
6373 { /* likely */ }
6374 else
6375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6376
6377 /* Exception error-code reserved bits. */
6378 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6379 { /* likely */ }
6380 else
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6382
6383 /* Injecting a software interrupt, software exception or privileged software exception. */
6384 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6385 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6386 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6387 {
6388 /* Instruction length must be in the range 0-15. */
6389 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6390 { /* likely */ }
6391 else
6392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6393
6394 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6395 if ( pVmcs->u32EntryInstrLen == 0
6396 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6397 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6398 }
6399 }
6400 }
6401
6402 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6403 if (pVmcs->u32EntryMsrLoadCount)
6404 {
6405 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6406 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6407 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6408 { /* likely */ }
6409 else
6410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6411 }
6412
6413 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6414 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6415
6416 NOREF(pszInstr);
6417 NOREF(pszFailure);
6418 return VINF_SUCCESS;
6419}
6420
6421
6422/**
6423 * Checks VM-exit controls fields as part of VM-entry.
6424 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6425 *
6426 * @returns VBox status code.
6427 * @param pVCpu The cross context virtual CPU structure.
6428 * @param pszInstr The VMX instruction name (for logging purposes).
6429 */
6430IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6431{
6432 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6433 const char * const pszFailure = "VMFail";
6434
6435 /* VM-exit controls. */
6436 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6437 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6438 { /* likely */ }
6439 else
6440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6441
6442 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6443 { /* likely */ }
6444 else
6445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6446
6447 /* Save preemption timer without activating it. */
6448 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6449 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6450 { /* likely */ }
6451 else
6452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6453
6454 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6455 if (pVmcs->u32ExitMsrStoreCount)
6456 {
6457 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6458 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6459 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6460 { /* likely */ }
6461 else
6462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6463 }
6464
6465 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6466 if (pVmcs->u32ExitMsrLoadCount)
6467 {
6468 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6469 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6470 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6474 }
6475
6476 NOREF(pszInstr);
6477 NOREF(pszFailure);
6478 return VINF_SUCCESS;
6479}
6480
6481
6482/**
6483 * Checks VM-execution controls fields as part of VM-entry.
6484 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6485 *
6486 * @returns VBox status code.
6487 * @param pVCpu The cross context virtual CPU structure.
6488 * @param pszInstr The VMX instruction name (for logging purposes).
6489 *
6490 * @remarks This may update secondary-processor based VM-execution control fields
6491 * in the current VMCS if necessary.
6492 */
6493IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6494{
6495 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6496 const char * const pszFailure = "VMFail";
6497
6498 /* Pin-based VM-execution controls. */
6499 {
6500 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6501 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6502 { /* likely */ }
6503 else
6504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6505
6506 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6507 { /* likely */ }
6508 else
6509 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6510 }
6511
6512 /* Processor-based VM-execution controls. */
6513 {
6514 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6515 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6516 { /* likely */ }
6517 else
6518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6519
6520 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6521 { /* likely */ }
6522 else
6523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6524 }
6525
6526 /* Secondary processor-based VM-execution controls. */
6527 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6528 {
6529 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6530 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6531 { /* likely */ }
6532 else
6533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6534
6535 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6539 }
6540 else
6541 Assert(!pVmcs->u32ProcCtls2);
6542
6543 /* CR3-target count. */
6544 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6545 { /* likely */ }
6546 else
6547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6548
6549 /* I/O bitmaps physical addresses. */
6550 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6551 {
6552 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6553 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6554 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6555 { /* likely */ }
6556 else
6557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6558
6559 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6560 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6561 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6562 { /* likely */ }
6563 else
6564 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6565 }
6566
6567 /* MSR bitmap physical address. */
6568 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6569 {
6570 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6571 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6572 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6573 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6574 { /* likely */ }
6575 else
6576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6577
6578 /* Read the MSR bitmap. */
6579 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6580 * implementing fast path. */
6581 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6582 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6583 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6584 if (RT_SUCCESS(rc))
6585 { /* likely */ }
6586 else
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6588 }
6589
6590 /* TPR shadow related controls. */
6591 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6592 {
6593 /* Virtual-APIC page physical address. */
6594 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6595 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6596 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6597 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6598 { /* likely */ }
6599 else
6600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6601
6602 /* TPR threshold without virtual-interrupt delivery. */
6603 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6604 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6606
6607 /* TPR threshold and VTPR. */
6608 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6609 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6610 {
6611 /* Read the VTPR from the virtual-APIC page. */
6612 uint8_t u8VTpr;
6613 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6614 if (RT_SUCCESS(rc))
6615 { /* likely */ }
6616 else
6617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6618
6619 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6620 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6621 { /* likely */ }
6622 else
6623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6624 }
6625 }
6626 else
6627 {
6628 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6629 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6630 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6631 { /* likely */ }
6632 else
6633 {
6634 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6636 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6638 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6640 }
6641 }
6642
6643 /* NMI exiting and virtual-NMIs. */
6644 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6645 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6646 { /* likely */ }
6647 else
6648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6649
6650 /* Virtual-NMIs and NMI-window exiting. */
6651 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6652 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6653 { /* likely */ }
6654 else
6655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6656
6657 /* Virtualize APIC accesses. */
6658 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6659 {
6660 /* APIC-access physical address. */
6661 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6662 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6663 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6664 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6665 { /* likely */ }
6666 else
6667 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6668
6669 /*
6670 * Disallow APIC-access page and virtual-APIC page from being the same address.
6671 * Note! This is not an Intel requirement, but one imposed by our implementation.
6672 */
6673 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6674 * redirecting accesses between the APIC-access page and the virtual-APIC
6675 * page. If any guest hypervisor requires this, we can implement it later. */
6676 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6677 {
6678 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6679 if (GCPhysVirtApic != GCPhysApicAccess)
6680 { /* likely */ }
6681 else
6682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6683 }
6684
6685 /*
6686 * Register the handler for the APIC-access page.
6687 *
6688 * We don't deregister the APIC-access page handler during the VM-exit as a different
6689 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6690 *
6691 * We leave the page registered until the first access that happens outside VMX non-root
6692 * mode. Guest software is allowed to access structures such as the APIC-access page
6693 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6694 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6695 *
6696 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6697 */
6698 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6699 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6700 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6701 if (RT_SUCCESS(rc))
6702 { /* likely */ }
6703 else
6704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6705 }
6706
6707 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6708 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6709 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6710 { /* likely */ }
6711 else
6712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6713
6714 /* Virtual-interrupt delivery requires external interrupt exiting. */
6715 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6716 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6717 { /* likely */ }
6718 else
6719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6720
6721 /* VPID. */
6722 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6723 || pVmcs->u16Vpid != 0)
6724 { /* likely */ }
6725 else
6726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6727
6728 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6729 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6730 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6731 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6732 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6733 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6734 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6735
6736 /* VMCS shadowing. */
6737 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6738 {
6739 /* VMREAD-bitmap physical address. */
6740 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6741 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6742 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6743 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6744 { /* likely */ }
6745 else
6746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6747
6748 /* VMWRITE-bitmap physical address. */
6749 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6750 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6751 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6752 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6753 { /* likely */ }
6754 else
6755 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6756
6757 /* Read the VMREAD-bitmap. */
6758 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6759 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6760 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6761 if (RT_SUCCESS(rc))
6762 { /* likely */ }
6763 else
6764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6765
6766 /* Read the VMWRITE-bitmap. */
6767 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6768 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6769 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6770 if (RT_SUCCESS(rc))
6771 { /* likely */ }
6772 else
6773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6774 }
6775
6776 NOREF(pszInstr);
6777 NOREF(pszFailure);
6778 return VINF_SUCCESS;
6779}
6780
6781
6782/**
6783 * Loads the guest control registers, debug register and some MSRs as part of
6784 * VM-entry.
6785 *
6786 * @param pVCpu The cross context virtual CPU structure.
6787 */
6788IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6789{
6790 /*
6791 * Load guest control registers, debug registers and MSRs.
6792 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6793 */
6794 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6795
6796 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6797 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6798 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6799 CPUMSetGuestCR0(pVCpu, uGstCr0);
6800 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6801 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6802
6803 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6804 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6805
6806 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6807 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6808 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6809
6810 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6811 {
6812 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6813
6814 /* EFER MSR. */
6815 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6816 {
6817 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6818 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6819 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6820 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6821 if (fGstInLongMode)
6822 {
6823 /* If the nested-guest is in long mode, LMA and LME are both set. */
6824 Assert(fGstPaging);
6825 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6826 }
6827 else
6828 {
6829 /*
6830 * If the nested-guest is outside long mode:
6831 * - With paging: LMA is cleared, LME is cleared.
6832 * - Without paging: LMA is cleared, LME is left unmodified.
6833 */
6834 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6835 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6836 }
6837 }
6838 /* else: see below. */
6839 }
6840
6841 /* PAT MSR. */
6842 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6843 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6844
6845 /* EFER MSR. */
6846 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6847 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6848
6849 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6850 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6851
6852 /* We don't support IA32_BNDCFGS MSR yet. */
6853 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6854
6855 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6856}
6857
6858
6859/**
6860 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6861 *
6862 * @param pVCpu The cross context virtual CPU structure.
6863 */
6864IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6865{
6866 /*
6867 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6868 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6869 */
6870 /* CS, SS, ES, DS, FS, GS. */
6871 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6872 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6873 {
6874 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6875 CPUMSELREG VmcsSelReg;
6876 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6877 AssertRC(rc); NOREF(rc);
6878 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6879 {
6880 pGstSelReg->Sel = VmcsSelReg.Sel;
6881 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6882 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6883 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6884 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6885 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6886 }
6887 else
6888 {
6889 pGstSelReg->Sel = VmcsSelReg.Sel;
6890 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6891 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6892 switch (iSegReg)
6893 {
6894 case X86_SREG_CS:
6895 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6896 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6897 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6898 break;
6899
6900 case X86_SREG_SS:
6901 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6902 pGstSelReg->u32Limit = 0;
6903 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6904 break;
6905
6906 case X86_SREG_ES:
6907 case X86_SREG_DS:
6908 pGstSelReg->u64Base = 0;
6909 pGstSelReg->u32Limit = 0;
6910 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6911 break;
6912
6913 case X86_SREG_FS:
6914 case X86_SREG_GS:
6915 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6916 pGstSelReg->u32Limit = 0;
6917 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6918 break;
6919 }
6920 Assert(pGstSelReg->Attr.n.u1Unusable);
6921 }
6922 }
6923
6924 /* LDTR. */
6925 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6926 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6927 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6928 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6929 {
6930 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6931 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6932 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6933 }
6934 else
6935 {
6936 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6937 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6938 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6939 }
6940
6941 /* TR. */
6942 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6943 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6944 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6945 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6946 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6947 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6948 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6949
6950 /* GDTR. */
6951 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6952 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6953
6954 /* IDTR. */
6955 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6956 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6957}
6958
6959
6960/**
6961 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6962 *
6963 * @returns VBox status code.
6964 * @param pVCpu The cross context virtual CPU structure.
6965 * @param pszInstr The VMX instruction name (for logging purposes).
6966 */
6967IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6968{
6969 /*
6970 * Load guest MSRs.
6971 * See Intel spec. 26.4 "Loading MSRs".
6972 */
6973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6974 const char *const pszFailure = "VM-exit";
6975
6976 /*
6977 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6978 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6979 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6980 */
6981 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6982 if (!cMsrs)
6983 return VINF_SUCCESS;
6984
6985 /*
6986 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6987 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6988 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6989 */
6990 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6991 if (fIsMsrCountValid)
6992 { /* likely */ }
6993 else
6994 {
6995 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6997 }
6998
6999 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7000 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7001 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7002 if (RT_SUCCESS(rc))
7003 {
7004 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7005 Assert(pMsr);
7006 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7007 {
7008 if ( !pMsr->u32Reserved
7009 && pMsr->u32Msr != MSR_K8_FS_BASE
7010 && pMsr->u32Msr != MSR_K8_GS_BASE
7011 && pMsr->u32Msr != MSR_K6_EFER
7012 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7013 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7014 {
7015 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7016 if (rcStrict == VINF_SUCCESS)
7017 continue;
7018
7019 /*
7020 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7021 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7022 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7023 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7024 * MSR in ring-0 if possible, or come up with a better, generic solution.
7025 */
7026 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7027 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7028 ? kVmxVDiag_Vmentry_MsrLoadRing3
7029 : kVmxVDiag_Vmentry_MsrLoad;
7030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7031 }
7032 else
7033 {
7034 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7036 }
7037 }
7038 }
7039 else
7040 {
7041 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7042 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7043 }
7044
7045 NOREF(pszInstr);
7046 NOREF(pszFailure);
7047 return VINF_SUCCESS;
7048}
7049
7050
7051/**
7052 * Loads the guest-state non-register state as part of VM-entry.
7053 *
7054 * @returns VBox status code.
7055 * @param pVCpu The cross context virtual CPU structure.
7056 *
7057 * @remarks This must be called only after loading the nested-guest register state
7058 * (especially nested-guest RIP).
7059 */
7060IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7061{
7062 /*
7063 * Load guest non-register state.
7064 * See Intel spec. 26.6 "Special Features of VM Entry"
7065 */
7066 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7067
7068 /*
7069 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7070 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7071 *
7072 * See Intel spec. 26.6.1 "Interruptibility State".
7073 */
7074 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7075 if ( !fEntryVectoring
7076 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7077 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7078 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7079 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7080
7081 /* NMI blocking. */
7082 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7083 {
7084 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7085 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7086 else
7087 {
7088 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7089 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7090 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7091 }
7092 }
7093 else
7094 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7095
7096 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7097
7098 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7099 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7100
7101 /* VPID is irrelevant. We don't support VPID yet. */
7102
7103 /* Clear address-range monitoring. */
7104 EMMonitorWaitClear(pVCpu);
7105}
7106
7107
7108/**
7109 * Loads the guest-state as part of VM-entry.
7110 *
7111 * @returns VBox status code.
7112 * @param pVCpu The cross context virtual CPU structure.
7113 * @param pszInstr The VMX instruction name (for logging purposes).
7114 *
7115 * @remarks This must be done after all the necessary steps prior to loading of
7116 * guest-state (e.g. checking various VMCS state).
7117 */
7118IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7119{
7120 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7121 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7122
7123 /*
7124 * Load guest RIP, RSP and RFLAGS.
7125 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7126 */
7127 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7128 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7129 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7130 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7131
7132 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7133 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7134 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7135
7136 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7137
7138 NOREF(pszInstr);
7139 return VINF_SUCCESS;
7140}
7141
7142
7143/**
7144 * Returns whether there are is a pending debug exception on VM-entry.
7145 *
7146 * @param pVCpu The cross context virtual CPU structure.
7147 * @param pszInstr The VMX instruction name (for logging purposes).
7148 */
7149IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7150{
7151 /*
7152 * Pending debug exceptions.
7153 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7154 */
7155 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7156 Assert(pVmcs);
7157
7158 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7159 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7160 if (fPendingDbgXcpt)
7161 {
7162 uint8_t uEntryIntInfoType;
7163 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7164 if (fEntryVectoring)
7165 {
7166 switch (uEntryIntInfoType)
7167 {
7168 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7169 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7170 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7171 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7172 fPendingDbgXcpt = false;
7173 break;
7174
7175 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7176 {
7177 /*
7178 * Whether the pending debug exception for software exceptions other than
7179 * #BP and #OF is delivered after injecting the exception or is discard
7180 * is CPU implementation specific. We will discard them (easier).
7181 */
7182 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7183 if ( uVector != X86_XCPT_BP
7184 && uVector != X86_XCPT_OF)
7185 fPendingDbgXcpt = false;
7186 RT_FALL_THRU();
7187 }
7188 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7189 {
7190 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7191 fPendingDbgXcpt = false;
7192 break;
7193 }
7194 }
7195 }
7196 else
7197 {
7198 /*
7199 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7200 * pending debug exception is held pending or is discarded is CPU implementation
7201 * specific. We will discard them (easier).
7202 */
7203 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7204 fPendingDbgXcpt = false;
7205
7206 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7207 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7208 fPendingDbgXcpt = false;
7209 }
7210 }
7211
7212 NOREF(pszInstr);
7213 return fPendingDbgXcpt;
7214}
7215
7216
7217/**
7218 * Set up the monitor-trap flag (MTF).
7219 *
7220 * @param pVCpu The cross context virtual CPU structure.
7221 * @param pszInstr The VMX instruction name (for logging purposes).
7222 */
7223IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7224{
7225 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7226 Assert(pVmcs);
7227 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7228 {
7229 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7230 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7231 }
7232 else
7233 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7234 NOREF(pszInstr);
7235}
7236
7237
7238/**
7239 * Sets up NMI-window exiting.
7240 *
7241 * @param pVCpu The cross context virtual CPU structure.
7242 * @param pszInstr The VMX instruction name (for logging purposes).
7243 */
7244IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7245{
7246 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7247 Assert(pVmcs);
7248 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7249 {
7250 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7251 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7252 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7253 }
7254 else
7255 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7256 NOREF(pszInstr);
7257}
7258
7259
7260/**
7261 * Sets up interrupt-window exiting.
7262 *
7263 * @param pVCpu The cross context virtual CPU structure.
7264 * @param pszInstr The VMX instruction name (for logging purposes).
7265 */
7266IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7267{
7268 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7269 Assert(pVmcs);
7270 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7271 {
7272 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7273 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7274 }
7275 else
7276 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7277 NOREF(pszInstr);
7278}
7279
7280
7281/**
7282 * Set up the VMX-preemption timer.
7283 *
7284 * @param pVCpu The cross context virtual CPU structure.
7285 * @param pszInstr The VMX instruction name (for logging purposes).
7286 */
7287IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7288{
7289 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7290 Assert(pVmcs);
7291 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7292 {
7293 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7294 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7295 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7296
7297 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7298 }
7299 else
7300 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7301
7302 NOREF(pszInstr);
7303}
7304
7305
7306/**
7307 * Injects an event using TRPM given a VM-entry interruption info. and related
7308 * fields.
7309 *
7310 * @returns VBox status code.
7311 * @param pVCpu The cross context virtual CPU structure.
7312 * @param uEntryIntInfo The VM-entry interruption info.
7313 * @param uErrCode The error code associated with the event if any.
7314 * @param cbInstr The VM-entry instruction length (for software
7315 * interrupts and software exceptions). Pass 0
7316 * otherwise.
7317 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7318 */
7319IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7320 RTGCUINTPTR GCPtrFaultAddress)
7321{
7322 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7323
7324 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7325 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7326 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7327
7328 TRPMEVENT enmTrapType;
7329 switch (uType)
7330 {
7331 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7332 enmTrapType = TRPM_HARDWARE_INT;
7333 break;
7334
7335 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7336 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7337 enmTrapType = TRPM_TRAP;
7338 break;
7339
7340 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7341 enmTrapType = TRPM_SOFTWARE_INT;
7342 break;
7343
7344 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7345 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7346 enmTrapType = TRPM_SOFTWARE_INT;
7347 break;
7348
7349 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7350 Assert(uVector == X86_XCPT_DB);
7351 enmTrapType = TRPM_SOFTWARE_INT;
7352 break;
7353
7354 default:
7355 /* Shouldn't really happen. */
7356 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7357 break;
7358 }
7359
7360 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7361 AssertRCReturn(rc, rc);
7362
7363 if (fErrCodeValid)
7364 TRPMSetErrorCode(pVCpu, uErrCode);
7365
7366 if ( enmTrapType == TRPM_TRAP
7367 && uVector == X86_XCPT_PF)
7368 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7369 else if (enmTrapType == TRPM_SOFTWARE_INT)
7370 TRPMSetInstrLength(pVCpu, cbInstr);
7371
7372 return VINF_SUCCESS;
7373}
7374
7375
7376/**
7377 * Performs event injection (if any) as part of VM-entry.
7378 *
7379 * @param pVCpu The cross context virtual CPU structure.
7380 * @param pszInstr The VMX instruction name (for logging purposes).
7381 */
7382IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7383{
7384 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7385
7386 /*
7387 * Inject events.
7388 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7389 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7390 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7391 * the actually delivery of this event.
7392 *
7393 * See Intel spec. 26.5 "Event Injection".
7394 */
7395 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7396 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7397
7398 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7399 if (fEntryIntInfoValid)
7400 {
7401 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7402 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7403 {
7404 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7405 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7406 return VINF_SUCCESS;
7407 }
7408
7409 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7410 pVCpu->cpum.GstCtx.cr2);
7411 if (RT_SUCCESS(rc))
7412 {
7413 /*
7414 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7415 *
7416 * However, we do it here on VM-entry because while it continues to not be visible to
7417 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7418 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7419 * information field.
7420 *
7421 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7422 */
7423 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7424 }
7425 return rc;
7426 }
7427
7428 /*
7429 * Inject any pending guest debug exception.
7430 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7431 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7432 */
7433 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7434 if (fPendingDbgXcpt)
7435 {
7436 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7437 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7438 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7439 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7440 0 /* GCPtrFaultAddress */);
7441 }
7442
7443 NOREF(pszInstr);
7444 return VINF_SUCCESS;
7445}
7446
7447
7448/**
7449 * Initializes all read-only VMCS fields as part of VM-entry.
7450 *
7451 * @param pVCpu The cross context virtual CPU structure.
7452 */
7453IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7454{
7455 /*
7456 * Any VMCS field which we do not establish on every VM-exit but may potentially
7457 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7458 * specified to be undefined needs to be initialized here.
7459 *
7460 * Thus, it is especially important to clear the Exit qualification field
7461 * since it must be zero for VM-exits where it is not used. Similarly, the
7462 * VM-exit interruption information field's valid bit needs to be cleared for
7463 * the same reasons.
7464 */
7465 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7466 Assert(pVmcs);
7467
7468 /* 16-bit (none currently). */
7469 /* 32-bit. */
7470 pVmcs->u32RoVmInstrError = 0;
7471 pVmcs->u32RoExitReason = 0;
7472 pVmcs->u32RoExitIntInfo = 0;
7473 pVmcs->u32RoExitIntErrCode = 0;
7474 pVmcs->u32RoIdtVectoringInfo = 0;
7475 pVmcs->u32RoIdtVectoringErrCode = 0;
7476 pVmcs->u32RoExitInstrLen = 0;
7477 pVmcs->u32RoExitInstrInfo = 0;
7478
7479 /* 64-bit. */
7480 pVmcs->u64RoGuestPhysAddr.u = 0;
7481
7482 /* Natural-width. */
7483 pVmcs->u64RoExitQual.u = 0;
7484 pVmcs->u64RoIoRcx.u = 0;
7485 pVmcs->u64RoIoRsi.u = 0;
7486 pVmcs->u64RoIoRdi.u = 0;
7487 pVmcs->u64RoIoRip.u = 0;
7488 pVmcs->u64RoGuestLinearAddr.u = 0;
7489}
7490
7491
7492/**
7493 * VMLAUNCH/VMRESUME instruction execution worker.
7494 *
7495 * @returns Strict VBox status code.
7496 * @param pVCpu The cross context virtual CPU structure.
7497 * @param cbInstr The instruction length in bytes.
7498 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7499 * VMXINSTRID_VMRESUME).
7500 *
7501 * @remarks Common VMX instruction checks are already expected to by the caller,
7502 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7503 */
7504IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7505{
7506# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7507 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7508 return VINF_EM_RAW_EMULATE_INSTR;
7509# else
7510 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7511 || uInstrId == VMXINSTRID_VMRESUME);
7512 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7513
7514 /* Nested-guest intercept. */
7515 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7516 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7517
7518 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7519
7520 /*
7521 * Basic VM-entry checks.
7522 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7523 * The checks following that do not have to follow a specific order.
7524 *
7525 * See Intel spec. 26.1 "Basic VM-entry Checks".
7526 */
7527
7528 /* CPL. */
7529 if (pVCpu->iem.s.uCpl == 0)
7530 { /* likely */ }
7531 else
7532 {
7533 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7534 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7535 return iemRaiseGeneralProtectionFault0(pVCpu);
7536 }
7537
7538 /* Current VMCS valid. */
7539 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7540 { /* likely */ }
7541 else
7542 {
7543 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7544 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7545 iemVmxVmFailInvalid(pVCpu);
7546 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7547 return VINF_SUCCESS;
7548 }
7549
7550 /* Current VMCS is not a shadow VMCS. */
7551 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7552 { /* likely */ }
7553 else
7554 {
7555 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7557 iemVmxVmFailInvalid(pVCpu);
7558 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7559 return VINF_SUCCESS;
7560 }
7561
7562 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7563 * use block-by-STI here which is not quite correct. */
7564 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7565 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7566 { /* likely */ }
7567 else
7568 {
7569 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7570 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7571 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7572 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7573 return VINF_SUCCESS;
7574 }
7575
7576 if (uInstrId == VMXINSTRID_VMLAUNCH)
7577 {
7578 /* VMLAUNCH with non-clear VMCS. */
7579 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7580 { /* likely */ }
7581 else
7582 {
7583 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7584 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7585 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7586 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7587 return VINF_SUCCESS;
7588 }
7589 }
7590 else
7591 {
7592 /* VMRESUME with non-launched VMCS. */
7593 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7594 { /* likely */ }
7595 else
7596 {
7597 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7598 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7599 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7600 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7601 return VINF_SUCCESS;
7602 }
7603 }
7604
7605 /*
7606 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7607 * while entering VMX non-root mode. We do some of this while checking VM-execution
7608 * controls. The guest hypervisor should not make assumptions and cannot expect
7609 * predictable behavior if changes to these structures are made in guest memory while
7610 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7611 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7612 *
7613 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7614 */
7615 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7616 Assert(pVmcs);
7617 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7618
7619 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7620 if (RT_SUCCESS(rc))
7621 {
7622 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7623 if (RT_SUCCESS(rc))
7624 {
7625 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7626 if (RT_SUCCESS(rc))
7627 {
7628 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7629 if (RT_SUCCESS(rc))
7630 {
7631 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7632 iemVmxVmentryInitReadOnlyFields(pVCpu);
7633
7634 /*
7635 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7636 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7637 * VM-exit when required.
7638 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7639 */
7640 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7641
7642 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7643 if (RT_SUCCESS(rc))
7644 {
7645 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7646 if (RT_SUCCESS(rc))
7647 {
7648 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7649 if (RT_SUCCESS(rc))
7650 {
7651 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7652
7653 /* VMLAUNCH instruction must update the VMCS launch state. */
7654 if (uInstrId == VMXINSTRID_VMLAUNCH)
7655 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7656
7657 /* Perform the VMX transition (PGM updates). */
7658 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7659 if (rcStrict == VINF_SUCCESS)
7660 { /* likely */ }
7661 else if (RT_SUCCESS(rcStrict))
7662 {
7663 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7664 VBOXSTRICTRC_VAL(rcStrict)));
7665 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7666 }
7667 else
7668 {
7669 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7670 return rcStrict;
7671 }
7672
7673 /* We've now entered nested-guest execution. */
7674 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7675
7676 /*
7677 * The priority of potential VM-exits during VM-entry is important.
7678 * The priorities of VM-exits and events are listed from highest
7679 * to lowest as follows:
7680 *
7681 * 1. Event injection.
7682 * 2. Trap on task-switch (T flag set in TSS).
7683 * 3. TPR below threshold / APIC-write.
7684 * 4. SMI, INIT.
7685 * 5. MTF exit.
7686 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7687 * 7. VMX-preemption timer.
7688 * 9. NMI-window exit.
7689 * 10. NMI injection.
7690 * 11. Interrupt-window exit.
7691 * 12. Virtual-interrupt injection.
7692 * 13. Interrupt injection.
7693 * 14. Process next instruction (fetch, decode, execute).
7694 */
7695
7696 /* Setup the VMX-preemption timer. */
7697 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7698
7699 /* Setup monitor-trap flag. */
7700 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7701
7702 /* Setup NMI-window exiting. */
7703 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7704
7705 /* Setup interrupt-window exiting. */
7706 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7707
7708 /* Now that we've switched page tables, we can go ahead and inject any event. */
7709 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7710 if (RT_SUCCESS(rcStrict))
7711 {
7712 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7713# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7714 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7715 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7716 if (rcSched != VINF_SUCCESS)
7717 iemSetPassUpStatus(pVCpu, rcSched);
7718# endif
7719 return VINF_SUCCESS;
7720 }
7721
7722 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7723 return rcStrict;
7724 }
7725 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7726 pVmcs->u64RoExitQual.u);
7727 }
7728 }
7729 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7730 pVmcs->u64RoExitQual.u);
7731 }
7732
7733 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7734 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7735 return VINF_SUCCESS;
7736 }
7737 }
7738 }
7739
7740 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7741 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7742 return VINF_SUCCESS;
7743# endif
7744}
7745
7746
7747/**
7748 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7749 * (causes a VM-exit) or not.
7750 *
7751 * @returns @c true if the instruction is intercepted, @c false otherwise.
7752 * @param pVCpu The cross context virtual CPU structure.
7753 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7754 * VMX_EXIT_WRMSR).
7755 * @param idMsr The MSR.
7756 */
7757IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7758{
7759 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7760 Assert( uExitReason == VMX_EXIT_RDMSR
7761 || uExitReason == VMX_EXIT_WRMSR);
7762
7763 /* Consult the MSR bitmap if the feature is supported. */
7764 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7765 Assert(pVmcs);
7766 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7767 {
7768 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7769 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7770 if (uExitReason == VMX_EXIT_RDMSR)
7771 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7772 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7773 }
7774
7775 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7776 return true;
7777}
7778
7779
7780/**
7781 * VMREAD common (memory/register) instruction execution worker
7782 *
7783 * @returns Strict VBox status code.
7784 * @param pVCpu The cross context virtual CPU structure.
7785 * @param cbInstr The instruction length in bytes.
7786 * @param pu64Dst Where to write the VMCS value (only updated when
7787 * VINF_SUCCESS is returned).
7788 * @param u64VmcsField The VMCS field.
7789 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7790 * NULL.
7791 */
7792IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7793 PCVMXVEXITINFO pExitInfo)
7794{
7795 /* Nested-guest intercept. */
7796 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7797 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7798 {
7799 if (pExitInfo)
7800 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7801 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7802 }
7803
7804 /* CPL. */
7805 if (pVCpu->iem.s.uCpl == 0)
7806 { /* likely */ }
7807 else
7808 {
7809 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7810 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7811 return iemRaiseGeneralProtectionFault0(pVCpu);
7812 }
7813
7814 /* VMCS pointer in root mode. */
7815 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7816 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7817 { /* likely */ }
7818 else
7819 {
7820 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7821 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7822 iemVmxVmFailInvalid(pVCpu);
7823 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7824 return VINF_SUCCESS;
7825 }
7826
7827 /* VMCS-link pointer in non-root mode. */
7828 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7829 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7830 { /* likely */ }
7831 else
7832 {
7833 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7834 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7835 iemVmxVmFailInvalid(pVCpu);
7836 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7837 return VINF_SUCCESS;
7838 }
7839
7840 /* Supported VMCS field. */
7841 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
7842 { /* likely */ }
7843 else
7844 {
7845 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7846 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7847 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7848 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7849 return VINF_SUCCESS;
7850 }
7851
7852 /*
7853 * Setup reading from the current or shadow VMCS.
7854 */
7855 uint8_t *pbVmcs;
7856 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7857 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7858 else
7859 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7860 Assert(pbVmcs);
7861
7862 VMXVMCSFIELD VmcsField;
7863 VmcsField.u = u64VmcsField;
7864 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
7865 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
7866 uint8_t const uWidthType = (uWidth << 2) | uType;
7867 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
7868 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7869 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7870 Assert(offField < VMX_V_VMCS_SIZE);
7871
7872 /*
7873 * Read the VMCS component based on the field's effective width.
7874 *
7875 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7876 * indicates high bits (little endian).
7877 *
7878 * Note! The caller is responsible to trim the result and update registers
7879 * or memory locations are required. Here we just zero-extend to the largest
7880 * type (i.e. 64-bits).
7881 */
7882 uint8_t *pbField = pbVmcs + offField;
7883 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7884 switch (uEffWidth)
7885 {
7886 case VMX_VMCS_ENC_WIDTH_64BIT:
7887 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7888 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7889 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7890 }
7891 return VINF_SUCCESS;
7892}
7893
7894
7895/**
7896 * VMREAD (64-bit register) instruction execution worker.
7897 *
7898 * @returns Strict VBox status code.
7899 * @param pVCpu The cross context virtual CPU structure.
7900 * @param cbInstr The instruction length in bytes.
7901 * @param pu64Dst Where to store the VMCS field's value.
7902 * @param u64VmcsField The VMCS field.
7903 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7904 * NULL.
7905 */
7906IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7907 PCVMXVEXITINFO pExitInfo)
7908{
7909 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7910 if (rcStrict == VINF_SUCCESS)
7911 {
7912 iemVmxVmreadSuccess(pVCpu, cbInstr);
7913 return VINF_SUCCESS;
7914 }
7915
7916 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7917 return rcStrict;
7918}
7919
7920
7921/**
7922 * VMREAD (32-bit register) instruction execution worker.
7923 *
7924 * @returns Strict VBox status code.
7925 * @param pVCpu The cross context virtual CPU structure.
7926 * @param cbInstr The instruction length in bytes.
7927 * @param pu32Dst Where to store the VMCS field's value.
7928 * @param u32VmcsField The VMCS field.
7929 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7930 * NULL.
7931 */
7932IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7933 PCVMXVEXITINFO pExitInfo)
7934{
7935 uint64_t u64Dst;
7936 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7937 if (rcStrict == VINF_SUCCESS)
7938 {
7939 *pu32Dst = u64Dst;
7940 iemVmxVmreadSuccess(pVCpu, cbInstr);
7941 return VINF_SUCCESS;
7942 }
7943
7944 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7945 return rcStrict;
7946}
7947
7948
7949/**
7950 * VMREAD (memory) instruction execution worker.
7951 *
7952 * @returns Strict VBox status code.
7953 * @param pVCpu The cross context virtual CPU structure.
7954 * @param cbInstr The instruction length in bytes.
7955 * @param iEffSeg The effective segment register to use with @a u64Val.
7956 * Pass UINT8_MAX if it is a register access.
7957 * @param GCPtrDst The guest linear address to store the VMCS field's
7958 * value.
7959 * @param u64VmcsField The VMCS field.
7960 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7961 * NULL.
7962 */
7963IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7964 PCVMXVEXITINFO pExitInfo)
7965{
7966 uint64_t u64Dst;
7967 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7968 if (rcStrict == VINF_SUCCESS)
7969 {
7970 /*
7971 * Write the VMCS field's value to the location specified in guest-memory.
7972 */
7973 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7974 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7975 else
7976 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7977 if (rcStrict == VINF_SUCCESS)
7978 {
7979 iemVmxVmreadSuccess(pVCpu, cbInstr);
7980 return VINF_SUCCESS;
7981 }
7982
7983 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7984 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7985 return rcStrict;
7986 }
7987
7988 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7989 return rcStrict;
7990}
7991
7992
7993/**
7994 * VMWRITE instruction execution worker.
7995 *
7996 * @returns Strict VBox status code.
7997 * @param pVCpu The cross context virtual CPU structure.
7998 * @param cbInstr The instruction length in bytes.
7999 * @param iEffSeg The effective segment register to use with @a u64Val.
8000 * Pass UINT8_MAX if it is a register access.
8001 * @param u64Val The value to write (or guest linear address to the
8002 * value), @a iEffSeg will indicate if it's a memory
8003 * operand.
8004 * @param u64VmcsField The VMCS field.
8005 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8006 * NULL.
8007 */
8008IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
8009 PCVMXVEXITINFO pExitInfo)
8010{
8011 /* Nested-guest intercept. */
8012 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8013 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8014 {
8015 if (pExitInfo)
8016 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8017 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8018 }
8019
8020 /* CPL. */
8021 if (pVCpu->iem.s.uCpl == 0)
8022 { /* likely */ }
8023 else
8024 {
8025 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8026 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8027 return iemRaiseGeneralProtectionFault0(pVCpu);
8028 }
8029
8030 /* VMCS pointer in root mode. */
8031 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8032 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8033 { /* likely */ }
8034 else
8035 {
8036 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8037 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8038 iemVmxVmFailInvalid(pVCpu);
8039 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8040 return VINF_SUCCESS;
8041 }
8042
8043 /* VMCS-link pointer in non-root mode. */
8044 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8045 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8046 { /* likely */ }
8047 else
8048 {
8049 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8050 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8051 iemVmxVmFailInvalid(pVCpu);
8052 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8053 return VINF_SUCCESS;
8054 }
8055
8056 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8057 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8058 if (!fIsRegOperand)
8059 {
8060 /* Read the value from the specified guest memory location. */
8061 VBOXSTRICTRC rcStrict;
8062 RTGCPTR const GCPtrVal = u64Val;
8063 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8064 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8065 else
8066 {
8067 uint32_t u32Val;
8068 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8069 u64Val = u32Val;
8070 }
8071 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8072 {
8073 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8074 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8075 return rcStrict;
8076 }
8077 }
8078 else
8079 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8080
8081 /* Supported VMCS field. */
8082 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
8083 { /* likely */ }
8084 else
8085 {
8086 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8087 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8088 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8089 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8090 return VINF_SUCCESS;
8091 }
8092
8093 /* Read-only VMCS field. */
8094 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
8095 if ( !fIsFieldReadOnly
8096 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8097 { /* likely */ }
8098 else
8099 {
8100 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8102 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8103 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8104 return VINF_SUCCESS;
8105 }
8106
8107 /*
8108 * Setup writing to the current or shadow VMCS.
8109 */
8110 uint8_t *pbVmcs;
8111 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8112 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8113 else
8114 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8115 Assert(pbVmcs);
8116
8117 VMXVMCSFIELD VmcsField;
8118 VmcsField.u = u64VmcsField;
8119 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
8120 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
8121 uint8_t const uWidthType = (uWidth << 2) | uType;
8122 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
8123 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8124 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8125 Assert(offField < VMX_V_VMCS_SIZE);
8126
8127 /*
8128 * Write the VMCS component based on the field's effective width.
8129 *
8130 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8131 * indicates high bits (little endian).
8132 */
8133 uint8_t *pbField = pbVmcs + offField;
8134 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
8135 switch (uEffWidth)
8136 {
8137 case VMX_VMCS_ENC_WIDTH_64BIT:
8138 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8139 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8140 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8141 }
8142
8143 iemVmxVmSucceed(pVCpu);
8144 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8145 return VINF_SUCCESS;
8146}
8147
8148
8149/**
8150 * VMCLEAR instruction execution worker.
8151 *
8152 * @returns Strict VBox status code.
8153 * @param pVCpu The cross context virtual CPU structure.
8154 * @param cbInstr The instruction length in bytes.
8155 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8156 * @param GCPtrVmcs The linear address of the VMCS pointer.
8157 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8158 * NULL.
8159 *
8160 * @remarks Common VMX instruction checks are already expected to by the caller,
8161 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8162 */
8163IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8164 PCVMXVEXITINFO pExitInfo)
8165{
8166 /* Nested-guest intercept. */
8167 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8168 {
8169 if (pExitInfo)
8170 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8171 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8172 }
8173
8174 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8175
8176 /* CPL. */
8177 if (pVCpu->iem.s.uCpl == 0)
8178 { /* likely */ }
8179 else
8180 {
8181 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8182 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8183 return iemRaiseGeneralProtectionFault0(pVCpu);
8184 }
8185
8186 /* Get the VMCS pointer from the location specified by the source memory operand. */
8187 RTGCPHYS GCPhysVmcs;
8188 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8189 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8190 { /* likely */ }
8191 else
8192 {
8193 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8194 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8195 return rcStrict;
8196 }
8197
8198 /* VMCS pointer alignment. */
8199 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8200 { /* likely */ }
8201 else
8202 {
8203 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8204 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8205 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8206 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8207 return VINF_SUCCESS;
8208 }
8209
8210 /* VMCS physical-address width limits. */
8211 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8212 { /* likely */ }
8213 else
8214 {
8215 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8216 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8217 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8218 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8219 return VINF_SUCCESS;
8220 }
8221
8222 /* VMCS is not the VMXON region. */
8223 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8224 { /* likely */ }
8225 else
8226 {
8227 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8228 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8229 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8230 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8231 return VINF_SUCCESS;
8232 }
8233
8234 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8235 restriction imposed by our implementation. */
8236 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8237 { /* likely */ }
8238 else
8239 {
8240 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8241 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8242 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8243 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8244 return VINF_SUCCESS;
8245 }
8246
8247 /*
8248 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8249 *
8250 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8251 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8252 * to 'clear'.
8253 */
8254 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8255 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8256 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8257 {
8258 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8259 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8260 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8261 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8262 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8263 }
8264 else
8265 {
8266 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8267 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8268 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8269 if (RT_FAILURE(rcStrict))
8270 return rcStrict;
8271 }
8272
8273 iemVmxVmSucceed(pVCpu);
8274 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8275 return VINF_SUCCESS;
8276}
8277
8278
8279/**
8280 * VMPTRST instruction execution worker.
8281 *
8282 * @returns Strict VBox status code.
8283 * @param pVCpu The cross context virtual CPU structure.
8284 * @param cbInstr The instruction length in bytes.
8285 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8286 * @param GCPtrVmcs The linear address of where to store the current VMCS
8287 * pointer.
8288 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8289 * NULL.
8290 *
8291 * @remarks Common VMX instruction checks are already expected to by the caller,
8292 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8293 */
8294IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8295 PCVMXVEXITINFO pExitInfo)
8296{
8297 /* Nested-guest intercept. */
8298 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8299 {
8300 if (pExitInfo)
8301 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8302 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8303 }
8304
8305 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8306
8307 /* CPL. */
8308 if (pVCpu->iem.s.uCpl == 0)
8309 { /* likely */ }
8310 else
8311 {
8312 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8313 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8314 return iemRaiseGeneralProtectionFault0(pVCpu);
8315 }
8316
8317 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8318 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8319 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8320 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8321 {
8322 iemVmxVmSucceed(pVCpu);
8323 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8324 return rcStrict;
8325 }
8326
8327 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8329 return rcStrict;
8330}
8331
8332
8333/**
8334 * VMPTRLD instruction execution worker.
8335 *
8336 * @returns Strict VBox status code.
8337 * @param pVCpu The cross context virtual CPU structure.
8338 * @param cbInstr The instruction length in bytes.
8339 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8340 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8341 * NULL.
8342 *
8343 * @remarks Common VMX instruction checks are already expected to by the caller,
8344 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8345 */
8346IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8347 PCVMXVEXITINFO pExitInfo)
8348{
8349 /* Nested-guest intercept. */
8350 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8351 {
8352 if (pExitInfo)
8353 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8354 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8355 }
8356
8357 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8358
8359 /* CPL. */
8360 if (pVCpu->iem.s.uCpl == 0)
8361 { /* likely */ }
8362 else
8363 {
8364 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8365 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8366 return iemRaiseGeneralProtectionFault0(pVCpu);
8367 }
8368
8369 /* Get the VMCS pointer from the location specified by the source memory operand. */
8370 RTGCPHYS GCPhysVmcs;
8371 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8372 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8373 { /* likely */ }
8374 else
8375 {
8376 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8377 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8378 return rcStrict;
8379 }
8380
8381 /* VMCS pointer alignment. */
8382 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8383 { /* likely */ }
8384 else
8385 {
8386 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8387 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8388 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8389 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8390 return VINF_SUCCESS;
8391 }
8392
8393 /* VMCS physical-address width limits. */
8394 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8395 { /* likely */ }
8396 else
8397 {
8398 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8399 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8400 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8401 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8402 return VINF_SUCCESS;
8403 }
8404
8405 /* VMCS is not the VMXON region. */
8406 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8407 { /* likely */ }
8408 else
8409 {
8410 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8411 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8412 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8413 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8414 return VINF_SUCCESS;
8415 }
8416
8417 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8418 restriction imposed by our implementation. */
8419 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8420 { /* likely */ }
8421 else
8422 {
8423 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8424 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8425 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8426 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8427 return VINF_SUCCESS;
8428 }
8429
8430 /* Read just the VMCS revision from the VMCS. */
8431 VMXVMCSREVID VmcsRevId;
8432 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8433 if (RT_SUCCESS(rc))
8434 { /* likely */ }
8435 else
8436 {
8437 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8438 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8439 return rc;
8440 }
8441
8442 /*
8443 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8444 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8445 */
8446 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8447 && ( !VmcsRevId.n.fIsShadowVmcs
8448 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8449 { /* likely */ }
8450 else
8451 {
8452 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8453 {
8454 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8455 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8456 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8457 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8458 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8459 return VINF_SUCCESS;
8460 }
8461
8462 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8464 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8465 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8466 return VINF_SUCCESS;
8467 }
8468
8469 /*
8470 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8471 * the cache of an existing, current VMCS back to guest memory before loading a new,
8472 * different current VMCS.
8473 */
8474 bool fLoadVmcsFromMem;
8475 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8476 {
8477 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8478 {
8479 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8480 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8481 fLoadVmcsFromMem = true;
8482 }
8483 else
8484 fLoadVmcsFromMem = false;
8485 }
8486 else
8487 fLoadVmcsFromMem = true;
8488
8489 if (fLoadVmcsFromMem)
8490 {
8491 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8492 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8493 sizeof(VMXVVMCS));
8494 if (RT_SUCCESS(rc))
8495 { /* likely */ }
8496 else
8497 {
8498 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8499 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8500 return rc;
8501 }
8502 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8503 }
8504
8505 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8506 iemVmxVmSucceed(pVCpu);
8507 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8508 return VINF_SUCCESS;
8509}
8510
8511
8512/**
8513 * INVVPID instruction execution worker.
8514 *
8515 * @returns Strict VBox status code.
8516 * @param pVCpu The cross context virtual CPU structure.
8517 * @param cbInstr The instruction length in bytes.
8518 * @param iEffSeg The segment of the invvpid descriptor.
8519 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8520 * @param u64InvvpidType The invalidation type.
8521 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8522 * NULL.
8523 *
8524 * @remarks Common VMX instruction checks are already expected to by the caller,
8525 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8526 */
8527IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8528 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8529{
8530 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8531 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8532 return iemRaiseUndefinedOpcode(pVCpu);
8533
8534 /* Nested-guest intercept. */
8535 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8536 {
8537 if (pExitInfo)
8538 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8539 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8540 }
8541
8542 /* CPL. */
8543 if (pVCpu->iem.s.uCpl != 0)
8544 {
8545 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8546 return iemRaiseGeneralProtectionFault0(pVCpu);
8547 }
8548
8549 /*
8550 * Validate INVVPID invalidation type.
8551 *
8552 * The instruction specifies exactly ONE of the supported invalidation types.
8553 *
8554 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8555 * supported. In theory, it's possible for a CPU to not support flushing individual
8556 * addresses but all the other types or any other combination. We do not take any
8557 * shortcuts here by assuming the types we currently expose to the guest.
8558 */
8559 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8560 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8561 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8562 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8563 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8564 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8565 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8566 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8567 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8568 { /* likely */ }
8569 else
8570 {
8571 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8572 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8573 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8574 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8575 return VINF_SUCCESS;
8576 }
8577
8578 /*
8579 * Fetch the invvpid descriptor from guest memory.
8580 */
8581 RTUINT128U uDesc;
8582 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8583 if (rcStrict == VINF_SUCCESS)
8584 {
8585 /*
8586 * Validate the descriptor.
8587 */
8588 if (uDesc.s.Lo > 0xfff)
8589 {
8590 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8591 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8592 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8593 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8594 return VINF_SUCCESS;
8595 }
8596
8597 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8598 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8599 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8600 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8601 switch (u64InvvpidType)
8602 {
8603 case VMXTLBFLUSHVPID_INDIV_ADDR:
8604 {
8605 if (uVpid != 0)
8606 {
8607 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8608 {
8609 /* Invalidate mappings for the linear address tagged with VPID. */
8610 /** @todo PGM support for VPID? Currently just flush everything. */
8611 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8612 iemVmxVmSucceed(pVCpu);
8613 }
8614 else
8615 {
8616 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8618 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8619 }
8620 }
8621 else
8622 {
8623 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8624 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8625 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8626 }
8627 break;
8628 }
8629
8630 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8631 {
8632 if (uVpid != 0)
8633 {
8634 /* Invalidate all mappings with VPID. */
8635 /** @todo PGM support for VPID? Currently just flush everything. */
8636 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8637 iemVmxVmSucceed(pVCpu);
8638 }
8639 else
8640 {
8641 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8642 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8643 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8644 }
8645 break;
8646 }
8647
8648 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8649 {
8650 /* Invalidate all mappings with non-zero VPIDs. */
8651 /** @todo PGM support for VPID? Currently just flush everything. */
8652 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8653 iemVmxVmSucceed(pVCpu);
8654 break;
8655 }
8656
8657 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8658 {
8659 if (uVpid != 0)
8660 {
8661 /* Invalidate all mappings with VPID except global translations. */
8662 /** @todo PGM support for VPID? Currently just flush everything. */
8663 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8664 iemVmxVmSucceed(pVCpu);
8665 }
8666 else
8667 {
8668 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8669 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8670 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8671 }
8672 break;
8673 }
8674 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8675 }
8676 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8677 }
8678 return rcStrict;
8679}
8680
8681
8682/**
8683 * VMXON instruction execution worker.
8684 *
8685 * @returns Strict VBox status code.
8686 * @param pVCpu The cross context virtual CPU structure.
8687 * @param cbInstr The instruction length in bytes.
8688 * @param iEffSeg The effective segment register to use with @a
8689 * GCPtrVmxon.
8690 * @param GCPtrVmxon The linear address of the VMXON pointer.
8691 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8692 * NULL.
8693 *
8694 * @remarks Common VMX instruction checks are already expected to by the caller,
8695 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8696 */
8697IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8698 PCVMXVEXITINFO pExitInfo)
8699{
8700 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8701 {
8702 /* CPL. */
8703 if (pVCpu->iem.s.uCpl == 0)
8704 { /* likely */ }
8705 else
8706 {
8707 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8709 return iemRaiseGeneralProtectionFault0(pVCpu);
8710 }
8711
8712 /* A20M (A20 Masked) mode. */
8713 if (PGMPhysIsA20Enabled(pVCpu))
8714 { /* likely */ }
8715 else
8716 {
8717 Log(("vmxon: A20M mode -> #GP(0)\n"));
8718 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8719 return iemRaiseGeneralProtectionFault0(pVCpu);
8720 }
8721
8722 /* CR0. */
8723 {
8724 /* CR0 MB1 bits. */
8725 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8726 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8727 { /* likely */ }
8728 else
8729 {
8730 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8731 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8732 return iemRaiseGeneralProtectionFault0(pVCpu);
8733 }
8734
8735 /* CR0 MBZ bits. */
8736 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8737 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8738 { /* likely */ }
8739 else
8740 {
8741 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8742 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8743 return iemRaiseGeneralProtectionFault0(pVCpu);
8744 }
8745 }
8746
8747 /* CR4. */
8748 {
8749 /* CR4 MB1 bits. */
8750 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8751 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8752 { /* likely */ }
8753 else
8754 {
8755 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8756 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8757 return iemRaiseGeneralProtectionFault0(pVCpu);
8758 }
8759
8760 /* CR4 MBZ bits. */
8761 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8762 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8763 { /* likely */ }
8764 else
8765 {
8766 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8767 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8768 return iemRaiseGeneralProtectionFault0(pVCpu);
8769 }
8770 }
8771
8772 /* Feature control MSR's LOCK and VMXON bits. */
8773 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8774 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8775 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8776 { /* likely */ }
8777 else
8778 {
8779 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8780 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8781 return iemRaiseGeneralProtectionFault0(pVCpu);
8782 }
8783
8784 /* Get the VMXON pointer from the location specified by the source memory operand. */
8785 RTGCPHYS GCPhysVmxon;
8786 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8787 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8788 { /* likely */ }
8789 else
8790 {
8791 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8792 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8793 return rcStrict;
8794 }
8795
8796 /* VMXON region pointer alignment. */
8797 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8798 { /* likely */ }
8799 else
8800 {
8801 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8802 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8803 iemVmxVmFailInvalid(pVCpu);
8804 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8805 return VINF_SUCCESS;
8806 }
8807
8808 /* VMXON physical-address width limits. */
8809 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8810 { /* likely */ }
8811 else
8812 {
8813 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8814 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8815 iemVmxVmFailInvalid(pVCpu);
8816 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8817 return VINF_SUCCESS;
8818 }
8819
8820 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8821 restriction imposed by our implementation. */
8822 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8823 { /* likely */ }
8824 else
8825 {
8826 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8828 iemVmxVmFailInvalid(pVCpu);
8829 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8830 return VINF_SUCCESS;
8831 }
8832
8833 /* Read the VMCS revision ID from the VMXON region. */
8834 VMXVMCSREVID VmcsRevId;
8835 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8836 if (RT_SUCCESS(rc))
8837 { /* likely */ }
8838 else
8839 {
8840 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8841 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8842 return rc;
8843 }
8844
8845 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8846 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8847 { /* likely */ }
8848 else
8849 {
8850 /* Revision ID mismatch. */
8851 if (!VmcsRevId.n.fIsShadowVmcs)
8852 {
8853 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8854 VmcsRevId.n.u31RevisionId));
8855 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8856 iemVmxVmFailInvalid(pVCpu);
8857 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8858 return VINF_SUCCESS;
8859 }
8860
8861 /* Shadow VMCS disallowed. */
8862 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8863 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8864 iemVmxVmFailInvalid(pVCpu);
8865 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8866 return VINF_SUCCESS;
8867 }
8868
8869 /*
8870 * Record that we're in VMX operation, block INIT, block and disable A20M.
8871 */
8872 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8873 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8874 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8875
8876 /* Clear address-range monitoring. */
8877 EMMonitorWaitClear(pVCpu);
8878 /** @todo NSTVMX: Intel PT. */
8879
8880 iemVmxVmSucceed(pVCpu);
8881 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8882 return VINF_SUCCESS;
8883 }
8884 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8885 {
8886 /* Nested-guest intercept. */
8887 if (pExitInfo)
8888 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8889 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8890 }
8891
8892 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8893
8894 /* CPL. */
8895 if (pVCpu->iem.s.uCpl > 0)
8896 {
8897 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8898 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8899 return iemRaiseGeneralProtectionFault0(pVCpu);
8900 }
8901
8902 /* VMXON when already in VMX root mode. */
8903 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8904 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8906 return VINF_SUCCESS;
8907}
8908
8909
8910/**
8911 * Implements 'VMXOFF'.
8912 *
8913 * @remarks Common VMX instruction checks are already expected to by the caller,
8914 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8915 */
8916IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8917{
8918 /* Nested-guest intercept. */
8919 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8920 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8921
8922 /* CPL. */
8923 if (pVCpu->iem.s.uCpl == 0)
8924 { /* likely */ }
8925 else
8926 {
8927 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8928 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8929 return iemRaiseGeneralProtectionFault0(pVCpu);
8930 }
8931
8932 /* Dual monitor treatment of SMIs and SMM. */
8933 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8934 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8935 { /* likely */ }
8936 else
8937 {
8938 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8939 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8940 return VINF_SUCCESS;
8941 }
8942
8943 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8944 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8945 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8946
8947 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8948 { /** @todo NSTVMX: Unblock SMI. */ }
8949
8950 EMMonitorWaitClear(pVCpu);
8951 /** @todo NSTVMX: Unblock and enable A20M. */
8952
8953 iemVmxVmSucceed(pVCpu);
8954 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8955 return VINF_SUCCESS;
8956}
8957
8958
8959/**
8960 * Implements 'VMXON'.
8961 */
8962IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8963{
8964 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8965}
8966
8967
8968/**
8969 * Implements 'VMLAUNCH'.
8970 */
8971IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8972{
8973 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8974}
8975
8976
8977/**
8978 * Implements 'VMRESUME'.
8979 */
8980IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8981{
8982 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8983}
8984
8985
8986/**
8987 * Implements 'VMPTRLD'.
8988 */
8989IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8990{
8991 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8992}
8993
8994
8995/**
8996 * Implements 'VMPTRST'.
8997 */
8998IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8999{
9000 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9001}
9002
9003
9004/**
9005 * Implements 'VMCLEAR'.
9006 */
9007IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9008{
9009 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9010}
9011
9012
9013/**
9014 * Implements 'VMWRITE' register.
9015 */
9016IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9017{
9018 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9019}
9020
9021
9022/**
9023 * Implements 'VMWRITE' memory.
9024 */
9025IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9026{
9027 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9028}
9029
9030
9031/**
9032 * Implements 'VMREAD' register (64-bit).
9033 */
9034IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9035{
9036 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9037}
9038
9039
9040/**
9041 * Implements 'VMREAD' register (32-bit).
9042 */
9043IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9044{
9045 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9046}
9047
9048
9049/**
9050 * Implements 'VMREAD' memory, 64-bit register.
9051 */
9052IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9053{
9054 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9055}
9056
9057
9058/**
9059 * Implements 'VMREAD' memory, 32-bit register.
9060 */
9061IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9062{
9063 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9064}
9065
9066
9067/**
9068 * Implements 'INVVPID'.
9069 */
9070IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9071{
9072 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9073}
9074
9075
9076/**
9077 * Implements VMX's implementation of PAUSE.
9078 */
9079IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9080{
9081 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9082 {
9083 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9084 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9085 return rcStrict;
9086 }
9087
9088 /*
9089 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9090 * a VM-exit, the instruction operates normally.
9091 */
9092 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9093 return VINF_SUCCESS;
9094}
9095
9096#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9097
9098
9099/**
9100 * Implements 'VMCALL'.
9101 */
9102IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9103{
9104#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9105 /* Nested-guest intercept. */
9106 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9107 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9108#endif
9109
9110 /* Join forces with vmmcall. */
9111 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9112}
9113
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