VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79205

Last change on this file since 79205 was 79203, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 VMX_VMCS_ENC_XXX -> VMX_VMCSFIELD_XXX.
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File size: 348.5 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79203 2019-06-18 09:14:02Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Gets a CR3 target value from the VMCS.
621 *
622 * @returns VBox status code.
623 * @param pVmcs Pointer to the virtual VMCS.
624 * @param idxCr3Target The index of the CR3-target value to retrieve.
625 * @param puValue Where to store the CR3-target value.
626 */
627IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
628{
629 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
630 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
631 uint8_t const uType = VMX_VMCSFIELD_TYPE_CONTROL;
632 uint8_t const uWidthType = (uWidth << 2) | uType;
633 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCSFIELD_INDEX);
634 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
635 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
636 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
637 uint8_t const *pbField = pbVmcs + offField;
638 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
639 return uCr3TargetValue;
640}
641
642
643/**
644 * Converts an IEM exception event type to a VMX event type.
645 *
646 * @returns The VMX event type.
647 * @param uVector The interrupt / exception vector.
648 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
649 */
650DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
651{
652 /* Paranoia (callers may use these interchangeably). */
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
662 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
663 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
664 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
665
666 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
667 {
668 if (uVector == X86_XCPT_NMI)
669 return VMX_EXIT_INT_INFO_TYPE_NMI;
670 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
671 }
672
673 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
674 {
675 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
676 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
677 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
678 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
679 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
680 }
681
682 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
683 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
684}
685
686
687/**
688 * Sets the Exit qualification VMCS field.
689 *
690 * @param pVCpu The cross context virtual CPU structure.
691 * @param u64ExitQual The Exit qualification.
692 */
693DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
694{
695 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
696 pVmcs->u64RoExitQual.u = u64ExitQual;
697}
698
699
700/**
701 * Sets the VM-exit interruption information field.
702 *
703 * @param pVCpu The cross context virtual CPU structure.
704 * @param uExitIntInfo The VM-exit interruption information.
705 */
706DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
707{
708 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
709 pVmcs->u32RoExitIntInfo = uExitIntInfo;
710}
711
712
713/**
714 * Sets the VM-exit interruption error code.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uErrCode The error code.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
720{
721 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
722 pVmcs->u32RoExitIntErrCode = uErrCode;
723}
724
725
726/**
727 * Sets the IDT-vectoring information field.
728 *
729 * @param pVCpu The cross context virtual CPU structure.
730 * @param uIdtVectorInfo The IDT-vectoring information.
731 */
732DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
733{
734 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
735 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
736}
737
738
739/**
740 * Sets the IDT-vectoring error code field.
741 *
742 * @param pVCpu The cross context virtual CPU structure.
743 * @param uErrCode The error code.
744 */
745DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
746{
747 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
748 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
749}
750
751
752/**
753 * Sets the VM-exit guest-linear address VMCS field.
754 *
755 * @param pVCpu The cross context virtual CPU structure.
756 * @param uGuestLinearAddr The VM-exit guest-linear address.
757 */
758DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
759{
760 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
761 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
762}
763
764
765/**
766 * Sets the VM-exit guest-physical address VMCS field.
767 *
768 * @param pVCpu The cross context virtual CPU structure.
769 * @param uGuestPhysAddr The VM-exit guest-physical address.
770 */
771DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
772{
773 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
774 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
775}
776
777
778/**
779 * Sets the VM-exit instruction length VMCS field.
780 *
781 * @param pVCpu The cross context virtual CPU structure.
782 * @param cbInstr The VM-exit instruction length in bytes.
783 *
784 * @remarks Callers may clear this field to 0. Hence, this function does not check
785 * the validity of the instruction length.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
788{
789 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
790 pVmcs->u32RoExitInstrLen = cbInstr;
791}
792
793
794/**
795 * Sets the VM-exit instruction info. VMCS field.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 * @param uExitInstrInfo The VM-exit instruction information.
799 */
800DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
801{
802 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
803 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
804}
805
806
807/**
808 * Implements VMSucceed for VMX instruction success.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 */
812DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
813{
814 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
815}
816
817
818/**
819 * Implements VMFailInvalid for VMX instruction failure.
820 *
821 * @param pVCpu The cross context virtual CPU structure.
822 */
823DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
824{
825 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
826}
827
828
829/**
830 * Implements VMFail for VMX instruction failure.
831 *
832 * @param pVCpu The cross context virtual CPU structure.
833 * @param enmInsErr The VM instruction error.
834 */
835DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
836{
837 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
838}
839
840
841/**
842 * Checks if the given auto-load/store MSR area count is valid for the
843 * implementation.
844 *
845 * @returns @c true if it's within the valid limit, @c false otherwise.
846 * @param pVCpu The cross context virtual CPU structure.
847 * @param uMsrCount The MSR area count to check.
848 */
849DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
850{
851 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
852 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
853 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
854 if (uMsrCount <= cMaxSupportedMsrs)
855 return true;
856 return false;
857}
858
859
860/**
861 * Flushes the current VMCS contents back to guest memory.
862 *
863 * @returns VBox status code.
864 * @param pVCpu The cross context virtual CPU structure.
865 */
866DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
867{
868 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
869 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
870 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
871 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
872 return rc;
873}
874
875
876/**
877 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
878 *
879 * @param pVCpu The cross context virtual CPU structure.
880 */
881DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
882{
883 iemVmxVmSucceed(pVCpu);
884 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
885}
886
887
888/**
889 * Gets the instruction diagnostic for segment base checks during VM-entry of a
890 * nested-guest.
891 *
892 * @param iSegReg The segment index (X86_SREG_XXX).
893 */
894IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
895{
896 switch (iSegReg)
897 {
898 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
899 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
900 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
901 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
902 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
903 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
904 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
905 }
906}
907
908
909/**
910 * Gets the instruction diagnostic for segment base checks during VM-entry of a
911 * nested-guest that is in Virtual-8086 mode.
912 *
913 * @param iSegReg The segment index (X86_SREG_XXX).
914 */
915IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
916{
917 switch (iSegReg)
918 {
919 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
920 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
921 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
922 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
923 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
924 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
925 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
926 }
927}
928
929
930/**
931 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
932 * nested-guest that is in Virtual-8086 mode.
933 *
934 * @param iSegReg The segment index (X86_SREG_XXX).
935 */
936IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
937{
938 switch (iSegReg)
939 {
940 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
941 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
942 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
943 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
944 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
945 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
946 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
947 }
948}
949
950
951/**
952 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
953 * nested-guest that is in Virtual-8086 mode.
954 *
955 * @param iSegReg The segment index (X86_SREG_XXX).
956 */
957IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
958{
959 switch (iSegReg)
960 {
961 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
962 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
963 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
964 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
965 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
966 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
967 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
968 }
969}
970
971
972/**
973 * Gets the instruction diagnostic for segment attributes reserved bits failure
974 * during VM-entry of a nested-guest.
975 *
976 * @param iSegReg The segment index (X86_SREG_XXX).
977 */
978IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
979{
980 switch (iSegReg)
981 {
982 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
983 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
984 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
985 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
986 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
987 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
988 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
989 }
990}
991
992
993/**
994 * Gets the instruction diagnostic for segment attributes descriptor-type
995 * (code/segment or system) failure during VM-entry of a nested-guest.
996 *
997 * @param iSegReg The segment index (X86_SREG_XXX).
998 */
999IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1000{
1001 switch (iSegReg)
1002 {
1003 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1004 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1005 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1006 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1007 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1008 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1009 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1010 }
1011}
1012
1013
1014/**
1015 * Gets the instruction diagnostic for segment attributes descriptor-type
1016 * (code/segment or system) failure during VM-entry of a nested-guest.
1017 *
1018 * @param iSegReg The segment index (X86_SREG_XXX).
1019 */
1020IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1021{
1022 switch (iSegReg)
1023 {
1024 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1025 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1026 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1027 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1028 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1029 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1030 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1031 }
1032}
1033
1034
1035/**
1036 * Gets the instruction diagnostic for segment attribute granularity failure during
1037 * VM-entry of a nested-guest.
1038 *
1039 * @param iSegReg The segment index (X86_SREG_XXX).
1040 */
1041IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1042{
1043 switch (iSegReg)
1044 {
1045 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1046 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1047 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1048 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1049 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1050 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1051 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1052 }
1053}
1054
1055/**
1056 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1057 * VM-entry of a nested-guest.
1058 *
1059 * @param iSegReg The segment index (X86_SREG_XXX).
1060 */
1061IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1062{
1063 switch (iSegReg)
1064 {
1065 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1066 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1067 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1068 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1069 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1070 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1071 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1072 }
1073}
1074
1075
1076/**
1077 * Gets the instruction diagnostic for segment attribute type accessed failure
1078 * during VM-entry of a nested-guest.
1079 *
1080 * @param iSegReg The segment index (X86_SREG_XXX).
1081 */
1082IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1083{
1084 switch (iSegReg)
1085 {
1086 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1087 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1088 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1089 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1090 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1091 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1092 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1093 }
1094}
1095
1096
1097/**
1098 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1099 * failure during VM-entry of a nested-guest.
1100 *
1101 * @param iSegReg The PDPTE entry index.
1102 */
1103IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1104{
1105 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1106 switch (iPdpte)
1107 {
1108 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1109 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1110 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1111 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1112 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1113 }
1114}
1115
1116
1117/**
1118 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1119 * failure during VM-exit of a nested-guest.
1120 *
1121 * @param iSegReg The PDPTE entry index.
1122 */
1123IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1124{
1125 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1126 switch (iPdpte)
1127 {
1128 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1129 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1130 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1131 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1132 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1133 }
1134}
1135
1136
1137/**
1138 * Saves the guest control registers, debug registers and some MSRs are part of
1139 * VM-exit.
1140 *
1141 * @param pVCpu The cross context virtual CPU structure.
1142 */
1143IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1144{
1145 /*
1146 * Saves the guest control registers, debug registers and some MSRs.
1147 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1148 */
1149 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1150
1151 /* Save control registers. */
1152 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1153 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1154 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1155
1156 /* Save SYSENTER CS, ESP, EIP. */
1157 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1158 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1159 {
1160 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1161 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1162 }
1163 else
1164 {
1165 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1166 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1167 }
1168
1169 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1170 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1171 {
1172 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1173 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1174 }
1175
1176 /* Save PAT MSR. */
1177 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1178 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1179
1180 /* Save EFER MSR. */
1181 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1182 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1183
1184 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1185 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1186
1187 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1188}
1189
1190
1191/**
1192 * Saves the guest force-flags in preparation of entering the nested-guest.
1193 *
1194 * @param pVCpu The cross context virtual CPU structure.
1195 */
1196IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1197{
1198 /* We shouldn't be called multiple times during VM-entry. */
1199 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1200
1201 /* MTF should not be set outside VMX non-root mode. */
1202 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1203
1204 /*
1205 * Preserve the required force-flags.
1206 *
1207 * We cache and clear force-flags that would affect the execution of the
1208 * nested-guest. Cached flags are then restored while returning to the guest
1209 * if necessary.
1210 *
1211 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1212 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1213 * instruction. Interrupt inhibition for any nested-guest instruction
1214 * is supplied by the guest-interruptibility state VMCS field and will
1215 * be set up as part of loading the guest state.
1216 *
1217 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1218 * successful VM-entry (due to invalid guest-state) need to continue
1219 * blocking NMIs if it was in effect before VM-entry.
1220 *
1221 * - MTF need not be preserved as it's used only in VMX non-root mode and
1222 * is supplied through the VM-execution controls.
1223 *
1224 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1225 * we will be able to generate interrupts that may cause VM-exits for
1226 * the nested-guest.
1227 */
1228 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1229}
1230
1231
1232/**
1233 * Restores the guest force-flags in preparation of exiting the nested-guest.
1234 *
1235 * @param pVCpu The cross context virtual CPU structure.
1236 */
1237IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1238{
1239 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1240 {
1241 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1242 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1243 }
1244}
1245
1246
1247/**
1248 * Perform a VMX transition updated PGM, IEM and CPUM.
1249 *
1250 * @param pVCpu The cross context virtual CPU structure.
1251 */
1252IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1253{
1254 /*
1255 * Inform PGM about paging mode changes.
1256 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1257 * see comment in iemMemPageTranslateAndCheckAccess().
1258 */
1259 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1260# ifdef IN_RING3
1261 Assert(rc != VINF_PGM_CHANGE_MODE);
1262# endif
1263 AssertRCReturn(rc, rc);
1264
1265 /* Inform CPUM (recompiler), can later be removed. */
1266 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1267
1268 /*
1269 * Flush the TLB with new CR3. This is required in case the PGM mode change
1270 * above doesn't actually change anything.
1271 */
1272 if (rc == VINF_SUCCESS)
1273 {
1274 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1275 AssertRCReturn(rc, rc);
1276 }
1277
1278 /* Re-initialize IEM cache/state after the drastic mode switch. */
1279 iemReInitExec(pVCpu);
1280 return rc;
1281}
1282
1283
1284/**
1285 * Calculates the current VMX-preemption timer value.
1286 *
1287 * @param pVCpu The cross context virtual CPU structure.
1288 */
1289IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1290{
1291 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1292 Assert(pVmcs);
1293
1294 /*
1295 * Assume the following:
1296 * PreemptTimerShift = 5
1297 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1298 * EntryTick = 50000 (TSC at time of VM-entry)
1299 *
1300 * CurTick Delta PreemptTimerVal
1301 * ----------------------------------
1302 * 60000 10000 2
1303 * 80000 30000 1
1304 * 90000 40000 0 -> VM-exit.
1305 *
1306 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1307 * The saved VMX-preemption timer value is calculated as follows:
1308 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1309 * E.g.:
1310 * Delta = 10000
1311 * Tmp = 10000 / (2 * 10000) = 0.5
1312 * NewPt = 2 - 0.5 = 2
1313 * Delta = 30000
1314 * Tmp = 30000 / (2 * 10000) = 1.5
1315 * NewPt = 2 - 1.5 = 1
1316 * Delta = 40000
1317 * Tmp = 40000 / 20000 = 2
1318 * NewPt = 2 - 2 = 0
1319 */
1320 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1321 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1322 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1323 uint64_t const uDelta = uCurTick - uEntryTick;
1324 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1325 uint32_t const uPreemptTimer = uVmcsPreemptVal
1326 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1327 return uPreemptTimer;
1328}
1329
1330
1331/**
1332 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1333 *
1334 * @param pVCpu The cross context virtual CPU structure.
1335 */
1336IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1337{
1338 /*
1339 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1340 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1341 */
1342 /* CS, SS, ES, DS, FS, GS. */
1343 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1344 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1345 {
1346 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1347 if (!pSelReg->Attr.n.u1Unusable)
1348 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1349 else
1350 {
1351 /*
1352 * For unusable segments the attributes are undefined except for CS and SS.
1353 * For the rest we don't bother preserving anything but the unusable bit.
1354 */
1355 switch (iSegReg)
1356 {
1357 case X86_SREG_CS:
1358 pVmcs->GuestCs = pSelReg->Sel;
1359 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1360 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1361 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1362 | X86DESCATTR_UNUSABLE);
1363 break;
1364
1365 case X86_SREG_SS:
1366 pVmcs->GuestSs = pSelReg->Sel;
1367 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1368 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1369 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1370 break;
1371
1372 case X86_SREG_DS:
1373 pVmcs->GuestDs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1377 break;
1378
1379 case X86_SREG_ES:
1380 pVmcs->GuestEs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1384 break;
1385
1386 case X86_SREG_FS:
1387 pVmcs->GuestFs = pSelReg->Sel;
1388 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1389 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1390 break;
1391
1392 case X86_SREG_GS:
1393 pVmcs->GuestGs = pSelReg->Sel;
1394 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1395 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1396 break;
1397 }
1398 }
1399 }
1400
1401 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1402 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1403 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1404 | X86DESCATTR_UNUSABLE;
1405 /* LDTR. */
1406 {
1407 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1408 pVmcs->GuestLdtr = pSelReg->Sel;
1409 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1410 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1411 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1412 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1413 }
1414
1415 /* TR. */
1416 {
1417 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1418 pVmcs->GuestTr = pSelReg->Sel;
1419 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1420 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1421 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1422 }
1423
1424 /* GDTR. */
1425 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1426 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1427
1428 /* IDTR. */
1429 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1430 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1431}
1432
1433
1434/**
1435 * Saves guest non-register state as part of VM-exit.
1436 *
1437 * @param pVCpu The cross context virtual CPU structure.
1438 * @param uExitReason The VM-exit reason.
1439 */
1440IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1441{
1442 /*
1443 * Save guest non-register state.
1444 * See Intel spec. 27.3.4 "Saving Non-Register State".
1445 */
1446 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1447
1448 /*
1449 * Activity state.
1450 * Most VM-exits will occur in the active state. However, if the first instruction
1451 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1452 * the VM-exit will be from the HLT activity state.
1453 *
1454 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1455 */
1456 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1457 * not? */
1458 EMSTATE const enmActivityState = EMGetState(pVCpu);
1459 switch (enmActivityState)
1460 {
1461 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1462 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1463 }
1464
1465 /*
1466 * Interruptibility-state.
1467 */
1468 /* NMI. */
1469 pVmcs->u32GuestIntrState = 0;
1470 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1471 {
1472 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1473 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1474 }
1475 else
1476 {
1477 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1478 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1479 }
1480
1481 /* Blocking-by-STI. */
1482 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1483 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1484 {
1485 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1486 * currently. */
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1488 }
1489 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1490
1491 /*
1492 * Pending debug exceptions.
1493 */
1494 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1495 && uExitReason != VMX_EXIT_SMI
1496 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1497 && !HMVmxIsVmexitTrapLike(uExitReason))
1498 {
1499 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1500 * block-by-MovSS is in effect. */
1501 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1502 }
1503 else
1504 {
1505 /*
1506 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1507 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1508 *
1509 * See Intel spec. 24.4.2 "Guest Non-Register State".
1510 */
1511 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1512 * DR6. */
1513 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1514 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1515 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1516 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1517 if (fPendingDbgMask & fBpHitMask)
1518 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1519 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1520 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1521 }
1522
1523 /*
1524 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1525 *
1526 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1527 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1528 */
1529 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1530 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1531 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1532
1533 /* PDPTEs. */
1534 /* We don't support EPT yet. */
1535 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1536 pVmcs->u64GuestPdpte0.u = 0;
1537 pVmcs->u64GuestPdpte1.u = 0;
1538 pVmcs->u64GuestPdpte2.u = 0;
1539 pVmcs->u64GuestPdpte3.u = 0;
1540}
1541
1542
1543/**
1544 * Saves the guest-state as part of VM-exit.
1545 *
1546 * @returns VBox status code.
1547 * @param pVCpu The cross context virtual CPU structure.
1548 * @param uExitReason The VM-exit reason.
1549 */
1550IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1551{
1552 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1553 Assert(pVmcs);
1554
1555 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1556 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1557
1558 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1559 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1560 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1561
1562 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1563}
1564
1565
1566/**
1567 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1568 *
1569 * @returns VBox status code.
1570 * @param pVCpu The cross context virtual CPU structure.
1571 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1572 */
1573IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1574{
1575 /*
1576 * Save guest MSRs.
1577 * See Intel spec. 27.4 "Saving MSRs".
1578 */
1579 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1580 const char *const pszFailure = "VMX-abort";
1581
1582 /*
1583 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1584 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1585 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1586 */
1587 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1588 if (!cMsrs)
1589 return VINF_SUCCESS;
1590
1591 /*
1592 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1593 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1594 * implementation causes a VMX-abort followed by a triple-fault.
1595 */
1596 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1597 if (fIsMsrCountValid)
1598 { /* likely */ }
1599 else
1600 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1601
1602 /*
1603 * Optimization if the guest hypervisor is using the same guest-physical page for both
1604 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1605 */
1606 PVMXAUTOMSR pMsrArea;
1607 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1608 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1609 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1610 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1611 else
1612 {
1613 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1614 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1615 if (RT_SUCCESS(rc))
1616 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1617 else
1618 {
1619 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1620 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1621 }
1622 }
1623
1624 /*
1625 * Update VM-exit MSR store area.
1626 */
1627 PVMXAUTOMSR pMsr = pMsrArea;
1628 Assert(pMsr);
1629 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1630 {
1631 if ( !pMsr->u32Reserved
1632 && pMsr->u32Msr != MSR_IA32_SMBASE
1633 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1634 {
1635 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1636 if (rcStrict == VINF_SUCCESS)
1637 continue;
1638
1639 /*
1640 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1641 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1642 * recording the MSR index in the auxiliary info. field and indicated further by our
1643 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1644 * if possible, or come up with a better, generic solution.
1645 */
1646 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1647 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1648 ? kVmxVDiag_Vmexit_MsrStoreRing3
1649 : kVmxVDiag_Vmexit_MsrStore;
1650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1651 }
1652 else
1653 {
1654 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1655 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1656 }
1657 }
1658
1659 /*
1660 * Commit the VM-exit MSR store are to guest memory.
1661 */
1662 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1663 if (RT_SUCCESS(rc))
1664 return VINF_SUCCESS;
1665
1666 NOREF(uExitReason);
1667 NOREF(pszFailure);
1668
1669 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1670 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1671}
1672
1673
1674/**
1675 * Performs a VMX abort (due to an fatal error during VM-exit).
1676 *
1677 * @returns Strict VBox status code.
1678 * @param pVCpu The cross context virtual CPU structure.
1679 * @param enmAbort The VMX abort reason.
1680 */
1681IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1682{
1683 /*
1684 * Perform the VMX abort.
1685 * See Intel spec. 27.7 "VMX Aborts".
1686 */
1687 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1688
1689 /* We don't support SMX yet. */
1690 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1691 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1692 {
1693 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1694 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1695 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1696 }
1697
1698 return VINF_EM_TRIPLE_FAULT;
1699}
1700
1701
1702/**
1703 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1704 *
1705 * @param pVCpu The cross context virtual CPU structure.
1706 */
1707IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1708{
1709 /*
1710 * Load host control registers, debug registers and MSRs.
1711 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1712 */
1713 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1714 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1715
1716 /* CR0. */
1717 {
1718 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1719 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1720 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1721 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1722 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1723 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1724 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1725 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1726 }
1727
1728 /* CR4. */
1729 {
1730 /* Fixed CR4 bits are not modified. */
1731 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1732 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1733 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1734 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1735 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1736 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1737 if (fHostInLongMode)
1738 uValidHostCr4 |= X86_CR4_PAE;
1739 else
1740 uValidHostCr4 &= ~X86_CR4_PCIDE;
1741 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1742 }
1743
1744 /* CR3 (host value validated while checking host-state during VM-entry). */
1745 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1746
1747 /* DR7. */
1748 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1749
1750 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1751
1752 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1753 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1754 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1755 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1756
1757 /* FS, GS bases are loaded later while we load host segment registers. */
1758
1759 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1760 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1761 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1762 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1763 {
1764 if (fHostInLongMode)
1765 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1766 else
1767 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1768 }
1769
1770 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1771
1772 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1773 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1774 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1775
1776 /* We don't support IA32_BNDCFGS MSR yet. */
1777}
1778
1779
1780/**
1781 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1782 *
1783 * @param pVCpu The cross context virtual CPU structure.
1784 */
1785IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
1786{
1787 /*
1788 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1789 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1790 *
1791 * Warning! Be careful to not touch fields that are reserved by VT-x,
1792 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1793 */
1794 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1795 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1796
1797 /* CS, SS, ES, DS, FS, GS. */
1798 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1799 {
1800 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1801 bool const fUnusable = RT_BOOL(HostSel == 0);
1802 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1803
1804 /* Selector. */
1805 pSelReg->Sel = HostSel;
1806 pSelReg->ValidSel = HostSel;
1807 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1808
1809 /* Limit. */
1810 pSelReg->u32Limit = 0xffffffff;
1811
1812 /* Base. */
1813 pSelReg->u64Base = 0;
1814
1815 /* Attributes. */
1816 if (iSegReg == X86_SREG_CS)
1817 {
1818 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1819 pSelReg->Attr.n.u1DescType = 1;
1820 pSelReg->Attr.n.u2Dpl = 0;
1821 pSelReg->Attr.n.u1Present = 1;
1822 pSelReg->Attr.n.u1Long = fHostInLongMode;
1823 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1824 pSelReg->Attr.n.u1Granularity = 1;
1825 Assert(!pSelReg->Attr.n.u1Unusable);
1826 Assert(!fUnusable);
1827 }
1828 else
1829 {
1830 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1831 pSelReg->Attr.n.u1DescType = 1;
1832 pSelReg->Attr.n.u2Dpl = 0;
1833 pSelReg->Attr.n.u1Present = 1;
1834 pSelReg->Attr.n.u1DefBig = 1;
1835 pSelReg->Attr.n.u1Granularity = 1;
1836 pSelReg->Attr.n.u1Unusable = fUnusable;
1837 }
1838 }
1839
1840 /* FS base. */
1841 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1842 || fHostInLongMode)
1843 {
1844 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1845 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1846 }
1847
1848 /* GS base. */
1849 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1850 || fHostInLongMode)
1851 {
1852 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1853 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1854 }
1855
1856 /* TR. */
1857 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1858 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1859 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1860 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1861 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1862 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1863 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1869 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1870
1871 /* LDTR (Warning! do not touch the base and limits here). */
1872 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1873 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1874 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1875 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1876
1877 /* GDTR. */
1878 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1879 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1880 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1881
1882 /* IDTR.*/
1883 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1884 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1885 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1886}
1887
1888
1889/**
1890 * Checks host PDPTes as part of VM-exit.
1891 *
1892 * @param pVCpu The cross context virtual CPU structure.
1893 * @param uExitReason The VM-exit reason (for logging purposes).
1894 */
1895IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
1896{
1897 /*
1898 * Check host PDPTEs.
1899 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1900 */
1901 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1902 const char *const pszFailure = "VMX-abort";
1903 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1904
1905 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1906 && !fHostInLongMode)
1907 {
1908 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1909 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1910 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1911 if (RT_SUCCESS(rc))
1912 {
1913 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1914 {
1915 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1916 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1917 { /* likely */ }
1918 else
1919 {
1920 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1921 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1922 }
1923 }
1924 }
1925 else
1926 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1927 }
1928
1929 NOREF(pszFailure);
1930 NOREF(uExitReason);
1931 return VINF_SUCCESS;
1932}
1933
1934
1935/**
1936 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1937 *
1938 * @returns VBox status code.
1939 * @param pVCpu The cross context virtual CPU structure.
1940 * @param pszInstr The VMX instruction name (for logging purposes).
1941 */
1942IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1943{
1944 /*
1945 * Load host MSRs.
1946 * See Intel spec. 27.6 "Loading MSRs".
1947 */
1948 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1949 const char *const pszFailure = "VMX-abort";
1950
1951 /*
1952 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1953 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1954 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1955 */
1956 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1957 if (!cMsrs)
1958 return VINF_SUCCESS;
1959
1960 /*
1961 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1962 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1963 * implementation causes a VMX-abort followed by a triple-fault.
1964 */
1965 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1966 if (fIsMsrCountValid)
1967 { /* likely */ }
1968 else
1969 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1970
1971 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1972 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1973 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1974 if (RT_SUCCESS(rc))
1975 {
1976 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1977 Assert(pMsr);
1978 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1979 {
1980 if ( !pMsr->u32Reserved
1981 && pMsr->u32Msr != MSR_K8_FS_BASE
1982 && pMsr->u32Msr != MSR_K8_GS_BASE
1983 && pMsr->u32Msr != MSR_K6_EFER
1984 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1985 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1986 {
1987 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1988 if (rcStrict == VINF_SUCCESS)
1989 continue;
1990
1991 /*
1992 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1993 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1994 * recording the MSR index in the auxiliary info. field and indicated further by our
1995 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1996 * if possible, or come up with a better, generic solution.
1997 */
1998 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1999 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2000 ? kVmxVDiag_Vmexit_MsrLoadRing3
2001 : kVmxVDiag_Vmexit_MsrLoad;
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2003 }
2004 else
2005 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2006 }
2007 }
2008 else
2009 {
2010 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2011 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2012 }
2013
2014 NOREF(uExitReason);
2015 NOREF(pszFailure);
2016 return VINF_SUCCESS;
2017}
2018
2019
2020/**
2021 * Loads the host state as part of VM-exit.
2022 *
2023 * @returns Strict VBox status code.
2024 * @param pVCpu The cross context virtual CPU structure.
2025 * @param uExitReason The VM-exit reason (for logging purposes).
2026 */
2027IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2028{
2029 /*
2030 * Load host state.
2031 * See Intel spec. 27.5 "Loading Host State".
2032 */
2033 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2034 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2035
2036 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2037 if ( CPUMIsGuestInLongMode(pVCpu)
2038 && !fHostInLongMode)
2039 {
2040 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2041 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2042 }
2043
2044 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2045 iemVmxVmexitLoadHostSegRegs(pVCpu);
2046
2047 /*
2048 * Load host RIP, RSP and RFLAGS.
2049 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2050 */
2051 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2052 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2053 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2054
2055 /* Clear address range monitoring. */
2056 EMMonitorWaitClear(pVCpu);
2057
2058 /* Perform the VMX transition (PGM updates). */
2059 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2060 if (rcStrict == VINF_SUCCESS)
2061 {
2062 /* Check host PDPTEs (only when we've fully switched page tables_. */
2063 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2064 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2065 if (RT_FAILURE(rc))
2066 {
2067 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2068 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2069 }
2070 }
2071 else if (RT_SUCCESS(rcStrict))
2072 {
2073 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2074 uExitReason));
2075 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2076 }
2077 else
2078 {
2079 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2080 return VBOXSTRICTRC_VAL(rcStrict);
2081 }
2082
2083 Assert(rcStrict == VINF_SUCCESS);
2084
2085 /* Load MSRs from the VM-exit auto-load MSR area. */
2086 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2087 if (RT_FAILURE(rc))
2088 {
2089 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2090 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2091 }
2092 return VINF_SUCCESS;
2093}
2094
2095
2096/**
2097 * Gets VM-exit instruction information along with any displacement for an
2098 * instruction VM-exit.
2099 *
2100 * @returns The VM-exit instruction information.
2101 * @param pVCpu The cross context virtual CPU structure.
2102 * @param uExitReason The VM-exit reason.
2103 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2104 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2105 * NULL.
2106 */
2107IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2108{
2109 RTGCPTR GCPtrDisp;
2110 VMXEXITINSTRINFO ExitInstrInfo;
2111 ExitInstrInfo.u = 0;
2112
2113 /*
2114 * Get and parse the ModR/M byte from our decoded opcodes.
2115 */
2116 uint8_t bRm;
2117 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2118 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2119 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2120 {
2121 /*
2122 * ModR/M indicates register addressing.
2123 *
2124 * The primary/secondary register operands are reported in the iReg1 or iReg2
2125 * fields depending on whether it is a read/write form.
2126 */
2127 uint8_t idxReg1;
2128 uint8_t idxReg2;
2129 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2130 {
2131 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2132 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2133 }
2134 else
2135 {
2136 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2137 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2138 }
2139 ExitInstrInfo.All.u2Scaling = 0;
2140 ExitInstrInfo.All.iReg1 = idxReg1;
2141 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2142 ExitInstrInfo.All.fIsRegOperand = 1;
2143 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2144 ExitInstrInfo.All.iSegReg = 0;
2145 ExitInstrInfo.All.iIdxReg = 0;
2146 ExitInstrInfo.All.fIdxRegInvalid = 1;
2147 ExitInstrInfo.All.iBaseReg = 0;
2148 ExitInstrInfo.All.fBaseRegInvalid = 1;
2149 ExitInstrInfo.All.iReg2 = idxReg2;
2150
2151 /* Displacement not applicable for register addressing. */
2152 GCPtrDisp = 0;
2153 }
2154 else
2155 {
2156 /*
2157 * ModR/M indicates memory addressing.
2158 */
2159 uint8_t uScale = 0;
2160 bool fBaseRegValid = false;
2161 bool fIdxRegValid = false;
2162 uint8_t iBaseReg = 0;
2163 uint8_t iIdxReg = 0;
2164 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2165 {
2166 /*
2167 * Parse the ModR/M, displacement for 16-bit addressing mode.
2168 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2169 */
2170 uint16_t u16Disp = 0;
2171 uint8_t const offDisp = offModRm + sizeof(bRm);
2172 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2173 {
2174 /* Displacement without any registers. */
2175 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2176 }
2177 else
2178 {
2179 /* Register (index and base). */
2180 switch (bRm & X86_MODRM_RM_MASK)
2181 {
2182 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2183 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2184 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2185 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2186 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2187 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2188 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2189 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2190 }
2191
2192 /* Register + displacement. */
2193 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2194 {
2195 case 0: break;
2196 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2197 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2198 default:
2199 {
2200 /* Register addressing, handled at the beginning. */
2201 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2202 break;
2203 }
2204 }
2205 }
2206
2207 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2208 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2209 }
2210 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2211 {
2212 /*
2213 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2214 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2215 */
2216 uint32_t u32Disp = 0;
2217 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2218 {
2219 /* Displacement without any registers. */
2220 uint8_t const offDisp = offModRm + sizeof(bRm);
2221 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2222 }
2223 else
2224 {
2225 /* Register (and perhaps scale, index and base). */
2226 uint8_t offDisp = offModRm + sizeof(bRm);
2227 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2228 if (iBaseReg == 4)
2229 {
2230 /* An SIB byte follows the ModR/M byte, parse it. */
2231 uint8_t bSib;
2232 uint8_t const offSib = offModRm + sizeof(bRm);
2233 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2234
2235 /* A displacement may follow SIB, update its offset. */
2236 offDisp += sizeof(bSib);
2237
2238 /* Get the scale. */
2239 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2240
2241 /* Get the index register. */
2242 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2243 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2244
2245 /* Get the base register. */
2246 iBaseReg = bSib & X86_SIB_BASE_MASK;
2247 fBaseRegValid = true;
2248 if (iBaseReg == 5)
2249 {
2250 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2251 {
2252 /* Mod is 0 implies a 32-bit displacement with no base. */
2253 fBaseRegValid = false;
2254 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2255 }
2256 else
2257 {
2258 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2259 iBaseReg = X86_GREG_xBP;
2260 }
2261 }
2262 }
2263
2264 /* Register + displacement. */
2265 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2266 {
2267 case 0: /* Handled above */ break;
2268 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2269 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2270 default:
2271 {
2272 /* Register addressing, handled at the beginning. */
2273 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2274 break;
2275 }
2276 }
2277 }
2278
2279 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2280 }
2281 else
2282 {
2283 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2284
2285 /*
2286 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2287 * See Intel instruction spec. 2.2 "IA-32e Mode".
2288 */
2289 uint64_t u64Disp = 0;
2290 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2291 if (fRipRelativeAddr)
2292 {
2293 /*
2294 * RIP-relative addressing mode.
2295 *
2296 * The displacement is 32-bit signed implying an offset range of +/-2G.
2297 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2298 */
2299 uint8_t const offDisp = offModRm + sizeof(bRm);
2300 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2301 }
2302 else
2303 {
2304 uint8_t offDisp = offModRm + sizeof(bRm);
2305
2306 /*
2307 * Register (and perhaps scale, index and base).
2308 *
2309 * REX.B extends the most-significant bit of the base register. However, REX.B
2310 * is ignored while determining whether an SIB follows the opcode. Hence, we
2311 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2312 *
2313 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2314 */
2315 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2316 if (iBaseReg == 4)
2317 {
2318 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2319 uint8_t bSib;
2320 uint8_t const offSib = offModRm + sizeof(bRm);
2321 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2322
2323 /* Displacement may follow SIB, update its offset. */
2324 offDisp += sizeof(bSib);
2325
2326 /* Get the scale. */
2327 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2328
2329 /* Get the index. */
2330 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2331 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2332
2333 /* Get the base. */
2334 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2335 fBaseRegValid = true;
2336 if (iBaseReg == 5)
2337 {
2338 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2339 {
2340 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2341 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2342 }
2343 else
2344 {
2345 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2346 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2347 }
2348 }
2349 }
2350 iBaseReg |= pVCpu->iem.s.uRexB;
2351
2352 /* Register + displacement. */
2353 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2354 {
2355 case 0: /* Handled above */ break;
2356 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2357 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2358 default:
2359 {
2360 /* Register addressing, handled at the beginning. */
2361 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2362 break;
2363 }
2364 }
2365 }
2366
2367 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2368 }
2369
2370 /*
2371 * The primary or secondary register operand is reported in iReg2 depending
2372 * on whether the primary operand is in read/write form.
2373 */
2374 uint8_t idxReg2;
2375 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2376 {
2377 idxReg2 = bRm & X86_MODRM_RM_MASK;
2378 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2379 idxReg2 |= pVCpu->iem.s.uRexB;
2380 }
2381 else
2382 {
2383 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2384 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2385 idxReg2 |= pVCpu->iem.s.uRexReg;
2386 }
2387 ExitInstrInfo.All.u2Scaling = uScale;
2388 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2389 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2390 ExitInstrInfo.All.fIsRegOperand = 0;
2391 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2392 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2393 ExitInstrInfo.All.iIdxReg = iIdxReg;
2394 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2395 ExitInstrInfo.All.iBaseReg = iBaseReg;
2396 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2397 ExitInstrInfo.All.iReg2 = idxReg2;
2398 }
2399
2400 /*
2401 * Handle exceptions to the norm for certain instructions.
2402 * (e.g. some instructions convey an instruction identity in place of iReg2).
2403 */
2404 switch (uExitReason)
2405 {
2406 case VMX_EXIT_GDTR_IDTR_ACCESS:
2407 {
2408 Assert(VMXINSTRID_IS_VALID(uInstrId));
2409 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2410 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2411 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2412 break;
2413 }
2414
2415 case VMX_EXIT_LDTR_TR_ACCESS:
2416 {
2417 Assert(VMXINSTRID_IS_VALID(uInstrId));
2418 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2419 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2420 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2421 break;
2422 }
2423
2424 case VMX_EXIT_RDRAND:
2425 case VMX_EXIT_RDSEED:
2426 {
2427 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2428 break;
2429 }
2430 }
2431
2432 /* Update displacement and return the constructed VM-exit instruction information field. */
2433 if (pGCPtrDisp)
2434 *pGCPtrDisp = GCPtrDisp;
2435
2436 return ExitInstrInfo.u;
2437}
2438
2439
2440/**
2441 * VMX VM-exit handler.
2442 *
2443 * @returns Strict VBox status code.
2444 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2445 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2446 * triple-fault.
2447 *
2448 * @param pVCpu The cross context virtual CPU structure.
2449 * @param uExitReason The VM-exit reason.
2450 * @param u64ExitQual The Exit qualification.
2451 */
2452IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2453{
2454# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2455 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2456 return VINF_EM_RAW_EMULATE_INSTR;
2457# else
2458 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2459 Assert(pVmcs);
2460
2461 /*
2462 * Import all the guest-CPU state.
2463 *
2464 * HM on returning to guest execution would have to reset up a whole lot of state
2465 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2466 * the state and flag reloading the entire state on re-entry. So import the entire
2467 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2468 */
2469 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2470
2471 /* Ensure VM-entry interruption information valid bit isn't set. */
2472 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2473
2474 /*
2475 * Update the VM-exit reason and Exit qualification.
2476 * Other VMCS read-only data fields are expected to be updated by the caller already.
2477 */
2478 pVmcs->u32RoExitReason = uExitReason;
2479 pVmcs->u64RoExitQual.u = u64ExitQual;
2480 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2481 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2482
2483 /*
2484 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2485 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2486 */
2487 {
2488 uint8_t uVector;
2489 uint32_t fFlags;
2490 uint32_t uErrCode;
2491 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2492 if (fInEventDelivery)
2493 {
2494 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2495 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2496 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2497 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2498 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2499 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2500 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2501 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2502 }
2503 }
2504
2505 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2506 Assert(pVmcs->u64RoIoRcx.u == 0);
2507 Assert(pVmcs->u64RoIoRsi.u == 0);
2508 Assert(pVmcs->u64RoIoRdi.u == 0);
2509 Assert(pVmcs->u64RoIoRip.u == 0);
2510
2511 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2512 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2513 {
2514 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2515 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2516 }
2517
2518 /*
2519 * Save the guest state back into the VMCS.
2520 * We only need to save the state when the VM-entry was successful.
2521 */
2522 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2523 if (!fVmentryFailed)
2524 {
2525 /*
2526 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2527 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2528 *
2529 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2530 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2531 * as guest-CPU state would not been modified. Hence for now, we do this only when
2532 * the VM-entry succeeded.
2533 */
2534 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2535 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2536 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2537 {
2538 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2539 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2540 else
2541 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2542 }
2543
2544 /*
2545 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2546 * occurs in enclave mode/SMM which we don't support yet.
2547 *
2548 * If we ever add support for it, we can pass just the lower bits to the functions
2549 * below, till then an assert should suffice.
2550 */
2551 Assert(!RT_HI_U16(uExitReason));
2552
2553 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2554 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2555 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2556 if (RT_SUCCESS(rc))
2557 { /* likely */ }
2558 else
2559 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2560
2561 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2562 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2563 }
2564 else
2565 {
2566 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2567 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2568 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2569 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2570 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2571 }
2572
2573 /*
2574 * Clear any pending VMX nested-guest force-flags.
2575 * These force-flags have no effect on guest execution and will
2576 * be re-evaluated and setup on the next nested-guest VM-entry.
2577 */
2578 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2579 | VMCPU_FF_VMX_MTF
2580 | VMCPU_FF_VMX_APIC_WRITE
2581 | VMCPU_FF_VMX_INT_WINDOW
2582 | VMCPU_FF_VMX_NMI_WINDOW);
2583
2584 /* Restore the host (outer guest) state. */
2585 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2586 if (RT_SUCCESS(rcStrict))
2587 {
2588 Assert(rcStrict == VINF_SUCCESS);
2589 rcStrict = VINF_VMX_VMEXIT;
2590 }
2591 else
2592 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2593
2594 /* Notify HM that we've completed the VM-exit. */
2595 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2596
2597 /* We're no longer in nested-guest execution mode. */
2598 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2599
2600# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2601 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2602 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2603 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2604 if (rcSched != VINF_SUCCESS)
2605 iemSetPassUpStatus(pVCpu, rcSched);
2606# endif
2607 return rcStrict;
2608# endif
2609}
2610
2611
2612/**
2613 * VMX VM-exit handler for VM-exits due to instruction execution.
2614 *
2615 * This is intended for instructions where the caller provides all the relevant
2616 * VM-exit information.
2617 *
2618 * @returns Strict VBox status code.
2619 * @param pVCpu The cross context virtual CPU structure.
2620 * @param pExitInfo Pointer to the VM-exit information.
2621 */
2622IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2623{
2624 /*
2625 * For instructions where any of the following fields are not applicable:
2626 * - Exit qualification must be cleared.
2627 * - VM-exit instruction info. is undefined.
2628 * - Guest-linear address is undefined.
2629 * - Guest-physical address is undefined.
2630 *
2631 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2632 * instruction execution. For VM-exits that are not due to instruction execution this
2633 * field is undefined.
2634 *
2635 * In our implementation in IEM, all undefined fields are generally cleared. However,
2636 * if the caller supplies information (from say the physical CPU directly) it is
2637 * then possible that the undefined fields are not cleared.
2638 *
2639 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2640 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2641 */
2642 Assert(pExitInfo);
2643 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2644 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2645 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2646
2647 /* Update all the relevant fields from the VM-exit instruction information struct. */
2648 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2649 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2650 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2651 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2652
2653 /* Perform the VM-exit. */
2654 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2655}
2656
2657
2658/**
2659 * VMX VM-exit handler for VM-exits due to instruction execution.
2660 *
2661 * This is intended for instructions that only provide the VM-exit instruction
2662 * length.
2663 *
2664 * @param pVCpu The cross context virtual CPU structure.
2665 * @param uExitReason The VM-exit reason.
2666 * @param cbInstr The instruction length in bytes.
2667 */
2668IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2669{
2670 VMXVEXITINFO ExitInfo;
2671 RT_ZERO(ExitInfo);
2672 ExitInfo.uReason = uExitReason;
2673 ExitInfo.cbInstr = cbInstr;
2674
2675#ifdef VBOX_STRICT
2676 /*
2677 * To prevent us from shooting ourselves in the foot.
2678 * The follow instructions should convey more than just the instruction length.
2679 */
2680 switch (uExitReason)
2681 {
2682 case VMX_EXIT_INVEPT:
2683 case VMX_EXIT_INVPCID:
2684 case VMX_EXIT_INVVPID:
2685 case VMX_EXIT_LDTR_TR_ACCESS:
2686 case VMX_EXIT_GDTR_IDTR_ACCESS:
2687 case VMX_EXIT_VMCLEAR:
2688 case VMX_EXIT_VMPTRLD:
2689 case VMX_EXIT_VMPTRST:
2690 case VMX_EXIT_VMREAD:
2691 case VMX_EXIT_VMWRITE:
2692 case VMX_EXIT_VMXON:
2693 case VMX_EXIT_XRSTORS:
2694 case VMX_EXIT_XSAVES:
2695 case VMX_EXIT_RDRAND:
2696 case VMX_EXIT_RDSEED:
2697 case VMX_EXIT_IO_INSTR:
2698 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2699 break;
2700 }
2701#endif
2702
2703 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2704}
2705
2706
2707/**
2708 * VMX VM-exit handler for VM-exits due to instruction execution.
2709 *
2710 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2711 * instruction information and Exit qualification fields.
2712 *
2713 * @param pVCpu The cross context virtual CPU structure.
2714 * @param uExitReason The VM-exit reason.
2715 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2716 * @param cbInstr The instruction length in bytes.
2717 *
2718 * @remarks Do not use this for INS/OUTS instruction.
2719 */
2720IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2721{
2722 VMXVEXITINFO ExitInfo;
2723 RT_ZERO(ExitInfo);
2724 ExitInfo.uReason = uExitReason;
2725 ExitInfo.cbInstr = cbInstr;
2726
2727 /*
2728 * Update the Exit qualification field with displacement bytes.
2729 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2730 */
2731 switch (uExitReason)
2732 {
2733 case VMX_EXIT_INVEPT:
2734 case VMX_EXIT_INVPCID:
2735 case VMX_EXIT_INVVPID:
2736 case VMX_EXIT_LDTR_TR_ACCESS:
2737 case VMX_EXIT_GDTR_IDTR_ACCESS:
2738 case VMX_EXIT_VMCLEAR:
2739 case VMX_EXIT_VMPTRLD:
2740 case VMX_EXIT_VMPTRST:
2741 case VMX_EXIT_VMREAD:
2742 case VMX_EXIT_VMWRITE:
2743 case VMX_EXIT_VMXON:
2744 case VMX_EXIT_XRSTORS:
2745 case VMX_EXIT_XSAVES:
2746 case VMX_EXIT_RDRAND:
2747 case VMX_EXIT_RDSEED:
2748 {
2749 /* Construct the VM-exit instruction information. */
2750 RTGCPTR GCPtrDisp;
2751 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2752
2753 /* Update the VM-exit instruction information. */
2754 ExitInfo.InstrInfo.u = uInstrInfo;
2755
2756 /* Update the Exit qualification. */
2757 ExitInfo.u64Qual = GCPtrDisp;
2758 break;
2759 }
2760
2761 default:
2762 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2763 break;
2764 }
2765
2766 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2767}
2768
2769
2770/**
2771 * VMX VM-exit handler for VM-exits due to INVLPG.
2772 *
2773 * @returns Strict VBox status code.
2774 * @param pVCpu The cross context virtual CPU structure.
2775 * @param GCPtrPage The guest-linear address of the page being invalidated.
2776 * @param cbInstr The instruction length in bytes.
2777 */
2778IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2779{
2780 VMXVEXITINFO ExitInfo;
2781 RT_ZERO(ExitInfo);
2782 ExitInfo.uReason = VMX_EXIT_INVLPG;
2783 ExitInfo.cbInstr = cbInstr;
2784 ExitInfo.u64Qual = GCPtrPage;
2785 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2786
2787 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2788}
2789
2790
2791/**
2792 * VMX VM-exit handler for VM-exits due to LMSW.
2793 *
2794 * @returns Strict VBox status code.
2795 * @param pVCpu The cross context virtual CPU structure.
2796 * @param uGuestCr0 The current guest CR0.
2797 * @param pu16NewMsw The machine-status word specified in LMSW's source
2798 * operand. This will be updated depending on the VMX
2799 * guest/host CR0 mask if LMSW is not intercepted.
2800 * @param GCPtrEffDst The guest-linear address of the source operand in case
2801 * of a memory operand. For register operand, pass
2802 * NIL_RTGCPTR.
2803 * @param cbInstr The instruction length in bytes.
2804 */
2805IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2806 uint8_t cbInstr)
2807{
2808 Assert(pu16NewMsw);
2809
2810 uint16_t const uNewMsw = *pu16NewMsw;
2811 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2812 {
2813 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2814
2815 VMXVEXITINFO ExitInfo;
2816 RT_ZERO(ExitInfo);
2817 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2818 ExitInfo.cbInstr = cbInstr;
2819
2820 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2821 if (fMemOperand)
2822 {
2823 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2824 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2825 }
2826
2827 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2828 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2829 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2830 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2831
2832 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2833 }
2834
2835 /*
2836 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2837 * CR0 guest/host mask must be left unmodified.
2838 *
2839 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2840 */
2841 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2842 Assert(pVmcs);
2843 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2844 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2845 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2846
2847 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2848}
2849
2850
2851/**
2852 * VMX VM-exit handler for VM-exits due to CLTS.
2853 *
2854 * @returns Strict VBox status code.
2855 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2856 * VM-exit but must not modify the guest CR0.TS bit.
2857 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2858 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2859 * CR0 fixed bits in VMX operation).
2860 * @param pVCpu The cross context virtual CPU structure.
2861 * @param cbInstr The instruction length in bytes.
2862 */
2863IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
2864{
2865 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2866 Assert(pVmcs);
2867
2868 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2869 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2870
2871 /*
2872 * If CR0.TS is owned by the host:
2873 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2874 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2875 * CLTS instruction completes without clearing CR0.TS.
2876 *
2877 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2878 */
2879 if (fGstHostMask & X86_CR0_TS)
2880 {
2881 if (fReadShadow & X86_CR0_TS)
2882 {
2883 Log2(("clts: Guest intercept -> VM-exit\n"));
2884
2885 VMXVEXITINFO ExitInfo;
2886 RT_ZERO(ExitInfo);
2887 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2888 ExitInfo.cbInstr = cbInstr;
2889 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2890 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2891 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2892 }
2893
2894 return VINF_VMX_MODIFIES_BEHAVIOR;
2895 }
2896
2897 /*
2898 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2899 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2900 */
2901 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2902}
2903
2904
2905/**
2906 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2907 * (CR0/CR4 write).
2908 *
2909 * @returns Strict VBox status code.
2910 * @param pVCpu The cross context virtual CPU structure.
2911 * @param iCrReg The control register (either CR0 or CR4).
2912 * @param uGuestCrX The current guest CR0/CR4.
2913 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
2914 * if no VM-exit is caused.
2915 * @param iGReg The general register from which the CR0/CR4 value is
2916 * being loaded.
2917 * @param cbInstr The instruction length in bytes.
2918 */
2919IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2920 uint8_t cbInstr)
2921{
2922 Assert(puNewCrX);
2923 Assert(iCrReg == 0 || iCrReg == 4);
2924 Assert(iGReg < X86_GREG_COUNT);
2925
2926 uint64_t const uNewCrX = *puNewCrX;
2927 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2928 {
2929 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2930
2931 VMXVEXITINFO ExitInfo;
2932 RT_ZERO(ExitInfo);
2933 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2934 ExitInfo.cbInstr = cbInstr;
2935 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2936 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2937 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2938 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2939 }
2940
2941 /*
2942 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2943 * must not be modified the instruction.
2944 *
2945 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2946 */
2947 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2948 Assert(pVmcs);
2949 uint64_t uGuestCrX;
2950 uint64_t fGstHostMask;
2951 if (iCrReg == 0)
2952 {
2953 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2954 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2955 fGstHostMask = pVmcs->u64Cr0Mask.u;
2956 }
2957 else
2958 {
2959 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2960 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2961 fGstHostMask = pVmcs->u64Cr4Mask.u;
2962 }
2963
2964 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2965 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2966}
2967
2968
2969/**
2970 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2971 *
2972 * @returns VBox strict status code.
2973 * @param pVCpu The cross context virtual CPU structure.
2974 * @param iGReg The general register to which the CR3 value is being stored.
2975 * @param cbInstr The instruction length in bytes.
2976 */
2977IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
2978{
2979 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2980 Assert(pVmcs);
2981 Assert(iGReg < X86_GREG_COUNT);
2982 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2983
2984 /*
2985 * If the CR3-store exiting control is set, we must cause a VM-exit.
2986 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2987 */
2988 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2989 {
2990 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2991
2992 VMXVEXITINFO ExitInfo;
2993 RT_ZERO(ExitInfo);
2994 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2995 ExitInfo.cbInstr = cbInstr;
2996 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2998 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2999 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3000 }
3001
3002 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3003}
3004
3005
3006/**
3007 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3008 *
3009 * @returns VBox strict status code.
3010 * @param pVCpu The cross context virtual CPU structure.
3011 * @param uNewCr3 The new CR3 value.
3012 * @param iGReg The general register from which the CR3 value is being
3013 * loaded.
3014 * @param cbInstr The instruction length in bytes.
3015 */
3016IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3017{
3018 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3019 Assert(pVmcs);
3020 Assert(iGReg < X86_GREG_COUNT);
3021
3022 /*
3023 * If the CR3-load exiting control is set and the new CR3 value does not
3024 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3025 *
3026 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3027 */
3028 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3029 {
3030 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3031 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3032
3033 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3034 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3035 if (!fIntercept)
3036 {
3037 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3038 {
3039 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3040 if (uNewCr3 != uCr3TargetValue)
3041 {
3042 fIntercept = true;
3043 break;
3044 }
3045 }
3046 }
3047
3048 if (fIntercept)
3049 {
3050 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3051
3052 VMXVEXITINFO ExitInfo;
3053 RT_ZERO(ExitInfo);
3054 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3055 ExitInfo.cbInstr = cbInstr;
3056 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3058 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3059 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3060 }
3061 }
3062
3063 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3064}
3065
3066
3067/**
3068 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3069 *
3070 * @returns VBox strict status code.
3071 * @param pVCpu The cross context virtual CPU structure.
3072 * @param iGReg The general register to which the CR8 value is being stored.
3073 * @param cbInstr The instruction length in bytes.
3074 */
3075IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3076{
3077 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3078 Assert(pVmcs);
3079 Assert(iGReg < X86_GREG_COUNT);
3080
3081 /*
3082 * If the CR8-store exiting control is set, we must cause a VM-exit.
3083 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3084 */
3085 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3086 {
3087 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3088
3089 VMXVEXITINFO ExitInfo;
3090 RT_ZERO(ExitInfo);
3091 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3092 ExitInfo.cbInstr = cbInstr;
3093 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3094 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3095 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3096 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3097 }
3098
3099 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3100}
3101
3102
3103/**
3104 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3105 *
3106 * @returns VBox strict status code.
3107 * @param pVCpu The cross context virtual CPU structure.
3108 * @param iGReg The general register from which the CR8 value is being
3109 * loaded.
3110 * @param cbInstr The instruction length in bytes.
3111 */
3112IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3113{
3114 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3115 Assert(pVmcs);
3116 Assert(iGReg < X86_GREG_COUNT);
3117
3118 /*
3119 * If the CR8-load exiting control is set, we must cause a VM-exit.
3120 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3121 */
3122 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3123 {
3124 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3125
3126 VMXVEXITINFO ExitInfo;
3127 RT_ZERO(ExitInfo);
3128 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3129 ExitInfo.cbInstr = cbInstr;
3130 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3131 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3132 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3133 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3134 }
3135
3136 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3137}
3138
3139
3140/**
3141 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3142 * GReg,DRx' (DRx read).
3143 *
3144 * @returns VBox strict status code.
3145 * @param pVCpu The cross context virtual CPU structure.
3146 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3147 * VMXINSTRID_MOV_FROM_DRX).
3148 * @param iDrReg The debug register being accessed.
3149 * @param iGReg The general register to/from which the DRx value is being
3150 * store/loaded.
3151 * @param cbInstr The instruction length in bytes.
3152 */
3153IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3154 uint8_t cbInstr)
3155{
3156 Assert(iDrReg <= 7);
3157 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3158 Assert(iGReg < X86_GREG_COUNT);
3159
3160 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3161 Assert(pVmcs);
3162
3163 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3164 {
3165 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3166 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3167 VMXVEXITINFO ExitInfo;
3168 RT_ZERO(ExitInfo);
3169 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3170 ExitInfo.cbInstr = cbInstr;
3171 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3173 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3174 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3175 }
3176
3177 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3178}
3179
3180
3181/**
3182 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3183 *
3184 * @returns VBox strict status code.
3185 * @param pVCpu The cross context virtual CPU structure.
3186 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3187 * VMXINSTRID_IO_OUT).
3188 * @param u16Port The I/O port being accessed.
3189 * @param fImm Whether the I/O port was encoded using an immediate operand
3190 * or the implicit DX register.
3191 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3192 * @param cbInstr The instruction length in bytes.
3193 */
3194IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3195 uint8_t cbInstr)
3196{
3197 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3198 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3199
3200 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3201 if (fIntercept)
3202 {
3203 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3204 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3205 VMXVEXITINFO ExitInfo;
3206 RT_ZERO(ExitInfo);
3207 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3208 ExitInfo.cbInstr = cbInstr;
3209 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3210 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3211 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3212 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3213 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3214 }
3215
3216 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3217}
3218
3219
3220/**
3221 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3222 *
3223 * @returns VBox strict status code.
3224 * @param pVCpu The cross context virtual CPU structure.
3225 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3226 * VMXINSTRID_IO_OUTS).
3227 * @param u16Port The I/O port being accessed.
3228 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3229 * @param fRep Whether the instruction has a REP prefix or not.
3230 * @param ExitInstrInfo The VM-exit instruction info. field.
3231 * @param cbInstr The instruction length in bytes.
3232 */
3233IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3234 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3235{
3236 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3237 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3238 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3239 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3240 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3241
3242 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3243 if (fIntercept)
3244 {
3245 /*
3246 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3247 */
3248 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3249 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3250 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3251 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3252 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3253
3254 uint32_t uDirection;
3255 uint64_t uGuestLinearAddr;
3256 if (uInstrId == VMXINSTRID_IO_INS)
3257 {
3258 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3259 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3260 }
3261 else
3262 {
3263 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3264 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3265 }
3266
3267 /*
3268 * If the segment is unusable, the guest-linear address in undefined.
3269 * We shall clear it for consistency.
3270 *
3271 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3272 */
3273 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3274 uGuestLinearAddr = 0;
3275
3276 VMXVEXITINFO ExitInfo;
3277 RT_ZERO(ExitInfo);
3278 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3279 ExitInfo.cbInstr = cbInstr;
3280 ExitInfo.InstrInfo = ExitInstrInfo;
3281 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3282 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3284 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3285 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3286 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3287 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3288 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3289 }
3290
3291 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3292}
3293
3294
3295/**
3296 * VMX VM-exit handler for VM-exits due to MWAIT.
3297 *
3298 * @returns VBox strict status code.
3299 * @param pVCpu The cross context virtual CPU structure.
3300 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3301 * @param cbInstr The instruction length in bytes.
3302 */
3303IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3304{
3305 VMXVEXITINFO ExitInfo;
3306 RT_ZERO(ExitInfo);
3307 ExitInfo.uReason = VMX_EXIT_MWAIT;
3308 ExitInfo.cbInstr = cbInstr;
3309 ExitInfo.u64Qual = fMonitorHwArmed;
3310 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3311}
3312
3313
3314/**
3315 * VMX VM-exit handler for VM-exits due to PAUSE.
3316 *
3317 * @returns VBox strict status code.
3318 * @param pVCpu The cross context virtual CPU structure.
3319 * @param cbInstr The instruction length in bytes.
3320 */
3321IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3322{
3323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3324 Assert(pVmcs);
3325
3326 /*
3327 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3328 * "PAUSE-loop exiting" control.
3329 *
3330 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3331 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3332 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3333 * a VM-exit.
3334 *
3335 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3336 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3337 */
3338 bool fIntercept = false;
3339 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3340 fIntercept = true;
3341 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3342 && pVCpu->iem.s.uCpl == 0)
3343 {
3344 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3345
3346 /*
3347 * A previous-PAUSE-tick value of 0 is used to identify the first time
3348 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3349 * consider this to be the first execution of PAUSE in a loop according
3350 * to the Intel.
3351 *
3352 * All subsequent records for the previous-PAUSE-tick we ensure that it
3353 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3354 */
3355 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3356 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3357 uint64_t const uTick = TMCpuTickGet(pVCpu);
3358 uint32_t const uPleGap = pVmcs->u32PleGap;
3359 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3360 if ( *puPrevPauseTick == 0
3361 || uTick - *puPrevPauseTick > uPleGap)
3362 *puFirstPauseLoopTick = uTick;
3363 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3364 fIntercept = true;
3365
3366 *puPrevPauseTick = uTick | 1;
3367 }
3368
3369 if (fIntercept)
3370 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3371
3372 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3373}
3374
3375
3376/**
3377 * VMX VM-exit handler for VM-exits due to task switches.
3378 *
3379 * @returns VBox strict status code.
3380 * @param pVCpu The cross context virtual CPU structure.
3381 * @param enmTaskSwitch The cause of the task switch.
3382 * @param SelNewTss The selector of the new TSS.
3383 * @param cbInstr The instruction length in bytes.
3384 */
3385IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3386{
3387 /*
3388 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3389 *
3390 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3391 * instruction or delivery of the exception generated by one of these instructions
3392 * lead to a task switch through a task gate in the IDT, we need to provide the
3393 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3394 * leaves the VM-exit instruction length field undefined.
3395 *
3396 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3397 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3398 */
3399 Assert(cbInstr <= 15);
3400
3401 uint8_t uType;
3402 switch (enmTaskSwitch)
3403 {
3404 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3405 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3406 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3407 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3408 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3409 }
3410
3411 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3412 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3413 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3414 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3415}
3416
3417
3418/**
3419 * VMX VM-exit handler for VM-exits due to task switches.
3420 *
3421 * This is intended for task switches where the caller provides all the relevant
3422 * VM-exit information.
3423 *
3424 * @returns VBox strict status code.
3425 * @param pVCpu The cross context virtual CPU structure.
3426 * @param pExitInfo Pointer to the VM-exit information.
3427 * @param pExitEventInfo Pointer to the VM-exit event information.
3428 */
3429IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3430 PCVMXVEXITEVENTINFO pExitEventInfo)
3431{
3432 Assert(pExitInfo);
3433 Assert(pExitEventInfo);
3434
3435 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3436 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3437 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3438
3439 /*
3440 * Figure out if an instruction was the source of the task switch.
3441 *
3442 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3443 * of an event generated by a software interrupt (INT-N), privileged software
3444 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3445 * the instruction length.
3446 */
3447 bool fHasInstrLen;
3448 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3449 {
3450 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3451 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3452 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3453 if (fIdtVectInfoValid)
3454 {
3455 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3456 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3457 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3458
3459 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3460 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3461 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3462 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3463 fHasInstrLen = true;
3464 else
3465 fHasInstrLen = false;
3466 }
3467 else
3468 fHasInstrLen = false;
3469 }
3470 else
3471 {
3472 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3473 fHasInstrLen = true;
3474 }
3475
3476 if (fHasInstrLen)
3477 {
3478 Assert(pExitInfo->cbInstr > 0);
3479 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3480 }
3481 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3482}
3483
3484
3485/**
3486 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3487 *
3488 * @returns VBox strict status code.
3489 * @param pVCpu The cross context virtual CPU structure.
3490 */
3491IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3492{
3493 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3494 Assert(pVmcs);
3495
3496 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3497 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3498 {
3499 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3500 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3501
3502 /*
3503 * Calculate the current VMX-preemption timer value.
3504 * Only if the value has reached zero, we cause the VM-exit.
3505 */
3506 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3507 if (!uPreemptTimer)
3508 {
3509 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3510 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3511 pVmcs->u32PreemptTimer = 0;
3512
3513 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3514 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3515 }
3516 }
3517
3518 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3519}
3520
3521
3522/**
3523 * VMX VM-exit handler for VM-exits due to external interrupts.
3524 *
3525 * @returns VBox strict status code.
3526 * @param pVCpu The cross context virtual CPU structure.
3527 * @param uVector The external interrupt vector (pass 0 if the interrupt
3528 * is still pending since we typically won't know the
3529 * vector).
3530 * @param fIntPending Whether the external interrupt is pending or
3531 * acknowledged in the interrupt controller.
3532 */
3533IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3534{
3535 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3536 Assert(pVmcs);
3537 Assert(fIntPending || uVector == 0);
3538
3539 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3540 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3541 * functions require prior checking of a blanket intercept and which don't.
3542 * It is better for the caller to check a blanket intercept performance wise
3543 * than making a function call. Leaving this as a todo because it is more
3544 * a performance issue. */
3545
3546 /* The VM-exit is subject to "External interrupt exiting" being set. */
3547 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3548 {
3549 if (fIntPending)
3550 {
3551 /*
3552 * If the interrupt is pending and we don't need to acknowledge the
3553 * interrupt on VM-exit, cause the VM-exit immediately.
3554 *
3555 * See Intel spec 25.2 "Other Causes Of VM Exits".
3556 */
3557 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3558 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3559
3560 /*
3561 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3562 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3563 * acknowledged that the interrupt has been consumed.
3564 */
3565 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3566 }
3567
3568 /*
3569 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3570 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3571 * all set, we cause the VM-exit now. We need to record the external interrupt that
3572 * just occurred in the VM-exit interruption information field.
3573 *
3574 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3575 */
3576 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3577 {
3578 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3579 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3580 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3581 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3582 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3583 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3584 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3585 }
3586 }
3587
3588 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3589}
3590
3591
3592/**
3593 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3594 * an event.
3595 *
3596 * @returns VBox strict status code.
3597 * @param pVCpu The cross context virtual CPU structure.
3598 */
3599IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3600{
3601 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3602 Assert(pVmcs);
3603
3604 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3605 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3606 {
3607 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3608 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3609 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3610 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3611 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3612 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3613 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3614 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3615 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3616
3617 /*
3618 * A VM-exit is not considered to occur during event delivery when the original
3619 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3620 * using the exception bitmap).
3621 *
3622 * Therefore, we must clear the original event from the IDT-vectoring fields which
3623 * would've been recorded before causing the VM-exit.
3624 *
3625 * 27.2.3 "Information for VM Exits During Event Delivery"
3626 */
3627 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3628 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3629 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3630 }
3631
3632 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3633}
3634
3635
3636/**
3637 * VMX VM-exit handler for VM-exit due to delivery of an events.
3638 *
3639 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3640 * all the relevant VM-exit information.
3641 *
3642 * @returns VBox strict status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 * @param pExitInfo Pointer to the VM-exit information.
3645 * @param pExitEventInfo Pointer to the VM-exit event information.
3646 */
3647IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3648{
3649 Assert(pExitInfo);
3650 Assert(pExitEventInfo);
3651 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3652
3653 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3654 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3655 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3656 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3657 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3658 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3659}
3660
3661
3662/**
3663 * VMX VM-exit handler for VM-exits due to delivery of an event.
3664 *
3665 * @returns VBox strict status code.
3666 * @param pVCpu The cross context virtual CPU structure.
3667 * @param uVector The interrupt / exception vector.
3668 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3669 * @param uErrCode The error code associated with the event.
3670 * @param uCr2 The CR2 value in case of a \#PF exception.
3671 * @param cbInstr The instruction length in bytes.
3672 */
3673IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3674 uint8_t cbInstr)
3675{
3676 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3677 Assert(pVmcs);
3678
3679 /*
3680 * If the event is being injected as part of VM-entry, it is -not- subject to event
3681 * intercepts in the nested-guest. However, secondary exceptions that occur during
3682 * injection of any event -are- subject to event interception.
3683 *
3684 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3685 */
3686 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3687 {
3688 /*
3689 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3690 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3691 *
3692 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3693 */
3694 if ( uVector == X86_XCPT_NMI
3695 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3696 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3697 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3698 else
3699 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3700
3701 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3702 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3703 }
3704
3705 /*
3706 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3707 * If not, the caller will continue delivery of the external interrupt as it would
3708 * normally. The interrupt is no longer pending in the interrupt controller at this
3709 * point.
3710 */
3711 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3712 {
3713 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3714 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3715 }
3716
3717 /*
3718 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3719 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3720 * interrupts.
3721 */
3722 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3723 bool fIntercept;
3724 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3725 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3726 {
3727 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3728 }
3729 else
3730 {
3731 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3732 fIntercept = false;
3733 }
3734
3735 /*
3736 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3737 * relevant VM-exit information and cause the VM-exit.
3738 */
3739 if (fIntercept)
3740 {
3741 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3742
3743 /* Construct the rest of the event related information fields and cause the VM-exit. */
3744 uint64_t u64ExitQual;
3745 if (uVector == X86_XCPT_PF)
3746 {
3747 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3748 u64ExitQual = uCr2;
3749 }
3750 else if (uVector == X86_XCPT_DB)
3751 {
3752 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3753 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3754 }
3755 else
3756 u64ExitQual = 0;
3757
3758 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3759 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3760 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3761 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3762 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3763 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3764 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3765 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3766 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3767 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3768
3769 /*
3770 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3771 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3772 * length.
3773 */
3774 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3775 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3776 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3777 else
3778 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3779
3780 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3781 }
3782
3783 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3784}
3785
3786
3787/**
3788 * VMX VM-exit handler for VM-exits due to a triple fault.
3789 *
3790 * @returns VBox strict status code.
3791 * @param pVCpu The cross context virtual CPU structure.
3792 */
3793IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3794{
3795 /*
3796 * A VM-exit is not considered to occur during event delivery when the original
3797 * event results in a triple-fault.
3798 *
3799 * Therefore, we must clear the original event from the IDT-vectoring fields which
3800 * would've been recorded before causing the VM-exit.
3801 *
3802 * 27.2.3 "Information for VM Exits During Event Delivery"
3803 */
3804 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3805 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3806
3807 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
3808}
3809
3810
3811/**
3812 * VMX VM-exit handler for APIC accesses.
3813 *
3814 * @param pVCpu The cross context virtual CPU structure.
3815 * @param offAccess The offset of the register being accessed.
3816 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3817 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3818 */
3819IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
3820{
3821 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3822
3823 VMXAPICACCESS enmAccess;
3824 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3825 if (fInEventDelivery)
3826 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3827 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3828 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3829 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3830 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3831 else
3832 enmAccess = VMXAPICACCESS_LINEAR_READ;
3833
3834 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3835 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3836 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3837}
3838
3839
3840/**
3841 * VMX VM-exit handler for APIC accesses.
3842 *
3843 * This is intended for APIC accesses where the caller provides all the
3844 * relevant VM-exit information.
3845 *
3846 * @returns VBox strict status code.
3847 * @param pVCpu The cross context virtual CPU structure.
3848 * @param pExitInfo Pointer to the VM-exit information.
3849 * @param pExitEventInfo Pointer to the VM-exit event information.
3850 */
3851IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3852 PCVMXVEXITEVENTINFO pExitEventInfo)
3853{
3854 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3855 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3856 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3857 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3858 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3859 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3860 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3861}
3862
3863
3864/**
3865 * VMX VM-exit handler for APIC-write VM-exits.
3866 *
3867 * @param pVCpu The cross context virtual CPU structure.
3868 * @param offApic The write to the virtual-APIC page offset that caused this
3869 * VM-exit.
3870 */
3871IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
3872{
3873 Assert(offApic < XAPIC_OFF_END + 4);
3874 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3875 offApic &= UINT16_C(0xfff);
3876 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3877}
3878
3879
3880/**
3881 * Sets virtual-APIC write emulation as pending.
3882 *
3883 * @param pVCpu The cross context virtual CPU structure.
3884 * @param offApic The offset in the virtual-APIC page that was written.
3885 */
3886DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
3887{
3888 Assert(offApic < XAPIC_OFF_END + 4);
3889
3890 /*
3891 * Record the currently updated APIC offset, as we need this later for figuring
3892 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3893 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3894 */
3895 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3896
3897 /*
3898 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3899 * virtualization or APIC-write emulation).
3900 */
3901 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3902 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3903}
3904
3905
3906/**
3907 * Clears any pending virtual-APIC write emulation.
3908 *
3909 * @returns The virtual-APIC offset that was written before clearing it.
3910 * @param pVCpu The cross context virtual CPU structure.
3911 */
3912DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
3913{
3914 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3915 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3916 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3917 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3918 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3919 return offVirtApicWrite;
3920}
3921
3922
3923/**
3924 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3925 *
3926 * @returns The register from the virtual-APIC page.
3927 * @param pVCpu The cross context virtual CPU structure.
3928 * @param offReg The offset of the register being read.
3929 */
3930IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
3931{
3932 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3933 Assert(pVmcs);
3934
3935 uint32_t uReg;
3936 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3937 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3938 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3939 if (RT_FAILURE(rc))
3940 {
3941 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3942 GCPhysVirtApic));
3943 uReg = 0;
3944 }
3945 return uReg;
3946}
3947
3948
3949/**
3950 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3951 *
3952 * @returns The register from the virtual-APIC page.
3953 * @param pVCpu The cross context virtual CPU structure.
3954 * @param offReg The offset of the register being read.
3955 */
3956IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
3957{
3958 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3959 Assert(pVmcs);
3960
3961 uint64_t uReg;
3962 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3963 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3964 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3965 if (RT_FAILURE(rc))
3966 {
3967 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3968 GCPhysVirtApic));
3969 uReg = 0;
3970 }
3971 return uReg;
3972}
3973
3974
3975/**
3976 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3977 *
3978 * @param pVCpu The cross context virtual CPU structure.
3979 * @param offReg The offset of the register being written.
3980 * @param uReg The register value to write.
3981 */
3982IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
3983{
3984 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3985 Assert(pVmcs);
3986 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3987 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3988 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3989 if (RT_FAILURE(rc))
3990 {
3991 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3992 GCPhysVirtApic));
3993 }
3994}
3995
3996
3997/**
3998 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3999 *
4000 * @param pVCpu The cross context virtual CPU structure.
4001 * @param offReg The offset of the register being written.
4002 * @param uReg The register value to write.
4003 */
4004IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4005{
4006 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4007 Assert(pVmcs);
4008 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4009 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4010 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4011 if (RT_FAILURE(rc))
4012 {
4013 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4014 GCPhysVirtApic));
4015 }
4016}
4017
4018
4019/**
4020 * Sets the vector in a virtual-APIC 256-bit sparse register.
4021 *
4022 * @param pVCpu The cross context virtual CPU structure.
4023 * @param offReg The offset of the 256-bit spare register.
4024 * @param uVector The vector to set.
4025 *
4026 * @remarks This is based on our APIC device code.
4027 */
4028IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4029{
4030 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4031 Assert(pVmcs);
4032 uint32_t uReg;
4033 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4034 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4035 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4036 if (RT_SUCCESS(rc))
4037 {
4038 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4039 uReg |= RT_BIT(idxVectorBit);
4040 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4041 if (RT_FAILURE(rc))
4042 {
4043 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4044 uVector, offReg, GCPhysVirtApic));
4045 }
4046 }
4047 else
4048 {
4049 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4050 uVector, offReg, GCPhysVirtApic));
4051 }
4052}
4053
4054
4055/**
4056 * Clears the vector in a virtual-APIC 256-bit sparse register.
4057 *
4058 * @param pVCpu The cross context virtual CPU structure.
4059 * @param offReg The offset of the 256-bit spare register.
4060 * @param uVector The vector to clear.
4061 *
4062 * @remarks This is based on our APIC device code.
4063 */
4064IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4065{
4066 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4067 Assert(pVmcs);
4068 uint32_t uReg;
4069 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4070 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4071 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4072 if (RT_SUCCESS(rc))
4073 {
4074 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4075 uReg &= ~RT_BIT(idxVectorBit);
4076 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4077 if (RT_FAILURE(rc))
4078 {
4079 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4080 uVector, offReg, GCPhysVirtApic));
4081 }
4082 }
4083 else
4084 {
4085 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4086 uVector, offReg, GCPhysVirtApic));
4087 }
4088}
4089
4090
4091/**
4092 * Checks if a memory access to the APIC-access page must causes an APIC-access
4093 * VM-exit.
4094 *
4095 * @param pVCpu The cross context virtual CPU structure.
4096 * @param offAccess The offset of the register being accessed.
4097 * @param cbAccess The size of the access in bytes.
4098 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4099 * IEM_ACCESS_TYPE_WRITE).
4100 *
4101 * @remarks This must not be used for MSR-based APIC-access page accesses!
4102 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4103 */
4104IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4105{
4106 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4107 Assert(pVmcs);
4108 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4109
4110 /*
4111 * We must cause a VM-exit if any of the following are true:
4112 * - TPR shadowing isn't active.
4113 * - The access size exceeds 32-bits.
4114 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4115 *
4116 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4117 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4118 */
4119 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4120 || cbAccess > sizeof(uint32_t)
4121 || ((offAccess + cbAccess - 1) & 0xc)
4122 || offAccess >= XAPIC_OFF_END + 4)
4123 return true;
4124
4125 /*
4126 * If the access is part of an operation where we have already
4127 * virtualized a virtual-APIC write, we must cause a VM-exit.
4128 */
4129 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4130 return true;
4131
4132 /*
4133 * Check write accesses to the APIC-access page that cause VM-exits.
4134 */
4135 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4136 {
4137 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4138 {
4139 /*
4140 * With APIC-register virtualization, a write access to any of the
4141 * following registers are virtualized. Accessing any other register
4142 * causes a VM-exit.
4143 */
4144 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4145 switch (offAlignedAccess)
4146 {
4147 case XAPIC_OFF_ID:
4148 case XAPIC_OFF_TPR:
4149 case XAPIC_OFF_EOI:
4150 case XAPIC_OFF_LDR:
4151 case XAPIC_OFF_DFR:
4152 case XAPIC_OFF_SVR:
4153 case XAPIC_OFF_ESR:
4154 case XAPIC_OFF_ICR_LO:
4155 case XAPIC_OFF_ICR_HI:
4156 case XAPIC_OFF_LVT_TIMER:
4157 case XAPIC_OFF_LVT_THERMAL:
4158 case XAPIC_OFF_LVT_PERF:
4159 case XAPIC_OFF_LVT_LINT0:
4160 case XAPIC_OFF_LVT_LINT1:
4161 case XAPIC_OFF_LVT_ERROR:
4162 case XAPIC_OFF_TIMER_ICR:
4163 case XAPIC_OFF_TIMER_DCR:
4164 break;
4165 default:
4166 return true;
4167 }
4168 }
4169 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4170 {
4171 /*
4172 * With virtual-interrupt delivery, a write access to any of the
4173 * following registers are virtualized. Accessing any other register
4174 * causes a VM-exit.
4175 *
4176 * Note! The specification does not allow writing to offsets in-between
4177 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4178 */
4179 switch (offAccess)
4180 {
4181 case XAPIC_OFF_TPR:
4182 case XAPIC_OFF_EOI:
4183 case XAPIC_OFF_ICR_LO:
4184 break;
4185 default:
4186 return true;
4187 }
4188 }
4189 else
4190 {
4191 /*
4192 * Without APIC-register virtualization or virtual-interrupt delivery,
4193 * only TPR accesses are virtualized.
4194 */
4195 if (offAccess == XAPIC_OFF_TPR)
4196 { /* likely */ }
4197 else
4198 return true;
4199 }
4200 }
4201 else
4202 {
4203 /*
4204 * Check read accesses to the APIC-access page that cause VM-exits.
4205 */
4206 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4207 {
4208 /*
4209 * With APIC-register virtualization, a read access to any of the
4210 * following registers are virtualized. Accessing any other register
4211 * causes a VM-exit.
4212 */
4213 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4214 switch (offAlignedAccess)
4215 {
4216 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4217 case XAPIC_OFF_ID:
4218 case XAPIC_OFF_VERSION:
4219 case XAPIC_OFF_TPR:
4220 case XAPIC_OFF_EOI:
4221 case XAPIC_OFF_LDR:
4222 case XAPIC_OFF_DFR:
4223 case XAPIC_OFF_SVR:
4224 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4225 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4226 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4227 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4228 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4229 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4230 case XAPIC_OFF_ESR:
4231 case XAPIC_OFF_ICR_LO:
4232 case XAPIC_OFF_ICR_HI:
4233 case XAPIC_OFF_LVT_TIMER:
4234 case XAPIC_OFF_LVT_THERMAL:
4235 case XAPIC_OFF_LVT_PERF:
4236 case XAPIC_OFF_LVT_LINT0:
4237 case XAPIC_OFF_LVT_LINT1:
4238 case XAPIC_OFF_LVT_ERROR:
4239 case XAPIC_OFF_TIMER_ICR:
4240 case XAPIC_OFF_TIMER_DCR:
4241 break;
4242 default:
4243 return true;
4244 }
4245 }
4246 else
4247 {
4248 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4249 if (offAccess == XAPIC_OFF_TPR)
4250 { /* likely */ }
4251 else
4252 return true;
4253 }
4254 }
4255
4256 /* The APIC access is virtualized, does not cause a VM-exit. */
4257 return false;
4258}
4259
4260
4261/**
4262 * Virtualizes a memory-based APIC access where the address is not used to access
4263 * memory.
4264 *
4265 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4266 * page-faults but do not use the address to access memory.
4267 *
4268 * @param pVCpu The cross context virtual CPU structure.
4269 * @param pGCPhysAccess Pointer to the guest-physical address used.
4270 */
4271IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4272{
4273 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4274 Assert(pVmcs);
4275 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4276 Assert(pGCPhysAccess);
4277
4278 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4279 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4280 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4281
4282 if (GCPhysAccess == GCPhysApic)
4283 {
4284 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4285 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4286 uint16_t const cbAccess = 1;
4287 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4288 if (fIntercept)
4289 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4290
4291 *pGCPhysAccess = GCPhysApic | offAccess;
4292 return VINF_VMX_MODIFIES_BEHAVIOR;
4293 }
4294
4295 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4296}
4297
4298
4299/**
4300 * Virtualizes a memory-based APIC access.
4301 *
4302 * @returns VBox strict status code.
4303 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4304 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4305 *
4306 * @param pVCpu The cross context virtual CPU structure.
4307 * @param offAccess The offset of the register being accessed (within the
4308 * APIC-access page).
4309 * @param cbAccess The size of the access in bytes.
4310 * @param pvData Pointer to the data being written or where to store the data
4311 * being read.
4312 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4313 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4314 */
4315IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4316 uint32_t fAccess)
4317{
4318 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4319 Assert(pVmcs);
4320 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4321 Assert(pvData);
4322 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4323 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4324 || (fAccess & IEM_ACCESS_INSTRUCTION));
4325
4326 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4327 if (fIntercept)
4328 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4329
4330 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4331 {
4332 /*
4333 * A write access to the APIC-access page that is virtualized (rather than
4334 * causing a VM-exit) writes data to the virtual-APIC page.
4335 */
4336 uint32_t const u32Data = *(uint32_t *)pvData;
4337 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4338
4339 /*
4340 * Record the currently updated APIC offset, as we need this later for figuring
4341 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4342 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4343 *
4344 * After completion of the current operation, we need to perform TPR virtualization,
4345 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4346 *
4347 * The current operation may be a REP-prefixed string instruction, execution of any
4348 * other instruction, or delivery of an event through the IDT.
4349 *
4350 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4351 * performed now but later after completion of the current operation.
4352 *
4353 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4354 */
4355 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4356 }
4357 else
4358 {
4359 /*
4360 * A read access from the APIC-access page that is virtualized (rather than
4361 * causing a VM-exit) returns data from the virtual-APIC page.
4362 *
4363 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4364 */
4365 Assert(cbAccess <= 4);
4366 Assert(offAccess < XAPIC_OFF_END + 4);
4367 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4368
4369 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4370 u32Data &= s_auAccessSizeMasks[cbAccess];
4371 *(uint32_t *)pvData = u32Data;
4372 }
4373
4374 return VINF_VMX_MODIFIES_BEHAVIOR;
4375}
4376
4377
4378/**
4379 * Virtualizes an MSR-based APIC read access.
4380 *
4381 * @returns VBox strict status code.
4382 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4383 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4384 * handled by the x2APIC device.
4385 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4386 * not within the range of valid MSRs, caller must raise \#GP(0).
4387 * @param pVCpu The cross context virtual CPU structure.
4388 * @param idMsr The x2APIC MSR being read.
4389 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4390 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4391 */
4392IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4393{
4394 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4395 Assert(pVmcs);
4396 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4397 Assert(pu64Value);
4398
4399 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4400 {
4401 /*
4402 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4403 * what the end of the valid x2APIC MSR range is. Hence the use of different
4404 * macros here.
4405 *
4406 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4407 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4408 */
4409 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4410 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4411 {
4412 uint16_t const offReg = (idMsr & 0xff) << 4;
4413 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4414 *pu64Value = u64Value;
4415 return VINF_VMX_MODIFIES_BEHAVIOR;
4416 }
4417 return VERR_OUT_OF_RANGE;
4418 }
4419
4420 if (idMsr == MSR_IA32_X2APIC_TPR)
4421 {
4422 uint16_t const offReg = (idMsr & 0xff) << 4;
4423 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4424 *pu64Value = u64Value;
4425 return VINF_VMX_MODIFIES_BEHAVIOR;
4426 }
4427
4428 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4429}
4430
4431
4432/**
4433 * Virtualizes an MSR-based APIC write access.
4434 *
4435 * @returns VBox strict status code.
4436 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4437 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4438 * not within the range of valid MSRs, caller must raise \#GP(0).
4439 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4440 *
4441 * @param pVCpu The cross context virtual CPU structure.
4442 * @param idMsr The x2APIC MSR being written.
4443 * @param u64Value The value of the x2APIC MSR being written.
4444 */
4445IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4446{
4447 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4448 Assert(pVmcs);
4449
4450 /*
4451 * Check if the access is to be virtualized.
4452 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4453 */
4454 if ( idMsr == MSR_IA32_X2APIC_TPR
4455 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4456 && ( idMsr == MSR_IA32_X2APIC_EOI
4457 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4458 {
4459 /* Validate the MSR write depending on the register. */
4460 switch (idMsr)
4461 {
4462 case MSR_IA32_X2APIC_TPR:
4463 case MSR_IA32_X2APIC_SELF_IPI:
4464 {
4465 if (u64Value & UINT64_C(0xffffffffffffff00))
4466 return VERR_OUT_OF_RANGE;
4467 break;
4468 }
4469 case MSR_IA32_X2APIC_EOI:
4470 {
4471 if (u64Value != 0)
4472 return VERR_OUT_OF_RANGE;
4473 break;
4474 }
4475 }
4476
4477 /* Write the MSR to the virtual-APIC page. */
4478 uint16_t const offReg = (idMsr & 0xff) << 4;
4479 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4480
4481 /*
4482 * Record the currently updated APIC offset, as we need this later for figuring
4483 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4484 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4485 */
4486 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4487
4488 return VINF_VMX_MODIFIES_BEHAVIOR;
4489 }
4490
4491 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4492}
4493
4494
4495/**
4496 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4497 *
4498 * @returns VBox status code.
4499 * @retval VINF_SUCCESS when the highest set bit is found.
4500 * @retval VERR_NOT_FOUND when no bit is set.
4501 *
4502 * @param pVCpu The cross context virtual CPU structure.
4503 * @param offReg The offset of the APIC 256-bit sparse register.
4504 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4505 * set in the register. Only valid when VINF_SUCCESS is
4506 * returned.
4507 *
4508 * @remarks The format of the 256-bit sparse register here mirrors that found in
4509 * real APIC hardware.
4510 */
4511static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4512{
4513 Assert(offReg < XAPIC_OFF_END + 4);
4514 Assert(pidxHighestBit);
4515 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4516
4517 /*
4518 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4519 * However, in each fragment only the first 4 bytes are used.
4520 */
4521 uint8_t const cFrags = 8;
4522 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4523 {
4524 uint16_t const offFrag = iFrag * 16;
4525 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4526 if (!u32Frag)
4527 continue;
4528
4529 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4530 Assert(idxHighestBit > 0);
4531 --idxHighestBit;
4532 Assert(idxHighestBit <= UINT8_MAX);
4533 *pidxHighestBit = idxHighestBit;
4534 return VINF_SUCCESS;
4535 }
4536 return VERR_NOT_FOUND;
4537}
4538
4539
4540/**
4541 * Evaluates pending virtual interrupts.
4542 *
4543 * @param pVCpu The cross context virtual CPU structure.
4544 */
4545IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4546{
4547 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4548 Assert(pVmcs);
4549 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4550
4551 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4552 {
4553 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4554 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4555
4556 if ((uRvi >> 4) > (uPpr >> 4))
4557 {
4558 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4559 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4560 }
4561 else
4562 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4563 }
4564}
4565
4566
4567/**
4568 * Performs PPR virtualization.
4569 *
4570 * @returns VBox strict status code.
4571 * @param pVCpu The cross context virtual CPU structure.
4572 */
4573IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4574{
4575 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4576 Assert(pVmcs);
4577 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4578 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4579
4580 /*
4581 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4582 * or EOI-virtualization.
4583 *
4584 * See Intel spec. 29.1.3 "PPR Virtualization".
4585 */
4586 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4587 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4588
4589 uint32_t uPpr;
4590 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4591 uPpr = uTpr & 0xff;
4592 else
4593 uPpr = uSvi & 0xf0;
4594
4595 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4596 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4597}
4598
4599
4600/**
4601 * Performs VMX TPR virtualization.
4602 *
4603 * @returns VBox strict status code.
4604 * @param pVCpu The cross context virtual CPU structure.
4605 */
4606IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4607{
4608 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4609 Assert(pVmcs);
4610 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4611
4612 /*
4613 * We should have already performed the virtual-APIC write to the TPR offset
4614 * in the virtual-APIC page. We now perform TPR virtualization.
4615 *
4616 * See Intel spec. 29.1.2 "TPR Virtualization".
4617 */
4618 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4619 {
4620 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4621 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4622
4623 /*
4624 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4625 * See Intel spec. 29.1.2 "TPR Virtualization".
4626 */
4627 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4628 {
4629 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4630 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4631 }
4632 }
4633 else
4634 {
4635 iemVmxPprVirtualization(pVCpu);
4636 iemVmxEvalPendingVirtIntrs(pVCpu);
4637 }
4638
4639 return VINF_SUCCESS;
4640}
4641
4642
4643/**
4644 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4645 * not.
4646 *
4647 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4648 * @param pVCpu The cross context virtual CPU structure.
4649 * @param uVector The interrupt that was acknowledged using an EOI.
4650 */
4651IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4652{
4653 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4654 Assert(pVmcs);
4655 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4656
4657 if (uVector < 64)
4658 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4659 if (uVector < 128)
4660 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4661 if (uVector < 192)
4662 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4663 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4664}
4665
4666
4667/**
4668 * Performs EOI virtualization.
4669 *
4670 * @returns VBox strict status code.
4671 * @param pVCpu The cross context virtual CPU structure.
4672 */
4673IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4674{
4675 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4676 Assert(pVmcs);
4677 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4678
4679 /*
4680 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4681 * and get the next guest-interrupt that's in-service (if any).
4682 *
4683 * See Intel spec. 29.1.4 "EOI Virtualization".
4684 */
4685 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4686 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4687 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4688
4689 uint8_t uVector = uSvi;
4690 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4691
4692 uVector = 0;
4693 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4694
4695 if (uVector)
4696 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4697 else
4698 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4699
4700 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4701 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4702
4703 iemVmxPprVirtualization(pVCpu);
4704 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4705 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4706 iemVmxEvalPendingVirtIntrs(pVCpu);
4707 return VINF_SUCCESS;
4708}
4709
4710
4711/**
4712 * Performs self-IPI virtualization.
4713 *
4714 * @returns VBox strict status code.
4715 * @param pVCpu The cross context virtual CPU structure.
4716 */
4717IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4718{
4719 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4720 Assert(pVmcs);
4721 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4722
4723 /*
4724 * We should have already performed the virtual-APIC write to the self-IPI offset
4725 * in the virtual-APIC page. We now perform self-IPI virtualization.
4726 *
4727 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4728 */
4729 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4730 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4731 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4732 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4733 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4734 if (uVector > uRvi)
4735 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4736 iemVmxEvalPendingVirtIntrs(pVCpu);
4737 return VINF_SUCCESS;
4738}
4739
4740
4741/**
4742 * Performs VMX APIC-write emulation.
4743 *
4744 * @returns VBox strict status code.
4745 * @param pVCpu The cross context virtual CPU structure.
4746 */
4747IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4748{
4749 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4750 Assert(pVmcs);
4751
4752 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4753 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4754
4755 /*
4756 * Perform APIC-write emulation based on the virtual-APIC register written.
4757 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4758 */
4759 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4760 VBOXSTRICTRC rcStrict;
4761 switch (offApicWrite)
4762 {
4763 case XAPIC_OFF_TPR:
4764 {
4765 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4766 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4767 uTpr &= UINT32_C(0x000000ff);
4768 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4769 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4770 rcStrict = iemVmxTprVirtualization(pVCpu);
4771 break;
4772 }
4773
4774 case XAPIC_OFF_EOI:
4775 {
4776 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4777 {
4778 /* Clear VEOI and perform EOI virtualization. */
4779 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4780 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4781 rcStrict = iemVmxEoiVirtualization(pVCpu);
4782 }
4783 else
4784 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4785 break;
4786 }
4787
4788 case XAPIC_OFF_ICR_LO:
4789 {
4790 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4791 {
4792 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4793 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4794 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4795 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4796 if ( !(uIcrLo & fIcrLoMb0)
4797 && (uIcrLo & fIcrLoMb1))
4798 {
4799 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4800 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4801 }
4802 else
4803 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4804 }
4805 else
4806 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4807 break;
4808 }
4809
4810 case XAPIC_OFF_ICR_HI:
4811 {
4812 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4813 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4814 uIcrHi &= UINT32_C(0xff000000);
4815 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4816 rcStrict = VINF_SUCCESS;
4817 break;
4818 }
4819
4820 default:
4821 {
4822 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4823 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4824 break;
4825 }
4826 }
4827
4828 return rcStrict;
4829}
4830
4831
4832/**
4833 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4834 *
4835 * @param pVCpu The cross context virtual CPU structure.
4836 * @param pszInstr The VMX instruction name (for logging purposes).
4837 */
4838IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
4839{
4840 /*
4841 * Guest Control Registers, Debug Registers, and MSRs.
4842 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4843 */
4844 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4845 const char *const pszFailure = "VM-exit";
4846 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4847
4848 /* CR0 reserved bits. */
4849 {
4850 /* CR0 MB1 bits. */
4851 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4852 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4853 if (fUnrestrictedGuest)
4854 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4855 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4856 { /* likely */ }
4857 else
4858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4859
4860 /* CR0 MBZ bits. */
4861 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4862 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4863 { /* likely */ }
4864 else
4865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4866
4867 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4868 if ( !fUnrestrictedGuest
4869 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4870 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4872 }
4873
4874 /* CR4 reserved bits. */
4875 {
4876 /* CR4 MB1 bits. */
4877 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4878 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4879 { /* likely */ }
4880 else
4881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4882
4883 /* CR4 MBZ bits. */
4884 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4885 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4886 { /* likely */ }
4887 else
4888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4889 }
4890
4891 /* DEBUGCTL MSR. */
4892 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4893 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4894 { /* likely */ }
4895 else
4896 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4897
4898 /* 64-bit CPU checks. */
4899 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4900 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4901 {
4902 if (fGstInLongMode)
4903 {
4904 /* PAE must be set. */
4905 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4906 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4907 { /* likely */ }
4908 else
4909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4910 }
4911 else
4912 {
4913 /* PCIDE should not be set. */
4914 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4915 { /* likely */ }
4916 else
4917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4918 }
4919
4920 /* CR3. */
4921 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4922 { /* likely */ }
4923 else
4924 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4925
4926 /* DR7. */
4927 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4928 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4929 { /* likely */ }
4930 else
4931 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4932
4933 /* SYSENTER ESP and SYSENTER EIP. */
4934 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4935 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4936 { /* likely */ }
4937 else
4938 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4939 }
4940
4941 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4942 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4943
4944 /* PAT MSR. */
4945 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4946 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4947 { /* likely */ }
4948 else
4949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4950
4951 /* EFER MSR. */
4952 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4953 {
4954 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4955 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4956 { /* likely */ }
4957 else
4958 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4959
4960 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4961 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4962 if ( fGstLma == fGstInLongMode
4963 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4964 || fGstLma == fGstLme))
4965 { /* likely */ }
4966 else
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4968 }
4969
4970 /* We don't support IA32_BNDCFGS MSR yet. */
4971 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4972
4973 NOREF(pszInstr);
4974 NOREF(pszFailure);
4975 return VINF_SUCCESS;
4976}
4977
4978
4979/**
4980 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4981 *
4982 * @param pVCpu The cross context virtual CPU structure.
4983 * @param pszInstr The VMX instruction name (for logging purposes).
4984 */
4985IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4986{
4987 /*
4988 * Segment registers.
4989 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4990 */
4991 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4992 const char *const pszFailure = "VM-exit";
4993 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4994 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4995 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4996
4997 /* Selectors. */
4998 if ( !fGstInV86Mode
4999 && !fUnrestrictedGuest
5000 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5001 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5002
5003 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5004 {
5005 CPUMSELREG SelReg;
5006 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5007 if (RT_LIKELY(rc == VINF_SUCCESS))
5008 { /* likely */ }
5009 else
5010 return rc;
5011
5012 /*
5013 * Virtual-8086 mode checks.
5014 */
5015 if (fGstInV86Mode)
5016 {
5017 /* Base address. */
5018 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5019 { /* likely */ }
5020 else
5021 {
5022 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5024 }
5025
5026 /* Limit. */
5027 if (SelReg.u32Limit == 0xffff)
5028 { /* likely */ }
5029 else
5030 {
5031 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5033 }
5034
5035 /* Attribute. */
5036 if (SelReg.Attr.u == 0xf3)
5037 { /* likely */ }
5038 else
5039 {
5040 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5042 }
5043
5044 /* We're done; move to checking the next segment. */
5045 continue;
5046 }
5047
5048 /* Checks done by 64-bit CPUs. */
5049 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5050 {
5051 /* Base address. */
5052 if ( iSegReg == X86_SREG_FS
5053 || iSegReg == X86_SREG_GS)
5054 {
5055 if (X86_IS_CANONICAL(SelReg.u64Base))
5056 { /* likely */ }
5057 else
5058 {
5059 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5061 }
5062 }
5063 else if (iSegReg == X86_SREG_CS)
5064 {
5065 if (!RT_HI_U32(SelReg.u64Base))
5066 { /* likely */ }
5067 else
5068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5069 }
5070 else
5071 {
5072 if ( SelReg.Attr.n.u1Unusable
5073 || !RT_HI_U32(SelReg.u64Base))
5074 { /* likely */ }
5075 else
5076 {
5077 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5079 }
5080 }
5081 }
5082
5083 /*
5084 * Checks outside Virtual-8086 mode.
5085 */
5086 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5087 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5088 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5089 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5090 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5091 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5092 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5093 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5094
5095 /* Code or usable segment. */
5096 if ( iSegReg == X86_SREG_CS
5097 || fUsable)
5098 {
5099 /* Reserved bits (bits 31:17 and bits 11:8). */
5100 if (!(SelReg.Attr.u & 0xfffe0f00))
5101 { /* likely */ }
5102 else
5103 {
5104 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5105 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5106 }
5107
5108 /* Descriptor type. */
5109 if (fCodeDataSeg)
5110 { /* likely */ }
5111 else
5112 {
5113 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5115 }
5116
5117 /* Present. */
5118 if (fPresent)
5119 { /* likely */ }
5120 else
5121 {
5122 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5124 }
5125
5126 /* Granularity. */
5127 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5128 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5129 { /* likely */ }
5130 else
5131 {
5132 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5134 }
5135 }
5136
5137 if (iSegReg == X86_SREG_CS)
5138 {
5139 /* Segment Type and DPL. */
5140 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5141 && fUnrestrictedGuest)
5142 {
5143 if (uDpl == 0)
5144 { /* likely */ }
5145 else
5146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5147 }
5148 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5149 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5150 {
5151 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5152 if (uDpl == AttrSs.n.u2Dpl)
5153 { /* likely */ }
5154 else
5155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5156 }
5157 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5158 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5159 {
5160 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5161 if (uDpl <= AttrSs.n.u2Dpl)
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5165 }
5166 else
5167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5168
5169 /* Def/Big. */
5170 if ( fGstInLongMode
5171 && fSegLong)
5172 {
5173 if (uDefBig == 0)
5174 { /* likely */ }
5175 else
5176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5177 }
5178 }
5179 else if (iSegReg == X86_SREG_SS)
5180 {
5181 /* Segment Type. */
5182 if ( !fUsable
5183 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5184 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5185 { /* likely */ }
5186 else
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5188
5189 /* DPL. */
5190 if (!fUnrestrictedGuest)
5191 {
5192 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5196 }
5197 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5198 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5199 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5200 {
5201 if (uDpl == 0)
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5205 }
5206 }
5207 else
5208 {
5209 /* DS, ES, FS, GS. */
5210 if (fUsable)
5211 {
5212 /* Segment type. */
5213 if (uSegType & X86_SEL_TYPE_ACCESSED)
5214 { /* likely */ }
5215 else
5216 {
5217 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5219 }
5220
5221 if ( !(uSegType & X86_SEL_TYPE_CODE)
5222 || (uSegType & X86_SEL_TYPE_READ))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5226
5227 /* DPL. */
5228 if ( !fUnrestrictedGuest
5229 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5230 {
5231 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5232 { /* likely */ }
5233 else
5234 {
5235 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5237 }
5238 }
5239 }
5240 }
5241 }
5242
5243 /*
5244 * LDTR.
5245 */
5246 {
5247 CPUMSELREG Ldtr;
5248 Ldtr.Sel = pVmcs->GuestLdtr;
5249 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5250 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5251 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5252
5253 if (!Ldtr.Attr.n.u1Unusable)
5254 {
5255 /* Selector. */
5256 if (!(Ldtr.Sel & X86_SEL_LDT))
5257 { /* likely */ }
5258 else
5259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5260
5261 /* Base. */
5262 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5263 {
5264 if (X86_IS_CANONICAL(Ldtr.u64Base))
5265 { /* likely */ }
5266 else
5267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5268 }
5269
5270 /* Attributes. */
5271 /* Reserved bits (bits 31:17 and bits 11:8). */
5272 if (!(Ldtr.Attr.u & 0xfffe0f00))
5273 { /* likely */ }
5274 else
5275 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5276
5277 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5278 { /* likely */ }
5279 else
5280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5281
5282 if (!Ldtr.Attr.n.u1DescType)
5283 { /* likely */ }
5284 else
5285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5286
5287 if (Ldtr.Attr.n.u1Present)
5288 { /* likely */ }
5289 else
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5291
5292 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5293 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5294 { /* likely */ }
5295 else
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5297 }
5298 }
5299
5300 /*
5301 * TR.
5302 */
5303 {
5304 CPUMSELREG Tr;
5305 Tr.Sel = pVmcs->GuestTr;
5306 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5307 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5308 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5309
5310 /* Selector. */
5311 if (!(Tr.Sel & X86_SEL_LDT))
5312 { /* likely */ }
5313 else
5314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5315
5316 /* Base. */
5317 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5318 {
5319 if (X86_IS_CANONICAL(Tr.u64Base))
5320 { /* likely */ }
5321 else
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5323 }
5324
5325 /* Attributes. */
5326 /* Reserved bits (bits 31:17 and bits 11:8). */
5327 if (!(Tr.Attr.u & 0xfffe0f00))
5328 { /* likely */ }
5329 else
5330 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5331
5332 if (!Tr.Attr.n.u1Unusable)
5333 { /* likely */ }
5334 else
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5336
5337 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5338 || ( !fGstInLongMode
5339 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5340 { /* likely */ }
5341 else
5342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5343
5344 if (!Tr.Attr.n.u1DescType)
5345 { /* likely */ }
5346 else
5347 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5348
5349 if (Tr.Attr.n.u1Present)
5350 { /* likely */ }
5351 else
5352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5353
5354 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5355 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5356 { /* likely */ }
5357 else
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5359 }
5360
5361 NOREF(pszInstr);
5362 NOREF(pszFailure);
5363 return VINF_SUCCESS;
5364}
5365
5366
5367/**
5368 * Checks guest GDTR and IDTR as part of VM-entry.
5369 *
5370 * @param pVCpu The cross context virtual CPU structure.
5371 * @param pszInstr The VMX instruction name (for logging purposes).
5372 */
5373IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5374{
5375 /*
5376 * GDTR and IDTR.
5377 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5378 */
5379 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5380 const char *const pszFailure = "VM-exit";
5381
5382 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5383 {
5384 /* Base. */
5385 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5386 { /* likely */ }
5387 else
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5389
5390 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5391 { /* likely */ }
5392 else
5393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5394 }
5395
5396 /* Limit. */
5397 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5398 { /* likely */ }
5399 else
5400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5401
5402 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5403 { /* likely */ }
5404 else
5405 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5406
5407 NOREF(pszInstr);
5408 NOREF(pszFailure);
5409 return VINF_SUCCESS;
5410}
5411
5412
5413/**
5414 * Checks guest RIP and RFLAGS as part of VM-entry.
5415 *
5416 * @param pVCpu The cross context virtual CPU structure.
5417 * @param pszInstr The VMX instruction name (for logging purposes).
5418 */
5419IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5420{
5421 /*
5422 * RIP and RFLAGS.
5423 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5424 */
5425 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5426 const char *const pszFailure = "VM-exit";
5427 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5428
5429 /* RIP. */
5430 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5431 {
5432 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5433 if ( !fGstInLongMode
5434 || !AttrCs.n.u1Long)
5435 {
5436 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5440 }
5441
5442 if ( fGstInLongMode
5443 && AttrCs.n.u1Long)
5444 {
5445 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5446 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5447 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5448 { /* likely */ }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5451 }
5452 }
5453
5454 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5455 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5456 : pVmcs->u64GuestRFlags.s.Lo;
5457 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5458 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5459 { /* likely */ }
5460 else
5461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5462
5463 if ( fGstInLongMode
5464 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5465 {
5466 if (!(uGuestRFlags & X86_EFL_VM))
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5470 }
5471
5472 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5473 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5474 {
5475 if (uGuestRFlags & X86_EFL_IF)
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5479 }
5480
5481 NOREF(pszInstr);
5482 NOREF(pszFailure);
5483 return VINF_SUCCESS;
5484}
5485
5486
5487/**
5488 * Checks guest non-register state as part of VM-entry.
5489 *
5490 * @param pVCpu The cross context virtual CPU structure.
5491 * @param pszInstr The VMX instruction name (for logging purposes).
5492 */
5493IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5494{
5495 /*
5496 * Guest non-register state.
5497 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5498 */
5499 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5500 const char *const pszFailure = "VM-exit";
5501
5502 /*
5503 * Activity state.
5504 */
5505 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5506 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5507 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5508 { /* likely */ }
5509 else
5510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5511
5512 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5513 if ( !AttrSs.n.u2Dpl
5514 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5515 { /* likely */ }
5516 else
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5518
5519 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5520 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5521 {
5522 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5526 }
5527
5528 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5529 {
5530 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5531 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5532 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5533 switch (pVmcs->u32GuestActivityState)
5534 {
5535 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5536 {
5537 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5538 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5539 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5540 && ( uVector == X86_XCPT_DB
5541 || uVector == X86_XCPT_MC))
5542 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5543 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5544 { /* likely */ }
5545 else
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5547 break;
5548 }
5549
5550 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5551 {
5552 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5553 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5554 && uVector == X86_XCPT_MC))
5555 { /* likely */ }
5556 else
5557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5558 break;
5559 }
5560
5561 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5562 default:
5563 break;
5564 }
5565 }
5566
5567 /*
5568 * Interruptibility state.
5569 */
5570 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5574
5575 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5576 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5580
5581 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5582 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5583 { /* likely */ }
5584 else
5585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5586
5587 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5588 {
5589 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5590 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5591 {
5592 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5596 }
5597 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5598 {
5599 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5600 { /* likely */ }
5601 else
5602 {
5603 /*
5604 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5605 * We update the Exit qualification only when blocking-by-STI is set
5606 * without blocking-by-MovSS being set. Although in practise it does not
5607 * make much difference since the order of checks are implementation defined.
5608 */
5609 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5610 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5612 }
5613
5614 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5615 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5616 { /* likely */ }
5617 else
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5619 }
5620 }
5621
5622 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5623 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5624 { /* likely */ }
5625 else
5626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5627
5628 /* We don't support SGX yet. So enclave-interruption must not be set. */
5629 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5630 { /* likely */ }
5631 else
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5633
5634 /*
5635 * Pending debug exceptions.
5636 */
5637 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5638 ? pVmcs->u64GuestPendingDbgXcpt.u
5639 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5640 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5641 { /* likely */ }
5642 else
5643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5644
5645 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5646 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5647 {
5648 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5649 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5650 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5652
5653 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5654 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5655 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5657 }
5658
5659 /* We don't support RTM (Real-time Transactional Memory) yet. */
5660 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5661 { /* likely */ }
5662 else
5663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5664
5665 /*
5666 * VMCS link pointer.
5667 */
5668 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5669 {
5670 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5671 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5672 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5673 { /* likely */ }
5674 else
5675 {
5676 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5677 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5678 }
5679
5680 /* Validate the address. */
5681 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5682 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5683 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5684 { /* likely */ }
5685 else
5686 {
5687 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5688 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5689 }
5690
5691 /* Read the VMCS-link pointer from guest memory. */
5692 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5693 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5694 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5695 if (RT_SUCCESS(rc))
5696 { /* likely */ }
5697 else
5698 {
5699 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5701 }
5702
5703 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5704 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5705 { /* likely */ }
5706 else
5707 {
5708 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5710 }
5711
5712 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5713 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5714 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5715 { /* likely */ }
5716 else
5717 {
5718 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5720 }
5721
5722 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5723 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5724 }
5725
5726 NOREF(pszInstr);
5727 NOREF(pszFailure);
5728 return VINF_SUCCESS;
5729}
5730
5731
5732/**
5733 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5734 * VM-entry.
5735 *
5736 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5737 * @param pVCpu The cross context virtual CPU structure.
5738 * @param pszInstr The VMX instruction name (for logging purposes).
5739 * @param pVmcs Pointer to the virtual VMCS.
5740 */
5741IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5742{
5743 /*
5744 * Check PDPTEs.
5745 * See Intel spec. 4.4.1 "PDPTE Registers".
5746 */
5747 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5748 const char *const pszFailure = "VM-exit";
5749
5750 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5751 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5752 if (RT_SUCCESS(rc))
5753 {
5754 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5755 {
5756 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5757 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5758 { /* likely */ }
5759 else
5760 {
5761 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5762 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5764 }
5765 }
5766 }
5767 else
5768 {
5769 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5771 }
5772
5773 NOREF(pszFailure);
5774 NOREF(pszInstr);
5775 return rc;
5776}
5777
5778
5779/**
5780 * Checks guest PDPTEs as part of VM-entry.
5781 *
5782 * @param pVCpu The cross context virtual CPU structure.
5783 * @param pszInstr The VMX instruction name (for logging purposes).
5784 */
5785IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5786{
5787 /*
5788 * Guest PDPTEs.
5789 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5790 */
5791 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5792 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5793
5794 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5795 int rc;
5796 if ( !fGstInLongMode
5797 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5798 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5799 {
5800 /*
5801 * We don't support nested-paging for nested-guests yet.
5802 *
5803 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5804 * rather we need to check the PDPTEs referenced by the guest CR3.
5805 */
5806 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5807 }
5808 else
5809 rc = VINF_SUCCESS;
5810 return rc;
5811}
5812
5813
5814/**
5815 * Checks guest-state as part of VM-entry.
5816 *
5817 * @returns VBox status code.
5818 * @param pVCpu The cross context virtual CPU structure.
5819 * @param pszInstr The VMX instruction name (for logging purposes).
5820 */
5821IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5822{
5823 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5824 if (RT_SUCCESS(rc))
5825 {
5826 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5827 if (RT_SUCCESS(rc))
5828 {
5829 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5830 if (RT_SUCCESS(rc))
5831 {
5832 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5833 if (RT_SUCCESS(rc))
5834 {
5835 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5836 if (RT_SUCCESS(rc))
5837 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5838 }
5839 }
5840 }
5841 }
5842 return rc;
5843}
5844
5845
5846/**
5847 * Checks host-state as part of VM-entry.
5848 *
5849 * @returns VBox status code.
5850 * @param pVCpu The cross context virtual CPU structure.
5851 * @param pszInstr The VMX instruction name (for logging purposes).
5852 */
5853IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
5854{
5855 /*
5856 * Host Control Registers and MSRs.
5857 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5858 */
5859 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5860 const char * const pszFailure = "VMFail";
5861
5862 /* CR0 reserved bits. */
5863 {
5864 /* CR0 MB1 bits. */
5865 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5866 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5870
5871 /* CR0 MBZ bits. */
5872 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5873 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5877 }
5878
5879 /* CR4 reserved bits. */
5880 {
5881 /* CR4 MB1 bits. */
5882 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5883 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5884 { /* likely */ }
5885 else
5886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5887
5888 /* CR4 MBZ bits. */
5889 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5890 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5891 { /* likely */ }
5892 else
5893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5894 }
5895
5896 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5897 {
5898 /* CR3 reserved bits. */
5899 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5903
5904 /* SYSENTER ESP and SYSENTER EIP. */
5905 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5906 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5907 { /* likely */ }
5908 else
5909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5910 }
5911
5912 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5913 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5914
5915 /* PAT MSR. */
5916 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5917 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5918 { /* likely */ }
5919 else
5920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5921
5922 /* EFER MSR. */
5923 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5924 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5925 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5926 { /* likely */ }
5927 else
5928 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5929
5930 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5931 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5932 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5933 if ( fHostInLongMode == fHostLma
5934 && fHostInLongMode == fHostLme)
5935 { /* likely */ }
5936 else
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5938
5939 /*
5940 * Host Segment and Descriptor-Table Registers.
5941 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5942 */
5943 /* Selector RPL and TI. */
5944 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5945 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5946 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5947 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5948 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5949 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5950 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5951 { /* likely */ }
5952 else
5953 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5954
5955 /* CS and TR selectors cannot be 0. */
5956 if ( pVmcs->HostCs
5957 && pVmcs->HostTr)
5958 { /* likely */ }
5959 else
5960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5961
5962 /* SS cannot be 0 if 32-bit host. */
5963 if ( fHostInLongMode
5964 || pVmcs->HostSs)
5965 { /* likely */ }
5966 else
5967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5968
5969 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5970 {
5971 /* FS, GS, GDTR, IDTR, TR base address. */
5972 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5973 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5974 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5975 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5976 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5977 { /* likely */ }
5978 else
5979 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5980 }
5981
5982 /*
5983 * Host address-space size for 64-bit CPUs.
5984 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5985 */
5986 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5987 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5988 {
5989 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5990
5991 /* Logical processor in IA-32e mode. */
5992 if (fCpuInLongMode)
5993 {
5994 if (fHostInLongMode)
5995 {
5996 /* PAE must be set. */
5997 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5998 { /* likely */ }
5999 else
6000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6001
6002 /* RIP must be canonical. */
6003 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6004 { /* likely */ }
6005 else
6006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6007 }
6008 else
6009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6010 }
6011 else
6012 {
6013 /* Logical processor is outside IA-32e mode. */
6014 if ( !fGstInLongMode
6015 && !fHostInLongMode)
6016 {
6017 /* PCIDE should not be set. */
6018 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6019 { /* likely */ }
6020 else
6021 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6022
6023 /* The high 32-bits of RIP MBZ. */
6024 if (!pVmcs->u64HostRip.s.Hi)
6025 { /* likely */ }
6026 else
6027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6028 }
6029 else
6030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6031 }
6032 }
6033 else
6034 {
6035 /* Host address-space size for 32-bit CPUs. */
6036 if ( !fGstInLongMode
6037 && !fHostInLongMode)
6038 { /* likely */ }
6039 else
6040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6041 }
6042
6043 NOREF(pszInstr);
6044 NOREF(pszFailure);
6045 return VINF_SUCCESS;
6046}
6047
6048
6049/**
6050 * Checks VM-entry controls fields as part of VM-entry.
6051 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6052 *
6053 * @returns VBox status code.
6054 * @param pVCpu The cross context virtual CPU structure.
6055 * @param pszInstr The VMX instruction name (for logging purposes).
6056 */
6057IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6058{
6059 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6060 const char * const pszFailure = "VMFail";
6061
6062 /* VM-entry controls. */
6063 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6064 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6065 { /* likely */ }
6066 else
6067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6068
6069 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6073
6074 /* Event injection. */
6075 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6076 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6077 {
6078 /* Type and vector. */
6079 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6080 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6081 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6082 if ( !uRsvd
6083 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6084 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6085 { /* likely */ }
6086 else
6087 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6088
6089 /* Exception error code. */
6090 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6091 {
6092 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6093 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6094 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6095 { /* likely */ }
6096 else
6097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6098
6099 /* Exceptions that provide an error code. */
6100 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6101 && ( uVector == X86_XCPT_DF
6102 || uVector == X86_XCPT_TS
6103 || uVector == X86_XCPT_NP
6104 || uVector == X86_XCPT_SS
6105 || uVector == X86_XCPT_GP
6106 || uVector == X86_XCPT_PF
6107 || uVector == X86_XCPT_AC))
6108 { /* likely */ }
6109 else
6110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6111
6112 /* Exception error-code reserved bits. */
6113 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6114 { /* likely */ }
6115 else
6116 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6117
6118 /* Injecting a software interrupt, software exception or privileged software exception. */
6119 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6120 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6121 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6122 {
6123 /* Instruction length must be in the range 0-15. */
6124 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6125 { /* likely */ }
6126 else
6127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6128
6129 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6130 if ( pVmcs->u32EntryInstrLen == 0
6131 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6133 }
6134 }
6135 }
6136
6137 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6138 if (pVmcs->u32EntryMsrLoadCount)
6139 {
6140 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6141 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6142 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6146 }
6147
6148 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6149 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6150
6151 NOREF(pszInstr);
6152 NOREF(pszFailure);
6153 return VINF_SUCCESS;
6154}
6155
6156
6157/**
6158 * Checks VM-exit controls fields as part of VM-entry.
6159 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6160 *
6161 * @returns VBox status code.
6162 * @param pVCpu The cross context virtual CPU structure.
6163 * @param pszInstr The VMX instruction name (for logging purposes).
6164 */
6165IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6166{
6167 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6168 const char * const pszFailure = "VMFail";
6169
6170 /* VM-exit controls. */
6171 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6172 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6176
6177 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6181
6182 /* Save preemption timer without activating it. */
6183 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6184 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6185 { /* likely */ }
6186 else
6187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6188
6189 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6190 if (pVmcs->u32ExitMsrStoreCount)
6191 {
6192 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6193 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6194 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6195 { /* likely */ }
6196 else
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6198 }
6199
6200 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6201 if (pVmcs->u32ExitMsrLoadCount)
6202 {
6203 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6204 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6205 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6209 }
6210
6211 NOREF(pszInstr);
6212 NOREF(pszFailure);
6213 return VINF_SUCCESS;
6214}
6215
6216
6217/**
6218 * Checks VM-execution controls fields as part of VM-entry.
6219 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6220 *
6221 * @returns VBox status code.
6222 * @param pVCpu The cross context virtual CPU structure.
6223 * @param pszInstr The VMX instruction name (for logging purposes).
6224 *
6225 * @remarks This may update secondary-processor based VM-execution control fields
6226 * in the current VMCS if necessary.
6227 */
6228IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6229{
6230 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6231 const char * const pszFailure = "VMFail";
6232
6233 /* Pin-based VM-execution controls. */
6234 {
6235 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6236 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6237 { /* likely */ }
6238 else
6239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6240
6241 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6242 { /* likely */ }
6243 else
6244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6245 }
6246
6247 /* Processor-based VM-execution controls. */
6248 {
6249 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6250 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6254
6255 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6256 { /* likely */ }
6257 else
6258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6259 }
6260
6261 /* Secondary processor-based VM-execution controls. */
6262 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6263 {
6264 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6265 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6266 { /* likely */ }
6267 else
6268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6269
6270 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6271 { /* likely */ }
6272 else
6273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6274 }
6275 else
6276 Assert(!pVmcs->u32ProcCtls2);
6277
6278 /* CR3-target count. */
6279 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6280 { /* likely */ }
6281 else
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6283
6284 /* I/O bitmaps physical addresses. */
6285 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6286 {
6287 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6288 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6289 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6293
6294 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6295 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6296 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6297 { /* likely */ }
6298 else
6299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6300 }
6301
6302 /* MSR bitmap physical address. */
6303 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6304 {
6305 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6306 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6307 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6308 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6309 { /* likely */ }
6310 else
6311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6312
6313 /* Read the MSR bitmap. */
6314 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6315 * implementing fast path. */
6316 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6317 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6318 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6319 if (RT_SUCCESS(rc))
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6323 }
6324
6325 /* TPR shadow related controls. */
6326 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6327 {
6328 /* Virtual-APIC page physical address. */
6329 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6330 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6331 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6332 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6333 { /* likely */ }
6334 else
6335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6336
6337 /* TPR threshold without virtual-interrupt delivery. */
6338 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6339 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6341
6342 /* TPR threshold and VTPR. */
6343 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6344 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6345 {
6346 /* Read the VTPR from the virtual-APIC page. */
6347 uint8_t u8VTpr;
6348 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6349 if (RT_SUCCESS(rc))
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6353
6354 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6355 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6356 { /* likely */ }
6357 else
6358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6359 }
6360 }
6361 else
6362 {
6363 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6364 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6365 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6366 { /* likely */ }
6367 else
6368 {
6369 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6371 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6373 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6375 }
6376 }
6377
6378 /* NMI exiting and virtual-NMIs. */
6379 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6380 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6384
6385 /* Virtual-NMIs and NMI-window exiting. */
6386 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6387 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6391
6392 /* Virtualize APIC accesses. */
6393 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6394 {
6395 /* APIC-access physical address. */
6396 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6397 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6398 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6399 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6400 { /* likely */ }
6401 else
6402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6403
6404 /*
6405 * Disallow APIC-access page and virtual-APIC page from being the same address.
6406 * Note! This is not an Intel requirement, but one imposed by our implementation.
6407 */
6408 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6409 * redirecting accesses between the APIC-access page and the virtual-APIC
6410 * page. If any guest hypervisor requires this, we can implement it later. */
6411 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6412 {
6413 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6414 if (GCPhysVirtApic != GCPhysApicAccess)
6415 { /* likely */ }
6416 else
6417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6418 }
6419
6420 /*
6421 * Register the handler for the APIC-access page.
6422 *
6423 * We don't deregister the APIC-access page handler during the VM-exit as a different
6424 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6425 *
6426 * We leave the page registered until the first access that happens outside VMX non-root
6427 * mode. Guest software is allowed to access structures such as the APIC-access page
6428 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6429 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6430 *
6431 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6432 */
6433 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6434 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6435 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6436 if (RT_SUCCESS(rc))
6437 { /* likely */ }
6438 else
6439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6440 }
6441
6442 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6443 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6444 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6445 { /* likely */ }
6446 else
6447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6448
6449 /* Virtual-interrupt delivery requires external interrupt exiting. */
6450 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6451 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6452 { /* likely */ }
6453 else
6454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6455
6456 /* VPID. */
6457 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6458 || pVmcs->u16Vpid != 0)
6459 { /* likely */ }
6460 else
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6462
6463 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6464 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6465 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6466 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6467 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6468 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6469 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6470
6471 /* VMCS shadowing. */
6472 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6473 {
6474 /* VMREAD-bitmap physical address. */
6475 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6476 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6477 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6478 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6479 { /* likely */ }
6480 else
6481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6482
6483 /* VMWRITE-bitmap physical address. */
6484 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6485 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6486 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6487 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6488 { /* likely */ }
6489 else
6490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6491
6492 /* Read the VMREAD-bitmap. */
6493 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6494 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6495 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6496 if (RT_SUCCESS(rc))
6497 { /* likely */ }
6498 else
6499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6500
6501 /* Read the VMWRITE-bitmap. */
6502 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6503 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6504 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6505 if (RT_SUCCESS(rc))
6506 { /* likely */ }
6507 else
6508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6509 }
6510
6511 NOREF(pszInstr);
6512 NOREF(pszFailure);
6513 return VINF_SUCCESS;
6514}
6515
6516
6517/**
6518 * Loads the guest control registers, debug register and some MSRs as part of
6519 * VM-entry.
6520 *
6521 * @param pVCpu The cross context virtual CPU structure.
6522 */
6523IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6524{
6525 /*
6526 * Load guest control registers, debug registers and MSRs.
6527 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6528 */
6529 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6530
6531 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6532 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6533 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6534 CPUMSetGuestCR0(pVCpu, uGstCr0);
6535 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6536 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6537
6538 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6539 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6540
6541 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6542 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6543 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6544
6545 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6546 {
6547 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6548
6549 /* EFER MSR. */
6550 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6551 {
6552 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6553 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6554 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6555 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6556 if (fGstInLongMode)
6557 {
6558 /* If the nested-guest is in long mode, LMA and LME are both set. */
6559 Assert(fGstPaging);
6560 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6561 }
6562 else
6563 {
6564 /*
6565 * If the nested-guest is outside long mode:
6566 * - With paging: LMA is cleared, LME is cleared.
6567 * - Without paging: LMA is cleared, LME is left unmodified.
6568 */
6569 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6570 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6571 }
6572 }
6573 /* else: see below. */
6574 }
6575
6576 /* PAT MSR. */
6577 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6578 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6579
6580 /* EFER MSR. */
6581 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6582 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6583
6584 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6585 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6586
6587 /* We don't support IA32_BNDCFGS MSR yet. */
6588 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6589
6590 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6591}
6592
6593
6594/**
6595 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6596 *
6597 * @param pVCpu The cross context virtual CPU structure.
6598 */
6599IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6600{
6601 /*
6602 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6603 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6604 */
6605 /* CS, SS, ES, DS, FS, GS. */
6606 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6607 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6608 {
6609 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6610 CPUMSELREG VmcsSelReg;
6611 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6612 AssertRC(rc); NOREF(rc);
6613 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6614 {
6615 pGstSelReg->Sel = VmcsSelReg.Sel;
6616 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6617 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6618 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6619 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6620 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6621 }
6622 else
6623 {
6624 pGstSelReg->Sel = VmcsSelReg.Sel;
6625 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6626 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6627 switch (iSegReg)
6628 {
6629 case X86_SREG_CS:
6630 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6631 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6632 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6633 break;
6634
6635 case X86_SREG_SS:
6636 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6637 pGstSelReg->u32Limit = 0;
6638 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6639 break;
6640
6641 case X86_SREG_ES:
6642 case X86_SREG_DS:
6643 pGstSelReg->u64Base = 0;
6644 pGstSelReg->u32Limit = 0;
6645 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6646 break;
6647
6648 case X86_SREG_FS:
6649 case X86_SREG_GS:
6650 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6651 pGstSelReg->u32Limit = 0;
6652 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6653 break;
6654 }
6655 Assert(pGstSelReg->Attr.n.u1Unusable);
6656 }
6657 }
6658
6659 /* LDTR. */
6660 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6661 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6662 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6663 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6664 {
6665 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6666 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6667 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6668 }
6669 else
6670 {
6671 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6672 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6673 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6674 }
6675
6676 /* TR. */
6677 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6678 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6679 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6680 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6681 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6682 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6683 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6684
6685 /* GDTR. */
6686 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6687 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6688
6689 /* IDTR. */
6690 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6691 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6692}
6693
6694
6695/**
6696 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6697 *
6698 * @returns VBox status code.
6699 * @param pVCpu The cross context virtual CPU structure.
6700 * @param pszInstr The VMX instruction name (for logging purposes).
6701 */
6702IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6703{
6704 /*
6705 * Load guest MSRs.
6706 * See Intel spec. 26.4 "Loading MSRs".
6707 */
6708 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6709 const char *const pszFailure = "VM-exit";
6710
6711 /*
6712 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6713 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6714 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6715 */
6716 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6717 if (!cMsrs)
6718 return VINF_SUCCESS;
6719
6720 /*
6721 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6722 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6723 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6724 */
6725 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6726 if (fIsMsrCountValid)
6727 { /* likely */ }
6728 else
6729 {
6730 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6732 }
6733
6734 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6735 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6736 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6737 if (RT_SUCCESS(rc))
6738 {
6739 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6740 Assert(pMsr);
6741 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6742 {
6743 if ( !pMsr->u32Reserved
6744 && pMsr->u32Msr != MSR_K8_FS_BASE
6745 && pMsr->u32Msr != MSR_K8_GS_BASE
6746 && pMsr->u32Msr != MSR_K6_EFER
6747 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6748 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6749 {
6750 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6751 if (rcStrict == VINF_SUCCESS)
6752 continue;
6753
6754 /*
6755 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6756 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6757 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6758 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6759 * MSR in ring-0 if possible, or come up with a better, generic solution.
6760 */
6761 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6762 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6763 ? kVmxVDiag_Vmentry_MsrLoadRing3
6764 : kVmxVDiag_Vmentry_MsrLoad;
6765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6766 }
6767 else
6768 {
6769 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6771 }
6772 }
6773 }
6774 else
6775 {
6776 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6778 }
6779
6780 NOREF(pszInstr);
6781 NOREF(pszFailure);
6782 return VINF_SUCCESS;
6783}
6784
6785
6786/**
6787 * Loads the guest-state non-register state as part of VM-entry.
6788 *
6789 * @returns VBox status code.
6790 * @param pVCpu The cross context virtual CPU structure.
6791 *
6792 * @remarks This must be called only after loading the nested-guest register state
6793 * (especially nested-guest RIP).
6794 */
6795IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6796{
6797 /*
6798 * Load guest non-register state.
6799 * See Intel spec. 26.6 "Special Features of VM Entry"
6800 */
6801 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6802
6803 /*
6804 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6805 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6806 *
6807 * See Intel spec. 26.6.1 "Interruptibility State".
6808 */
6809 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6810 if ( !fEntryVectoring
6811 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6812 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6813 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6814 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6815
6816 /* NMI blocking. */
6817 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6818 {
6819 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6820 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6821 else
6822 {
6823 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6824 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6825 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6826 }
6827 }
6828 else
6829 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6830
6831 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6832
6833 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6834 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6835
6836 /* VPID is irrelevant. We don't support VPID yet. */
6837
6838 /* Clear address-range monitoring. */
6839 EMMonitorWaitClear(pVCpu);
6840}
6841
6842
6843/**
6844 * Loads the guest-state as part of VM-entry.
6845 *
6846 * @returns VBox status code.
6847 * @param pVCpu The cross context virtual CPU structure.
6848 * @param pszInstr The VMX instruction name (for logging purposes).
6849 *
6850 * @remarks This must be done after all the necessary steps prior to loading of
6851 * guest-state (e.g. checking various VMCS state).
6852 */
6853IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6854{
6855 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6856 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6857
6858 /*
6859 * Load guest RIP, RSP and RFLAGS.
6860 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6861 */
6862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6863 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6864 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6865 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6866
6867 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6868 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6869 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6870
6871 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6872
6873 NOREF(pszInstr);
6874 return VINF_SUCCESS;
6875}
6876
6877
6878/**
6879 * Returns whether there are is a pending debug exception on VM-entry.
6880 *
6881 * @param pVCpu The cross context virtual CPU structure.
6882 * @param pszInstr The VMX instruction name (for logging purposes).
6883 */
6884IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6885{
6886 /*
6887 * Pending debug exceptions.
6888 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6889 */
6890 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6891 Assert(pVmcs);
6892
6893 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6894 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6895 if (fPendingDbgXcpt)
6896 {
6897 uint8_t uEntryIntInfoType;
6898 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6899 if (fEntryVectoring)
6900 {
6901 switch (uEntryIntInfoType)
6902 {
6903 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6904 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6905 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6906 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6907 fPendingDbgXcpt = false;
6908 break;
6909
6910 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6911 {
6912 /*
6913 * Whether the pending debug exception for software exceptions other than
6914 * #BP and #OF is delivered after injecting the exception or is discard
6915 * is CPU implementation specific. We will discard them (easier).
6916 */
6917 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6918 if ( uVector != X86_XCPT_BP
6919 && uVector != X86_XCPT_OF)
6920 fPendingDbgXcpt = false;
6921 RT_FALL_THRU();
6922 }
6923 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6924 {
6925 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6926 fPendingDbgXcpt = false;
6927 break;
6928 }
6929 }
6930 }
6931 else
6932 {
6933 /*
6934 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6935 * pending debug exception is held pending or is discarded is CPU implementation
6936 * specific. We will discard them (easier).
6937 */
6938 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6939 fPendingDbgXcpt = false;
6940
6941 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6942 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6943 fPendingDbgXcpt = false;
6944 }
6945 }
6946
6947 NOREF(pszInstr);
6948 return fPendingDbgXcpt;
6949}
6950
6951
6952/**
6953 * Set up the monitor-trap flag (MTF).
6954 *
6955 * @param pVCpu The cross context virtual CPU structure.
6956 * @param pszInstr The VMX instruction name (for logging purposes).
6957 */
6958IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
6959{
6960 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6961 Assert(pVmcs);
6962 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6963 {
6964 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6965 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6966 }
6967 else
6968 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6969 NOREF(pszInstr);
6970}
6971
6972
6973/**
6974 * Sets up NMI-window exiting.
6975 *
6976 * @param pVCpu The cross context virtual CPU structure.
6977 * @param pszInstr The VMX instruction name (for logging purposes).
6978 */
6979IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
6980{
6981 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6982 Assert(pVmcs);
6983 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6984 {
6985 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6986 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6987 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6988 }
6989 else
6990 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6991 NOREF(pszInstr);
6992}
6993
6994
6995/**
6996 * Sets up interrupt-window exiting.
6997 *
6998 * @param pVCpu The cross context virtual CPU structure.
6999 * @param pszInstr The VMX instruction name (for logging purposes).
7000 */
7001IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7002{
7003 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7004 Assert(pVmcs);
7005 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7006 {
7007 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7008 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7009 }
7010 else
7011 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7012 NOREF(pszInstr);
7013}
7014
7015
7016/**
7017 * Set up the VMX-preemption timer.
7018 *
7019 * @param pVCpu The cross context virtual CPU structure.
7020 * @param pszInstr The VMX instruction name (for logging purposes).
7021 */
7022IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7023{
7024 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7025 Assert(pVmcs);
7026 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7027 {
7028 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7029 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7030 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7031
7032 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7033 }
7034 else
7035 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7036
7037 NOREF(pszInstr);
7038}
7039
7040
7041/**
7042 * Injects an event using TRPM given a VM-entry interruption info. and related
7043 * fields.
7044 *
7045 * @returns VBox status code.
7046 * @param pVCpu The cross context virtual CPU structure.
7047 * @param uEntryIntInfo The VM-entry interruption info.
7048 * @param uErrCode The error code associated with the event if any.
7049 * @param cbInstr The VM-entry instruction length (for software
7050 * interrupts and software exceptions). Pass 0
7051 * otherwise.
7052 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7053 */
7054IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7055 RTGCUINTPTR GCPtrFaultAddress)
7056{
7057 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7058
7059 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7060 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7061 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7062
7063 TRPMEVENT enmTrapType;
7064 switch (uType)
7065 {
7066 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7067 enmTrapType = TRPM_HARDWARE_INT;
7068 break;
7069
7070 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7071 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7072 enmTrapType = TRPM_TRAP;
7073 break;
7074
7075 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7076 enmTrapType = TRPM_SOFTWARE_INT;
7077 break;
7078
7079 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7080 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7081 enmTrapType = TRPM_SOFTWARE_INT;
7082 break;
7083
7084 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7085 Assert(uVector == X86_XCPT_DB);
7086 enmTrapType = TRPM_SOFTWARE_INT;
7087 break;
7088
7089 default:
7090 /* Shouldn't really happen. */
7091 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7092 break;
7093 }
7094
7095 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7096 AssertRCReturn(rc, rc);
7097
7098 if (fErrCodeValid)
7099 TRPMSetErrorCode(pVCpu, uErrCode);
7100
7101 if ( enmTrapType == TRPM_TRAP
7102 && uVector == X86_XCPT_PF)
7103 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7104 else if (enmTrapType == TRPM_SOFTWARE_INT)
7105 TRPMSetInstrLength(pVCpu, cbInstr);
7106
7107 return VINF_SUCCESS;
7108}
7109
7110
7111/**
7112 * Performs event injection (if any) as part of VM-entry.
7113 *
7114 * @param pVCpu The cross context virtual CPU structure.
7115 * @param pszInstr The VMX instruction name (for logging purposes).
7116 */
7117IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7118{
7119 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7120
7121 /*
7122 * Inject events.
7123 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7124 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7125 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7126 * the actually delivery of this event.
7127 *
7128 * See Intel spec. 26.5 "Event Injection".
7129 */
7130 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7131 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7132
7133 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7134 if (fEntryIntInfoValid)
7135 {
7136 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7137 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7138 {
7139 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7140 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7141 return VINF_SUCCESS;
7142 }
7143
7144 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7145 pVCpu->cpum.GstCtx.cr2);
7146 if (RT_SUCCESS(rc))
7147 {
7148 /*
7149 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7150 *
7151 * However, we do it here on VM-entry because while it continues to not be visible to
7152 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7153 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7154 * information field.
7155 *
7156 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7157 */
7158 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7159 }
7160 return rc;
7161 }
7162
7163 /*
7164 * Inject any pending guest debug exception.
7165 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7166 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7167 */
7168 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7169 if (fPendingDbgXcpt)
7170 {
7171 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7172 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7173 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7174 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7175 0 /* GCPtrFaultAddress */);
7176 }
7177
7178 NOREF(pszInstr);
7179 return VINF_SUCCESS;
7180}
7181
7182
7183/**
7184 * Initializes all read-only VMCS fields as part of VM-entry.
7185 *
7186 * @param pVCpu The cross context virtual CPU structure.
7187 */
7188IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7189{
7190 /*
7191 * Any VMCS field which we do not establish on every VM-exit but may potentially
7192 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7193 * specified to be undefined needs to be initialized here.
7194 *
7195 * Thus, it is especially important to clear the Exit qualification field
7196 * since it must be zero for VM-exits where it is not used. Similarly, the
7197 * VM-exit interruption information field's valid bit needs to be cleared for
7198 * the same reasons.
7199 */
7200 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7201 Assert(pVmcs);
7202
7203 /* 16-bit (none currently). */
7204 /* 32-bit. */
7205 pVmcs->u32RoVmInstrError = 0;
7206 pVmcs->u32RoExitReason = 0;
7207 pVmcs->u32RoExitIntInfo = 0;
7208 pVmcs->u32RoExitIntErrCode = 0;
7209 pVmcs->u32RoIdtVectoringInfo = 0;
7210 pVmcs->u32RoIdtVectoringErrCode = 0;
7211 pVmcs->u32RoExitInstrLen = 0;
7212 pVmcs->u32RoExitInstrInfo = 0;
7213
7214 /* 64-bit. */
7215 pVmcs->u64RoGuestPhysAddr.u = 0;
7216
7217 /* Natural-width. */
7218 pVmcs->u64RoExitQual.u = 0;
7219 pVmcs->u64RoIoRcx.u = 0;
7220 pVmcs->u64RoIoRsi.u = 0;
7221 pVmcs->u64RoIoRdi.u = 0;
7222 pVmcs->u64RoIoRip.u = 0;
7223 pVmcs->u64RoGuestLinearAddr.u = 0;
7224}
7225
7226
7227/**
7228 * VMLAUNCH/VMRESUME instruction execution worker.
7229 *
7230 * @returns Strict VBox status code.
7231 * @param pVCpu The cross context virtual CPU structure.
7232 * @param cbInstr The instruction length in bytes.
7233 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7234 * VMXINSTRID_VMRESUME).
7235 *
7236 * @remarks Common VMX instruction checks are already expected to by the caller,
7237 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7238 */
7239IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7240{
7241# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7242 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7243 return VINF_EM_RAW_EMULATE_INSTR;
7244# else
7245 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7246 || uInstrId == VMXINSTRID_VMRESUME);
7247 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7248
7249 /* Nested-guest intercept. */
7250 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7251 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7252
7253 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7254
7255 /*
7256 * Basic VM-entry checks.
7257 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7258 * The checks following that do not have to follow a specific order.
7259 *
7260 * See Intel spec. 26.1 "Basic VM-entry Checks".
7261 */
7262
7263 /* CPL. */
7264 if (pVCpu->iem.s.uCpl == 0)
7265 { /* likely */ }
7266 else
7267 {
7268 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7269 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7270 return iemRaiseGeneralProtectionFault0(pVCpu);
7271 }
7272
7273 /* Current VMCS valid. */
7274 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7275 { /* likely */ }
7276 else
7277 {
7278 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7279 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7280 iemVmxVmFailInvalid(pVCpu);
7281 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7282 return VINF_SUCCESS;
7283 }
7284
7285 /* Current VMCS is not a shadow VMCS. */
7286 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7287 { /* likely */ }
7288 else
7289 {
7290 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7291 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7292 iemVmxVmFailInvalid(pVCpu);
7293 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7294 return VINF_SUCCESS;
7295 }
7296
7297 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7298 * use block-by-STI here which is not quite correct. */
7299 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7300 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7301 { /* likely */ }
7302 else
7303 {
7304 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7305 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7306 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7307 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7308 return VINF_SUCCESS;
7309 }
7310
7311 if (uInstrId == VMXINSTRID_VMLAUNCH)
7312 {
7313 /* VMLAUNCH with non-clear VMCS. */
7314 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7315 { /* likely */ }
7316 else
7317 {
7318 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7319 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7320 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7321 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7322 return VINF_SUCCESS;
7323 }
7324 }
7325 else
7326 {
7327 /* VMRESUME with non-launched VMCS. */
7328 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7329 { /* likely */ }
7330 else
7331 {
7332 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7333 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7334 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7335 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7336 return VINF_SUCCESS;
7337 }
7338 }
7339
7340 /*
7341 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7342 * while entering VMX non-root mode. We do some of this while checking VM-execution
7343 * controls. The guest hypervisor should not make assumptions and cannot expect
7344 * predictable behavior if changes to these structures are made in guest memory while
7345 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7346 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7347 *
7348 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7349 */
7350 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7351 Assert(pVmcs);
7352 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7353
7354 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7355 if (RT_SUCCESS(rc))
7356 {
7357 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7358 if (RT_SUCCESS(rc))
7359 {
7360 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7361 if (RT_SUCCESS(rc))
7362 {
7363 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7364 if (RT_SUCCESS(rc))
7365 {
7366 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7367 iemVmxVmentryInitReadOnlyFields(pVCpu);
7368
7369 /*
7370 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7371 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7372 * VM-exit when required.
7373 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7374 */
7375 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7376
7377 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7378 if (RT_SUCCESS(rc))
7379 {
7380 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7381 if (RT_SUCCESS(rc))
7382 {
7383 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7384 if (RT_SUCCESS(rc))
7385 {
7386 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7387
7388 /* VMLAUNCH instruction must update the VMCS launch state. */
7389 if (uInstrId == VMXINSTRID_VMLAUNCH)
7390 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7391
7392 /* Perform the VMX transition (PGM updates). */
7393 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7394 if (rcStrict == VINF_SUCCESS)
7395 { /* likely */ }
7396 else if (RT_SUCCESS(rcStrict))
7397 {
7398 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7399 VBOXSTRICTRC_VAL(rcStrict)));
7400 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7401 }
7402 else
7403 {
7404 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7405 return rcStrict;
7406 }
7407
7408 /* We've now entered nested-guest execution. */
7409 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7410
7411 /*
7412 * The priority of potential VM-exits during VM-entry is important.
7413 * The priorities of VM-exits and events are listed from highest
7414 * to lowest as follows:
7415 *
7416 * 1. Event injection.
7417 * 2. Trap on task-switch (T flag set in TSS).
7418 * 3. TPR below threshold / APIC-write.
7419 * 4. SMI, INIT.
7420 * 5. MTF exit.
7421 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7422 * 7. VMX-preemption timer.
7423 * 9. NMI-window exit.
7424 * 10. NMI injection.
7425 * 11. Interrupt-window exit.
7426 * 12. Virtual-interrupt injection.
7427 * 13. Interrupt injection.
7428 * 14. Process next instruction (fetch, decode, execute).
7429 */
7430
7431 /* Setup the VMX-preemption timer. */
7432 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7433
7434 /* Setup monitor-trap flag. */
7435 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7436
7437 /* Setup NMI-window exiting. */
7438 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7439
7440 /* Setup interrupt-window exiting. */
7441 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7442
7443 /* Now that we've switched page tables, we can go ahead and inject any event. */
7444 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7445 if (RT_SUCCESS(rcStrict))
7446 {
7447 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7448# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7449 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7450 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7451 if (rcSched != VINF_SUCCESS)
7452 iemSetPassUpStatus(pVCpu, rcSched);
7453# endif
7454 return VINF_SUCCESS;
7455 }
7456
7457 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7458 return rcStrict;
7459 }
7460 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7461 pVmcs->u64RoExitQual.u);
7462 }
7463 }
7464 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7465 pVmcs->u64RoExitQual.u);
7466 }
7467
7468 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7469 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7470 return VINF_SUCCESS;
7471 }
7472 }
7473 }
7474
7475 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7476 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7477 return VINF_SUCCESS;
7478# endif
7479}
7480
7481
7482/**
7483 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7484 * (causes a VM-exit) or not.
7485 *
7486 * @returns @c true if the instruction is intercepted, @c false otherwise.
7487 * @param pVCpu The cross context virtual CPU structure.
7488 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7489 * VMX_EXIT_WRMSR).
7490 * @param idMsr The MSR.
7491 */
7492IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7493{
7494 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7495 Assert( uExitReason == VMX_EXIT_RDMSR
7496 || uExitReason == VMX_EXIT_WRMSR);
7497
7498 /* Consult the MSR bitmap if the feature is supported. */
7499 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7500 Assert(pVmcs);
7501 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7502 {
7503 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7504 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7505 if (uExitReason == VMX_EXIT_RDMSR)
7506 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7507 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7508 }
7509
7510 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7511 return true;
7512}
7513
7514
7515/**
7516 * VMREAD common (memory/register) instruction execution worker
7517 *
7518 * @returns Strict VBox status code.
7519 * @param pVCpu The cross context virtual CPU structure.
7520 * @param cbInstr The instruction length in bytes.
7521 * @param pu64Dst Where to write the VMCS value (only updated when
7522 * VINF_SUCCESS is returned).
7523 * @param u64VmcsField The VMCS field.
7524 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7525 * NULL.
7526 */
7527IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7528 PCVMXVEXITINFO pExitInfo)
7529{
7530 /* Nested-guest intercept. */
7531 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7532 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7533 {
7534 if (pExitInfo)
7535 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7536 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7537 }
7538
7539 /* CPL. */
7540 if (pVCpu->iem.s.uCpl == 0)
7541 { /* likely */ }
7542 else
7543 {
7544 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7545 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7546 return iemRaiseGeneralProtectionFault0(pVCpu);
7547 }
7548
7549 /* VMCS pointer in root mode. */
7550 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7551 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7552 { /* likely */ }
7553 else
7554 {
7555 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7557 iemVmxVmFailInvalid(pVCpu);
7558 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7559 return VINF_SUCCESS;
7560 }
7561
7562 /* VMCS-link pointer in non-root mode. */
7563 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7564 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7565 { /* likely */ }
7566 else
7567 {
7568 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7570 iemVmxVmFailInvalid(pVCpu);
7571 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7572 return VINF_SUCCESS;
7573 }
7574
7575 /* Supported VMCS field. */
7576 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7577 { /* likely */ }
7578 else
7579 {
7580 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7582 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7583 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7584 return VINF_SUCCESS;
7585 }
7586
7587 /*
7588 * Setup reading from the current or shadow VMCS.
7589 */
7590 uint8_t *pbVmcs;
7591 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7592 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7593 else
7594 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7595 Assert(pbVmcs);
7596
7597 VMXVMCSFIELD VmcsField;
7598 VmcsField.u = u64VmcsField;
7599 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7600 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7601 uint8_t const uWidthType = (uWidth << 2) | uType;
7602 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7603 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7604 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7605 Assert(offField < VMX_V_VMCS_SIZE);
7606
7607 /*
7608 * Read the VMCS component based on the field's effective width.
7609 *
7610 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7611 * indicates high bits (little endian).
7612 *
7613 * Note! The caller is responsible to trim the result and update registers
7614 * or memory locations are required. Here we just zero-extend to the largest
7615 * type (i.e. 64-bits).
7616 */
7617 uint8_t *pbField = pbVmcs + offField;
7618 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7619 switch (uEffWidth)
7620 {
7621 case VMX_VMCSFIELD_WIDTH_64BIT:
7622 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7623 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7624 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7625 }
7626 return VINF_SUCCESS;
7627}
7628
7629
7630/**
7631 * VMREAD (64-bit register) instruction execution worker.
7632 *
7633 * @returns Strict VBox status code.
7634 * @param pVCpu The cross context virtual CPU structure.
7635 * @param cbInstr The instruction length in bytes.
7636 * @param pu64Dst Where to store the VMCS field's value.
7637 * @param u64VmcsField The VMCS field.
7638 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7639 * NULL.
7640 */
7641IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7642 PCVMXVEXITINFO pExitInfo)
7643{
7644 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7645 if (rcStrict == VINF_SUCCESS)
7646 {
7647 iemVmxVmreadSuccess(pVCpu, cbInstr);
7648 return VINF_SUCCESS;
7649 }
7650
7651 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7652 return rcStrict;
7653}
7654
7655
7656/**
7657 * VMREAD (32-bit register) instruction execution worker.
7658 *
7659 * @returns Strict VBox status code.
7660 * @param pVCpu The cross context virtual CPU structure.
7661 * @param cbInstr The instruction length in bytes.
7662 * @param pu32Dst Where to store the VMCS field's value.
7663 * @param u32VmcsField The VMCS field.
7664 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7665 * NULL.
7666 */
7667IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7668 PCVMXVEXITINFO pExitInfo)
7669{
7670 uint64_t u64Dst;
7671 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7672 if (rcStrict == VINF_SUCCESS)
7673 {
7674 *pu32Dst = u64Dst;
7675 iemVmxVmreadSuccess(pVCpu, cbInstr);
7676 return VINF_SUCCESS;
7677 }
7678
7679 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7680 return rcStrict;
7681}
7682
7683
7684/**
7685 * VMREAD (memory) instruction execution worker.
7686 *
7687 * @returns Strict VBox status code.
7688 * @param pVCpu The cross context virtual CPU structure.
7689 * @param cbInstr The instruction length in bytes.
7690 * @param iEffSeg The effective segment register to use with @a u64Val.
7691 * Pass UINT8_MAX if it is a register access.
7692 * @param GCPtrDst The guest linear address to store the VMCS field's
7693 * value.
7694 * @param u64VmcsField The VMCS field.
7695 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7696 * NULL.
7697 */
7698IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7699 PCVMXVEXITINFO pExitInfo)
7700{
7701 uint64_t u64Dst;
7702 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7703 if (rcStrict == VINF_SUCCESS)
7704 {
7705 /*
7706 * Write the VMCS field's value to the location specified in guest-memory.
7707 */
7708 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7709 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7710 else
7711 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7712 if (rcStrict == VINF_SUCCESS)
7713 {
7714 iemVmxVmreadSuccess(pVCpu, cbInstr);
7715 return VINF_SUCCESS;
7716 }
7717
7718 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7719 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7720 return rcStrict;
7721 }
7722
7723 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7724 return rcStrict;
7725}
7726
7727
7728/**
7729 * VMWRITE instruction execution worker.
7730 *
7731 * @returns Strict VBox status code.
7732 * @param pVCpu The cross context virtual CPU structure.
7733 * @param cbInstr The instruction length in bytes.
7734 * @param iEffSeg The effective segment register to use with @a u64Val.
7735 * Pass UINT8_MAX if it is a register access.
7736 * @param u64Val The value to write (or guest linear address to the
7737 * value), @a iEffSeg will indicate if it's a memory
7738 * operand.
7739 * @param u64VmcsField The VMCS field.
7740 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7741 * NULL.
7742 */
7743IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7744 PCVMXVEXITINFO pExitInfo)
7745{
7746 /* Nested-guest intercept. */
7747 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7748 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7749 {
7750 if (pExitInfo)
7751 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7752 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7753 }
7754
7755 /* CPL. */
7756 if (pVCpu->iem.s.uCpl == 0)
7757 { /* likely */ }
7758 else
7759 {
7760 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7761 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7762 return iemRaiseGeneralProtectionFault0(pVCpu);
7763 }
7764
7765 /* VMCS pointer in root mode. */
7766 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7767 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7768 { /* likely */ }
7769 else
7770 {
7771 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7773 iemVmxVmFailInvalid(pVCpu);
7774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7775 return VINF_SUCCESS;
7776 }
7777
7778 /* VMCS-link pointer in non-root mode. */
7779 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7780 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7781 { /* likely */ }
7782 else
7783 {
7784 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7785 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7786 iemVmxVmFailInvalid(pVCpu);
7787 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7788 return VINF_SUCCESS;
7789 }
7790
7791 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7792 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7793 if (!fIsRegOperand)
7794 {
7795 /* Read the value from the specified guest memory location. */
7796 VBOXSTRICTRC rcStrict;
7797 RTGCPTR const GCPtrVal = u64Val;
7798 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7799 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7800 else
7801 {
7802 uint32_t u32Val;
7803 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7804 u64Val = u32Val;
7805 }
7806 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7807 {
7808 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7809 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7810 return rcStrict;
7811 }
7812 }
7813 else
7814 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7815
7816 /* Supported VMCS field. */
7817 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7818 { /* likely */ }
7819 else
7820 {
7821 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7822 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7823 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7824 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7825 return VINF_SUCCESS;
7826 }
7827
7828 /* Read-only VMCS field. */
7829 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
7830 if ( !fIsFieldReadOnly
7831 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7832 { /* likely */ }
7833 else
7834 {
7835 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7836 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7837 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7838 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7839 return VINF_SUCCESS;
7840 }
7841
7842 /*
7843 * Setup writing to the current or shadow VMCS.
7844 */
7845 uint8_t *pbVmcs;
7846 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7847 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7848 else
7849 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7850 Assert(pbVmcs);
7851
7852 VMXVMCSFIELD VmcsField;
7853 VmcsField.u = u64VmcsField;
7854 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7855 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7856 uint8_t const uWidthType = (uWidth << 2) | uType;
7857 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7858 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7859 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7860 Assert(offField < VMX_V_VMCS_SIZE);
7861
7862 /*
7863 * Write the VMCS component based on the field's effective width.
7864 *
7865 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7866 * indicates high bits (little endian).
7867 */
7868 uint8_t *pbField = pbVmcs + offField;
7869 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7870 switch (uEffWidth)
7871 {
7872 case VMX_VMCSFIELD_WIDTH_64BIT:
7873 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7874 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7875 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7876 }
7877
7878 iemVmxVmSucceed(pVCpu);
7879 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7880 return VINF_SUCCESS;
7881}
7882
7883
7884/**
7885 * VMCLEAR instruction execution worker.
7886 *
7887 * @returns Strict VBox status code.
7888 * @param pVCpu The cross context virtual CPU structure.
7889 * @param cbInstr The instruction length in bytes.
7890 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7891 * @param GCPtrVmcs The linear address of the VMCS pointer.
7892 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7893 * NULL.
7894 *
7895 * @remarks Common VMX instruction checks are already expected to by the caller,
7896 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7897 */
7898IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7899 PCVMXVEXITINFO pExitInfo)
7900{
7901 /* Nested-guest intercept. */
7902 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7903 {
7904 if (pExitInfo)
7905 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7906 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7907 }
7908
7909 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7910
7911 /* CPL. */
7912 if (pVCpu->iem.s.uCpl == 0)
7913 { /* likely */ }
7914 else
7915 {
7916 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7917 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7918 return iemRaiseGeneralProtectionFault0(pVCpu);
7919 }
7920
7921 /* Get the VMCS pointer from the location specified by the source memory operand. */
7922 RTGCPHYS GCPhysVmcs;
7923 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7924 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7925 { /* likely */ }
7926 else
7927 {
7928 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7929 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7930 return rcStrict;
7931 }
7932
7933 /* VMCS pointer alignment. */
7934 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7935 { /* likely */ }
7936 else
7937 {
7938 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7939 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7940 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7941 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7942 return VINF_SUCCESS;
7943 }
7944
7945 /* VMCS physical-address width limits. */
7946 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7947 { /* likely */ }
7948 else
7949 {
7950 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7952 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7953 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7954 return VINF_SUCCESS;
7955 }
7956
7957 /* VMCS is not the VMXON region. */
7958 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7959 { /* likely */ }
7960 else
7961 {
7962 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7963 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7964 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7966 return VINF_SUCCESS;
7967 }
7968
7969 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7970 restriction imposed by our implementation. */
7971 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7972 { /* likely */ }
7973 else
7974 {
7975 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7976 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7977 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7978 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7979 return VINF_SUCCESS;
7980 }
7981
7982 /*
7983 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7984 *
7985 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7986 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7987 * to 'clear'.
7988 */
7989 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7990 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7991 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7992 {
7993 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
7994 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7995 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
7996 iemVmxCommitCurrentVmcsToMemory(pVCpu);
7997 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7998 }
7999 else
8000 {
8001 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8002 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8003 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8004 if (RT_FAILURE(rcStrict))
8005 return rcStrict;
8006 }
8007
8008 iemVmxVmSucceed(pVCpu);
8009 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8010 return VINF_SUCCESS;
8011}
8012
8013
8014/**
8015 * VMPTRST instruction execution worker.
8016 *
8017 * @returns Strict VBox status code.
8018 * @param pVCpu The cross context virtual CPU structure.
8019 * @param cbInstr The instruction length in bytes.
8020 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8021 * @param GCPtrVmcs The linear address of where to store the current VMCS
8022 * pointer.
8023 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8024 * NULL.
8025 *
8026 * @remarks Common VMX instruction checks are already expected to by the caller,
8027 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8028 */
8029IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8030 PCVMXVEXITINFO pExitInfo)
8031{
8032 /* Nested-guest intercept. */
8033 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8034 {
8035 if (pExitInfo)
8036 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8037 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8038 }
8039
8040 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8041
8042 /* CPL. */
8043 if (pVCpu->iem.s.uCpl == 0)
8044 { /* likely */ }
8045 else
8046 {
8047 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8048 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8049 return iemRaiseGeneralProtectionFault0(pVCpu);
8050 }
8051
8052 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8053 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8054 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8055 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8056 {
8057 iemVmxVmSucceed(pVCpu);
8058 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8059 return rcStrict;
8060 }
8061
8062 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8063 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8064 return rcStrict;
8065}
8066
8067
8068/**
8069 * VMPTRLD instruction execution worker.
8070 *
8071 * @returns Strict VBox status code.
8072 * @param pVCpu The cross context virtual CPU structure.
8073 * @param cbInstr The instruction length in bytes.
8074 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8075 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8076 * NULL.
8077 *
8078 * @remarks Common VMX instruction checks are already expected to by the caller,
8079 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8080 */
8081IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8082 PCVMXVEXITINFO pExitInfo)
8083{
8084 /* Nested-guest intercept. */
8085 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8086 {
8087 if (pExitInfo)
8088 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8089 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8090 }
8091
8092 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8093
8094 /* CPL. */
8095 if (pVCpu->iem.s.uCpl == 0)
8096 { /* likely */ }
8097 else
8098 {
8099 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8100 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8101 return iemRaiseGeneralProtectionFault0(pVCpu);
8102 }
8103
8104 /* Get the VMCS pointer from the location specified by the source memory operand. */
8105 RTGCPHYS GCPhysVmcs;
8106 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8107 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8108 { /* likely */ }
8109 else
8110 {
8111 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8112 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8113 return rcStrict;
8114 }
8115
8116 /* VMCS pointer alignment. */
8117 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8118 { /* likely */ }
8119 else
8120 {
8121 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8122 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8123 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8125 return VINF_SUCCESS;
8126 }
8127
8128 /* VMCS physical-address width limits. */
8129 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8130 { /* likely */ }
8131 else
8132 {
8133 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8134 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8135 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8136 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8137 return VINF_SUCCESS;
8138 }
8139
8140 /* VMCS is not the VMXON region. */
8141 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8142 { /* likely */ }
8143 else
8144 {
8145 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8146 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8147 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8149 return VINF_SUCCESS;
8150 }
8151
8152 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8153 restriction imposed by our implementation. */
8154 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8155 { /* likely */ }
8156 else
8157 {
8158 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8159 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8160 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8161 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8162 return VINF_SUCCESS;
8163 }
8164
8165 /* Read just the VMCS revision from the VMCS. */
8166 VMXVMCSREVID VmcsRevId;
8167 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8168 if (RT_SUCCESS(rc))
8169 { /* likely */ }
8170 else
8171 {
8172 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8174 return rc;
8175 }
8176
8177 /*
8178 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8179 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8180 */
8181 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8182 && ( !VmcsRevId.n.fIsShadowVmcs
8183 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8184 { /* likely */ }
8185 else
8186 {
8187 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8188 {
8189 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8190 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8191 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8192 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8193 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8194 return VINF_SUCCESS;
8195 }
8196
8197 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8198 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8199 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8200 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8201 return VINF_SUCCESS;
8202 }
8203
8204 /*
8205 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8206 * the cache of an existing, current VMCS back to guest memory before loading a new,
8207 * different current VMCS.
8208 */
8209 bool fLoadVmcsFromMem;
8210 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8211 {
8212 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8213 {
8214 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8215 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8216 fLoadVmcsFromMem = true;
8217 }
8218 else
8219 fLoadVmcsFromMem = false;
8220 }
8221 else
8222 fLoadVmcsFromMem = true;
8223
8224 if (fLoadVmcsFromMem)
8225 {
8226 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8227 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8228 sizeof(VMXVVMCS));
8229 if (RT_SUCCESS(rc))
8230 { /* likely */ }
8231 else
8232 {
8233 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8234 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8235 return rc;
8236 }
8237 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8238 }
8239
8240 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8241 iemVmxVmSucceed(pVCpu);
8242 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8243 return VINF_SUCCESS;
8244}
8245
8246
8247/**
8248 * INVVPID instruction execution worker.
8249 *
8250 * @returns Strict VBox status code.
8251 * @param pVCpu The cross context virtual CPU structure.
8252 * @param cbInstr The instruction length in bytes.
8253 * @param iEffSeg The segment of the invvpid descriptor.
8254 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8255 * @param u64InvvpidType The invalidation type.
8256 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8257 * NULL.
8258 *
8259 * @remarks Common VMX instruction checks are already expected to by the caller,
8260 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8261 */
8262IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8263 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8264{
8265 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8266 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8267 return iemRaiseUndefinedOpcode(pVCpu);
8268
8269 /* Nested-guest intercept. */
8270 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8271 {
8272 if (pExitInfo)
8273 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8274 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8275 }
8276
8277 /* CPL. */
8278 if (pVCpu->iem.s.uCpl != 0)
8279 {
8280 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8281 return iemRaiseGeneralProtectionFault0(pVCpu);
8282 }
8283
8284 /*
8285 * Validate INVVPID invalidation type.
8286 *
8287 * The instruction specifies exactly ONE of the supported invalidation types.
8288 *
8289 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8290 * supported. In theory, it's possible for a CPU to not support flushing individual
8291 * addresses but all the other types or any other combination. We do not take any
8292 * shortcuts here by assuming the types we currently expose to the guest.
8293 */
8294 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8295 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8296 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8297 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8298 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8299 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8300 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8301 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8302 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8303 { /* likely */ }
8304 else
8305 {
8306 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8307 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8308 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8309 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8310 return VINF_SUCCESS;
8311 }
8312
8313 /*
8314 * Fetch the invvpid descriptor from guest memory.
8315 */
8316 RTUINT128U uDesc;
8317 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8318 if (rcStrict == VINF_SUCCESS)
8319 {
8320 /*
8321 * Validate the descriptor.
8322 */
8323 if (uDesc.s.Lo > 0xfff)
8324 {
8325 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8326 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8327 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8328 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8329 return VINF_SUCCESS;
8330 }
8331
8332 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8333 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8334 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8335 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8336 switch (u64InvvpidType)
8337 {
8338 case VMXTLBFLUSHVPID_INDIV_ADDR:
8339 {
8340 if (uVpid != 0)
8341 {
8342 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8343 {
8344 /* Invalidate mappings for the linear address tagged with VPID. */
8345 /** @todo PGM support for VPID? Currently just flush everything. */
8346 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8347 iemVmxVmSucceed(pVCpu);
8348 }
8349 else
8350 {
8351 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8352 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8353 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8354 }
8355 }
8356 else
8357 {
8358 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8359 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8360 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8361 }
8362 break;
8363 }
8364
8365 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8366 {
8367 if (uVpid != 0)
8368 {
8369 /* Invalidate all mappings with VPID. */
8370 /** @todo PGM support for VPID? Currently just flush everything. */
8371 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8372 iemVmxVmSucceed(pVCpu);
8373 }
8374 else
8375 {
8376 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8377 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8378 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8379 }
8380 break;
8381 }
8382
8383 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8384 {
8385 /* Invalidate all mappings with non-zero VPIDs. */
8386 /** @todo PGM support for VPID? Currently just flush everything. */
8387 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8388 iemVmxVmSucceed(pVCpu);
8389 break;
8390 }
8391
8392 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8393 {
8394 if (uVpid != 0)
8395 {
8396 /* Invalidate all mappings with VPID except global translations. */
8397 /** @todo PGM support for VPID? Currently just flush everything. */
8398 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8399 iemVmxVmSucceed(pVCpu);
8400 }
8401 else
8402 {
8403 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8405 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8406 }
8407 break;
8408 }
8409 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8410 }
8411 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8412 }
8413 return rcStrict;
8414}
8415
8416
8417/**
8418 * VMXON instruction execution worker.
8419 *
8420 * @returns Strict VBox status code.
8421 * @param pVCpu The cross context virtual CPU structure.
8422 * @param cbInstr The instruction length in bytes.
8423 * @param iEffSeg The effective segment register to use with @a
8424 * GCPtrVmxon.
8425 * @param GCPtrVmxon The linear address of the VMXON pointer.
8426 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8427 * NULL.
8428 *
8429 * @remarks Common VMX instruction checks are already expected to by the caller,
8430 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8431 */
8432IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8433 PCVMXVEXITINFO pExitInfo)
8434{
8435 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8436 {
8437 /* CPL. */
8438 if (pVCpu->iem.s.uCpl == 0)
8439 { /* likely */ }
8440 else
8441 {
8442 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8444 return iemRaiseGeneralProtectionFault0(pVCpu);
8445 }
8446
8447 /* A20M (A20 Masked) mode. */
8448 if (PGMPhysIsA20Enabled(pVCpu))
8449 { /* likely */ }
8450 else
8451 {
8452 Log(("vmxon: A20M mode -> #GP(0)\n"));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8454 return iemRaiseGeneralProtectionFault0(pVCpu);
8455 }
8456
8457 /* CR0. */
8458 {
8459 /* CR0 MB1 bits. */
8460 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8461 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8462 { /* likely */ }
8463 else
8464 {
8465 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8466 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8467 return iemRaiseGeneralProtectionFault0(pVCpu);
8468 }
8469
8470 /* CR0 MBZ bits. */
8471 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8472 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8473 { /* likely */ }
8474 else
8475 {
8476 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8478 return iemRaiseGeneralProtectionFault0(pVCpu);
8479 }
8480 }
8481
8482 /* CR4. */
8483 {
8484 /* CR4 MB1 bits. */
8485 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8486 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8487 { /* likely */ }
8488 else
8489 {
8490 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8492 return iemRaiseGeneralProtectionFault0(pVCpu);
8493 }
8494
8495 /* CR4 MBZ bits. */
8496 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8497 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8498 { /* likely */ }
8499 else
8500 {
8501 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8502 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8503 return iemRaiseGeneralProtectionFault0(pVCpu);
8504 }
8505 }
8506
8507 /* Feature control MSR's LOCK and VMXON bits. */
8508 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8509 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8510 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8511 { /* likely */ }
8512 else
8513 {
8514 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8516 return iemRaiseGeneralProtectionFault0(pVCpu);
8517 }
8518
8519 /* Get the VMXON pointer from the location specified by the source memory operand. */
8520 RTGCPHYS GCPhysVmxon;
8521 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8522 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8523 { /* likely */ }
8524 else
8525 {
8526 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8527 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8528 return rcStrict;
8529 }
8530
8531 /* VMXON region pointer alignment. */
8532 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8533 { /* likely */ }
8534 else
8535 {
8536 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8537 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8538 iemVmxVmFailInvalid(pVCpu);
8539 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8540 return VINF_SUCCESS;
8541 }
8542
8543 /* VMXON physical-address width limits. */
8544 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8545 { /* likely */ }
8546 else
8547 {
8548 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8550 iemVmxVmFailInvalid(pVCpu);
8551 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8552 return VINF_SUCCESS;
8553 }
8554
8555 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8556 restriction imposed by our implementation. */
8557 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8558 { /* likely */ }
8559 else
8560 {
8561 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8563 iemVmxVmFailInvalid(pVCpu);
8564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8565 return VINF_SUCCESS;
8566 }
8567
8568 /* Read the VMCS revision ID from the VMXON region. */
8569 VMXVMCSREVID VmcsRevId;
8570 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8571 if (RT_SUCCESS(rc))
8572 { /* likely */ }
8573 else
8574 {
8575 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8576 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8577 return rc;
8578 }
8579
8580 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8581 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8582 { /* likely */ }
8583 else
8584 {
8585 /* Revision ID mismatch. */
8586 if (!VmcsRevId.n.fIsShadowVmcs)
8587 {
8588 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8589 VmcsRevId.n.u31RevisionId));
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8591 iemVmxVmFailInvalid(pVCpu);
8592 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8593 return VINF_SUCCESS;
8594 }
8595
8596 /* Shadow VMCS disallowed. */
8597 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8598 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8599 iemVmxVmFailInvalid(pVCpu);
8600 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8601 return VINF_SUCCESS;
8602 }
8603
8604 /*
8605 * Record that we're in VMX operation, block INIT, block and disable A20M.
8606 */
8607 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8608 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8609 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8610
8611 /* Clear address-range monitoring. */
8612 EMMonitorWaitClear(pVCpu);
8613 /** @todo NSTVMX: Intel PT. */
8614
8615 iemVmxVmSucceed(pVCpu);
8616 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8617 return VINF_SUCCESS;
8618 }
8619 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8620 {
8621 /* Nested-guest intercept. */
8622 if (pExitInfo)
8623 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8624 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8625 }
8626
8627 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8628
8629 /* CPL. */
8630 if (pVCpu->iem.s.uCpl > 0)
8631 {
8632 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8634 return iemRaiseGeneralProtectionFault0(pVCpu);
8635 }
8636
8637 /* VMXON when already in VMX root mode. */
8638 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8640 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8641 return VINF_SUCCESS;
8642}
8643
8644
8645/**
8646 * Implements 'VMXOFF'.
8647 *
8648 * @remarks Common VMX instruction checks are already expected to by the caller,
8649 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8650 */
8651IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8652{
8653 /* Nested-guest intercept. */
8654 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8655 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8656
8657 /* CPL. */
8658 if (pVCpu->iem.s.uCpl == 0)
8659 { /* likely */ }
8660 else
8661 {
8662 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8663 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8664 return iemRaiseGeneralProtectionFault0(pVCpu);
8665 }
8666
8667 /* Dual monitor treatment of SMIs and SMM. */
8668 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8669 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8670 { /* likely */ }
8671 else
8672 {
8673 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8674 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8675 return VINF_SUCCESS;
8676 }
8677
8678 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8679 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8680 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8681
8682 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8683 { /** @todo NSTVMX: Unblock SMI. */ }
8684
8685 EMMonitorWaitClear(pVCpu);
8686 /** @todo NSTVMX: Unblock and enable A20M. */
8687
8688 iemVmxVmSucceed(pVCpu);
8689 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8690 return VINF_SUCCESS;
8691}
8692
8693
8694/**
8695 * Implements 'VMXON'.
8696 */
8697IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8698{
8699 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8700}
8701
8702
8703/**
8704 * Implements 'VMLAUNCH'.
8705 */
8706IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8707{
8708 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8709}
8710
8711
8712/**
8713 * Implements 'VMRESUME'.
8714 */
8715IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8716{
8717 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8718}
8719
8720
8721/**
8722 * Implements 'VMPTRLD'.
8723 */
8724IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8725{
8726 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8727}
8728
8729
8730/**
8731 * Implements 'VMPTRST'.
8732 */
8733IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8734{
8735 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8736}
8737
8738
8739/**
8740 * Implements 'VMCLEAR'.
8741 */
8742IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8743{
8744 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8745}
8746
8747
8748/**
8749 * Implements 'VMWRITE' register.
8750 */
8751IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8752{
8753 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8754}
8755
8756
8757/**
8758 * Implements 'VMWRITE' memory.
8759 */
8760IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8761{
8762 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8763}
8764
8765
8766/**
8767 * Implements 'VMREAD' register (64-bit).
8768 */
8769IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8770{
8771 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8772}
8773
8774
8775/**
8776 * Implements 'VMREAD' register (32-bit).
8777 */
8778IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8779{
8780 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8781}
8782
8783
8784/**
8785 * Implements 'VMREAD' memory, 64-bit register.
8786 */
8787IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8788{
8789 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8790}
8791
8792
8793/**
8794 * Implements 'VMREAD' memory, 32-bit register.
8795 */
8796IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8797{
8798 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8799}
8800
8801
8802/**
8803 * Implements 'INVVPID'.
8804 */
8805IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8806{
8807 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8808}
8809
8810
8811/**
8812 * Implements VMX's implementation of PAUSE.
8813 */
8814IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8815{
8816 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8817 {
8818 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8819 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8820 return rcStrict;
8821 }
8822
8823 /*
8824 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8825 * a VM-exit, the instruction operates normally.
8826 */
8827 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8828 return VINF_SUCCESS;
8829}
8830
8831#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8832
8833
8834/**
8835 * Implements 'VMCALL'.
8836 */
8837IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8838{
8839#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8840 /* Nested-guest intercept. */
8841 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8842 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8843#endif
8844
8845 /* Join forces with vmmcall. */
8846 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8847}
8848
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