VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92679

Last change on this file since 92679 was 92626, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Adjust PGM APIs and translate nested-guest CR3 prior to mapping them when switching mode and other places.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 358.5 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp.h 92626 2021-11-29 12:32:58Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason and logs. */
156# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 } while (0)
163
164/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
165# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
166 do \
167 { \
168 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
169 return VERR_VMX_VMEXIT_FAILED; \
170 } while (0)
171
172
173/*********************************************************************************************************************************
174* Global Variables *
175*********************************************************************************************************************************/
176/** @todo NSTVMX: The following VM-exit intercepts are pending:
177 * VMX_EXIT_IO_SMI
178 * VMX_EXIT_SMI
179 * VMX_EXIT_GETSEC
180 * VMX_EXIT_RSM
181 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
182 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
183 * VMX_EXIT_EPT_VIOLATION
184 * VMX_EXIT_EPT_MISCONFIG
185 * VMX_EXIT_INVEPT
186 * VMX_EXIT_RDRAND
187 * VMX_EXIT_VMFUNC
188 * VMX_EXIT_ENCLS
189 * VMX_EXIT_RDSEED
190 * VMX_EXIT_PML_FULL
191 * VMX_EXIT_XSAVES
192 * VMX_EXIT_XRSTORS
193 */
194/**
195 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
196 *
197 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
198 * second dimension is the Index, see VMXVMCSFIELD.
199 */
200uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
201{
202 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
203 {
204 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
205 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
206 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
207 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 27 */ UINT16_MAX,
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
213 {
214 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
215 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
216 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
218 },
219 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
220 {
221 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
222 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
223 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
224 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
225 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
226 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
227 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
228 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
229 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
230 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
231 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 26-27 */ UINT16_MAX, UINT16_MAX
234 },
235 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
244 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
257 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
258 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
259 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
260 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
261 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
262 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
263 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
264 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
265 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
266 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
267 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
268 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
269 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
270 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
271 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
272 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
273 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
274 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
275 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
276 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
277 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
278 },
279 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
280 {
281 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
282 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
284 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
285 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
286 },
287 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
288 {
289 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
290 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
291 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
292 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
293 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
294 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
295 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
296 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
297 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
298 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
299 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
300 /* 11 */ UINT16_MAX,
301 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
302 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
303 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
304 },
305 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
306 {
307 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
308 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
309 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
310 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
311 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
313 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
314 },
315 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
316 {
317 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
318 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
319 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
320 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
321 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
322 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
323 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
324 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
325 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
326 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
327 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
328 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
329 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
330 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
331 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
332 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
333 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
334 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
335 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 26-27 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
348 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
349 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
350 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
351 },
352 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
353 {
354 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
355 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
356 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
357 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
358 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
359 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
360 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
361 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
362 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
363 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
364 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
365 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
366 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
367 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
368 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
369 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
370 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
371 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
372 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
373 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
374 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
375 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
376 /* 22 */ UINT16_MAX,
377 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
378 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
379 },
380 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
381 {
382 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
383 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
386 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
387 },
388 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
389 {
390 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
391 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
392 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
393 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
394 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
395 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
396 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
397 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
398 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
399 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
401 },
402 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
403 {
404 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
405 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
406 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
407 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
408 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
409 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
410 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
413 },
414 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
415 {
416 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
417 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
418 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
419 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
420 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
421 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
422 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
423 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
424 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
425 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
426 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
427 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
428 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
429 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
430 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
431 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
432 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
433 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
434 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
435 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
436 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
437 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
438 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
439 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
440 },
441 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
442 {
443 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
444 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
445 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
446 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
447 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
448 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
449 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
450 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
451 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
452 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
453 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
454 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
455 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
456 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
457 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
458 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
459 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
460 }
461};
462
463
464/**
465 * Gets a host selector from the VMCS.
466 *
467 * @param pVmcs Pointer to the virtual VMCS.
468 * @param iSelReg The index of the segment register (X86_SREG_XXX).
469 */
470DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
471{
472 Assert(iSegReg < X86_SREG_COUNT);
473 RTSEL HostSel;
474 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
475 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
476 uint8_t const uWidthType = (uWidth << 2) | uType;
477 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
478 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
479 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
480 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
481 uint8_t const *pbField = pbVmcs + offField;
482 HostSel = *(uint16_t *)pbField;
483 return HostSel;
484}
485
486
487/**
488 * Sets a guest segment register in the VMCS.
489 *
490 * @param pVmcs Pointer to the virtual VMCS.
491 * @param iSegReg The index of the segment register (X86_SREG_XXX).
492 * @param pSelReg Pointer to the segment register.
493 */
494IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
495{
496 Assert(pSelReg);
497 Assert(iSegReg < X86_SREG_COUNT);
498
499 /* Selector. */
500 {
501 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
502 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
503 uint8_t const uWidthType = (uWidth << 2) | uType;
504 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
505 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
506 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
507 uint8_t *pbVmcs = (uint8_t *)pVmcs;
508 uint8_t *pbField = pbVmcs + offField;
509 *(uint16_t *)pbField = pSelReg->Sel;
510 }
511
512 /* Limit. */
513 {
514 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
515 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
516 uint8_t const uWidthType = (uWidth << 2) | uType;
517 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
518 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
519 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
520 uint8_t *pbVmcs = (uint8_t *)pVmcs;
521 uint8_t *pbField = pbVmcs + offField;
522 *(uint32_t *)pbField = pSelReg->u32Limit;
523 }
524
525 /* Base. */
526 {
527 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
528 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
529 uint8_t const uWidthType = (uWidth << 2) | uType;
530 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
531 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
532 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
533 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
534 uint8_t const *pbField = pbVmcs + offField;
535 *(uint64_t *)pbField = pSelReg->u64Base;
536 }
537
538 /* Attributes. */
539 {
540 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
541 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
542 | X86DESCATTR_UNUSABLE;
543 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
544 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
545 uint8_t const uWidthType = (uWidth << 2) | uType;
546 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
547 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
548 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
549 uint8_t *pbVmcs = (uint8_t *)pVmcs;
550 uint8_t *pbField = pbVmcs + offField;
551 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
552 }
553}
554
555
556/**
557 * Gets a guest segment register from the VMCS.
558 *
559 * @returns VBox status code.
560 * @param pVmcs Pointer to the virtual VMCS.
561 * @param iSegReg The index of the segment register (X86_SREG_XXX).
562 * @param pSelReg Where to store the segment register (only updated when
563 * VINF_SUCCESS is returned).
564 *
565 * @remarks Warning! This does not validate the contents of the retrieved segment
566 * register.
567 */
568IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
569{
570 Assert(pSelReg);
571 Assert(iSegReg < X86_SREG_COUNT);
572
573 /* Selector. */
574 uint16_t u16Sel;
575 {
576 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
577 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
578 uint8_t const uWidthType = (uWidth << 2) | uType;
579 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
580 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
581 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
582 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
583 uint8_t const *pbField = pbVmcs + offField;
584 u16Sel = *(uint16_t *)pbField;
585 }
586
587 /* Limit. */
588 uint32_t u32Limit;
589 {
590 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
591 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
592 uint8_t const uWidthType = (uWidth << 2) | uType;
593 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
594 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
595 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
596 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
597 uint8_t const *pbField = pbVmcs + offField;
598 u32Limit = *(uint32_t *)pbField;
599 }
600
601 /* Base. */
602 uint64_t u64Base;
603 {
604 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
605 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
606 uint8_t const uWidthType = (uWidth << 2) | uType;
607 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
608 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
609 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
610 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
611 uint8_t const *pbField = pbVmcs + offField;
612 u64Base = *(uint64_t *)pbField;
613 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
614 }
615
616 /* Attributes. */
617 uint32_t u32Attr;
618 {
619 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
620 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
621 uint8_t const uWidthType = (uWidth << 2) | uType;
622 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
623 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
624 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
625 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
626 uint8_t const *pbField = pbVmcs + offField;
627 u32Attr = *(uint32_t *)pbField;
628 }
629
630 pSelReg->Sel = u16Sel;
631 pSelReg->ValidSel = u16Sel;
632 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
633 pSelReg->u32Limit = u32Limit;
634 pSelReg->u64Base = u64Base;
635 pSelReg->Attr.u = u32Attr;
636 return VINF_SUCCESS;
637}
638
639
640/**
641 * Converts an IEM exception event type to a VMX event type.
642 *
643 * @returns The VMX event type.
644 * @param uVector The interrupt / exception vector.
645 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
646 */
647DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
648{
649 /* Paranoia (callers may use these interchangeably). */
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
662
663 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
664 {
665 if (uVector == X86_XCPT_NMI)
666 return VMX_EXIT_INT_INFO_TYPE_NMI;
667 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
668 }
669
670 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
671 {
672 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
673 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
674 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
675 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
676 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
677 }
678
679 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
680 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
681}
682
683
684/**
685 * Determines whether the guest is using PAE paging given the VMCS.
686 *
687 * @returns @c true if PAE paging mode is used, @c false otherwise.
688 * @param pVmcs Pointer to the virtual VMCS.
689 */
690DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
691{
692 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
693 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
694 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
695}
696
697
698/**
699 * Sets the Exit qualification VMCS field.
700 *
701 * @param pVCpu The cross context virtual CPU structure.
702 * @param u64ExitQual The Exit qualification.
703 */
704DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
705{
706 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
707}
708
709
710/**
711 * Sets the VM-exit interruption information field.
712 *
713 * @param pVCpu The cross context virtual CPU structure.
714 * @param uExitIntInfo The VM-exit interruption information.
715 */
716DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
717{
718 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
719}
720
721
722/**
723 * Sets the VM-exit interruption error code.
724 *
725 * @param pVCpu The cross context virtual CPU structure.
726 * @param uErrCode The error code.
727 */
728DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
729{
730 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
731}
732
733
734/**
735 * Sets the IDT-vectoring information field.
736 *
737 * @param pVCpu The cross context virtual CPU structure.
738 * @param uIdtVectorInfo The IDT-vectoring information.
739 */
740DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
741{
742 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
743}
744
745
746/**
747 * Sets the IDT-vectoring error code field.
748 *
749 * @param pVCpu The cross context virtual CPU structure.
750 * @param uErrCode The error code.
751 */
752DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
753{
754 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
755}
756
757
758/**
759 * Sets the VM-exit guest-linear address VMCS field.
760 *
761 * @param pVCpu The cross context virtual CPU structure.
762 * @param uGuestLinearAddr The VM-exit guest-linear address.
763 */
764DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
765{
766 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
767}
768
769
770/**
771 * Sets the VM-exit guest-physical address VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uGuestPhysAddr The VM-exit guest-physical address.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
777{
778 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
779}
780
781
782/**
783 * Sets the VM-exit instruction length VMCS field.
784 *
785 * @param pVCpu The cross context virtual CPU structure.
786 * @param cbInstr The VM-exit instruction length in bytes.
787 *
788 * @remarks Callers may clear this field to 0. Hence, this function does not check
789 * the validity of the instruction length.
790 */
791DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
792{
793 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
794}
795
796
797/**
798 * Sets the VM-exit instruction info. VMCS field.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 * @param uExitInstrInfo The VM-exit instruction information.
802 */
803DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
804{
805 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
806}
807
808
809/**
810 * Sets the guest pending-debug exceptions field.
811 *
812 * @param pVCpu The cross context virtual CPU structure.
813 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
814 */
815DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
816{
817 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
818 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
819}
820
821
822/**
823 * Implements VMSucceed for VMX instruction success.
824 *
825 * @param pVCpu The cross context virtual CPU structure.
826 */
827DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
828{
829 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
830}
831
832
833/**
834 * Implements VMFailInvalid for VMX instruction failure.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 */
838DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
839{
840 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
841}
842
843
844/**
845 * Implements VMFail for VMX instruction failure.
846 *
847 * @param pVCpu The cross context virtual CPU structure.
848 * @param enmInsErr The VM instruction error.
849 */
850DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
851{
852 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
853}
854
855
856/**
857 * Checks if the given auto-load/store MSR area count is valid for the
858 * implementation.
859 *
860 * @returns @c true if it's within the valid limit, @c false otherwise.
861 * @param pVCpu The cross context virtual CPU structure.
862 * @param uMsrCount The MSR area count to check.
863 */
864DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
865{
866 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
867 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
868 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
869 if (uMsrCount <= cMaxSupportedMsrs)
870 return true;
871 return false;
872}
873
874
875/**
876 * Flushes the current VMCS contents back to guest memory.
877 *
878 * @returns VBox status code.
879 * @param pVCpu The cross context virtual CPU structure.
880 */
881DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
882{
883 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
884 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
885 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
886 return rc;
887}
888
889
890/**
891 * Populates the current VMCS contents from guest memory.
892 *
893 * @returns VBox status code.
894 * @param pVCpu The cross context virtual CPU structure.
895 */
896DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
897{
898 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
899 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
900 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
901 return rc;
902}
903
904
905/**
906 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
907 *
908 * @param pVCpu The cross context virtual CPU structure.
909 */
910DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
911{
912 iemVmxVmSucceed(pVCpu);
913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment base checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
982 * nested-guest that is in Virtual-8086 mode.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes reserved bits failure
1003 * during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attributes descriptor-type
1045 * (code/segment or system) failure during VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1060 }
1061}
1062
1063
1064/**
1065 * Gets the instruction diagnostic for segment attribute granularity failure during
1066 * VM-entry of a nested-guest.
1067 *
1068 * @param iSegReg The segment index (X86_SREG_XXX).
1069 */
1070IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1071{
1072 switch (iSegReg)
1073 {
1074 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1075 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1076 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1077 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1078 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1079 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1080 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1081 }
1082}
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1086 * VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1101 }
1102}
1103
1104
1105/**
1106 * Gets the instruction diagnostic for segment attribute type accessed failure
1107 * during VM-entry of a nested-guest.
1108 *
1109 * @param iSegReg The segment index (X86_SREG_XXX).
1110 */
1111IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1112{
1113 switch (iSegReg)
1114 {
1115 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1116 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1117 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1118 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1119 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1120 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1121 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1122 }
1123}
1124
1125
1126/**
1127 * Saves the guest control registers, debug registers and some MSRs are part of
1128 * VM-exit.
1129 *
1130 * @param pVCpu The cross context virtual CPU structure.
1131 */
1132IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1133{
1134 /*
1135 * Saves the guest control registers, debug registers and some MSRs.
1136 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1137 */
1138 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1139
1140 /* Save control registers. */
1141 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1142 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1143 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1144
1145 /* Save SYSENTER CS, ESP, EIP. */
1146 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1147 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1148 {
1149 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1150 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1151 }
1152 else
1153 {
1154 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1155 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1156 }
1157
1158 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1159 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1160 {
1161 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1162 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1163 }
1164
1165 /* Save PAT MSR. */
1166 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1167 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1168
1169 /* Save EFER MSR. */
1170 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1171 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1172
1173 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1174 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1175
1176 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1177}
1178
1179
1180/**
1181 * Saves the guest force-flags in preparation of entering the nested-guest.
1182 *
1183 * @param pVCpu The cross context virtual CPU structure.
1184 */
1185IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1186{
1187 /* We shouldn't be called multiple times during VM-entry. */
1188 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1189
1190 /* MTF should not be set outside VMX non-root mode. */
1191 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1192
1193 /*
1194 * Preserve the required force-flags.
1195 *
1196 * We cache and clear force-flags that would affect the execution of the
1197 * nested-guest. Cached flags are then restored while returning to the guest
1198 * if necessary.
1199 *
1200 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1201 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1202 * instruction. Interrupt inhibition for any nested-guest instruction
1203 * is supplied by the guest-interruptibility state VMCS field and will
1204 * be set up as part of loading the guest state.
1205 *
1206 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1207 * successful VM-entry (due to invalid guest-state) need to continue
1208 * blocking NMIs if it was in effect before VM-entry.
1209 *
1210 * - MTF need not be preserved as it's used only in VMX non-root mode and
1211 * is supplied through the VM-execution controls.
1212 *
1213 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1214 * we will be able to generate interrupts that may cause VM-exits for
1215 * the nested-guest.
1216 */
1217 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1218}
1219
1220
1221/**
1222 * Restores the guest force-flags in preparation of exiting the nested-guest.
1223 *
1224 * @param pVCpu The cross context virtual CPU structure.
1225 */
1226IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1227{
1228 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1229 {
1230 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1231 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1232 }
1233}
1234
1235
1236/**
1237 * Performs the VMX transition to/from VMX non-root mode.
1238 *
1239 * @param pVCpu The cross context virtual CPU structure.
1240*/
1241IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu)
1242{
1243 /*
1244 * Inform PGM about paging mode changes.
1245 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1246 * see comment in iemMemPageTranslateAndCheckAccess().
1247 */
1248 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1249 true /* fForce */);
1250 AssertRCReturn(rc, rc);
1251
1252 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1253 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
1254
1255 /* Inform CPUM (recompiler), can later be removed. */
1256 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1257
1258 /* Re-initialize IEM cache/state after the drastic mode switch. */
1259 iemReInitExec(pVCpu);
1260 return rc;
1261}
1262
1263
1264/**
1265 * Calculates the current VMX-preemption timer value.
1266 *
1267 * @returns The current VMX-preemption timer value.
1268 * @param pVCpu The cross context virtual CPU structure.
1269 */
1270IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1271{
1272 /*
1273 * Assume the following:
1274 * PreemptTimerShift = 5
1275 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1276 * EntryTick = 50000 (TSC at time of VM-entry)
1277 *
1278 * CurTick Delta PreemptTimerVal
1279 * ----------------------------------
1280 * 60000 10000 2
1281 * 80000 30000 1
1282 * 90000 40000 0 -> VM-exit.
1283 *
1284 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1285 * The saved VMX-preemption timer value is calculated as follows:
1286 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1287 * E.g.:
1288 * Delta = 10000
1289 * Tmp = 10000 / (2 * 10000) = 0.5
1290 * NewPt = 2 - 0.5 = 2
1291 * Delta = 30000
1292 * Tmp = 30000 / (2 * 10000) = 1.5
1293 * NewPt = 2 - 1.5 = 1
1294 * Delta = 40000
1295 * Tmp = 40000 / 20000 = 2
1296 * NewPt = 2 - 2 = 0
1297 */
1298 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1299 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1300 if (uVmcsPreemptVal > 0)
1301 {
1302 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1303 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1304 uint64_t const uDelta = uCurTick - uEntryTick;
1305 uint32_t const uPreemptTimer = uVmcsPreemptVal
1306 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1307 return uPreemptTimer;
1308 }
1309 return 0;
1310}
1311
1312
1313/**
1314 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1315 *
1316 * @param pVCpu The cross context virtual CPU structure.
1317 */
1318IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1319{
1320 /*
1321 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1322 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1323 */
1324 /* CS, SS, ES, DS, FS, GS. */
1325 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1326 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1327 {
1328 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1329 if (!pSelReg->Attr.n.u1Unusable)
1330 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1331 else
1332 {
1333 /*
1334 * For unusable segments the attributes are undefined except for CS and SS.
1335 * For the rest we don't bother preserving anything but the unusable bit.
1336 */
1337 switch (iSegReg)
1338 {
1339 case X86_SREG_CS:
1340 pVmcs->GuestCs = pSelReg->Sel;
1341 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1342 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1343 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1344 | X86DESCATTR_UNUSABLE);
1345 break;
1346
1347 case X86_SREG_SS:
1348 pVmcs->GuestSs = pSelReg->Sel;
1349 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1350 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1351 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1352 break;
1353
1354 case X86_SREG_DS:
1355 pVmcs->GuestDs = pSelReg->Sel;
1356 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1357 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1358 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1359 break;
1360
1361 case X86_SREG_ES:
1362 pVmcs->GuestEs = pSelReg->Sel;
1363 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1364 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1365 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1366 break;
1367
1368 case X86_SREG_FS:
1369 pVmcs->GuestFs = pSelReg->Sel;
1370 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1371 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1372 break;
1373
1374 case X86_SREG_GS:
1375 pVmcs->GuestGs = pSelReg->Sel;
1376 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1377 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1378 break;
1379 }
1380 }
1381 }
1382
1383 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1384 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1385 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1386 | X86DESCATTR_UNUSABLE;
1387 /* LDTR. */
1388 {
1389 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1390 pVmcs->GuestLdtr = pSelReg->Sel;
1391 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1392 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1393 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1394 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1395 }
1396
1397 /* TR. */
1398 {
1399 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1400 pVmcs->GuestTr = pSelReg->Sel;
1401 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1403 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1404 }
1405
1406 /* GDTR. */
1407 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1408 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1409
1410 /* IDTR. */
1411 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1412 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1413}
1414
1415
1416/**
1417 * Saves guest non-register state as part of VM-exit.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uExitReason The VM-exit reason.
1421 */
1422IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1423{
1424 /*
1425 * Save guest non-register state.
1426 * See Intel spec. 27.3.4 "Saving Non-Register State".
1427 */
1428 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1429
1430 /*
1431 * Activity state.
1432 * Most VM-exits will occur in the active state. However, if the first instruction
1433 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1434 * the VM-exit will be from the HLT activity state.
1435 *
1436 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1437 */
1438 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1439 * not? */
1440 EMSTATE const enmActivityState = EMGetState(pVCpu);
1441 switch (enmActivityState)
1442 {
1443 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1444 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1445 }
1446
1447 /*
1448 * Interruptibility-state.
1449 */
1450 /* NMI. */
1451 pVmcs->u32GuestIntrState = 0;
1452 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1453 {
1454 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1455 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1456 }
1457 else
1458 {
1459 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1460 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1461 }
1462
1463 /* Blocking-by-STI. */
1464 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1465 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1466 {
1467 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1468 * currently. */
1469 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1470 }
1471 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1472
1473 /*
1474 * Pending debug exceptions.
1475 *
1476 * For VM-exits where it is not applicable, we can safely zero out the field.
1477 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1478 */
1479 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1480 && uExitReason != VMX_EXIT_SMI
1481 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1482 && !VMXIsVmexitTrapLike(uExitReason))
1483 {
1484 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1485 * block-by-MovSS is in effect. */
1486 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1487 }
1488
1489 /*
1490 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1491 *
1492 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1493 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1494 */
1495 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1496 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1497 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1498
1499 /*
1500 * PAE PDPTEs.
1501 *
1502 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1503 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1504 * we zero them for consistency.
1505 */
1506 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1507 {
1508 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1509 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1510 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1511 {
1512 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1513 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1514 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1515 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1516 }
1517 else
1518 {
1519 pVmcs->u64GuestPdpte0.u = 0;
1520 pVmcs->u64GuestPdpte1.u = 0;
1521 pVmcs->u64GuestPdpte2.u = 0;
1522 pVmcs->u64GuestPdpte3.u = 0;
1523 }
1524
1525 /* Clear PGM's copy of the EPT pointer for added safety. */
1526 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1527 }
1528 else
1529 {
1530 pVmcs->u64GuestPdpte0.u = 0;
1531 pVmcs->u64GuestPdpte1.u = 0;
1532 pVmcs->u64GuestPdpte2.u = 0;
1533 pVmcs->u64GuestPdpte3.u = 0;
1534 }
1535}
1536
1537
1538/**
1539 * Saves the guest-state as part of VM-exit.
1540 *
1541 * @returns VBox status code.
1542 * @param pVCpu The cross context virtual CPU structure.
1543 * @param uExitReason The VM-exit reason.
1544 */
1545IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1546{
1547 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1548 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1549
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1552 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1553
1554 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1555}
1556
1557
1558/**
1559 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1560 *
1561 * @returns VBox status code.
1562 * @param pVCpu The cross context virtual CPU structure.
1563 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1564 */
1565IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1566{
1567 /*
1568 * Save guest MSRs.
1569 * See Intel spec. 27.4 "Saving MSRs".
1570 */
1571 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1572 const char * const pszFailure = "VMX-abort";
1573
1574 /*
1575 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1576 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1577 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1578 */
1579 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1580 if (!cMsrs)
1581 return VINF_SUCCESS;
1582
1583 /*
1584 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1585 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1586 * implementation causes a VMX-abort followed by a triple-fault.
1587 */
1588 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1589 if (fIsMsrCountValid)
1590 { /* likely */ }
1591 else
1592 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1593
1594 /*
1595 * Optimization if the nested hypervisor is using the same guest-physical page for both
1596 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1597 */
1598 PVMXAUTOMSR pMsrArea;
1599 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1600 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1601 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1602 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1603 else
1604 {
1605 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1606 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1607 if (RT_SUCCESS(rc))
1608 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1609 else
1610 {
1611 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1612 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1613 }
1614 }
1615
1616 /*
1617 * Update VM-exit MSR store area.
1618 */
1619 PVMXAUTOMSR pMsr = pMsrArea;
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716
1717 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1718 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1719 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1720 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1721 }
1722
1723 /* CR4. */
1724 {
1725 /* CR4 fixed bits are not modified. */
1726 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1727 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1728 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1729 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1730 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1731 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1732 if (fHostInLongMode)
1733 uValidHostCr4 |= X86_CR4_PAE;
1734 else
1735 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1736
1737 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1738 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1739 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1740 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1741 }
1742
1743 /* CR3 (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1745
1746 /* DR7. */
1747 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1748
1749 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1750
1751 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1752 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1753 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1754 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1755
1756 /* FS, GS bases are loaded later while we load host segment registers. */
1757
1758 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1759 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1760 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1761 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1762 {
1763 if (fHostInLongMode)
1764 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1765 else
1766 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1767 }
1768
1769 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1770
1771 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1772 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1773 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1774
1775 /* We don't support IA32_BNDCFGS MSR yet. */
1776}
1777
1778
1779/**
1780 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1781 *
1782 * @param pVCpu The cross context virtual CPU structure.
1783 */
1784IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1785{
1786 /*
1787 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1788 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1789 *
1790 * Warning! Be careful to not touch fields that are reserved by VT-x,
1791 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1792 */
1793 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1794 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1795
1796 /* CS, SS, ES, DS, FS, GS. */
1797 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1798 {
1799 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1800 bool const fUnusable = RT_BOOL(HostSel == 0);
1801 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1802
1803 /* Selector. */
1804 pSelReg->Sel = HostSel;
1805 pSelReg->ValidSel = HostSel;
1806 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1807
1808 /* Limit. */
1809 pSelReg->u32Limit = 0xffffffff;
1810
1811 /* Base. */
1812 pSelReg->u64Base = 0;
1813
1814 /* Attributes. */
1815 if (iSegReg == X86_SREG_CS)
1816 {
1817 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1818 pSelReg->Attr.n.u1DescType = 1;
1819 pSelReg->Attr.n.u2Dpl = 0;
1820 pSelReg->Attr.n.u1Present = 1;
1821 pSelReg->Attr.n.u1Long = fHostInLongMode;
1822 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 Assert(!pSelReg->Attr.n.u1Unusable);
1825 Assert(!fUnusable);
1826 }
1827 else
1828 {
1829 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1830 pSelReg->Attr.n.u1DescType = 1;
1831 pSelReg->Attr.n.u2Dpl = 0;
1832 pSelReg->Attr.n.u1Present = 1;
1833 pSelReg->Attr.n.u1DefBig = 1;
1834 pSelReg->Attr.n.u1Granularity = 1;
1835 pSelReg->Attr.n.u1Unusable = fUnusable;
1836 }
1837 }
1838
1839 /* FS base. */
1840 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1844 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1845 }
1846
1847 /* GS base. */
1848 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1849 || fHostInLongMode)
1850 {
1851 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1852 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1853 }
1854
1855 /* TR. */
1856 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1857 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1858 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1860 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1861 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1862 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1869
1870 /* LDTR (Warning! do not touch the base and limits here). */
1871 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1873 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1874 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1875
1876 /* GDTR. */
1877 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1878 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1879 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1880
1881 /* IDTR.*/
1882 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1883 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1884 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1885}
1886
1887
1888/**
1889 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1890 *
1891 * @returns VBox status code.
1892 * @param pVCpu The cross context virtual CPU structure.
1893 * @param uExitReason The VMX instruction name (for logging purposes).
1894 */
1895IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1896{
1897 /*
1898 * Load host MSRs.
1899 * See Intel spec. 27.6 "Loading MSRs".
1900 */
1901 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1902 const char * const pszFailure = "VMX-abort";
1903
1904 /*
1905 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1906 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1907 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1908 */
1909 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1910 if (!cMsrs)
1911 return VINF_SUCCESS;
1912
1913 /*
1914 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1915 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1916 * implementation causes a VMX-abort followed by a triple-fault.
1917 */
1918 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1919 if (fIsMsrCountValid)
1920 { /* likely */ }
1921 else
1922 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1923
1924 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1925 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1926 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1927 if (RT_SUCCESS(rc))
1928 {
1929 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1930 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1931 {
1932 if ( !pMsr->u32Reserved
1933 && pMsr->u32Msr != MSR_K8_FS_BASE
1934 && pMsr->u32Msr != MSR_K8_GS_BASE
1935 && pMsr->u32Msr != MSR_K6_EFER
1936 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1937 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1938 {
1939 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1940 if (rcStrict == VINF_SUCCESS)
1941 continue;
1942
1943 /*
1944 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1945 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1946 * recording the MSR index in the auxiliary info. field and indicated further by our
1947 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1948 * if possible, or come up with a better, generic solution.
1949 */
1950 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1951 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1952 ? kVmxVDiag_Vmexit_MsrLoadRing3
1953 : kVmxVDiag_Vmexit_MsrLoad;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1955 }
1956 else
1957 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1958 }
1959 }
1960 else
1961 {
1962 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1964 }
1965
1966 NOREF(uExitReason);
1967 NOREF(pszFailure);
1968 return VINF_SUCCESS;
1969}
1970
1971
1972/**
1973 * Loads the host state as part of VM-exit.
1974 *
1975 * @returns Strict VBox status code.
1976 * @param pVCpu The cross context virtual CPU structure.
1977 * @param uExitReason The VM-exit reason (for logging purposes).
1978 */
1979IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1980{
1981 /*
1982 * Load host state.
1983 * See Intel spec. 27.5 "Loading Host State".
1984 */
1985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1986 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1987
1988 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1989 if ( CPUMIsGuestInLongMode(pVCpu)
1990 && !fHostInLongMode)
1991 {
1992 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1993 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1994 }
1995
1996 /*
1997 * Check host PAE PDPTEs prior to loading the host state.
1998 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1999 */
2000 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2001 && !fHostInLongMode
2002 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2003 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2004 {
2005 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2006 if (RT_SUCCESS(rc))
2007 { /* likely*/ }
2008 else
2009 {
2010 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2011 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2012 }
2013 }
2014
2015 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2016 iemVmxVmexitLoadHostSegRegs(pVCpu);
2017
2018 /*
2019 * Load host RIP, RSP and RFLAGS.
2020 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2021 */
2022 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2023 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2024 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2025
2026 /* Clear address range monitoring. */
2027 EMMonitorWaitClear(pVCpu);
2028
2029 /* Perform the VMX transition (PGM updates). */
2030 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2031 if (rcStrict == VINF_SUCCESS)
2032 { /* likely */ }
2033 else if (RT_SUCCESS(rcStrict))
2034 {
2035 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2036 uExitReason));
2037 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2038 }
2039 else
2040 {
2041 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2042 return VBOXSTRICTRC_VAL(rcStrict);
2043 }
2044
2045 Assert(rcStrict == VINF_SUCCESS);
2046
2047 /* Load MSRs from the VM-exit auto-load MSR area. */
2048 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2049 if (RT_FAILURE(rc))
2050 {
2051 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2052 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2053 }
2054 return VINF_SUCCESS;
2055}
2056
2057
2058/**
2059 * Gets VM-exit instruction information along with any displacement for an
2060 * instruction VM-exit.
2061 *
2062 * @returns The VM-exit instruction information.
2063 * @param pVCpu The cross context virtual CPU structure.
2064 * @param uExitReason The VM-exit reason.
2065 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2066 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2067 * NULL.
2068 */
2069IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2070{
2071 RTGCPTR GCPtrDisp;
2072 VMXEXITINSTRINFO ExitInstrInfo;
2073 ExitInstrInfo.u = 0;
2074
2075 /*
2076 * Get and parse the ModR/M byte from our decoded opcodes.
2077 */
2078 uint8_t bRm;
2079 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2080 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2081 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2082 {
2083 /*
2084 * ModR/M indicates register addressing.
2085 *
2086 * The primary/secondary register operands are reported in the iReg1 or iReg2
2087 * fields depending on whether it is a read/write form.
2088 */
2089 uint8_t idxReg1;
2090 uint8_t idxReg2;
2091 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2092 {
2093 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2094 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2095 }
2096 else
2097 {
2098 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2099 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2100 }
2101 ExitInstrInfo.All.u2Scaling = 0;
2102 ExitInstrInfo.All.iReg1 = idxReg1;
2103 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2104 ExitInstrInfo.All.fIsRegOperand = 1;
2105 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2106 ExitInstrInfo.All.iSegReg = 0;
2107 ExitInstrInfo.All.iIdxReg = 0;
2108 ExitInstrInfo.All.fIdxRegInvalid = 1;
2109 ExitInstrInfo.All.iBaseReg = 0;
2110 ExitInstrInfo.All.fBaseRegInvalid = 1;
2111 ExitInstrInfo.All.iReg2 = idxReg2;
2112
2113 /* Displacement not applicable for register addressing. */
2114 GCPtrDisp = 0;
2115 }
2116 else
2117 {
2118 /*
2119 * ModR/M indicates memory addressing.
2120 */
2121 uint8_t uScale = 0;
2122 bool fBaseRegValid = false;
2123 bool fIdxRegValid = false;
2124 uint8_t iBaseReg = 0;
2125 uint8_t iIdxReg = 0;
2126 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2127 {
2128 /*
2129 * Parse the ModR/M, displacement for 16-bit addressing mode.
2130 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2131 */
2132 uint16_t u16Disp = 0;
2133 uint8_t const offDisp = offModRm + sizeof(bRm);
2134 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2135 {
2136 /* Displacement without any registers. */
2137 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2138 }
2139 else
2140 {
2141 /* Register (index and base). */
2142 switch (bRm & X86_MODRM_RM_MASK)
2143 {
2144 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2145 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2146 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2147 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2148 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2149 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2150 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2151 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2152 }
2153
2154 /* Register + displacement. */
2155 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2156 {
2157 case 0: break;
2158 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2159 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2160 default:
2161 {
2162 /* Register addressing, handled at the beginning. */
2163 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2164 break;
2165 }
2166 }
2167 }
2168
2169 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2170 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2171 }
2172 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2173 {
2174 /*
2175 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2176 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2177 */
2178 uint32_t u32Disp = 0;
2179 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2180 {
2181 /* Displacement without any registers. */
2182 uint8_t const offDisp = offModRm + sizeof(bRm);
2183 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2184 }
2185 else
2186 {
2187 /* Register (and perhaps scale, index and base). */
2188 uint8_t offDisp = offModRm + sizeof(bRm);
2189 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2190 if (iBaseReg == 4)
2191 {
2192 /* An SIB byte follows the ModR/M byte, parse it. */
2193 uint8_t bSib;
2194 uint8_t const offSib = offModRm + sizeof(bRm);
2195 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2196
2197 /* A displacement may follow SIB, update its offset. */
2198 offDisp += sizeof(bSib);
2199
2200 /* Get the scale. */
2201 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2202
2203 /* Get the index register. */
2204 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2205 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2206
2207 /* Get the base register. */
2208 iBaseReg = bSib & X86_SIB_BASE_MASK;
2209 fBaseRegValid = true;
2210 if (iBaseReg == 5)
2211 {
2212 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2213 {
2214 /* Mod is 0 implies a 32-bit displacement with no base. */
2215 fBaseRegValid = false;
2216 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2217 }
2218 else
2219 {
2220 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2221 iBaseReg = X86_GREG_xBP;
2222 }
2223 }
2224 }
2225
2226 /* Register + displacement. */
2227 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2228 {
2229 case 0: /* Handled above */ break;
2230 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2231 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2232 default:
2233 {
2234 /* Register addressing, handled at the beginning. */
2235 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2236 break;
2237 }
2238 }
2239 }
2240
2241 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2242 }
2243 else
2244 {
2245 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2246
2247 /*
2248 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2249 * See Intel instruction spec. 2.2 "IA-32e Mode".
2250 */
2251 uint64_t u64Disp = 0;
2252 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2253 if (fRipRelativeAddr)
2254 {
2255 /*
2256 * RIP-relative addressing mode.
2257 *
2258 * The displacement is 32-bit signed implying an offset range of +/-2G.
2259 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2260 */
2261 uint8_t const offDisp = offModRm + sizeof(bRm);
2262 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2263 }
2264 else
2265 {
2266 uint8_t offDisp = offModRm + sizeof(bRm);
2267
2268 /*
2269 * Register (and perhaps scale, index and base).
2270 *
2271 * REX.B extends the most-significant bit of the base register. However, REX.B
2272 * is ignored while determining whether an SIB follows the opcode. Hence, we
2273 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2274 *
2275 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2276 */
2277 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2278 if (iBaseReg == 4)
2279 {
2280 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2281 uint8_t bSib;
2282 uint8_t const offSib = offModRm + sizeof(bRm);
2283 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2284
2285 /* Displacement may follow SIB, update its offset. */
2286 offDisp += sizeof(bSib);
2287
2288 /* Get the scale. */
2289 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2290
2291 /* Get the index. */
2292 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2293 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2294
2295 /* Get the base. */
2296 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2297 fBaseRegValid = true;
2298 if (iBaseReg == 5)
2299 {
2300 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2301 {
2302 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2303 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2304 }
2305 else
2306 {
2307 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2308 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2309 }
2310 }
2311 }
2312 iBaseReg |= pVCpu->iem.s.uRexB;
2313
2314 /* Register + displacement. */
2315 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2316 {
2317 case 0: /* Handled above */ break;
2318 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2319 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2320 default:
2321 {
2322 /* Register addressing, handled at the beginning. */
2323 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2324 break;
2325 }
2326 }
2327 }
2328
2329 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2330 }
2331
2332 /*
2333 * The primary or secondary register operand is reported in iReg2 depending
2334 * on whether the primary operand is in read/write form.
2335 */
2336 uint8_t idxReg2;
2337 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2338 {
2339 idxReg2 = bRm & X86_MODRM_RM_MASK;
2340 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2341 idxReg2 |= pVCpu->iem.s.uRexB;
2342 }
2343 else
2344 {
2345 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2346 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2347 idxReg2 |= pVCpu->iem.s.uRexReg;
2348 }
2349 ExitInstrInfo.All.u2Scaling = uScale;
2350 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2351 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2352 ExitInstrInfo.All.fIsRegOperand = 0;
2353 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2354 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2355 ExitInstrInfo.All.iIdxReg = iIdxReg;
2356 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2357 ExitInstrInfo.All.iBaseReg = iBaseReg;
2358 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2359 ExitInstrInfo.All.iReg2 = idxReg2;
2360 }
2361
2362 /*
2363 * Handle exceptions to the norm for certain instructions.
2364 * (e.g. some instructions convey an instruction identity in place of iReg2).
2365 */
2366 switch (uExitReason)
2367 {
2368 case VMX_EXIT_GDTR_IDTR_ACCESS:
2369 {
2370 Assert(VMXINSTRID_IS_VALID(uInstrId));
2371 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2372 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2373 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2374 break;
2375 }
2376
2377 case VMX_EXIT_LDTR_TR_ACCESS:
2378 {
2379 Assert(VMXINSTRID_IS_VALID(uInstrId));
2380 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2381 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2382 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2383 break;
2384 }
2385
2386 case VMX_EXIT_RDRAND:
2387 case VMX_EXIT_RDSEED:
2388 {
2389 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2390 break;
2391 }
2392 }
2393
2394 /* Update displacement and return the constructed VM-exit instruction information field. */
2395 if (pGCPtrDisp)
2396 *pGCPtrDisp = GCPtrDisp;
2397
2398 return ExitInstrInfo.u;
2399}
2400
2401
2402/**
2403 * VMX VM-exit handler.
2404 *
2405 * @returns Strict VBox status code.
2406 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2407 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2408 * triple-fault.
2409 *
2410 * @param pVCpu The cross context virtual CPU structure.
2411 * @param uExitReason The VM-exit reason.
2412 * @param u64ExitQual The Exit qualification.
2413 */
2414IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2415{
2416# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2417 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2418 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2419 return VERR_IEM_IPE_7;
2420# else
2421 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2422
2423 /*
2424 * Import all the guest-CPU state.
2425 *
2426 * HM on returning to guest execution would have to reset up a whole lot of state
2427 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2428 * the state and flag reloading the entire state on re-entry. So import the entire
2429 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2430 */
2431 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2432
2433 /*
2434 * Ensure VM-entry interruption information valid bit is cleared.
2435 *
2436 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2437 * by invalid-guest state or machine-check exceptions) also clear this bit.
2438 *
2439 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2440 */
2441 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2442 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2443
2444 /*
2445 * Update the VM-exit reason and Exit qualification.
2446 * Other VMCS read-only data fields are expected to be updated by the caller already.
2447 */
2448 pVmcs->u32RoExitReason = uExitReason;
2449 pVmcs->u64RoExitQual.u = u64ExitQual;
2450
2451 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2452 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2453 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2454
2455 /*
2456 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2457 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2458 */
2459 {
2460 uint8_t uVector;
2461 uint32_t fFlags;
2462 uint32_t uErrCode;
2463 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2464 if (fInEventDelivery)
2465 {
2466 /*
2467 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2468 * caused by a triple-fault or the original event results in a double-fault that
2469 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2470 * original event information into the IDT-vectoring information fields.
2471 *
2472 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2473 */
2474 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2475 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2476 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2477 {
2478 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2479 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2480 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2481 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2482 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2483 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2484 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2485 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2486 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2487 pVCpu->cpum.GstCtx.cr2));
2488 }
2489 }
2490 }
2491
2492 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2493 Assert(pVmcs->u64RoIoRcx.u == 0);
2494 Assert(pVmcs->u64RoIoRsi.u == 0);
2495 Assert(pVmcs->u64RoIoRdi.u == 0);
2496 Assert(pVmcs->u64RoIoRip.u == 0);
2497
2498 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2499 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2500 {
2501 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2502 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2503 }
2504
2505 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2506 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2507
2508 /*
2509 * Save the guest state back into the VMCS.
2510 * We only need to save the state when the VM-entry was successful.
2511 */
2512 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2513 if (!fVmentryFailed)
2514 {
2515 /*
2516 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2517 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2518 *
2519 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2520 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2521 * as guest-CPU state would not been modified. Hence for now, we do this only when
2522 * the VM-entry succeeded.
2523 */
2524 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2525 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2526 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2527 {
2528 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2529 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2530 else
2531 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2532 }
2533
2534 /*
2535 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2536 * occurs in enclave mode/SMM which we don't support yet.
2537 *
2538 * If we ever add support for it, we can pass just the lower bits to the functions
2539 * below, till then an assert should suffice.
2540 */
2541 Assert(!RT_HI_U16(uExitReason));
2542
2543 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2544 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2545 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2546 if (RT_SUCCESS(rc))
2547 { /* likely */ }
2548 else
2549 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2550
2551 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2552 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2553 }
2554 else
2555 {
2556 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2557 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2558 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2559 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2560 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2561 }
2562
2563 /*
2564 * Stop any running VMX-preemption timer if necessary.
2565 */
2566 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2567 CPUMStopGuestVmxPremptTimer(pVCpu);
2568
2569 /*
2570 * Clear any pending VMX nested-guest force-flags.
2571 * These force-flags have no effect on (outer) guest execution and will
2572 * be re-evaluated and setup on the next nested-guest VM-entry.
2573 */
2574 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2575
2576 /*
2577 * We're no longer in nested-guest execution mode.
2578 *
2579 * It is important to do this prior to loading the host state because
2580 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2581 * second-level address translation while switching to host CR3.
2582 */
2583 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2584
2585 /* Restore the host (outer guest) state. */
2586 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2587 if (RT_SUCCESS(rcStrict))
2588 {
2589 Assert(rcStrict == VINF_SUCCESS);
2590 rcStrict = VINF_VMX_VMEXIT;
2591 }
2592 else
2593 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2594
2595 /* Notify HM that the current VMCS fields have been modified. */
2596 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2597
2598 /* Notify HM that we've completed the VM-exit. */
2599 HMNotifyVmxNstGstVmexit(pVCpu);
2600
2601# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2602 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2603 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2604 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2605 if (rcSched != VINF_SUCCESS)
2606 iemSetPassUpStatus(pVCpu, rcSched);
2607# endif
2608 return rcStrict;
2609# endif
2610}
2611
2612
2613/**
2614 * VMX VM-exit handler for VM-exits due to instruction execution.
2615 *
2616 * This is intended for instructions where the caller provides all the relevant
2617 * VM-exit information.
2618 *
2619 * @returns Strict VBox status code.
2620 * @param pVCpu The cross context virtual CPU structure.
2621 * @param pExitInfo Pointer to the VM-exit information.
2622 */
2623IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2624{
2625 /*
2626 * For instructions where any of the following fields are not applicable:
2627 * - Exit qualification must be cleared.
2628 * - VM-exit instruction info. is undefined.
2629 * - Guest-linear address is undefined.
2630 * - Guest-physical address is undefined.
2631 *
2632 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2633 * instruction execution. For VM-exits that are not due to instruction execution this
2634 * field is undefined.
2635 *
2636 * In our implementation in IEM, all undefined fields are generally cleared. However,
2637 * if the caller supplies information (from say the physical CPU directly) it is
2638 * then possible that the undefined fields are not cleared.
2639 *
2640 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2641 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2642 */
2643 Assert(pExitInfo);
2644 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2645 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2646 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2647
2648 /* Update all the relevant fields from the VM-exit instruction information struct. */
2649 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2650 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2651 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2652 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2653
2654 /* Perform the VM-exit. */
2655 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2656}
2657
2658
2659/**
2660 * VMX VM-exit handler for VM-exits due to instruction execution.
2661 *
2662 * This is intended for instructions that only provide the VM-exit instruction
2663 * length.
2664 *
2665 * @param pVCpu The cross context virtual CPU structure.
2666 * @param uExitReason The VM-exit reason.
2667 * @param cbInstr The instruction length in bytes.
2668 */
2669IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2670{
2671 VMXVEXITINFO ExitInfo;
2672 RT_ZERO(ExitInfo);
2673 ExitInfo.uReason = uExitReason;
2674 ExitInfo.cbInstr = cbInstr;
2675
2676#ifdef VBOX_STRICT
2677 /*
2678 * To prevent us from shooting ourselves in the foot.
2679 * The follow instructions should convey more than just the instruction length.
2680 */
2681 switch (uExitReason)
2682 {
2683 case VMX_EXIT_INVEPT:
2684 case VMX_EXIT_INVPCID:
2685 case VMX_EXIT_INVVPID:
2686 case VMX_EXIT_LDTR_TR_ACCESS:
2687 case VMX_EXIT_GDTR_IDTR_ACCESS:
2688 case VMX_EXIT_VMCLEAR:
2689 case VMX_EXIT_VMPTRLD:
2690 case VMX_EXIT_VMPTRST:
2691 case VMX_EXIT_VMREAD:
2692 case VMX_EXIT_VMWRITE:
2693 case VMX_EXIT_VMXON:
2694 case VMX_EXIT_XRSTORS:
2695 case VMX_EXIT_XSAVES:
2696 case VMX_EXIT_RDRAND:
2697 case VMX_EXIT_RDSEED:
2698 case VMX_EXIT_IO_INSTR:
2699 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2700 break;
2701 }
2702#endif
2703
2704 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2705}
2706
2707
2708/**
2709 * VMX VM-exit handler for VM-exits due to instruction execution.
2710 *
2711 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2712 * instruction information and Exit qualification fields.
2713 *
2714 * @param pVCpu The cross context virtual CPU structure.
2715 * @param uExitReason The VM-exit reason.
2716 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2717 * @param cbInstr The instruction length in bytes.
2718 *
2719 * @remarks Do not use this for INS/OUTS instruction.
2720 */
2721IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2722{
2723 VMXVEXITINFO ExitInfo;
2724 RT_ZERO(ExitInfo);
2725 ExitInfo.uReason = uExitReason;
2726 ExitInfo.cbInstr = cbInstr;
2727
2728 /*
2729 * Update the Exit qualification field with displacement bytes.
2730 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2731 */
2732 switch (uExitReason)
2733 {
2734 case VMX_EXIT_INVEPT:
2735 case VMX_EXIT_INVPCID:
2736 case VMX_EXIT_INVVPID:
2737 case VMX_EXIT_LDTR_TR_ACCESS:
2738 case VMX_EXIT_GDTR_IDTR_ACCESS:
2739 case VMX_EXIT_VMCLEAR:
2740 case VMX_EXIT_VMPTRLD:
2741 case VMX_EXIT_VMPTRST:
2742 case VMX_EXIT_VMREAD:
2743 case VMX_EXIT_VMWRITE:
2744 case VMX_EXIT_VMXON:
2745 case VMX_EXIT_XRSTORS:
2746 case VMX_EXIT_XSAVES:
2747 case VMX_EXIT_RDRAND:
2748 case VMX_EXIT_RDSEED:
2749 {
2750 /* Construct the VM-exit instruction information. */
2751 RTGCPTR GCPtrDisp;
2752 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2753
2754 /* Update the VM-exit instruction information. */
2755 ExitInfo.InstrInfo.u = uInstrInfo;
2756
2757 /* Update the Exit qualification. */
2758 ExitInfo.u64Qual = GCPtrDisp;
2759 break;
2760 }
2761
2762 default:
2763 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2764 break;
2765 }
2766
2767 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2768}
2769
2770
2771/**
2772 * VMX VM-exit handler for VM-exits due to INVLPG.
2773 *
2774 * @returns Strict VBox status code.
2775 * @param pVCpu The cross context virtual CPU structure.
2776 * @param GCPtrPage The guest-linear address of the page being invalidated.
2777 * @param cbInstr The instruction length in bytes.
2778 */
2779IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2780{
2781 VMXVEXITINFO ExitInfo;
2782 RT_ZERO(ExitInfo);
2783 ExitInfo.uReason = VMX_EXIT_INVLPG;
2784 ExitInfo.cbInstr = cbInstr;
2785 ExitInfo.u64Qual = GCPtrPage;
2786 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2787
2788 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2789}
2790
2791
2792/**
2793 * VMX VM-exit handler for VM-exits due to LMSW.
2794 *
2795 * @returns Strict VBox status code.
2796 * @param pVCpu The cross context virtual CPU structure.
2797 * @param uGuestCr0 The current guest CR0.
2798 * @param pu16NewMsw The machine-status word specified in LMSW's source
2799 * operand. This will be updated depending on the VMX
2800 * guest/host CR0 mask if LMSW is not intercepted.
2801 * @param GCPtrEffDst The guest-linear address of the source operand in case
2802 * of a memory operand. For register operand, pass
2803 * NIL_RTGCPTR.
2804 * @param cbInstr The instruction length in bytes.
2805 */
2806IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2807 uint8_t cbInstr)
2808{
2809 Assert(pu16NewMsw);
2810
2811 uint16_t const uNewMsw = *pu16NewMsw;
2812 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2813 {
2814 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2815
2816 VMXVEXITINFO ExitInfo;
2817 RT_ZERO(ExitInfo);
2818 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2819 ExitInfo.cbInstr = cbInstr;
2820
2821 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2822 if (fMemOperand)
2823 {
2824 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2825 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2826 }
2827
2828 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2829 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2830 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2831 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2832
2833 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2834 }
2835
2836 /*
2837 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2838 * CR0 guest/host mask must be left unmodified.
2839 *
2840 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2841 */
2842 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2843 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2844 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2845
2846 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2847}
2848
2849
2850/**
2851 * VMX VM-exit handler for VM-exits due to CLTS.
2852 *
2853 * @returns Strict VBox status code.
2854 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2855 * VM-exit but must not modify the guest CR0.TS bit.
2856 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2857 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2858 * CR0 fixed bits in VMX operation).
2859 * @param pVCpu The cross context virtual CPU structure.
2860 * @param cbInstr The instruction length in bytes.
2861 */
2862IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2863{
2864 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2865 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2866
2867 /*
2868 * If CR0.TS is owned by the host:
2869 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2870 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2871 * CLTS instruction completes without clearing CR0.TS.
2872 *
2873 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2874 */
2875 if (fGstHostMask & X86_CR0_TS)
2876 {
2877 if (fReadShadow & X86_CR0_TS)
2878 {
2879 Log2(("clts: Guest intercept -> VM-exit\n"));
2880
2881 VMXVEXITINFO ExitInfo;
2882 RT_ZERO(ExitInfo);
2883 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2884 ExitInfo.cbInstr = cbInstr;
2885 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2886 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2887 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2888 }
2889
2890 return VINF_VMX_MODIFIES_BEHAVIOR;
2891 }
2892
2893 /*
2894 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2895 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2896 */
2897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2898}
2899
2900
2901/**
2902 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2903 * (CR0/CR4 write).
2904 *
2905 * @returns Strict VBox status code.
2906 * @param pVCpu The cross context virtual CPU structure.
2907 * @param iCrReg The control register (either CR0 or CR4).
2908 * @param uGuestCrX The current guest CR0/CR4.
2909 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2910 * VM-exit is caused.
2911 * @param iGReg The general register from which the CR0/CR4 value is being
2912 * loaded.
2913 * @param cbInstr The instruction length in bytes.
2914 */
2915IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2916 uint8_t cbInstr)
2917{
2918 Assert(puNewCrX);
2919 Assert(iCrReg == 0 || iCrReg == 4);
2920 Assert(iGReg < X86_GREG_COUNT);
2921
2922 uint64_t const uNewCrX = *puNewCrX;
2923 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2924 {
2925 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2926
2927 VMXVEXITINFO ExitInfo;
2928 RT_ZERO(ExitInfo);
2929 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2930 ExitInfo.cbInstr = cbInstr;
2931 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2932 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2933 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2934 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2935 }
2936
2937 /*
2938 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2939 * must not be modified the instruction.
2940 *
2941 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2942 */
2943 uint64_t uGuestCrX;
2944 uint64_t fGstHostMask;
2945 if (iCrReg == 0)
2946 {
2947 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2948 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2949 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2950 }
2951 else
2952 {
2953 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2954 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2955 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2956 }
2957
2958 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2959 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2960}
2961
2962
2963/**
2964 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2965 *
2966 * @returns VBox strict status code.
2967 * @param pVCpu The cross context virtual CPU structure.
2968 * @param iGReg The general register to which the CR3 value is being stored.
2969 * @param cbInstr The instruction length in bytes.
2970 */
2971IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2972{
2973 Assert(iGReg < X86_GREG_COUNT);
2974 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2975
2976 /*
2977 * If the CR3-store exiting control is set, we must cause a VM-exit.
2978 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2979 */
2980 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2981 {
2982 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2983
2984 VMXVEXITINFO ExitInfo;
2985 RT_ZERO(ExitInfo);
2986 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2987 ExitInfo.cbInstr = cbInstr;
2988 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2989 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2990 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2991 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2992 }
2993
2994 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2995}
2996
2997
2998/**
2999 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3000 *
3001 * @returns VBox strict status code.
3002 * @param pVCpu The cross context virtual CPU structure.
3003 * @param uNewCr3 The new CR3 value.
3004 * @param iGReg The general register from which the CR3 value is being
3005 * loaded.
3006 * @param cbInstr The instruction length in bytes.
3007 */
3008IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3009{
3010 Assert(iGReg < X86_GREG_COUNT);
3011
3012 /*
3013 * If the CR3-load exiting control is set and the new CR3 value does not
3014 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3015 *
3016 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3017 */
3018 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3019 {
3020 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3021
3022 VMXVEXITINFO ExitInfo;
3023 RT_ZERO(ExitInfo);
3024 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3025 ExitInfo.cbInstr = cbInstr;
3026 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3027 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3028 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030 }
3031
3032 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3033}
3034
3035
3036/**
3037 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3038 *
3039 * @returns VBox strict status code.
3040 * @param pVCpu The cross context virtual CPU structure.
3041 * @param iGReg The general register to which the CR8 value is being stored.
3042 * @param cbInstr The instruction length in bytes.
3043 */
3044IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3045{
3046 Assert(iGReg < X86_GREG_COUNT);
3047
3048 /*
3049 * If the CR8-store exiting control is set, we must cause a VM-exit.
3050 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3051 */
3052 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3053 {
3054 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3055
3056 VMXVEXITINFO ExitInfo;
3057 RT_ZERO(ExitInfo);
3058 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3059 ExitInfo.cbInstr = cbInstr;
3060 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3061 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3062 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3063 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3064 }
3065
3066 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3067}
3068
3069
3070/**
3071 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3072 *
3073 * @returns VBox strict status code.
3074 * @param pVCpu The cross context virtual CPU structure.
3075 * @param iGReg The general register from which the CR8 value is being
3076 * loaded.
3077 * @param cbInstr The instruction length in bytes.
3078 */
3079IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3080{
3081 Assert(iGReg < X86_GREG_COUNT);
3082
3083 /*
3084 * If the CR8-load exiting control is set, we must cause a VM-exit.
3085 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3086 */
3087 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3088 {
3089 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3090
3091 VMXVEXITINFO ExitInfo;
3092 RT_ZERO(ExitInfo);
3093 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3094 ExitInfo.cbInstr = cbInstr;
3095 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3096 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3098 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3099 }
3100
3101 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3102}
3103
3104
3105/**
3106 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3107 * GReg,DRx' (DRx read).
3108 *
3109 * @returns VBox strict status code.
3110 * @param pVCpu The cross context virtual CPU structure.
3111 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3112 * VMXINSTRID_MOV_FROM_DRX).
3113 * @param iDrReg The debug register being accessed.
3114 * @param iGReg The general register to/from which the DRx value is being
3115 * store/loaded.
3116 * @param cbInstr The instruction length in bytes.
3117 */
3118IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3119 uint8_t cbInstr)
3120{
3121 Assert(iDrReg <= 7);
3122 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3123 Assert(iGReg < X86_GREG_COUNT);
3124
3125 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3126 {
3127 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3128 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3129 VMXVEXITINFO ExitInfo;
3130 RT_ZERO(ExitInfo);
3131 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3132 ExitInfo.cbInstr = cbInstr;
3133 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3134 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3135 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3136 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3137 }
3138
3139 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3140}
3141
3142
3143/**
3144 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3145 *
3146 * @returns VBox strict status code.
3147 * @param pVCpu The cross context virtual CPU structure.
3148 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3149 * VMXINSTRID_IO_OUT).
3150 * @param u16Port The I/O port being accessed.
3151 * @param fImm Whether the I/O port was encoded using an immediate operand
3152 * or the implicit DX register.
3153 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3154 * @param cbInstr The instruction length in bytes.
3155 */
3156IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3157 uint8_t cbInstr)
3158{
3159 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3160 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3161
3162 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3163 if (fIntercept)
3164 {
3165 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3166 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3167 VMXVEXITINFO ExitInfo;
3168 RT_ZERO(ExitInfo);
3169 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3170 ExitInfo.cbInstr = cbInstr;
3171 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3173 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3175 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3176 }
3177
3178 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3179}
3180
3181
3182/**
3183 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3184 *
3185 * @returns VBox strict status code.
3186 * @param pVCpu The cross context virtual CPU structure.
3187 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3188 * VMXINSTRID_IO_OUTS).
3189 * @param u16Port The I/O port being accessed.
3190 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3191 * @param fRep Whether the instruction has a REP prefix or not.
3192 * @param ExitInstrInfo The VM-exit instruction info. field.
3193 * @param cbInstr The instruction length in bytes.
3194 */
3195IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3196 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3197{
3198 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3199 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3200 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3201 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3202 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3203
3204 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3205 if (fIntercept)
3206 {
3207 /*
3208 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3209 */
3210 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3211 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3212 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3213 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3214 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3215
3216 uint32_t uDirection;
3217 uint64_t uGuestLinearAddr;
3218 if (uInstrId == VMXINSTRID_IO_INS)
3219 {
3220 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3221 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3222 }
3223 else
3224 {
3225 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3226 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3227 }
3228
3229 /*
3230 * If the segment is unusable, the guest-linear address in undefined.
3231 * We shall clear it for consistency.
3232 *
3233 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3234 */
3235 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3236 uGuestLinearAddr = 0;
3237
3238 VMXVEXITINFO ExitInfo;
3239 RT_ZERO(ExitInfo);
3240 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3241 ExitInfo.cbInstr = cbInstr;
3242 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3243 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3244 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3245 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3246 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3247 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3248 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3249 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3250 ExitInfo.InstrInfo = ExitInstrInfo;
3251 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3252 }
3253
3254 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3255}
3256
3257
3258/**
3259 * VMX VM-exit handler for VM-exits due to MWAIT.
3260 *
3261 * @returns VBox strict status code.
3262 * @param pVCpu The cross context virtual CPU structure.
3263 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3264 * @param cbInstr The instruction length in bytes.
3265 */
3266IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3267{
3268 VMXVEXITINFO ExitInfo;
3269 RT_ZERO(ExitInfo);
3270 ExitInfo.uReason = VMX_EXIT_MWAIT;
3271 ExitInfo.cbInstr = cbInstr;
3272 ExitInfo.u64Qual = fMonitorHwArmed;
3273 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3274}
3275
3276
3277/**
3278 * VMX VM-exit handler for VM-exits due to PAUSE.
3279 *
3280 * @returns VBox strict status code.
3281 * @param pVCpu The cross context virtual CPU structure.
3282 * @param cbInstr The instruction length in bytes.
3283 */
3284IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3285{
3286 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3287
3288 /*
3289 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3290 * "PAUSE-loop exiting" control.
3291 *
3292 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3293 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3294 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3295 * a VM-exit.
3296 *
3297 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3298 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3299 */
3300 bool fIntercept = false;
3301 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3302 fIntercept = true;
3303 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3304 && pVCpu->iem.s.uCpl == 0)
3305 {
3306 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3307
3308 /*
3309 * A previous-PAUSE-tick value of 0 is used to identify the first time
3310 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3311 * consider this to be the first execution of PAUSE in a loop according
3312 * to the Intel.
3313 *
3314 * All subsequent records for the previous-PAUSE-tick we ensure that it
3315 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3316 */
3317 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3318 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3319 uint64_t const uTick = TMCpuTickGet(pVCpu);
3320 uint32_t const uPleGap = pVmcs->u32PleGap;
3321 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3322 if ( *puPrevPauseTick == 0
3323 || uTick - *puPrevPauseTick > uPleGap)
3324 *puFirstPauseLoopTick = uTick;
3325 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3326 fIntercept = true;
3327
3328 *puPrevPauseTick = uTick | 1;
3329 }
3330
3331 if (fIntercept)
3332 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3333
3334 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3335}
3336
3337
3338/**
3339 * VMX VM-exit handler for VM-exits due to task switches.
3340 *
3341 * @returns VBox strict status code.
3342 * @param pVCpu The cross context virtual CPU structure.
3343 * @param enmTaskSwitch The cause of the task switch.
3344 * @param SelNewTss The selector of the new TSS.
3345 * @param cbInstr The instruction length in bytes.
3346 */
3347IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3348{
3349 /*
3350 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3351 *
3352 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3353 * instruction or delivery of the exception generated by one of these instructions
3354 * lead to a task switch through a task gate in the IDT, we need to provide the
3355 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3356 * leaves the VM-exit instruction length field undefined.
3357 *
3358 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3359 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3360 */
3361 Assert(cbInstr <= 15);
3362
3363 uint8_t uType;
3364 switch (enmTaskSwitch)
3365 {
3366 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3367 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3368 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3369 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3370 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3371 }
3372
3373 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3374 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3375 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3376 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3377}
3378
3379
3380/**
3381 * VMX VM-exit handler for trap-like VM-exits.
3382 *
3383 * @returns VBox strict status code.
3384 * @param pVCpu The cross context virtual CPU structure.
3385 * @param pExitInfo Pointer to the VM-exit information.
3386 * @param pExitEventInfo Pointer to the VM-exit event information.
3387 */
3388IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3389{
3390 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3391 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3392 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3393}
3394
3395
3396/**
3397 * VMX VM-exit handler for VM-exits due to task switches.
3398 *
3399 * This is intended for task switches where the caller provides all the relevant
3400 * VM-exit information.
3401 *
3402 * @returns VBox strict status code.
3403 * @param pVCpu The cross context virtual CPU structure.
3404 * @param pExitInfo Pointer to the VM-exit information.
3405 * @param pExitEventInfo Pointer to the VM-exit event information.
3406 */
3407IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3408 PCVMXVEXITEVENTINFO pExitEventInfo)
3409{
3410 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3411 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3412 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3413 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3414 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3415}
3416
3417
3418/**
3419 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3420 *
3421 * @returns VBox strict status code.
3422 * @param pVCpu The cross context virtual CPU structure.
3423 */
3424IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3425{
3426 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3427 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3428
3429 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3430 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3431
3432 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3433 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3434 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3435
3436 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3437 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3438}
3439
3440
3441/**
3442 * VMX VM-exit handler for VM-exits due to external interrupts.
3443 *
3444 * @returns VBox strict status code.
3445 * @param pVCpu The cross context virtual CPU structure.
3446 * @param uVector The external interrupt vector (pass 0 if the interrupt
3447 * is still pending since we typically won't know the
3448 * vector).
3449 * @param fIntPending Whether the external interrupt is pending or
3450 * acknowledged in the interrupt controller.
3451 */
3452IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3453{
3454 Assert(!fIntPending || uVector == 0);
3455
3456 /* The VM-exit is subject to "External interrupt exiting" being set. */
3457 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3458 {
3459 if (fIntPending)
3460 {
3461 /*
3462 * If the interrupt is pending and we don't need to acknowledge the
3463 * interrupt on VM-exit, cause the VM-exit immediately.
3464 *
3465 * See Intel spec 25.2 "Other Causes Of VM Exits".
3466 */
3467 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3469
3470 /*
3471 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3472 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3473 * acknowledged that the interrupt has been consumed. Callers would have to call
3474 * us again after getting the vector (and ofc, with fIntPending with false).
3475 */
3476 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3477 }
3478
3479 /*
3480 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3481 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3482 * all set, we need to record the vector of the external interrupt in the
3483 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3484 *
3485 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3486 */
3487 uint32_t uExitIntInfo;
3488 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3489 {
3490 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3491 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3492 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3493 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3494 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3495 }
3496 else
3497 uExitIntInfo = 0;
3498 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3499
3500 /*
3501 * Cause the VM-exit whether or not the vector has been stored
3502 * in the VM-exit interruption-information field.
3503 */
3504 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3505 }
3506
3507 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3508}
3509
3510
3511/**
3512 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3513 * an event.
3514 *
3515 * @returns VBox strict status code.
3516 * @param pVCpu The cross context virtual CPU structure.
3517 */
3518IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3519{
3520 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3521 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3522 {
3523 /*
3524 * The NMI-unblocking due to IRET field need not be set for double faults.
3525 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3526 */
3527 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3528 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3529 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3530 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3531 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3532 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3533 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3534 }
3535
3536 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3537}
3538
3539
3540/**
3541 * VMX VM-exit handler for VM-exit due to delivery of an events.
3542 *
3543 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3544 * all the relevant VM-exit information.
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 * @param pExitInfo Pointer to the VM-exit information.
3549 * @param pExitEventInfo Pointer to the VM-exit event information.
3550 */
3551IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3552{
3553 Assert(pExitInfo);
3554 Assert(pExitEventInfo);
3555 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3556 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3557
3558 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3559 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3560 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3561 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3562 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3563 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3564}
3565
3566
3567/**
3568 * VMX VM-exit handler for VM-exits due to delivery of an event.
3569 *
3570 * @returns VBox strict status code.
3571 * @param pVCpu The cross context virtual CPU structure.
3572 * @param uVector The interrupt / exception vector.
3573 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3574 * @param uErrCode The error code associated with the event.
3575 * @param uCr2 The CR2 value in case of a \#PF exception.
3576 * @param cbInstr The instruction length in bytes.
3577 */
3578IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3579 uint8_t cbInstr)
3580{
3581 /*
3582 * If the event is being injected as part of VM-entry, it is -not- subject to event
3583 * intercepts in the nested-guest. However, secondary exceptions that occur during
3584 * injection of any event -are- subject to event interception.
3585 *
3586 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3587 */
3588 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3589 {
3590 /*
3591 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3592 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3593 *
3594 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3595 */
3596 if ( uVector == X86_XCPT_NMI
3597 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3598 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3599 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3600 else
3601 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3602
3603 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3604 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3605 }
3606
3607 /*
3608 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3609 * If not, the caller will continue delivery of the external interrupt as it would
3610 * normally. The interrupt is no longer pending in the interrupt controller at this
3611 * point.
3612 */
3613 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3614 {
3615 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3616 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3617 }
3618
3619 /*
3620 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3621 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3622 * interrupts.
3623 */
3624 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3625 bool fIntercept;
3626 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3627 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3628 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3629 else
3630 {
3631 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3632 fIntercept = false;
3633 }
3634
3635 /*
3636 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3637 * relevant VM-exit information and cause the VM-exit.
3638 */
3639 if (fIntercept)
3640 {
3641 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3642
3643 /* Construct the rest of the event related information fields and cause the VM-exit. */
3644 uint64_t u64ExitQual;
3645 if (uVector == X86_XCPT_PF)
3646 {
3647 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3648 u64ExitQual = uCr2;
3649 }
3650 else if (uVector == X86_XCPT_DB)
3651 {
3652 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3653 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3654 }
3655 else
3656 u64ExitQual = 0;
3657
3658 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3659 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3660 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3661 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3662 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3663 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3664 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3665 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3666 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3667 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3668
3669 /*
3670 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3671 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3672 * length.
3673 */
3674 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3675 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3676 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3677 else
3678 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3679
3680 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3681 }
3682
3683 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3684}
3685
3686
3687#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3688/**
3689 * VMX VM-exit handler for EPT violation.
3690 *
3691 * @param pVCpu The cross context virtual CPU structure.
3692 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3693 * @param fEptAccess The EPT paging structure bits.
3694 * @param GCPhysAddr The physical address causing the EPT violation.
3695 * @param GCPtrAddr The linear address causing the EPT violation.
3696 * @param cbInstr The VM-exit instruction length.
3697 */
3698IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3699 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3700{
3701 /*
3702 * If the linear address isn't valid (can happen when loading PDPTEs
3703 * as part of MOV CR execution) the linear address field is undefined.
3704 * While we can leave it this way, it's preferrable to zero it for consistency.
3705 */
3706 Assert(fLinearAddrValid || GCPtrAddr == 0);
3707
3708 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3709 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3710
3711 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3712 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3713 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3714 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3715 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3716 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3717 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3718
3719 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3720 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3721 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3722 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3723 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3724 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3725 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3726 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3727
3728 /** @todo bit 8 of Exit Qualification!
3729 * If the access causing the EPT violation is to a guest-physical address that is
3730 * the translation of a linear address.
3731 * - OR -
3732 * if the access causing the EPT violation is to a paging-structure entry as part
3733 * of a page walk or the update of an accessed or dirty bit.
3734 *
3735 * Caller needs to be able to distinguish this... */
3736
3737#ifdef VBOX_STRICT
3738 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3739 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3740 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3741 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3742 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3743 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3744 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3745#endif
3746
3747 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3748 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3749 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3750
3751 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3752}
3753#endif
3754
3755
3756/**
3757 * VMX VM-exit handler for APIC accesses.
3758 *
3759 * @param pVCpu The cross context virtual CPU structure.
3760 * @param offAccess The offset of the register being accessed.
3761 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3762 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3763 */
3764IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3765{
3766 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3767
3768 VMXAPICACCESS enmAccess;
3769 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3770 if (fInEventDelivery)
3771 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3772 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3773 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3774 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3775 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3776 else
3777 enmAccess = VMXAPICACCESS_LINEAR_READ;
3778
3779 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3780 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3781 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3782}
3783
3784
3785/**
3786 * VMX VM-exit handler for APIC accesses.
3787 *
3788 * This is intended for APIC accesses where the caller provides all the
3789 * relevant VM-exit information.
3790 *
3791 * @returns VBox strict status code.
3792 * @param pVCpu The cross context virtual CPU structure.
3793 * @param pExitInfo Pointer to the VM-exit information.
3794 * @param pExitEventInfo Pointer to the VM-exit event information.
3795 */
3796IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3797 PCVMXVEXITEVENTINFO pExitEventInfo)
3798{
3799 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3800 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3801 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3802 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3803 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3804 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3805 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3806 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3807 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3808}
3809
3810
3811/**
3812 * VMX VM-exit handler for APIC-write VM-exits.
3813 *
3814 * @param pVCpu The cross context virtual CPU structure.
3815 * @param offApic The write to the virtual-APIC page offset that caused this
3816 * VM-exit.
3817 */
3818IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3819{
3820 Assert(offApic < XAPIC_OFF_END + 4);
3821 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3822 offApic &= UINT16_C(0xfff);
3823 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3824}
3825
3826
3827/**
3828 * Sets virtual-APIC write emulation as pending.
3829 *
3830 * @param pVCpu The cross context virtual CPU structure.
3831 * @param offApic The offset in the virtual-APIC page that was written.
3832 */
3833DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3834{
3835 Assert(offApic < XAPIC_OFF_END + 4);
3836
3837 /*
3838 * Record the currently updated APIC offset, as we need this later for figuring
3839 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3840 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3841 */
3842 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3843
3844 /*
3845 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3846 * virtualization or APIC-write emulation).
3847 */
3848 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3849 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3850}
3851
3852
3853/**
3854 * Clears any pending virtual-APIC write emulation.
3855 *
3856 * @returns The virtual-APIC offset that was written before clearing it.
3857 * @param pVCpu The cross context virtual CPU structure.
3858 */
3859DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3860{
3861 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3862 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3863 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3864 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3865 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3866 return offVirtApicWrite;
3867}
3868
3869
3870/**
3871 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3872 *
3873 * @returns The register from the virtual-APIC page.
3874 * @param pVCpu The cross context virtual CPU structure.
3875 * @param offReg The offset of the register being read.
3876 */
3877IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3878{
3879 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3880
3881 uint32_t uReg = 0;
3882 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3883 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3884 AssertMsgStmt(RT_SUCCESS(rc),
3885 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3886 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3887 uReg = 0);
3888 return uReg;
3889}
3890
3891
3892/**
3893 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3894 *
3895 * @returns The register from the virtual-APIC page.
3896 * @param pVCpu The cross context virtual CPU structure.
3897 * @param offReg The offset of the register being read.
3898 */
3899IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3900{
3901 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3902
3903 uint64_t uReg = 0;
3904 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3905 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3906 AssertMsgStmt(RT_SUCCESS(rc),
3907 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3908 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3909 uReg = 0);
3910 return uReg;
3911}
3912
3913
3914/**
3915 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3916 *
3917 * @param pVCpu The cross context virtual CPU structure.
3918 * @param offReg The offset of the register being written.
3919 * @param uReg The register value to write.
3920 */
3921IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3922{
3923 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3924
3925 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3926 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3927 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3928 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3929}
3930
3931
3932/**
3933 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3934 *
3935 * @param pVCpu The cross context virtual CPU structure.
3936 * @param offReg The offset of the register being written.
3937 * @param uReg The register value to write.
3938 */
3939IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3940{
3941 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3942
3943 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3944 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3945 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3946 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3947}
3948
3949
3950/**
3951 * Sets the vector in a virtual-APIC 256-bit sparse register.
3952 *
3953 * @param pVCpu The cross context virtual CPU structure.
3954 * @param offReg The offset of the 256-bit spare register.
3955 * @param uVector The vector to set.
3956 *
3957 * @remarks This is based on our APIC device code.
3958 */
3959IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3960{
3961 /* Determine the vector offset within the chunk. */
3962 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3963
3964 /* Read the chunk at the offset. */
3965 uint32_t uReg;
3966 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3967 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3968 if (RT_SUCCESS(rc))
3969 {
3970 /* Modify the chunk. */
3971 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3972 uReg |= RT_BIT(idxVectorBit);
3973
3974 /* Write the chunk. */
3975 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3976 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3977 uVector, offReg, GCPhysVirtApic, rc));
3978 }
3979 else
3980 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3981 uVector, offReg, GCPhysVirtApic, rc));
3982}
3983
3984
3985/**
3986 * Clears the vector in a virtual-APIC 256-bit sparse register.
3987 *
3988 * @param pVCpu The cross context virtual CPU structure.
3989 * @param offReg The offset of the 256-bit spare register.
3990 * @param uVector The vector to clear.
3991 *
3992 * @remarks This is based on our APIC device code.
3993 */
3994IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3995{
3996 /* Determine the vector offset within the chunk. */
3997 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3998
3999 /* Read the chunk at the offset. */
4000 uint32_t uReg;
4001 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4002 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4003 if (RT_SUCCESS(rc))
4004 {
4005 /* Modify the chunk. */
4006 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4007 uReg &= ~RT_BIT(idxVectorBit);
4008
4009 /* Write the chunk. */
4010 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4011 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4012 uVector, offReg, GCPhysVirtApic, rc));
4013 }
4014 else
4015 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4016 uVector, offReg, GCPhysVirtApic, rc));
4017}
4018
4019
4020/**
4021 * Checks if a memory access to the APIC-access page must causes an APIC-access
4022 * VM-exit.
4023 *
4024 * @param pVCpu The cross context virtual CPU structure.
4025 * @param offAccess The offset of the register being accessed.
4026 * @param cbAccess The size of the access in bytes.
4027 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4028 * IEM_ACCESS_TYPE_WRITE).
4029 *
4030 * @remarks This must not be used for MSR-based APIC-access page accesses!
4031 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4032 */
4033IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4034{
4035 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4036 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4037
4038 /*
4039 * We must cause a VM-exit if any of the following are true:
4040 * - TPR shadowing isn't active.
4041 * - The access size exceeds 32-bits.
4042 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4043 *
4044 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4045 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4046 */
4047 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4048 || cbAccess > sizeof(uint32_t)
4049 || ((offAccess + cbAccess - 1) & 0xc)
4050 || offAccess >= XAPIC_OFF_END + 4)
4051 return true;
4052
4053 /*
4054 * If the access is part of an operation where we have already
4055 * virtualized a virtual-APIC write, we must cause a VM-exit.
4056 */
4057 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4058 return true;
4059
4060 /*
4061 * Check write accesses to the APIC-access page that cause VM-exits.
4062 */
4063 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4064 {
4065 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4066 {
4067 /*
4068 * With APIC-register virtualization, a write access to any of the
4069 * following registers are virtualized. Accessing any other register
4070 * causes a VM-exit.
4071 */
4072 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4073 switch (offAlignedAccess)
4074 {
4075 case XAPIC_OFF_ID:
4076 case XAPIC_OFF_TPR:
4077 case XAPIC_OFF_EOI:
4078 case XAPIC_OFF_LDR:
4079 case XAPIC_OFF_DFR:
4080 case XAPIC_OFF_SVR:
4081 case XAPIC_OFF_ESR:
4082 case XAPIC_OFF_ICR_LO:
4083 case XAPIC_OFF_ICR_HI:
4084 case XAPIC_OFF_LVT_TIMER:
4085 case XAPIC_OFF_LVT_THERMAL:
4086 case XAPIC_OFF_LVT_PERF:
4087 case XAPIC_OFF_LVT_LINT0:
4088 case XAPIC_OFF_LVT_LINT1:
4089 case XAPIC_OFF_LVT_ERROR:
4090 case XAPIC_OFF_TIMER_ICR:
4091 case XAPIC_OFF_TIMER_DCR:
4092 break;
4093 default:
4094 return true;
4095 }
4096 }
4097 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4098 {
4099 /*
4100 * With virtual-interrupt delivery, a write access to any of the
4101 * following registers are virtualized. Accessing any other register
4102 * causes a VM-exit.
4103 *
4104 * Note! The specification does not allow writing to offsets in-between
4105 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4106 */
4107 switch (offAccess)
4108 {
4109 case XAPIC_OFF_TPR:
4110 case XAPIC_OFF_EOI:
4111 case XAPIC_OFF_ICR_LO:
4112 break;
4113 default:
4114 return true;
4115 }
4116 }
4117 else
4118 {
4119 /*
4120 * Without APIC-register virtualization or virtual-interrupt delivery,
4121 * only TPR accesses are virtualized.
4122 */
4123 if (offAccess == XAPIC_OFF_TPR)
4124 { /* likely */ }
4125 else
4126 return true;
4127 }
4128 }
4129 else
4130 {
4131 /*
4132 * Check read accesses to the APIC-access page that cause VM-exits.
4133 */
4134 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4135 {
4136 /*
4137 * With APIC-register virtualization, a read access to any of the
4138 * following registers are virtualized. Accessing any other register
4139 * causes a VM-exit.
4140 */
4141 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4142 switch (offAlignedAccess)
4143 {
4144 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4145 case XAPIC_OFF_ID:
4146 case XAPIC_OFF_VERSION:
4147 case XAPIC_OFF_TPR:
4148 case XAPIC_OFF_EOI:
4149 case XAPIC_OFF_LDR:
4150 case XAPIC_OFF_DFR:
4151 case XAPIC_OFF_SVR:
4152 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4153 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4154 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4155 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4156 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4157 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4158 case XAPIC_OFF_ESR:
4159 case XAPIC_OFF_ICR_LO:
4160 case XAPIC_OFF_ICR_HI:
4161 case XAPIC_OFF_LVT_TIMER:
4162 case XAPIC_OFF_LVT_THERMAL:
4163 case XAPIC_OFF_LVT_PERF:
4164 case XAPIC_OFF_LVT_LINT0:
4165 case XAPIC_OFF_LVT_LINT1:
4166 case XAPIC_OFF_LVT_ERROR:
4167 case XAPIC_OFF_TIMER_ICR:
4168 case XAPIC_OFF_TIMER_DCR:
4169 break;
4170 default:
4171 return true;
4172 }
4173 }
4174 else
4175 {
4176 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4177 if (offAccess == XAPIC_OFF_TPR)
4178 { /* likely */ }
4179 else
4180 return true;
4181 }
4182 }
4183
4184 /* The APIC access is virtualized, does not cause a VM-exit. */
4185 return false;
4186}
4187
4188
4189/**
4190 * Virtualizes a memory-based APIC access where the address is not used to access
4191 * memory.
4192 *
4193 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4194 * page-faults but do not use the address to access memory.
4195 *
4196 * @param pVCpu The cross context virtual CPU structure.
4197 * @param pGCPhysAccess Pointer to the guest-physical address used.
4198 */
4199IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4200{
4201 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4202 Assert(pGCPhysAccess);
4203
4204 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4205 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4206 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4207
4208 if (GCPhysAccess == GCPhysApic)
4209 {
4210 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4211 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4212 uint16_t const cbAccess = 1;
4213 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4214 if (fIntercept)
4215 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4216
4217 *pGCPhysAccess = GCPhysApic | offAccess;
4218 return VINF_VMX_MODIFIES_BEHAVIOR;
4219 }
4220
4221 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4222}
4223
4224
4225/**
4226 * Virtualizes a memory-based APIC access.
4227 *
4228 * @returns VBox strict status code.
4229 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4230 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4231 *
4232 * @param pVCpu The cross context virtual CPU structure.
4233 * @param offAccess The offset of the register being accessed (within the
4234 * APIC-access page).
4235 * @param cbAccess The size of the access in bytes.
4236 * @param pvData Pointer to the data being written or where to store the data
4237 * being read.
4238 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4239 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4240 */
4241IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4242 uint32_t fAccess)
4243{
4244 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4245 Assert(pvData);
4246 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4247 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4248 || (fAccess & IEM_ACCESS_INSTRUCTION));
4249
4250 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4251 if (fIntercept)
4252 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4253
4254 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4255 {
4256 /*
4257 * A write access to the APIC-access page that is virtualized (rather than
4258 * causing a VM-exit) writes data to the virtual-APIC page.
4259 */
4260 uint32_t const u32Data = *(uint32_t *)pvData;
4261 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4262
4263 /*
4264 * Record the currently updated APIC offset, as we need this later for figuring
4265 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4266 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4267 *
4268 * After completion of the current operation, we need to perform TPR virtualization,
4269 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4270 *
4271 * The current operation may be a REP-prefixed string instruction, execution of any
4272 * other instruction, or delivery of an event through the IDT.
4273 *
4274 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4275 * performed now but later after completion of the current operation.
4276 *
4277 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4278 */
4279 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4280 }
4281 else
4282 {
4283 /*
4284 * A read access from the APIC-access page that is virtualized (rather than
4285 * causing a VM-exit) returns data from the virtual-APIC page.
4286 *
4287 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4288 */
4289 Assert(cbAccess <= 4);
4290 Assert(offAccess < XAPIC_OFF_END + 4);
4291 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4292
4293 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4294 u32Data &= s_auAccessSizeMasks[cbAccess];
4295 *(uint32_t *)pvData = u32Data;
4296 }
4297
4298 return VINF_VMX_MODIFIES_BEHAVIOR;
4299}
4300
4301
4302/**
4303 * Virtualizes an MSR-based APIC read access.
4304 *
4305 * @returns VBox strict status code.
4306 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4307 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4308 * handled by the x2APIC device.
4309 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4310 * not within the range of valid MSRs, caller must raise \#GP(0).
4311 * @param pVCpu The cross context virtual CPU structure.
4312 * @param idMsr The x2APIC MSR being read.
4313 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4314 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4315 */
4316IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4317{
4318 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4319 Assert(pu64Value);
4320
4321 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4322 {
4323 if ( idMsr >= MSR_IA32_X2APIC_START
4324 && idMsr <= MSR_IA32_X2APIC_END)
4325 {
4326 uint16_t const offReg = (idMsr & 0xff) << 4;
4327 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4328 *pu64Value = u64Value;
4329 return VINF_VMX_MODIFIES_BEHAVIOR;
4330 }
4331 return VERR_OUT_OF_RANGE;
4332 }
4333
4334 if (idMsr == MSR_IA32_X2APIC_TPR)
4335 {
4336 uint16_t const offReg = (idMsr & 0xff) << 4;
4337 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4338 *pu64Value = u64Value;
4339 return VINF_VMX_MODIFIES_BEHAVIOR;
4340 }
4341
4342 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4343}
4344
4345
4346/**
4347 * Virtualizes an MSR-based APIC write access.
4348 *
4349 * @returns VBox strict status code.
4350 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4351 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4352 * not within the range of valid MSRs, caller must raise \#GP(0).
4353 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4354 *
4355 * @param pVCpu The cross context virtual CPU structure.
4356 * @param idMsr The x2APIC MSR being written.
4357 * @param u64Value The value of the x2APIC MSR being written.
4358 */
4359IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4360{
4361 /*
4362 * Check if the access is to be virtualized.
4363 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4364 */
4365 if ( idMsr == MSR_IA32_X2APIC_TPR
4366 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4367 && ( idMsr == MSR_IA32_X2APIC_EOI
4368 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4369 {
4370 /* Validate the MSR write depending on the register. */
4371 switch (idMsr)
4372 {
4373 case MSR_IA32_X2APIC_TPR:
4374 case MSR_IA32_X2APIC_SELF_IPI:
4375 {
4376 if (u64Value & UINT64_C(0xffffffffffffff00))
4377 return VERR_OUT_OF_RANGE;
4378 break;
4379 }
4380 case MSR_IA32_X2APIC_EOI:
4381 {
4382 if (u64Value != 0)
4383 return VERR_OUT_OF_RANGE;
4384 break;
4385 }
4386 }
4387
4388 /* Write the MSR to the virtual-APIC page. */
4389 uint16_t const offReg = (idMsr & 0xff) << 4;
4390 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4391
4392 /*
4393 * Record the currently updated APIC offset, as we need this later for figuring
4394 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4395 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4396 */
4397 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4398
4399 return VINF_VMX_MODIFIES_BEHAVIOR;
4400 }
4401
4402 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4403}
4404
4405
4406/**
4407 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4408 *
4409 * @returns VBox status code.
4410 * @retval VINF_SUCCESS when the highest set bit is found.
4411 * @retval VERR_NOT_FOUND when no bit is set.
4412 *
4413 * @param pVCpu The cross context virtual CPU structure.
4414 * @param offReg The offset of the APIC 256-bit sparse register.
4415 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4416 * set in the register. Only valid when VINF_SUCCESS is
4417 * returned.
4418 *
4419 * @remarks The format of the 256-bit sparse register here mirrors that found in
4420 * real APIC hardware.
4421 */
4422static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4423{
4424 Assert(offReg < XAPIC_OFF_END + 4);
4425 Assert(pidxHighestBit);
4426
4427 /*
4428 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4429 * However, in each fragment only the first 4 bytes are used.
4430 */
4431 uint8_t const cFrags = 8;
4432 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4433 {
4434 uint16_t const offFrag = iFrag * 16;
4435 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4436 if (!u32Frag)
4437 continue;
4438
4439 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4440 Assert(idxHighestBit > 0);
4441 --idxHighestBit;
4442 Assert(idxHighestBit <= UINT8_MAX);
4443 *pidxHighestBit = idxHighestBit;
4444 return VINF_SUCCESS;
4445 }
4446 return VERR_NOT_FOUND;
4447}
4448
4449
4450/**
4451 * Evaluates pending virtual interrupts.
4452 *
4453 * @param pVCpu The cross context virtual CPU structure.
4454 */
4455IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4456{
4457 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4458
4459 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4460 {
4461 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4462 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4463
4464 if ((uRvi >> 4) > (uPpr >> 4))
4465 {
4466 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4467 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4468 }
4469 else
4470 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4471 }
4472}
4473
4474
4475/**
4476 * Performs PPR virtualization.
4477 *
4478 * @returns VBox strict status code.
4479 * @param pVCpu The cross context virtual CPU structure.
4480 */
4481IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4482{
4483 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4484 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4485
4486 /*
4487 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4488 * or EOI-virtualization.
4489 *
4490 * See Intel spec. 29.1.3 "PPR Virtualization".
4491 */
4492 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4493 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4494
4495 uint32_t uPpr;
4496 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4497 uPpr = uTpr & 0xff;
4498 else
4499 uPpr = uSvi & 0xf0;
4500
4501 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4502 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4503}
4504
4505
4506/**
4507 * Performs VMX TPR virtualization.
4508 *
4509 * @returns VBox strict status code.
4510 * @param pVCpu The cross context virtual CPU structure.
4511 */
4512IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4513{
4514 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4515
4516 /*
4517 * We should have already performed the virtual-APIC write to the TPR offset
4518 * in the virtual-APIC page. We now perform TPR virtualization.
4519 *
4520 * See Intel spec. 29.1.2 "TPR Virtualization".
4521 */
4522 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4523 {
4524 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4525 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4526
4527 /*
4528 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4529 * See Intel spec. 29.1.2 "TPR Virtualization".
4530 */
4531 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4532 {
4533 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4534 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4535 }
4536 }
4537 else
4538 {
4539 iemVmxPprVirtualization(pVCpu);
4540 iemVmxEvalPendingVirtIntrs(pVCpu);
4541 }
4542
4543 return VINF_SUCCESS;
4544}
4545
4546
4547/**
4548 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4549 * not.
4550 *
4551 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4552 * @param pVCpu The cross context virtual CPU structure.
4553 * @param uVector The interrupt that was acknowledged using an EOI.
4554 */
4555IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4556{
4557 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4558 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4559
4560 if (uVector < 64)
4561 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4562 if (uVector < 128)
4563 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4564 if (uVector < 192)
4565 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4566 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4567}
4568
4569
4570/**
4571 * Performs EOI virtualization.
4572 *
4573 * @returns VBox strict status code.
4574 * @param pVCpu The cross context virtual CPU structure.
4575 */
4576IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4577{
4578 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4579 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4580
4581 /*
4582 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4583 * and get the next guest-interrupt that's in-service (if any).
4584 *
4585 * See Intel spec. 29.1.4 "EOI Virtualization".
4586 */
4587 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4588 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4589 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4590
4591 uint8_t uVector = uSvi;
4592 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4593
4594 uVector = 0;
4595 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4596
4597 if (uVector)
4598 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4599 else
4600 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4601
4602 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4603 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4604
4605 iemVmxPprVirtualization(pVCpu);
4606 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4607 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4608 iemVmxEvalPendingVirtIntrs(pVCpu);
4609 return VINF_SUCCESS;
4610}
4611
4612
4613/**
4614 * Performs self-IPI virtualization.
4615 *
4616 * @returns VBox strict status code.
4617 * @param pVCpu The cross context virtual CPU structure.
4618 */
4619IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4620{
4621 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4622 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4623
4624 /*
4625 * We should have already performed the virtual-APIC write to the self-IPI offset
4626 * in the virtual-APIC page. We now perform self-IPI virtualization.
4627 *
4628 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4629 */
4630 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4631 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4632 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4633 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4634 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4635 if (uVector > uRvi)
4636 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4637 iemVmxEvalPendingVirtIntrs(pVCpu);
4638 return VINF_SUCCESS;
4639}
4640
4641
4642/**
4643 * Performs VMX APIC-write emulation.
4644 *
4645 * @returns VBox strict status code.
4646 * @param pVCpu The cross context virtual CPU structure.
4647 */
4648IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4649{
4650 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4651
4652 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4653 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4654
4655 /*
4656 * Perform APIC-write emulation based on the virtual-APIC register written.
4657 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4658 */
4659 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4660 VBOXSTRICTRC rcStrict;
4661 switch (offApicWrite)
4662 {
4663 case XAPIC_OFF_TPR:
4664 {
4665 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4666 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4667 uTpr &= UINT32_C(0x000000ff);
4668 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4669 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4670 rcStrict = iemVmxTprVirtualization(pVCpu);
4671 break;
4672 }
4673
4674 case XAPIC_OFF_EOI:
4675 {
4676 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4677 {
4678 /* Clear VEOI and perform EOI virtualization. */
4679 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4680 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4681 rcStrict = iemVmxEoiVirtualization(pVCpu);
4682 }
4683 else
4684 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4685 break;
4686 }
4687
4688 case XAPIC_OFF_ICR_LO:
4689 {
4690 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4691 {
4692 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4693 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4694 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4695 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4696 if ( !(uIcrLo & fIcrLoMb0)
4697 && (uIcrLo & fIcrLoMb1))
4698 {
4699 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4700 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4701 }
4702 else
4703 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4704 }
4705 else
4706 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4707 break;
4708 }
4709
4710 case XAPIC_OFF_ICR_HI:
4711 {
4712 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4713 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4714 uIcrHi &= UINT32_C(0xff000000);
4715 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4716 rcStrict = VINF_SUCCESS;
4717 break;
4718 }
4719
4720 default:
4721 {
4722 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4723 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4724 break;
4725 }
4726 }
4727
4728 return rcStrict;
4729}
4730
4731
4732/**
4733 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4734 *
4735 * @param pVCpu The cross context virtual CPU structure.
4736 * @param pszInstr The VMX instruction name (for logging purposes).
4737 */
4738DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4739{
4740 /*
4741 * Guest Control Registers, Debug Registers, and MSRs.
4742 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4743 */
4744 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4745 const char * const pszFailure = "VM-exit";
4746 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4747
4748 /* CR0 reserved bits. */
4749 {
4750 /* CR0 MB1 bits. */
4751 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4752 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4753 if (fUnrestrictedGuest)
4754 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4755 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4756 { /* likely */ }
4757 else
4758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4759
4760 /* CR0 MBZ bits. */
4761 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4762 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4763 { /* likely */ }
4764 else
4765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4766
4767 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4768 if ( !fUnrestrictedGuest
4769 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4770 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4772 }
4773
4774 /* CR4 reserved bits. */
4775 {
4776 /* CR4 MB1 bits. */
4777 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4778 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4779 { /* likely */ }
4780 else
4781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4782
4783 /* CR4 MBZ bits. */
4784 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4785 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4786 { /* likely */ }
4787 else
4788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4789 }
4790
4791 /* DEBUGCTL MSR. */
4792 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4793 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4794 { /* likely */ }
4795 else
4796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4797
4798 /* 64-bit CPU checks. */
4799 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4800 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4801 {
4802 if (fGstInLongMode)
4803 {
4804 /* PAE must be set. */
4805 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4806 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4807 { /* likely */ }
4808 else
4809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4810 }
4811 else
4812 {
4813 /* PCIDE should not be set. */
4814 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4815 { /* likely */ }
4816 else
4817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4818 }
4819
4820 /* CR3. */
4821 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4822 { /* likely */ }
4823 else
4824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4825
4826 /* DR7. */
4827 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4828 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4829 { /* likely */ }
4830 else
4831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4832
4833 /* SYSENTER ESP and SYSENTER EIP. */
4834 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4835 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4836 { /* likely */ }
4837 else
4838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4839 }
4840
4841 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4842 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4843
4844 /* PAT MSR. */
4845 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4846 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4847 { /* likely */ }
4848 else
4849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4850
4851 /* EFER MSR. */
4852 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4853 {
4854 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4855 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4856 { /* likely */ }
4857 else
4858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4859
4860 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4861 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4862 if ( fGstLma == fGstInLongMode
4863 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4864 || fGstLma == fGstLme))
4865 { /* likely */ }
4866 else
4867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4868 }
4869
4870 /* We don't support IA32_BNDCFGS MSR yet. */
4871 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4872
4873 NOREF(pszInstr);
4874 NOREF(pszFailure);
4875 return VINF_SUCCESS;
4876}
4877
4878
4879/**
4880 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4881 *
4882 * @param pVCpu The cross context virtual CPU structure.
4883 * @param pszInstr The VMX instruction name (for logging purposes).
4884 */
4885DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4886{
4887 /*
4888 * Segment registers.
4889 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4890 */
4891 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4892 const char * const pszFailure = "VM-exit";
4893 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4894 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4895 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4896
4897 /* Selectors. */
4898 if ( !fGstInV86Mode
4899 && !fUnrestrictedGuest
4900 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4902
4903 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4904 {
4905 CPUMSELREG SelReg;
4906 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4907 if (RT_LIKELY(rc == VINF_SUCCESS))
4908 { /* likely */ }
4909 else
4910 return rc;
4911
4912 /*
4913 * Virtual-8086 mode checks.
4914 */
4915 if (fGstInV86Mode)
4916 {
4917 /* Base address. */
4918 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4919 { /* likely */ }
4920 else
4921 {
4922 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4924 }
4925
4926 /* Limit. */
4927 if (SelReg.u32Limit == 0xffff)
4928 { /* likely */ }
4929 else
4930 {
4931 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4933 }
4934
4935 /* Attribute. */
4936 if (SelReg.Attr.u == 0xf3)
4937 { /* likely */ }
4938 else
4939 {
4940 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4942 }
4943
4944 /* We're done; move to checking the next segment. */
4945 continue;
4946 }
4947
4948 /* Checks done by 64-bit CPUs. */
4949 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4950 {
4951 /* Base address. */
4952 if ( iSegReg == X86_SREG_FS
4953 || iSegReg == X86_SREG_GS)
4954 {
4955 if (X86_IS_CANONICAL(SelReg.u64Base))
4956 { /* likely */ }
4957 else
4958 {
4959 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4961 }
4962 }
4963 else if (iSegReg == X86_SREG_CS)
4964 {
4965 if (!RT_HI_U32(SelReg.u64Base))
4966 { /* likely */ }
4967 else
4968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4969 }
4970 else
4971 {
4972 if ( SelReg.Attr.n.u1Unusable
4973 || !RT_HI_U32(SelReg.u64Base))
4974 { /* likely */ }
4975 else
4976 {
4977 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4979 }
4980 }
4981 }
4982
4983 /*
4984 * Checks outside Virtual-8086 mode.
4985 */
4986 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4987 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4988 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4989 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4990 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4991 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4992 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4993 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4994
4995 /* Code or usable segment. */
4996 if ( iSegReg == X86_SREG_CS
4997 || fUsable)
4998 {
4999 /* Reserved bits (bits 31:17 and bits 11:8). */
5000 if (!(SelReg.Attr.u & 0xfffe0f00))
5001 { /* likely */ }
5002 else
5003 {
5004 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5006 }
5007
5008 /* Descriptor type. */
5009 if (fCodeDataSeg)
5010 { /* likely */ }
5011 else
5012 {
5013 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5014 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5015 }
5016
5017 /* Present. */
5018 if (fPresent)
5019 { /* likely */ }
5020 else
5021 {
5022 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5024 }
5025
5026 /* Granularity. */
5027 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5028 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5029 { /* likely */ }
5030 else
5031 {
5032 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5034 }
5035 }
5036
5037 if (iSegReg == X86_SREG_CS)
5038 {
5039 /* Segment Type and DPL. */
5040 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5041 && fUnrestrictedGuest)
5042 {
5043 if (uDpl == 0)
5044 { /* likely */ }
5045 else
5046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5047 }
5048 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5049 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5050 {
5051 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5052 if (uDpl == AttrSs.n.u2Dpl)
5053 { /* likely */ }
5054 else
5055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5056 }
5057 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5058 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5059 {
5060 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5061 if (uDpl <= AttrSs.n.u2Dpl)
5062 { /* likely */ }
5063 else
5064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5065 }
5066 else
5067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5068
5069 /* Def/Big. */
5070 if ( fGstInLongMode
5071 && fSegLong)
5072 {
5073 if (uDefBig == 0)
5074 { /* likely */ }
5075 else
5076 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5077 }
5078 }
5079 else if (iSegReg == X86_SREG_SS)
5080 {
5081 /* Segment Type. */
5082 if ( !fUsable
5083 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5084 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5085 { /* likely */ }
5086 else
5087 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5088
5089 /* DPL. */
5090 if (!fUnrestrictedGuest)
5091 {
5092 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5093 { /* likely */ }
5094 else
5095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5096 }
5097 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5098 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5099 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5100 {
5101 if (uDpl == 0)
5102 { /* likely */ }
5103 else
5104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5105 }
5106 }
5107 else
5108 {
5109 /* DS, ES, FS, GS. */
5110 if (fUsable)
5111 {
5112 /* Segment type. */
5113 if (uSegType & X86_SEL_TYPE_ACCESSED)
5114 { /* likely */ }
5115 else
5116 {
5117 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5119 }
5120
5121 if ( !(uSegType & X86_SEL_TYPE_CODE)
5122 || (uSegType & X86_SEL_TYPE_READ))
5123 { /* likely */ }
5124 else
5125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5126
5127 /* DPL. */
5128 if ( !fUnrestrictedGuest
5129 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5130 {
5131 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5132 { /* likely */ }
5133 else
5134 {
5135 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5137 }
5138 }
5139 }
5140 }
5141 }
5142
5143 /*
5144 * LDTR.
5145 */
5146 {
5147 CPUMSELREG Ldtr;
5148 Ldtr.Sel = pVmcs->GuestLdtr;
5149 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5150 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5151 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5152
5153 if (!Ldtr.Attr.n.u1Unusable)
5154 {
5155 /* Selector. */
5156 if (!(Ldtr.Sel & X86_SEL_LDT))
5157 { /* likely */ }
5158 else
5159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5160
5161 /* Base. */
5162 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5163 {
5164 if (X86_IS_CANONICAL(Ldtr.u64Base))
5165 { /* likely */ }
5166 else
5167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5168 }
5169
5170 /* Attributes. */
5171 /* Reserved bits (bits 31:17 and bits 11:8). */
5172 if (!(Ldtr.Attr.u & 0xfffe0f00))
5173 { /* likely */ }
5174 else
5175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5176
5177 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5178 { /* likely */ }
5179 else
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5181
5182 if (!Ldtr.Attr.n.u1DescType)
5183 { /* likely */ }
5184 else
5185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5186
5187 if (Ldtr.Attr.n.u1Present)
5188 { /* likely */ }
5189 else
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5191
5192 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5193 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5194 { /* likely */ }
5195 else
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5197 }
5198 }
5199
5200 /*
5201 * TR.
5202 */
5203 {
5204 CPUMSELREG Tr;
5205 Tr.Sel = pVmcs->GuestTr;
5206 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5207 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5208 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5209
5210 /* Selector. */
5211 if (!(Tr.Sel & X86_SEL_LDT))
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5215
5216 /* Base. */
5217 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5218 {
5219 if (X86_IS_CANONICAL(Tr.u64Base))
5220 { /* likely */ }
5221 else
5222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5223 }
5224
5225 /* Attributes. */
5226 /* Reserved bits (bits 31:17 and bits 11:8). */
5227 if (!(Tr.Attr.u & 0xfffe0f00))
5228 { /* likely */ }
5229 else
5230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5231
5232 if (!Tr.Attr.n.u1Unusable)
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5236
5237 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5238 || ( !fGstInLongMode
5239 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5240 { /* likely */ }
5241 else
5242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5243
5244 if (!Tr.Attr.n.u1DescType)
5245 { /* likely */ }
5246 else
5247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5248
5249 if (Tr.Attr.n.u1Present)
5250 { /* likely */ }
5251 else
5252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5253
5254 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5255 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5256 { /* likely */ }
5257 else
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5259 }
5260
5261 NOREF(pszInstr);
5262 NOREF(pszFailure);
5263 return VINF_SUCCESS;
5264}
5265
5266
5267/**
5268 * Checks guest GDTR and IDTR as part of VM-entry.
5269 *
5270 * @param pVCpu The cross context virtual CPU structure.
5271 * @param pszInstr The VMX instruction name (for logging purposes).
5272 */
5273DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5274{
5275 /*
5276 * GDTR and IDTR.
5277 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5278 */
5279 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5280 const char *const pszFailure = "VM-exit";
5281
5282 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5283 {
5284 /* Base. */
5285 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5286 { /* likely */ }
5287 else
5288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5289
5290 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5291 { /* likely */ }
5292 else
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5294 }
5295
5296 /* Limit. */
5297 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5298 { /* likely */ }
5299 else
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5301
5302 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5303 { /* likely */ }
5304 else
5305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5306
5307 NOREF(pszInstr);
5308 NOREF(pszFailure);
5309 return VINF_SUCCESS;
5310}
5311
5312
5313/**
5314 * Checks guest RIP and RFLAGS as part of VM-entry.
5315 *
5316 * @param pVCpu The cross context virtual CPU structure.
5317 * @param pszInstr The VMX instruction name (for logging purposes).
5318 */
5319DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5320{
5321 /*
5322 * RIP and RFLAGS.
5323 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5324 */
5325 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5326 const char *const pszFailure = "VM-exit";
5327 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5328
5329 /* RIP. */
5330 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5331 {
5332 X86DESCATTR AttrCs;
5333 AttrCs.u = pVmcs->u32GuestCsAttr;
5334 if ( !fGstInLongMode
5335 || !AttrCs.n.u1Long)
5336 {
5337 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5338 { /* likely */ }
5339 else
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5341 }
5342
5343 if ( fGstInLongMode
5344 && AttrCs.n.u1Long)
5345 {
5346 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5347 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5348 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5349 { /* likely */ }
5350 else
5351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5352 }
5353 }
5354
5355 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5356 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5357 : pVmcs->u64GuestRFlags.s.Lo;
5358 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5359 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5360 { /* likely */ }
5361 else
5362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5363
5364 if ( fGstInLongMode
5365 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5366 {
5367 if (!(uGuestRFlags & X86_EFL_VM))
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5371 }
5372
5373 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5374 {
5375 if (uGuestRFlags & X86_EFL_IF)
5376 { /* likely */ }
5377 else
5378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5379 }
5380
5381 NOREF(pszInstr);
5382 NOREF(pszFailure);
5383 return VINF_SUCCESS;
5384}
5385
5386
5387/**
5388 * Checks guest non-register state as part of VM-entry.
5389 *
5390 * @param pVCpu The cross context virtual CPU structure.
5391 * @param pszInstr The VMX instruction name (for logging purposes).
5392 */
5393DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5394{
5395 /*
5396 * Guest non-register state.
5397 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5398 */
5399 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5400 const char *const pszFailure = "VM-exit";
5401
5402 /*
5403 * Activity state.
5404 */
5405 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5406 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5407 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5408 { /* likely */ }
5409 else
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5411
5412 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5413 if ( !AttrSs.n.u2Dpl
5414 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5418
5419 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5420 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5421 {
5422 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5423 { /* likely */ }
5424 else
5425 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5426 }
5427
5428 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5429 {
5430 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5431 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5432 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5433 switch (pVmcs->u32GuestActivityState)
5434 {
5435 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5436 {
5437 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5438 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5439 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5440 && ( uVector == X86_XCPT_DB
5441 || uVector == X86_XCPT_MC))
5442 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5443 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5444 { /* likely */ }
5445 else
5446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5447 break;
5448 }
5449
5450 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5451 {
5452 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5453 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5454 && uVector == X86_XCPT_MC))
5455 { /* likely */ }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5458 break;
5459 }
5460
5461 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5462 default:
5463 break;
5464 }
5465 }
5466
5467 /*
5468 * Interruptibility state.
5469 */
5470 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5471 { /* likely */ }
5472 else
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5474
5475 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5476 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5477 { /* likely */ }
5478 else
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5480
5481 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5482 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5486
5487 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5488 {
5489 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5490 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5491 {
5492 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5493 { /* likely */ }
5494 else
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5496 }
5497 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5498 {
5499 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5500 { /* likely */ }
5501 else
5502 {
5503 /*
5504 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5505 * We update the Exit qualification only when blocking-by-STI is set
5506 * without blocking-by-MovSS being set. Although in practise it does not
5507 * make much difference since the order of checks are implementation defined.
5508 */
5509 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5510 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5512 }
5513
5514 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5515 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5516 { /* likely */ }
5517 else
5518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5519 }
5520 }
5521
5522 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5523 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5524 { /* likely */ }
5525 else
5526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5527
5528 /* We don't support SGX yet. So enclave-interruption must not be set. */
5529 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5530 { /* likely */ }
5531 else
5532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5533
5534 /*
5535 * Pending debug exceptions.
5536 */
5537 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5538 ? pVmcs->u64GuestPendingDbgXcpts.u
5539 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5540 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5541 { /* likely */ }
5542 else
5543 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5544
5545 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5546 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5547 {
5548 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5549 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5550 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5552
5553 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5554 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5555 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5557 }
5558
5559 /* We don't support RTM (Real-time Transactional Memory) yet. */
5560 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5561 { /* likely */ }
5562 else
5563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5564
5565 /*
5566 * VMCS link pointer.
5567 */
5568 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5569 {
5570 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5571 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5572 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5573 { /* likely */ }
5574 else
5575 {
5576 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5578 }
5579
5580 /* Validate the address. */
5581 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5582 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5583 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5584 { /* likely */ }
5585 else
5586 {
5587 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5589 }
5590 }
5591
5592 NOREF(pszInstr);
5593 NOREF(pszFailure);
5594 return VINF_SUCCESS;
5595}
5596
5597
5598#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5599/**
5600 * Checks guest PDPTEs as part of VM-entry.
5601 *
5602 * @param pVCpu The cross context virtual CPU structure.
5603 * @param pszInstr The VMX instruction name (for logging purposes).
5604 */
5605IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5606{
5607 /*
5608 * Guest PDPTEs.
5609 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5610 */
5611 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5612 const char * const pszFailure = "VM-exit";
5613
5614 /*
5615 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5616 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5617 */
5618 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5619 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5620 {
5621 /* Get PDPTEs from the VMCS. */
5622 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5623 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5624 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5625 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5626 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5627
5628 /* Check validity of the PDPTEs. */
5629 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5630 if (fValid)
5631 { /* likely */ }
5632 else
5633 {
5634 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5636 }
5637 }
5638
5639 NOREF(pszFailure);
5640 NOREF(pszInstr);
5641 return VINF_SUCCESS;
5642}
5643#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
5644
5645
5646/**
5647 * Checks guest-state as part of VM-entry.
5648 *
5649 * @returns VBox status code.
5650 * @param pVCpu The cross context virtual CPU structure.
5651 * @param pszInstr The VMX instruction name (for logging purposes).
5652 */
5653IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5654{
5655 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5656 if (RT_SUCCESS(rc))
5657 {
5658 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5659 if (RT_SUCCESS(rc))
5660 {
5661 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5662 if (RT_SUCCESS(rc))
5663 {
5664 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5665 if (RT_SUCCESS(rc))
5666 {
5667 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5668#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5669 if (RT_SUCCESS(rc))
5670 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5671#endif
5672 }
5673 }
5674 }
5675 }
5676 return rc;
5677}
5678
5679
5680/**
5681 * Checks host-state as part of VM-entry.
5682 *
5683 * @returns VBox status code.
5684 * @param pVCpu The cross context virtual CPU structure.
5685 * @param pszInstr The VMX instruction name (for logging purposes).
5686 */
5687IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5688{
5689 /*
5690 * Host Control Registers and MSRs.
5691 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5692 */
5693 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5694 const char * const pszFailure = "VMFail";
5695
5696 /* CR0 reserved bits. */
5697 {
5698 /* CR0 MB1 bits. */
5699 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5700 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5701 { /* likely */ }
5702 else
5703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5704
5705 /* CR0 MBZ bits. */
5706 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5707 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5708 { /* likely */ }
5709 else
5710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5711 }
5712
5713 /* CR4 reserved bits. */
5714 {
5715 /* CR4 MB1 bits. */
5716 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5717 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5718 { /* likely */ }
5719 else
5720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5721
5722 /* CR4 MBZ bits. */
5723 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5724 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5725 { /* likely */ }
5726 else
5727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5728 }
5729
5730 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5731 {
5732 /* CR3 reserved bits. */
5733 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5734 { /* likely */ }
5735 else
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5737
5738 /* SYSENTER ESP and SYSENTER EIP. */
5739 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5740 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5744 }
5745
5746 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5747 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5748
5749 /* PAT MSR. */
5750 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5751 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5752 { /* likely */ }
5753 else
5754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5755
5756 /* EFER MSR. */
5757 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5758 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5759 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5763
5764 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5765 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5766 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5767 if ( fHostInLongMode == fHostLma
5768 && fHostInLongMode == fHostLme)
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5772
5773 /*
5774 * Host Segment and Descriptor-Table Registers.
5775 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5776 */
5777 /* Selector RPL and TI. */
5778 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5779 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5780 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5781 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5782 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5783 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5784 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5785 { /* likely */ }
5786 else
5787 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5788
5789 /* CS and TR selectors cannot be 0. */
5790 if ( pVmcs->HostCs
5791 && pVmcs->HostTr)
5792 { /* likely */ }
5793 else
5794 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5795
5796 /* SS cannot be 0 if 32-bit host. */
5797 if ( fHostInLongMode
5798 || pVmcs->HostSs)
5799 { /* likely */ }
5800 else
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5802
5803 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5804 {
5805 /* FS, GS, GDTR, IDTR, TR base address. */
5806 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5807 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5808 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5809 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5810 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5811 { /* likely */ }
5812 else
5813 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5814 }
5815
5816 /*
5817 * Host address-space size for 64-bit CPUs.
5818 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5819 */
5820 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5821 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5822 {
5823 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5824
5825 /* Logical processor in IA-32e mode. */
5826 if (fCpuInLongMode)
5827 {
5828 if (fHostInLongMode)
5829 {
5830 /* PAE must be set. */
5831 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5835
5836 /* RIP must be canonical. */
5837 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5838 { /* likely */ }
5839 else
5840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5841 }
5842 else
5843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5844 }
5845 else
5846 {
5847 /* Logical processor is outside IA-32e mode. */
5848 if ( !fGstInLongMode
5849 && !fHostInLongMode)
5850 {
5851 /* PCIDE should not be set. */
5852 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5856
5857 /* The high 32-bits of RIP MBZ. */
5858 if (!pVmcs->u64HostRip.s.Hi)
5859 { /* likely */ }
5860 else
5861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5862 }
5863 else
5864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5865 }
5866 }
5867 else
5868 {
5869 /* Host address-space size for 32-bit CPUs. */
5870 if ( !fGstInLongMode
5871 && !fHostInLongMode)
5872 { /* likely */ }
5873 else
5874 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5875 }
5876
5877 NOREF(pszInstr);
5878 NOREF(pszFailure);
5879 return VINF_SUCCESS;
5880}
5881
5882
5883#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5884/**
5885 * Checks the EPT pointer VMCS field as part of VM-entry.
5886 *
5887 * @returns VBox status code.
5888 * @param pVCpu The cross context virtual CPU structure.
5889 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5890 * updated on success). Optional, can be NULL.
5891 */
5892IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5893{
5894 VMXVDIAG enmVmxDiag;
5895 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5896
5897 /* Reserved bits. */
5898 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5899 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5900 if (pVmcs->u64EptPtr.u & fValidMask)
5901 {
5902 /* Memory Type. */
5903 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5904 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5905 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5906 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5907 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5908 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5909 {
5910 /*
5911 * Page walk length (PML4).
5912 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5913 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5914 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5915 */
5916 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5917 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5918 {
5919 /* Access and dirty bits support in EPT structures. */
5920 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5921 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5922 return VINF_SUCCESS;
5923
5924 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5925 }
5926 else
5927 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5928 }
5929 else
5930 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5931 }
5932 else
5933 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5934
5935 if (penmVmxDiag)
5936 *penmVmxDiag = enmVmxDiag;
5937 return VERR_VMX_VMENTRY_FAILED;
5938}
5939#endif
5940
5941
5942/**
5943 * Checks VMCS controls fields as part of VM-entry.
5944 *
5945 * @returns VBox status code.
5946 * @param pVCpu The cross context virtual CPU structure.
5947 * @param pszInstr The VMX instruction name (for logging purposes).
5948 *
5949 * @remarks This may update secondary-processor based VM-execution control fields
5950 * in the current VMCS if necessary.
5951 */
5952IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5953{
5954 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5955 const char * const pszFailure = "VMFail";
5956
5957 /*
5958 * VM-execution controls.
5959 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5960 */
5961 {
5962 /* Pin-based VM-execution controls. */
5963 {
5964 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5965 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5966 { /* likely */ }
5967 else
5968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5969
5970 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5971 { /* likely */ }
5972 else
5973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5974 }
5975
5976 /* Processor-based VM-execution controls. */
5977 {
5978 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5979 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5980 { /* likely */ }
5981 else
5982 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5983
5984 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
5985 { /* likely */ }
5986 else
5987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5988 }
5989
5990 /* Secondary processor-based VM-execution controls. */
5991 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5992 {
5993 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
5994 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
5995 { /* likely */ }
5996 else
5997 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5998
5999 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6003 }
6004 else
6005 Assert(!pVmcs->u32ProcCtls2);
6006
6007 /* CR3-target count. */
6008 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6009 { /* likely */ }
6010 else
6011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6012
6013 /* I/O bitmaps physical addresses. */
6014 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6015 {
6016 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6017 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6018 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6019 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6020 { /* likely */ }
6021 else
6022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6023
6024 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6025 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6026 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6027 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6028 { /* likely */ }
6029 else
6030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6031 }
6032
6033 /* MSR bitmap physical address. */
6034 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6035 {
6036 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6037 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6038 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6039 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6040 { /* likely */ }
6041 else
6042 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6043 }
6044
6045 /* TPR shadow related controls. */
6046 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6047 {
6048 /* Virtual-APIC page physical address. */
6049 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6050 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6051 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6052 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6053 { /* likely */ }
6054 else
6055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6056
6057 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6058 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6059 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6060 { /* likely */ }
6061 else
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6063
6064 /* The rest done XXX document */
6065 }
6066 else
6067 {
6068 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6069 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6070 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6071 { /* likely */ }
6072 else
6073 {
6074 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6076 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6077 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6078 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6080 }
6081 }
6082
6083 /* NMI exiting and virtual-NMIs. */
6084 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6085 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6086 { /* likely */ }
6087 else
6088 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6089
6090 /* Virtual-NMIs and NMI-window exiting. */
6091 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6092 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6093 { /* likely */ }
6094 else
6095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6096
6097 /* Virtualize APIC accesses. */
6098 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6099 {
6100 /* APIC-access physical address. */
6101 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6102 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6103 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6104 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6105 { /* likely */ }
6106 else
6107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6108
6109 /*
6110 * Disallow APIC-access page and virtual-APIC page from being the same address.
6111 * Note! This is not an Intel requirement, but one imposed by our implementation.
6112 */
6113 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6114 * redirecting accesses between the APIC-access page and the virtual-APIC
6115 * page. If any nested hypervisor requires this, we can implement it later. */
6116 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6117 {
6118 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6119 if (GCPhysVirtApic != GCPhysApicAccess)
6120 { /* likely */ }
6121 else
6122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6123 }
6124 }
6125
6126 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6127 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6128 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6129 { /* likely */ }
6130 else
6131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6132
6133 /* Virtual-interrupt delivery requires external interrupt exiting. */
6134 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6135 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6139
6140 /* VPID. */
6141 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6142 || pVmcs->u16Vpid != 0)
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6146
6147#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6148 /* Extended-Page-Table Pointer (EPTP). */
6149 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6150 {
6151 VMXVDIAG enmVmxDiag;
6152 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6153 if (RT_SUCCESS(rc))
6154 { /* likely */ }
6155 else
6156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6157 }
6158#else
6159 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6160#endif
6161
6162 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6163 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6164 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6165 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6166 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6167 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6168 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6169
6170 /* VMCS shadowing. */
6171 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6172 {
6173 /* VMREAD-bitmap physical address. */
6174 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6175 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6176 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6177 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6181
6182 /* VMWRITE-bitmap physical address. */
6183 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6184 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6185 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6186 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6190 }
6191 }
6192
6193 /*
6194 * VM-exit controls.
6195 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6196 */
6197 {
6198 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6199 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6203
6204 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6205 { /* likely */ }
6206 else
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6208
6209 /* Save preemption timer without activating it. */
6210 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6211 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6215
6216 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6217 if (pVmcs->u32ExitMsrStoreCount)
6218 {
6219 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6220 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6221 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6225 }
6226
6227 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6228 if (pVmcs->u32ExitMsrLoadCount)
6229 {
6230 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6231 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6232 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6233 { /* likely */ }
6234 else
6235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6236 }
6237 }
6238
6239 /*
6240 * VM-entry controls.
6241 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6242 */
6243 {
6244 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6245 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6246 { /* likely */ }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6249
6250 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6254
6255 /* Event injection. */
6256 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6257 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6258 {
6259 /* Type and vector. */
6260 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6261 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6262 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6263 if ( !uRsvd
6264 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6265 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6266 { /* likely */ }
6267 else
6268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6269
6270 /* Exception error code. */
6271 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6272 {
6273 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6274 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6275 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6276 { /* likely */ }
6277 else
6278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6279
6280 /* Exceptions that provide an error code. */
6281 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6282 && ( uVector == X86_XCPT_DF
6283 || uVector == X86_XCPT_TS
6284 || uVector == X86_XCPT_NP
6285 || uVector == X86_XCPT_SS
6286 || uVector == X86_XCPT_GP
6287 || uVector == X86_XCPT_PF
6288 || uVector == X86_XCPT_AC))
6289 { /* likely */ }
6290 else
6291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6292
6293 /* Exception error-code reserved bits. */
6294 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6295 { /* likely */ }
6296 else
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6298
6299 /* Injecting a software interrupt, software exception or privileged software exception. */
6300 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6301 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6302 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6303 {
6304 /* Instruction length must be in the range 0-15. */
6305 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6306 { /* likely */ }
6307 else
6308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6309
6310 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6311 if ( pVmcs->u32EntryInstrLen != 0
6312 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6313 { /* likely */ }
6314 else
6315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6316 }
6317 }
6318 }
6319
6320 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6321 if (pVmcs->u32EntryMsrLoadCount)
6322 {
6323 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6324 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6325 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6326 { /* likely */ }
6327 else
6328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6329 }
6330
6331 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6332 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6333 }
6334
6335 NOREF(pszInstr);
6336 NOREF(pszFailure);
6337 return VINF_SUCCESS;
6338}
6339
6340
6341/**
6342 * Loads the guest control registers, debug register and some MSRs as part of
6343 * VM-entry.
6344 *
6345 * @param pVCpu The cross context virtual CPU structure.
6346 */
6347IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6348{
6349 /*
6350 * Load guest control registers, debug registers and MSRs.
6351 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6352 */
6353 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6354
6355 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6356 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6357 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6358 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6359 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6360 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6361
6362 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6363 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6364
6365 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6366 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6367 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6368
6369 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6370 {
6371 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6372
6373 /* EFER MSR. */
6374 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6375 {
6376 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6377 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6378 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6379 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6380 if (fGstInLongMode)
6381 {
6382 /* If the nested-guest is in long mode, LMA and LME are both set. */
6383 Assert(fGstPaging);
6384 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6385 }
6386 else
6387 {
6388 /*
6389 * If the nested-guest is outside long mode:
6390 * - With paging: LMA is cleared, LME is cleared.
6391 * - Without paging: LMA is cleared, LME is left unmodified.
6392 */
6393 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6394 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6395 }
6396 }
6397 /* else: see below. */
6398 }
6399
6400 /* PAT MSR. */
6401 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6402 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6403
6404 /* EFER MSR. */
6405 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6406 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6407
6408 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6409 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6410
6411 /* We don't support IA32_BNDCFGS MSR yet. */
6412 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6413
6414 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6415}
6416
6417
6418/**
6419 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6420 *
6421 * @param pVCpu The cross context virtual CPU structure.
6422 */
6423IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6424{
6425 /*
6426 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6427 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6428 */
6429 /* CS, SS, ES, DS, FS, GS. */
6430 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6431 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6432 {
6433 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6434 CPUMSELREG VmcsSelReg;
6435 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6436 AssertRC(rc); NOREF(rc);
6437 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6438 {
6439 pGstSelReg->Sel = VmcsSelReg.Sel;
6440 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6441 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6442 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6443 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6444 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6445 }
6446 else
6447 {
6448 pGstSelReg->Sel = VmcsSelReg.Sel;
6449 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6450 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6451 switch (iSegReg)
6452 {
6453 case X86_SREG_CS:
6454 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6455 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6456 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6457 break;
6458
6459 case X86_SREG_SS:
6460 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6461 pGstSelReg->u32Limit = 0;
6462 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6463 break;
6464
6465 case X86_SREG_ES:
6466 case X86_SREG_DS:
6467 pGstSelReg->u64Base = 0;
6468 pGstSelReg->u32Limit = 0;
6469 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6470 break;
6471
6472 case X86_SREG_FS:
6473 case X86_SREG_GS:
6474 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6475 pGstSelReg->u32Limit = 0;
6476 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6477 break;
6478 }
6479 Assert(pGstSelReg->Attr.n.u1Unusable);
6480 }
6481 }
6482
6483 /* LDTR. */
6484 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6485 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6486 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6487 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6488 {
6489 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6490 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6491 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6492 }
6493 else
6494 {
6495 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6496 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6497 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6498 }
6499
6500 /* TR. */
6501 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6502 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6503 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6504 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6505 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6506 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6507 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6508
6509 /* GDTR. */
6510 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6511 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6512
6513 /* IDTR. */
6514 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6515 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6516}
6517
6518
6519/**
6520 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6521 *
6522 * @returns VBox status code.
6523 * @param pVCpu The cross context virtual CPU structure.
6524 * @param pszInstr The VMX instruction name (for logging purposes).
6525 */
6526IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6527{
6528 /*
6529 * Load guest MSRs.
6530 * See Intel spec. 26.4 "Loading MSRs".
6531 */
6532 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6533 const char *const pszFailure = "VM-exit";
6534
6535 /*
6536 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6537 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6538 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6539 */
6540 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6541 if (!cMsrs)
6542 return VINF_SUCCESS;
6543
6544 /*
6545 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6546 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6547 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6548 */
6549 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6550 if (fIsMsrCountValid)
6551 { /* likely */ }
6552 else
6553 {
6554 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6556 }
6557
6558 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6559 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6560 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6561 if (RT_SUCCESS(rc))
6562 {
6563 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6564 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6565 {
6566 if ( !pMsr->u32Reserved
6567 && pMsr->u32Msr != MSR_K8_FS_BASE
6568 && pMsr->u32Msr != MSR_K8_GS_BASE
6569 && pMsr->u32Msr != MSR_K6_EFER
6570 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6571 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6572 {
6573 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6574 if (rcStrict == VINF_SUCCESS)
6575 continue;
6576
6577 /*
6578 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6579 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6580 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6581 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6582 * MSR in ring-0 if possible, or come up with a better, generic solution.
6583 */
6584 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6585 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6586 ? kVmxVDiag_Vmentry_MsrLoadRing3
6587 : kVmxVDiag_Vmentry_MsrLoad;
6588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6589 }
6590 else
6591 {
6592 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6594 }
6595 }
6596 }
6597 else
6598 {
6599 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6601 }
6602
6603 NOREF(pszInstr);
6604 NOREF(pszFailure);
6605 return VINF_SUCCESS;
6606}
6607
6608
6609/**
6610 * Loads the guest-state non-register state as part of VM-entry.
6611 *
6612 * @returns VBox status code.
6613 * @param pVCpu The cross context virtual CPU structure.
6614 * @param pszInstr The VMX instruction name (for logging purposes).
6615 *
6616 * @remarks This must be called only after loading the nested-guest register state
6617 * (especially nested-guest RIP).
6618 */
6619IEM_STATIC int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
6620{
6621 /*
6622 * Load guest non-register state.
6623 * See Intel spec. 26.6 "Special Features of VM Entry"
6624 */
6625 const char *const pszFailure = "VM-exit";
6626 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6627
6628 /*
6629 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6630 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6631 *
6632 * See Intel spec. 26.6.1 "Interruptibility State".
6633 */
6634 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6635 if ( !fEntryVectoring
6636 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6637 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6638 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6639 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6640
6641 /* NMI blocking. */
6642 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6643 {
6644 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6645 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6646 else
6647 {
6648 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6649 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6650 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6651 }
6652 }
6653 else
6654 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6655
6656 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6657
6658 /*
6659 * Set PGM's copy of the EPT pointer.
6660 * The EPTP has already been validated while checking guest state.
6661 *
6662 * It is important to do this prior to mapping PAE PDPTEs (below).
6663 */
6664 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6665 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6666
6667 /*
6668 * Load the guest's PAE PDPTEs.
6669 */
6670 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
6671 {
6672 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6673 {
6674 /*
6675 * With EPT, we've already validated these while checking the guest state.
6676 * Just load them directly from the VMCS here.
6677 */
6678 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6679 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6680 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6681 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6682 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6683 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6684 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6685 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6686 }
6687 else
6688 {
6689 /*
6690 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
6691 * This involves loading (and mapping) CR3 and validating them now.
6692 */
6693 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
6694 if (RT_SUCCESS(rc))
6695 { /* likely */ }
6696 else
6697 {
6698 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6699 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6700 }
6701 }
6702 }
6703
6704 /* VPID is irrelevant. We don't support VPID yet. */
6705
6706 /* Clear address-range monitoring. */
6707 EMMonitorWaitClear(pVCpu);
6708
6709 return VINF_SUCCESS;
6710}
6711
6712
6713/**
6714 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6715 *
6716 * @param pVCpu The cross context virtual CPU structure.
6717 * @param pszInstr The VMX instruction name (for logging purposes).
6718 *
6719 * @remarks This assumes various VMCS related data structure pointers have already
6720 * been verified prior to calling this function.
6721 */
6722IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6723{
6724 const char *const pszFailure = "VM-exit";
6725 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6726
6727 /*
6728 * Virtualize APIC accesses.
6729 */
6730 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6731 {
6732 /* APIC-access physical address. */
6733 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6734
6735 /*
6736 * Register the handler for the APIC-access page.
6737 *
6738 * We don't deregister the APIC-access page handler during the VM-exit as a different
6739 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6740 *
6741 * We leave the page registered until the first access that happens outside VMX non-root
6742 * mode. Guest software is allowed to access structures such as the APIC-access page
6743 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6744 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6745 *
6746 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6747 */
6748 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6749 {
6750 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6751 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6752 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6753 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6754 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6755 if (RT_SUCCESS(rc))
6756 { /* likely */ }
6757 else
6758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6759 }
6760 }
6761
6762 /*
6763 * VMCS shadowing.
6764 */
6765 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6766 {
6767 /* Read the VMREAD-bitmap. */
6768 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6769 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6770 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6771 if (RT_SUCCESS(rc))
6772 { /* likely */ }
6773 else
6774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6775
6776 /* Read the VMWRITE-bitmap. */
6777 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6778 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6779 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6780 if (RT_SUCCESS(rc))
6781 { /* likely */ }
6782 else
6783 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6784 }
6785
6786 /*
6787 * I/O bitmaps.
6788 */
6789 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6790 {
6791 /* Read the IO bitmap A. */
6792 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6793 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6794 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6795 if (RT_SUCCESS(rc))
6796 { /* likely */ }
6797 else
6798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6799
6800 /* Read the IO bitmap B. */
6801 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6802 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6803 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6804 if (RT_SUCCESS(rc))
6805 { /* likely */ }
6806 else
6807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6808 }
6809
6810 /*
6811 * TPR shadow and Virtual-APIC page.
6812 */
6813 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6814 {
6815 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6816 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6817 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6818 {
6819 /* Read the VTPR from the virtual-APIC page. */
6820 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6821 uint8_t u8VTpr;
6822 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6823 if (RT_SUCCESS(rc))
6824 { /* likely */ }
6825 else
6826 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6827
6828 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6829 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6830 { /* likely */ }
6831 else
6832 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6833 }
6834 }
6835
6836 /*
6837 * VMCS link pointer.
6838 */
6839 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6840 {
6841 /* Read the VMCS-link pointer from guest memory. */
6842 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6843 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6844 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6845 if (RT_SUCCESS(rc))
6846 { /* likely */ }
6847 else
6848 {
6849 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6851 }
6852
6853 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6854 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6855 { /* likely */ }
6856 else
6857 {
6858 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6860 }
6861
6862 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6863 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6864 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6865 { /* likely */ }
6866 else
6867 {
6868 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6870 }
6871
6872 /* Update our cache of the guest physical address of the shadow VMCS. */
6873 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6874 }
6875
6876 /*
6877 * MSR bitmap.
6878 */
6879 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6880 {
6881 /* Read the MSR bitmap. */
6882 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6883 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6884 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6885 if (RT_SUCCESS(rc))
6886 { /* likely */ }
6887 else
6888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6889 }
6890
6891 NOREF(pszFailure);
6892 NOREF(pszInstr);
6893 return VINF_SUCCESS;
6894}
6895
6896
6897/**
6898 * Loads the guest-state as part of VM-entry.
6899 *
6900 * @returns VBox status code.
6901 * @param pVCpu The cross context virtual CPU structure.
6902 * @param pszInstr The VMX instruction name (for logging purposes).
6903 *
6904 * @remarks This must be done after all the necessary steps prior to loading of
6905 * guest-state (e.g. checking various VMCS state).
6906 */
6907IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6908{
6909 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6910 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6911
6912 /* Load guest segment registers. */
6913 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6914
6915 /*
6916 * Load guest RIP, RSP and RFLAGS.
6917 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6918 */
6919 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6920 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6921 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6922 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6923
6924 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6925 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6926 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6927
6928 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6929 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
6930 if (rc == VINF_SUCCESS)
6931 { /* likely */ }
6932 else
6933 return rc;
6934
6935 /* Load VMX related structures and state referenced by the VMCS. */
6936 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6937 if (rc == VINF_SUCCESS)
6938 { /* likely */ }
6939 else
6940 return rc;
6941
6942 NOREF(pszInstr);
6943 return VINF_SUCCESS;
6944}
6945
6946
6947/**
6948 * Returns whether there are is a pending debug exception on VM-entry.
6949 *
6950 * @param pVCpu The cross context virtual CPU structure.
6951 * @param pszInstr The VMX instruction name (for logging purposes).
6952 */
6953IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6954{
6955 /*
6956 * Pending debug exceptions.
6957 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6958 */
6959 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6960 Assert(pVmcs);
6961
6962 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6963 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6964 if (fPendingDbgXcpt)
6965 {
6966 uint8_t uEntryIntInfoType;
6967 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6968 if (fEntryVectoring)
6969 {
6970 switch (uEntryIntInfoType)
6971 {
6972 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6973 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6974 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6975 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6976 fPendingDbgXcpt = false;
6977 break;
6978
6979 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6980 {
6981 /*
6982 * Whether the pending debug exception for software exceptions other than
6983 * #BP and #OF is delivered after injecting the exception or is discard
6984 * is CPU implementation specific. We will discard them (easier).
6985 */
6986 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6987 if ( uVector != X86_XCPT_BP
6988 && uVector != X86_XCPT_OF)
6989 fPendingDbgXcpt = false;
6990 RT_FALL_THRU();
6991 }
6992 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6993 {
6994 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6995 fPendingDbgXcpt = false;
6996 break;
6997 }
6998 }
6999 }
7000 else
7001 {
7002 /*
7003 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7004 * pending debug exception is held pending or is discarded is CPU implementation
7005 * specific. We will discard them (easier).
7006 */
7007 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7008 fPendingDbgXcpt = false;
7009
7010 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7011 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7012 fPendingDbgXcpt = false;
7013 }
7014 }
7015
7016 NOREF(pszInstr);
7017 return fPendingDbgXcpt;
7018}
7019
7020
7021/**
7022 * Set up the monitor-trap flag (MTF).
7023 *
7024 * @param pVCpu The cross context virtual CPU structure.
7025 * @param pszInstr The VMX instruction name (for logging purposes).
7026 */
7027IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7028{
7029 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7030 Assert(pVmcs);
7031 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7032 {
7033 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7034 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7035 }
7036 else
7037 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7038 NOREF(pszInstr);
7039}
7040
7041
7042/**
7043 * Sets up NMI-window exiting.
7044 *
7045 * @param pVCpu The cross context virtual CPU structure.
7046 * @param pszInstr The VMX instruction name (for logging purposes).
7047 */
7048IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7049{
7050 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7051 Assert(pVmcs);
7052 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7053 {
7054 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7055 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7056 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7057 }
7058 else
7059 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7060 NOREF(pszInstr);
7061}
7062
7063
7064/**
7065 * Sets up interrupt-window exiting.
7066 *
7067 * @param pVCpu The cross context virtual CPU structure.
7068 * @param pszInstr The VMX instruction name (for logging purposes).
7069 */
7070IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7071{
7072 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7073 Assert(pVmcs);
7074 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7075 {
7076 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7077 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7078 }
7079 else
7080 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7081 NOREF(pszInstr);
7082}
7083
7084
7085/**
7086 * Set up the VMX-preemption timer.
7087 *
7088 * @param pVCpu The cross context virtual CPU structure.
7089 * @param pszInstr The VMX instruction name (for logging purposes).
7090 */
7091IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7092{
7093 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7094 Assert(pVmcs);
7095 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7096 {
7097 /*
7098 * If the timer is 0, we must cause a VM-exit before executing the first
7099 * nested-guest instruction. So we can flag as though the timer has already
7100 * expired and we will check and cause a VM-exit at the right priority elsewhere
7101 * in the code.
7102 */
7103 uint64_t uEntryTick;
7104 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7105 if (uPreemptTimer)
7106 {
7107 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7108 AssertRC(rc);
7109 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7110 }
7111 else
7112 {
7113 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7114 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7115 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7116 }
7117
7118 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7119 }
7120 else
7121 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7122
7123 NOREF(pszInstr);
7124}
7125
7126
7127/**
7128 * Injects an event using TRPM given a VM-entry interruption info. and related
7129 * fields.
7130 *
7131 * @param pVCpu The cross context virtual CPU structure.
7132 * @param pszInstr The VMX instruction name (for logging purposes).
7133 * @param uEntryIntInfo The VM-entry interruption info.
7134 * @param uErrCode The error code associated with the event if any.
7135 * @param cbInstr The VM-entry instruction length (for software
7136 * interrupts and software exceptions). Pass 0
7137 * otherwise.
7138 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7139 */
7140IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7141 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7142{
7143 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7144
7145 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7146 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7147 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7148
7149 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7150
7151 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7152 AssertRC(rc);
7153 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7154
7155 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7156 {
7157 TRPMSetErrorCode(pVCpu, uErrCode);
7158 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7159 }
7160
7161 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7162 {
7163 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7164 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7165 }
7166 else
7167 {
7168 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7169 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7170 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7171 {
7172 TRPMSetInstrLength(pVCpu, cbInstr);
7173 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7174 }
7175 }
7176
7177 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7178 {
7179 TRPMSetTrapDueToIcebp(pVCpu);
7180 Log(("%s: Injecting: icebp\n", pszInstr));
7181 }
7182
7183 NOREF(pszInstr);
7184}
7185
7186
7187/**
7188 * Performs event injection (if any) as part of VM-entry.
7189 *
7190 * @param pVCpu The cross context virtual CPU structure.
7191 * @param pszInstr The VMX instruction name (for logging purposes).
7192 */
7193IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7194{
7195 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7196
7197 /*
7198 * Inject events.
7199 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7200 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7201 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7202 * the actually delivery of this event.
7203 *
7204 * See Intel spec. 26.5 "Event Injection".
7205 */
7206 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7207 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7208
7209 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7210 if (fEntryIntInfoValid)
7211 {
7212 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7213 {
7214 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7215 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7216 }
7217 else
7218 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7219 pVCpu->cpum.GstCtx.cr2);
7220
7221 /*
7222 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7223 *
7224 * However, we do it here on VM-entry as well because while it isn't visible to guest
7225 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7226 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7227 *
7228 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7229 */
7230 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7231 }
7232 else
7233 {
7234 /*
7235 * Inject any pending guest debug exception.
7236 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7237 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7238 */
7239 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7240 if (fPendingDbgXcpt)
7241 {
7242 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7243 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7244 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7245 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7246 0 /* GCPtrFaultAddress */);
7247 }
7248 }
7249
7250 NOREF(pszInstr);
7251}
7252
7253
7254/**
7255 * Initializes all read-only VMCS fields as part of VM-entry.
7256 *
7257 * @param pVCpu The cross context virtual CPU structure.
7258 */
7259IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7260{
7261 /*
7262 * Any VMCS field which we do not establish on every VM-exit but may potentially
7263 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7264 * specified to be undefined, needs to be initialized here.
7265 *
7266 * Thus, it is especially important to clear the Exit qualification field
7267 * since it must be zero for VM-exits where it is not used. Similarly, the
7268 * VM-exit interruption information field's valid bit needs to be cleared for
7269 * the same reasons.
7270 */
7271 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7272 Assert(pVmcs);
7273
7274 /* 16-bit (none currently). */
7275 /* 32-bit. */
7276 pVmcs->u32RoVmInstrError = 0;
7277 pVmcs->u32RoExitReason = 0;
7278 pVmcs->u32RoExitIntInfo = 0;
7279 pVmcs->u32RoExitIntErrCode = 0;
7280 pVmcs->u32RoIdtVectoringInfo = 0;
7281 pVmcs->u32RoIdtVectoringErrCode = 0;
7282 pVmcs->u32RoExitInstrLen = 0;
7283 pVmcs->u32RoExitInstrInfo = 0;
7284
7285 /* 64-bit. */
7286 pVmcs->u64RoGuestPhysAddr.u = 0;
7287
7288 /* Natural-width. */
7289 pVmcs->u64RoExitQual.u = 0;
7290 pVmcs->u64RoIoRcx.u = 0;
7291 pVmcs->u64RoIoRsi.u = 0;
7292 pVmcs->u64RoIoRdi.u = 0;
7293 pVmcs->u64RoIoRip.u = 0;
7294 pVmcs->u64RoGuestLinearAddr.u = 0;
7295}
7296
7297
7298/**
7299 * VMLAUNCH/VMRESUME instruction execution worker.
7300 *
7301 * @returns Strict VBox status code.
7302 * @param pVCpu The cross context virtual CPU structure.
7303 * @param cbInstr The instruction length in bytes.
7304 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7305 * VMXINSTRID_VMRESUME).
7306 *
7307 * @remarks Common VMX instruction checks are already expected to by the caller,
7308 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7309 */
7310IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7311{
7312# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7313 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7314 return VINF_EM_RAW_EMULATE_INSTR;
7315# else
7316 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7317 || uInstrId == VMXINSTRID_VMRESUME);
7318 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7319
7320 /* Nested-guest intercept. */
7321 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7322 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7323
7324 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7325
7326 /*
7327 * Basic VM-entry checks.
7328 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7329 * The checks following that do not have to follow a specific order.
7330 *
7331 * See Intel spec. 26.1 "Basic VM-entry Checks".
7332 */
7333
7334 /* CPL. */
7335 if (pVCpu->iem.s.uCpl == 0)
7336 { /* likely */ }
7337 else
7338 {
7339 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7340 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7341 return iemRaiseGeneralProtectionFault0(pVCpu);
7342 }
7343
7344 /* Current VMCS valid. */
7345 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7346 { /* likely */ }
7347 else
7348 {
7349 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7350 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7351 iemVmxVmFailInvalid(pVCpu);
7352 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7353 return VINF_SUCCESS;
7354 }
7355
7356 /* Current VMCS is not a shadow VMCS. */
7357 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7358 { /* likely */ }
7359 else
7360 {
7361 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7362 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7363 iemVmxVmFailInvalid(pVCpu);
7364 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7365 return VINF_SUCCESS;
7366 }
7367
7368 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7369 * use block-by-STI here which is not quite correct. */
7370 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7371 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7372 { /* likely */ }
7373 else
7374 {
7375 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7377 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7378 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7379 return VINF_SUCCESS;
7380 }
7381
7382 if (uInstrId == VMXINSTRID_VMLAUNCH)
7383 {
7384 /* VMLAUNCH with non-clear VMCS. */
7385 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7386 { /* likely */ }
7387 else
7388 {
7389 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7390 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7391 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7392 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7393 return VINF_SUCCESS;
7394 }
7395 }
7396 else
7397 {
7398 /* VMRESUME with non-launched VMCS. */
7399 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7400 { /* likely */ }
7401 else
7402 {
7403 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7405 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7406 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7407 return VINF_SUCCESS;
7408 }
7409 }
7410
7411 /*
7412 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7413 * while entering VMX non-root mode. We do some of this while checking VM-execution
7414 * controls. The nested hypervisor should not make assumptions and cannot expect
7415 * predictable behavior if changes to these structures are made in guest memory while
7416 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7417 * modify them anyway as we cache them in host memory.
7418 *
7419 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7420 */
7421 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7422 Assert(pVmcs);
7423 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7424
7425 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7426 if (RT_SUCCESS(rc))
7427 {
7428 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7429 if (RT_SUCCESS(rc))
7430 {
7431 /*
7432 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7433 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7434 * ones that may occur during VM-entry below).
7435 */
7436 iemVmxVmentryInitReadOnlyFields(pVCpu);
7437
7438 /*
7439 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7440 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7441 * VM-exit when required.
7442 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7443 */
7444 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7445
7446 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7447 if (RT_SUCCESS(rc))
7448 {
7449 /*
7450 * We've now entered nested-guest execution.
7451 *
7452 * It is important do this prior to loading the guest state because
7453 * as part of loading the guest state, PGM (and perhaps other components
7454 * in the future) relies on detecting whether VMX non-root mode has been
7455 * entered.
7456 */
7457 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7458
7459 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7460 if (RT_SUCCESS(rc))
7461 {
7462 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7463 if (RT_SUCCESS(rc))
7464 {
7465 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7466
7467 /* VMLAUNCH instruction must update the VMCS launch state. */
7468 if (uInstrId == VMXINSTRID_VMLAUNCH)
7469 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7470
7471 /* Perform the VMX transition (PGM updates). */
7472 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7473 if (rcStrict == VINF_SUCCESS)
7474 { /* likely */ }
7475 else if (RT_SUCCESS(rcStrict))
7476 {
7477 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7478 VBOXSTRICTRC_VAL(rcStrict)));
7479 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7480 }
7481 else
7482 {
7483 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7484 return rcStrict;
7485 }
7486
7487 /* Paranoia. */
7488 Assert(rcStrict == VINF_SUCCESS);
7489
7490 /*
7491 * The priority of potential VM-exits during VM-entry is important.
7492 * The priorities of VM-exits and events are listed from highest
7493 * to lowest as follows:
7494 *
7495 * 1. Event injection.
7496 * 2. Trap on task-switch (T flag set in TSS).
7497 * 3. TPR below threshold / APIC-write.
7498 * 4. SMI, INIT.
7499 * 5. MTF exit.
7500 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7501 * 7. VMX-preemption timer.
7502 * 9. NMI-window exit.
7503 * 10. NMI injection.
7504 * 11. Interrupt-window exit.
7505 * 12. Virtual-interrupt injection.
7506 * 13. Interrupt injection.
7507 * 14. Process next instruction (fetch, decode, execute).
7508 */
7509
7510 /* Setup VMX-preemption timer. */
7511 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7512
7513 /* Setup monitor-trap flag. */
7514 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7515
7516 /* Setup NMI-window exiting. */
7517 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7518
7519 /* Setup interrupt-window exiting. */
7520 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7521
7522 /*
7523 * Inject any event that the nested hypervisor wants to inject.
7524 * Note! We cannot immediately perform the event injection here as we may have
7525 * pending PGM operations to perform due to switching page tables and/or
7526 * mode.
7527 */
7528 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7529
7530# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7531 /* Reschedule to IEM-only execution of the nested-guest. */
7532 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7533 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7534 if (rcSched != VINF_SUCCESS)
7535 iemSetPassUpStatus(pVCpu, rcSched);
7536# endif
7537
7538 /* Finally, done. */
7539 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7540 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7541 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7542 pVCpu->cpum.GstCtx.msrEFER));
7543 return VINF_SUCCESS;
7544 }
7545 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7546 pVmcs->u64RoExitQual.u);
7547 }
7548 }
7549 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7550 pVmcs->u64RoExitQual.u);
7551 }
7552
7553 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7554 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7555 return VINF_SUCCESS;
7556 }
7557
7558 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7559 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7560 return VINF_SUCCESS;
7561# endif
7562}
7563
7564
7565/**
7566 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7567 * (causes a VM-exit) or not.
7568 *
7569 * @returns @c true if the instruction is intercepted, @c false otherwise.
7570 * @param pVCpu The cross context virtual CPU structure.
7571 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7572 * VMX_EXIT_WRMSR).
7573 * @param idMsr The MSR.
7574 */
7575IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7576{
7577 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7578 Assert( uExitReason == VMX_EXIT_RDMSR
7579 || uExitReason == VMX_EXIT_WRMSR);
7580
7581 /* Consult the MSR bitmap if the feature is supported. */
7582 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7583 Assert(pVmcs);
7584 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7585 {
7586 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7587 if (uExitReason == VMX_EXIT_RDMSR)
7588 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7589 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7590 }
7591
7592 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7593 return true;
7594}
7595
7596
7597/**
7598 * VMREAD instruction execution worker that does not perform any validation checks.
7599 *
7600 * Callers are expected to have performed the necessary checks and to ensure the
7601 * VMREAD will succeed.
7602 *
7603 * @param pVmcs Pointer to the virtual VMCS.
7604 * @param pu64Dst Where to write the VMCS value.
7605 * @param u64VmcsField The VMCS field.
7606 *
7607 * @remarks May be called with interrupts disabled.
7608 */
7609IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7610{
7611 VMXVMCSFIELD VmcsField;
7612 VmcsField.u = u64VmcsField;
7613 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7614 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7615 uint8_t const uWidthType = (uWidth << 2) | uType;
7616 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7617 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7618 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7619 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7620 uWidth, uType, uIndex, uIndex));
7621 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7622
7623 /*
7624 * Read the VMCS component based on the field's effective width.
7625 *
7626 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7627 * indicates high bits (little endian).
7628 *
7629 * Note! The caller is responsible to trim the result and update registers
7630 * or memory locations are required. Here we just zero-extend to the largest
7631 * type (i.e. 64-bits).
7632 */
7633 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7634 uint8_t const *pbField = pbVmcs + offField;
7635 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7636 switch (uEffWidth)
7637 {
7638 case VMX_VMCSFIELD_WIDTH_64BIT:
7639 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7640 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7641 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7642 }
7643}
7644
7645
7646/**
7647 * VMREAD common (memory/register) instruction execution worker.
7648 *
7649 * @returns Strict VBox status code.
7650 * @param pVCpu The cross context virtual CPU structure.
7651 * @param cbInstr The instruction length in bytes.
7652 * @param pu64Dst Where to write the VMCS value (only updated when
7653 * VINF_SUCCESS is returned).
7654 * @param u64VmcsField The VMCS field.
7655 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7656 * NULL.
7657 */
7658IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7659 PCVMXVEXITINFO pExitInfo)
7660{
7661 /* Nested-guest intercept. */
7662 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7663 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7664 {
7665 if (pExitInfo)
7666 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7667 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7668 }
7669
7670 /* CPL. */
7671 if (pVCpu->iem.s.uCpl == 0)
7672 { /* likely */ }
7673 else
7674 {
7675 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7676 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7677 return iemRaiseGeneralProtectionFault0(pVCpu);
7678 }
7679
7680 /* VMCS pointer in root mode. */
7681 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7682 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7683 { /* likely */ }
7684 else
7685 {
7686 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7687 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7688 iemVmxVmFailInvalid(pVCpu);
7689 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7690 return VINF_SUCCESS;
7691 }
7692
7693 /* VMCS-link pointer in non-root mode. */
7694 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7695 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7696 { /* likely */ }
7697 else
7698 {
7699 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7700 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7701 iemVmxVmFailInvalid(pVCpu);
7702 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7703 return VINF_SUCCESS;
7704 }
7705
7706 /* Supported VMCS field. */
7707 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7708 { /* likely */ }
7709 else
7710 {
7711 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7712 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7713 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7714 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7716 return VINF_SUCCESS;
7717 }
7718
7719 /*
7720 * Reading from the current or shadow VMCS.
7721 */
7722 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7723 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7724 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7725 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7726 return VINF_SUCCESS;
7727}
7728
7729
7730/**
7731 * VMREAD (64-bit register) instruction execution worker.
7732 *
7733 * @returns Strict VBox status code.
7734 * @param pVCpu The cross context virtual CPU structure.
7735 * @param cbInstr The instruction length in bytes.
7736 * @param pu64Dst Where to store the VMCS field's value.
7737 * @param u64VmcsField The VMCS field.
7738 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7739 * NULL.
7740 */
7741IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7742 PCVMXVEXITINFO pExitInfo)
7743{
7744 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7745 if (rcStrict == VINF_SUCCESS)
7746 {
7747 iemVmxVmreadSuccess(pVCpu, cbInstr);
7748 return VINF_SUCCESS;
7749 }
7750
7751 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7752 return rcStrict;
7753}
7754
7755
7756/**
7757 * VMREAD (32-bit register) instruction execution worker.
7758 *
7759 * @returns Strict VBox status code.
7760 * @param pVCpu The cross context virtual CPU structure.
7761 * @param cbInstr The instruction length in bytes.
7762 * @param pu32Dst Where to store the VMCS field's value.
7763 * @param u32VmcsField The VMCS field.
7764 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7765 * NULL.
7766 */
7767IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7768 PCVMXVEXITINFO pExitInfo)
7769{
7770 uint64_t u64Dst;
7771 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7772 if (rcStrict == VINF_SUCCESS)
7773 {
7774 *pu32Dst = u64Dst;
7775 iemVmxVmreadSuccess(pVCpu, cbInstr);
7776 return VINF_SUCCESS;
7777 }
7778
7779 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7780 return rcStrict;
7781}
7782
7783
7784/**
7785 * VMREAD (memory) instruction execution worker.
7786 *
7787 * @returns Strict VBox status code.
7788 * @param pVCpu The cross context virtual CPU structure.
7789 * @param cbInstr The instruction length in bytes.
7790 * @param iEffSeg The effective segment register to use with @a u64Val.
7791 * Pass UINT8_MAX if it is a register access.
7792 * @param GCPtrDst The guest linear address to store the VMCS field's
7793 * value.
7794 * @param u64VmcsField The VMCS field.
7795 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7796 * NULL.
7797 */
7798IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7799 PCVMXVEXITINFO pExitInfo)
7800{
7801 uint64_t u64Dst;
7802 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7803 if (rcStrict == VINF_SUCCESS)
7804 {
7805 /*
7806 * Write the VMCS field's value to the location specified in guest-memory.
7807 */
7808 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7809 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7810 else
7811 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7812 if (rcStrict == VINF_SUCCESS)
7813 {
7814 iemVmxVmreadSuccess(pVCpu, cbInstr);
7815 return VINF_SUCCESS;
7816 }
7817
7818 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7819 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7820 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7821 return rcStrict;
7822 }
7823
7824 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7825 return rcStrict;
7826}
7827
7828
7829/**
7830 * VMWRITE instruction execution worker that does not perform any validation
7831 * checks.
7832 *
7833 * Callers are expected to have performed the necessary checks and to ensure the
7834 * VMWRITE will succeed.
7835 *
7836 * @param pVmcs Pointer to the virtual VMCS.
7837 * @param u64Val The value to write.
7838 * @param u64VmcsField The VMCS field.
7839 *
7840 * @remarks May be called with interrupts disabled.
7841 */
7842IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7843{
7844 VMXVMCSFIELD VmcsField;
7845 VmcsField.u = u64VmcsField;
7846 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7847 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7848 uint8_t const uWidthType = (uWidth << 2) | uType;
7849 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7850 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7851 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7852 Assert(offField < VMX_V_VMCS_SIZE);
7853 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7854
7855 /*
7856 * Write the VMCS component based on the field's effective width.
7857 *
7858 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7859 * indicates high bits (little endian).
7860 */
7861 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7862 uint8_t *pbField = pbVmcs + offField;
7863 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7864 switch (uEffWidth)
7865 {
7866 case VMX_VMCSFIELD_WIDTH_64BIT:
7867 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7868 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7869 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7870 }
7871}
7872
7873
7874/**
7875 * VMWRITE instruction execution worker.
7876 *
7877 * @returns Strict VBox status code.
7878 * @param pVCpu The cross context virtual CPU structure.
7879 * @param cbInstr The instruction length in bytes.
7880 * @param iEffSeg The effective segment register to use with @a u64Val.
7881 * Pass UINT8_MAX if it is a register access.
7882 * @param u64Val The value to write (or guest linear address to the
7883 * value), @a iEffSeg will indicate if it's a memory
7884 * operand.
7885 * @param u64VmcsField The VMCS field.
7886 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7887 * NULL.
7888 */
7889IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7890 PCVMXVEXITINFO pExitInfo)
7891{
7892 /* Nested-guest intercept. */
7893 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7894 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7895 {
7896 if (pExitInfo)
7897 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7898 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7899 }
7900
7901 /* CPL. */
7902 if (pVCpu->iem.s.uCpl == 0)
7903 { /* likely */ }
7904 else
7905 {
7906 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7907 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7908 return iemRaiseGeneralProtectionFault0(pVCpu);
7909 }
7910
7911 /* VMCS pointer in root mode. */
7912 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7913 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7914 { /* likely */ }
7915 else
7916 {
7917 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7918 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7919 iemVmxVmFailInvalid(pVCpu);
7920 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7921 return VINF_SUCCESS;
7922 }
7923
7924 /* VMCS-link pointer in non-root mode. */
7925 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7926 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7927 { /* likely */ }
7928 else
7929 {
7930 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7931 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7932 iemVmxVmFailInvalid(pVCpu);
7933 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7934 return VINF_SUCCESS;
7935 }
7936
7937 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7938 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7939 if (!fIsRegOperand)
7940 {
7941 /* Read the value from the specified guest memory location. */
7942 VBOXSTRICTRC rcStrict;
7943 RTGCPTR const GCPtrVal = u64Val;
7944 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7945 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7946 else
7947 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7948 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7949 {
7950 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7952 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7953 return rcStrict;
7954 }
7955 }
7956 else
7957 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7958
7959 /* Supported VMCS field. */
7960 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7961 { /* likely */ }
7962 else
7963 {
7964 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7965 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7966 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7967 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7968 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7969 return VINF_SUCCESS;
7970 }
7971
7972 /* Read-only VMCS field. */
7973 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7974 if ( !fIsFieldReadOnly
7975 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7976 { /* likely */ }
7977 else
7978 {
7979 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7980 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7981 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7982 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7983 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7984 return VINF_SUCCESS;
7985 }
7986
7987 /*
7988 * Write to the current or shadow VMCS.
7989 */
7990 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7991 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7992 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7993 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7994 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7995
7996 /* Notify HM that the VMCS content might have changed. */
7997 if (!fInVmxNonRootMode)
7998 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7999
8000 iemVmxVmSucceed(pVCpu);
8001 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8002 return VINF_SUCCESS;
8003}
8004
8005
8006/**
8007 * VMCLEAR instruction execution worker.
8008 *
8009 * @returns Strict VBox status code.
8010 * @param pVCpu The cross context virtual CPU structure.
8011 * @param cbInstr The instruction length in bytes.
8012 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8013 * @param GCPtrVmcs The linear address of the VMCS pointer.
8014 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8015 *
8016 * @remarks Common VMX instruction checks are already expected to by the caller,
8017 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8018 */
8019IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8020 PCVMXVEXITINFO pExitInfo)
8021{
8022 /* Nested-guest intercept. */
8023 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8024 {
8025 if (pExitInfo)
8026 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8027 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8028 }
8029
8030 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8031
8032 /* CPL. */
8033 if (pVCpu->iem.s.uCpl == 0)
8034 { /* likely */ }
8035 else
8036 {
8037 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8038 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8039 return iemRaiseGeneralProtectionFault0(pVCpu);
8040 }
8041
8042 /* Get the VMCS pointer from the location specified by the source memory operand. */
8043 RTGCPHYS GCPhysVmcs;
8044 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8045 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8046 { /* likely */ }
8047 else
8048 {
8049 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8050 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8051 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8052 return rcStrict;
8053 }
8054
8055 /* VMCS pointer alignment. */
8056 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8057 { /* likely */ }
8058 else
8059 {
8060 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8061 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8062 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8063 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8064 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8065 return VINF_SUCCESS;
8066 }
8067
8068 /* VMCS physical-address width limits. */
8069 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8070 { /* likely */ }
8071 else
8072 {
8073 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8074 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8075 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8076 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8077 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8078 return VINF_SUCCESS;
8079 }
8080
8081 /* VMCS is not the VMXON region. */
8082 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8083 { /* likely */ }
8084 else
8085 {
8086 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8087 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8088 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8089 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8090 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8091 return VINF_SUCCESS;
8092 }
8093
8094 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8095 restriction imposed by our implementation. */
8096 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8097 { /* likely */ }
8098 else
8099 {
8100 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8102 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8103 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8104 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8105 return VINF_SUCCESS;
8106 }
8107
8108 /*
8109 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8110 *
8111 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8112 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8113 * to 'clear'.
8114 */
8115 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8116 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8117 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8118 {
8119 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8120 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8121 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8122 }
8123 else
8124 {
8125 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8126 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8127 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8128 if (RT_FAILURE(rcStrict))
8129 return rcStrict;
8130 }
8131
8132 iemVmxVmSucceed(pVCpu);
8133 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8134 return VINF_SUCCESS;
8135}
8136
8137
8138/**
8139 * VMPTRST instruction execution worker.
8140 *
8141 * @returns Strict VBox status code.
8142 * @param pVCpu The cross context virtual CPU structure.
8143 * @param cbInstr The instruction length in bytes.
8144 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8145 * @param GCPtrVmcs The linear address of where to store the current VMCS
8146 * pointer.
8147 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8148 *
8149 * @remarks Common VMX instruction checks are already expected to by the caller,
8150 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8151 */
8152IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8153 PCVMXVEXITINFO pExitInfo)
8154{
8155 /* Nested-guest intercept. */
8156 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8157 {
8158 if (pExitInfo)
8159 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8160 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8161 }
8162
8163 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8164
8165 /* CPL. */
8166 if (pVCpu->iem.s.uCpl == 0)
8167 { /* likely */ }
8168 else
8169 {
8170 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8171 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8172 return iemRaiseGeneralProtectionFault0(pVCpu);
8173 }
8174
8175 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8176 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8177 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8178 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8179 {
8180 iemVmxVmSucceed(pVCpu);
8181 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8182 return rcStrict;
8183 }
8184
8185 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8186 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8187 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8188 return rcStrict;
8189}
8190
8191
8192/**
8193 * VMPTRLD instruction execution worker.
8194 *
8195 * @returns Strict VBox status code.
8196 * @param pVCpu The cross context virtual CPU structure.
8197 * @param cbInstr The instruction length in bytes.
8198 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8199 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8200 *
8201 * @remarks Common VMX instruction checks are already expected to by the caller,
8202 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8203 */
8204IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8205 PCVMXVEXITINFO pExitInfo)
8206{
8207 /* Nested-guest intercept. */
8208 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8209 {
8210 if (pExitInfo)
8211 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8212 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8213 }
8214
8215 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8216
8217 /* CPL. */
8218 if (pVCpu->iem.s.uCpl == 0)
8219 { /* likely */ }
8220 else
8221 {
8222 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8223 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8224 return iemRaiseGeneralProtectionFault0(pVCpu);
8225 }
8226
8227 /* Get the VMCS pointer from the location specified by the source memory operand. */
8228 RTGCPHYS GCPhysVmcs;
8229 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8230 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8231 { /* likely */ }
8232 else
8233 {
8234 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8235 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8236 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8237 return rcStrict;
8238 }
8239
8240 /* VMCS pointer alignment. */
8241 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8242 { /* likely */ }
8243 else
8244 {
8245 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8246 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8247 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8248 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8249 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8250 return VINF_SUCCESS;
8251 }
8252
8253 /* VMCS physical-address width limits. */
8254 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8255 { /* likely */ }
8256 else
8257 {
8258 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8259 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8260 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8261 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8262 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8263 return VINF_SUCCESS;
8264 }
8265
8266 /* VMCS is not the VMXON region. */
8267 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8268 { /* likely */ }
8269 else
8270 {
8271 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8272 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8273 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8274 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8275 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8276 return VINF_SUCCESS;
8277 }
8278
8279 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8280 restriction imposed by our implementation. */
8281 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8282 { /* likely */ }
8283 else
8284 {
8285 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8286 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8287 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8288 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8290 return VINF_SUCCESS;
8291 }
8292
8293 /* Read just the VMCS revision from the VMCS. */
8294 VMXVMCSREVID VmcsRevId;
8295 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8296 if (RT_SUCCESS(rc))
8297 { /* likely */ }
8298 else
8299 {
8300 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8301 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8302 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8303 return rc;
8304 }
8305
8306 /*
8307 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8308 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8309 */
8310 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8311 && ( !VmcsRevId.n.fIsShadowVmcs
8312 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8313 { /* likely */ }
8314 else
8315 {
8316 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8317 {
8318 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8319 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8320 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8321 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8322 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8323 return VINF_SUCCESS;
8324 }
8325
8326 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8327 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8328 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8329 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8330 return VINF_SUCCESS;
8331 }
8332
8333 /*
8334 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8335 * the cache of an existing, current VMCS back to guest memory before loading a new,
8336 * different current VMCS.
8337 */
8338 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8339 {
8340 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8341 {
8342 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8343 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8344 }
8345
8346 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8347 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8348 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8349 if (RT_SUCCESS(rc))
8350 {
8351 /* Notify HM that a new, current VMCS is loaded. */
8352 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8353 }
8354 else
8355 {
8356 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8357 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8358 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8359 return rc;
8360 }
8361 }
8362
8363 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8364 iemVmxVmSucceed(pVCpu);
8365 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8366 return VINF_SUCCESS;
8367}
8368
8369
8370/**
8371 * INVVPID instruction execution worker.
8372 *
8373 * @returns Strict VBox status code.
8374 * @param pVCpu The cross context virtual CPU structure.
8375 * @param cbInstr The instruction length in bytes.
8376 * @param iEffSeg The segment of the invvpid descriptor.
8377 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8378 * @param u64InvvpidType The invalidation type.
8379 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8380 * NULL.
8381 *
8382 * @remarks Common VMX instruction checks are already expected to by the caller,
8383 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8384 */
8385IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8386 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8387{
8388 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8389 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8390 return iemRaiseUndefinedOpcode(pVCpu);
8391
8392 /* Nested-guest intercept. */
8393 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8394 {
8395 if (pExitInfo)
8396 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8397 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8398 }
8399
8400 /* CPL. */
8401 if (pVCpu->iem.s.uCpl != 0)
8402 {
8403 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8404 return iemRaiseGeneralProtectionFault0(pVCpu);
8405 }
8406
8407 /*
8408 * Validate INVVPID invalidation type.
8409 *
8410 * The instruction specifies exactly ONE of the supported invalidation types.
8411 *
8412 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8413 * supported. In theory, it's possible for a CPU to not support flushing individual
8414 * addresses but all the other types or any other combination. We do not take any
8415 * shortcuts here by assuming the types we currently expose to the guest.
8416 */
8417 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8418 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8419 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8420 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8421 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8422 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8423 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8424 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8425 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8426 { /* likely */ }
8427 else
8428 {
8429 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8431 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8432 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8433 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8434 return VINF_SUCCESS;
8435 }
8436
8437 /*
8438 * Fetch the invvpid descriptor from guest memory.
8439 */
8440 RTUINT128U uDesc;
8441 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8442 if (rcStrict == VINF_SUCCESS)
8443 {
8444 /*
8445 * Validate the descriptor.
8446 */
8447 if (uDesc.s.Lo > 0xfff)
8448 {
8449 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8450 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8451 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8452 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8453 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8454 return VINF_SUCCESS;
8455 }
8456
8457 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8458 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8459 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8460 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8461 switch (u64InvvpidType)
8462 {
8463 case VMXTLBFLUSHVPID_INDIV_ADDR:
8464 {
8465 if (uVpid != 0)
8466 {
8467 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8468 {
8469 /* Invalidate mappings for the linear address tagged with VPID. */
8470 /** @todo PGM support for VPID? Currently just flush everything. */
8471 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8472 iemVmxVmSucceed(pVCpu);
8473 }
8474 else
8475 {
8476 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8478 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8479 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8480 }
8481 }
8482 else
8483 {
8484 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8485 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8486 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8487 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8488 }
8489 break;
8490 }
8491
8492 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8493 {
8494 if (uVpid != 0)
8495 {
8496 /* Invalidate all mappings with VPID. */
8497 /** @todo PGM support for VPID? Currently just flush everything. */
8498 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8499 iemVmxVmSucceed(pVCpu);
8500 }
8501 else
8502 {
8503 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8505 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8506 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8507 }
8508 break;
8509 }
8510
8511 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8512 {
8513 /* Invalidate all mappings with non-zero VPIDs. */
8514 /** @todo PGM support for VPID? Currently just flush everything. */
8515 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8516 iemVmxVmSucceed(pVCpu);
8517 break;
8518 }
8519
8520 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8521 {
8522 if (uVpid != 0)
8523 {
8524 /* Invalidate all mappings with VPID except global translations. */
8525 /** @todo PGM support for VPID? Currently just flush everything. */
8526 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8527 iemVmxVmSucceed(pVCpu);
8528 }
8529 else
8530 {
8531 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8532 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8533 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8534 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8535 }
8536 break;
8537 }
8538 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8539 }
8540 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8541 }
8542 return rcStrict;
8543}
8544
8545
8546/**
8547 * VMXON instruction execution worker.
8548 *
8549 * @returns Strict VBox status code.
8550 * @param pVCpu The cross context virtual CPU structure.
8551 * @param cbInstr The instruction length in bytes.
8552 * @param iEffSeg The effective segment register to use with @a
8553 * GCPtrVmxon.
8554 * @param GCPtrVmxon The linear address of the VMXON pointer.
8555 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8556 *
8557 * @remarks Common VMX instruction checks are already expected to by the caller,
8558 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8559 */
8560IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8561 PCVMXVEXITINFO pExitInfo)
8562{
8563 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8564 {
8565 /* CPL. */
8566 if (pVCpu->iem.s.uCpl == 0)
8567 { /* likely */ }
8568 else
8569 {
8570 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8572 return iemRaiseGeneralProtectionFault0(pVCpu);
8573 }
8574
8575 /* A20M (A20 Masked) mode. */
8576 if (PGMPhysIsA20Enabled(pVCpu))
8577 { /* likely */ }
8578 else
8579 {
8580 Log(("vmxon: A20M mode -> #GP(0)\n"));
8581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8582 return iemRaiseGeneralProtectionFault0(pVCpu);
8583 }
8584
8585 /* CR0. */
8586 {
8587 /* CR0 MB1 bits. */
8588 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8589 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8590 { /* likely */ }
8591 else
8592 {
8593 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8595 return iemRaiseGeneralProtectionFault0(pVCpu);
8596 }
8597
8598 /* CR0 MBZ bits. */
8599 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8600 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8601 { /* likely */ }
8602 else
8603 {
8604 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8605 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8606 return iemRaiseGeneralProtectionFault0(pVCpu);
8607 }
8608 }
8609
8610 /* CR4. */
8611 {
8612 /* CR4 MB1 bits. */
8613 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8614 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8615 { /* likely */ }
8616 else
8617 {
8618 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8619 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8620 return iemRaiseGeneralProtectionFault0(pVCpu);
8621 }
8622
8623 /* CR4 MBZ bits. */
8624 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8625 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8626 { /* likely */ }
8627 else
8628 {
8629 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8630 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8631 return iemRaiseGeneralProtectionFault0(pVCpu);
8632 }
8633 }
8634
8635 /* Feature control MSR's LOCK and VMXON bits. */
8636 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8637 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8638 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8639 { /* likely */ }
8640 else
8641 {
8642 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8644 return iemRaiseGeneralProtectionFault0(pVCpu);
8645 }
8646
8647 /* Get the VMXON pointer from the location specified by the source memory operand. */
8648 RTGCPHYS GCPhysVmxon;
8649 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8650 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8651 { /* likely */ }
8652 else
8653 {
8654 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8655 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8657 return rcStrict;
8658 }
8659
8660 /* VMXON region pointer alignment. */
8661 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8662 { /* likely */ }
8663 else
8664 {
8665 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8666 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8667 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8668 iemVmxVmFailInvalid(pVCpu);
8669 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8670 return VINF_SUCCESS;
8671 }
8672
8673 /* VMXON physical-address width limits. */
8674 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8675 { /* likely */ }
8676 else
8677 {
8678 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8679 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8681 iemVmxVmFailInvalid(pVCpu);
8682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8683 return VINF_SUCCESS;
8684 }
8685
8686 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8687 restriction imposed by our implementation. */
8688 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8689 { /* likely */ }
8690 else
8691 {
8692 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8694 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8695 iemVmxVmFailInvalid(pVCpu);
8696 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8697 return VINF_SUCCESS;
8698 }
8699
8700 /* Read the VMCS revision ID from the VMXON region. */
8701 VMXVMCSREVID VmcsRevId;
8702 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8703 if (RT_SUCCESS(rc))
8704 { /* likely */ }
8705 else
8706 {
8707 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8709 return rc;
8710 }
8711
8712 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8713 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8714 { /* likely */ }
8715 else
8716 {
8717 /* Revision ID mismatch. */
8718 if (!VmcsRevId.n.fIsShadowVmcs)
8719 {
8720 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8721 VmcsRevId.n.u31RevisionId));
8722 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8723 iemVmxVmFailInvalid(pVCpu);
8724 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8725 return VINF_SUCCESS;
8726 }
8727
8728 /* Shadow VMCS disallowed. */
8729 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8730 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8731 iemVmxVmFailInvalid(pVCpu);
8732 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8733 return VINF_SUCCESS;
8734 }
8735
8736 /*
8737 * Record that we're in VMX operation, block INIT, block and disable A20M.
8738 */
8739 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8740 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8741 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8742
8743 /* Clear address-range monitoring. */
8744 EMMonitorWaitClear(pVCpu);
8745 /** @todo NSTVMX: Intel PT. */
8746
8747 iemVmxVmSucceed(pVCpu);
8748 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8749 return VINF_SUCCESS;
8750 }
8751 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8752 {
8753 /* Nested-guest intercept. */
8754 if (pExitInfo)
8755 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8756 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8757 }
8758
8759 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8760
8761 /* CPL. */
8762 if (pVCpu->iem.s.uCpl > 0)
8763 {
8764 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8766 return iemRaiseGeneralProtectionFault0(pVCpu);
8767 }
8768
8769 /* VMXON when already in VMX root mode. */
8770 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8771 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8772 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8773 return VINF_SUCCESS;
8774}
8775
8776
8777/**
8778 * Implements 'VMXOFF'.
8779 *
8780 * @remarks Common VMX instruction checks are already expected to by the caller,
8781 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8782 */
8783IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8784{
8785 /* Nested-guest intercept. */
8786 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8787 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8788
8789 /* CPL. */
8790 if (pVCpu->iem.s.uCpl == 0)
8791 { /* likely */ }
8792 else
8793 {
8794 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8795 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8796 return iemRaiseGeneralProtectionFault0(pVCpu);
8797 }
8798
8799 /* Dual monitor treatment of SMIs and SMM. */
8800 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8801 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8802 { /* likely */ }
8803 else
8804 {
8805 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8806 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8807 return VINF_SUCCESS;
8808 }
8809
8810 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8811 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8812 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8813
8814 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8815 { /** @todo NSTVMX: Unblock SMI. */ }
8816
8817 EMMonitorWaitClear(pVCpu);
8818 /** @todo NSTVMX: Unblock and enable A20M. */
8819
8820 iemVmxVmSucceed(pVCpu);
8821 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8822 return VINF_SUCCESS;
8823}
8824
8825
8826/**
8827 * Implements 'VMXON'.
8828 */
8829IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8830{
8831 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8832}
8833
8834
8835/**
8836 * Implements 'VMLAUNCH'.
8837 */
8838IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8839{
8840 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8841}
8842
8843
8844/**
8845 * Implements 'VMRESUME'.
8846 */
8847IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8848{
8849 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8850}
8851
8852
8853/**
8854 * Implements 'VMPTRLD'.
8855 */
8856IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8857{
8858 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8859}
8860
8861
8862/**
8863 * Implements 'VMPTRST'.
8864 */
8865IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8866{
8867 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8868}
8869
8870
8871/**
8872 * Implements 'VMCLEAR'.
8873 */
8874IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8875{
8876 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8877}
8878
8879
8880/**
8881 * Implements 'VMWRITE' register.
8882 */
8883IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8884{
8885 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8886}
8887
8888
8889/**
8890 * Implements 'VMWRITE' memory.
8891 */
8892IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8893{
8894 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8895}
8896
8897
8898/**
8899 * Implements 'VMREAD' register (64-bit).
8900 */
8901IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8902{
8903 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8904}
8905
8906
8907/**
8908 * Implements 'VMREAD' register (32-bit).
8909 */
8910IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8911{
8912 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8913}
8914
8915
8916/**
8917 * Implements 'VMREAD' memory, 64-bit register.
8918 */
8919IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8920{
8921 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8922}
8923
8924
8925/**
8926 * Implements 'VMREAD' memory, 32-bit register.
8927 */
8928IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8929{
8930 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8931}
8932
8933
8934/**
8935 * Implements 'INVVPID'.
8936 */
8937IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8938{
8939 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8940}
8941
8942
8943/**
8944 * Implements VMX's implementation of PAUSE.
8945 */
8946IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8947{
8948 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8949 {
8950 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8951 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8952 return rcStrict;
8953 }
8954
8955 /*
8956 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8957 * a VM-exit, the instruction operates normally.
8958 */
8959 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8960 return VINF_SUCCESS;
8961}
8962
8963#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8964
8965
8966/**
8967 * Implements 'VMCALL'.
8968 */
8969IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8970{
8971#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8972 /* Nested-guest intercept. */
8973 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8974 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8975#endif
8976
8977 /* Join forces with vmmcall. */
8978 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8979}
8980
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette