VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 74073

Last change on this file since 74073 was 74073, checked in by vboxsync, 6 years ago

VMM/IEM, HM: Nested VMX: bugref:9180 vmlaunch/vmresume bits.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 116.5 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp.h 74073 2018-09-04 18:05:14Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/**
20 * Implements 'VMCALL'.
21 */
22IEM_CIMPL_DEF_0(iemCImpl_vmcall)
23{
24 /** @todo NSTVMX: intercept. */
25
26 /* Join forces with vmmcall. */
27 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
28}
29
30#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
31/**
32 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
33 *
34 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
35 * second dimension is the Index, see VMXVMCSFIELDENC.
36 */
37uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
38{
39 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
40 {
41 /* 0 */ RT_OFFSETOF(VMXVVMCS, u16Vpid),
42 /* 1 */ RT_OFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
43 /* 2 */ RT_OFFSETOF(VMXVVMCS, u16EptpIndex),
44 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
45 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
46 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
47 },
48 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
49 {
50 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
51 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
52 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
53 /* 24-25 */ UINT16_MAX, UINT16_MAX
54 },
55 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
56 {
57 /* 0 */ RT_OFFSETOF(VMXVVMCS, GuestEs),
58 /* 1 */ RT_OFFSETOF(VMXVVMCS, GuestCs),
59 /* 2 */ RT_OFFSETOF(VMXVVMCS, GuestSs),
60 /* 3 */ RT_OFFSETOF(VMXVVMCS, GuestDs),
61 /* 4 */ RT_OFFSETOF(VMXVVMCS, GuestFs),
62 /* 5 */ RT_OFFSETOF(VMXVVMCS, GuestGs),
63 /* 6 */ RT_OFFSETOF(VMXVVMCS, GuestLdtr),
64 /* 7 */ RT_OFFSETOF(VMXVVMCS, GuestTr),
65 /* 8 */ RT_OFFSETOF(VMXVVMCS, u16GuestIntStatus),
66 /* 9 */ RT_OFFSETOF(VMXVVMCS, u16PmlIndex),
67 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
68 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
69 },
70 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
71 {
72 /* 0 */ RT_OFFSETOF(VMXVVMCS, HostEs),
73 /* 1 */ RT_OFFSETOF(VMXVVMCS, HostCs),
74 /* 2 */ RT_OFFSETOF(VMXVVMCS, HostSs),
75 /* 3 */ RT_OFFSETOF(VMXVVMCS, HostDs),
76 /* 4 */ RT_OFFSETOF(VMXVVMCS, HostFs),
77 /* 5 */ RT_OFFSETOF(VMXVVMCS, HostGs),
78 /* 6 */ RT_OFFSETOF(VMXVVMCS, HostTr),
79 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
80 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
81 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
82 },
83 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
84 {
85 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
86 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
87 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
88 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
89 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
90 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
91 /* 6 */ RT_OFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
92 /* 7 */ RT_OFFSETOF(VMXVVMCS, u64AddrPml),
93 /* 8 */ RT_OFFSETOF(VMXVVMCS, u64TscOffset),
94 /* 9 */ RT_OFFSETOF(VMXVVMCS, u64AddrVirtApic),
95 /* 10 */ RT_OFFSETOF(VMXVVMCS, u64AddrApicAccess),
96 /* 11 */ RT_OFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
97 /* 12 */ RT_OFFSETOF(VMXVVMCS, u64VmFuncCtls),
98 /* 13 */ RT_OFFSETOF(VMXVVMCS, u64EptpPtr),
99 /* 14 */ RT_OFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
100 /* 15 */ RT_OFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
101 /* 16 */ RT_OFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
102 /* 17 */ RT_OFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
103 /* 18 */ RT_OFFSETOF(VMXVVMCS, u64AddrEptpList),
104 /* 19 */ RT_OFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
105 /* 20 */ RT_OFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
106 /* 21 */ RT_OFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
107 /* 22 */ RT_OFFSETOF(VMXVVMCS, u64AddrXssBitmap),
108 /* 23 */ RT_OFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
109 /* 24 */ UINT16_MAX,
110 /* 25 */ RT_OFFSETOF(VMXVVMCS, u64TscMultiplier)
111 },
112 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
113 {
114 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64GuestPhysAddr),
115 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
116 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
117 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
118 /* 25 */ UINT16_MAX
119 },
120 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
121 {
122 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
123 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
124 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64GuestPatMsr),
125 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64GuestEferMsr),
126 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
127 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64GuestPdpte0),
128 /* 6 */ RT_OFFSETOF(VMXVVMCS, u64GuestPdpte1),
129 /* 7 */ RT_OFFSETOF(VMXVVMCS, u64GuestPdpte2),
130 /* 8 */ RT_OFFSETOF(VMXVVMCS, u64GuestPdpte3),
131 /* 9 */ RT_OFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
132 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
133 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
134 },
135 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
136 {
137 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64HostPatMsr),
138 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64HostEferMsr),
139 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
140 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
141 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
142 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
143 },
144 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
145 {
146 /* 0 */ RT_OFFSETOF(VMXVVMCS, u32PinCtls),
147 /* 1 */ RT_OFFSETOF(VMXVVMCS, u32ProcCtls),
148 /* 2 */ RT_OFFSETOF(VMXVVMCS, u32XcptBitmap),
149 /* 3 */ RT_OFFSETOF(VMXVVMCS, u32XcptPFMask),
150 /* 4 */ RT_OFFSETOF(VMXVVMCS, u32XcptPFMatch),
151 /* 5 */ RT_OFFSETOF(VMXVVMCS, u32Cr3TargetCount),
152 /* 6 */ RT_OFFSETOF(VMXVVMCS, u32ExitCtls),
153 /* 7 */ RT_OFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
154 /* 8 */ RT_OFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
155 /* 9 */ RT_OFFSETOF(VMXVVMCS, u32EntryCtls),
156 /* 10 */ RT_OFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
157 /* 11 */ RT_OFFSETOF(VMXVVMCS, u32EntryIntInfo),
158 /* 12 */ RT_OFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
159 /* 13 */ RT_OFFSETOF(VMXVVMCS, u32EntryInstrLen),
160 /* 14 */ RT_OFFSETOF(VMXVVMCS, u32TprThreshold),
161 /* 15 */ RT_OFFSETOF(VMXVVMCS, u32ProcCtls2),
162 /* 16 */ RT_OFFSETOF(VMXVVMCS, u32PleGap),
163 /* 17 */ RT_OFFSETOF(VMXVVMCS, u32PleWindow),
164 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
165 },
166 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
167 {
168 /* 0 */ RT_OFFSETOF(VMXVVMCS, u32RoVmInstrError),
169 /* 1 */ RT_OFFSETOF(VMXVVMCS, u32RoExitReason),
170 /* 2 */ RT_OFFSETOF(VMXVVMCS, u32RoExitIntInfo),
171 /* 3 */ RT_OFFSETOF(VMXVVMCS, u32RoExitErrCode),
172 /* 4 */ RT_OFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
173 /* 5 */ RT_OFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
174 /* 6 */ RT_OFFSETOF(VMXVVMCS, u32RoExitInstrLen),
175 /* 7 */ RT_OFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
176 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
177 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
178 /* 24-25 */ UINT16_MAX, UINT16_MAX
179 },
180 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
181 {
182 /* 0 */ RT_OFFSETOF(VMXVVMCS, u32GuestEsLimit),
183 /* 1 */ RT_OFFSETOF(VMXVVMCS, u32GuestCsLimit),
184 /* 2 */ RT_OFFSETOF(VMXVVMCS, u32GuestSsLimit),
185 /* 3 */ RT_OFFSETOF(VMXVVMCS, u32GuestDsLimit),
186 /* 4 */ RT_OFFSETOF(VMXVVMCS, u32GuestEsLimit),
187 /* 5 */ RT_OFFSETOF(VMXVVMCS, u32GuestFsLimit),
188 /* 6 */ RT_OFFSETOF(VMXVVMCS, u32GuestGsLimit),
189 /* 7 */ RT_OFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
190 /* 8 */ RT_OFFSETOF(VMXVVMCS, u32GuestTrLimit),
191 /* 9 */ RT_OFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
192 /* 10 */ RT_OFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
193 /* 11 */ RT_OFFSETOF(VMXVVMCS, u32GuestEsAttr),
194 /* 12 */ RT_OFFSETOF(VMXVVMCS, u32GuestCsAttr),
195 /* 13 */ RT_OFFSETOF(VMXVVMCS, u32GuestSsAttr),
196 /* 14 */ RT_OFFSETOF(VMXVVMCS, u32GuestDsAttr),
197 /* 15 */ RT_OFFSETOF(VMXVVMCS, u32GuestFsAttr),
198 /* 16 */ RT_OFFSETOF(VMXVVMCS, u32GuestGsAttr),
199 /* 17 */ RT_OFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
200 /* 18 */ RT_OFFSETOF(VMXVVMCS, u32GuestTrAttr),
201 /* 19 */ RT_OFFSETOF(VMXVVMCS, u32GuestIntrState),
202 /* 20 */ RT_OFFSETOF(VMXVVMCS, u32GuestActivityState),
203 /* 21 */ RT_OFFSETOF(VMXVVMCS, u32GuestSmBase),
204 /* 22 */ RT_OFFSETOF(VMXVVMCS, u32GuestSysenterCS),
205 /* 23 */ RT_OFFSETOF(VMXVVMCS, u32PreemptTimer),
206 /* 24-25 */ UINT16_MAX, UINT16_MAX
207 },
208 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
209 {
210 /* 0 */ RT_OFFSETOF(VMXVVMCS, u32HostSysenterCs),
211 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
212 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
213 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
214 /* 25 */ UINT16_MAX
215 },
216 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
217 {
218 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64Cr0Mask),
219 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64Cr4Mask),
220 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
221 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
222 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64Cr3Target0),
223 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64Cr3Target1),
224 /* 6 */ RT_OFFSETOF(VMXVVMCS, u64Cr3Target2),
225 /* 7 */ RT_OFFSETOF(VMXVVMCS, u64Cr3Target3),
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-25 */ UINT16_MAX, UINT16_MAX
229 },
230 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
231 {
232 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64ExitQual),
233 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64IoRcx),
234 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64IoRsi),
235 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64IoRdi),
236 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64IoRip),
237 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64GuestLinearAddr),
238 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
241 },
242 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
243 {
244 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64GuestCr0),
245 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64GuestCr3),
246 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64GuestCr4),
247 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64GuestEsBase),
248 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64GuestCsBase),
249 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64GuestSsBase),
250 /* 6 */ RT_OFFSETOF(VMXVVMCS, u64GuestDsBase),
251 /* 7 */ RT_OFFSETOF(VMXVVMCS, u64GuestFsBase),
252 /* 8 */ RT_OFFSETOF(VMXVVMCS, u64GuestGsBase),
253 /* 9 */ RT_OFFSETOF(VMXVVMCS, u64GuestLdtrBase),
254 /* 10 */ RT_OFFSETOF(VMXVVMCS, u64GuestTrBase),
255 /* 11 */ RT_OFFSETOF(VMXVVMCS, u64GuestGdtrBase),
256 /* 12 */ RT_OFFSETOF(VMXVVMCS, u64GuestIdtrBase),
257 /* 13 */ RT_OFFSETOF(VMXVVMCS, u64GuestDr7),
258 /* 14 */ RT_OFFSETOF(VMXVVMCS, u64GuestRsp),
259 /* 15 */ RT_OFFSETOF(VMXVVMCS, u64GuestRip),
260 /* 16 */ RT_OFFSETOF(VMXVVMCS, u64GuestRFlags),
261 /* 17 */ RT_OFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
262 /* 18 */ RT_OFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
263 /* 19 */ RT_OFFSETOF(VMXVVMCS, u64GuestSysenterEip),
264 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
265 },
266 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
267 {
268 /* 0 */ RT_OFFSETOF(VMXVVMCS, u64HostCr0),
269 /* 1 */ RT_OFFSETOF(VMXVVMCS, u64HostCr3),
270 /* 2 */ RT_OFFSETOF(VMXVVMCS, u64HostCr4),
271 /* 3 */ RT_OFFSETOF(VMXVVMCS, u64HostFsBase),
272 /* 4 */ RT_OFFSETOF(VMXVVMCS, u64HostGsBase),
273 /* 5 */ RT_OFFSETOF(VMXVVMCS, u64HostTrBase),
274 /* 6 */ RT_OFFSETOF(VMXVVMCS, u64HostGdtrBase),
275 /* 7 */ RT_OFFSETOF(VMXVVMCS, u64HostIdtrBase),
276 /* 8 */ RT_OFFSETOF(VMXVVMCS, u64HostSysenterEsp),
277 /* 9 */ RT_OFFSETOF(VMXVVMCS, u64HostSysenterEip),
278 /* 10 */ RT_OFFSETOF(VMXVVMCS, u64HostRsp),
279 /* 11 */ RT_OFFSETOF(VMXVVMCS, u64HostRip),
280 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
281 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
282 }
283};
284
285
286/**
287 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
288 * relative offsets.
289 */
290# ifdef IEM_WITH_CODE_TLB
291# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
292# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
293# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
294# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
295# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
296# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
297# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
298# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
299# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
300# else /* !IEM_WITH_CODE_TLB */
301# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
302 do \
303 { \
304 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
305 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
306 } while (0)
307
308# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
309
310# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
311 do \
312 { \
313 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
314 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
315 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
316 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
317 } while (0)
318
319# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
320 do \
321 { \
322 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
323 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
324 } while (0)
325
326# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
327 do \
328 { \
329 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
330 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
331 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
332 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
333 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
334 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
335 } while (0)
336
337# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
338 do \
339 { \
340 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
341 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
342 } while (0)
343
344# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
345 do \
346 { \
347 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
348 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
349 } while (0)
350
351# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
352 do \
353 { \
354 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
355 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
356 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
357 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
358 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
359 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
360 } while (0)
361# endif /* !IEM_WITH_CODE_TLB */
362
363/** Whether a shadow VMCS is present for the given VCPU. */
364#define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
365
366/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
367#define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u64VmcsLinkPtr.u)
368
369/** Whether a current VMCS is present for the given VCPU. */
370#define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
371
372/** Gets the guest-physical address of the current VMCS for the given VCPU. */
373#define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
374
375/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
376#define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
377 do \
378 { \
379 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
380 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
381 } while (0)
382
383/** Clears any current VMCS for the given VCPU. */
384#define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
385 do \
386 { \
387 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
388 } while (0)
389
390/** Check the common VMX instruction preconditions.
391 * @note Any changes here, also check if IEMOP_HLP_VMX_INSTR needs updating.
392 */
393#define IEM_VMX_INSTR_CHECKS(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
394 do { \
395 if ( !IEM_IS_REAL_OR_V86_MODE(a_pVCpu) \
396 && ( !IEM_IS_LONG_MODE(a_pVCpu) \
397 || IEM_IS_64BIT_CODE(a_pVCpu))) \
398 { /* likely */ } \
399 else \
400 { \
401 if (IEM_IS_REAL_OR_V86_MODE(a_pVCpu)) \
402 { \
403 Log((a_szInstr ": Real or v8086 mode -> #UD\n")); \
404 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = a_InsDiagPrefix##_RealOrV86Mode; \
405 return iemRaiseUndefinedOpcode(a_pVCpu); \
406 } \
407 if (IEM_IS_LONG_MODE(a_pVCpu) && !IEM_IS_64BIT_CODE(a_pVCpu)) \
408 { \
409 Log((a_szInstr ": Long mode without 64-bit code segment -> #UD\n")); \
410 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = a_InsDiagPrefix##_LongModeCS; \
411 return iemRaiseUndefinedOpcode(a_pVCpu); \
412 } \
413 } \
414 } while (0)
415
416/** Check for VMX instructions requiring to be in VMX operation.
417 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs udpating. */
418#define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
419 do \
420 { \
421 if (IEM_IS_VMX_ROOT_MODE(a_pVCpu)) \
422 { /* likely */ } \
423 else \
424 { \
425 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
426 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = a_InsDiagPrefix##_VmxRoot; \
427 return iemRaiseUndefinedOpcode(a_pVCpu); \
428 } \
429 } while (0)
430
431
432/**
433 * Returns whether the given VMCS field is valid and supported by our emulation.
434 *
435 * @param pVCpu The cross context virtual CPU structure.
436 * @param u64FieldEnc The VMCS field encoding.
437 *
438 * @remarks This takes into account the CPU features exposed to the guest.
439 */
440IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
441{
442 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
443 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
444 if (!uFieldEncHi)
445 { /* likely */ }
446 else
447 return false;
448
449 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
450 switch (uFieldEncLo)
451 {
452 /*
453 * 16-bit fields.
454 */
455 /* Control fields. */
456 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
457 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
458 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
459
460 /* Guest-state fields. */
461 case VMX_VMCS16_GUEST_ES_SEL:
462 case VMX_VMCS16_GUEST_CS_SEL:
463 case VMX_VMCS16_GUEST_SS_SEL:
464 case VMX_VMCS16_GUEST_DS_SEL:
465 case VMX_VMCS16_GUEST_FS_SEL:
466 case VMX_VMCS16_GUEST_GS_SEL:
467 case VMX_VMCS16_GUEST_LDTR_SEL:
468 case VMX_VMCS16_GUEST_TR_SEL:
469 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
470 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
471
472 /* Host-state fields. */
473 case VMX_VMCS16_HOST_ES_SEL:
474 case VMX_VMCS16_HOST_CS_SEL:
475 case VMX_VMCS16_HOST_SS_SEL:
476 case VMX_VMCS16_HOST_DS_SEL:
477 case VMX_VMCS16_HOST_FS_SEL:
478 case VMX_VMCS16_HOST_GS_SEL:
479 case VMX_VMCS16_HOST_TR_SEL: return true;
480
481 /*
482 * 64-bit fields.
483 */
484 /* Control fields. */
485 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
486 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
487 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
488 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
489 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
490 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
491 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
492 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
493 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
494 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
495 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
496 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
497 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
498 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
499 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
500 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
501 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
502 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
503 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
504 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
505 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
506 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
507 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
508 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
509 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
510 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
511 case VMX_VMCS64_CTRL_EPTP_FULL:
512 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
513 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
514 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
515 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
516 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
517 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
518 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
519 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
520 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
521 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
522 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
523 {
524 uint64_t const uVmFuncMsr = CPUMGetGuestIa32VmxVmFunc(pVCpu);
525 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
526 }
527 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
528 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
529 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
530 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
531 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
532 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
533 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
534 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
535 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
536 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
537 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
538 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
539
540 /* Read-only data fields. */
541 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
542 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
543
544 /* Guest-state fields. */
545 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
546 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
547 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
548 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
549 case VMX_VMCS64_GUEST_PAT_FULL:
550 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
551 case VMX_VMCS64_GUEST_EFER_FULL:
552 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
553 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
554 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
555 case VMX_VMCS64_GUEST_PDPTE0_FULL:
556 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
557 case VMX_VMCS64_GUEST_PDPTE1_FULL:
558 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
559 case VMX_VMCS64_GUEST_PDPTE2_FULL:
560 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
561 case VMX_VMCS64_GUEST_PDPTE3_FULL:
562 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
563 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
564 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
565
566 /* Host-state fields. */
567 case VMX_VMCS64_HOST_PAT_FULL:
568 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
569 case VMX_VMCS64_HOST_EFER_FULL:
570 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
571 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
572 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
573
574 /*
575 * 32-bit fields.
576 */
577 /* Control fields. */
578 case VMX_VMCS32_CTRL_PIN_EXEC:
579 case VMX_VMCS32_CTRL_PROC_EXEC:
580 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
581 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
582 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
583 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
584 case VMX_VMCS32_CTRL_EXIT:
585 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
586 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
587 case VMX_VMCS32_CTRL_ENTRY:
588 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
589 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
590 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
591 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
592 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
593 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
594 case VMX_VMCS32_CTRL_PLE_GAP:
595 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
596
597 /* Read-only data fields. */
598 case VMX_VMCS32_RO_VM_INSTR_ERROR:
599 case VMX_VMCS32_RO_EXIT_REASON:
600 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
601 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
602 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
603 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
604 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
605 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
606
607 /* Guest-state fields. */
608 case VMX_VMCS32_GUEST_ES_LIMIT:
609 case VMX_VMCS32_GUEST_CS_LIMIT:
610 case VMX_VMCS32_GUEST_SS_LIMIT:
611 case VMX_VMCS32_GUEST_DS_LIMIT:
612 case VMX_VMCS32_GUEST_FS_LIMIT:
613 case VMX_VMCS32_GUEST_GS_LIMIT:
614 case VMX_VMCS32_GUEST_LDTR_LIMIT:
615 case VMX_VMCS32_GUEST_TR_LIMIT:
616 case VMX_VMCS32_GUEST_GDTR_LIMIT:
617 case VMX_VMCS32_GUEST_IDTR_LIMIT:
618 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
619 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
620 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
621 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
622 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
623 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
624 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
625 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
626 case VMX_VMCS32_GUEST_INT_STATE:
627 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
628 case VMX_VMCS32_GUEST_SMBASE:
629 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
630 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
631
632 /* Host-state fields. */
633 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
634
635 /*
636 * Natural-width fields.
637 */
638 /* Control fields. */
639 case VMX_VMCS_CTRL_CR0_MASK:
640 case VMX_VMCS_CTRL_CR4_MASK:
641 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
642 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
643 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
644 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
645 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
646 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
647
648 /* Read-only data fields. */
649 case VMX_VMCS_RO_EXIT_QUALIFICATION:
650 case VMX_VMCS_RO_IO_RCX:
651 case VMX_VMCS_RO_IO_RSX:
652 case VMX_VMCS_RO_IO_RDI:
653 case VMX_VMCS_RO_IO_RIP:
654 case VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR: return true;
655
656 /* Guest-state fields. */
657 case VMX_VMCS_GUEST_CR0:
658 case VMX_VMCS_GUEST_CR3:
659 case VMX_VMCS_GUEST_CR4:
660 case VMX_VMCS_GUEST_ES_BASE:
661 case VMX_VMCS_GUEST_CS_BASE:
662 case VMX_VMCS_GUEST_SS_BASE:
663 case VMX_VMCS_GUEST_DS_BASE:
664 case VMX_VMCS_GUEST_FS_BASE:
665 case VMX_VMCS_GUEST_GS_BASE:
666 case VMX_VMCS_GUEST_LDTR_BASE:
667 case VMX_VMCS_GUEST_TR_BASE:
668 case VMX_VMCS_GUEST_GDTR_BASE:
669 case VMX_VMCS_GUEST_IDTR_BASE:
670 case VMX_VMCS_GUEST_DR7:
671 case VMX_VMCS_GUEST_RSP:
672 case VMX_VMCS_GUEST_RIP:
673 case VMX_VMCS_GUEST_RFLAGS:
674 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
675 case VMX_VMCS_GUEST_SYSENTER_ESP:
676 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
677
678 /* Host-state fields. */
679 case VMX_VMCS_HOST_CR0:
680 case VMX_VMCS_HOST_CR3:
681 case VMX_VMCS_HOST_CR4:
682 case VMX_VMCS_HOST_FS_BASE:
683 case VMX_VMCS_HOST_GS_BASE:
684 case VMX_VMCS_HOST_TR_BASE:
685 case VMX_VMCS_HOST_GDTR_BASE:
686 case VMX_VMCS_HOST_IDTR_BASE:
687 case VMX_VMCS_HOST_SYSENTER_ESP:
688 case VMX_VMCS_HOST_SYSENTER_EIP:
689 case VMX_VMCS_HOST_RSP:
690 case VMX_VMCS_HOST_RIP: return true;
691 }
692
693 return false;
694}
695
696
697/**
698 * Gets VM-exit instruction information along with any displacement for an
699 * instruction VM-exit.
700 *
701 * @returns The VM-exit instruction information.
702 * @param pVCpu The cross context virtual CPU structure.
703 * @param uExitReason The VM-exit reason.
704 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX) if
705 * any. Pass VMXINSTRID_NONE otherwise.
706 * @param fPrimaryOpRead If the primary operand of the ModR/M byte (bits 0:3) is
707 * a read or write.
708 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
709 * NULL.
710 */
711IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, bool fPrimaryOpRead,
712 PRTGCPTR pGCPtrDisp)
713{
714 RTGCPTR GCPtrDisp;
715 VMXEXITINSTRINFO ExitInstrInfo;
716 ExitInstrInfo.u = 0;
717
718 /*
719 * Get and parse the ModR/M byte from our decoded opcodes.
720 */
721 uint8_t bRm;
722 uint8_t const offModRm = pVCpu->iem.s.offModRm;
723 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
724 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
725 {
726 /*
727 * ModR/M indicates register addressing.
728 *
729 * The primary/secondary register operands are reported in the iReg1 or iReg2
730 * fields depending on whether it is a read/write form.
731 */
732 uint8_t idxReg1;
733 uint8_t idxReg2;
734 if (fPrimaryOpRead)
735 {
736 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
737 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
738 }
739 else
740 {
741 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
742 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
743 }
744 ExitInstrInfo.All.u2Scaling = 0;
745 ExitInstrInfo.All.iReg1 = idxReg1;
746 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
747 ExitInstrInfo.All.fIsRegOperand = 1;
748 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
749 ExitInstrInfo.All.iSegReg = 0;
750 ExitInstrInfo.All.iIdxReg = 0;
751 ExitInstrInfo.All.fIdxRegInvalid = 1;
752 ExitInstrInfo.All.iBaseReg = 0;
753 ExitInstrInfo.All.fBaseRegInvalid = 1;
754 ExitInstrInfo.All.iReg2 = idxReg2;
755
756 /* Displacement not applicable for register addressing. */
757 GCPtrDisp = 0;
758 }
759 else
760 {
761 /*
762 * ModR/M indicates memory addressing.
763 */
764 uint8_t uScale = 0;
765 bool fBaseRegValid = false;
766 bool fIdxRegValid = false;
767 uint8_t iBaseReg = 0;
768 uint8_t iIdxReg = 0;
769 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
770 {
771 /*
772 * Parse the ModR/M, displacement for 16-bit addressing mode.
773 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
774 */
775 uint16_t u16Disp = 0;
776 uint8_t const offDisp = offModRm + sizeof(bRm);
777 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
778 {
779 /* Displacement without any registers. */
780 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
781 }
782 else
783 {
784 /* Register (index and base). */
785 switch (bRm & X86_MODRM_RM_MASK)
786 {
787 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
788 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
789 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
790 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
791 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
792 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
793 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
794 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
795 }
796
797 /* Register + displacement. */
798 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
799 {
800 case 0: break;
801 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
802 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
803 default:
804 {
805 /* Register addressing, handled at the beginning. */
806 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
807 break;
808 }
809 }
810 }
811
812 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
813 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
814 }
815 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
816 {
817 /*
818 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
819 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
820 */
821 uint32_t u32Disp = 0;
822 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
823 {
824 /* Displacement without any registers. */
825 uint8_t const offDisp = offModRm + sizeof(bRm);
826 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
827 }
828 else
829 {
830 /* Register (and perhaps scale, index and base). */
831 uint8_t offDisp = offModRm + sizeof(bRm);
832 iBaseReg = (bRm & X86_MODRM_RM_MASK);
833 if (iBaseReg == 4)
834 {
835 /* An SIB byte follows the ModR/M byte, parse it. */
836 uint8_t bSib;
837 uint8_t const offSib = offModRm + sizeof(bRm);
838 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
839
840 /* A displacement may follow SIB, update its offset. */
841 offDisp += sizeof(bSib);
842
843 /* Get the scale. */
844 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
845
846 /* Get the index register. */
847 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
848 fIdxRegValid = RT_BOOL(iIdxReg != 4);
849
850 /* Get the base register. */
851 iBaseReg = bSib & X86_SIB_BASE_MASK;
852 fBaseRegValid = true;
853 if (iBaseReg == 5)
854 {
855 if ((bRm & X86_MODRM_MOD_MASK) == 0)
856 {
857 /* Mod is 0 implies a 32-bit displacement with no base. */
858 fBaseRegValid = false;
859 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
860 }
861 else
862 {
863 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
864 iBaseReg = X86_GREG_xBP;
865 }
866 }
867 }
868
869 /* Register + displacement. */
870 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
871 {
872 case 0: /* Handled above */ break;
873 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
874 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
875 default:
876 {
877 /* Register addressing, handled at the beginning. */
878 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
879 break;
880 }
881 }
882 }
883
884 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
885 }
886 else
887 {
888 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
889
890 /*
891 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
892 * See Intel instruction spec. 2.2 "IA-32e Mode".
893 */
894 uint64_t u64Disp = 0;
895 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
896 if (fRipRelativeAddr)
897 {
898 /*
899 * RIP-relative addressing mode.
900 *
901 * The displacment is 32-bit signed implying an offset range of +/-2G.
902 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
903 */
904 uint8_t const offDisp = offModRm + sizeof(bRm);
905 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
906 }
907 else
908 {
909 uint8_t offDisp = offModRm + sizeof(bRm);
910
911 /*
912 * Register (and perhaps scale, index and base).
913 *
914 * REX.B extends the most-significant bit of the base register. However, REX.B
915 * is ignored while determining whether an SIB follows the opcode. Hence, we
916 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
917 *
918 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
919 */
920 iBaseReg = (bRm & X86_MODRM_RM_MASK);
921 if (iBaseReg == 4)
922 {
923 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
924 uint8_t bSib;
925 uint8_t const offSib = offModRm + sizeof(bRm);
926 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
927
928 /* Displacement may follow SIB, update its offset. */
929 offDisp += sizeof(bSib);
930
931 /* Get the scale. */
932 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
933
934 /* Get the index. */
935 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
936 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
937
938 /* Get the base. */
939 iBaseReg = (bSib & X86_SIB_BASE_MASK);
940 fBaseRegValid = true;
941 if (iBaseReg == 5)
942 {
943 if ((bRm & X86_MODRM_MOD_MASK) == 0)
944 {
945 /* Mod is 0 implies a signed 32-bit displacement with no base. */
946 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
947 }
948 else
949 {
950 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
951 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
952 }
953 }
954 }
955 iBaseReg |= pVCpu->iem.s.uRexB;
956
957 /* Register + displacement. */
958 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
959 {
960 case 0: /* Handled above */ break;
961 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
962 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
963 default:
964 {
965 /* Register addressing, handled at the beginning. */
966 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
967 break;
968 }
969 }
970 }
971
972 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
973 }
974
975 /*
976 * The primary or secondary register operand is reported in iReg2 depending
977 * on whether the primary operand is in read/write form.
978 */
979 uint8_t idxReg2;
980 if (fPrimaryOpRead)
981 {
982 idxReg2 = bRm & X86_MODRM_RM_MASK;
983 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
984 idxReg2 |= pVCpu->iem.s.uRexB;
985 }
986 else
987 {
988 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
989 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
990 idxReg2 |= pVCpu->iem.s.uRexReg;
991 }
992 ExitInstrInfo.All.u2Scaling = uScale;
993 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
994 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
995 ExitInstrInfo.All.fIsRegOperand = 0;
996 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
997 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
998 ExitInstrInfo.All.iIdxReg = iIdxReg;
999 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
1000 ExitInstrInfo.All.iBaseReg = iBaseReg;
1001 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
1002 ExitInstrInfo.All.iReg2 = idxReg2;
1003 }
1004
1005 /*
1006 * Handle exceptions for certain instructions.
1007 * (e.g. some instructions convey an instruction identity).
1008 */
1009 switch (uExitReason)
1010 {
1011 case VMX_EXIT_GDTR_IDTR_ACCESS:
1012 {
1013 Assert(VMXINSTRID_IS_VALID(uInstrId));
1014 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1015 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
1016 break;
1017 }
1018
1019 case VMX_EXIT_LDTR_TR_ACCESS:
1020 {
1021 Assert(VMXINSTRID_IS_VALID(uInstrId));
1022 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1023 ExitInstrInfo.LdtTr.u2Undef0 = 0;
1024 break;
1025 }
1026
1027 case VMX_EXIT_RDRAND:
1028 case VMX_EXIT_RDSEED:
1029 {
1030 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
1031 break;
1032 }
1033 }
1034
1035 /* Update displacement and return the constructed VM-exit instruction information field. */
1036 if (pGCPtrDisp)
1037 *pGCPtrDisp = GCPtrDisp;
1038 return ExitInstrInfo.u;
1039}
1040
1041
1042/**
1043 * Implements VMSucceed for VMX instruction success.
1044 *
1045 * @param pVCpu The cross context virtual CPU structure.
1046 */
1047DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1048{
1049 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1050}
1051
1052
1053/**
1054 * Implements VMFailInvalid for VMX instruction failure.
1055 *
1056 * @param pVCpu The cross context virtual CPU structure.
1057 */
1058DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1059{
1060 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1061 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1062}
1063
1064
1065/**
1066 * Implements VMFailValid for VMX instruction failure.
1067 *
1068 * @param pVCpu The cross context virtual CPU structure.
1069 * @param enmInsErr The VM instruction error.
1070 */
1071DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1072{
1073 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1074 {
1075 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1076 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1077 /** @todo NSTVMX: VMWrite enmInsErr to VM-instruction error field. */
1078 RT_NOREF(enmInsErr);
1079 }
1080}
1081
1082
1083/**
1084 * Implements VMFail for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 * @param enmInsErr The VM instruction error.
1088 */
1089DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1090{
1091 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1092 {
1093 iemVmxVmFailValid(pVCpu, enmInsErr);
1094 /** @todo Set VM-instruction error field in the current virtual-VMCS. */
1095 }
1096 else
1097 iemVmxVmFailInvalid(pVCpu);
1098}
1099
1100
1101/**
1102 * Flushes the current VMCS contents back to guest memory.
1103 *
1104 * @returns VBox status code.
1105 * @param pVCpu The cross context virtual CPU structure.
1106 */
1107DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1108{
1109 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1110 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1111 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1112 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1113 return rc;
1114}
1115
1116
1117/**
1118 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1119 *
1120 * @param pVCpu The cross context virtual CPU structure.
1121 */
1122DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1123{
1124 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_Success;
1125 iemVmxVmSucceed(pVCpu);
1126 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1127}
1128
1129
1130/**
1131 * VMREAD common (memory/register) instruction execution worker
1132 *
1133 * @param pVCpu The cross context virtual CPU structure.
1134 * @param cbInstr The instruction length.
1135 * @param pu64Dst Where to write the VMCS value (only updated when
1136 * VINF_SUCCESS is returned).
1137 * @param u64FieldEnc The VMCS field encoding.
1138 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1139 * be NULL.
1140 */
1141IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
1142 PCVMXVEXITINFO pExitInfo)
1143{
1144 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1145 {
1146 RT_NOREF(pExitInfo); RT_NOREF(cbInstr);
1147 /** @todo NSTVMX: intercept. */
1148 /** @todo NSTVMX: VMCS shadowing intercept (VMREAD bitmap). */
1149 }
1150
1151 /* CPL. */
1152 if (pVCpu->iem.s.uCpl > 0)
1153 {
1154 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1155 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_Cpl;
1156 return iemRaiseGeneralProtectionFault0(pVCpu);
1157 }
1158
1159 /* VMCS pointer in root mode. */
1160 if ( IEM_IS_VMX_ROOT_MODE(pVCpu)
1161 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1162 {
1163 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
1164 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_PtrInvalid;
1165 iemVmxVmFailInvalid(pVCpu);
1166 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1167 return VINF_SUCCESS;
1168 }
1169
1170 /* VMCS-link pointer in non-root mode. */
1171 if ( IEM_IS_VMX_NON_ROOT_MODE(pVCpu)
1172 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
1173 {
1174 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
1175 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_LinkPtrInvalid;
1176 iemVmxVmFailInvalid(pVCpu);
1177 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1178 return VINF_SUCCESS;
1179 }
1180
1181 /* Supported VMCS field. */
1182 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
1183 {
1184 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
1185 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_FieldInvalid;
1186 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
1187 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1188 return VINF_SUCCESS;
1189 }
1190
1191 /*
1192 * Setup reading from the current or shadow VMCS.
1193 */
1194 uint8_t *pbVmcs;
1195 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1196 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
1197 else
1198 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1199 Assert(pbVmcs);
1200
1201 VMXVMCSFIELDENC FieldEnc;
1202 FieldEnc.u = RT_LO_U32(u64FieldEnc);
1203 uint8_t const uWidth = FieldEnc.n.u2Width;
1204 uint8_t const uType = FieldEnc.n.u2Type;
1205 uint8_t const uWidthType = (uWidth << 2) | uType;
1206 uint8_t const uIndex = FieldEnc.n.u8Index;
1207 AssertRCReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
1208 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
1209
1210 /*
1211 * Read the VMCS component based on the field's effective width.
1212 *
1213 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
1214 * indicates high bits (little endian).
1215 *
1216 * Note! The caller is responsible to trim the result and update registers
1217 * or memory locations are required. Here we just zero-extend to the largest
1218 * type (i.e. 64-bits).
1219 */
1220 uint8_t *pbField = pbVmcs + offField;
1221 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
1222 switch (uEffWidth)
1223 {
1224 case VMX_VMCS_ENC_WIDTH_64BIT:
1225 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
1226 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
1227 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
1228 }
1229 return VINF_SUCCESS;
1230}
1231
1232
1233/**
1234 * VMREAD (64-bit register) instruction execution worker.
1235 *
1236 * @param pVCpu The cross context virtual CPU structure.
1237 * @param cbInstr The instruction length.
1238 * @param pu64Dst Where to store the VMCS field's value.
1239 * @param u64FieldEnc The VMCS field encoding.
1240 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1241 * be NULL.
1242 */
1243IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
1244 PCVMXVEXITINFO pExitInfo)
1245{
1246 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
1247 if (rcStrict == VINF_SUCCESS)
1248 {
1249 iemVmxVmreadSuccess(pVCpu, cbInstr);
1250 return VINF_SUCCESS;
1251 }
1252
1253 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1254 return rcStrict;
1255}
1256
1257
1258/**
1259 * VMREAD (32-bit register) instruction execution worker.
1260 *
1261 * @param pVCpu The cross context virtual CPU structure.
1262 * @param cbInstr The instruction length.
1263 * @param pu32Dst Where to store the VMCS field's value.
1264 * @param u32FieldEnc The VMCS field encoding.
1265 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1266 * be NULL.
1267 */
1268IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
1269 PCVMXVEXITINFO pExitInfo)
1270{
1271 uint64_t u64Dst;
1272 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
1273 if (rcStrict == VINF_SUCCESS)
1274 {
1275 *pu32Dst = u64Dst;
1276 iemVmxVmreadSuccess(pVCpu, cbInstr);
1277 return VINF_SUCCESS;
1278 }
1279
1280 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1281 return rcStrict;
1282}
1283
1284
1285/**
1286 * VMREAD (memory) instruction execution worker.
1287 *
1288 * @param pVCpu The cross context virtual CPU structure.
1289 * @param cbInstr The instruction length.
1290 * @param iEffSeg The effective segment register to use with @a u64Val.
1291 * Pass UINT8_MAX if it is a register access.
1292 * @param enmEffAddrMode The effective addressing mode (only used with memory
1293 * operand).
1294 * @param GCPtrDst The guest linear address to store the VMCS field's
1295 * value.
1296 * @param u64FieldEnc The VMCS field encoding.
1297 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1298 * be NULL.
1299 */
1300IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
1301 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
1302{
1303 uint64_t u64Dst;
1304 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
1305 if (rcStrict == VINF_SUCCESS)
1306 {
1307 /*
1308 * Write the VMCS field's value to the location specified in guest-memory.
1309 *
1310 * The pointer size depends on the address size (address-size prefix allowed).
1311 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
1312 */
1313 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
1314 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
1315 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
1316
1317 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1318 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
1319 else
1320 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
1321 if (rcStrict == VINF_SUCCESS)
1322 {
1323 iemVmxVmreadSuccess(pVCpu, cbInstr);
1324 return VINF_SUCCESS;
1325 }
1326
1327 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
1328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmread_PtrMap;
1329 return rcStrict;
1330 }
1331
1332 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1333 return rcStrict;
1334}
1335
1336
1337/**
1338 * VMWRITE instruction execution worker.
1339 *
1340 * @param pVCpu The cross context virtual CPU structure.
1341 * @param cbInstr The instruction length.
1342 * @param iEffSeg The effective segment register to use with @a u64Val.
1343 * Pass UINT8_MAX if it is a register access.
1344 * @param enmEffAddrMode The effective addressing mode (only used with memory
1345 * operand).
1346 * @param u64Val The value to write (or guest linear address to the
1347 * value), @a iEffSeg will indicate if it's a memory
1348 * operand.
1349 * @param u64FieldEnc The VMCS field encoding.
1350 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1351 * be NULL.
1352 */
1353IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
1354 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
1355{
1356 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1357 {
1358 RT_NOREF(pExitInfo);
1359 /** @todo NSTVMX: intercept. */
1360 /** @todo NSTVMX: VMCS shadowing intercept (VMWRITE bitmap). */
1361 }
1362
1363 /* CPL. */
1364 if (pVCpu->iem.s.uCpl > 0)
1365 {
1366 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_Cpl;
1368 return iemRaiseGeneralProtectionFault0(pVCpu);
1369 }
1370
1371 /* VMCS pointer in root mode. */
1372 if ( IEM_IS_VMX_ROOT_MODE(pVCpu)
1373 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1374 {
1375 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
1376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_PtrInvalid;
1377 iemVmxVmFailInvalid(pVCpu);
1378 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1379 return VINF_SUCCESS;
1380 }
1381
1382 /* VMCS-link pointer in non-root mode. */
1383 if ( IEM_IS_VMX_NON_ROOT_MODE(pVCpu)
1384 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
1385 {
1386 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
1387 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_LinkPtrInvalid;
1388 iemVmxVmFailInvalid(pVCpu);
1389 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1390 return VINF_SUCCESS;
1391 }
1392
1393 /* If the VMWRITE instruction references memory, access the specified memory operand. */
1394 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
1395 if (!fIsRegOperand)
1396 {
1397 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
1398 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
1399 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
1400
1401 /* Read the value from the specified guest memory location. */
1402 VBOXSTRICTRC rcStrict;
1403 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1404 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
1405 else
1406 {
1407 uint32_t u32Val;
1408 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
1409 u64Val = u32Val;
1410 }
1411 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1412 {
1413 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
1414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_PtrMap;
1415 return rcStrict;
1416 }
1417 }
1418 else
1419 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
1420
1421 /* Supported VMCS field. */
1422 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
1423 {
1424 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
1425 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_FieldInvalid;
1426 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
1427 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1428 return VINF_SUCCESS;
1429 }
1430
1431 /* Read-only VMCS field. */
1432 bool const fReadOnlyField = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
1433 if ( fReadOnlyField
1434 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
1435 {
1436 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
1437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_FieldRo;
1438 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
1439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1440 return VINF_SUCCESS;
1441 }
1442
1443 /*
1444 * Setup writing to the current or shadow VMCS.
1445 */
1446 uint8_t *pbVmcs;
1447 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1448 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
1449 else
1450 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1451 Assert(pbVmcs);
1452
1453 VMXVMCSFIELDENC FieldEnc;
1454 FieldEnc.u = RT_LO_U32(u64FieldEnc);
1455 uint8_t const uWidth = FieldEnc.n.u2Width;
1456 uint8_t const uType = FieldEnc.n.u2Type;
1457 uint8_t const uWidthType = (uWidth << 2) | uType;
1458 uint8_t const uIndex = FieldEnc.n.u8Index;
1459 AssertRCReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
1460 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
1461
1462 /*
1463 * Write the VMCS component based on the field's effective width.
1464 *
1465 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
1466 * indicates high bits (little endian).
1467 */
1468 uint8_t *pbField = pbVmcs + offField;
1469 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
1470 switch (uEffWidth)
1471 {
1472 case VMX_VMCS_ENC_WIDTH_64BIT:
1473 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
1474 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
1475 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
1476 }
1477
1478 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmwrite_Success;
1479 iemVmxVmSucceed(pVCpu);
1480 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1481 return VINF_SUCCESS;
1482}
1483
1484
1485/**
1486 * VMCLEAR instruction execution worker.
1487 *
1488 * @param pVCpu The cross context virtual CPU structure.
1489 * @param cbInstr The instruction length.
1490 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
1491 * @param GCPtrVmcs The linear address of the VMCS pointer.
1492 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1493 * be NULL.
1494 *
1495 * @remarks Common VMX instruction checks are already expected to by the caller,
1496 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
1497 */
1498IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
1499 PCVMXVEXITINFO pExitInfo)
1500{
1501 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1502 {
1503 RT_NOREF(pExitInfo);
1504 /** @todo NSTVMX: intercept. */
1505 }
1506 Assert(IEM_IS_VMX_ROOT_MODE(pVCpu));
1507
1508 /* CPL. */
1509 if (pVCpu->iem.s.uCpl > 0)
1510 {
1511 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1512 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_Cpl;
1513 return iemRaiseGeneralProtectionFault0(pVCpu);
1514 }
1515
1516 /* Get the VMCS pointer from the location specified by the source memory operand. */
1517 RTGCPHYS GCPhysVmcs;
1518 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
1519 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1520 {
1521 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
1522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_PtrMap;
1523 return rcStrict;
1524 }
1525
1526 /* VMCS pointer alignment. */
1527 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
1528 {
1529 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
1530 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_PtrAlign;
1531 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
1532 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1533 return VINF_SUCCESS;
1534 }
1535
1536 /* VMCS physical-address width limits. */
1537 Assert(!VMX_V_VMCS_PHYSADDR_4G_LIMIT);
1538 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
1539 {
1540 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
1541 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_PtrWidth;
1542 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
1543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1544 return VINF_SUCCESS;
1545 }
1546
1547 /* VMCS is not the VMXON region. */
1548 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
1549 {
1550 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_PtrVmxon;
1552 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
1553 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1554 return VINF_SUCCESS;
1555 }
1556
1557 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
1558 restriction imposed by our implementation. */
1559 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
1560 {
1561 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
1562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_PtrAbnormal;
1563 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
1564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1565 return VINF_SUCCESS;
1566 }
1567
1568 /*
1569 * VMCLEAR allows committing and clearing any valid VMCS pointer.
1570 *
1571 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
1572 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
1573 * to 'clear'.
1574 */
1575 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
1576 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
1577 {
1578 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
1579 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
1580 iemVmxCommitCurrentVmcsToMemory(pVCpu);
1581 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1582 }
1583 else
1584 {
1585 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPtrVmcs + RT_OFFSETOF(VMXVVMCS, fVmcsState),
1586 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
1587 }
1588
1589 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmclear_Success;
1590 iemVmxVmSucceed(pVCpu);
1591 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1592 return rcStrict;
1593}
1594
1595
1596/**
1597 * VMPTRST instruction execution worker.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 * @param cbInstr The instruction length.
1601 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
1602 * @param GCPtrVmcs The linear address of where to store the current VMCS
1603 * pointer.
1604 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1605 * be NULL.
1606 *
1607 * @remarks Common VMX instruction checks are already expected to by the caller,
1608 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
1609 */
1610IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
1611 PCVMXVEXITINFO pExitInfo)
1612{
1613 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1614 {
1615 RT_NOREF(pExitInfo);
1616 /** @todo NSTVMX: intercept. */
1617 }
1618 Assert(IEM_IS_VMX_ROOT_MODE(pVCpu));
1619
1620 /* CPL. */
1621 if (pVCpu->iem.s.uCpl > 0)
1622 {
1623 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1624 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrst_Cpl;
1625 return iemRaiseGeneralProtectionFault0(pVCpu);
1626 }
1627
1628 /* Set the VMCS pointer to the location specified by the destination memory operand. */
1629 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
1630 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
1631 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
1632 {
1633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrst_Success;
1634 iemVmxVmSucceed(pVCpu);
1635 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1636 return rcStrict;
1637 }
1638
1639 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1640 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrst_PtrMap;
1641 return rcStrict;
1642}
1643
1644
1645/**
1646 * VMPTRLD instruction execution worker.
1647 *
1648 * @param pVCpu The cross context virtual CPU structure.
1649 * @param cbInstr The instruction length.
1650 * @param GCPtrVmcs The linear address of the current VMCS pointer.
1651 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
1652 * be NULL.
1653 *
1654 * @remarks Common VMX instruction checks are already expected to by the caller,
1655 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
1656 */
1657IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
1658 PCVMXVEXITINFO pExitInfo)
1659{
1660 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1661 {
1662 RT_NOREF(pExitInfo);
1663 /** @todo NSTVMX: intercept. */
1664 }
1665 Assert(IEM_IS_VMX_ROOT_MODE(pVCpu));
1666
1667 /* CPL. */
1668 if (pVCpu->iem.s.uCpl > 0)
1669 {
1670 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1671 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_Cpl;
1672 return iemRaiseGeneralProtectionFault0(pVCpu);
1673 }
1674
1675 /* Get the VMCS pointer from the location specified by the source memory operand. */
1676 RTGCPHYS GCPhysVmcs;
1677 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
1678 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1679 {
1680 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrMap;
1682 return rcStrict;
1683 }
1684
1685 /* VMCS pointer alignment. */
1686 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
1687 {
1688 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
1689 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrAlign;
1690 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
1691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1692 return VINF_SUCCESS;
1693 }
1694
1695 /* VMCS physical-address width limits. */
1696 Assert(!VMX_V_VMCS_PHYSADDR_4G_LIMIT);
1697 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
1698 {
1699 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
1700 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrWidth;
1701 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
1702 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1703 return VINF_SUCCESS;
1704 }
1705
1706 /* VMCS is not the VMXON region. */
1707 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
1708 {
1709 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
1710 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrVmxon;
1711 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
1712 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1713 return VINF_SUCCESS;
1714 }
1715
1716 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
1717 restriction imposed by our implementation. */
1718 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
1719 {
1720 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
1721 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrAbnormal;
1722 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
1723 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1724 return VINF_SUCCESS;
1725 }
1726
1727 /* Read the VMCS revision ID from the VMCS. */
1728 VMXVMCSREVID VmcsRevId;
1729 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
1730 if (RT_FAILURE(rc))
1731 {
1732 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
1733 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_PtrReadPhys;
1734 return rc;
1735 }
1736
1737 /* Verify the VMCS revision specified by the guest matches what we reported to the guest,
1738 also check VMCS shadowing feature. */
1739 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
1740 || ( VmcsRevId.n.fIsShadowVmcs
1741 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
1742 {
1743 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
1744 {
1745 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFail()\n", VMX_V_VMCS_REVISION_ID,
1746 VmcsRevId.n.u31RevisionId));
1747 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_VmcsRevId;
1748 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
1749 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1750 return VINF_SUCCESS;
1751 }
1752
1753 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
1754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_ShadowVmcs;
1755 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
1756 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1757 return VINF_SUCCESS;
1758 }
1759
1760 /*
1761 * We only maintain only the current VMCS in our virtual CPU context (CPUMCTX). Therefore,
1762 * VMPTRLD shall always flush any existing current VMCS back to guest memory before loading
1763 * a new VMCS as current.
1764 */
1765 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
1766 {
1767 iemVmxCommitCurrentVmcsToMemory(pVCpu);
1768 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
1769 }
1770 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmptrld_Success;
1771 iemVmxVmSucceed(pVCpu);
1772 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1773 return VINF_SUCCESS;
1774}
1775
1776
1777/**
1778 * VMXON instruction execution worker.
1779 *
1780 * @param pVCpu The cross context virtual CPU structure.
1781 * @param cbInstr The instruction length.
1782 * @param iEffSeg The effective segment register to use with @a
1783 * GCPtrVmxon.
1784 * @param GCPtrVmxon The linear address of the VMXON pointer.
1785 * @param pExitInfo Pointer to the VM-exit instruction information struct.
1786 * Optional, can be NULL.
1787 *
1788 * @remarks Common VMX instruction checks are already expected to by the caller,
1789 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
1790 */
1791IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
1792 PCVMXVEXITINFO pExitInfo)
1793{
1794#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1795 RT_NOREF5(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
1796 return VINF_EM_RAW_EMULATE_INSTR;
1797#else
1798 if (!IEM_IS_VMX_ROOT_MODE(pVCpu))
1799 {
1800 /* CPL. */
1801 if (pVCpu->iem.s.uCpl > 0)
1802 {
1803 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_Cpl;
1805 return iemRaiseGeneralProtectionFault0(pVCpu);
1806 }
1807
1808 /* A20M (A20 Masked) mode. */
1809 if (!PGMPhysIsA20Enabled(pVCpu))
1810 {
1811 Log(("vmxon: A20M mode -> #GP(0)\n"));
1812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_A20M;
1813 return iemRaiseGeneralProtectionFault0(pVCpu);
1814 }
1815
1816 /* CR0 fixed bits. */
1817 bool const fUnrestrictedGuest = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxUnrestrictedGuest;
1818 uint64_t const uCr0Fixed0 = fUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1819 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
1820 {
1821 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
1822 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_Cr0Fixed0;
1823 return iemRaiseGeneralProtectionFault0(pVCpu);
1824 }
1825
1826 /* CR4 fixed bits. */
1827 if ((pVCpu->cpum.GstCtx.cr4 & VMX_V_CR4_FIXED0) != VMX_V_CR4_FIXED0)
1828 {
1829 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
1830 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_Cr4Fixed0;
1831 return iemRaiseGeneralProtectionFault0(pVCpu);
1832 }
1833
1834 /* Feature control MSR's LOCK and VMXON bits. */
1835 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatureControl(pVCpu);
1836 if (!(uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON)))
1837 {
1838 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
1839 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_MsrFeatCtl;
1840 return iemRaiseGeneralProtectionFault0(pVCpu);
1841 }
1842
1843 /* Get the VMXON pointer from the location specified by the source memory operand. */
1844 RTGCPHYS GCPhysVmxon;
1845 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
1846 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1847 {
1848 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
1849 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_PtrMap;
1850 return rcStrict;
1851 }
1852
1853 /* VMXON region pointer alignment. */
1854 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
1855 {
1856 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
1857 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_PtrAlign;
1858 iemVmxVmFailInvalid(pVCpu);
1859 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1860 return VINF_SUCCESS;
1861 }
1862
1863 /* VMXON physical-address width limits. */
1864 Assert(!VMX_V_VMCS_PHYSADDR_4G_LIMIT);
1865 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
1866 {
1867 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
1868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_PtrWidth;
1869 iemVmxVmFailInvalid(pVCpu);
1870 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1871 return VINF_SUCCESS;
1872 }
1873
1874 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
1875 restriction imposed by our implementation. */
1876 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
1877 {
1878 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
1879 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_PtrAbnormal;
1880 iemVmxVmFailInvalid(pVCpu);
1881 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1882 return VINF_SUCCESS;
1883 }
1884
1885 /* Read the VMCS revision ID from the VMXON region. */
1886 VMXVMCSREVID VmcsRevId;
1887 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
1888 if (RT_FAILURE(rc))
1889 {
1890 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
1891 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_PtrReadPhys;
1892 return rc;
1893 }
1894
1895 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
1896 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
1897 {
1898 /* Revision ID mismatch. */
1899 if (!VmcsRevId.n.fIsShadowVmcs)
1900 {
1901 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
1902 VmcsRevId.n.u31RevisionId));
1903 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_VmcsRevId;
1904 iemVmxVmFailInvalid(pVCpu);
1905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1906 return VINF_SUCCESS;
1907 }
1908
1909 /* Shadow VMCS disallowed. */
1910 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_ShadowVmcs;
1912 iemVmxVmFailInvalid(pVCpu);
1913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1914 return VINF_SUCCESS;
1915 }
1916
1917 /*
1918 * Record that we're in VMX operation, block INIT, block and disable A20M.
1919 */
1920 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
1921 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1922 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
1923 /** @todo NSTVMX: clear address-range monitoring. */
1924 /** @todo NSTVMX: Intel PT. */
1925 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_Success;
1926 iemVmxVmSucceed(pVCpu);
1927 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1928# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1929 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1930# else
1931 return VINF_SUCCESS;
1932# endif
1933 }
1934 else if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
1935 {
1936 RT_NOREF(pExitInfo);
1937 /** @todo NSTVMX: intercept. */
1938 }
1939
1940 Assert(IEM_IS_VMX_ROOT_MODE(pVCpu));
1941
1942 /* CPL. */
1943 if (pVCpu->iem.s.uCpl > 0)
1944 {
1945 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
1946 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_VmxRootCpl;
1947 return iemRaiseGeneralProtectionFault0(pVCpu);
1948 }
1949
1950 /* VMXON when already in VMX root mode. */
1951 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
1952 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxon_VmxAlreadyRoot;
1953 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1954 return VINF_SUCCESS;
1955#endif
1956}
1957
1958
1959/**
1960 * Checks VM-entry controls fields as part of VM-entry.
1961 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
1962 *
1963 * @returns VBox status code.
1964 * @param pVCpu The cross context virtual CPU structure.
1965 * @param pszInstr The VMX instruction name (for logging purposes).
1966 */
1967IEM_STATIC VBOXSTRICTRC iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
1968{
1969 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1970
1971 /* VM-entry controls. */
1972 VMXCTLSMSR EntryCtls;
1973 EntryCtls.u = CPUMGetGuestIa32VmxEntryCtls(pVCpu);
1974 if (~pVmcs->u32EntryCtls & EntryCtls.n.disallowed0)
1975 {
1976 Log(("%s: Invalid EntryCtls %#RX32 (disallowed0) -> VMFail\n", pszInstr, pVmcs->u32EntryCtls));
1977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryCtlsDisallowed0;
1978 return VERR_VMX_VMENTRY_FAILED;
1979 }
1980 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
1981 {
1982 Log(("%s: Invalid EntryCtls %#RX32 (allowed1) -> VMFail\n", pszInstr, pVmcs->u32EntryCtls));
1983 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryCtlsAllowed1;
1984 return VERR_VMX_VMENTRY_FAILED;
1985 }
1986
1987 /* Event injection. */
1988 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
1989 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
1990 {
1991 /* Type and vector. */
1992 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
1993 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
1994 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
1995 if ( uRsvd == 0
1996 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
1997 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
1998 { /* likely */ }
1999 else
2000 {
2001 Log(("%s: VM-entry interruption info (%#RX32) invalid (rsvd/type/vector) -> VMFail\n", pszInstr, uIntInfo));
2002 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryIntInfoTypeVecRsvd;
2003 return VERR_VMX_VMENTRY_FAILED;
2004 }
2005
2006 /* Error code. */
2007 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
2008 {
2009 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
2010 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
2011 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
2012 { /* likely */ }
2013 else
2014 {
2015 Log(("%s: VM-entry interruption (%#RX32) invalid error-code (paging-mode) -> VMFail\n", pszInstr, uIntInfo));
2016 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryIntInfoErrCodePe;
2017 return VERR_VMX_VMENTRY_FAILED;
2018 }
2019
2020 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
2021 && ( uVector == X86_XCPT_DF
2022 || uVector == X86_XCPT_TS
2023 || uVector == X86_XCPT_NP
2024 || uVector == X86_XCPT_SS
2025 || uVector == X86_XCPT_GP
2026 || uVector == X86_XCPT_PF
2027 || uVector == X86_XCPT_AC))
2028 { /* likely */ }
2029 else
2030 {
2031 Log(("%s: VM-entry interruption (%#RX32) invalid error-code (vector) -> VMFail\n", pszInstr, uIntInfo));
2032 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryIntInfoErrCodeVec;
2033 return VERR_VMX_VMENTRY_FAILED;
2034 }
2035
2036 /* Exception error-code reserved bits. */
2037 if (pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK)
2038 {
2039 Log(("%s: VM-entry exception error-code (%#RX32) invalid -> VMFail\n", pszInstr, uIntInfo));
2040 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryXcptErrCodeRsvd;
2041 return VERR_VMX_VMENTRY_FAILED;
2042 }
2043
2044 /* Injecting a software interrupt, software exception or privileged software exception. */
2045 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
2046 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
2047 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
2048 {
2049 /* Instruction length must be in the range 0-15. */
2050 if (pVmcs->u32EntryInstrLen > VMX_ENTRY_INSTR_LEN_MAX)
2051 {
2052 Log(("%s: VM-entry instruction length (%#RX32) invalid -> VMFail\n", pszInstr, pVmcs->u32EntryInstrLen));
2053 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryInstrLen;
2054 return VERR_VMX_VMENTRY_FAILED;
2055 }
2056
2057 /* Zero instruction length is only allowed when the CPU supports it explicitly. */
2058 if ( pVmcs->u32EntryInstrLen == 0
2059 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
2060 {
2061 Log(("%s: VM-entry instruction length zero invalid (swint/xcpt/priv) -> VMFail\n", pszInstr));
2062 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_EntryInstrLenZero;
2063 return VERR_VMX_VMENTRY_FAILED;
2064 }
2065 }
2066 }
2067 }
2068
2069 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
2070 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
2071 if (pVmcs->u32EntryMsrLoadCount)
2072 {
2073 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
2074 || (pVmcs->u64AddrEntryMsrLoad.u >> cMaxPhysAddrWidth)
2075 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
2076 {
2077 Log(("%s: VM-entry MSR-load area address %#RX64 invalid -> VMFail\n", pszInstr, pVmcs->u64AddrEntryMsrLoad.u));
2078 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrEntryMsrLoad;
2079 return VERR_VMX_VMENTRY_FAILED;
2080 }
2081 }
2082
2083 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
2084 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
2085
2086 NOREF(pszInstr);
2087 return VINF_SUCCESS;
2088}
2089
2090
2091/**
2092 * Checks VM-exit controls fields as part of VM-entry.
2093 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
2094 *
2095 * @returns VBox status code.
2096 * @param pVCpu The cross context virtual CPU structure.
2097 * @param pszInstr The VMX instruction name (for logging purposes).
2098 */
2099IEM_STATIC VBOXSTRICTRC iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
2100{
2101 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2102
2103 /* VM-exit controls. */
2104 VMXCTLSMSR ExitCtls;
2105 ExitCtls.u = CPUMGetGuestIa32VmxExitCtls(pVCpu);
2106 if (~pVmcs->u32ExitCtls & ExitCtls.n.disallowed0)
2107 {
2108 Log(("%s: Invalid ExitCtls %#RX32 (disallowed0) -> VMFail\n", pszInstr, pVmcs->u32ExitCtls));
2109 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ExitCtlsDisallowed0;
2110 return VERR_VMX_VMENTRY_FAILED;
2111 }
2112 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
2113 {
2114 Log(("%s: Invalid ExitCtls %#RX32 (allowed1) -> VMFail\n", pszInstr, pVmcs->u32ExitCtls));
2115 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ExitCtlsAllowed1;
2116 return VERR_VMX_VMENTRY_FAILED;
2117 }
2118
2119 /* Save preemption timer without activating it. */
2120 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2121 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
2122 {
2123 Log(("%s: Save Preempt-Timer without activate Preempt timer -> VMFail\n", pszInstr, pVmcs->u32ExitCtls));
2124 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_SavePreemptTimer;
2125 return VERR_VMX_VMENTRY_FAILED;
2126 }
2127
2128 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
2129 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
2130 if (pVmcs->u32ExitMsrStoreCount)
2131 {
2132 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
2133 || (pVmcs->u64AddrExitMsrStore.u >> cMaxPhysAddrWidth)
2134 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
2135 {
2136 Log(("%s: VM-exit MSR-store area address %#RX64 invalid -> VMFail\n", pszInstr, pVmcs->u64AddrExitMsrStore.u));
2137 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrExitMsrStore;
2138 return VERR_VMX_VMENTRY_FAILED;
2139 }
2140 }
2141
2142 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
2143 if (pVmcs->u32ExitMsrLoadCount)
2144 {
2145 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
2146 || (pVmcs->u64AddrExitMsrLoad.u >> cMaxPhysAddrWidth)
2147 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
2148 {
2149 Log(("%s: VM-exit MSR-store area address %#RX64 invalid -> VMFail\n", pszInstr, pVmcs->u64AddrExitMsrLoad.u));
2150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrExitMsrLoad;
2151 return VERR_VMX_VMENTRY_FAILED;
2152 }
2153 }
2154
2155 NOREF(pszInstr);
2156 return VINF_SUCCESS;
2157}
2158
2159
2160/**
2161 * Checks VM-execution controls fields as part of VM-entry.
2162 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
2163 *
2164 * @returns VBox status code.
2165 * @param pVCpu The cross context virtual CPU structure.
2166 * @param pszInstr The VMX instruction name (for logging purposes).
2167 */
2168IEM_STATIC VBOXSTRICTRC iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
2169{
2170 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2171 /* Pin-based VM-execution controls. */
2172 {
2173 VMXCTLSMSR PinCtls;
2174 PinCtls.u = CPUMGetGuestIa32VmxPinbasedCtls(pVCpu);
2175 if (~pVmcs->u32PinCtls & PinCtls.n.disallowed0)
2176 {
2177 Log(("%s: Invalid PinCtls %#RX32 (disallowed0) -> VMFail\n", pszInstr, pVmcs->u32PinCtls));
2178 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_PinCtlsDisallowed0;
2179 return VERR_VMX_VMENTRY_FAILED;
2180 }
2181 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
2182 {
2183 Log(("%s: Invalid PinCtls %#RX32 (allowed1) -> VMFail\n", pszInstr, pVmcs->u32PinCtls));
2184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_PinCtlsAllowed1;
2185 return VERR_VMX_VMENTRY_FAILED;
2186 }
2187 }
2188
2189 /* Processor-based VM-execution controls. */
2190 {
2191 VMXCTLSMSR ProcCtls;
2192 ProcCtls.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
2193 if (~pVmcs->u32ProcCtls & ProcCtls.n.disallowed0)
2194 {
2195 Log(("%s: Invalid ProcCtls %#RX32 (disallowed0) -> VMFail\n", pszInstr, pVmcs->u32ProcCtls));
2196 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ProcCtlsDisallowed0;
2197 return VERR_VMX_VMENTRY_FAILED;
2198 }
2199 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
2200 {
2201 Log(("%s: Invalid ProcCtls %#RX32 (allowed1) -> VMFail\n", pszInstr, pVmcs->u32ProcCtls));
2202 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ProcCtlsAllowed1;
2203 return VERR_VMX_VMENTRY_FAILED;
2204 }
2205 }
2206
2207 /* Secondary processor-based VM-execution controls. */
2208 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2209 {
2210 VMXCTLSMSR ProcCtls2;
2211 ProcCtls2.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
2212 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.disallowed0)
2213 {
2214 Log(("%s: Invalid ProcCtls2 %#RX32 (disallowed0) -> VMFail\n", pszInstr, pVmcs->u32ProcCtls2));
2215 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ProcCtls2Disallowed0;
2216 return VERR_VMX_VMENTRY_FAILED;
2217 }
2218 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
2219 {
2220 Log(("%s: Invalid ProcCtls2 %#RX32 (allowed1) -> VMFail\n", pszInstr, pVmcs->u32ProcCtls2));
2221 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ProcCtls2Allowed1;
2222 return VERR_VMX_VMENTRY_FAILED;
2223 }
2224 }
2225 else
2226 pVmcs->u32ProcCtls2 = 0;
2227
2228 /* CR3-target count. */
2229 if (pVmcs->u32Cr3TargetCount > VMX_V_CR3_TARGET_COUNT)
2230 {
2231 Log(("%s: CR3-target count exceeded %#x -> VMFail\n", pszInstr, pVmcs->u32Cr3TargetCount));
2232 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_Cr3TargetCount;
2233 return VERR_VMX_VMENTRY_FAILED;
2234 }
2235
2236 /* IO bitmaps physical addresses. */
2237 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
2238 Assert(!VMX_V_VMCS_PHYSADDR_4G_LIMIT);
2239 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
2240 {
2241 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
2242 || (pVmcs->u64AddrIoBitmapA.u >> cMaxPhysAddrWidth)
2243 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
2244 {
2245 Log(("%s: I/O Bitmap A physaddr invalid %#RX64 -> VMFail\n", pszInstr, pVmcs->u64AddrIoBitmapA.u));
2246 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrIoBitmapA;
2247 return VERR_VMX_VMENTRY_FAILED;
2248 }
2249
2250 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
2251 || (pVmcs->u64AddrIoBitmapB.u >> cMaxPhysAddrWidth)
2252 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
2253 {
2254 Log(("%s: I/O Bitmap B physaddr invalid %#RX64 -> VMFail\n", pszInstr, pVmcs->u64AddrIoBitmapB.u));
2255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrIoBitmapB;
2256 return VERR_VMX_VMENTRY_FAILED;
2257 }
2258 }
2259
2260 /* MSR bitmap physical address. */
2261 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2262 {
2263 if ( (pVmcs->u64AddrMsrBitmap.u & X86_PAGE_4K_OFFSET_MASK)
2264 || (pVmcs->u64AddrMsrBitmap.u >> cMaxPhysAddrWidth)
2265 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrMsrBitmap.u))
2266 {
2267 Log(("%s: MSR Bitmap physaddr invalid %#RX64 -> VMFail\n", pszInstr, pVmcs->u64AddrMsrBitmap.u));
2268 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrMsrBitmap;
2269 return VERR_VMX_VMENTRY_FAILED;
2270 }
2271 }
2272
2273 /* TPR shadow related controls. */
2274 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
2275 {
2276 /* Virtual-APIC page physical address. */
2277 RTGCPHYS GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
2278 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
2279 || (GCPhysVirtApic >> cMaxPhysAddrWidth)
2280 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
2281 {
2282 Log(("%s: Virtual-APIC page physaddr invalid %#RX64 -> VMFail\n", pszInstr, GCPhysVirtApic));
2283 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrVirtApicPage;
2284 return VERR_VMX_VMENTRY_FAILED;
2285 }
2286
2287 /* Read the Virtual-APIC page. */
2288 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
2289 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
2290 if (RT_FAILURE(rc))
2291 {
2292 Log(("%s: Failed to read Virtual-APIC page at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVirtApic, rc));
2293 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtApicPagePtrReadPhys;
2294 return rc;
2295 }
2296
2297 /* TPR threshold without virtual-interrupt delivery. */
2298 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
2299 && (pVmcs->u32TprThreshold & VMX_TPR_THRESHOLD_MASK))
2300 {
2301 Log(("%s: TPR-threshold (%#RX32) invalid -> VMFail\n", pszInstr, pVmcs->u32TprThreshold));
2302 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_TprThreshold;
2303 return VERR_VMX_VMENTRY_FAILED;
2304 }
2305
2306 /* TPR threshold and VTPR. */
2307 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
2308 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
2309 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2310 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
2311 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
2312 {
2313 Log(("%s: TPR-threshold (%#x) exceeds VTPR (%#x) -> VMFail\n", pszInstr,
2314 (pVmcs->u32TprThreshold & VMX_TPR_THRESHOLD_MASK), u8VTpr));
2315 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_TprThresholdVTpr;
2316 return VERR_VMX_VMENTRY_FAILED;
2317 }
2318 }
2319 else
2320 {
2321 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
2322 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
2323 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
2324 { /* likely */ }
2325 else
2326 {
2327 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
2328 {
2329 Log(("%s: Virtualize x2APIC access without TPR shadowing -> VMFail\n", pszInstr));
2330 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtX2ApicTprShadow;
2331 return VERR_VMX_VMENTRY_FAILED;
2332 }
2333 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
2334 {
2335 Log(("%s: APIC-register virtualization without TPR shadowing -> VMFail\n", pszInstr));
2336 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_ApicRegVirt;
2337 return VERR_VMX_VMENTRY_FAILED;
2338 }
2339 else
2340 {
2341 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
2342 Log(("%s: Virtual-interrupt delivery without TPR shadowing -> VMFail\n", pszInstr));
2343 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtIntDelivery;
2344 return VERR_VMX_VMENTRY_FAILED;
2345 }
2346 }
2347 }
2348
2349 /* NMI exiting and virtual-NMIs. */
2350 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
2351 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
2352 {
2353 Log(("%s: Virtual-NMIs invalid without NMI-exiting -> VMFail\n", pszInstr));
2354 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtNmi;
2355 return VERR_VMX_VMENTRY_FAILED;
2356 }
2357
2358 /* Virtual-NMIs and NMI-window exiting. */
2359 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
2360 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
2361 {
2362 Log(("%s: NMI-window exiting invalid without virtual-NMIs -> VMFail\n", pszInstr));
2363 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_NmiWindowExit;
2364 return VERR_VMX_VMENTRY_FAILED;
2365 }
2366
2367 /* Virtualize APIC accesses. */
2368 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2369 {
2370 /* APIC-access physical address. */
2371 RTGCPHYS GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
2372 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
2373 || (GCPhysApicAccess >> cMaxPhysAddrWidth)
2374 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
2375 {
2376 Log(("%s: APIC-access address invalid %#RX64 -> VMFail\n", pszInstr, GCPhysApicAccess));
2377 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrApicAccess;
2378 return VERR_VMX_VMENTRY_FAILED;
2379 }
2380 }
2381
2382 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
2383 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
2384 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
2385 {
2386 Log(("%s: Virtualize-APIC access when virtualize-x2APIC mode is enabled -> VMFail", pszInstr));
2387 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtX2ApicVirtApic;
2388 return VERR_VMX_VMENTRY_FAILED;
2389 }
2390
2391 /* Virtual-interrupt delivery requires external interrupt exiting. */
2392 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
2393 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
2394 {
2395 Log(("%s: Virtual-interrupt delivery without external interrupt exiting -> VMFail\n", pszInstr));
2396 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VirtX2ApicVirtApic;
2397 return VERR_VMX_VMENTRY_FAILED;
2398 }
2399
2400 /* VPID. */
2401 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
2402 && pVmcs->u16Vpid == 0)
2403 {
2404 Log(("%s: VPID invalid -> VMFail\n", pszInstr));
2405 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_Vpid;
2406 return VERR_VMX_VMENTRY_FAILED;
2407 }
2408
2409 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
2410 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
2411 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
2412 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
2413 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
2414 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
2415
2416 /* VMCS shadowing. */
2417 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
2418 {
2419 /* VMREAD-bitmap physical address. */
2420 RTGCPHYS GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
2421 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
2422 || ( GCPhysVmreadBitmap >> cMaxPhysAddrWidth)
2423 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
2424 {
2425 Log(("%s: VMREAD-bitmap address invalid %#RX64 -> VMFail\n", pszInstr, GCPhysVmreadBitmap));
2426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrVmreadBitmap;
2427 return VERR_VMX_VMENTRY_FAILED;
2428 }
2429
2430 /* VMWRITE-bitmap physical address. */
2431 RTGCPHYS GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
2432 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
2433 || ( GCPhysVmwriteBitmap >> cMaxPhysAddrWidth)
2434 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
2435 {
2436 Log(("%s: VMWRITE-bitmap address invalid %#RX64 -> VMFail\n", pszInstr, GCPhysVmwriteBitmap));
2437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_AddrVmwriteBitmap;
2438 return VERR_VMX_VMENTRY_FAILED;
2439 }
2440
2441 /* Read the VMREAD-bitmap. */
2442 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
2443 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2444 if (RT_FAILURE(rc))
2445 {
2446 Log(("%s: Failed to read VMREAD-bitmap at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmreadBitmap, rc));
2447 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VmreadBitmapPtrReadPhys;
2448 return rc;
2449 }
2450
2451 /* Read the VMWRITE-bitmap. */
2452 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
2453 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2454 if (RT_FAILURE(rc))
2455 {
2456 Log(("%s: Failed to read VMWRITE-bitmap at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmwriteBitmap, rc));
2457 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VmwriteBitmapPtrReadPhys;
2458 return rc;
2459 }
2460 }
2461
2462 NOREF(pszInstr);
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/**
2468 * VMLAUNCH/VMRESUME instruction execution worker.
2469 *
2470 * @param pVCpu The cross context virtual CPU structure.
2471 * @param cbInstr The instruction length.
2472 * @param uInstrId The instruction identity (either VMXINSTRID_VMLAUNCH or
2473 * VMXINSTRID_VMRESUME).
2474 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2475 * Optional, can be NULL.
2476 *
2477 * @remarks Common VMX instruction checks are already expected to by the caller,
2478 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
2479 */
2480IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId, PCVMXVEXITINFO pExitInfo)
2481{
2482 Assert( uInstrId == VMXINSTRID_VMLAUNCH
2483 || uInstrId == VMXINSTRID_VMRESUME);
2484
2485 const char *pszInstr = uInstrId == VMXINSTRID_VMLAUNCH ? "vmlaunch" : "vmresume";
2486 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
2487 {
2488 RT_NOREF(pExitInfo);
2489 /** @todo NSTVMX: intercept. */
2490 }
2491 Assert(IEM_IS_VMX_ROOT_MODE(pVCpu));
2492
2493 /* CPL. */
2494 if (pVCpu->iem.s.uCpl > 0)
2495 {
2496 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
2497 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_Cpl;
2498 return iemRaiseGeneralProtectionFault0(pVCpu);
2499 }
2500
2501 /* Current VMCS valid. */
2502 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2503 {
2504 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
2505 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_PtrInvalid;
2506 iemVmxVmFailInvalid(pVCpu);
2507 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2508 return VINF_SUCCESS;
2509 }
2510
2511 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
2512 * use block-by-STI here which is not quite correct. */
2513 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2514 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
2515 {
2516 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
2517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_BlocKMovSS;
2518 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
2519 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2520 return VINF_SUCCESS;
2521 }
2522
2523 if (uInstrId == VMXINSTRID_VMLAUNCH)
2524 {
2525 /* VMLAUNCH with non-clear VMCS. */
2526 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState != VMX_V_VMCS_STATE_CLEAR)
2527 {
2528 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
2529 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VmcsClear;
2530 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
2531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2532 return VINF_SUCCESS;
2533 }
2534 }
2535 else
2536 {
2537 /* VMRESUME with non-launched VMCS. */
2538 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState != VMX_V_VMCS_STATE_LAUNCHED)
2539 {
2540 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
2541 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_VmcsLaunch;
2542 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
2543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2544 return VINF_SUCCESS;
2545 }
2546 }
2547
2548 /*
2549 * Load the current VMCS.
2550 */
2551 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
2552 IEM_VMX_GET_CURRENT_VMCS(pVCpu), VMX_V_VMCS_SIZE);
2553 if (RT_FAILURE(rc))
2554 {
2555 Log(("%s: Failed to read VMCS at %#RGp, rc=%Rrc\n", pszInstr, rc));
2556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_PtrReadPhys;
2557 return rc;
2558 }
2559
2560 /*
2561 * Check VM-execution control fields.
2562 */
2563 rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
2564 if (rc == VINF_SUCCESS)
2565 { /* likely */ }
2566 else
2567 {
2568 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
2569 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2570 return VINF_SUCCESS;
2571 }
2572
2573 /*
2574 * Check VM-exit control fields.
2575 */
2576 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
2577 if (rc == VINF_SUCCESS)
2578 { /* likely */ }
2579 else
2580 {
2581 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
2582 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2583 return VINF_SUCCESS;
2584 }
2585
2586 /*
2587 * Check VM-entry control fields.
2588 */
2589 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
2590 if (rc == VINF_SUCCESS)
2591 { /* likely */ }
2592 else
2593 {
2594 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
2595 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2596 return VINF_SUCCESS;
2597 }
2598
2599 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmentry_Success;
2600 iemVmxVmSucceed(pVCpu);
2601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2602 return VERR_IEM_IPE_2;
2603}
2604
2605
2606/**
2607 * Implements 'VMXON'.
2608 */
2609IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
2610{
2611 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
2612}
2613
2614
2615/**
2616 * Implements 'VMXOFF'.
2617 *
2618 * @remarks Common VMX instruction checks are already expected to by the caller,
2619 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
2620 */
2621IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
2622{
2623# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2624 RT_NOREF2(pVCpu, cbInstr);
2625 return VINF_EM_RAW_EMULATE_INSTR;
2626# else
2627 if (IEM_IS_VMX_NON_ROOT_MODE(pVCpu))
2628 {
2629 /** @todo NSTVMX: intercept. */
2630 }
2631
2632 /* CPL. */
2633 if (pVCpu->iem.s.uCpl > 0)
2634 {
2635 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
2636 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxoff_Cpl;
2637 return iemRaiseGeneralProtectionFault0(pVCpu);
2638 }
2639
2640 /* Dual monitor treatment of SMIs and SMM. */
2641 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
2642 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
2643 {
2644 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
2645 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2646 return VINF_SUCCESS;
2647 }
2648
2649 /*
2650 * Record that we're no longer in VMX root operation, block INIT, block and disable A20M.
2651 */
2652 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
2653 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
2654
2655 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
2656 { /** @todo NSTVMX: Unblock SMI. */ }
2657 /** @todo NSTVMX: Unblock and enable A20M. */
2658 /** @todo NSTVMX: Clear address-range monitoring. */
2659
2660 pVCpu->cpum.GstCtx.hwvirt.vmx.enmInstrDiag = kVmxVInstrDiag_Vmxoff_Success;
2661 iemVmxVmSucceed(pVCpu);
2662 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2663# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2664 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2665# else
2666 return VINF_SUCCESS;
2667# endif
2668# endif
2669}
2670
2671
2672/**
2673 * Implements 'VMLAUNCH'.
2674 */
2675IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
2676{
2677 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH, NULL /* pExitInfo */);
2678}
2679
2680
2681/**
2682 * Implements 'VMRESUME'.
2683 */
2684IEM_CIMPL_DEF_0(iemCImpl_vmresume)
2685{
2686 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME, NULL /* pExitInfo */);
2687}
2688
2689
2690/**
2691 * Implements 'VMPTRLD'.
2692 */
2693IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
2694{
2695 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
2696}
2697
2698
2699/**
2700 * Implements 'VMPTRST'.
2701 */
2702IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
2703{
2704 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
2705}
2706
2707
2708/**
2709 * Implements 'VMCLEAR'.
2710 */
2711IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
2712{
2713 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
2714}
2715
2716
2717/**
2718 * Implements 'VMWRITE' register.
2719 */
2720IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
2721{
2722 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
2723 NULL /* pExitInfo */);
2724}
2725
2726
2727/**
2728 * Implements 'VMWRITE' memory.
2729 */
2730IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
2731{
2732 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
2733}
2734
2735
2736/**
2737 * Implements 'VMREAD' 64-bit register.
2738 */
2739IEM_CIMPL_DEF_2(iemCImpl_vmread64_reg, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
2740{
2741 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
2742}
2743
2744
2745/**
2746 * Implements 'VMREAD' 32-bit register.
2747 */
2748IEM_CIMPL_DEF_2(iemCImpl_vmread32_reg, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
2749{
2750 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
2751}
2752
2753
2754/**
2755 * Implements 'VMREAD' memory.
2756 */
2757IEM_CIMPL_DEF_4(iemCImpl_vmread_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
2758{
2759 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
2760}
2761
2762#endif
2763
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette