VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 74878

Last change on this file since 74878 was 74861, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 VM-exit bits; Interrupt-window exit.
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File size: 289.6 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 74861 2018-10-16 04:40:12Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
20/** @todo NSTVMX: The following VM-exit intercepts are pending:
21 * VMX_EXIT_INIT_SIGNAL
22 * VMX_EXIT_SIPI
23 * VMX_EXIT_IO_SMI
24 * VMX_EXIT_SMI
25 * VMX_EXIT_INT_WINDOW
26 * VMX_EXIT_NMI_WINDOW
27 * VMX_EXIT_GETSEC
28 * VMX_EXIT_RSM
29 * VMX_EXIT_MTF
30 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
31 * VMX_EXIT_ERR_MACHINE_CHECK
32 * VMX_EXIT_TPR_BELOW_THRESHOLD
33 * VMX_EXIT_APIC_ACCESS
34 * VMX_EXIT_VIRTUALIZED_EOI
35 * VMX_EXIT_EPT_VIOLATION
36 * VMX_EXIT_EPT_MISCONFIG
37 * VMX_EXIT_INVEPT
38 * VMX_EXIT_PREEMPT_TIMER
39 * VMX_EXIT_INVVPID
40 * VMX_EXIT_APIC_WRITE
41 * VMX_EXIT_RDRAND
42 * VMX_EXIT_VMFUNC
43 * VMX_EXIT_ENCLS
44 * VMX_EXIT_RDSEED
45 * VMX_EXIT_PML_FULL
46 * VMX_EXIT_XSAVES
47 * VMX_EXIT_XRSTORS
48 */
49
50/**
51 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
52 *
53 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
54 * second dimension is the Index, see VMXVMCSFIELDENC.
55 */
56uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
57{
58 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
59 {
60 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
61 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
62 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
63 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
64 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
65 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
66 },
67 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
68 {
69 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
70 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
71 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
72 /* 24-25 */ UINT16_MAX, UINT16_MAX
73 },
74 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
75 {
76 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
77 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
78 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
79 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
80 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
81 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
82 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
83 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
84 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
85 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
86 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
87 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
88 },
89 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
90 {
91 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
92 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
93 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
94 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
95 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
96 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
97 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
98 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
99 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
100 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
101 },
102 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
103 {
104 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
105 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
106 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
107 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
108 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
109 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
110 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
111 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
112 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
113 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
114 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
115 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
116 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
117 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
118 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
119 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
120 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
121 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
122 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
123 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
124 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
125 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
126 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
127 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
128 /* 24 */ UINT16_MAX,
129 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
130 },
131 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
132 {
133 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
134 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
135 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
136 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
137 /* 25 */ UINT16_MAX
138 },
139 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
140 {
141 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
142 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
143 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
144 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
145 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
146 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
147 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
148 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
149 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
150 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
151 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
152 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
153 },
154 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
155 {
156 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
157 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
158 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
159 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
160 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
161 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
162 },
163 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
164 {
165 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
166 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
167 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
168 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
169 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
170 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
171 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
172 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
173 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
174 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
175 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
176 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
177 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
178 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
179 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
180 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
181 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
182 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
183 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
184 },
185 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
186 {
187 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
188 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
189 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
190 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
191 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
192 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
193 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
194 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
195 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
196 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
197 /* 24-25 */ UINT16_MAX, UINT16_MAX
198 },
199 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
200 {
201 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
202 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
203 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
204 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
205 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
206 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
207 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
208 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
209 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
210 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
211 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
212 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
213 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
214 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
215 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
216 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
217 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
218 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
219 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
220 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
221 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
222 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
223 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
224 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
225 /* 24-25 */ UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
230 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 25 */ UINT16_MAX
234 },
235 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
244 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
245 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
247 /* 24-25 */ UINT16_MAX, UINT16_MAX
248 },
249 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
250 {
251 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
252 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
253 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
254 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
255 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
256 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
257 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
260 },
261 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
262 {
263 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
264 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
265 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
266 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
267 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
268 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
269 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
270 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
271 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
272 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
273 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
274 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
275 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
276 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
277 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
278 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
279 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
280 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
281 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
282 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
283 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
284 },
285 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
297 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
298 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
299 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 }
302};
303
304
305/**
306 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
307 * relative offsets.
308 */
309# ifdef IEM_WITH_CODE_TLB
310# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
311# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
312# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
313# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
314# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
315# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
316# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
317# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
318# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
319# else /* !IEM_WITH_CODE_TLB */
320# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
321 do \
322 { \
323 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
324 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
325 } while (0)
326
327# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
328
329# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
330 do \
331 { \
332 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
333 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
334 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
335 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
336 } while (0)
337
338# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
339 do \
340 { \
341 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
342 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
343 } while (0)
344
345# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
346 do \
347 { \
348 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
349 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
350 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
351 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
352 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
353 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
354 } while (0)
355
356# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
357 do \
358 { \
359 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
360 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
361 } while (0)
362
363# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
364 do \
365 { \
366 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
367 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
368 } while (0)
369
370# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
371 do \
372 { \
373 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
374 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
375 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
376 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
377 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
378 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
379 } while (0)
380# endif /* !IEM_WITH_CODE_TLB */
381
382/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
383#define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
384
385/** Whether a shadow VMCS is present for the given VCPU. */
386#define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
387
388/** Gets the VMXON region pointer. */
389#define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
390
391/** Gets the guest-physical address of the current VMCS for the given VCPU. */
392#define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
393
394/** Whether a current VMCS is present for the given VCPU. */
395#define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
396
397/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
398#define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
399 do \
400 { \
401 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
402 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
403 } while (0)
404
405/** Clears any current VMCS for the given VCPU. */
406#define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
407 do \
408 { \
409 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
410 } while (0)
411
412/** Check for VMX instructions requiring to be in VMX operation.
413 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
414#define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
415 do \
416 { \
417 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
418 { /* likely */ } \
419 else \
420 { \
421 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
422 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
423 return iemRaiseUndefinedOpcode(a_pVCpu); \
424 } \
425 } while (0)
426
427/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
428#define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
429 do \
430 { \
431 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
432 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
433 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
434 return VERR_VMX_VMENTRY_FAILED; \
435 } while (0)
436
437/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
438#define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
439 do \
440 { \
441 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
442 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
443 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
444 return VERR_VMX_VMEXIT_FAILED; \
445 } while (0)
446
447
448/**
449 * Returns whether the given VMCS field is valid and supported by our emulation.
450 *
451 * @param pVCpu The cross context virtual CPU structure.
452 * @param u64FieldEnc The VMCS field encoding.
453 *
454 * @remarks This takes into account the CPU features exposed to the guest.
455 */
456IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
457{
458 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
459 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
460 if (!uFieldEncHi)
461 { /* likely */ }
462 else
463 return false;
464
465 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
466 switch (uFieldEncLo)
467 {
468 /*
469 * 16-bit fields.
470 */
471 /* Control fields. */
472 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
473 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
474 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
475
476 /* Guest-state fields. */
477 case VMX_VMCS16_GUEST_ES_SEL:
478 case VMX_VMCS16_GUEST_CS_SEL:
479 case VMX_VMCS16_GUEST_SS_SEL:
480 case VMX_VMCS16_GUEST_DS_SEL:
481 case VMX_VMCS16_GUEST_FS_SEL:
482 case VMX_VMCS16_GUEST_GS_SEL:
483 case VMX_VMCS16_GUEST_LDTR_SEL:
484 case VMX_VMCS16_GUEST_TR_SEL:
485 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
486 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
487
488 /* Host-state fields. */
489 case VMX_VMCS16_HOST_ES_SEL:
490 case VMX_VMCS16_HOST_CS_SEL:
491 case VMX_VMCS16_HOST_SS_SEL:
492 case VMX_VMCS16_HOST_DS_SEL:
493 case VMX_VMCS16_HOST_FS_SEL:
494 case VMX_VMCS16_HOST_GS_SEL:
495 case VMX_VMCS16_HOST_TR_SEL: return true;
496
497 /*
498 * 64-bit fields.
499 */
500 /* Control fields. */
501 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
502 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
503 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
504 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
505 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
506 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
507 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
508 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
509 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
510 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
511 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
512 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
513 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
514 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
515 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
516 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
517 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
518 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
519 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
520 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
521 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
522 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
523 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
524 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
525 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
526 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
527 case VMX_VMCS64_CTRL_EPTP_FULL:
528 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
529 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
532 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
533 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
534 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
535 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
536 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
537 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
538 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
539 {
540 uint64_t const uVmFuncMsr = CPUMGetGuestIa32VmxVmFunc(pVCpu);
541 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
542 }
543 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
545 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
547 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
548 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
549 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
550 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
551 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
552 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
553 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
554 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
555
556 /* Read-only data fields. */
557 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
558 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
559
560 /* Guest-state fields. */
561 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
562 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
563 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
564 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
565 case VMX_VMCS64_GUEST_PAT_FULL:
566 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
567 case VMX_VMCS64_GUEST_EFER_FULL:
568 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
569 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
570 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
571 case VMX_VMCS64_GUEST_PDPTE0_FULL:
572 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
573 case VMX_VMCS64_GUEST_PDPTE1_FULL:
574 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
575 case VMX_VMCS64_GUEST_PDPTE2_FULL:
576 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
577 case VMX_VMCS64_GUEST_PDPTE3_FULL:
578 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
579 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
580 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
581
582 /* Host-state fields. */
583 case VMX_VMCS64_HOST_PAT_FULL:
584 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
585 case VMX_VMCS64_HOST_EFER_FULL:
586 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
587 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
588 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
589
590 /*
591 * 32-bit fields.
592 */
593 /* Control fields. */
594 case VMX_VMCS32_CTRL_PIN_EXEC:
595 case VMX_VMCS32_CTRL_PROC_EXEC:
596 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
597 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
598 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
599 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
600 case VMX_VMCS32_CTRL_EXIT:
601 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
602 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
603 case VMX_VMCS32_CTRL_ENTRY:
604 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
605 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
606 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
607 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
608 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
609 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
610 case VMX_VMCS32_CTRL_PLE_GAP:
611 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
612
613 /* Read-only data fields. */
614 case VMX_VMCS32_RO_VM_INSTR_ERROR:
615 case VMX_VMCS32_RO_EXIT_REASON:
616 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
617 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
618 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
619 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
620 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
621 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
622
623 /* Guest-state fields. */
624 case VMX_VMCS32_GUEST_ES_LIMIT:
625 case VMX_VMCS32_GUEST_CS_LIMIT:
626 case VMX_VMCS32_GUEST_SS_LIMIT:
627 case VMX_VMCS32_GUEST_DS_LIMIT:
628 case VMX_VMCS32_GUEST_FS_LIMIT:
629 case VMX_VMCS32_GUEST_GS_LIMIT:
630 case VMX_VMCS32_GUEST_LDTR_LIMIT:
631 case VMX_VMCS32_GUEST_TR_LIMIT:
632 case VMX_VMCS32_GUEST_GDTR_LIMIT:
633 case VMX_VMCS32_GUEST_IDTR_LIMIT:
634 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
638 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
639 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
640 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
641 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
642 case VMX_VMCS32_GUEST_INT_STATE:
643 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
644 case VMX_VMCS32_GUEST_SMBASE:
645 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
646 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
647
648 /* Host-state fields. */
649 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
650
651 /*
652 * Natural-width fields.
653 */
654 /* Control fields. */
655 case VMX_VMCS_CTRL_CR0_MASK:
656 case VMX_VMCS_CTRL_CR4_MASK:
657 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
658 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
659 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
660 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
661 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
662 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
663
664 /* Read-only data fields. */
665 case VMX_VMCS_RO_EXIT_QUALIFICATION:
666 case VMX_VMCS_RO_IO_RCX:
667 case VMX_VMCS_RO_IO_RSX:
668 case VMX_VMCS_RO_IO_RDI:
669 case VMX_VMCS_RO_IO_RIP:
670 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
671
672 /* Guest-state fields. */
673 case VMX_VMCS_GUEST_CR0:
674 case VMX_VMCS_GUEST_CR3:
675 case VMX_VMCS_GUEST_CR4:
676 case VMX_VMCS_GUEST_ES_BASE:
677 case VMX_VMCS_GUEST_CS_BASE:
678 case VMX_VMCS_GUEST_SS_BASE:
679 case VMX_VMCS_GUEST_DS_BASE:
680 case VMX_VMCS_GUEST_FS_BASE:
681 case VMX_VMCS_GUEST_GS_BASE:
682 case VMX_VMCS_GUEST_LDTR_BASE:
683 case VMX_VMCS_GUEST_TR_BASE:
684 case VMX_VMCS_GUEST_GDTR_BASE:
685 case VMX_VMCS_GUEST_IDTR_BASE:
686 case VMX_VMCS_GUEST_DR7:
687 case VMX_VMCS_GUEST_RSP:
688 case VMX_VMCS_GUEST_RIP:
689 case VMX_VMCS_GUEST_RFLAGS:
690 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
691 case VMX_VMCS_GUEST_SYSENTER_ESP:
692 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
693
694 /* Host-state fields. */
695 case VMX_VMCS_HOST_CR0:
696 case VMX_VMCS_HOST_CR3:
697 case VMX_VMCS_HOST_CR4:
698 case VMX_VMCS_HOST_FS_BASE:
699 case VMX_VMCS_HOST_GS_BASE:
700 case VMX_VMCS_HOST_TR_BASE:
701 case VMX_VMCS_HOST_GDTR_BASE:
702 case VMX_VMCS_HOST_IDTR_BASE:
703 case VMX_VMCS_HOST_SYSENTER_ESP:
704 case VMX_VMCS_HOST_SYSENTER_EIP:
705 case VMX_VMCS_HOST_RSP:
706 case VMX_VMCS_HOST_RIP: return true;
707 }
708
709 return false;
710}
711
712
713/**
714 * Gets a host selector from the VMCS.
715 *
716 * @param pVmcs Pointer to the virtual VMCS.
717 * @param iSelReg The index of the segment register (X86_SREG_XXX).
718 */
719DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
720{
721 Assert(iSegReg < X86_SREG_COUNT);
722 RTSEL HostSel;
723 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
724 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
725 uint8_t const uWidthType = (uWidth << 2) | uType;
726 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
727 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
728 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
729 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
730 uint8_t const *pbField = pbVmcs + offField;
731 HostSel = *(uint16_t *)pbField;
732 return HostSel;
733}
734
735
736/**
737 * Sets a guest segment register in the VMCS.
738 *
739 * @param pVmcs Pointer to the virtual VMCS.
740 * @param iSegReg The index of the segment register (X86_SREG_XXX).
741 * @param pSelReg Pointer to the segment register.
742 */
743IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
744{
745 Assert(pSelReg);
746 Assert(iSegReg < X86_SREG_COUNT);
747
748 /* Selector. */
749 {
750 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
751 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
752 uint8_t const uWidthType = (uWidth << 2) | uType;
753 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
754 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
755 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
756 uint8_t *pbVmcs = (uint8_t *)pVmcs;
757 uint8_t *pbField = pbVmcs + offField;
758 *(uint16_t *)pbField = pSelReg->Sel;
759 }
760
761 /* Limit. */
762 {
763 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
764 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
765 uint8_t const uWidthType = (uWidth << 2) | uType;
766 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
767 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
768 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
769 uint8_t *pbVmcs = (uint8_t *)pVmcs;
770 uint8_t *pbField = pbVmcs + offField;
771 *(uint32_t *)pbField = pSelReg->u32Limit;
772 }
773
774 /* Base. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t const *pbField = pbVmcs + offField;
784 *(uint64_t *)pbField = pSelReg->u64Base;
785 }
786
787 /* Attributes. */
788 {
789 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
790 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
791 | X86DESCATTR_UNUSABLE;
792 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
793 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
794 uint8_t const uWidthType = (uWidth << 2) | uType;
795 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
796 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
797 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
798 uint8_t *pbVmcs = (uint8_t *)pVmcs;
799 uint8_t *pbField = pbVmcs + offField;
800 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
801 }
802}
803
804
805/**
806 * Gets a guest segment register from the VMCS.
807 *
808 * @returns VBox status code.
809 * @param pVmcs Pointer to the virtual VMCS.
810 * @param iSegReg The index of the segment register (X86_SREG_XXX).
811 * @param pSelReg Where to store the segment register (only updated when
812 * VINF_SUCCESS is returned).
813 *
814 * @remarks Warning! This does not validate the contents of the retrieved segment
815 * register.
816 */
817IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
818{
819 Assert(pSelReg);
820 Assert(iSegReg < X86_SREG_COUNT);
821
822 /* Selector. */
823 uint16_t u16Sel;
824 {
825 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
826 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
827 uint8_t const uWidthType = (uWidth << 2) | uType;
828 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
829 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
830 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
831 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
832 uint8_t const *pbField = pbVmcs + offField;
833 u16Sel = *(uint16_t *)pbField;
834 }
835
836 /* Limit. */
837 uint32_t u32Limit;
838 {
839 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
840 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
841 uint8_t const uWidthType = (uWidth << 2) | uType;
842 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
843 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
844 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
845 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
846 uint8_t const *pbField = pbVmcs + offField;
847 u32Limit = *(uint32_t *)pbField;
848 }
849
850 /* Base. */
851 uint64_t u64Base;
852 {
853 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
854 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
855 uint8_t const uWidthType = (uWidth << 2) | uType;
856 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
857 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
858 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
859 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
860 uint8_t const *pbField = pbVmcs + offField;
861 u64Base = *(uint64_t *)pbField;
862 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
863 }
864
865 /* Attributes. */
866 uint32_t u32Attr;
867 {
868 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
869 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
870 uint8_t const uWidthType = (uWidth << 2) | uType;
871 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
872 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
873 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
874 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
875 uint8_t const *pbField = pbVmcs + offField;
876 u32Attr = *(uint32_t *)pbField;
877 }
878
879 pSelReg->Sel = u16Sel;
880 pSelReg->ValidSel = u16Sel;
881 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
882 pSelReg->u32Limit = u32Limit;
883 pSelReg->u64Base = u64Base;
884 pSelReg->Attr.u = u32Attr;
885 return VINF_SUCCESS;
886}
887
888
889/**
890 * Gets a CR3 target value from the VMCS.
891 *
892 * @returns VBox status code.
893 * @param pVmcs Pointer to the virtual VMCS.
894 * @param idxCr3Target The index of the CR3-target value to retrieve.
895 * @param puValue Where to store the CR3-target value.
896 */
897DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
898{
899 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
900 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
901 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
902 uint8_t const uWidthType = (uWidth << 2) | uType;
903 uint8_t const uIndex = (idxCr3Target << 1) + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
904 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
905 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
906 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
907 uint8_t const *pbField = pbVmcs + offField;
908 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
909
910 return uCr3TargetValue;
911}
912
913
914/**
915 * Reads a 32-bit register from the virtual-APIC page at the given offset.
916 *
917 * @returns The register from the virtual-APIC page.
918 * @param pVCpu The cross context virtual CPU structure.
919 * @param offReg The offset of the register being read.
920 */
921DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint8_t offReg)
922{
923 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
924 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
925 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
926 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
927 return uReg;
928}
929
930
931/**
932 * Writes a 32-bit register to the virtual-APIC page at the given offset.
933 *
934 * @param pVCpu The cross context virtual CPU structure.
935 * @param uReg The register value to write.
936 * @param offReg The offset of the register being written.
937 */
938DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint32_t uReg, uint8_t offReg)
939{
940 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
941 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
942 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
943 *(uint32_t *)(pbVirtApic + offReg) = uReg;
944}
945
946
947/**
948 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
949 * mask and the read-shadow (CR0/CR4 read).
950 *
951 * @returns The masked CR0/CR4.
952 * @param pVCpu The cross context virtual CPU structure.
953 * @param iCrReg The control register (either CR0 or CR4).
954 * @param uGuestCrX The current guest CR0 or guest CR4.
955 */
956IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
957{
958 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
959 Assert(iCrReg == 0 || iCrReg == 4);
960
961 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
962 Assert(pVmcs);
963
964 /*
965 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
966 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
967 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
968 *
969 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
970 */
971 uint64_t fGstHostMask;
972 uint64_t fReadShadow;
973 if (iCrReg == 0)
974 {
975 fGstHostMask = pVmcs->u64Cr0Mask.u;
976 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
977 }
978 else
979 {
980 fGstHostMask = pVmcs->u64Cr4Mask.u;
981 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
982 }
983
984 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
985 return fMaskedCrX;
986}
987
988
989/**
990 * Gets VM-exit instruction information along with any displacement for an
991 * instruction VM-exit.
992 *
993 * @returns The VM-exit instruction information.
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uExitReason The VM-exit reason.
996 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
997 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
998 * NULL.
999 */
1000IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
1001{
1002 RTGCPTR GCPtrDisp;
1003 VMXEXITINSTRINFO ExitInstrInfo;
1004 ExitInstrInfo.u = 0;
1005
1006 /*
1007 * Get and parse the ModR/M byte from our decoded opcodes.
1008 */
1009 uint8_t bRm;
1010 uint8_t const offModRm = pVCpu->iem.s.offModRm;
1011 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
1012 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1013 {
1014 /*
1015 * ModR/M indicates register addressing.
1016 *
1017 * The primary/secondary register operands are reported in the iReg1 or iReg2
1018 * fields depending on whether it is a read/write form.
1019 */
1020 uint8_t idxReg1;
1021 uint8_t idxReg2;
1022 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1023 {
1024 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1025 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1026 }
1027 else
1028 {
1029 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1030 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1031 }
1032 ExitInstrInfo.All.u2Scaling = 0;
1033 ExitInstrInfo.All.iReg1 = idxReg1;
1034 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1035 ExitInstrInfo.All.fIsRegOperand = 1;
1036 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1037 ExitInstrInfo.All.iSegReg = 0;
1038 ExitInstrInfo.All.iIdxReg = 0;
1039 ExitInstrInfo.All.fIdxRegInvalid = 1;
1040 ExitInstrInfo.All.iBaseReg = 0;
1041 ExitInstrInfo.All.fBaseRegInvalid = 1;
1042 ExitInstrInfo.All.iReg2 = idxReg2;
1043
1044 /* Displacement not applicable for register addressing. */
1045 GCPtrDisp = 0;
1046 }
1047 else
1048 {
1049 /*
1050 * ModR/M indicates memory addressing.
1051 */
1052 uint8_t uScale = 0;
1053 bool fBaseRegValid = false;
1054 bool fIdxRegValid = false;
1055 uint8_t iBaseReg = 0;
1056 uint8_t iIdxReg = 0;
1057 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
1058 {
1059 /*
1060 * Parse the ModR/M, displacement for 16-bit addressing mode.
1061 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
1062 */
1063 uint16_t u16Disp = 0;
1064 uint8_t const offDisp = offModRm + sizeof(bRm);
1065 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
1066 {
1067 /* Displacement without any registers. */
1068 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
1069 }
1070 else
1071 {
1072 /* Register (index and base). */
1073 switch (bRm & X86_MODRM_RM_MASK)
1074 {
1075 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1076 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1077 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1078 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1079 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1080 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1081 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
1082 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
1083 }
1084
1085 /* Register + displacement. */
1086 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1087 {
1088 case 0: break;
1089 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
1090 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
1091 default:
1092 {
1093 /* Register addressing, handled at the beginning. */
1094 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1095 break;
1096 }
1097 }
1098 }
1099
1100 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
1101 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
1102 }
1103 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
1104 {
1105 /*
1106 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
1107 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
1108 */
1109 uint32_t u32Disp = 0;
1110 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
1111 {
1112 /* Displacement without any registers. */
1113 uint8_t const offDisp = offModRm + sizeof(bRm);
1114 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1115 }
1116 else
1117 {
1118 /* Register (and perhaps scale, index and base). */
1119 uint8_t offDisp = offModRm + sizeof(bRm);
1120 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1121 if (iBaseReg == 4)
1122 {
1123 /* An SIB byte follows the ModR/M byte, parse it. */
1124 uint8_t bSib;
1125 uint8_t const offSib = offModRm + sizeof(bRm);
1126 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1127
1128 /* A displacement may follow SIB, update its offset. */
1129 offDisp += sizeof(bSib);
1130
1131 /* Get the scale. */
1132 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1133
1134 /* Get the index register. */
1135 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
1136 fIdxRegValid = RT_BOOL(iIdxReg != 4);
1137
1138 /* Get the base register. */
1139 iBaseReg = bSib & X86_SIB_BASE_MASK;
1140 fBaseRegValid = true;
1141 if (iBaseReg == 5)
1142 {
1143 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1144 {
1145 /* Mod is 0 implies a 32-bit displacement with no base. */
1146 fBaseRegValid = false;
1147 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1148 }
1149 else
1150 {
1151 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
1152 iBaseReg = X86_GREG_xBP;
1153 }
1154 }
1155 }
1156
1157 /* Register + displacement. */
1158 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1159 {
1160 case 0: /* Handled above */ break;
1161 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
1162 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
1163 default:
1164 {
1165 /* Register addressing, handled at the beginning. */
1166 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1167 break;
1168 }
1169 }
1170 }
1171
1172 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
1173 }
1174 else
1175 {
1176 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
1177
1178 /*
1179 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
1180 * See Intel instruction spec. 2.2 "IA-32e Mode".
1181 */
1182 uint64_t u64Disp = 0;
1183 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
1184 if (fRipRelativeAddr)
1185 {
1186 /*
1187 * RIP-relative addressing mode.
1188 *
1189 * The displacement is 32-bit signed implying an offset range of +/-2G.
1190 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
1191 */
1192 uint8_t const offDisp = offModRm + sizeof(bRm);
1193 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1194 }
1195 else
1196 {
1197 uint8_t offDisp = offModRm + sizeof(bRm);
1198
1199 /*
1200 * Register (and perhaps scale, index and base).
1201 *
1202 * REX.B extends the most-significant bit of the base register. However, REX.B
1203 * is ignored while determining whether an SIB follows the opcode. Hence, we
1204 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
1205 *
1206 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
1207 */
1208 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1209 if (iBaseReg == 4)
1210 {
1211 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
1212 uint8_t bSib;
1213 uint8_t const offSib = offModRm + sizeof(bRm);
1214 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1215
1216 /* Displacement may follow SIB, update its offset. */
1217 offDisp += sizeof(bSib);
1218
1219 /* Get the scale. */
1220 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1221
1222 /* Get the index. */
1223 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
1224 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
1225
1226 /* Get the base. */
1227 iBaseReg = (bSib & X86_SIB_BASE_MASK);
1228 fBaseRegValid = true;
1229 if (iBaseReg == 5)
1230 {
1231 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1232 {
1233 /* Mod is 0 implies a signed 32-bit displacement with no base. */
1234 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1235 }
1236 else
1237 {
1238 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
1239 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
1240 }
1241 }
1242 }
1243 iBaseReg |= pVCpu->iem.s.uRexB;
1244
1245 /* Register + displacement. */
1246 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1247 {
1248 case 0: /* Handled above */ break;
1249 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
1250 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
1251 default:
1252 {
1253 /* Register addressing, handled at the beginning. */
1254 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1255 break;
1256 }
1257 }
1258 }
1259
1260 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
1261 }
1262
1263 /*
1264 * The primary or secondary register operand is reported in iReg2 depending
1265 * on whether the primary operand is in read/write form.
1266 */
1267 uint8_t idxReg2;
1268 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1269 {
1270 idxReg2 = bRm & X86_MODRM_RM_MASK;
1271 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1272 idxReg2 |= pVCpu->iem.s.uRexB;
1273 }
1274 else
1275 {
1276 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
1277 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1278 idxReg2 |= pVCpu->iem.s.uRexReg;
1279 }
1280 ExitInstrInfo.All.u2Scaling = uScale;
1281 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
1282 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1283 ExitInstrInfo.All.fIsRegOperand = 0;
1284 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1285 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
1286 ExitInstrInfo.All.iIdxReg = iIdxReg;
1287 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
1288 ExitInstrInfo.All.iBaseReg = iBaseReg;
1289 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
1290 ExitInstrInfo.All.iReg2 = idxReg2;
1291 }
1292
1293 /*
1294 * Handle exceptions to the norm for certain instructions.
1295 * (e.g. some instructions convey an instruction identity in place of iReg2).
1296 */
1297 switch (uExitReason)
1298 {
1299 case VMX_EXIT_GDTR_IDTR_ACCESS:
1300 {
1301 Assert(VMXINSTRID_IS_VALID(uInstrId));
1302 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1303 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1304 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
1305 break;
1306 }
1307
1308 case VMX_EXIT_LDTR_TR_ACCESS:
1309 {
1310 Assert(VMXINSTRID_IS_VALID(uInstrId));
1311 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1312 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1313 ExitInstrInfo.LdtTr.u2Undef0 = 0;
1314 break;
1315 }
1316
1317 case VMX_EXIT_RDRAND:
1318 case VMX_EXIT_RDSEED:
1319 {
1320 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
1321 break;
1322 }
1323 }
1324
1325 /* Update displacement and return the constructed VM-exit instruction information field. */
1326 if (pGCPtrDisp)
1327 *pGCPtrDisp = GCPtrDisp;
1328
1329 return ExitInstrInfo.u;
1330}
1331
1332
1333/**
1334 * Converts an IEM exception event type to a VMX event type.
1335 *
1336 * @returns The VMX event type.
1337 * @param uVector The interrupt / exception vector.
1338 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
1339 */
1340DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
1341{
1342 /* Paranoia (callers may use these interchangeably). */
1343 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
1344 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
1345 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
1346 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
1347 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
1348 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
1349 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
1350 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
1351 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
1352 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
1353 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
1354 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
1355
1356 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
1357 {
1358 if (uVector == X86_XCPT_NMI)
1359 return VMX_EXIT_INT_INFO_TYPE_NMI;
1360 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
1361 }
1362
1363 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
1364 {
1365 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
1366 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
1367 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
1368 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
1369 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
1370 }
1371
1372 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
1373 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
1374}
1375
1376
1377/**
1378 * Sets the VM-instruction error VMCS field.
1379 *
1380 * @param pVCpu The cross context virtual CPU structure.
1381 * @param enmInsErr The VM-instruction error.
1382 */
1383DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1384{
1385 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1386 pVmcs->u32RoVmInstrError = enmInsErr;
1387}
1388
1389
1390/**
1391 * Sets the VM-exit qualification VMCS field.
1392 *
1393 * @param pVCpu The cross context virtual CPU structure.
1394 * @param uExitQual The VM-exit qualification.
1395 */
1396DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
1397{
1398 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1399 pVmcs->u64RoExitQual.u = uExitQual;
1400}
1401
1402
1403/**
1404 * Sets the VM-exit interruption information field.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param uExitQual The VM-exit interruption information.
1408 */
1409DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1410{
1411 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1412 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1413}
1414
1415
1416/**
1417 * Sets the VM-exit interruption error code.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uErrCode The error code.
1421 */
1422DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1423{
1424 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1425 pVmcs->u32RoExitIntErrCode = uErrCode;
1426}
1427
1428
1429/**
1430 * Sets the IDT-vectoring information field.
1431 *
1432 * @param pVCpu The cross context virtual CPU structure.
1433 * @param uIdtVectorInfo The IDT-vectoring information.
1434 */
1435DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1436{
1437 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1438 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1439}
1440
1441
1442/**
1443 * Sets the IDT-vectoring error code field.
1444 *
1445 * @param pVCpu The cross context virtual CPU structure.
1446 * @param uErrCode The error code.
1447 */
1448DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1449{
1450 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1451 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1452}
1453
1454
1455/**
1456 * Sets the VM-exit guest-linear address VMCS field.
1457 *
1458 * @param pVCpu The cross context virtual CPU structure.
1459 * @param uGuestLinearAddr The VM-exit guest-linear address.
1460 */
1461DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1462{
1463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1464 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1465}
1466
1467
1468/**
1469 * Sets the VM-exit guest-physical address VMCS field.
1470 *
1471 * @param pVCpu The cross context virtual CPU structure.
1472 * @param uGuestPhysAddr The VM-exit guest-physical address.
1473 */
1474DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1475{
1476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1477 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1478}
1479
1480
1481/**
1482 * Sets the VM-exit instruction length VMCS field.
1483 *
1484 * @param pVCpu The cross context virtual CPU structure.
1485 * @param cbInstr The VM-exit instruction length in bytes.
1486 *
1487 * @remarks Callers may clear this field to 0. Hence, this function does not check
1488 * the validity of the instruction length.
1489 */
1490DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1491{
1492 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1493 pVmcs->u32RoExitInstrLen = cbInstr;
1494}
1495
1496
1497/**
1498 * Sets the VM-exit instruction info. VMCS field.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 * @param uExitInstrInfo The VM-exit instruction information.
1502 */
1503DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1504{
1505 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1506 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1507}
1508
1509
1510/**
1511 * Implements VMSucceed for VMX instruction success.
1512 *
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1516{
1517 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1518}
1519
1520
1521/**
1522 * Implements VMFailInvalid for VMX instruction failure.
1523 *
1524 * @param pVCpu The cross context virtual CPU structure.
1525 */
1526DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1527{
1528 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1529 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1530}
1531
1532
1533/**
1534 * Implements VMFailValid for VMX instruction failure.
1535 *
1536 * @param pVCpu The cross context virtual CPU structure.
1537 * @param enmInsErr The VM instruction error.
1538 */
1539DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1540{
1541 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1542 {
1543 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1544 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1545 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1546 }
1547}
1548
1549
1550/**
1551 * Implements VMFail for VMX instruction failure.
1552 *
1553 * @param pVCpu The cross context virtual CPU structure.
1554 * @param enmInsErr The VM instruction error.
1555 */
1556DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1557{
1558 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1559 iemVmxVmFailValid(pVCpu, enmInsErr);
1560 else
1561 iemVmxVmFailInvalid(pVCpu);
1562}
1563
1564
1565/**
1566 * Checks if the given auto-load/store MSR area count is valid for the
1567 * implementation.
1568 *
1569 * @returns @c true if it's within the valid limit, @c false otherwise.
1570 * @param pVCpu The cross context virtual CPU structure.
1571 * @param uMsrCount The MSR area count to check.
1572 */
1573DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1574{
1575 uint64_t const u64VmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
1576 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1577 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1578 if (uMsrCount <= cMaxSupportedMsrs)
1579 return true;
1580 return false;
1581}
1582
1583
1584/**
1585 * Flushes the current VMCS contents back to guest memory.
1586 *
1587 * @returns VBox status code.
1588 * @param pVCpu The cross context virtual CPU structure.
1589 */
1590DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1591{
1592 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1593 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1594 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1595 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1596 return rc;
1597}
1598
1599
1600/**
1601 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1602 *
1603 * @param pVCpu The cross context virtual CPU structure.
1604 */
1605DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1606{
1607 iemVmxVmSucceed(pVCpu);
1608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1609}
1610
1611
1612/**
1613 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1614 * nested-guest.
1615 *
1616 * @param iSegReg The segment index (X86_SREG_XXX).
1617 */
1618IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1619{
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1623 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1624 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1625 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1626 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1627 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1628 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1629 }
1630}
1631
1632
1633/**
1634 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1635 * nested-guest that is in Virtual-8086 mode.
1636 *
1637 * @param iSegReg The segment index (X86_SREG_XXX).
1638 */
1639IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1640{
1641 switch (iSegReg)
1642 {
1643 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1644 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1645 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1646 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1647 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1648 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1649 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1650 }
1651}
1652
1653
1654/**
1655 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1656 * nested-guest that is in Virtual-8086 mode.
1657 *
1658 * @param iSegReg The segment index (X86_SREG_XXX).
1659 */
1660IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1661{
1662 switch (iSegReg)
1663 {
1664 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1665 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1666 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1667 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1668 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1669 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1670 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1671 }
1672}
1673
1674
1675/**
1676 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1677 * nested-guest that is in Virtual-8086 mode.
1678 *
1679 * @param iSegReg The segment index (X86_SREG_XXX).
1680 */
1681IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1682{
1683 switch (iSegReg)
1684 {
1685 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1686 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1687 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1688 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1689 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1690 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1691 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1692 }
1693}
1694
1695
1696/**
1697 * Gets the instruction diagnostic for segment attributes reserved bits failure
1698 * during VM-entry of a nested-guest.
1699 *
1700 * @param iSegReg The segment index (X86_SREG_XXX).
1701 */
1702IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1703{
1704 switch (iSegReg)
1705 {
1706 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1707 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1708 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1709 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1710 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1711 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1712 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1713 }
1714}
1715
1716
1717/**
1718 * Gets the instruction diagnostic for segment attributes descriptor-type
1719 * (code/segment or system) failure during VM-entry of a nested-guest.
1720 *
1721 * @param iSegReg The segment index (X86_SREG_XXX).
1722 */
1723IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1724{
1725 switch (iSegReg)
1726 {
1727 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1728 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1729 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1730 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1731 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1732 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1733 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1734 }
1735}
1736
1737
1738/**
1739 * Gets the instruction diagnostic for segment attributes descriptor-type
1740 * (code/segment or system) failure during VM-entry of a nested-guest.
1741 *
1742 * @param iSegReg The segment index (X86_SREG_XXX).
1743 */
1744IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1745{
1746 switch (iSegReg)
1747 {
1748 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1749 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1750 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1751 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1752 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1753 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1754 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1755 }
1756}
1757
1758
1759/**
1760 * Gets the instruction diagnostic for segment attribute granularity failure during
1761 * VM-entry of a nested-guest.
1762 *
1763 * @param iSegReg The segment index (X86_SREG_XXX).
1764 */
1765IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1766{
1767 switch (iSegReg)
1768 {
1769 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1770 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1771 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1772 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1773 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1774 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1775 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1776 }
1777}
1778
1779/**
1780 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1781 * VM-entry of a nested-guest.
1782 *
1783 * @param iSegReg The segment index (X86_SREG_XXX).
1784 */
1785IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1786{
1787 switch (iSegReg)
1788 {
1789 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1790 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1791 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1792 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1793 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1794 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1795 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1796 }
1797}
1798
1799
1800/**
1801 * Gets the instruction diagnostic for segment attribute type accessed failure
1802 * during VM-entry of a nested-guest.
1803 *
1804 * @param iSegReg The segment index (X86_SREG_XXX).
1805 */
1806IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1807{
1808 switch (iSegReg)
1809 {
1810 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1811 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1812 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1813 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1814 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1815 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1816 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1817 }
1818}
1819
1820
1821/**
1822 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1823 * failure during VM-entry of a nested-guest.
1824 *
1825 * @param iSegReg The PDPTE entry index.
1826 */
1827IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1828{
1829 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1830 switch (iPdpte)
1831 {
1832 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1833 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1834 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1835 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1836 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1837 }
1838}
1839
1840
1841/**
1842 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1843 * failure during VM-exit of a nested-guest.
1844 *
1845 * @param iSegReg The PDPTE entry index.
1846 */
1847IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1848{
1849 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1850 switch (iPdpte)
1851 {
1852 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1853 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1854 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1855 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1856 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1857 }
1858}
1859
1860
1861/**
1862 * Saves the guest control registers, debug registers and some MSRs are part of
1863 * VM-exit.
1864 *
1865 * @param pVCpu The cross context virtual CPU structure.
1866 */
1867IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1868{
1869 /*
1870 * Saves the guest control registers, debug registers and some MSRs.
1871 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1872 */
1873 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1874
1875 /* Save control registers. */
1876 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1877 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1878 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1879
1880 /* Save SYSENTER CS, ESP, EIP. */
1881 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1882 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1883 {
1884 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1885 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1886 }
1887 else
1888 {
1889 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1890 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1891 }
1892
1893 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1894 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1895 {
1896 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1897 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1898 }
1899
1900 /* Save PAT MSR. */
1901 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1902 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1903
1904 /* Save EFER MSR. */
1905 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1906 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1907
1908 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1909 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1910
1911 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1912}
1913
1914
1915/**
1916 * Saves the guest force-flags in preparation of entering the nested-guest.
1917 *
1918 * @param pVCpu The cross context virtual CPU structure.
1919 */
1920IEM_STATIC void iemVmxVmentrySaveForceFlags(PVMCPU pVCpu)
1921{
1922 /* We shouldn't be called multiple times during VM-entry. */
1923 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1924
1925 /* MTF should not be set outside VMX non-root mode. */
1926 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_MTF));
1927
1928 /*
1929 * Preserve the required force-flags.
1930 *
1931 * We cache and clear force-flags that would affect the execution of the
1932 * nested-guest. Cached flags are then restored while returning to the guest
1933 * if necessary.
1934 *
1935 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1936 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1937 * instruction. Interrupt inhibition for any nested-guest instruction
1938 * will be set later while loading the guest-interruptibility state.
1939 *
1940 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1941 * successful VM-entry needs to continue blocking NMIs if it was in effect
1942 * during VM-entry.
1943 *
1944 * - MTF need not be preserved as it's used only in VMX non-root mode and
1945 * is supplied on VM-entry through the VM-execution controls.
1946 *
1947 * The remaining FFs (e.g. timers, APIC updates) must stay in place so that
1948 * we will be able to generate interrupts that may cause VM-exits for
1949 * the nested-guest.
1950 */
1951 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1952
1953 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS))
1954 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS);
1955}
1956
1957
1958/**
1959 * Restores the guest force-flags in preparation of exiting the nested-guest.
1960 *
1961 * @param pVCpu The cross context virtual CPU structure.
1962 */
1963IEM_STATIC void iemVmxVmexitRestoreForceFlags(PVMCPU pVCpu)
1964{
1965 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1966 {
1967 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1968 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1969 }
1970}
1971
1972
1973/**
1974 * Perform a VMX transition updated PGM, IEM and CPUM.
1975 *
1976 * @param pVCpu The cross context virtual CPU structure.
1977 */
1978IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1979{
1980 /*
1981 * Inform PGM about paging mode changes.
1982 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1983 * see comment in iemMemPageTranslateAndCheckAccess().
1984 */
1985 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1986# ifdef IN_RING3
1987 Assert(rc != VINF_PGM_CHANGE_MODE);
1988# endif
1989 AssertRCReturn(rc, rc);
1990
1991 /* Inform CPUM (recompiler), can later be removed. */
1992 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1993
1994 /*
1995 * Flush the TLB with new CR3. This is required in case the PGM mode change
1996 * above doesn't actually change anything.
1997 */
1998 if (rc == VINF_SUCCESS)
1999 {
2000 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
2001 AssertRCReturn(rc, rc);
2002 }
2003
2004 /* Re-initialize IEM cache/state after the drastic mode switch. */
2005 iemReInitExec(pVCpu);
2006 return rc;
2007}
2008
2009
2010/**
2011 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
2012 *
2013 * @param pVCpu The cross context virtual CPU structure.
2014 */
2015IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
2016{
2017 /*
2018 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
2019 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
2020 */
2021 /* CS, SS, ES, DS, FS, GS. */
2022 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2023 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2024 {
2025 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2026 if (!pSelReg->Attr.n.u1Unusable)
2027 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
2028 else
2029 {
2030 /*
2031 * For unusable segments the attributes are undefined except for CS and SS.
2032 * For the rest we don't bother preserving anything but the unusable bit.
2033 */
2034 switch (iSegReg)
2035 {
2036 case X86_SREG_CS:
2037 pVmcs->GuestCs = pSelReg->Sel;
2038 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
2039 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
2040 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
2041 | X86DESCATTR_UNUSABLE);
2042 break;
2043
2044 case X86_SREG_SS:
2045 pVmcs->GuestSs = pSelReg->Sel;
2046 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2047 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
2048 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
2049 break;
2050
2051 case X86_SREG_DS:
2052 pVmcs->GuestDs = pSelReg->Sel;
2053 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2054 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
2055 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
2056 break;
2057
2058 case X86_SREG_ES:
2059 pVmcs->GuestEs = pSelReg->Sel;
2060 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2061 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
2062 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
2063 break;
2064
2065 case X86_SREG_FS:
2066 pVmcs->GuestFs = pSelReg->Sel;
2067 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
2068 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
2069 break;
2070
2071 case X86_SREG_GS:
2072 pVmcs->GuestGs = pSelReg->Sel;
2073 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
2074 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
2075 break;
2076 }
2077 }
2078 }
2079
2080 /* Segment attribute bits 31:7 and 11:8 MBZ. */
2081 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
2082 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
2083 /* LDTR. */
2084 {
2085 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
2086 pVmcs->GuestLdtr = pSelReg->Sel;
2087 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
2088 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
2089 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
2090 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
2091 }
2092
2093 /* TR. */
2094 {
2095 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
2096 pVmcs->GuestTr = pSelReg->Sel;
2097 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
2098 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
2099 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
2100 }
2101
2102 /* GDTR. */
2103 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
2104 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
2105
2106 /* IDTR. */
2107 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
2108 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
2109}
2110
2111
2112/**
2113 * Saves guest non-register state as part of VM-exit.
2114 *
2115 * @param pVCpu The cross context virtual CPU structure.
2116 * @param uExitReason The VM-exit reason.
2117 */
2118IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
2119{
2120 /*
2121 * Save guest non-register state.
2122 * See Intel spec. 27.3.4 "Saving Non-Register State".
2123 */
2124 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2125
2126 /* Activity-state: VM-exits occur before changing the activity state, nothing further to do */
2127
2128 /* Interruptibility-state. */
2129 pVmcs->u32GuestIntrState = 0;
2130 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
2131 { /** @todo NSTVMX: Virtual-NMI blocking. */ }
2132 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2133 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
2134
2135 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2136 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
2137 {
2138 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
2139 * currently. */
2140 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
2141 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2142 }
2143 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
2144
2145 /* Pending debug exceptions. */
2146 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
2147 && uExitReason != VMX_EXIT_SMI
2148 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
2149 && !HMVmxIsTrapLikeVmexit(uExitReason))
2150 {
2151 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
2152 * block-by-MovSS is in effect. */
2153 pVmcs->u64GuestPendingDbgXcpt.u = 0;
2154 }
2155
2156 /** @todo NSTVMX: Save VMX preemption timer value. */
2157
2158 /* PDPTEs. */
2159 /* We don't support EPT yet. */
2160 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
2161 pVmcs->u64GuestPdpte0.u = 0;
2162 pVmcs->u64GuestPdpte1.u = 0;
2163 pVmcs->u64GuestPdpte2.u = 0;
2164 pVmcs->u64GuestPdpte3.u = 0;
2165}
2166
2167
2168/**
2169 * Saves the guest-state as part of VM-exit.
2170 *
2171 * @returns VBox status code.
2172 * @param pVCpu The cross context virtual CPU structure.
2173 * @param uExitReason The VM-exit reason.
2174 */
2175IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
2176{
2177 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2178 Assert(pVmcs);
2179
2180 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
2181 iemVmxVmexitSaveGuestSegRegs(pVCpu);
2182
2183 /*
2184 * Save guest RIP, RSP and RFLAGS.
2185 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
2186 *
2187 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
2188 * Callers must pass the instruction length in the VM-exit instruction length
2189 * field though it is undefined for such VM-exits. After updating RIP here, we clear
2190 * the VM-exit instruction length field.
2191 *
2192 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
2193 */
2194 if (HMVmxIsTrapLikeVmexit(uExitReason))
2195 {
2196 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
2197 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
2198 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2199 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
2200 }
2201
2202 /* We don't support enclave mode yet. */
2203 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
2204 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
2205 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
2206
2207 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
2208}
2209
2210
2211/**
2212 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
2213 *
2214 * @returns VBox status code.
2215 * @param pVCpu The cross context virtual CPU structure.
2216 * @param uExitReason The VM-exit reason (for diagnostic purposes).
2217 */
2218IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2219{
2220 /*
2221 * Save guest MSRs.
2222 * See Intel spec. 27.4 "Saving MSRs".
2223 */
2224 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2225 const char *const pszFailure = "VMX-abort";
2226
2227 /*
2228 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
2229 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
2230 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2231 */
2232 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
2233 if (!cMsrs)
2234 return VINF_SUCCESS;
2235
2236 /*
2237 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
2238 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2239 * implementation causes a VMX-abort followed by a triple-fault.
2240 */
2241 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2242 if (fIsMsrCountValid)
2243 { /* likely */ }
2244 else
2245 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
2246
2247 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2248 Assert(pMsr);
2249 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2250 {
2251 if ( !pMsr->u32Reserved
2252 && pMsr->u32Msr != MSR_IA32_SMBASE
2253 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2254 {
2255 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
2256 if (rcStrict == VINF_SUCCESS)
2257 continue;
2258
2259 /*
2260 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2261 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2262 * recording the MSR index in the auxiliary info. field and indicated further by our
2263 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2264 * if possible, or come up with a better, generic solution.
2265 */
2266 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2267 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2268 ? kVmxVDiag_Vmexit_MsrStoreRing3
2269 : kVmxVDiag_Vmexit_MsrStore;
2270 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2271 }
2272 else
2273 {
2274 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2275 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2276 }
2277 }
2278
2279 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2280 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2281 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), VMX_V_AUTOMSR_AREA_SIZE);
2282 if (RT_SUCCESS(rc))
2283 { /* likely */ }
2284 else
2285 {
2286 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2287 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2288 }
2289
2290 NOREF(uExitReason);
2291 NOREF(pszFailure);
2292 return VINF_SUCCESS;
2293}
2294
2295
2296/**
2297 * Performs a VMX abort (due to an fatal error during VM-exit).
2298 *
2299 * @returns Strict VBox status code.
2300 * @param pVCpu The cross context virtual CPU structure.
2301 * @param enmAbort The VMX abort reason.
2302 */
2303IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2304{
2305 /*
2306 * Perform the VMX abort.
2307 * See Intel spec. 27.7 "VMX Aborts".
2308 */
2309 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2310
2311 /* We don't support SMX yet. */
2312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2313 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2314 {
2315 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2316 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, u32VmxAbortId);
2317 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2318 }
2319
2320 return VINF_EM_TRIPLE_FAULT;
2321}
2322
2323
2324/**
2325 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2326 *
2327 * @param pVCpu The cross context virtual CPU structure.
2328 */
2329IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2330{
2331 /*
2332 * Load host control registers, debug registers and MSRs.
2333 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2334 */
2335 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2336 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2337
2338 /* CR0. */
2339 {
2340 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2341 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
2342 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2343 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2344 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2345 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2346 CPUMSetGuestCR0(pVCpu, uValidCr0);
2347 }
2348
2349 /* CR4. */
2350 {
2351 /* CR4 MB1 bits are not modified. */
2352 uint64_t const fCr4IgnMask = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
2353 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2354 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2355 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2356 if (fHostInLongMode)
2357 uValidCr4 |= X86_CR4_PAE;
2358 else
2359 uValidCr4 &= ~X86_CR4_PCIDE;
2360 CPUMSetGuestCR4(pVCpu, uValidCr4);
2361 }
2362
2363 /* CR3 (host value validated while checking host-state during VM-entry). */
2364 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2365
2366 /* DR7. */
2367 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2368
2369 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2370
2371 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2372 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2373 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2374 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2375
2376 /* FS, GS bases are loaded later while we load host segment registers. */
2377
2378 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2379 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2380 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2381 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2382 {
2383 if (fHostInLongMode)
2384 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2385 else
2386 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2387 }
2388
2389 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2390
2391 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2392 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2393 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2394
2395 /* We don't support IA32_BNDCFGS MSR yet. */
2396}
2397
2398
2399/**
2400 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2401 *
2402 * @param pVCpu The cross context virtual CPU structure.
2403 */
2404IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2405{
2406 /*
2407 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2408 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2409 *
2410 * Warning! Be careful to not touch fields that are reserved by VT-x,
2411 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2412 */
2413 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2414 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2415
2416 /* CS, SS, ES, DS, FS, GS. */
2417 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2418 {
2419 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2420 bool const fUnusable = RT_BOOL(HostSel == 0);
2421
2422 /* Selector. */
2423 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel = HostSel;
2424 pVCpu->cpum.GstCtx.aSRegs[iSegReg].ValidSel = HostSel;
2425 pVCpu->cpum.GstCtx.aSRegs[iSegReg].fFlags = CPUMSELREG_FLAGS_VALID;
2426
2427 /* Limit. */
2428 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u32Limit = 0xffffffff;
2429
2430 /* Base and Attributes. */
2431 switch (iSegReg)
2432 {
2433 case X86_SREG_CS:
2434 {
2435 pVCpu->cpum.GstCtx.cs.u64Base = 0;
2436 pVCpu->cpum.GstCtx.cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2437 pVCpu->cpum.GstCtx.ss.Attr.n.u1DescType = 1;
2438 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = 0;
2439 pVCpu->cpum.GstCtx.cs.Attr.n.u1Present = 1;
2440 pVCpu->cpum.GstCtx.cs.Attr.n.u1Long = fHostInLongMode;
2441 pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig = !fHostInLongMode;
2442 pVCpu->cpum.GstCtx.cs.Attr.n.u1Granularity = 1;
2443 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Unusable);
2444 Assert(!fUnusable);
2445 break;
2446 }
2447
2448 case X86_SREG_SS:
2449 case X86_SREG_ES:
2450 case X86_SREG_DS:
2451 {
2452 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base = 0;
2453 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2454 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DescType = 1;
2455 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u2Dpl = 0;
2456 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Present = 1;
2457 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DefBig = 1;
2458 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Granularity = 1;
2459 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable = fUnusable;
2460 break;
2461 }
2462
2463 case X86_SREG_FS:
2464 {
2465 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2466 pVCpu->cpum.GstCtx.fs.u64Base = !fUnusable ? pVmcs->u64HostFsBase.u : 0;
2467 pVCpu->cpum.GstCtx.fs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2468 pVCpu->cpum.GstCtx.fs.Attr.n.u1DescType = 1;
2469 pVCpu->cpum.GstCtx.fs.Attr.n.u2Dpl = 0;
2470 pVCpu->cpum.GstCtx.fs.Attr.n.u1Present = 1;
2471 pVCpu->cpum.GstCtx.fs.Attr.n.u1DefBig = 1;
2472 pVCpu->cpum.GstCtx.fs.Attr.n.u1Granularity = 1;
2473 pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable = fUnusable;
2474 break;
2475 }
2476
2477 case X86_SREG_GS:
2478 {
2479 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2480 pVCpu->cpum.GstCtx.gs.u64Base = !fUnusable ? pVmcs->u64HostGsBase.u : 0;
2481 pVCpu->cpum.GstCtx.gs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2482 pVCpu->cpum.GstCtx.gs.Attr.n.u1DescType = 1;
2483 pVCpu->cpum.GstCtx.gs.Attr.n.u2Dpl = 0;
2484 pVCpu->cpum.GstCtx.gs.Attr.n.u1Present = 1;
2485 pVCpu->cpum.GstCtx.gs.Attr.n.u1DefBig = 1;
2486 pVCpu->cpum.GstCtx.gs.Attr.n.u1Granularity = 1;
2487 pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable = fUnusable;
2488 break;
2489 }
2490 }
2491 }
2492
2493 /* TR. */
2494 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2495 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2496 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2497 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2498 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2499 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2500 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2501 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2502 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2503 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2504 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2505 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2506 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2507
2508 /* LDTR. */
2509 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2510 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2511 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2512 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
2513 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
2514 pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Unusable = 1;
2515
2516 /* GDTR. */
2517 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2518 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2519 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xfff;
2520
2521 /* IDTR.*/
2522 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2523 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2524 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xfff;
2525}
2526
2527
2528/**
2529 * Checks host PDPTes as part of VM-exit.
2530 *
2531 * @param pVCpu The cross context virtual CPU structure.
2532 * @param uExitReason The VM-exit reason (for logging purposes).
2533 */
2534IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2535{
2536 /*
2537 * Check host PDPTEs.
2538 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2539 */
2540 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2541 const char *const pszFailure = "VMX-abort";
2542 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2543
2544 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2545 && !fHostInLongMode)
2546 {
2547 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2548 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2549 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2550 if (RT_SUCCESS(rc))
2551 {
2552 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2553 {
2554 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2555 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2556 { /* likely */ }
2557 else
2558 {
2559 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2560 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2561 }
2562 }
2563 }
2564 else
2565 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2566 }
2567
2568 NOREF(pszFailure);
2569 NOREF(uExitReason);
2570 return VINF_SUCCESS;
2571}
2572
2573
2574/**
2575 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2576 *
2577 * @returns VBox status code.
2578 * @param pVCpu The cross context virtual CPU structure.
2579 * @param pszInstr The VMX instruction name (for logging purposes).
2580 */
2581IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2582{
2583 /*
2584 * Load host MSRs.
2585 * See Intel spec. 27.6 "Loading MSRs".
2586 */
2587 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2588 const char *const pszFailure = "VMX-abort";
2589
2590 /*
2591 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2592 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2593 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2594 */
2595 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2596 if (!cMsrs)
2597 return VINF_SUCCESS;
2598
2599 /*
2600 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2601 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2602 * implementation causes a VMX-abort followed by a triple-fault.
2603 */
2604 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2605 if (fIsMsrCountValid)
2606 { /* likely */ }
2607 else
2608 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2609
2610 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2611 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2612 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
2613 if (RT_SUCCESS(rc))
2614 {
2615 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2616 Assert(pMsr);
2617 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2618 {
2619 if ( !pMsr->u32Reserved
2620 && pMsr->u32Msr != MSR_K8_FS_BASE
2621 && pMsr->u32Msr != MSR_K8_GS_BASE
2622 && pMsr->u32Msr != MSR_K6_EFER
2623 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2625 {
2626 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2627 if (rcStrict == VINF_SUCCESS)
2628 continue;
2629
2630 /*
2631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2632 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2633 * recording the MSR index in the auxiliary info. field and indicated further by our
2634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2635 * if possible, or come up with a better, generic solution.
2636 */
2637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2639 ? kVmxVDiag_Vmexit_MsrLoadRing3
2640 : kVmxVDiag_Vmexit_MsrLoad;
2641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2642 }
2643 else
2644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2645 }
2646 }
2647 else
2648 {
2649 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2651 }
2652
2653 NOREF(uExitReason);
2654 NOREF(pszFailure);
2655 return VINF_SUCCESS;
2656}
2657
2658
2659/**
2660 * Loads the host state as part of VM-exit.
2661 *
2662 * @returns Strict VBox status code.
2663 * @param pVCpu The cross context virtual CPU structure.
2664 * @param uExitReason The VM-exit reason (for logging purposes).
2665 */
2666IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2667{
2668 /*
2669 * Load host state.
2670 * See Intel spec. 27.5 "Loading Host State".
2671 */
2672 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2673 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2674
2675 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2676 if ( CPUMIsGuestInLongMode(pVCpu)
2677 && !fHostInLongMode)
2678 {
2679 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2680 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2681 }
2682
2683 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2684 iemVmxVmexitLoadHostSegRegs(pVCpu);
2685
2686 /*
2687 * Load host RIP, RSP and RFLAGS.
2688 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2689 */
2690 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2691 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2692 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2693
2694 /* Update non-register state. */
2695 iemVmxVmexitRestoreForceFlags(pVCpu);
2696
2697 /* Clear address range monitoring. */
2698 EMMonitorWaitClear(pVCpu);
2699
2700 /* Perform the VMX transition (PGM updates). */
2701 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2702 if (rcStrict == VINF_SUCCESS)
2703 {
2704 /* Check host PDPTEs (only when we've fully switched page tables_. */
2705 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2706 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2707 if (RT_FAILURE(rc))
2708 {
2709 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2710 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2711 }
2712 }
2713 else if (RT_SUCCESS(rcStrict))
2714 {
2715 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2716 uExitReason));
2717 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2718 }
2719 else
2720 {
2721 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2722 return VBOXSTRICTRC_VAL(rcStrict);
2723 }
2724
2725 Assert(rcStrict == VINF_SUCCESS);
2726
2727 /* Load MSRs from the VM-exit auto-load MSR area. */
2728 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2729 if (RT_FAILURE(rc))
2730 {
2731 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2732 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2733 }
2734
2735 return rcStrict;
2736}
2737
2738
2739/**
2740 * VMX VM-exit handler.
2741 *
2742 * @returns Strict VBox status code.
2743 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2744 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2745 * triple-fault.
2746 *
2747 * @param pVCpu The cross context virtual CPU structure.
2748 * @param uExitReason The VM-exit reason.
2749 *
2750 * @remarks Make sure VM-exit qualification is updated before calling this
2751 * function!
2752 */
2753IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2754{
2755 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2756 Assert(pVmcs);
2757
2758 pVmcs->u32RoExitReason = uExitReason;
2759
2760 /** @todo NSTVMX: IEMGetCurrentXcpt will be VM-exit interruption info. */
2761 /** @todo NSTVMX: The source event should be recorded in IDT-vectoring info
2762 * during injection. */
2763
2764 /*
2765 * Save the guest state back into the VMCS.
2766 * We only need to save the state when the VM-entry was successful.
2767 */
2768 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2769 if (!fVmentryFailed)
2770 {
2771 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2772 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2773 if (RT_SUCCESS(rc))
2774 { /* likely */ }
2775 else
2776 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2777 }
2778
2779 /*
2780 * The high bits of the VM-exit reason are only relevant when the VM-exit occurs in
2781 * enclave mode/SMM which we don't support yet. If we ever add support for it, we can
2782 * pass just the lower bits, till then an assert should suffice.
2783 */
2784 Assert(!RT_HI_U16(uExitReason));
2785
2786 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2787 if (RT_FAILURE(rcStrict))
2788 LogFunc(("Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2789
2790 /* We're no longer in nested-guest execution mode. */
2791 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2792
2793 return rcStrict;
2794}
2795
2796
2797/**
2798 * VMX VM-exit handler for VM-exits due to instruction execution.
2799 *
2800 * This is intended for instructions where the caller provides all the relevant
2801 * VM-exit information.
2802 *
2803 * @returns Strict VBox status code.
2804 * @param pVCpu The cross context virtual CPU structure.
2805 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2806 */
2807DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2808{
2809 /*
2810 * For instructions where any of the following fields are not applicable:
2811 * - VM-exit instruction info. is undefined.
2812 * - VM-exit qualification must be cleared.
2813 * - VM-exit guest-linear address is undefined.
2814 * - VM-exit guest-physical address is undefined.
2815 *
2816 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2817 * instruction execution. For VM-exits that are not due to instruction execution this
2818 * field is undefined.
2819 *
2820 * In our implementation in IEM, all undefined fields are generally cleared. However,
2821 * if the caller supplies information (from say the physical CPU directly) it is
2822 * then possible that the undefined fields not cleared.
2823 *
2824 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2825 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2826 */
2827 Assert(pExitInfo);
2828 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2829 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2830 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2831
2832 /* Update all the relevant fields from the VM-exit instruction information struct. */
2833 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2834 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2835 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2836 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2837 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2838
2839 /* Perform the VM-exit. */
2840 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2841}
2842
2843
2844/**
2845 * VMX VM-exit handler for VM-exits due to instruction execution.
2846 *
2847 * This is intended for instructions that only provide the VM-exit instruction
2848 * length.
2849 *
2850 * @param pVCpu The cross context virtual CPU structure.
2851 * @param uExitReason The VM-exit reason.
2852 * @param cbInstr The instruction length in bytes.
2853 */
2854IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2855{
2856 VMXVEXITINFO ExitInfo;
2857 RT_ZERO(ExitInfo);
2858 ExitInfo.uReason = uExitReason;
2859 ExitInfo.cbInstr = cbInstr;
2860
2861#ifdef VBOX_STRICT
2862 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2863 switch (uExitReason)
2864 {
2865 case VMX_EXIT_INVEPT:
2866 case VMX_EXIT_INVPCID:
2867 case VMX_EXIT_LDTR_TR_ACCESS:
2868 case VMX_EXIT_GDTR_IDTR_ACCESS:
2869 case VMX_EXIT_VMCLEAR:
2870 case VMX_EXIT_VMPTRLD:
2871 case VMX_EXIT_VMPTRST:
2872 case VMX_EXIT_VMREAD:
2873 case VMX_EXIT_VMWRITE:
2874 case VMX_EXIT_VMXON:
2875 case VMX_EXIT_XRSTORS:
2876 case VMX_EXIT_XSAVES:
2877 case VMX_EXIT_RDRAND:
2878 case VMX_EXIT_RDSEED:
2879 case VMX_EXIT_IO_INSTR:
2880 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2881 break;
2882 }
2883#endif
2884
2885 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2886}
2887
2888
2889/**
2890 * VMX VM-exit handler for VM-exits due to instruction execution.
2891 *
2892 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2893 * instruction information and VM-exit qualification fields.
2894 *
2895 * @param pVCpu The cross context virtual CPU structure.
2896 * @param uExitReason The VM-exit reason.
2897 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2898 * @param cbInstr The instruction length in bytes.
2899 *
2900 * @remarks Do not use this for INS/OUTS instruction.
2901 */
2902IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2903{
2904 VMXVEXITINFO ExitInfo;
2905 RT_ZERO(ExitInfo);
2906 ExitInfo.uReason = uExitReason;
2907 ExitInfo.cbInstr = cbInstr;
2908
2909 /*
2910 * Update the VM-exit qualification field with displacement bytes.
2911 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2912 */
2913 switch (uExitReason)
2914 {
2915 case VMX_EXIT_INVEPT:
2916 case VMX_EXIT_INVPCID:
2917 case VMX_EXIT_LDTR_TR_ACCESS:
2918 case VMX_EXIT_GDTR_IDTR_ACCESS:
2919 case VMX_EXIT_VMCLEAR:
2920 case VMX_EXIT_VMPTRLD:
2921 case VMX_EXIT_VMPTRST:
2922 case VMX_EXIT_VMREAD:
2923 case VMX_EXIT_VMWRITE:
2924 case VMX_EXIT_VMXON:
2925 case VMX_EXIT_XRSTORS:
2926 case VMX_EXIT_XSAVES:
2927 case VMX_EXIT_RDRAND:
2928 case VMX_EXIT_RDSEED:
2929 {
2930 /* Construct the VM-exit instruction information. */
2931 RTGCPTR GCPtrDisp;
2932 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2933
2934 /* Update the VM-exit instruction information. */
2935 ExitInfo.InstrInfo.u = uInstrInfo;
2936
2937 /* Update the VM-exit qualification. */
2938 ExitInfo.u64Qual = GCPtrDisp;
2939 break;
2940 }
2941
2942 default:
2943 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2944 break;
2945 }
2946
2947 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2948}
2949
2950
2951/**
2952 * Checks whether an I/O instruction for the given port is intercepted (causes a
2953 * VM-exit) or not.
2954 *
2955 * @returns @c true if the instruction is intercepted, @c false otherwise.
2956 * @param pVCpu The cross context virtual CPU structure.
2957 * @param u16Port The I/O port being accessed by the instruction.
2958 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2959 */
2960IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2961{
2962 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2963 Assert(pVmcs);
2964
2965 /*
2966 * Check whether the I/O instruction must cause a VM-exit or not.
2967 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2968 */
2969 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
2970 return true;
2971
2972 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
2973 {
2974 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
2975 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
2976 Assert(pbIoBitmapA);
2977 Assert(pbIoBitmapB);
2978 return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
2979 }
2980
2981 return false;
2982}
2983
2984
2985/**
2986 * VMX VM-exit handler for VM-exits due to INVLPG.
2987 *
2988 * @param pVCpu The cross context virtual CPU structure.
2989 * @param GCPtrPage The guest-linear address of the page being invalidated.
2990 * @param cbInstr The instruction length in bytes.
2991 */
2992IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2993{
2994 VMXVEXITINFO ExitInfo;
2995 RT_ZERO(ExitInfo);
2996 ExitInfo.uReason = VMX_EXIT_INVLPG;
2997 ExitInfo.cbInstr = cbInstr;
2998 ExitInfo.u64Qual = GCPtrPage;
2999 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3000
3001 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3002}
3003
3004
3005/**
3006 * VMX VM-exit handler for VM-exits due to LMSW.
3007 *
3008 * @returns Strict VBox status code.
3009 * @param pVCpu The cross context virtual CPU structure.
3010 * @param uGuestCr0 The current guest CR0.
3011 * @param pu16NewMsw The machine-status word specified in LMSW's source
3012 * operand. This will be updated depending on the VMX
3013 * guest/host CR0 mask if LMSW is not intercepted.
3014 * @param GCPtrEffDst The guest-linear address of the source operand in case
3015 * of a memory operand. For register operand, pass
3016 * NIL_RTGCPTR.
3017 * @param cbInstr The instruction length in bytes.
3018 */
3019IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3020 uint8_t cbInstr)
3021{
3022 /*
3023 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3024 *
3025 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3026 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3027 */
3028 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3029 Assert(pVmcs);
3030 Assert(pu16NewMsw);
3031
3032 bool fIntercept = false;
3033 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3034 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3035
3036 /*
3037 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3038 * CR0.PE case first, before the rest of the bits in the MSW.
3039 *
3040 * If CR0.PE is owned by the host and CR0.PE differs between the
3041 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3042 */
3043 if ( (fGstHostMask & X86_CR0_PE)
3044 && (*pu16NewMsw & X86_CR0_PE)
3045 && !(fReadShadow & X86_CR0_PE))
3046 fIntercept = true;
3047
3048 /*
3049 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3050 * bits differ between the MSW (source operand) and the read-shadow, we must
3051 * cause a VM-exit.
3052 */
3053 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3054 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3055 fIntercept = true;
3056
3057 if (fIntercept)
3058 {
3059 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3060
3061 VMXVEXITINFO ExitInfo;
3062 RT_ZERO(ExitInfo);
3063 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3064 ExitInfo.cbInstr = cbInstr;
3065
3066 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3067 if (fMemOperand)
3068 {
3069 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3070 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3071 }
3072
3073 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3074 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3075 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3076 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3077
3078 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3079 }
3080
3081 /*
3082 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3083 * CR0 guest/host mask must be left unmodified.
3084 *
3085 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3086 */
3087 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3088 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3089
3090 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3091}
3092
3093
3094/**
3095 * VMX VM-exit handler for VM-exits due to CLTS.
3096 *
3097 * @returns Strict VBox status code.
3098 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3099 * VM-exit but must not modify the guest CR0.TS bit.
3100 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3101 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3102 * CR0 fixed bits in VMX operation).
3103 * @param pVCpu The cross context virtual CPU structure.
3104 * @param cbInstr The instruction length in bytes.
3105 */
3106IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3107{
3108 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3109 Assert(pVmcs);
3110
3111 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3112 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3113
3114 /*
3115 * If CR0.TS is owned by the host:
3116 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3117 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3118 * CLTS instruction completes without clearing CR0.TS.
3119 *
3120 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3121 */
3122 if (fGstHostMask & X86_CR0_TS)
3123 {
3124 if (fReadShadow & X86_CR0_TS)
3125 {
3126 Log2(("clts: Guest intercept -> VM-exit\n"));
3127
3128 VMXVEXITINFO ExitInfo;
3129 RT_ZERO(ExitInfo);
3130 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3131 ExitInfo.cbInstr = cbInstr;
3132
3133 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3134 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3135 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3136 }
3137
3138 return VINF_VMX_MODIFIES_BEHAVIOR;
3139 }
3140
3141 /*
3142 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3143 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3144 */
3145 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3146}
3147
3148
3149/**
3150 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3151 * (CR0/CR4 write).
3152 *
3153 * @returns Strict VBox status code.
3154 * @param pVCpu The cross context virtual CPU structure.
3155 * @param iCrReg The control register (either CR0 or CR4).
3156 * @param uGuestCrX The current guest CR0/CR4.
3157 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3158 * if no VM-exit is caused.
3159 * @param iGReg The general register from which the CR0/CR4 value is
3160 * being loaded.
3161 * @param cbInstr The instruction length in bytes.
3162 */
3163IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3164 uint8_t cbInstr)
3165{
3166 Assert(puNewCrX);
3167 Assert(iCrReg == 0 || iCrReg == 4);
3168
3169 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3170 Assert(pVmcs);
3171
3172 uint64_t uGuestCrX;
3173 uint64_t fGstHostMask;
3174 uint64_t fReadShadow;
3175 if (iCrReg == 0)
3176 {
3177 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3178 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3179 fGstHostMask = pVmcs->u64Cr0Mask.u;
3180 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3181 }
3182 else
3183 {
3184 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3185 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3186 fGstHostMask = pVmcs->u64Cr4Mask.u;
3187 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3188 }
3189
3190 /*
3191 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3192 * corresponding bits differ between the source operand and the read-shadow,
3193 * we must cause a VM-exit.
3194 *
3195 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3196 */
3197 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3198 {
3199 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3200
3201 VMXVEXITINFO ExitInfo;
3202 RT_ZERO(ExitInfo);
3203 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3204 ExitInfo.cbInstr = cbInstr;
3205
3206 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3207 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3208 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3209 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3210 }
3211
3212 /*
3213 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3214 * must not be modified the instruction.
3215 *
3216 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3217 */
3218 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3219
3220 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3221}
3222
3223
3224/**
3225 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3226 *
3227 * @returns VBox strict status code.
3228 * @param pVCpu The cross context virtual CPU structure.
3229 * @param iGReg The general register to which the CR3 value is being stored.
3230 * @param cbInstr The instruction length in bytes.
3231 */
3232IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3233{
3234 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3235 Assert(pVmcs);
3236 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3237
3238 /*
3239 * If the CR3-store exiting control is set, we must cause a VM-exit.
3240 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3241 */
3242 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3243 {
3244 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3245
3246 VMXVEXITINFO ExitInfo;
3247 RT_ZERO(ExitInfo);
3248 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3249 ExitInfo.cbInstr = cbInstr;
3250
3251 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3252 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3254 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3255 }
3256
3257 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3258}
3259
3260
3261/**
3262 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3263 *
3264 * @returns VBox strict status code.
3265 * @param pVCpu The cross context virtual CPU structure.
3266 * @param uNewCr3 The new CR3 value.
3267 * @param iGReg The general register from which the CR3 value is being
3268 * loaded.
3269 * @param cbInstr The instruction length in bytes.
3270 */
3271IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3272{
3273 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3274 Assert(pVmcs);
3275
3276 /*
3277 * If the CR3-load exiting control is set and the new CR3 value does not
3278 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3279 *
3280 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3281 */
3282 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3283 {
3284 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3285 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3286
3287 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3288 {
3289 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3290 if (uNewCr3 != uCr3TargetValue)
3291 {
3292 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3293
3294 VMXVEXITINFO ExitInfo;
3295 RT_ZERO(ExitInfo);
3296 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3297 ExitInfo.cbInstr = cbInstr;
3298
3299 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3300 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3301 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3302 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3303 }
3304 }
3305 }
3306
3307 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3308}
3309
3310
3311/**
3312 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3313 *
3314 * @returns VBox strict status code.
3315 * @param pVCpu The cross context virtual CPU structure.
3316 * @param iGReg The general register to which the CR8 value is being stored.
3317 * @param cbInstr The instruction length in bytes.
3318 */
3319IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3320{
3321 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3322 Assert(pVmcs);
3323
3324 /*
3325 * If the CR8-store exiting control is set, we must cause a VM-exit.
3326 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3327 */
3328 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3329 {
3330 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3331
3332 VMXVEXITINFO ExitInfo;
3333 RT_ZERO(ExitInfo);
3334 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3335 ExitInfo.cbInstr = cbInstr;
3336
3337 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3338 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3339 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3340 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3341 }
3342
3343 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3344}
3345
3346
3347/**
3348 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3349 *
3350 * @returns VBox strict status code.
3351 * @param pVCpu The cross context virtual CPU structure.
3352 * @param iGReg The general register from which the CR8 value is being
3353 * loaded.
3354 * @param cbInstr The instruction length in bytes.
3355 */
3356IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3357{
3358 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3359 Assert(pVmcs);
3360
3361 /*
3362 * If the CR8-load exiting control is set, we must cause a VM-exit.
3363 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3364 */
3365 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3366 {
3367 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3368
3369 VMXVEXITINFO ExitInfo;
3370 RT_ZERO(ExitInfo);
3371 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3372 ExitInfo.cbInstr = cbInstr;
3373
3374 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3375 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3376 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3377 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3378 }
3379
3380 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3381}
3382
3383
3384/**
3385 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3386 * GReg,DRx' (DRx read).
3387 *
3388 * @returns VBox strict status code.
3389 * @param pVCpu The cross context virtual CPU structure.
3390 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3391 * VMXINSTRID_MOV_FROM_DRX).
3392 * @param iDrReg The debug register being accessed.
3393 * @param iGReg The general register to/from which the DRx value is being
3394 * store/loaded.
3395 * @param cbInstr The instruction length in bytes.
3396 */
3397IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3398 uint8_t cbInstr)
3399{
3400 Assert(iDrReg <= 7);
3401 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3402
3403 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3404 Assert(pVmcs);
3405
3406 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3407 {
3408 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3409 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3410 VMXVEXITINFO ExitInfo;
3411 RT_ZERO(ExitInfo);
3412 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3413 ExitInfo.cbInstr = cbInstr;
3414 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3415 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3416 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3417 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3418 }
3419
3420 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3421}
3422
3423
3424/**
3425 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3426 *
3427 * @returns VBox strict status code.
3428 * @param pVCpu The cross context virtual CPU structure.
3429 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3430 * VMXINSTRID_IO_OUT).
3431 * @param u16Port The I/O port being accessed.
3432 * @param fImm Whether the I/O port was encoded using an immediate operand
3433 * or the implicit DX register.
3434 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3435 * @param cbInstr The instruction length in bytes.
3436 */
3437IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3438 uint8_t cbInstr)
3439{
3440 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3441 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3442
3443 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3444 if (fIntercept)
3445 {
3446 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3447 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3448 VMXVEXITINFO ExitInfo;
3449 RT_ZERO(ExitInfo);
3450 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3451 ExitInfo.cbInstr = cbInstr;
3452 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3453 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3454 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3455 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3456 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3457 }
3458
3459 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3460}
3461
3462
3463/**
3464 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3465 *
3466 * @returns VBox strict status code.
3467 * @param pVCpu The cross context virtual CPU structure.
3468 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3469 * VMXINSTRID_IO_OUTS).
3470 * @param u16Port The I/O port being accessed.
3471 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3472 * @param fRep Whether the instruction has a REP prefix or not.
3473 * @param ExitInstrInfo The VM-exit instruction info. field.
3474 * @param cbInstr The instruction length in bytes.
3475 */
3476IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3477 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3478{
3479 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3480 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3481 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3482 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3483 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3484
3485 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3486 if (fIntercept)
3487 {
3488 /*
3489 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3490 */
3491 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3492 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3493 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3494 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3495 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3496
3497 uint32_t uDirection;
3498 uint64_t uGuestLinearAddr;
3499 if (uInstrId == VMXINSTRID_IO_INS)
3500 {
3501 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3502 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3503 }
3504 else
3505 {
3506 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3507 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3508 }
3509
3510 /*
3511 * If the segment is ununsable, the guest-linear address in undefined.
3512 * We shall clear it for consistency.
3513 *
3514 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3515 */
3516 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3517 uGuestLinearAddr = 0;
3518
3519 VMXVEXITINFO ExitInfo;
3520 RT_ZERO(ExitInfo);
3521 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3522 ExitInfo.cbInstr = cbInstr;
3523 ExitInfo.InstrInfo = ExitInstrInfo;
3524 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3525 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3526 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3527 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3528 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3529 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3530 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3531 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3532 }
3533
3534 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3535}
3536
3537
3538/**
3539 * VMX VM-exit handler for VM-exits due to MWAIT.
3540 *
3541 * @returns VBox strict status code.
3542 * @param pVCpu The cross context virtual CPU structure.
3543 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3544 * @param cbInstr The instruction length in bytes.
3545 */
3546IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3547{
3548 VMXVEXITINFO ExitInfo;
3549 RT_ZERO(ExitInfo);
3550 ExitInfo.uReason = VMX_EXIT_MWAIT;
3551 ExitInfo.cbInstr = cbInstr;
3552 ExitInfo.u64Qual = fMonitorHwArmed;
3553 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3554}
3555
3556
3557/**
3558 * VMX VM-exit handler for VM-exits due to PAUSE.
3559 *
3560 * @returns VBox strict status code.
3561 * @param pVCpu The cross context virtual CPU structure.
3562 * @param cbInstr The instruction length in bytes.
3563 */
3564IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3565{
3566 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3567 Assert(pVmcs);
3568
3569 /*
3570 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3571 * "PAUSE-loop exiting" control.
3572 *
3573 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3574 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3575 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3576 * a VM-exit.
3577 *
3578 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3579 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3580 */
3581 bool fIntercept = false;
3582 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3583 fIntercept = true;
3584 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3585 && pVCpu->iem.s.uCpl == 0)
3586 {
3587 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3588
3589 /*
3590 * A previous-PAUSE-tick value of 0 is used to identify the first time
3591 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3592 * consider this to be the first execution of PAUSE in a loop according
3593 * to the Intel.
3594 *
3595 * All subsequent records for the previous-PAUSE-tick we ensure that it
3596 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3597 */
3598 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3599 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3600 uint64_t const uTick = TMCpuTickGet(pVCpu);
3601 uint32_t const uPleGap = pVmcs->u32PleGap;
3602 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3603 if ( *puPrevPauseTick == 0
3604 || uTick - *puPrevPauseTick > uPleGap)
3605 *puFirstPauseLoopTick = uTick;
3606 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3607 fIntercept = true;
3608
3609 *puPrevPauseTick = uTick | 1;
3610 }
3611
3612 if (fIntercept)
3613 {
3614 VMXVEXITINFO ExitInfo;
3615 RT_ZERO(ExitInfo);
3616 ExitInfo.uReason = VMX_EXIT_PAUSE;
3617 ExitInfo.cbInstr = cbInstr;
3618 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3619 }
3620
3621 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3622}
3623
3624
3625/**
3626 * VMX VM-exit handler for VM-exits due to task switches.
3627 *
3628 * @returns VBox strict status code.
3629 * @param pVCpu The cross context virtual CPU structure.
3630 * @param enmTaskSwitch The cause of the task switch.
3631 * @param SelNewTss The selector of the new TSS.
3632 * @param cbInstr The instruction length in bytes.
3633 */
3634IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3635{
3636 /*
3637 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3638 *
3639 * If the the cause of the task switch is due to execution of CALL, IRET or the JMP
3640 * instruction or delivery of the exception generated by one of these instructions
3641 * lead to a task switch through a task gate in the IDT, we need to provide the
3642 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3643 * leaves the VM-exit instruction length field undefined.
3644 *
3645 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3646 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3647 */
3648 Assert(cbInstr <= 15);
3649
3650 uint8_t uType;
3651 switch (enmTaskSwitch)
3652 {
3653 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3654 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3655 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3656 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3657 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3658 }
3659
3660 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3661 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3662 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3663 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3664 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3665}
3666
3667
3668/**
3669 * VMX VM-exit handler for VM-exits due to external interrupts.
3670 *
3671 * @returns VBox strict status code.
3672 * @param pVCpu The cross context virtual CPU structure.
3673 * @param uVector The external interrupt vector.
3674 * @param fIntPending Whether the external interrupt is pending or
3675 * acknowdledged in the interrupt controller.
3676 */
3677IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3678{
3679 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3680 Assert(pVmcs);
3681
3682 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3683 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3684 {
3685 if (fIntPending)
3686 {
3687 /*
3688 * If the interrupt is pending and we don't need to acknowledge the
3689 * interrupt on VM-exit, cause the VM-exit immediately.
3690 *
3691 * See Intel spec 25.2 "Other Causes Of VM Exits".
3692 */
3693 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3694 {
3695 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3696 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3697 iemVmxVmcsSetExitQual(pVCpu, 0);
3698 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3699 }
3700
3701 /*
3702 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3703 * on VM-exit, postpone VM-exit til after the interrupt controller has been
3704 * acknowledged that the interrupt has been consumed.
3705 */
3706 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3707 }
3708
3709 /*
3710 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3711 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3712 * all set, we cause the VM-exit now. We need to record the external interrupt that
3713 * just occurred in the VM-exit interruption information field.
3714 *
3715 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3716 */
3717 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3718 {
3719 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3720 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3721 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3722 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3723 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3724 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3725 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3726 iemVmxVmcsSetExitQual(pVCpu, 0);
3727 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3728 }
3729 }
3730
3731 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3732}
3733
3734
3735/**
3736 * VMX VM-exit handler for interrupt-window VM-exits.
3737 *
3738 * @returns VBox strict status code.
3739 * @param pVCpu The cross context virtual CPU structure.
3740 */
3741IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3742{
3743 iemVmxVmcsSetExitQual(pVCpu, 0);
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3745}
3746
3747
3748/**
3749 * VMX VM-exit handler for VM-exits due to delivery of an event.
3750 *
3751 * @returns VBox strict status code.
3752 * @param pVCpu The cross context virtual CPU structure.
3753 * @param uVector The interrupt / exception vector.
3754 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3755 * @param uErrCode The error code associated with the event.
3756 * @param uCr2 The CR2 value in case of a \#PF exception.
3757 * @param cbInstr The instruction length in bytes.
3758 */
3759IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3760 uint8_t cbInstr)
3761{
3762 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3763 Assert(pVmcs);
3764
3765 /*
3766 * If the event is being injected as part of VM-entry, it isn't subject to event
3767 * intercepts in the nested-guest. However, secondary exceptions that occur during
3768 * injection of any event -are- subject to event interception.
3769 *
3770 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3771 */
3772 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3773 {
3774 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3775 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3776 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3777 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3778 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3779 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3780 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3781 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3782 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3783
3784 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3785 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3786 }
3787
3788 /*
3789 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3790 * If not, the caller will continue delivery of the external interrupt as it would
3791 * normally.
3792 */
3793 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3794 {
3795 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3796 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3797 }
3798
3799 /*
3800 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3801 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3802 */
3803 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3804 bool fIntercept = false;
3805 bool fIsHwXcpt = false;
3806 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3807 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3808 {
3809 fIsHwXcpt = true;
3810 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3811 if (uVector == X86_XCPT_NMI)
3812 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3813 else
3814 {
3815 /* Page-faults are subject to masking using its error code. */
3816 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3817 if (uVector == X86_XCPT_PF)
3818 {
3819 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
3820 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
3821 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
3822 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
3823 }
3824
3825 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
3826 if (fXcptBitmap & RT_BIT(uVector))
3827 fIntercept = true;
3828 }
3829 }
3830 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3831
3832 /*
3833 * Now that we've determined whether the software interrupt or hardware exception
3834 * causes a VM-exit, we need to construct the relevant VM-exit information and
3835 * cause the VM-exit.
3836 */
3837 if (fIntercept)
3838 {
3839 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3840
3841 /* Construct the rest of the event related information fields and cause the VM-exit. */
3842 uint64_t uExitQual = 0;
3843 if (fIsHwXcpt)
3844 {
3845 if (uVector == X86_XCPT_PF)
3846 uExitQual = uCr2;
3847 else if (uVector == X86_XCPT_DB)
3848 {
3849 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
3850 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3851 }
3852 }
3853
3854 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3855 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3856 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3857 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3858 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3859 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3860 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3861 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3862 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3863 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3864 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3865
3866 /*
3867 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
3868 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3869 * length.
3870 */
3871 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3872 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3873 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3874 else
3875 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3876
3877 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3878 }
3879
3880 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3881}
3882
3883
3884/**
3885 * VMX VM-exit handler for VM-exits due to a triple fault.
3886 *
3887 * @returns VBox strict status code.
3888 * @param pVCpu The cross context virtual CPU structure.
3889 */
3890IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3891{
3892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3893 Assert(pVmcs);
3894 iemVmxVmcsSetExitQual(pVCpu, 0);
3895 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
3896}
3897
3898
3899/**
3900 * VMX VM-exit handler for TPR virtualization.
3901 *
3902 * @returns VBox strict status code.
3903 * @param pVCpu The cross context virtual CPU structure.
3904 * @param cbInstr The instruction length in bytes.
3905 */
3906IEM_STATIC VBOXSTRICTRC iemVmxVmexitTprVirtualization(PVMCPU pVCpu, uint8_t cbInstr)
3907{
3908 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3909 Assert(pVmcs);
3910
3911 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
3912 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)); /* We don't support virtual-interrupt delivery yet. */
3913
3914 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
3915 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
3916
3917 /*
3918 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
3919 * See Intel spec. 29.1.2 "TPR Virtualization".
3920 */
3921 if (((uVTpr >> 4) & 0xf) < uTprThreshold)
3922 {
3923 Log2(("tpr_virt: uVTpr=%u uTprThreshold=%u -> VM-exit\n", uVTpr, uTprThreshold));
3924
3925 /*
3926 * This is a trap-like VM-exit. We pass the instruction length along in the VM-exit
3927 * instruction length field and let the VM-exit handler update the RIP when appropriate.
3928 * It will then clear the VM-exit instruction length field before completing the VM-exit.
3929 *
3930 * The VM-exit qualification must be cleared.
3931 */
3932 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3933 iemVmxVmcsSetExitQual(pVCpu, 0);
3934 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
3935 }
3936
3937 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3938}
3939
3940
3941/**
3942 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
3943 *
3944 * @param pVCpu The cross context virtual CPU structure.
3945 * @param pszInstr The VMX instruction name (for logging purposes).
3946 */
3947IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
3948{
3949 /*
3950 * Guest Control Registers, Debug Registers, and MSRs.
3951 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
3952 */
3953 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3954 const char *const pszFailure = "VM-exit";
3955 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
3956
3957 /* CR0 reserved bits. */
3958 {
3959 /* CR0 MB1 bits. */
3960 uint64_t u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
3961 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
3962 if (fUnrestrictedGuest)
3963 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
3964 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
3965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
3966
3967 /* CR0 MBZ bits. */
3968 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
3969 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
3970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
3971
3972 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
3973 if ( !fUnrestrictedGuest
3974 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
3975 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
3976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
3977 }
3978
3979 /* CR4 reserved bits. */
3980 {
3981 /* CR4 MB1 bits. */
3982 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
3983 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
3984 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
3985
3986 /* CR4 MBZ bits. */
3987 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
3988 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
3989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
3990 }
3991
3992 /* DEBUGCTL MSR. */
3993 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
3994 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
3995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
3996
3997 /* 64-bit CPU checks. */
3998 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
3999 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4000 {
4001 if (fGstInLongMode)
4002 {
4003 /* PAE must be set. */
4004 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4005 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4006 { /* likely */ }
4007 else
4008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4009 }
4010 else
4011 {
4012 /* PCIDE should not be set. */
4013 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4014 { /* likely */ }
4015 else
4016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4017 }
4018
4019 /* CR3. */
4020 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4021 { /* likely */ }
4022 else
4023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4024
4025 /* DR7. */
4026 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4027 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4029
4030 /* SYSENTER ESP and SYSENTER EIP. */
4031 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4032 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4033 { /* likely */ }
4034 else
4035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4036 }
4037
4038 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4039 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4040
4041 /* PAT MSR. */
4042 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4043 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4044 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4045
4046 /* EFER MSR. */
4047 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4048 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4049 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4050 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4051
4052 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
4053 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
4054 if ( fGstInLongMode == fGstLma
4055 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4056 || fGstLma == fGstLme))
4057 { /* likely */ }
4058 else
4059 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4060
4061 /* We don't support IA32_BNDCFGS MSR yet. */
4062 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4063
4064 NOREF(pszInstr);
4065 NOREF(pszFailure);
4066 return VINF_SUCCESS;
4067}
4068
4069
4070/**
4071 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4072 *
4073 * @param pVCpu The cross context virtual CPU structure.
4074 * @param pszInstr The VMX instruction name (for logging purposes).
4075 */
4076IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4077{
4078 /*
4079 * Segment registers.
4080 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4081 */
4082 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4083 const char *const pszFailure = "VM-exit";
4084 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4085 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4086 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4087
4088 /* Selectors. */
4089 if ( !fGstInV86Mode
4090 && !fUnrestrictedGuest
4091 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4093
4094 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4095 {
4096 CPUMSELREG SelReg;
4097 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4098 if (RT_LIKELY(rc == VINF_SUCCESS))
4099 { /* likely */ }
4100 else
4101 return rc;
4102
4103 /*
4104 * Virtual-8086 mode checks.
4105 */
4106 if (fGstInV86Mode)
4107 {
4108 /* Base address. */
4109 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4110 { /* likely */ }
4111 else
4112 {
4113 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4115 }
4116
4117 /* Limit. */
4118 if (SelReg.u32Limit == 0xffff)
4119 { /* likely */ }
4120 else
4121 {
4122 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4124 }
4125
4126 /* Attribute. */
4127 if (SelReg.Attr.u == 0xf3)
4128 { /* likely */ }
4129 else
4130 {
4131 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4133 }
4134
4135 /* We're done; move to checking the next segment. */
4136 continue;
4137 }
4138
4139 /* Checks done by 64-bit CPUs. */
4140 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4141 {
4142 /* Base address. */
4143 if ( iSegReg == X86_SREG_FS
4144 || iSegReg == X86_SREG_GS)
4145 {
4146 if (X86_IS_CANONICAL(SelReg.u64Base))
4147 { /* likely */ }
4148 else
4149 {
4150 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4152 }
4153 }
4154 else if (iSegReg == X86_SREG_CS)
4155 {
4156 if (!RT_HI_U32(SelReg.u64Base))
4157 { /* likely */ }
4158 else
4159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4160 }
4161 else
4162 {
4163 if ( SelReg.Attr.n.u1Unusable
4164 || !RT_HI_U32(SelReg.u64Base))
4165 { /* likely */ }
4166 else
4167 {
4168 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4170 }
4171 }
4172 }
4173
4174 /*
4175 * Checks outside Virtual-8086 mode.
4176 */
4177 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4178 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4179 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4180 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4181 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4182 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4183 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4184 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4185
4186 /* Code or usable segment. */
4187 if ( iSegReg == X86_SREG_CS
4188 || fUsable)
4189 {
4190 /* Reserved bits (bits 31:17 and bits 11:8). */
4191 if (!(SelReg.Attr.u & 0xfffe0f00))
4192 { /* likely */ }
4193 else
4194 {
4195 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4197 }
4198
4199 /* Descriptor type. */
4200 if (fCodeDataSeg)
4201 { /* likely */ }
4202 else
4203 {
4204 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
4205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4206 }
4207
4208 /* Present. */
4209 if (fPresent)
4210 { /* likely */ }
4211 else
4212 {
4213 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
4214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4215 }
4216
4217 /* Granularity. */
4218 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
4219 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
4220 { /* likely */ }
4221 else
4222 {
4223 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
4224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4225 }
4226 }
4227
4228 if (iSegReg == X86_SREG_CS)
4229 {
4230 /* Segment Type and DPL. */
4231 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4232 && fUnrestrictedGuest)
4233 {
4234 if (uDpl == 0)
4235 { /* likely */ }
4236 else
4237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
4238 }
4239 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4240 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4241 {
4242 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4243 if (uDpl == AttrSs.n.u2Dpl)
4244 { /* likely */ }
4245 else
4246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
4247 }
4248 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4249 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4250 {
4251 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4252 if (uDpl <= AttrSs.n.u2Dpl)
4253 { /* likely */ }
4254 else
4255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
4256 }
4257 else
4258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
4259
4260 /* Def/Big. */
4261 if ( fGstInLongMode
4262 && fSegLong)
4263 {
4264 if (uDefBig == 0)
4265 { /* likely */ }
4266 else
4267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
4268 }
4269 }
4270 else if (iSegReg == X86_SREG_SS)
4271 {
4272 /* Segment Type. */
4273 if ( !fUsable
4274 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4275 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
4276 { /* likely */ }
4277 else
4278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
4279
4280 /* DPL. */
4281 if (fUnrestrictedGuest)
4282 {
4283 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
4284 { /* likely */ }
4285 else
4286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
4287 }
4288 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4289 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4290 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
4291 {
4292 if (uDpl == 0)
4293 { /* likely */ }
4294 else
4295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
4296 }
4297 }
4298 else
4299 {
4300 /* DS, ES, FS, GS. */
4301 if (fUsable)
4302 {
4303 /* Segment type. */
4304 if (uSegType & X86_SEL_TYPE_ACCESSED)
4305 { /* likely */ }
4306 else
4307 {
4308 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
4309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4310 }
4311
4312 if ( !(uSegType & X86_SEL_TYPE_CODE)
4313 || (uSegType & X86_SEL_TYPE_READ))
4314 { /* likely */ }
4315 else
4316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
4317
4318 /* DPL. */
4319 if ( !fUnrestrictedGuest
4320 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4321 {
4322 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
4323 { /* likely */ }
4324 else
4325 {
4326 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
4327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4328 }
4329 }
4330 }
4331 }
4332 }
4333
4334 /*
4335 * LDTR.
4336 */
4337 {
4338 CPUMSELREG Ldtr;
4339 Ldtr.Sel = pVmcs->GuestLdtr;
4340 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
4341 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
4342 Ldtr.Attr.u = pVmcs->u32GuestLdtrLimit;
4343
4344 if (!Ldtr.Attr.n.u1Unusable)
4345 {
4346 /* Selector. */
4347 if (!(Ldtr.Sel & X86_SEL_LDT))
4348 { /* likely */ }
4349 else
4350 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
4351
4352 /* Base. */
4353 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4354 {
4355 if (X86_IS_CANONICAL(Ldtr.u64Base))
4356 { /* likely */ }
4357 else
4358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
4359 }
4360
4361 /* Attributes. */
4362 /* Reserved bits (bits 31:17 and bits 11:8). */
4363 if (!(Ldtr.Attr.u & 0xfffe0f00))
4364 { /* likely */ }
4365 else
4366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
4367
4368 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
4369 { /* likely */ }
4370 else
4371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
4372
4373 if (!Ldtr.Attr.n.u1DescType)
4374 { /* likely */ }
4375 else
4376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
4377
4378 if (Ldtr.Attr.n.u1Present)
4379 { /* likely */ }
4380 else
4381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
4382
4383 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
4384 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
4385 { /* likely */ }
4386 else
4387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
4388 }
4389 }
4390
4391 /*
4392 * TR.
4393 */
4394 {
4395 CPUMSELREG Tr;
4396 Tr.Sel = pVmcs->GuestTr;
4397 Tr.u32Limit = pVmcs->u32GuestTrLimit;
4398 Tr.u64Base = pVmcs->u64GuestTrBase.u;
4399 Tr.Attr.u = pVmcs->u32GuestTrLimit;
4400
4401 /* Selector. */
4402 if (!(Tr.Sel & X86_SEL_LDT))
4403 { /* likely */ }
4404 else
4405 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
4406
4407 /* Base. */
4408 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4409 {
4410 if (X86_IS_CANONICAL(Tr.u64Base))
4411 { /* likely */ }
4412 else
4413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
4414 }
4415
4416 /* Attributes. */
4417 /* Reserved bits (bits 31:17 and bits 11:8). */
4418 if (!(Tr.Attr.u & 0xfffe0f00))
4419 { /* likely */ }
4420 else
4421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
4422
4423 if (!Tr.Attr.n.u1Unusable)
4424 { /* likely */ }
4425 else
4426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
4427
4428 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
4429 || ( !fGstInLongMode
4430 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
4431 { /* likely */ }
4432 else
4433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
4434
4435 if (!Tr.Attr.n.u1DescType)
4436 { /* likely */ }
4437 else
4438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
4439
4440 if (Tr.Attr.n.u1Present)
4441 { /* likely */ }
4442 else
4443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
4444
4445 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
4446 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
4447 { /* likely */ }
4448 else
4449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
4450 }
4451
4452 NOREF(pszInstr);
4453 NOREF(pszFailure);
4454 return VINF_SUCCESS;
4455}
4456
4457
4458/**
4459 * Checks guest GDTR and IDTR as part of VM-entry.
4460 *
4461 * @param pVCpu The cross context virtual CPU structure.
4462 * @param pszInstr The VMX instruction name (for logging purposes).
4463 */
4464IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
4465{
4466 /*
4467 * GDTR and IDTR.
4468 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
4469 */
4470 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4471 const char *const pszFailure = "VM-exit";
4472
4473 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4474 {
4475 /* Base. */
4476 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
4477 { /* likely */ }
4478 else
4479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
4480
4481 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
4482 { /* likely */ }
4483 else
4484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
4485 }
4486
4487 /* Limit. */
4488 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
4489 { /* likely */ }
4490 else
4491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
4492
4493 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
4494 { /* likely */ }
4495 else
4496 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
4497
4498 NOREF(pszInstr);
4499 NOREF(pszFailure);
4500 return VINF_SUCCESS;
4501}
4502
4503
4504/**
4505 * Checks guest RIP and RFLAGS as part of VM-entry.
4506 *
4507 * @param pVCpu The cross context virtual CPU structure.
4508 * @param pszInstr The VMX instruction name (for logging purposes).
4509 */
4510IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
4511{
4512 /*
4513 * RIP and RFLAGS.
4514 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
4515 */
4516 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4517 const char *const pszFailure = "VM-exit";
4518 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4519
4520 /* RIP. */
4521 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4522 {
4523 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4524 if ( !fGstInLongMode
4525 || !AttrCs.n.u1Long)
4526 {
4527 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
4528 { /* likely */ }
4529 else
4530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
4531 }
4532
4533 if ( fGstInLongMode
4534 && AttrCs.n.u1Long)
4535 {
4536 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
4537 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
4538 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
4539 { /* likely */ }
4540 else
4541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
4542 }
4543 }
4544
4545 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
4546 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
4547 : pVmcs->u64GuestRFlags.s.Lo;
4548 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
4549 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
4550 { /* likely */ }
4551 else
4552 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
4553
4554 if ( fGstInLongMode
4555 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4556 {
4557 if (!(uGuestRFlags & X86_EFL_VM))
4558 { /* likely */ }
4559 else
4560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
4561 }
4562
4563 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
4564 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4565 {
4566 if (uGuestRFlags & X86_EFL_IF)
4567 { /* likely */ }
4568 else
4569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
4570 }
4571
4572 NOREF(pszInstr);
4573 NOREF(pszFailure);
4574 return VINF_SUCCESS;
4575}
4576
4577
4578/**
4579 * Checks guest non-register state as part of VM-entry.
4580 *
4581 * @param pVCpu The cross context virtual CPU structure.
4582 * @param pszInstr The VMX instruction name (for logging purposes).
4583 */
4584IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
4585{
4586 /*
4587 * Guest non-register state.
4588 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
4589 */
4590 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4591 const char *const pszFailure = "VM-exit";
4592
4593 /*
4594 * Activity state.
4595 */
4596 uint64_t const u64GuestVmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
4597 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
4598 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
4599 { /* likely */ }
4600 else
4601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
4602
4603 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4604 if ( !AttrSs.n.u2Dpl
4605 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
4606 { /* likely */ }
4607 else
4608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
4609
4610 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
4611 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
4612 {
4613 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
4614 { /* likely */ }
4615 else
4616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
4617 }
4618
4619 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4620 {
4621 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4622 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
4623 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
4624 switch (pVmcs->u32GuestActivityState)
4625 {
4626 case VMX_VMCS_GUEST_ACTIVITY_HLT:
4627 {
4628 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
4629 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4630 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4631 && ( uVector == X86_XCPT_DB
4632 || uVector == X86_XCPT_MC))
4633 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
4634 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
4635 { /* likely */ }
4636 else
4637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
4638 break;
4639 }
4640
4641 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
4642 {
4643 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4644 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4645 && uVector == X86_XCPT_MC))
4646 { /* likely */ }
4647 else
4648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
4649 break;
4650 }
4651
4652 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
4653 default:
4654 break;
4655 }
4656 }
4657
4658 /*
4659 * Interruptibility state.
4660 */
4661 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
4662 { /* likely */ }
4663 else
4664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
4665
4666 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4667 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4668 { /* likely */ }
4669 else
4670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
4671
4672 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
4673 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4674 { /* likely */ }
4675 else
4676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
4677
4678 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4679 {
4680 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4681 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4682 {
4683 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4684 { /* likely */ }
4685 else
4686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
4687 }
4688 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
4689 {
4690 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4691 { /* likely */ }
4692 else
4693 {
4694 /*
4695 * We don't support injecting NMIs when blocking-by-STI would be in effect.
4696 * We update the VM-exit qualification only when blocking-by-STI is set
4697 * without blocking-by-MovSS being set. Although in practise it does not
4698 * make much difference since the order of checks are implementation defined.
4699 */
4700 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
4701 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
4702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
4703 }
4704
4705 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
4706 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
4707 { /* likely */ }
4708 else
4709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
4710 }
4711 }
4712
4713 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
4714 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
4715 { /* likely */ }
4716 else
4717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
4718
4719 /* We don't support SGX yet. So enclave-interruption must not be set. */
4720 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
4721 { /* likely */ }
4722 else
4723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
4724
4725 /*
4726 * Pending debug exceptions.
4727 */
4728 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
4729 ? pVmcs->u64GuestPendingDbgXcpt.u
4730 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
4731 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
4732 { /* likely */ }
4733 else
4734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
4735
4736 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4737 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
4738 {
4739 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4740 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
4741 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4742 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
4743
4744 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4745 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
4746 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4747 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
4748 }
4749
4750 /* We don't support RTM (Real-time Transactional Memory) yet. */
4751 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
4752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
4753
4754 /*
4755 * VMCS link pointer.
4756 */
4757 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
4758 {
4759 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
4760 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
4761 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
4762 { /* likely */ }
4763 else
4764 {
4765 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4766 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
4767 }
4768
4769 /* Validate the address. */
4770 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
4771 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
4772 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
4773 {
4774 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
4776 }
4777
4778 /* Read the VMCS-link pointer from guest memory. */
4779 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
4780 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
4781 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
4782 if (RT_FAILURE(rc))
4783 {
4784 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4785 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
4786 }
4787
4788 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
4789 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
4790 { /* likely */ }
4791 else
4792 {
4793 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4794 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
4795 }
4796
4797 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
4798 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
4799 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
4800 { /* likely */ }
4801 else
4802 {
4803 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
4805 }
4806
4807 /* Finally update our cache of the guest physical address of the shadow VMCS. */
4808 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
4809 }
4810
4811 NOREF(pszInstr);
4812 NOREF(pszFailure);
4813 return VINF_SUCCESS;
4814}
4815
4816
4817/**
4818 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
4819 * VM-entry.
4820 *
4821 * @returns @c true if all PDPTEs are valid, @c false otherwise.
4822 * @param pVCpu The cross context virtual CPU structure.
4823 * @param pszInstr The VMX instruction name (for logging purposes).
4824 * @param pVmcs Pointer to the virtual VMCS.
4825 */
4826IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
4827{
4828 /*
4829 * Check PDPTEs.
4830 * See Intel spec. 4.4.1 "PDPTE Registers".
4831 */
4832 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
4833 const char *const pszFailure = "VM-exit";
4834
4835 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
4836 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
4837 if (RT_SUCCESS(rc))
4838 {
4839 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
4840 {
4841 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
4842 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
4843 { /* likely */ }
4844 else
4845 {
4846 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4847 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
4848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4849 }
4850 }
4851 }
4852 else
4853 {
4854 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
4856 }
4857
4858 NOREF(pszFailure);
4859 return rc;
4860}
4861
4862
4863/**
4864 * Checks guest PDPTEs as part of VM-entry.
4865 *
4866 * @param pVCpu The cross context virtual CPU structure.
4867 * @param pszInstr The VMX instruction name (for logging purposes).
4868 */
4869IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
4870{
4871 /*
4872 * Guest PDPTEs.
4873 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
4874 */
4875 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4876 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4877
4878 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
4879 int rc;
4880 if ( !fGstInLongMode
4881 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
4882 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
4883 {
4884 /*
4885 * We don't support nested-paging for nested-guests yet.
4886 *
4887 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
4888 * rather we need to check the PDPTEs referenced by the guest CR3.
4889 */
4890 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
4891 }
4892 else
4893 rc = VINF_SUCCESS;
4894 return rc;
4895}
4896
4897
4898/**
4899 * Checks guest-state as part of VM-entry.
4900 *
4901 * @returns VBox status code.
4902 * @param pVCpu The cross context virtual CPU structure.
4903 * @param pszInstr The VMX instruction name (for logging purposes).
4904 */
4905IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
4906{
4907 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
4908 if (RT_SUCCESS(rc))
4909 {
4910 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
4911 if (RT_SUCCESS(rc))
4912 {
4913 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
4914 if (RT_SUCCESS(rc))
4915 {
4916 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
4917 if (RT_SUCCESS(rc))
4918 {
4919 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
4920 if (RT_SUCCESS(rc))
4921 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
4922 }
4923 }
4924 }
4925 }
4926 return rc;
4927}
4928
4929
4930/**
4931 * Checks host-state as part of VM-entry.
4932 *
4933 * @returns VBox status code.
4934 * @param pVCpu The cross context virtual CPU structure.
4935 * @param pszInstr The VMX instruction name (for logging purposes).
4936 */
4937IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
4938{
4939 /*
4940 * Host Control Registers and MSRs.
4941 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
4942 */
4943 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4944 const char * const pszFailure = "VMFail";
4945
4946 /* CR0 reserved bits. */
4947 {
4948 /* CR0 MB1 bits. */
4949 uint64_t const u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
4950 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
4951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
4952
4953 /* CR0 MBZ bits. */
4954 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
4955 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
4956 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
4957 }
4958
4959 /* CR4 reserved bits. */
4960 {
4961 /* CR4 MB1 bits. */
4962 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
4963 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
4964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
4965
4966 /* CR4 MBZ bits. */
4967 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
4968 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
4969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
4970 }
4971
4972 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4973 {
4974 /* CR3 reserved bits. */
4975 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4976 { /* likely */ }
4977 else
4978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
4979
4980 /* SYSENTER ESP and SYSENTER EIP. */
4981 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
4982 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
4983 { /* likely */ }
4984 else
4985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
4986 }
4987
4988 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4989 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
4990
4991 /* PAT MSR. */
4992 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
4993 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
4994 { /* likely */ }
4995 else
4996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
4997
4998 /* EFER MSR. */
4999 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5000 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5001 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5002 { /* likely */ }
5003 else
5004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5005
5006 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5007 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5008 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5009 if ( fHostInLongMode == fHostLma
5010 && fHostInLongMode == fHostLme)
5011 { /* likely */ }
5012 else
5013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5014
5015 /*
5016 * Host Segment and Descriptor-Table Registers.
5017 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5018 */
5019 /* Selector RPL and TI. */
5020 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5021 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5022 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5023 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5024 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5025 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5026 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5027 { /* likely */ }
5028 else
5029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5030
5031 /* CS and TR selectors cannot be 0. */
5032 if ( pVmcs->HostCs
5033 && pVmcs->HostTr)
5034 { /* likely */ }
5035 else
5036 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5037
5038 /* SS cannot be 0 if 32-bit host. */
5039 if ( fHostInLongMode
5040 || pVmcs->HostSs)
5041 { /* likely */ }
5042 else
5043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5044
5045 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5046 {
5047 /* FS, GS, GDTR, IDTR, TR base address. */
5048 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5049 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5050 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5051 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5052 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5053 { /* likely */ }
5054 else
5055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5056 }
5057
5058 /*
5059 * Host address-space size for 64-bit CPUs.
5060 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5061 */
5062 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5063 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5064 {
5065 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5066
5067 /* Logical processor in IA-32e mode. */
5068 if (fCpuInLongMode)
5069 {
5070 if (fHostInLongMode)
5071 {
5072 /* PAE must be set. */
5073 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5074 { /* likely */ }
5075 else
5076 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5077
5078 /* RIP must be canonical. */
5079 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5080 { /* likely */ }
5081 else
5082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5083 }
5084 else
5085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5086 }
5087 else
5088 {
5089 /* Logical processor is outside IA-32e mode. */
5090 if ( !fGstInLongMode
5091 && !fHostInLongMode)
5092 {
5093 /* PCIDE should not be set. */
5094 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5095 { /* likely */ }
5096 else
5097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5098
5099 /* The high 32-bits of RIP MBZ. */
5100 if (!pVmcs->u64HostRip.s.Hi)
5101 { /* likely */ }
5102 else
5103 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5104 }
5105 else
5106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5107 }
5108 }
5109 else
5110 {
5111 /* Host address-space size for 32-bit CPUs. */
5112 if ( !fGstInLongMode
5113 && !fHostInLongMode)
5114 { /* likely */ }
5115 else
5116 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5117 }
5118
5119 NOREF(pszInstr);
5120 NOREF(pszFailure);
5121 return VINF_SUCCESS;
5122}
5123
5124
5125/**
5126 * Checks VM-entry controls fields as part of VM-entry.
5127 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
5128 *
5129 * @returns VBox status code.
5130 * @param pVCpu The cross context virtual CPU structure.
5131 * @param pszInstr The VMX instruction name (for logging purposes).
5132 */
5133IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
5134{
5135 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5136 const char * const pszFailure = "VMFail";
5137
5138 /* VM-entry controls. */
5139 VMXCTLSMSR EntryCtls;
5140 EntryCtls.u = CPUMGetGuestIa32VmxEntryCtls(pVCpu);
5141 if (~pVmcs->u32EntryCtls & EntryCtls.n.disallowed0)
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
5143
5144 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
5145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
5146
5147 /* Event injection. */
5148 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
5149 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
5150 {
5151 /* Type and vector. */
5152 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
5153 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
5154 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
5155 if ( !uRsvd
5156 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
5157 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
5158 { /* likely */ }
5159 else
5160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
5161
5162 /* Exception error code. */
5163 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
5164 {
5165 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
5166 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
5167 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
5171
5172 /* Exceptions that provide an error code. */
5173 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5174 && ( uVector == X86_XCPT_DF
5175 || uVector == X86_XCPT_TS
5176 || uVector == X86_XCPT_NP
5177 || uVector == X86_XCPT_SS
5178 || uVector == X86_XCPT_GP
5179 || uVector == X86_XCPT_PF
5180 || uVector == X86_XCPT_AC))
5181 { /* likely */ }
5182 else
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
5184
5185 /* Exception error-code reserved bits. */
5186 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
5190
5191 /* Injecting a software interrupt, software exception or privileged software exception. */
5192 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
5193 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
5194 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
5195 {
5196 /* Instruction length must be in the range 0-15. */
5197 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
5201
5202 /* Instruction length of 0 is allowed only when its CPU feature is present. */
5203 if ( pVmcs->u32EntryInstrLen == 0
5204 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
5206 }
5207 }
5208 }
5209
5210 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
5211 if (pVmcs->u32EntryMsrLoadCount)
5212 {
5213 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5214 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5215 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
5216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
5217 }
5218
5219 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
5220 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
5221
5222 NOREF(pszInstr);
5223 NOREF(pszFailure);
5224 return VINF_SUCCESS;
5225}
5226
5227
5228/**
5229 * Checks VM-exit controls fields as part of VM-entry.
5230 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
5231 *
5232 * @returns VBox status code.
5233 * @param pVCpu The cross context virtual CPU structure.
5234 * @param pszInstr The VMX instruction name (for logging purposes).
5235 */
5236IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
5237{
5238 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5239 const char * const pszFailure = "VMFail";
5240
5241 /* VM-exit controls. */
5242 VMXCTLSMSR ExitCtls;
5243 ExitCtls.u = CPUMGetGuestIa32VmxExitCtls(pVCpu);
5244 if (~pVmcs->u32ExitCtls & ExitCtls.n.disallowed0)
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
5246
5247 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
5249
5250 /* Save preemption timer without activating it. */
5251 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
5252 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
5253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
5254
5255 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
5256 if (pVmcs->u32ExitMsrStoreCount)
5257 {
5258 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
5259 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5260 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
5262 }
5263
5264 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
5265 if (pVmcs->u32ExitMsrLoadCount)
5266 {
5267 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5268 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5269 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
5270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
5271 }
5272
5273 NOREF(pszInstr);
5274 NOREF(pszFailure);
5275 return VINF_SUCCESS;
5276}
5277
5278
5279/**
5280 * Checks VM-execution controls fields as part of VM-entry.
5281 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5282 *
5283 * @returns VBox status code.
5284 * @param pVCpu The cross context virtual CPU structure.
5285 * @param pszInstr The VMX instruction name (for logging purposes).
5286 *
5287 * @remarks This may update secondary-processor based VM-execution control fields
5288 * in the current VMCS if necessary.
5289 */
5290IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
5291{
5292 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5293 const char * const pszFailure = "VMFail";
5294
5295 /* Pin-based VM-execution controls. */
5296 {
5297 VMXCTLSMSR PinCtls;
5298 PinCtls.u = CPUMGetGuestIa32VmxPinbasedCtls(pVCpu);
5299 if (~pVmcs->u32PinCtls & PinCtls.n.disallowed0)
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5301
5302 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
5303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5304 }
5305
5306 /* Processor-based VM-execution controls. */
5307 {
5308 VMXCTLSMSR ProcCtls;
5309 ProcCtls.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
5310 if (~pVmcs->u32ProcCtls & ProcCtls.n.disallowed0)
5311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5312
5313 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
5314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5315 }
5316
5317 /* Secondary processor-based VM-execution controls. */
5318 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5319 {
5320 VMXCTLSMSR ProcCtls2;
5321 ProcCtls2.u = CPUMGetGuestIa32VmxProcbasedCtls2(pVCpu);
5322 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.disallowed0)
5323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5324
5325 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
5326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
5327 }
5328 else
5329 Assert(!pVmcs->u32ProcCtls2);
5330
5331 /* CR3-target count. */
5332 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
5333 { /* likely */ }
5334 else
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
5336
5337 /* I/O bitmaps physical addresses. */
5338 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
5339 {
5340 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
5341 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5342 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
5343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
5344
5345 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
5346 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5347 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
5348 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
5349 }
5350
5351 /* MSR bitmap physical address. */
5352 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
5353 {
5354 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
5355 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
5356 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5357 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
5359
5360 /* Read the MSR bitmap. */
5361 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
5362 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
5363 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
5364 if (RT_FAILURE(rc))
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
5366 }
5367
5368 /* TPR shadow related controls. */
5369 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5370 {
5371 /* Virtual-APIC page physical address. */
5372 RTGCPHYS GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
5373 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
5374 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5375 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
5376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
5377
5378 /* Read the Virtual-APIC page. */
5379 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
5380 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
5381 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
5382 if (RT_FAILURE(rc))
5383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
5384
5385 /* TPR threshold without virtual-interrupt delivery. */
5386 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5387 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
5389
5390 /* TPR threshold and VTPR. */
5391 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
5392 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
5393 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5394 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5395 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
5396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
5397 }
5398 else
5399 {
5400 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5401 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5402 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
5403 { /* likely */ }
5404 else
5405 {
5406 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5407 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
5408 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
5410 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
5412 }
5413 }
5414
5415 /* NMI exiting and virtual-NMIs. */
5416 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
5417 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
5418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
5419
5420 /* Virtual-NMIs and NMI-window exiting. */
5421 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5422 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
5423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
5424
5425 /* Virtualize APIC accesses. */
5426 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5427 {
5428 /* APIC-access physical address. */
5429 RTGCPHYS GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
5430 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
5431 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5432 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
5434 }
5435
5436 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
5437 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5438 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5440
5441 /* Virtual-interrupt delivery requires external interrupt exiting. */
5442 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5443 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
5444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5445
5446 /* VPID. */
5447 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
5448 || pVmcs->u16Vpid != 0)
5449 { /* likely */ }
5450 else
5451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
5452
5453 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
5454 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
5455 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
5456 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
5457 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
5458 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
5459 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
5460
5461 /* VMCS shadowing. */
5462 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5463 {
5464 /* VMREAD-bitmap physical address. */
5465 RTGCPHYS GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
5466 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
5467 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5468 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
5470
5471 /* VMWRITE-bitmap physical address. */
5472 RTGCPHYS GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
5473 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
5474 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5475 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
5477
5478 /* Read the VMREAD-bitmap. */
5479 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
5480 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
5481 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5482 if (RT_FAILURE(rc))
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
5484
5485 /* Read the VMWRITE-bitmap. */
5486 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
5487 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
5488 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5489 if (RT_FAILURE(rc))
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
5491 }
5492
5493 NOREF(pszInstr);
5494 NOREF(pszFailure);
5495 return VINF_SUCCESS;
5496}
5497
5498
5499/**
5500 * Loads the guest control registers, debug register and some MSRs as part of
5501 * VM-entry.
5502 *
5503 * @param pVCpu The cross context virtual CPU structure.
5504 */
5505IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
5506{
5507 /*
5508 * Load guest control registers, debug registers and MSRs.
5509 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
5510 */
5511 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5512 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
5513 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
5514 CPUMSetGuestCR0(pVCpu, uGstCr0);
5515 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
5516 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
5517
5518 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5519 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
5520
5521 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
5522 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
5523 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
5524
5525 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5526 {
5527 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
5528
5529 /* EFER MSR. */
5530 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
5531 {
5532 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5533 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
5534 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
5535 if (fGstInLongMode)
5536 {
5537 /* If the nested-guest is in long mode, LMA and LME are both set. */
5538 Assert(fGstPaging);
5539 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
5540 }
5541 else
5542 {
5543 /*
5544 * If the nested-guest is outside long mode:
5545 * - With paging: LMA is cleared, LME is cleared.
5546 * - Without paging: LMA is cleared, LME is left unmodified.
5547 */
5548 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
5549 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
5550 }
5551 }
5552 /* else: see below. */
5553 }
5554
5555 /* PAT MSR. */
5556 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5557 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
5558
5559 /* EFER MSR. */
5560 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5561 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
5562
5563 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5564 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5565
5566 /* We don't support IA32_BNDCFGS MSR yet. */
5567 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5568
5569 /* Nothing to do for SMBASE register - We don't support SMM yet. */
5570}
5571
5572
5573/**
5574 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
5575 *
5576 * @param pVCpu The cross context virtual CPU structure.
5577 */
5578IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
5579{
5580 /*
5581 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
5582 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
5583 */
5584 /* CS, SS, ES, DS, FS, GS. */
5585 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5586 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5587 {
5588 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5589 CPUMSELREG VmcsSelReg;
5590 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
5591 AssertRC(rc); NOREF(rc);
5592 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
5593 {
5594 pGstSelReg->Sel = VmcsSelReg.Sel;
5595 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5596 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5597 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5598 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5599 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5600 }
5601 else
5602 {
5603 pGstSelReg->Sel = VmcsSelReg.Sel;
5604 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5605 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5606 switch (iSegReg)
5607 {
5608 case X86_SREG_CS:
5609 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5610 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5611 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5612 break;
5613
5614 case X86_SREG_SS:
5615 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
5616 pGstSelReg->u32Limit = 0;
5617 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
5618 break;
5619
5620 case X86_SREG_ES:
5621 case X86_SREG_DS:
5622 pGstSelReg->u64Base = 0;
5623 pGstSelReg->u32Limit = 0;
5624 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5625 break;
5626
5627 case X86_SREG_FS:
5628 case X86_SREG_GS:
5629 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5630 pGstSelReg->u32Limit = 0;
5631 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5632 break;
5633 }
5634 Assert(pGstSelReg->Attr.n.u1Unusable);
5635 }
5636 }
5637
5638 /* LDTR. */
5639 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
5640 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
5641 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5642 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
5643 {
5644 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5645 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5646 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5647 }
5648 else
5649 {
5650 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5651 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
5652 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5653 }
5654
5655 /* TR. */
5656 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
5657 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
5658 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
5659 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5660 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
5661 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
5662 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
5663
5664 /* GDTR. */
5665 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
5666 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
5667
5668 /* IDTR. */
5669 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
5670 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
5671}
5672
5673
5674/**
5675 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
5676 *
5677 * @returns VBox status code.
5678 * @param pVCpu The cross context virtual CPU structure.
5679 * @param pszInstr The VMX instruction name (for logging purposes).
5680 */
5681IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
5682{
5683 /*
5684 * Load guest MSRs.
5685 * See Intel spec. 26.4 "Loading MSRs".
5686 */
5687 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5688 const char *const pszFailure = "VM-exit";
5689
5690 /*
5691 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
5692 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
5693 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
5694 */
5695 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
5696 if (!cMsrs)
5697 return VINF_SUCCESS;
5698
5699 /*
5700 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
5701 * exceeded including possibly raising #MC exceptions during VMX transition. Our
5702 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
5703 */
5704 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
5705 if (fIsMsrCountValid)
5706 { /* likely */ }
5707 else
5708 {
5709 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
5710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
5711 }
5712
5713 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
5714 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
5715 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
5716 if (RT_SUCCESS(rc))
5717 {
5718 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
5719 Assert(pMsr);
5720 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
5721 {
5722 if ( !pMsr->u32Reserved
5723 && pMsr->u32Msr != MSR_K8_FS_BASE
5724 && pMsr->u32Msr != MSR_K8_GS_BASE
5725 && pMsr->u32Msr != MSR_K6_EFER
5726 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
5727 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
5728 {
5729 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
5730 if (rcStrict == VINF_SUCCESS)
5731 continue;
5732
5733 /*
5734 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
5735 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
5736 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
5737 * further by our own, specific diagnostic code. Later, we can try implement handling of the
5738 * MSR in ring-0 if possible, or come up with a better, generic solution.
5739 */
5740 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5741 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
5742 ? kVmxVDiag_Vmentry_MsrLoadRing3
5743 : kVmxVDiag_Vmentry_MsrLoad;
5744 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5745 }
5746 else
5747 {
5748 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5749 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
5750 }
5751 }
5752 }
5753 else
5754 {
5755 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
5756 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
5757 }
5758
5759 NOREF(pszInstr);
5760 NOREF(pszFailure);
5761 return VINF_SUCCESS;
5762}
5763
5764
5765/**
5766 * Loads the guest-state non-register state as part of VM-entry.
5767 *
5768 * @returns VBox status code.
5769 * @param pVCpu The cross context virtual CPU structure.
5770 *
5771 * @remarks This must be called only after loading the nested-guest register state
5772 * (especially nested-guest RIP).
5773 */
5774IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
5775{
5776 /*
5777 * Load guest non-register state.
5778 * See Intel spec. 26.6 "Special Features of VM Entry"
5779 */
5780 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5781 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
5782 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5783 {
5784 /** @todo NSTVMX: Pending debug exceptions. */
5785 Assert(!(pVmcs->u64GuestPendingDbgXcpt.u));
5786
5787 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
5788 {
5789 /** @todo NSTVMX: Virtual-NMIs doesn't affect NMI blocking in the normal sense.
5790 * We probably need a different force flag for virtual-NMI
5791 * pending/blocking. */
5792 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI));
5793 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
5794 }
5795 else
5796 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
5797
5798 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5799 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
5800 else
5801 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
5802
5803 /* SMI blocking is irrelevant. We don't support SMIs yet. */
5804 }
5805
5806 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
5807 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
5808
5809 /* VPID is irrelevant. We don't support VPID yet. */
5810
5811 /* Clear address-range monitoring. */
5812 EMMonitorWaitClear(pVCpu);
5813}
5814
5815
5816/**
5817 * Loads the guest-state as part of VM-entry.
5818 *
5819 * @returns VBox status code.
5820 * @param pVCpu The cross context virtual CPU structure.
5821 * @param pszInstr The VMX instruction name (for logging purposes).
5822 *
5823 * @remarks This must be done after all the necessary steps prior to loading of
5824 * guest-state (e.g. checking various VMCS state).
5825 */
5826IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
5827{
5828 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
5829 iemVmxVmentryLoadGuestSegRegs(pVCpu);
5830
5831 /*
5832 * Load guest RIP, RSP and RFLAGS.
5833 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
5834 */
5835 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5836 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
5837 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
5838 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
5839
5840 /* Initialize the PAUSE-loop controls as part of VM-entry. */
5841 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
5842 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
5843
5844 iemVmxVmentryLoadGuestNonRegState(pVCpu);
5845
5846 NOREF(pszInstr);
5847 return VINF_SUCCESS;
5848}
5849
5850
5851/**
5852 * Performs event injection (if any) as part of VM-entry.
5853 *
5854 * @param pVCpu The cross context virtual CPU structure.
5855 * @param pszInstr The VMX instruction name (for logging purposes).
5856 */
5857IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
5858{
5859 /*
5860 * Inject events.
5861 * See Intel spec. 26.5 "Event Injection".
5862 */
5863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5864 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
5865 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5866 {
5867 /*
5868 * The event that is going to be made pending for injection is not subject to VMX intercepts,
5869 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
5870 * of the current event -are- subject to intercepts, hence this flag will be flipped during
5871 * the actually delivery of this event.
5872 */
5873 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = false;
5874
5875 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
5876 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
5877 {
5878 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
5879 VMCPU_FF_SET(pVCpu, VMCPU_FF_MTF);
5880 return VINF_SUCCESS;
5881 }
5882
5883 int rc = HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
5884 pVCpu->cpum.GstCtx.cr2);
5885 AssertRCReturn(rc, rc);
5886 }
5887
5888 NOREF(pszInstr);
5889 return VINF_SUCCESS;
5890}
5891
5892
5893/**
5894 * VMLAUNCH/VMRESUME instruction execution worker.
5895 *
5896 * @returns Strict VBox status code.
5897 * @param pVCpu The cross context virtual CPU structure.
5898 * @param cbInstr The instruction length in bytes.
5899 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
5900 * VMXINSTRID_VMRESUME).
5901 * @param pExitInfo Pointer to the VM-exit instruction information struct.
5902 * Optional, can be NULL.
5903 *
5904 * @remarks Common VMX instruction checks are already expected to by the caller,
5905 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
5906 */
5907IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId, PCVMXVEXITINFO pExitInfo)
5908{
5909 Assert( uInstrId == VMXINSTRID_VMLAUNCH
5910 || uInstrId == VMXINSTRID_VMRESUME);
5911 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
5912
5913 /* Nested-guest intercept. */
5914 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5915 {
5916 if (pExitInfo)
5917 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
5918 uint32_t const uExitReason = uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH;
5919 return iemVmxVmexitInstrNeedsInfo(pVCpu, uExitReason, uInstrId, cbInstr);
5920 }
5921
5922 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
5923
5924 /* CPL. */
5925 if (pVCpu->iem.s.uCpl > 0)
5926 {
5927 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
5928 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
5929 return iemRaiseGeneralProtectionFault0(pVCpu);
5930 }
5931
5932 /* Current VMCS valid. */
5933 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
5934 {
5935 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
5936 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
5937 iemVmxVmFailInvalid(pVCpu);
5938 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5939 return VINF_SUCCESS;
5940 }
5941
5942 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
5943 * use block-by-STI here which is not quite correct. */
5944 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5945 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
5946 {
5947 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
5948 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
5949 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
5950 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5951 return VINF_SUCCESS;
5952 }
5953
5954 if (uInstrId == VMXINSTRID_VMLAUNCH)
5955 {
5956 /* VMLAUNCH with non-clear VMCS. */
5957 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
5958 { /* likely */ }
5959 else
5960 {
5961 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
5962 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
5963 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
5964 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5965 return VINF_SUCCESS;
5966 }
5967 }
5968 else
5969 {
5970 /* VMRESUME with non-launched VMCS. */
5971 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
5972 { /* likely */ }
5973 else
5974 {
5975 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
5976 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
5977 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
5978 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5979 return VINF_SUCCESS;
5980 }
5981 }
5982
5983 /*
5984 * Load the current VMCS.
5985 */
5986 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
5987 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
5988 IEM_VMX_GET_CURRENT_VMCS(pVCpu), VMX_V_VMCS_SIZE);
5989 if (RT_FAILURE(rc))
5990 {
5991 Log(("%s: Failed to read VMCS at %#RGp, rc=%Rrc\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu), rc));
5992 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrReadPhys;
5993 return rc;
5994 }
5995
5996 /*
5997 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
5998 * while entering VMX non-root mode. We do some of this while checking VM-execution
5999 * controls. The guest hypervisor should not make assumptions and cannot expect
6000 * predictable behavior if changes to these structures are made in guest memory while
6001 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
6002 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
6003 *
6004 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6005 */
6006 rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
6007 if (RT_SUCCESS(rc))
6008 {
6009 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
6010 if (RT_SUCCESS(rc))
6011 {
6012 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
6013 if (RT_SUCCESS(rc))
6014 {
6015 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
6016 if (RT_SUCCESS(rc))
6017 {
6018 /* Save the guest force-flags as VM-exits can occur from this point on. */
6019 iemVmxVmentrySaveForceFlags(pVCpu);
6020
6021 /* Initialize the VM-exit qualification field as it MBZ for VM-exits where it isn't specified. */
6022 iemVmxVmcsSetExitQual(pVCpu, 0);
6023
6024 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
6025 if (RT_SUCCESS(rc))
6026 {
6027 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
6028 if (RT_SUCCESS(rc))
6029 {
6030 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
6031 if (RT_SUCCESS(rc))
6032 {
6033 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
6034
6035 /* VMLAUNCH instruction must update the VMCS launch state. */
6036 if (uInstrId == VMXINSTRID_VMLAUNCH)
6037 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
6038
6039 /* Perform the VMX transition (PGM updates). */
6040 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
6041 if (rcStrict == VINF_SUCCESS)
6042 { /* likely */ }
6043 else if (RT_SUCCESS(rcStrict))
6044 {
6045 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
6046 VBOXSTRICTRC_VAL(rcStrict)));
6047 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6048 }
6049 else
6050 {
6051 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
6052 return rcStrict;
6053 }
6054
6055 /* We've now entered nested-guest execution. */
6056 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
6057
6058 /* Now that we've switched page tables, we can inject events if any. */
6059 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
6060
6061 /** @todo NSTVMX: Setup VMX preemption timer */
6062 /** @todo NSTVMX: TPR thresholding. */
6063
6064 return VINF_SUCCESS;
6065 }
6066 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
6067 }
6068 }
6069 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
6070 }
6071
6072 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
6073 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6074 return VINF_SUCCESS;
6075 }
6076 }
6077 }
6078
6079 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
6080 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6081 return VINF_SUCCESS;
6082}
6083
6084
6085/**
6086 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
6087 * (causes a VM-exit) or not.
6088 *
6089 * @returns @c true if the instruction is intercepted, @c false otherwise.
6090 * @param pVCpu The cross context virtual CPU structure.
6091 * @param uExitReason The VM-exit exit reason (VMX_EXIT_RDMSR or
6092 * VMX_EXIT_WRMSR).
6093 * @param idMsr The MSR.
6094 */
6095IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
6096{
6097 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6098 Assert( uExitReason == VMX_EXIT_RDMSR
6099 || uExitReason == VMX_EXIT_WRMSR);
6100
6101 /* Consult the MSR bitmap if the feature is supported. */
6102 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6103 Assert(pVmcs);
6104 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6105 {
6106 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6107 if (uExitReason == VMX_EXIT_RDMSR)
6108 {
6109 VMXMSREXITREAD enmRead;
6110 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
6111 NULL /* penmWrite */);
6112 AssertRC(rc);
6113 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
6114 return true;
6115 }
6116 else
6117 {
6118 VMXMSREXITWRITE enmWrite;
6119 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
6120 &enmWrite);
6121 AssertRC(rc);
6122 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
6123 return true;
6124 }
6125 return false;
6126 }
6127
6128 /* Without MSR bitmaps, all MSR accesses are intercepted. */
6129 return true;
6130}
6131
6132
6133/**
6134 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
6135 * intercepted (causes a VM-exit) or not.
6136 *
6137 * @returns @c true if the instruction is intercepted, @c false otherwise.
6138 * @param pVCpu The cross context virtual CPU structure.
6139 * @param u64FieldEnc The VMCS field encoding.
6140 * @param uExitReason The VM-exit exit reason (VMX_EXIT_VMREAD or
6141 * VMX_EXIT_VMREAD).
6142 */
6143IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
6144{
6145 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6146 Assert( uExitReason == VMX_EXIT_VMREAD
6147 || uExitReason == VMX_EXIT_VMWRITE);
6148
6149 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
6150 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
6151 return true;
6152
6153 /*
6154 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
6155 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
6156 */
6157 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
6158 return true;
6159
6160 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
6161 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
6162 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6163 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6164 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
6165 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
6166 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
6167 pbBitmap += (u32FieldEnc >> 3);
6168 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
6169 return true;
6170
6171 return false;
6172}
6173
6174
6175/**
6176 * VMREAD common (memory/register) instruction execution worker
6177 *
6178 * @returns Strict VBox status code.
6179 * @param pVCpu The cross context virtual CPU structure.
6180 * @param cbInstr The instruction length in bytes.
6181 * @param pu64Dst Where to write the VMCS value (only updated when
6182 * VINF_SUCCESS is returned).
6183 * @param u64FieldEnc The VMCS field encoding.
6184 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6185 * be NULL.
6186 */
6187IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6188 PCVMXVEXITINFO pExitInfo)
6189{
6190 /* Nested-guest intercept. */
6191 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6192 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
6193 {
6194 if (pExitInfo)
6195 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6196 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
6197 }
6198
6199 /* CPL. */
6200 if (pVCpu->iem.s.uCpl > 0)
6201 {
6202 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6203 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
6204 return iemRaiseGeneralProtectionFault0(pVCpu);
6205 }
6206
6207 /* VMCS pointer in root mode. */
6208 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6209 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6210 {
6211 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6212 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
6213 iemVmxVmFailInvalid(pVCpu);
6214 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6215 return VINF_SUCCESS;
6216 }
6217
6218 /* VMCS-link pointer in non-root mode. */
6219 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6220 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6221 {
6222 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6223 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
6224 iemVmxVmFailInvalid(pVCpu);
6225 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6226 return VINF_SUCCESS;
6227 }
6228
6229 /* Supported VMCS field. */
6230 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6231 {
6232 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6233 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
6234 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
6235 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6236 return VINF_SUCCESS;
6237 }
6238
6239 /*
6240 * Setup reading from the current or shadow VMCS.
6241 */
6242 uint8_t *pbVmcs;
6243 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6244 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6245 else
6246 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6247 Assert(pbVmcs);
6248
6249 VMXVMCSFIELDENC FieldEnc;
6250 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6251 uint8_t const uWidth = FieldEnc.n.u2Width;
6252 uint8_t const uType = FieldEnc.n.u2Type;
6253 uint8_t const uWidthType = (uWidth << 2) | uType;
6254 uint8_t const uIndex = FieldEnc.n.u8Index;
6255 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6256 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6257
6258 /*
6259 * Read the VMCS component based on the field's effective width.
6260 *
6261 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6262 * indicates high bits (little endian).
6263 *
6264 * Note! The caller is responsible to trim the result and update registers
6265 * or memory locations are required. Here we just zero-extend to the largest
6266 * type (i.e. 64-bits).
6267 */
6268 uint8_t *pbField = pbVmcs + offField;
6269 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6270 switch (uEffWidth)
6271 {
6272 case VMX_VMCS_ENC_WIDTH_64BIT:
6273 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
6274 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
6275 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
6276 }
6277 return VINF_SUCCESS;
6278}
6279
6280
6281/**
6282 * VMREAD (64-bit register) instruction execution worker.
6283 *
6284 * @returns Strict VBox status code.
6285 * @param pVCpu The cross context virtual CPU structure.
6286 * @param cbInstr The instruction length in bytes.
6287 * @param pu64Dst Where to store the VMCS field's value.
6288 * @param u64FieldEnc The VMCS field encoding.
6289 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6290 * be NULL.
6291 */
6292IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6293 PCVMXVEXITINFO pExitInfo)
6294{
6295 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
6296 if (rcStrict == VINF_SUCCESS)
6297 {
6298 iemVmxVmreadSuccess(pVCpu, cbInstr);
6299 return VINF_SUCCESS;
6300 }
6301
6302 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6303 return rcStrict;
6304}
6305
6306
6307/**
6308 * VMREAD (32-bit register) instruction execution worker.
6309 *
6310 * @returns Strict VBox status code.
6311 * @param pVCpu The cross context virtual CPU structure.
6312 * @param cbInstr The instruction length in bytes.
6313 * @param pu32Dst Where to store the VMCS field's value.
6314 * @param u32FieldEnc The VMCS field encoding.
6315 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6316 * be NULL.
6317 */
6318IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
6319 PCVMXVEXITINFO pExitInfo)
6320{
6321 uint64_t u64Dst;
6322 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
6323 if (rcStrict == VINF_SUCCESS)
6324 {
6325 *pu32Dst = u64Dst;
6326 iemVmxVmreadSuccess(pVCpu, cbInstr);
6327 return VINF_SUCCESS;
6328 }
6329
6330 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6331 return rcStrict;
6332}
6333
6334
6335/**
6336 * VMREAD (memory) instruction execution worker.
6337 *
6338 * @returns Strict VBox status code.
6339 * @param pVCpu The cross context virtual CPU structure.
6340 * @param cbInstr The instruction length in bytes.
6341 * @param iEffSeg The effective segment register to use with @a u64Val.
6342 * Pass UINT8_MAX if it is a register access.
6343 * @param enmEffAddrMode The effective addressing mode (only used with memory
6344 * operand).
6345 * @param GCPtrDst The guest linear address to store the VMCS field's
6346 * value.
6347 * @param u64FieldEnc The VMCS field encoding.
6348 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6349 * be NULL.
6350 */
6351IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
6352 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6353{
6354 uint64_t u64Dst;
6355 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
6356 if (rcStrict == VINF_SUCCESS)
6357 {
6358 /*
6359 * Write the VMCS field's value to the location specified in guest-memory.
6360 *
6361 * The pointer size depends on the address size (address-size prefix allowed).
6362 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
6363 */
6364 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6365 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6366 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
6367
6368 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6369 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6370 else
6371 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6372 if (rcStrict == VINF_SUCCESS)
6373 {
6374 iemVmxVmreadSuccess(pVCpu, cbInstr);
6375 return VINF_SUCCESS;
6376 }
6377
6378 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
6379 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
6380 return rcStrict;
6381 }
6382
6383 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6384 return rcStrict;
6385}
6386
6387
6388/**
6389 * VMWRITE instruction execution worker.
6390 *
6391 * @returns Strict VBox status code.
6392 * @param pVCpu The cross context virtual CPU structure.
6393 * @param cbInstr The instruction length in bytes.
6394 * @param iEffSeg The effective segment register to use with @a u64Val.
6395 * Pass UINT8_MAX if it is a register access.
6396 * @param enmEffAddrMode The effective addressing mode (only used with memory
6397 * operand).
6398 * @param u64Val The value to write (or guest linear address to the
6399 * value), @a iEffSeg will indicate if it's a memory
6400 * operand.
6401 * @param u64FieldEnc The VMCS field encoding.
6402 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6403 * be NULL.
6404 */
6405IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
6406 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6407{
6408 /* Nested-guest intercept. */
6409 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6410 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
6411 {
6412 if (pExitInfo)
6413 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6414 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
6415 }
6416
6417 /* CPL. */
6418 if (pVCpu->iem.s.uCpl > 0)
6419 {
6420 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6421 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
6422 return iemRaiseGeneralProtectionFault0(pVCpu);
6423 }
6424
6425 /* VMCS pointer in root mode. */
6426 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6427 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6428 {
6429 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
6431 iemVmxVmFailInvalid(pVCpu);
6432 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6433 return VINF_SUCCESS;
6434 }
6435
6436 /* VMCS-link pointer in non-root mode. */
6437 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6438 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6439 {
6440 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6441 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
6442 iemVmxVmFailInvalid(pVCpu);
6443 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6444 return VINF_SUCCESS;
6445 }
6446
6447 /* If the VMWRITE instruction references memory, access the specified memory operand. */
6448 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
6449 if (!fIsRegOperand)
6450 {
6451 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6452 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6453 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
6454
6455 /* Read the value from the specified guest memory location. */
6456 VBOXSTRICTRC rcStrict;
6457 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6458 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
6459 else
6460 {
6461 uint32_t u32Val;
6462 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
6463 u64Val = u32Val;
6464 }
6465 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6466 {
6467 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
6468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
6469 return rcStrict;
6470 }
6471 }
6472 else
6473 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
6474
6475 /* Supported VMCS field. */
6476 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6477 {
6478 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
6480 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
6481 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6482 return VINF_SUCCESS;
6483 }
6484
6485 /* Read-only VMCS field. */
6486 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
6487 if ( fIsFieldReadOnly
6488 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
6489 {
6490 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
6491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
6492 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
6493 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6494 return VINF_SUCCESS;
6495 }
6496
6497 /*
6498 * Setup writing to the current or shadow VMCS.
6499 */
6500 uint8_t *pbVmcs;
6501 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6502 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6503 else
6504 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6505 Assert(pbVmcs);
6506
6507 VMXVMCSFIELDENC FieldEnc;
6508 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6509 uint8_t const uWidth = FieldEnc.n.u2Width;
6510 uint8_t const uType = FieldEnc.n.u2Type;
6511 uint8_t const uWidthType = (uWidth << 2) | uType;
6512 uint8_t const uIndex = FieldEnc.n.u8Index;
6513 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6514 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6515
6516 /*
6517 * Write the VMCS component based on the field's effective width.
6518 *
6519 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6520 * indicates high bits (little endian).
6521 */
6522 uint8_t *pbField = pbVmcs + offField;
6523 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6524 switch (uEffWidth)
6525 {
6526 case VMX_VMCS_ENC_WIDTH_64BIT:
6527 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
6528 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
6529 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
6530 }
6531
6532 iemVmxVmSucceed(pVCpu);
6533 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6534 return VINF_SUCCESS;
6535}
6536
6537
6538/**
6539 * VMCLEAR instruction execution worker.
6540 *
6541 * @returns Strict VBox status code.
6542 * @param pVCpu The cross context virtual CPU structure.
6543 * @param cbInstr The instruction length in bytes.
6544 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6545 * @param GCPtrVmcs The linear address of the VMCS pointer.
6546 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6547 * be NULL.
6548 *
6549 * @remarks Common VMX instruction checks are already expected to by the caller,
6550 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6551 */
6552IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6553 PCVMXVEXITINFO pExitInfo)
6554{
6555 /* Nested-guest intercept. */
6556 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6557 {
6558 if (pExitInfo)
6559 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6560 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
6561 }
6562
6563 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6564
6565 /* CPL. */
6566 if (pVCpu->iem.s.uCpl > 0)
6567 {
6568 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
6570 return iemRaiseGeneralProtectionFault0(pVCpu);
6571 }
6572
6573 /* Get the VMCS pointer from the location specified by the source memory operand. */
6574 RTGCPHYS GCPhysVmcs;
6575 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6576 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6577 {
6578 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
6580 return rcStrict;
6581 }
6582
6583 /* VMCS pointer alignment. */
6584 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6585 {
6586 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
6587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
6588 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6590 return VINF_SUCCESS;
6591 }
6592
6593 /* VMCS physical-address width limits. */
6594 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6595 {
6596 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6597 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
6598 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6599 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6600 return VINF_SUCCESS;
6601 }
6602
6603 /* VMCS is not the VMXON region. */
6604 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6605 {
6606 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6607 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
6608 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
6609 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6610 return VINF_SUCCESS;
6611 }
6612
6613 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6614 restriction imposed by our implementation. */
6615 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6616 {
6617 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
6618 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
6619 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6620 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6621 return VINF_SUCCESS;
6622 }
6623
6624 /*
6625 * VMCLEAR allows committing and clearing any valid VMCS pointer.
6626 *
6627 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
6628 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
6629 * to 'clear'.
6630 */
6631 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
6632 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
6633 {
6634 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
6635 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6636 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
6637 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6638 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
6639 }
6640 else
6641 {
6642 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPtrVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
6643 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
6644 }
6645
6646 iemVmxVmSucceed(pVCpu);
6647 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6648 return rcStrict;
6649}
6650
6651
6652/**
6653 * VMPTRST instruction execution worker.
6654 *
6655 * @returns Strict VBox status code.
6656 * @param pVCpu The cross context virtual CPU structure.
6657 * @param cbInstr The instruction length in bytes.
6658 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6659 * @param GCPtrVmcs The linear address of where to store the current VMCS
6660 * pointer.
6661 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6662 * be NULL.
6663 *
6664 * @remarks Common VMX instruction checks are already expected to by the caller,
6665 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6666 */
6667IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6668 PCVMXVEXITINFO pExitInfo)
6669{
6670 /* Nested-guest intercept. */
6671 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6672 {
6673 if (pExitInfo)
6674 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6675 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
6676 }
6677
6678 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6679
6680 /* CPL. */
6681 if (pVCpu->iem.s.uCpl > 0)
6682 {
6683 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6684 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
6685 return iemRaiseGeneralProtectionFault0(pVCpu);
6686 }
6687
6688 /* Set the VMCS pointer to the location specified by the destination memory operand. */
6689 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
6690 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
6691 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6692 {
6693 iemVmxVmSucceed(pVCpu);
6694 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6695 return rcStrict;
6696 }
6697
6698 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6699 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
6700 return rcStrict;
6701}
6702
6703
6704/**
6705 * VMPTRLD instruction execution worker.
6706 *
6707 * @returns Strict VBox status code.
6708 * @param pVCpu The cross context virtual CPU structure.
6709 * @param cbInstr The instruction length in bytes.
6710 * @param GCPtrVmcs The linear address of the current VMCS pointer.
6711 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6712 * be NULL.
6713 *
6714 * @remarks Common VMX instruction checks are already expected to by the caller,
6715 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6716 */
6717IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6718 PCVMXVEXITINFO pExitInfo)
6719{
6720 /* Nested-guest intercept. */
6721 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6722 {
6723 if (pExitInfo)
6724 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6725 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
6726 }
6727
6728 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6729
6730 /* CPL. */
6731 if (pVCpu->iem.s.uCpl > 0)
6732 {
6733 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6734 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
6735 return iemRaiseGeneralProtectionFault0(pVCpu);
6736 }
6737
6738 /* Get the VMCS pointer from the location specified by the source memory operand. */
6739 RTGCPHYS GCPhysVmcs;
6740 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6741 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6742 {
6743 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6744 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
6745 return rcStrict;
6746 }
6747
6748 /* VMCS pointer alignment. */
6749 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6750 {
6751 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
6752 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
6753 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6754 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6755 return VINF_SUCCESS;
6756 }
6757
6758 /* VMCS physical-address width limits. */
6759 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6760 {
6761 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6762 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
6763 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6765 return VINF_SUCCESS;
6766 }
6767
6768 /* VMCS is not the VMXON region. */
6769 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6770 {
6771 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
6773 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
6774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6775 return VINF_SUCCESS;
6776 }
6777
6778 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6779 restriction imposed by our implementation. */
6780 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6781 {
6782 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
6783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
6784 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6785 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6786 return VINF_SUCCESS;
6787 }
6788
6789 /* Read the VMCS revision ID from the VMCS. */
6790 VMXVMCSREVID VmcsRevId;
6791 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
6792 if (RT_FAILURE(rc))
6793 {
6794 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
6795 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
6796 return rc;
6797 }
6798
6799 /* Verify the VMCS revision specified by the guest matches what we reported to the guest,
6800 also check VMCS shadowing feature. */
6801 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
6802 || ( VmcsRevId.n.fIsShadowVmcs
6803 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
6804 {
6805 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
6806 {
6807 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFail()\n", VMX_V_VMCS_REVISION_ID,
6808 VmcsRevId.n.u31RevisionId));
6809 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
6810 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6811 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6812 return VINF_SUCCESS;
6813 }
6814
6815 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
6816 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
6817 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6818 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6819 return VINF_SUCCESS;
6820 }
6821
6822 /*
6823 * We only maintain only the current VMCS in our virtual CPU context (CPUMCTX). Therefore,
6824 * VMPTRLD shall always flush any existing current VMCS back to guest memory before loading
6825 * a new VMCS as current.
6826 */
6827 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
6828 {
6829 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6830 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
6831 }
6832
6833 iemVmxVmSucceed(pVCpu);
6834 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6835 return VINF_SUCCESS;
6836}
6837
6838
6839/**
6840 * VMXON instruction execution worker.
6841 *
6842 * @returns Strict VBox status code.
6843 * @param pVCpu The cross context virtual CPU structure.
6844 * @param cbInstr The instruction length in bytes.
6845 * @param iEffSeg The effective segment register to use with @a
6846 * GCPtrVmxon.
6847 * @param GCPtrVmxon The linear address of the VMXON pointer.
6848 * @param pExitInfo Pointer to the VM-exit instruction information struct.
6849 * Optional, can be NULL.
6850 *
6851 * @remarks Common VMX instruction checks are already expected to by the caller,
6852 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6853 */
6854IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
6855 PCVMXVEXITINFO pExitInfo)
6856{
6857#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
6858 RT_NOREF5(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
6859 return VINF_EM_RAW_EMULATE_INSTR;
6860#else
6861 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
6862 {
6863 /* CPL. */
6864 if (pVCpu->iem.s.uCpl > 0)
6865 {
6866 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6867 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
6868 return iemRaiseGeneralProtectionFault0(pVCpu);
6869 }
6870
6871 /* A20M (A20 Masked) mode. */
6872 if (!PGMPhysIsA20Enabled(pVCpu))
6873 {
6874 Log(("vmxon: A20M mode -> #GP(0)\n"));
6875 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
6876 return iemRaiseGeneralProtectionFault0(pVCpu);
6877 }
6878
6879 /* CR0. */
6880 {
6881 /* CR0 MB1 bits. */
6882 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
6883 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
6884 {
6885 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
6886 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
6887 return iemRaiseGeneralProtectionFault0(pVCpu);
6888 }
6889
6890 /* CR0 MBZ bits. */
6891 uint64_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
6892 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
6893 {
6894 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
6895 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
6896 return iemRaiseGeneralProtectionFault0(pVCpu);
6897 }
6898 }
6899
6900 /* CR4. */
6901 {
6902 /* CR4 MB1 bits. */
6903 uint64_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
6904 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
6905 {
6906 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
6907 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
6908 return iemRaiseGeneralProtectionFault0(pVCpu);
6909 }
6910
6911 /* CR4 MBZ bits. */
6912 uint64_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
6913 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
6914 {
6915 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
6916 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
6917 return iemRaiseGeneralProtectionFault0(pVCpu);
6918 }
6919 }
6920
6921 /* Feature control MSR's LOCK and VMXON bits. */
6922 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatureControl(pVCpu);
6923 if (!(uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON)))
6924 {
6925 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
6926 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
6927 return iemRaiseGeneralProtectionFault0(pVCpu);
6928 }
6929
6930 /* Get the VMXON pointer from the location specified by the source memory operand. */
6931 RTGCPHYS GCPhysVmxon;
6932 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
6933 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6934 {
6935 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
6936 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
6937 return rcStrict;
6938 }
6939
6940 /* VMXON region pointer alignment. */
6941 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
6942 {
6943 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
6944 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
6945 iemVmxVmFailInvalid(pVCpu);
6946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6947 return VINF_SUCCESS;
6948 }
6949
6950 /* VMXON physical-address width limits. */
6951 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6952 {
6953 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
6954 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
6955 iemVmxVmFailInvalid(pVCpu);
6956 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6957 return VINF_SUCCESS;
6958 }
6959
6960 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
6961 restriction imposed by our implementation. */
6962 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
6963 {
6964 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
6965 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
6966 iemVmxVmFailInvalid(pVCpu);
6967 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6968 return VINF_SUCCESS;
6969 }
6970
6971 /* Read the VMCS revision ID from the VMXON region. */
6972 VMXVMCSREVID VmcsRevId;
6973 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
6974 if (RT_FAILURE(rc))
6975 {
6976 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
6977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
6978 return rc;
6979 }
6980
6981 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6982 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
6983 {
6984 /* Revision ID mismatch. */
6985 if (!VmcsRevId.n.fIsShadowVmcs)
6986 {
6987 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
6988 VmcsRevId.n.u31RevisionId));
6989 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
6990 iemVmxVmFailInvalid(pVCpu);
6991 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6992 return VINF_SUCCESS;
6993 }
6994
6995 /* Shadow VMCS disallowed. */
6996 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
6997 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
6998 iemVmxVmFailInvalid(pVCpu);
6999 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7000 return VINF_SUCCESS;
7001 }
7002
7003 /*
7004 * Record that we're in VMX operation, block INIT, block and disable A20M.
7005 */
7006 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
7007 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7008 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
7009
7010 /* Clear address-range monitoring. */
7011 EMMonitorWaitClear(pVCpu);
7012 /** @todo NSTVMX: Intel PT. */
7013
7014 iemVmxVmSucceed(pVCpu);
7015 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7016# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7017 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7018# else
7019 return VINF_SUCCESS;
7020# endif
7021 }
7022 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7023 {
7024 /* Nested-guest intercept. */
7025 if (pExitInfo)
7026 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7027 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
7028 }
7029
7030 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7031
7032 /* CPL. */
7033 if (pVCpu->iem.s.uCpl > 0)
7034 {
7035 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7036 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
7037 return iemRaiseGeneralProtectionFault0(pVCpu);
7038 }
7039
7040 /* VMXON when already in VMX root mode. */
7041 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
7042 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
7043 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7044 return VINF_SUCCESS;
7045#endif
7046}
7047
7048
7049/**
7050 * Implements 'VMXOFF'.
7051 *
7052 * @remarks Common VMX instruction checks are already expected to by the caller,
7053 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7054 */
7055IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
7056{
7057# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7058 RT_NOREF2(pVCpu, cbInstr);
7059 return VINF_EM_RAW_EMULATE_INSTR;
7060# else
7061 /* Nested-guest intercept. */
7062 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7063 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
7064
7065 /* CPL. */
7066 if (pVCpu->iem.s.uCpl > 0)
7067 {
7068 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7069 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
7070 return iemRaiseGeneralProtectionFault0(pVCpu);
7071 }
7072
7073 /* Dual monitor treatment of SMIs and SMM. */
7074 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
7075 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
7076 {
7077 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
7078 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7079 return VINF_SUCCESS;
7080 }
7081
7082 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
7083 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
7084 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
7085
7086 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
7087 { /** @todo NSTVMX: Unblock SMI. */ }
7088
7089 EMMonitorWaitClear(pVCpu);
7090 /** @todo NSTVMX: Unblock and enable A20M. */
7091
7092 iemVmxVmSucceed(pVCpu);
7093 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7094# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7095 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
7096# else
7097 return VINF_SUCCESS;
7098# endif
7099# endif
7100}
7101
7102
7103/**
7104 * Implements 'VMXON'.
7105 */
7106IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
7107{
7108 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
7109}
7110
7111
7112/**
7113 * Implements 'VMLAUNCH'.
7114 */
7115IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
7116{
7117 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH, NULL /* pExitInfo */);
7118}
7119
7120
7121/**
7122 * Implements 'VMRESUME'.
7123 */
7124IEM_CIMPL_DEF_0(iemCImpl_vmresume)
7125{
7126 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME, NULL /* pExitInfo */);
7127}
7128
7129
7130/**
7131 * Implements 'VMPTRLD'.
7132 */
7133IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7134{
7135 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7136}
7137
7138
7139/**
7140 * Implements 'VMPTRST'.
7141 */
7142IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7143{
7144 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7145}
7146
7147
7148/**
7149 * Implements 'VMCLEAR'.
7150 */
7151IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7152{
7153 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7154}
7155
7156
7157/**
7158 * Implements 'VMWRITE' register.
7159 */
7160IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
7161{
7162 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
7163 NULL /* pExitInfo */);
7164}
7165
7166
7167/**
7168 * Implements 'VMWRITE' memory.
7169 */
7170IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
7171{
7172 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
7173}
7174
7175
7176/**
7177 * Implements 'VMREAD' 64-bit register.
7178 */
7179IEM_CIMPL_DEF_2(iemCImpl_vmread64_reg, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
7180{
7181 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
7182}
7183
7184
7185/**
7186 * Implements 'VMREAD' 32-bit register.
7187 */
7188IEM_CIMPL_DEF_2(iemCImpl_vmread32_reg, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
7189{
7190 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
7191}
7192
7193
7194/**
7195 * Implements 'VMREAD' memory.
7196 */
7197IEM_CIMPL_DEF_4(iemCImpl_vmread_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
7198{
7199 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
7200}
7201
7202
7203/**
7204 * Implements VMX's implementation of PAUSE.
7205 */
7206IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
7207{
7208 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7209 {
7210 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
7211 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7212 return rcStrict;
7213 }
7214
7215 /*
7216 * Outside VMX non-root operation or if the PAUSE instruction does not cause
7217 * a VM-exit, the instruction operates normally.
7218 */
7219 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7220 return VINF_SUCCESS;
7221}
7222
7223#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
7224
7225
7226/**
7227 * Implements 'VMCALL'.
7228 */
7229IEM_CIMPL_DEF_0(iemCImpl_vmcall)
7230{
7231#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7232 /* Nested-guest intercept. */
7233 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7234 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
7235#endif
7236
7237 /* Join forces with vmmcall. */
7238 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
7239}
7240
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