VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 74930

Last change on this file since 74930 was 74902, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Trying to figure out the relative priority of exits here. The spec is hard to parse.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 291.6 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp.h 74902 2018-10-18 06:52:43Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
20/** @todo NSTVMX: The following VM-exit intercepts are pending:
21 * VMX_EXIT_INIT_SIGNAL
22 * VMX_EXIT_SIPI
23 * VMX_EXIT_IO_SMI
24 * VMX_EXIT_SMI
25 * VMX_EXIT_INT_WINDOW
26 * VMX_EXIT_NMI_WINDOW
27 * VMX_EXIT_GETSEC
28 * VMX_EXIT_RSM
29 * VMX_EXIT_MTF
30 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
31 * VMX_EXIT_ERR_MACHINE_CHECK
32 * VMX_EXIT_TPR_BELOW_THRESHOLD
33 * VMX_EXIT_APIC_ACCESS
34 * VMX_EXIT_VIRTUALIZED_EOI
35 * VMX_EXIT_EPT_VIOLATION
36 * VMX_EXIT_EPT_MISCONFIG
37 * VMX_EXIT_INVEPT
38 * VMX_EXIT_PREEMPT_TIMER
39 * VMX_EXIT_INVVPID
40 * VMX_EXIT_APIC_WRITE
41 * VMX_EXIT_RDRAND
42 * VMX_EXIT_VMFUNC
43 * VMX_EXIT_ENCLS
44 * VMX_EXIT_RDSEED
45 * VMX_EXIT_PML_FULL
46 * VMX_EXIT_XSAVES
47 * VMX_EXIT_XRSTORS
48 */
49
50/**
51 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
52 *
53 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
54 * second dimension is the Index, see VMXVMCSFIELDENC.
55 */
56uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
57{
58 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
59 {
60 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
61 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
62 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
63 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
64 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
65 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
66 },
67 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
68 {
69 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
70 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
71 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
72 /* 24-25 */ UINT16_MAX, UINT16_MAX
73 },
74 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
75 {
76 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
77 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
78 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
79 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
80 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
81 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
82 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
83 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
84 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
85 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
86 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
87 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
88 },
89 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
90 {
91 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
92 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
93 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
94 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
95 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
96 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
97 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
98 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
99 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
100 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
101 },
102 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
103 {
104 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
105 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
106 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
107 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
108 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
109 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
110 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
111 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
112 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
113 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
114 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
115 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
116 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
117 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
118 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
119 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
120 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
121 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
122 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
123 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
124 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
125 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
126 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
127 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
128 /* 24 */ UINT16_MAX,
129 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
130 },
131 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
132 {
133 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
134 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
135 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
136 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
137 /* 25 */ UINT16_MAX
138 },
139 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
140 {
141 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
142 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
143 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
144 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
145 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
146 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
147 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
148 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
149 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
150 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
151 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
152 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
153 },
154 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
155 {
156 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
157 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
158 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
159 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
160 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
161 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
162 },
163 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
164 {
165 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
166 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
167 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
168 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
169 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
170 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
171 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
172 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
173 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
174 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
175 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
176 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
177 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
178 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
179 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
180 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
181 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
182 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
183 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
184 },
185 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
186 {
187 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
188 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
189 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
190 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
191 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
192 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
193 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
194 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
195 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
196 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
197 /* 24-25 */ UINT16_MAX, UINT16_MAX
198 },
199 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
200 {
201 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
202 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
203 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
204 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
205 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
206 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
207 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
208 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
209 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
210 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
211 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
212 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
213 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
214 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
215 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
216 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
217 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
218 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
219 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
220 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
221 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
222 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
223 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
224 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
225 /* 24-25 */ UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
230 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 25 */ UINT16_MAX
234 },
235 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
244 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
245 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
247 /* 24-25 */ UINT16_MAX, UINT16_MAX
248 },
249 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
250 {
251 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
252 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
253 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
254 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
255 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
256 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
257 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
260 },
261 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
262 {
263 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
264 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
265 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
266 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
267 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
268 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
269 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
270 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
271 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
272 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
273 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
274 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
275 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
276 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
277 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
278 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
279 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
280 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
281 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
282 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
283 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
284 },
285 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
297 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
298 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
299 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 }
302};
303
304
305/**
306 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
307 * relative offsets.
308 */
309# ifdef IEM_WITH_CODE_TLB
310# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
311# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
312# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
313# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
314# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
315# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
316# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
317# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
318# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
319# else /* !IEM_WITH_CODE_TLB */
320# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
321 do \
322 { \
323 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
324 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
325 } while (0)
326
327# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
328
329# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
330 do \
331 { \
332 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
333 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
334 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
335 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
336 } while (0)
337
338# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
339 do \
340 { \
341 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
342 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
343 } while (0)
344
345# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
346 do \
347 { \
348 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
349 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
350 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
351 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
352 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
353 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
354 } while (0)
355
356# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
357 do \
358 { \
359 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
360 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
361 } while (0)
362
363# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
364 do \
365 { \
366 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
367 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
368 } while (0)
369
370# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
371 do \
372 { \
373 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
374 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
375 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
376 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
377 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
378 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
379 } while (0)
380# endif /* !IEM_WITH_CODE_TLB */
381
382/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
383#define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
384
385/** Whether a shadow VMCS is present for the given VCPU. */
386#define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
387
388/** Gets the VMXON region pointer. */
389#define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
390
391/** Gets the guest-physical address of the current VMCS for the given VCPU. */
392#define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
393
394/** Whether a current VMCS is present for the given VCPU. */
395#define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
396
397/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
398#define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
399 do \
400 { \
401 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
402 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
403 } while (0)
404
405/** Clears any current VMCS for the given VCPU. */
406#define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
407 do \
408 { \
409 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
410 } while (0)
411
412/** Check for VMX instructions requiring to be in VMX operation.
413 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
414#define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
415 do \
416 { \
417 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
418 { /* likely */ } \
419 else \
420 { \
421 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
422 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
423 return iemRaiseUndefinedOpcode(a_pVCpu); \
424 } \
425 } while (0)
426
427/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
428#define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
429 do \
430 { \
431 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
432 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
433 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
434 return VERR_VMX_VMENTRY_FAILED; \
435 } while (0)
436
437/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
438#define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
439 do \
440 { \
441 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
442 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
443 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
444 return VERR_VMX_VMEXIT_FAILED; \
445 } while (0)
446
447
448/**
449 * Returns whether the given VMCS field is valid and supported by our emulation.
450 *
451 * @param pVCpu The cross context virtual CPU structure.
452 * @param u64FieldEnc The VMCS field encoding.
453 *
454 * @remarks This takes into account the CPU features exposed to the guest.
455 */
456IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
457{
458 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
459 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
460 if (!uFieldEncHi)
461 { /* likely */ }
462 else
463 return false;
464
465 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
466 switch (uFieldEncLo)
467 {
468 /*
469 * 16-bit fields.
470 */
471 /* Control fields. */
472 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
473 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
474 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
475
476 /* Guest-state fields. */
477 case VMX_VMCS16_GUEST_ES_SEL:
478 case VMX_VMCS16_GUEST_CS_SEL:
479 case VMX_VMCS16_GUEST_SS_SEL:
480 case VMX_VMCS16_GUEST_DS_SEL:
481 case VMX_VMCS16_GUEST_FS_SEL:
482 case VMX_VMCS16_GUEST_GS_SEL:
483 case VMX_VMCS16_GUEST_LDTR_SEL:
484 case VMX_VMCS16_GUEST_TR_SEL:
485 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
486 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
487
488 /* Host-state fields. */
489 case VMX_VMCS16_HOST_ES_SEL:
490 case VMX_VMCS16_HOST_CS_SEL:
491 case VMX_VMCS16_HOST_SS_SEL:
492 case VMX_VMCS16_HOST_DS_SEL:
493 case VMX_VMCS16_HOST_FS_SEL:
494 case VMX_VMCS16_HOST_GS_SEL:
495 case VMX_VMCS16_HOST_TR_SEL: return true;
496
497 /*
498 * 64-bit fields.
499 */
500 /* Control fields. */
501 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
502 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
503 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
504 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
505 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
506 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
507 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
508 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
509 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
510 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
511 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
512 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
513 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
514 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
515 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
516 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
517 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
518 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
519 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
520 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
521 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
522 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
523 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
524 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
525 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
526 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
527 case VMX_VMCS64_CTRL_EPTP_FULL:
528 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
529 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
532 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
533 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
534 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
535 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
536 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
537 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
538 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
539 {
540 uint64_t const uVmFuncMsr = CPUMGetGuestIa32VmxVmFunc(pVCpu);
541 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
542 }
543 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
545 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
547 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
548 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
549 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
550 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
551 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
552 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
553 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
554 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
555
556 /* Read-only data fields. */
557 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
558 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
559
560 /* Guest-state fields. */
561 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
562 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
563 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
564 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
565 case VMX_VMCS64_GUEST_PAT_FULL:
566 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
567 case VMX_VMCS64_GUEST_EFER_FULL:
568 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
569 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
570 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
571 case VMX_VMCS64_GUEST_PDPTE0_FULL:
572 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
573 case VMX_VMCS64_GUEST_PDPTE1_FULL:
574 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
575 case VMX_VMCS64_GUEST_PDPTE2_FULL:
576 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
577 case VMX_VMCS64_GUEST_PDPTE3_FULL:
578 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
579 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
580 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
581
582 /* Host-state fields. */
583 case VMX_VMCS64_HOST_PAT_FULL:
584 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
585 case VMX_VMCS64_HOST_EFER_FULL:
586 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
587 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
588 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
589
590 /*
591 * 32-bit fields.
592 */
593 /* Control fields. */
594 case VMX_VMCS32_CTRL_PIN_EXEC:
595 case VMX_VMCS32_CTRL_PROC_EXEC:
596 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
597 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
598 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
599 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
600 case VMX_VMCS32_CTRL_EXIT:
601 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
602 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
603 case VMX_VMCS32_CTRL_ENTRY:
604 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
605 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
606 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
607 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
608 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
609 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
610 case VMX_VMCS32_CTRL_PLE_GAP:
611 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
612
613 /* Read-only data fields. */
614 case VMX_VMCS32_RO_VM_INSTR_ERROR:
615 case VMX_VMCS32_RO_EXIT_REASON:
616 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
617 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
618 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
619 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
620 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
621 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
622
623 /* Guest-state fields. */
624 case VMX_VMCS32_GUEST_ES_LIMIT:
625 case VMX_VMCS32_GUEST_CS_LIMIT:
626 case VMX_VMCS32_GUEST_SS_LIMIT:
627 case VMX_VMCS32_GUEST_DS_LIMIT:
628 case VMX_VMCS32_GUEST_FS_LIMIT:
629 case VMX_VMCS32_GUEST_GS_LIMIT:
630 case VMX_VMCS32_GUEST_LDTR_LIMIT:
631 case VMX_VMCS32_GUEST_TR_LIMIT:
632 case VMX_VMCS32_GUEST_GDTR_LIMIT:
633 case VMX_VMCS32_GUEST_IDTR_LIMIT:
634 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
638 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
639 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
640 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
641 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
642 case VMX_VMCS32_GUEST_INT_STATE:
643 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
644 case VMX_VMCS32_GUEST_SMBASE:
645 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
646 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
647
648 /* Host-state fields. */
649 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
650
651 /*
652 * Natural-width fields.
653 */
654 /* Control fields. */
655 case VMX_VMCS_CTRL_CR0_MASK:
656 case VMX_VMCS_CTRL_CR4_MASK:
657 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
658 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
659 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
660 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
661 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
662 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
663
664 /* Read-only data fields. */
665 case VMX_VMCS_RO_EXIT_QUALIFICATION:
666 case VMX_VMCS_RO_IO_RCX:
667 case VMX_VMCS_RO_IO_RSX:
668 case VMX_VMCS_RO_IO_RDI:
669 case VMX_VMCS_RO_IO_RIP:
670 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
671
672 /* Guest-state fields. */
673 case VMX_VMCS_GUEST_CR0:
674 case VMX_VMCS_GUEST_CR3:
675 case VMX_VMCS_GUEST_CR4:
676 case VMX_VMCS_GUEST_ES_BASE:
677 case VMX_VMCS_GUEST_CS_BASE:
678 case VMX_VMCS_GUEST_SS_BASE:
679 case VMX_VMCS_GUEST_DS_BASE:
680 case VMX_VMCS_GUEST_FS_BASE:
681 case VMX_VMCS_GUEST_GS_BASE:
682 case VMX_VMCS_GUEST_LDTR_BASE:
683 case VMX_VMCS_GUEST_TR_BASE:
684 case VMX_VMCS_GUEST_GDTR_BASE:
685 case VMX_VMCS_GUEST_IDTR_BASE:
686 case VMX_VMCS_GUEST_DR7:
687 case VMX_VMCS_GUEST_RSP:
688 case VMX_VMCS_GUEST_RIP:
689 case VMX_VMCS_GUEST_RFLAGS:
690 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
691 case VMX_VMCS_GUEST_SYSENTER_ESP:
692 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
693
694 /* Host-state fields. */
695 case VMX_VMCS_HOST_CR0:
696 case VMX_VMCS_HOST_CR3:
697 case VMX_VMCS_HOST_CR4:
698 case VMX_VMCS_HOST_FS_BASE:
699 case VMX_VMCS_HOST_GS_BASE:
700 case VMX_VMCS_HOST_TR_BASE:
701 case VMX_VMCS_HOST_GDTR_BASE:
702 case VMX_VMCS_HOST_IDTR_BASE:
703 case VMX_VMCS_HOST_SYSENTER_ESP:
704 case VMX_VMCS_HOST_SYSENTER_EIP:
705 case VMX_VMCS_HOST_RSP:
706 case VMX_VMCS_HOST_RIP: return true;
707 }
708
709 return false;
710}
711
712
713/**
714 * Gets a host selector from the VMCS.
715 *
716 * @param pVmcs Pointer to the virtual VMCS.
717 * @param iSelReg The index of the segment register (X86_SREG_XXX).
718 */
719DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
720{
721 Assert(iSegReg < X86_SREG_COUNT);
722 RTSEL HostSel;
723 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
724 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
725 uint8_t const uWidthType = (uWidth << 2) | uType;
726 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
727 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
728 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
729 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
730 uint8_t const *pbField = pbVmcs + offField;
731 HostSel = *(uint16_t *)pbField;
732 return HostSel;
733}
734
735
736/**
737 * Sets a guest segment register in the VMCS.
738 *
739 * @param pVmcs Pointer to the virtual VMCS.
740 * @param iSegReg The index of the segment register (X86_SREG_XXX).
741 * @param pSelReg Pointer to the segment register.
742 */
743IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
744{
745 Assert(pSelReg);
746 Assert(iSegReg < X86_SREG_COUNT);
747
748 /* Selector. */
749 {
750 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
751 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
752 uint8_t const uWidthType = (uWidth << 2) | uType;
753 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
754 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
755 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
756 uint8_t *pbVmcs = (uint8_t *)pVmcs;
757 uint8_t *pbField = pbVmcs + offField;
758 *(uint16_t *)pbField = pSelReg->Sel;
759 }
760
761 /* Limit. */
762 {
763 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
764 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
765 uint8_t const uWidthType = (uWidth << 2) | uType;
766 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
767 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
768 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
769 uint8_t *pbVmcs = (uint8_t *)pVmcs;
770 uint8_t *pbField = pbVmcs + offField;
771 *(uint32_t *)pbField = pSelReg->u32Limit;
772 }
773
774 /* Base. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t const *pbField = pbVmcs + offField;
784 *(uint64_t *)pbField = pSelReg->u64Base;
785 }
786
787 /* Attributes. */
788 {
789 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
790 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
791 | X86DESCATTR_UNUSABLE;
792 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
793 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
794 uint8_t const uWidthType = (uWidth << 2) | uType;
795 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
796 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
797 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
798 uint8_t *pbVmcs = (uint8_t *)pVmcs;
799 uint8_t *pbField = pbVmcs + offField;
800 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
801 }
802}
803
804
805/**
806 * Gets a guest segment register from the VMCS.
807 *
808 * @returns VBox status code.
809 * @param pVmcs Pointer to the virtual VMCS.
810 * @param iSegReg The index of the segment register (X86_SREG_XXX).
811 * @param pSelReg Where to store the segment register (only updated when
812 * VINF_SUCCESS is returned).
813 *
814 * @remarks Warning! This does not validate the contents of the retrieved segment
815 * register.
816 */
817IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
818{
819 Assert(pSelReg);
820 Assert(iSegReg < X86_SREG_COUNT);
821
822 /* Selector. */
823 uint16_t u16Sel;
824 {
825 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
826 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
827 uint8_t const uWidthType = (uWidth << 2) | uType;
828 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
829 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
830 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
831 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
832 uint8_t const *pbField = pbVmcs + offField;
833 u16Sel = *(uint16_t *)pbField;
834 }
835
836 /* Limit. */
837 uint32_t u32Limit;
838 {
839 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
840 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
841 uint8_t const uWidthType = (uWidth << 2) | uType;
842 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
843 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
844 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
845 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
846 uint8_t const *pbField = pbVmcs + offField;
847 u32Limit = *(uint32_t *)pbField;
848 }
849
850 /* Base. */
851 uint64_t u64Base;
852 {
853 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
854 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
855 uint8_t const uWidthType = (uWidth << 2) | uType;
856 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
857 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
858 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
859 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
860 uint8_t const *pbField = pbVmcs + offField;
861 u64Base = *(uint64_t *)pbField;
862 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
863 }
864
865 /* Attributes. */
866 uint32_t u32Attr;
867 {
868 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
869 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
870 uint8_t const uWidthType = (uWidth << 2) | uType;
871 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
872 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
873 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
874 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
875 uint8_t const *pbField = pbVmcs + offField;
876 u32Attr = *(uint32_t *)pbField;
877 }
878
879 pSelReg->Sel = u16Sel;
880 pSelReg->ValidSel = u16Sel;
881 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
882 pSelReg->u32Limit = u32Limit;
883 pSelReg->u64Base = u64Base;
884 pSelReg->Attr.u = u32Attr;
885 return VINF_SUCCESS;
886}
887
888
889/**
890 * Gets a CR3 target value from the VMCS.
891 *
892 * @returns VBox status code.
893 * @param pVmcs Pointer to the virtual VMCS.
894 * @param idxCr3Target The index of the CR3-target value to retrieve.
895 * @param puValue Where to store the CR3-target value.
896 */
897DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
898{
899 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
900 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
901 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
902 uint8_t const uWidthType = (uWidth << 2) | uType;
903 uint8_t const uIndex = (idxCr3Target << 1) + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
904 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
905 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
906 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
907 uint8_t const *pbField = pbVmcs + offField;
908 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
909
910 return uCr3TargetValue;
911}
912
913
914/**
915 * Reads a 32-bit register from the virtual-APIC page at the given offset.
916 *
917 * @returns The register from the virtual-APIC page.
918 * @param pVCpu The cross context virtual CPU structure.
919 * @param offReg The offset of the register being read.
920 */
921DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint8_t offReg)
922{
923 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
924 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
925 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
926 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
927 return uReg;
928}
929
930
931/**
932 * Writes a 32-bit register to the virtual-APIC page at the given offset.
933 *
934 * @param pVCpu The cross context virtual CPU structure.
935 * @param uReg The register value to write.
936 * @param offReg The offset of the register being written.
937 */
938DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint32_t uReg, uint8_t offReg)
939{
940 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
941 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
942 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
943 *(uint32_t *)(pbVirtApic + offReg) = uReg;
944}
945
946
947/**
948 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
949 * mask and the read-shadow (CR0/CR4 read).
950 *
951 * @returns The masked CR0/CR4.
952 * @param pVCpu The cross context virtual CPU structure.
953 * @param iCrReg The control register (either CR0 or CR4).
954 * @param uGuestCrX The current guest CR0 or guest CR4.
955 */
956IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
957{
958 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
959 Assert(iCrReg == 0 || iCrReg == 4);
960
961 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
962 Assert(pVmcs);
963
964 /*
965 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
966 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
967 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
968 *
969 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
970 */
971 uint64_t fGstHostMask;
972 uint64_t fReadShadow;
973 if (iCrReg == 0)
974 {
975 fGstHostMask = pVmcs->u64Cr0Mask.u;
976 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
977 }
978 else
979 {
980 fGstHostMask = pVmcs->u64Cr4Mask.u;
981 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
982 }
983
984 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
985 return fMaskedCrX;
986}
987
988
989/**
990 * Gets VM-exit instruction information along with any displacement for an
991 * instruction VM-exit.
992 *
993 * @returns The VM-exit instruction information.
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uExitReason The VM-exit reason.
996 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
997 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
998 * NULL.
999 */
1000IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
1001{
1002 RTGCPTR GCPtrDisp;
1003 VMXEXITINSTRINFO ExitInstrInfo;
1004 ExitInstrInfo.u = 0;
1005
1006 /*
1007 * Get and parse the ModR/M byte from our decoded opcodes.
1008 */
1009 uint8_t bRm;
1010 uint8_t const offModRm = pVCpu->iem.s.offModRm;
1011 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
1012 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1013 {
1014 /*
1015 * ModR/M indicates register addressing.
1016 *
1017 * The primary/secondary register operands are reported in the iReg1 or iReg2
1018 * fields depending on whether it is a read/write form.
1019 */
1020 uint8_t idxReg1;
1021 uint8_t idxReg2;
1022 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1023 {
1024 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1025 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1026 }
1027 else
1028 {
1029 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1030 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1031 }
1032 ExitInstrInfo.All.u2Scaling = 0;
1033 ExitInstrInfo.All.iReg1 = idxReg1;
1034 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1035 ExitInstrInfo.All.fIsRegOperand = 1;
1036 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1037 ExitInstrInfo.All.iSegReg = 0;
1038 ExitInstrInfo.All.iIdxReg = 0;
1039 ExitInstrInfo.All.fIdxRegInvalid = 1;
1040 ExitInstrInfo.All.iBaseReg = 0;
1041 ExitInstrInfo.All.fBaseRegInvalid = 1;
1042 ExitInstrInfo.All.iReg2 = idxReg2;
1043
1044 /* Displacement not applicable for register addressing. */
1045 GCPtrDisp = 0;
1046 }
1047 else
1048 {
1049 /*
1050 * ModR/M indicates memory addressing.
1051 */
1052 uint8_t uScale = 0;
1053 bool fBaseRegValid = false;
1054 bool fIdxRegValid = false;
1055 uint8_t iBaseReg = 0;
1056 uint8_t iIdxReg = 0;
1057 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
1058 {
1059 /*
1060 * Parse the ModR/M, displacement for 16-bit addressing mode.
1061 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
1062 */
1063 uint16_t u16Disp = 0;
1064 uint8_t const offDisp = offModRm + sizeof(bRm);
1065 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
1066 {
1067 /* Displacement without any registers. */
1068 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
1069 }
1070 else
1071 {
1072 /* Register (index and base). */
1073 switch (bRm & X86_MODRM_RM_MASK)
1074 {
1075 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1076 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1077 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1078 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1079 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1080 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1081 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
1082 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
1083 }
1084
1085 /* Register + displacement. */
1086 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1087 {
1088 case 0: break;
1089 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
1090 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
1091 default:
1092 {
1093 /* Register addressing, handled at the beginning. */
1094 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1095 break;
1096 }
1097 }
1098 }
1099
1100 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
1101 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
1102 }
1103 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
1104 {
1105 /*
1106 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
1107 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
1108 */
1109 uint32_t u32Disp = 0;
1110 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
1111 {
1112 /* Displacement without any registers. */
1113 uint8_t const offDisp = offModRm + sizeof(bRm);
1114 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1115 }
1116 else
1117 {
1118 /* Register (and perhaps scale, index and base). */
1119 uint8_t offDisp = offModRm + sizeof(bRm);
1120 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1121 if (iBaseReg == 4)
1122 {
1123 /* An SIB byte follows the ModR/M byte, parse it. */
1124 uint8_t bSib;
1125 uint8_t const offSib = offModRm + sizeof(bRm);
1126 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1127
1128 /* A displacement may follow SIB, update its offset. */
1129 offDisp += sizeof(bSib);
1130
1131 /* Get the scale. */
1132 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1133
1134 /* Get the index register. */
1135 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
1136 fIdxRegValid = RT_BOOL(iIdxReg != 4);
1137
1138 /* Get the base register. */
1139 iBaseReg = bSib & X86_SIB_BASE_MASK;
1140 fBaseRegValid = true;
1141 if (iBaseReg == 5)
1142 {
1143 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1144 {
1145 /* Mod is 0 implies a 32-bit displacement with no base. */
1146 fBaseRegValid = false;
1147 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1148 }
1149 else
1150 {
1151 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
1152 iBaseReg = X86_GREG_xBP;
1153 }
1154 }
1155 }
1156
1157 /* Register + displacement. */
1158 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1159 {
1160 case 0: /* Handled above */ break;
1161 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
1162 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
1163 default:
1164 {
1165 /* Register addressing, handled at the beginning. */
1166 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1167 break;
1168 }
1169 }
1170 }
1171
1172 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
1173 }
1174 else
1175 {
1176 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
1177
1178 /*
1179 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
1180 * See Intel instruction spec. 2.2 "IA-32e Mode".
1181 */
1182 uint64_t u64Disp = 0;
1183 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
1184 if (fRipRelativeAddr)
1185 {
1186 /*
1187 * RIP-relative addressing mode.
1188 *
1189 * The displacement is 32-bit signed implying an offset range of +/-2G.
1190 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
1191 */
1192 uint8_t const offDisp = offModRm + sizeof(bRm);
1193 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1194 }
1195 else
1196 {
1197 uint8_t offDisp = offModRm + sizeof(bRm);
1198
1199 /*
1200 * Register (and perhaps scale, index and base).
1201 *
1202 * REX.B extends the most-significant bit of the base register. However, REX.B
1203 * is ignored while determining whether an SIB follows the opcode. Hence, we
1204 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
1205 *
1206 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
1207 */
1208 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1209 if (iBaseReg == 4)
1210 {
1211 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
1212 uint8_t bSib;
1213 uint8_t const offSib = offModRm + sizeof(bRm);
1214 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1215
1216 /* Displacement may follow SIB, update its offset. */
1217 offDisp += sizeof(bSib);
1218
1219 /* Get the scale. */
1220 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1221
1222 /* Get the index. */
1223 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
1224 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
1225
1226 /* Get the base. */
1227 iBaseReg = (bSib & X86_SIB_BASE_MASK);
1228 fBaseRegValid = true;
1229 if (iBaseReg == 5)
1230 {
1231 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1232 {
1233 /* Mod is 0 implies a signed 32-bit displacement with no base. */
1234 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1235 }
1236 else
1237 {
1238 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
1239 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
1240 }
1241 }
1242 }
1243 iBaseReg |= pVCpu->iem.s.uRexB;
1244
1245 /* Register + displacement. */
1246 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1247 {
1248 case 0: /* Handled above */ break;
1249 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
1250 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
1251 default:
1252 {
1253 /* Register addressing, handled at the beginning. */
1254 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1255 break;
1256 }
1257 }
1258 }
1259
1260 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
1261 }
1262
1263 /*
1264 * The primary or secondary register operand is reported in iReg2 depending
1265 * on whether the primary operand is in read/write form.
1266 */
1267 uint8_t idxReg2;
1268 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1269 {
1270 idxReg2 = bRm & X86_MODRM_RM_MASK;
1271 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1272 idxReg2 |= pVCpu->iem.s.uRexB;
1273 }
1274 else
1275 {
1276 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
1277 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1278 idxReg2 |= pVCpu->iem.s.uRexReg;
1279 }
1280 ExitInstrInfo.All.u2Scaling = uScale;
1281 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
1282 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1283 ExitInstrInfo.All.fIsRegOperand = 0;
1284 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1285 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
1286 ExitInstrInfo.All.iIdxReg = iIdxReg;
1287 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
1288 ExitInstrInfo.All.iBaseReg = iBaseReg;
1289 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
1290 ExitInstrInfo.All.iReg2 = idxReg2;
1291 }
1292
1293 /*
1294 * Handle exceptions to the norm for certain instructions.
1295 * (e.g. some instructions convey an instruction identity in place of iReg2).
1296 */
1297 switch (uExitReason)
1298 {
1299 case VMX_EXIT_GDTR_IDTR_ACCESS:
1300 {
1301 Assert(VMXINSTRID_IS_VALID(uInstrId));
1302 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1303 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1304 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
1305 break;
1306 }
1307
1308 case VMX_EXIT_LDTR_TR_ACCESS:
1309 {
1310 Assert(VMXINSTRID_IS_VALID(uInstrId));
1311 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1312 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1313 ExitInstrInfo.LdtTr.u2Undef0 = 0;
1314 break;
1315 }
1316
1317 case VMX_EXIT_RDRAND:
1318 case VMX_EXIT_RDSEED:
1319 {
1320 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
1321 break;
1322 }
1323 }
1324
1325 /* Update displacement and return the constructed VM-exit instruction information field. */
1326 if (pGCPtrDisp)
1327 *pGCPtrDisp = GCPtrDisp;
1328
1329 return ExitInstrInfo.u;
1330}
1331
1332
1333/**
1334 * Converts an IEM exception event type to a VMX event type.
1335 *
1336 * @returns The VMX event type.
1337 * @param uVector The interrupt / exception vector.
1338 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
1339 */
1340DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
1341{
1342 /* Paranoia (callers may use these interchangeably). */
1343 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
1344 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
1345 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
1346 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
1347 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
1348 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
1349 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
1350 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
1351 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
1352 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
1353 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
1354 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
1355
1356 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
1357 {
1358 if (uVector == X86_XCPT_NMI)
1359 return VMX_EXIT_INT_INFO_TYPE_NMI;
1360 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
1361 }
1362
1363 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
1364 {
1365 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
1366 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
1367 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
1368 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
1369 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
1370 }
1371
1372 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
1373 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
1374}
1375
1376
1377/**
1378 * Sets the VM-instruction error VMCS field.
1379 *
1380 * @param pVCpu The cross context virtual CPU structure.
1381 * @param enmInsErr The VM-instruction error.
1382 */
1383DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1384{
1385 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1386 pVmcs->u32RoVmInstrError = enmInsErr;
1387}
1388
1389
1390/**
1391 * Sets the VM-exit qualification VMCS field.
1392 *
1393 * @param pVCpu The cross context virtual CPU structure.
1394 * @param uExitQual The VM-exit qualification.
1395 */
1396DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
1397{
1398 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1399 pVmcs->u64RoExitQual.u = uExitQual;
1400}
1401
1402
1403/**
1404 * Sets the VM-exit interruption information field.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param uExitQual The VM-exit interruption information.
1408 */
1409DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1410{
1411 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1412 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1413}
1414
1415
1416/**
1417 * Sets the VM-exit interruption error code.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uErrCode The error code.
1421 */
1422DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1423{
1424 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1425 pVmcs->u32RoExitIntErrCode = uErrCode;
1426}
1427
1428
1429/**
1430 * Sets the IDT-vectoring information field.
1431 *
1432 * @param pVCpu The cross context virtual CPU structure.
1433 * @param uIdtVectorInfo The IDT-vectoring information.
1434 */
1435DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1436{
1437 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1438 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1439}
1440
1441
1442/**
1443 * Sets the IDT-vectoring error code field.
1444 *
1445 * @param pVCpu The cross context virtual CPU structure.
1446 * @param uErrCode The error code.
1447 */
1448DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1449{
1450 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1451 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1452}
1453
1454
1455/**
1456 * Sets the VM-exit guest-linear address VMCS field.
1457 *
1458 * @param pVCpu The cross context virtual CPU structure.
1459 * @param uGuestLinearAddr The VM-exit guest-linear address.
1460 */
1461DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1462{
1463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1464 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1465}
1466
1467
1468/**
1469 * Sets the VM-exit guest-physical address VMCS field.
1470 *
1471 * @param pVCpu The cross context virtual CPU structure.
1472 * @param uGuestPhysAddr The VM-exit guest-physical address.
1473 */
1474DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1475{
1476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1477 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1478}
1479
1480
1481/**
1482 * Sets the VM-exit instruction length VMCS field.
1483 *
1484 * @param pVCpu The cross context virtual CPU structure.
1485 * @param cbInstr The VM-exit instruction length in bytes.
1486 *
1487 * @remarks Callers may clear this field to 0. Hence, this function does not check
1488 * the validity of the instruction length.
1489 */
1490DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1491{
1492 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1493 pVmcs->u32RoExitInstrLen = cbInstr;
1494}
1495
1496
1497/**
1498 * Sets the VM-exit instruction info. VMCS field.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 * @param uExitInstrInfo The VM-exit instruction information.
1502 */
1503DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1504{
1505 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1506 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1507}
1508
1509
1510/**
1511 * Implements VMSucceed for VMX instruction success.
1512 *
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1516{
1517 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1518}
1519
1520
1521/**
1522 * Implements VMFailInvalid for VMX instruction failure.
1523 *
1524 * @param pVCpu The cross context virtual CPU structure.
1525 */
1526DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1527{
1528 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1529 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1530}
1531
1532
1533/**
1534 * Implements VMFailValid for VMX instruction failure.
1535 *
1536 * @param pVCpu The cross context virtual CPU structure.
1537 * @param enmInsErr The VM instruction error.
1538 */
1539DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1540{
1541 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1542 {
1543 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1544 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1545 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1546 }
1547}
1548
1549
1550/**
1551 * Implements VMFail for VMX instruction failure.
1552 *
1553 * @param pVCpu The cross context virtual CPU structure.
1554 * @param enmInsErr The VM instruction error.
1555 */
1556DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1557{
1558 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1559 iemVmxVmFailValid(pVCpu, enmInsErr);
1560 else
1561 iemVmxVmFailInvalid(pVCpu);
1562}
1563
1564
1565/**
1566 * Checks if the given auto-load/store MSR area count is valid for the
1567 * implementation.
1568 *
1569 * @returns @c true if it's within the valid limit, @c false otherwise.
1570 * @param pVCpu The cross context virtual CPU structure.
1571 * @param uMsrCount The MSR area count to check.
1572 */
1573DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1574{
1575 uint64_t const u64VmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
1576 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1577 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1578 if (uMsrCount <= cMaxSupportedMsrs)
1579 return true;
1580 return false;
1581}
1582
1583
1584/**
1585 * Flushes the current VMCS contents back to guest memory.
1586 *
1587 * @returns VBox status code.
1588 * @param pVCpu The cross context virtual CPU structure.
1589 */
1590DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1591{
1592 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1593 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1594 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1595 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1596 return rc;
1597}
1598
1599
1600/**
1601 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1602 *
1603 * @param pVCpu The cross context virtual CPU structure.
1604 */
1605DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1606{
1607 iemVmxVmSucceed(pVCpu);
1608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1609}
1610
1611
1612/**
1613 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1614 * nested-guest.
1615 *
1616 * @param iSegReg The segment index (X86_SREG_XXX).
1617 */
1618IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1619{
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1623 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1624 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1625 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1626 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1627 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1628 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1629 }
1630}
1631
1632
1633/**
1634 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1635 * nested-guest that is in Virtual-8086 mode.
1636 *
1637 * @param iSegReg The segment index (X86_SREG_XXX).
1638 */
1639IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1640{
1641 switch (iSegReg)
1642 {
1643 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1644 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1645 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1646 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1647 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1648 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1649 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1650 }
1651}
1652
1653
1654/**
1655 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1656 * nested-guest that is in Virtual-8086 mode.
1657 *
1658 * @param iSegReg The segment index (X86_SREG_XXX).
1659 */
1660IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1661{
1662 switch (iSegReg)
1663 {
1664 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1665 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1666 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1667 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1668 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1669 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1670 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1671 }
1672}
1673
1674
1675/**
1676 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1677 * nested-guest that is in Virtual-8086 mode.
1678 *
1679 * @param iSegReg The segment index (X86_SREG_XXX).
1680 */
1681IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1682{
1683 switch (iSegReg)
1684 {
1685 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1686 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1687 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1688 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1689 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1690 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1691 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1692 }
1693}
1694
1695
1696/**
1697 * Gets the instruction diagnostic for segment attributes reserved bits failure
1698 * during VM-entry of a nested-guest.
1699 *
1700 * @param iSegReg The segment index (X86_SREG_XXX).
1701 */
1702IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1703{
1704 switch (iSegReg)
1705 {
1706 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1707 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1708 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1709 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1710 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1711 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1712 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1713 }
1714}
1715
1716
1717/**
1718 * Gets the instruction diagnostic for segment attributes descriptor-type
1719 * (code/segment or system) failure during VM-entry of a nested-guest.
1720 *
1721 * @param iSegReg The segment index (X86_SREG_XXX).
1722 */
1723IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1724{
1725 switch (iSegReg)
1726 {
1727 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1728 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1729 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1730 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1731 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1732 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1733 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1734 }
1735}
1736
1737
1738/**
1739 * Gets the instruction diagnostic for segment attributes descriptor-type
1740 * (code/segment or system) failure during VM-entry of a nested-guest.
1741 *
1742 * @param iSegReg The segment index (X86_SREG_XXX).
1743 */
1744IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1745{
1746 switch (iSegReg)
1747 {
1748 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1749 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1750 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1751 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1752 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1753 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1754 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1755 }
1756}
1757
1758
1759/**
1760 * Gets the instruction diagnostic for segment attribute granularity failure during
1761 * VM-entry of a nested-guest.
1762 *
1763 * @param iSegReg The segment index (X86_SREG_XXX).
1764 */
1765IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1766{
1767 switch (iSegReg)
1768 {
1769 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1770 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1771 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1772 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1773 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1774 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1775 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1776 }
1777}
1778
1779/**
1780 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1781 * VM-entry of a nested-guest.
1782 *
1783 * @param iSegReg The segment index (X86_SREG_XXX).
1784 */
1785IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1786{
1787 switch (iSegReg)
1788 {
1789 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1790 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1791 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1792 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1793 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1794 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1795 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1796 }
1797}
1798
1799
1800/**
1801 * Gets the instruction diagnostic for segment attribute type accessed failure
1802 * during VM-entry of a nested-guest.
1803 *
1804 * @param iSegReg The segment index (X86_SREG_XXX).
1805 */
1806IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1807{
1808 switch (iSegReg)
1809 {
1810 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1811 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1812 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1813 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1814 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1815 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1816 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1817 }
1818}
1819
1820
1821/**
1822 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1823 * failure during VM-entry of a nested-guest.
1824 *
1825 * @param iSegReg The PDPTE entry index.
1826 */
1827IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1828{
1829 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1830 switch (iPdpte)
1831 {
1832 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1833 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1834 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1835 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1836 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1837 }
1838}
1839
1840
1841/**
1842 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1843 * failure during VM-exit of a nested-guest.
1844 *
1845 * @param iSegReg The PDPTE entry index.
1846 */
1847IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1848{
1849 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1850 switch (iPdpte)
1851 {
1852 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1853 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1854 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1855 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1856 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1857 }
1858}
1859
1860
1861/**
1862 * Saves the guest control registers, debug registers and some MSRs are part of
1863 * VM-exit.
1864 *
1865 * @param pVCpu The cross context virtual CPU structure.
1866 */
1867IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1868{
1869 /*
1870 * Saves the guest control registers, debug registers and some MSRs.
1871 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1872 */
1873 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1874
1875 /* Save control registers. */
1876 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1877 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1878 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1879
1880 /* Save SYSENTER CS, ESP, EIP. */
1881 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1882 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1883 {
1884 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1885 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1886 }
1887 else
1888 {
1889 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1890 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1891 }
1892
1893 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1894 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1895 {
1896 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1897 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1898 }
1899
1900 /* Save PAT MSR. */
1901 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1902 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1903
1904 /* Save EFER MSR. */
1905 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1906 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1907
1908 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1909 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1910
1911 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1912}
1913
1914
1915/**
1916 * Saves the guest force-flags in preparation of entering the nested-guest.
1917 *
1918 * @param pVCpu The cross context virtual CPU structure.
1919 */
1920IEM_STATIC void iemVmxVmentrySaveForceFlags(PVMCPU pVCpu)
1921{
1922 /* We shouldn't be called multiple times during VM-entry. */
1923 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1924
1925 /* MTF should not be set outside VMX non-root mode. */
1926 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_MTF));
1927
1928 /*
1929 * Preserve the required force-flags.
1930 *
1931 * We cache and clear force-flags that would affect the execution of the
1932 * nested-guest. Cached flags are then restored while returning to the guest
1933 * if necessary.
1934 *
1935 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1936 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1937 * instruction. Interrupt inhibition for any nested-guest instruction
1938 * will be set later while loading the guest-interruptibility state.
1939 *
1940 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1941 * successful VM-entry needs to continue blocking NMIs if it was in effect
1942 * during VM-entry.
1943 *
1944 * - MTF need not be preserved as it's used only in VMX non-root mode and
1945 * is supplied on VM-entry through the VM-execution controls.
1946 *
1947 * The remaining FFs (e.g. timers, APIC updates) must stay in place so that
1948 * we will be able to generate interrupts that may cause VM-exits for
1949 * the nested-guest.
1950 */
1951 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1952
1953 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS))
1954 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS);
1955}
1956
1957
1958/**
1959 * Restores the guest force-flags in preparation of exiting the nested-guest.
1960 *
1961 * @param pVCpu The cross context virtual CPU structure.
1962 */
1963IEM_STATIC void iemVmxVmexitRestoreForceFlags(PVMCPU pVCpu)
1964{
1965 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1966 {
1967 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1968 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1969 }
1970}
1971
1972
1973/**
1974 * Perform a VMX transition updated PGM, IEM and CPUM.
1975 *
1976 * @param pVCpu The cross context virtual CPU structure.
1977 */
1978IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1979{
1980 /*
1981 * Inform PGM about paging mode changes.
1982 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1983 * see comment in iemMemPageTranslateAndCheckAccess().
1984 */
1985 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1986# ifdef IN_RING3
1987 Assert(rc != VINF_PGM_CHANGE_MODE);
1988# endif
1989 AssertRCReturn(rc, rc);
1990
1991 /* Inform CPUM (recompiler), can later be removed. */
1992 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1993
1994 /*
1995 * Flush the TLB with new CR3. This is required in case the PGM mode change
1996 * above doesn't actually change anything.
1997 */
1998 if (rc == VINF_SUCCESS)
1999 {
2000 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
2001 AssertRCReturn(rc, rc);
2002 }
2003
2004 /* Re-initialize IEM cache/state after the drastic mode switch. */
2005 iemReInitExec(pVCpu);
2006 return rc;
2007}
2008
2009
2010/**
2011 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
2012 *
2013 * @param pVCpu The cross context virtual CPU structure.
2014 */
2015IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
2016{
2017 /*
2018 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
2019 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
2020 */
2021 /* CS, SS, ES, DS, FS, GS. */
2022 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2023 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2024 {
2025 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2026 if (!pSelReg->Attr.n.u1Unusable)
2027 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
2028 else
2029 {
2030 /*
2031 * For unusable segments the attributes are undefined except for CS and SS.
2032 * For the rest we don't bother preserving anything but the unusable bit.
2033 */
2034 switch (iSegReg)
2035 {
2036 case X86_SREG_CS:
2037 pVmcs->GuestCs = pSelReg->Sel;
2038 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
2039 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
2040 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
2041 | X86DESCATTR_UNUSABLE);
2042 break;
2043
2044 case X86_SREG_SS:
2045 pVmcs->GuestSs = pSelReg->Sel;
2046 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2047 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
2048 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
2049 break;
2050
2051 case X86_SREG_DS:
2052 pVmcs->GuestDs = pSelReg->Sel;
2053 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2054 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
2055 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
2056 break;
2057
2058 case X86_SREG_ES:
2059 pVmcs->GuestEs = pSelReg->Sel;
2060 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2061 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
2062 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
2063 break;
2064
2065 case X86_SREG_FS:
2066 pVmcs->GuestFs = pSelReg->Sel;
2067 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
2068 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
2069 break;
2070
2071 case X86_SREG_GS:
2072 pVmcs->GuestGs = pSelReg->Sel;
2073 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
2074 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
2075 break;
2076 }
2077 }
2078 }
2079
2080 /* Segment attribute bits 31:7 and 11:8 MBZ. */
2081 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
2082 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
2083 /* LDTR. */
2084 {
2085 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
2086 pVmcs->GuestLdtr = pSelReg->Sel;
2087 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
2088 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
2089 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
2090 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
2091 }
2092
2093 /* TR. */
2094 {
2095 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
2096 pVmcs->GuestTr = pSelReg->Sel;
2097 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
2098 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
2099 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
2100 }
2101
2102 /* GDTR. */
2103 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
2104 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
2105
2106 /* IDTR. */
2107 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
2108 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
2109}
2110
2111
2112/**
2113 * Saves guest non-register state as part of VM-exit.
2114 *
2115 * @param pVCpu The cross context virtual CPU structure.
2116 * @param uExitReason The VM-exit reason.
2117 */
2118IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
2119{
2120 /*
2121 * Save guest non-register state.
2122 * See Intel spec. 27.3.4 "Saving Non-Register State".
2123 */
2124 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2125
2126 /* Activity-state: VM-exits occur before changing the activity state, nothing further to do */
2127
2128 /* Interruptibility-state. */
2129 pVmcs->u32GuestIntrState = 0;
2130 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
2131 { /** @todo NSTVMX: Virtual-NMI blocking. */ }
2132 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2133 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
2134
2135 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2136 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
2137 {
2138 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
2139 * currently. */
2140 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
2141 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2142 }
2143 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
2144
2145 /* Pending debug exceptions. */
2146 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
2147 && uExitReason != VMX_EXIT_SMI
2148 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
2149 && !HMVmxIsTrapLikeVmexit(uExitReason))
2150 {
2151 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
2152 * block-by-MovSS is in effect. */
2153 pVmcs->u64GuestPendingDbgXcpt.u = 0;
2154 }
2155
2156 /** @todo NSTVMX: Save VMX preemption timer value. */
2157
2158 /* PDPTEs. */
2159 /* We don't support EPT yet. */
2160 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
2161 pVmcs->u64GuestPdpte0.u = 0;
2162 pVmcs->u64GuestPdpte1.u = 0;
2163 pVmcs->u64GuestPdpte2.u = 0;
2164 pVmcs->u64GuestPdpte3.u = 0;
2165}
2166
2167
2168/**
2169 * Saves the guest-state as part of VM-exit.
2170 *
2171 * @returns VBox status code.
2172 * @param pVCpu The cross context virtual CPU structure.
2173 * @param uExitReason The VM-exit reason.
2174 */
2175IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
2176{
2177 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2178 Assert(pVmcs);
2179
2180 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
2181 iemVmxVmexitSaveGuestSegRegs(pVCpu);
2182
2183 /*
2184 * Save guest RIP, RSP and RFLAGS.
2185 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
2186 *
2187 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
2188 * Callers must pass the instruction length in the VM-exit instruction length
2189 * field though it is undefined for such VM-exits. After updating RIP here, we clear
2190 * the VM-exit instruction length field.
2191 *
2192 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
2193 */
2194 if (HMVmxIsTrapLikeVmexit(uExitReason))
2195 {
2196 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
2197 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
2198 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2199 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
2200 }
2201
2202 /* We don't support enclave mode yet. */
2203 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
2204 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
2205 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
2206
2207 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
2208}
2209
2210
2211/**
2212 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
2213 *
2214 * @returns VBox status code.
2215 * @param pVCpu The cross context virtual CPU structure.
2216 * @param uExitReason The VM-exit reason (for diagnostic purposes).
2217 */
2218IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2219{
2220 /*
2221 * Save guest MSRs.
2222 * See Intel spec. 27.4 "Saving MSRs".
2223 */
2224 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2225 const char *const pszFailure = "VMX-abort";
2226
2227 /*
2228 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
2229 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
2230 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2231 */
2232 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
2233 if (!cMsrs)
2234 return VINF_SUCCESS;
2235
2236 /*
2237 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
2238 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2239 * implementation causes a VMX-abort followed by a triple-fault.
2240 */
2241 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2242 if (fIsMsrCountValid)
2243 { /* likely */ }
2244 else
2245 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
2246
2247 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2248 Assert(pMsr);
2249 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2250 {
2251 if ( !pMsr->u32Reserved
2252 && pMsr->u32Msr != MSR_IA32_SMBASE
2253 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2254 {
2255 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
2256 if (rcStrict == VINF_SUCCESS)
2257 continue;
2258
2259 /*
2260 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2261 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2262 * recording the MSR index in the auxiliary info. field and indicated further by our
2263 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2264 * if possible, or come up with a better, generic solution.
2265 */
2266 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2267 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2268 ? kVmxVDiag_Vmexit_MsrStoreRing3
2269 : kVmxVDiag_Vmexit_MsrStore;
2270 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2271 }
2272 else
2273 {
2274 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2275 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2276 }
2277 }
2278
2279 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2280 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2281 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), VMX_V_AUTOMSR_AREA_SIZE);
2282 if (RT_SUCCESS(rc))
2283 { /* likely */ }
2284 else
2285 {
2286 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2287 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2288 }
2289
2290 NOREF(uExitReason);
2291 NOREF(pszFailure);
2292 return VINF_SUCCESS;
2293}
2294
2295
2296/**
2297 * Performs a VMX abort (due to an fatal error during VM-exit).
2298 *
2299 * @returns Strict VBox status code.
2300 * @param pVCpu The cross context virtual CPU structure.
2301 * @param enmAbort The VMX abort reason.
2302 */
2303IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2304{
2305 /*
2306 * Perform the VMX abort.
2307 * See Intel spec. 27.7 "VMX Aborts".
2308 */
2309 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2310
2311 /* We don't support SMX yet. */
2312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2313 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2314 {
2315 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2316 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, u32VmxAbortId);
2317 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2318 }
2319
2320 return VINF_EM_TRIPLE_FAULT;
2321}
2322
2323
2324/**
2325 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2326 *
2327 * @param pVCpu The cross context virtual CPU structure.
2328 */
2329IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2330{
2331 /*
2332 * Load host control registers, debug registers and MSRs.
2333 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2334 */
2335 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2336 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2337
2338 /* CR0. */
2339 {
2340 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2341 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
2342 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2343 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2344 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2345 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2346 CPUMSetGuestCR0(pVCpu, uValidCr0);
2347 }
2348
2349 /* CR4. */
2350 {
2351 /* CR4 MB1 bits are not modified. */
2352 uint64_t const fCr4IgnMask = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
2353 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2354 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2355 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2356 if (fHostInLongMode)
2357 uValidCr4 |= X86_CR4_PAE;
2358 else
2359 uValidCr4 &= ~X86_CR4_PCIDE;
2360 CPUMSetGuestCR4(pVCpu, uValidCr4);
2361 }
2362
2363 /* CR3 (host value validated while checking host-state during VM-entry). */
2364 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2365
2366 /* DR7. */
2367 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2368
2369 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2370
2371 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2372 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2373 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2374 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2375
2376 /* FS, GS bases are loaded later while we load host segment registers. */
2377
2378 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2379 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2380 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2381 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2382 {
2383 if (fHostInLongMode)
2384 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2385 else
2386 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2387 }
2388
2389 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2390
2391 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2392 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2393 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2394
2395 /* We don't support IA32_BNDCFGS MSR yet. */
2396}
2397
2398
2399/**
2400 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2401 *
2402 * @param pVCpu The cross context virtual CPU structure.
2403 */
2404IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2405{
2406 /*
2407 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2408 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2409 *
2410 * Warning! Be careful to not touch fields that are reserved by VT-x,
2411 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2412 */
2413 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2414 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2415
2416 /* CS, SS, ES, DS, FS, GS. */
2417 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2418 {
2419 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2420 bool const fUnusable = RT_BOOL(HostSel == 0);
2421
2422 /* Selector. */
2423 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel = HostSel;
2424 pVCpu->cpum.GstCtx.aSRegs[iSegReg].ValidSel = HostSel;
2425 pVCpu->cpum.GstCtx.aSRegs[iSegReg].fFlags = CPUMSELREG_FLAGS_VALID;
2426
2427 /* Limit. */
2428 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u32Limit = 0xffffffff;
2429
2430 /* Base and Attributes. */
2431 switch (iSegReg)
2432 {
2433 case X86_SREG_CS:
2434 {
2435 pVCpu->cpum.GstCtx.cs.u64Base = 0;
2436 pVCpu->cpum.GstCtx.cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2437 pVCpu->cpum.GstCtx.ss.Attr.n.u1DescType = 1;
2438 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = 0;
2439 pVCpu->cpum.GstCtx.cs.Attr.n.u1Present = 1;
2440 pVCpu->cpum.GstCtx.cs.Attr.n.u1Long = fHostInLongMode;
2441 pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig = !fHostInLongMode;
2442 pVCpu->cpum.GstCtx.cs.Attr.n.u1Granularity = 1;
2443 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Unusable);
2444 Assert(!fUnusable);
2445 break;
2446 }
2447
2448 case X86_SREG_SS:
2449 case X86_SREG_ES:
2450 case X86_SREG_DS:
2451 {
2452 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base = 0;
2453 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2454 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DescType = 1;
2455 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u2Dpl = 0;
2456 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Present = 1;
2457 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DefBig = 1;
2458 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Granularity = 1;
2459 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable = fUnusable;
2460 break;
2461 }
2462
2463 case X86_SREG_FS:
2464 {
2465 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2466 pVCpu->cpum.GstCtx.fs.u64Base = !fUnusable ? pVmcs->u64HostFsBase.u : 0;
2467 pVCpu->cpum.GstCtx.fs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2468 pVCpu->cpum.GstCtx.fs.Attr.n.u1DescType = 1;
2469 pVCpu->cpum.GstCtx.fs.Attr.n.u2Dpl = 0;
2470 pVCpu->cpum.GstCtx.fs.Attr.n.u1Present = 1;
2471 pVCpu->cpum.GstCtx.fs.Attr.n.u1DefBig = 1;
2472 pVCpu->cpum.GstCtx.fs.Attr.n.u1Granularity = 1;
2473 pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable = fUnusable;
2474 break;
2475 }
2476
2477 case X86_SREG_GS:
2478 {
2479 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2480 pVCpu->cpum.GstCtx.gs.u64Base = !fUnusable ? pVmcs->u64HostGsBase.u : 0;
2481 pVCpu->cpum.GstCtx.gs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2482 pVCpu->cpum.GstCtx.gs.Attr.n.u1DescType = 1;
2483 pVCpu->cpum.GstCtx.gs.Attr.n.u2Dpl = 0;
2484 pVCpu->cpum.GstCtx.gs.Attr.n.u1Present = 1;
2485 pVCpu->cpum.GstCtx.gs.Attr.n.u1DefBig = 1;
2486 pVCpu->cpum.GstCtx.gs.Attr.n.u1Granularity = 1;
2487 pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable = fUnusable;
2488 break;
2489 }
2490 }
2491 }
2492
2493 /* TR. */
2494 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2495 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2496 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2497 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2498 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2499 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2500 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2501 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2502 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2503 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2504 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2505 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2506 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2507
2508 /* LDTR. */
2509 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2510 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2511 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2512 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
2513 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
2514 pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Unusable = 1;
2515
2516 /* GDTR. */
2517 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2518 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2519 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xfff;
2520
2521 /* IDTR.*/
2522 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2523 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2524 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xfff;
2525}
2526
2527
2528/**
2529 * Checks host PDPTes as part of VM-exit.
2530 *
2531 * @param pVCpu The cross context virtual CPU structure.
2532 * @param uExitReason The VM-exit reason (for logging purposes).
2533 */
2534IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2535{
2536 /*
2537 * Check host PDPTEs.
2538 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2539 */
2540 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2541 const char *const pszFailure = "VMX-abort";
2542 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2543
2544 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2545 && !fHostInLongMode)
2546 {
2547 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2548 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2549 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2550 if (RT_SUCCESS(rc))
2551 {
2552 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2553 {
2554 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2555 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2556 { /* likely */ }
2557 else
2558 {
2559 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2560 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2561 }
2562 }
2563 }
2564 else
2565 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2566 }
2567
2568 NOREF(pszFailure);
2569 NOREF(uExitReason);
2570 return VINF_SUCCESS;
2571}
2572
2573
2574/**
2575 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2576 *
2577 * @returns VBox status code.
2578 * @param pVCpu The cross context virtual CPU structure.
2579 * @param pszInstr The VMX instruction name (for logging purposes).
2580 */
2581IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2582{
2583 /*
2584 * Load host MSRs.
2585 * See Intel spec. 27.6 "Loading MSRs".
2586 */
2587 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2588 const char *const pszFailure = "VMX-abort";
2589
2590 /*
2591 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2592 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2593 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2594 */
2595 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2596 if (!cMsrs)
2597 return VINF_SUCCESS;
2598
2599 /*
2600 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2601 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2602 * implementation causes a VMX-abort followed by a triple-fault.
2603 */
2604 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2605 if (fIsMsrCountValid)
2606 { /* likely */ }
2607 else
2608 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2609
2610 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2611 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2612 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
2613 if (RT_SUCCESS(rc))
2614 {
2615 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2616 Assert(pMsr);
2617 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2618 {
2619 if ( !pMsr->u32Reserved
2620 && pMsr->u32Msr != MSR_K8_FS_BASE
2621 && pMsr->u32Msr != MSR_K8_GS_BASE
2622 && pMsr->u32Msr != MSR_K6_EFER
2623 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2625 {
2626 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2627 if (rcStrict == VINF_SUCCESS)
2628 continue;
2629
2630 /*
2631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2632 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2633 * recording the MSR index in the auxiliary info. field and indicated further by our
2634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2635 * if possible, or come up with a better, generic solution.
2636 */
2637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2639 ? kVmxVDiag_Vmexit_MsrLoadRing3
2640 : kVmxVDiag_Vmexit_MsrLoad;
2641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2642 }
2643 else
2644 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2645 }
2646 }
2647 else
2648 {
2649 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2651 }
2652
2653 NOREF(uExitReason);
2654 NOREF(pszFailure);
2655 return VINF_SUCCESS;
2656}
2657
2658
2659/**
2660 * Loads the host state as part of VM-exit.
2661 *
2662 * @returns Strict VBox status code.
2663 * @param pVCpu The cross context virtual CPU structure.
2664 * @param uExitReason The VM-exit reason (for logging purposes).
2665 */
2666IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2667{
2668 /*
2669 * Load host state.
2670 * See Intel spec. 27.5 "Loading Host State".
2671 */
2672 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2673 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2674
2675 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2676 if ( CPUMIsGuestInLongMode(pVCpu)
2677 && !fHostInLongMode)
2678 {
2679 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2680 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2681 }
2682
2683 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2684 iemVmxVmexitLoadHostSegRegs(pVCpu);
2685
2686 /*
2687 * Load host RIP, RSP and RFLAGS.
2688 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2689 */
2690 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2691 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2692 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2693
2694 /* Update non-register state. */
2695 iemVmxVmexitRestoreForceFlags(pVCpu);
2696
2697 /* Clear address range monitoring. */
2698 EMMonitorWaitClear(pVCpu);
2699
2700 /* Perform the VMX transition (PGM updates). */
2701 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2702 if (rcStrict == VINF_SUCCESS)
2703 {
2704 /* Check host PDPTEs (only when we've fully switched page tables_. */
2705 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2706 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2707 if (RT_FAILURE(rc))
2708 {
2709 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2710 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2711 }
2712 }
2713 else if (RT_SUCCESS(rcStrict))
2714 {
2715 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2716 uExitReason));
2717 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2718 }
2719 else
2720 {
2721 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2722 return VBOXSTRICTRC_VAL(rcStrict);
2723 }
2724
2725 Assert(rcStrict == VINF_SUCCESS);
2726
2727 /* Load MSRs from the VM-exit auto-load MSR area. */
2728 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2729 if (RT_FAILURE(rc))
2730 {
2731 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2732 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2733 }
2734
2735 return rcStrict;
2736}
2737
2738
2739/**
2740 * VMX VM-exit handler.
2741 *
2742 * @returns Strict VBox status code.
2743 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2744 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2745 * triple-fault.
2746 *
2747 * @param pVCpu The cross context virtual CPU structure.
2748 * @param uExitReason The VM-exit reason.
2749 *
2750 * @remarks Make sure VM-exit qualification is updated before calling this
2751 * function!
2752 */
2753IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2754{
2755 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2756 Assert(pVmcs);
2757
2758 pVmcs->u32RoExitReason = uExitReason;
2759
2760 /** @todo NSTVMX: IEMGetCurrentXcpt will be VM-exit interruption info. */
2761 /** @todo NSTVMX: The source event should be recorded in IDT-vectoring info
2762 * during injection. */
2763
2764 /*
2765 * Save the guest state back into the VMCS.
2766 * We only need to save the state when the VM-entry was successful.
2767 */
2768 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2769 if (!fVmentryFailed)
2770 {
2771 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2772 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2773 if (RT_SUCCESS(rc))
2774 { /* likely */ }
2775 else
2776 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2777 }
2778
2779 /*
2780 * The high bits of the VM-exit reason are only relevant when the VM-exit occurs in
2781 * enclave mode/SMM which we don't support yet. If we ever add support for it, we can
2782 * pass just the lower bits, till then an assert should suffice.
2783 */
2784 Assert(!RT_HI_U16(uExitReason));
2785
2786 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2787 if (RT_FAILURE(rcStrict))
2788 LogFunc(("Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2789
2790 /* We're no longer in nested-guest execution mode. */
2791 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2792
2793 Assert(rcStrict == VINF_SUCCESS);
2794 return VINF_VMX_VMEXIT;
2795}
2796
2797
2798/**
2799 * VMX VM-exit handler for VM-exits due to instruction execution.
2800 *
2801 * This is intended for instructions where the caller provides all the relevant
2802 * VM-exit information.
2803 *
2804 * @returns Strict VBox status code.
2805 * @param pVCpu The cross context virtual CPU structure.
2806 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2807 */
2808DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2809{
2810 /*
2811 * For instructions where any of the following fields are not applicable:
2812 * - VM-exit instruction info. is undefined.
2813 * - VM-exit qualification must be cleared.
2814 * - VM-exit guest-linear address is undefined.
2815 * - VM-exit guest-physical address is undefined.
2816 *
2817 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2818 * instruction execution. For VM-exits that are not due to instruction execution this
2819 * field is undefined.
2820 *
2821 * In our implementation in IEM, all undefined fields are generally cleared. However,
2822 * if the caller supplies information (from say the physical CPU directly) it is
2823 * then possible that the undefined fields not cleared.
2824 *
2825 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2826 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2827 */
2828 Assert(pExitInfo);
2829 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2830 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2831 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2832
2833 /* Update all the relevant fields from the VM-exit instruction information struct. */
2834 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2835 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2836 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2837 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2838 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2839
2840 /* Perform the VM-exit. */
2841 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2842}
2843
2844
2845/**
2846 * VMX VM-exit handler for VM-exits due to instruction execution.
2847 *
2848 * This is intended for instructions that only provide the VM-exit instruction
2849 * length.
2850 *
2851 * @param pVCpu The cross context virtual CPU structure.
2852 * @param uExitReason The VM-exit reason.
2853 * @param cbInstr The instruction length in bytes.
2854 */
2855IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2856{
2857 VMXVEXITINFO ExitInfo;
2858 RT_ZERO(ExitInfo);
2859 ExitInfo.uReason = uExitReason;
2860 ExitInfo.cbInstr = cbInstr;
2861
2862#ifdef VBOX_STRICT
2863 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2864 switch (uExitReason)
2865 {
2866 case VMX_EXIT_INVEPT:
2867 case VMX_EXIT_INVPCID:
2868 case VMX_EXIT_LDTR_TR_ACCESS:
2869 case VMX_EXIT_GDTR_IDTR_ACCESS:
2870 case VMX_EXIT_VMCLEAR:
2871 case VMX_EXIT_VMPTRLD:
2872 case VMX_EXIT_VMPTRST:
2873 case VMX_EXIT_VMREAD:
2874 case VMX_EXIT_VMWRITE:
2875 case VMX_EXIT_VMXON:
2876 case VMX_EXIT_XRSTORS:
2877 case VMX_EXIT_XSAVES:
2878 case VMX_EXIT_RDRAND:
2879 case VMX_EXIT_RDSEED:
2880 case VMX_EXIT_IO_INSTR:
2881 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2882 break;
2883 }
2884#endif
2885
2886 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2887}
2888
2889
2890/**
2891 * VMX VM-exit handler for VM-exits due to instruction execution.
2892 *
2893 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2894 * instruction information and VM-exit qualification fields.
2895 *
2896 * @param pVCpu The cross context virtual CPU structure.
2897 * @param uExitReason The VM-exit reason.
2898 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2899 * @param cbInstr The instruction length in bytes.
2900 *
2901 * @remarks Do not use this for INS/OUTS instruction.
2902 */
2903IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2904{
2905 VMXVEXITINFO ExitInfo;
2906 RT_ZERO(ExitInfo);
2907 ExitInfo.uReason = uExitReason;
2908 ExitInfo.cbInstr = cbInstr;
2909
2910 /*
2911 * Update the VM-exit qualification field with displacement bytes.
2912 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2913 */
2914 switch (uExitReason)
2915 {
2916 case VMX_EXIT_INVEPT:
2917 case VMX_EXIT_INVPCID:
2918 case VMX_EXIT_LDTR_TR_ACCESS:
2919 case VMX_EXIT_GDTR_IDTR_ACCESS:
2920 case VMX_EXIT_VMCLEAR:
2921 case VMX_EXIT_VMPTRLD:
2922 case VMX_EXIT_VMPTRST:
2923 case VMX_EXIT_VMREAD:
2924 case VMX_EXIT_VMWRITE:
2925 case VMX_EXIT_VMXON:
2926 case VMX_EXIT_XRSTORS:
2927 case VMX_EXIT_XSAVES:
2928 case VMX_EXIT_RDRAND:
2929 case VMX_EXIT_RDSEED:
2930 {
2931 /* Construct the VM-exit instruction information. */
2932 RTGCPTR GCPtrDisp;
2933 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2934
2935 /* Update the VM-exit instruction information. */
2936 ExitInfo.InstrInfo.u = uInstrInfo;
2937
2938 /* Update the VM-exit qualification. */
2939 ExitInfo.u64Qual = GCPtrDisp;
2940 break;
2941 }
2942
2943 default:
2944 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2945 break;
2946 }
2947
2948 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2949}
2950
2951
2952/**
2953 * Checks whether an I/O instruction for the given port is intercepted (causes a
2954 * VM-exit) or not.
2955 *
2956 * @returns @c true if the instruction is intercepted, @c false otherwise.
2957 * @param pVCpu The cross context virtual CPU structure.
2958 * @param u16Port The I/O port being accessed by the instruction.
2959 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
2960 */
2961IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
2962{
2963 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2964 Assert(pVmcs);
2965
2966 /*
2967 * Check whether the I/O instruction must cause a VM-exit or not.
2968 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2969 */
2970 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
2971 return true;
2972
2973 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
2974 {
2975 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
2976 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
2977 Assert(pbIoBitmapA);
2978 Assert(pbIoBitmapB);
2979 return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
2980 }
2981
2982 return false;
2983}
2984
2985
2986/**
2987 * VMX VM-exit handler for VM-exits due to INVLPG.
2988 *
2989 * @param pVCpu The cross context virtual CPU structure.
2990 * @param GCPtrPage The guest-linear address of the page being invalidated.
2991 * @param cbInstr The instruction length in bytes.
2992 */
2993IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2994{
2995 VMXVEXITINFO ExitInfo;
2996 RT_ZERO(ExitInfo);
2997 ExitInfo.uReason = VMX_EXIT_INVLPG;
2998 ExitInfo.cbInstr = cbInstr;
2999 ExitInfo.u64Qual = GCPtrPage;
3000 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3001
3002 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3003}
3004
3005
3006/**
3007 * VMX VM-exit handler for VM-exits due to LMSW.
3008 *
3009 * @returns Strict VBox status code.
3010 * @param pVCpu The cross context virtual CPU structure.
3011 * @param uGuestCr0 The current guest CR0.
3012 * @param pu16NewMsw The machine-status word specified in LMSW's source
3013 * operand. This will be updated depending on the VMX
3014 * guest/host CR0 mask if LMSW is not intercepted.
3015 * @param GCPtrEffDst The guest-linear address of the source operand in case
3016 * of a memory operand. For register operand, pass
3017 * NIL_RTGCPTR.
3018 * @param cbInstr The instruction length in bytes.
3019 */
3020IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3021 uint8_t cbInstr)
3022{
3023 /*
3024 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3025 *
3026 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3027 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3028 */
3029 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3030 Assert(pVmcs);
3031 Assert(pu16NewMsw);
3032
3033 bool fIntercept = false;
3034 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3035 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3036
3037 /*
3038 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3039 * CR0.PE case first, before the rest of the bits in the MSW.
3040 *
3041 * If CR0.PE is owned by the host and CR0.PE differs between the
3042 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3043 */
3044 if ( (fGstHostMask & X86_CR0_PE)
3045 && (*pu16NewMsw & X86_CR0_PE)
3046 && !(fReadShadow & X86_CR0_PE))
3047 fIntercept = true;
3048
3049 /*
3050 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3051 * bits differ between the MSW (source operand) and the read-shadow, we must
3052 * cause a VM-exit.
3053 */
3054 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3055 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3056 fIntercept = true;
3057
3058 if (fIntercept)
3059 {
3060 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3061
3062 VMXVEXITINFO ExitInfo;
3063 RT_ZERO(ExitInfo);
3064 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3065 ExitInfo.cbInstr = cbInstr;
3066
3067 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3068 if (fMemOperand)
3069 {
3070 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3071 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3072 }
3073
3074 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3075 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3076 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3077 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3078
3079 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3080 }
3081
3082 /*
3083 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3084 * CR0 guest/host mask must be left unmodified.
3085 *
3086 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3087 */
3088 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3089 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3090
3091 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3092}
3093
3094
3095/**
3096 * VMX VM-exit handler for VM-exits due to CLTS.
3097 *
3098 * @returns Strict VBox status code.
3099 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3100 * VM-exit but must not modify the guest CR0.TS bit.
3101 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3102 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3103 * CR0 fixed bits in VMX operation).
3104 * @param pVCpu The cross context virtual CPU structure.
3105 * @param cbInstr The instruction length in bytes.
3106 */
3107IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3108{
3109 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3110 Assert(pVmcs);
3111
3112 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3113 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3114
3115 /*
3116 * If CR0.TS is owned by the host:
3117 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3118 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3119 * CLTS instruction completes without clearing CR0.TS.
3120 *
3121 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3122 */
3123 if (fGstHostMask & X86_CR0_TS)
3124 {
3125 if (fReadShadow & X86_CR0_TS)
3126 {
3127 Log2(("clts: Guest intercept -> VM-exit\n"));
3128
3129 VMXVEXITINFO ExitInfo;
3130 RT_ZERO(ExitInfo);
3131 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3132 ExitInfo.cbInstr = cbInstr;
3133
3134 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3135 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3136 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3137 }
3138
3139 return VINF_VMX_MODIFIES_BEHAVIOR;
3140 }
3141
3142 /*
3143 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3144 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3145 */
3146 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3147}
3148
3149
3150/**
3151 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3152 * (CR0/CR4 write).
3153 *
3154 * @returns Strict VBox status code.
3155 * @param pVCpu The cross context virtual CPU structure.
3156 * @param iCrReg The control register (either CR0 or CR4).
3157 * @param uGuestCrX The current guest CR0/CR4.
3158 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3159 * if no VM-exit is caused.
3160 * @param iGReg The general register from which the CR0/CR4 value is
3161 * being loaded.
3162 * @param cbInstr The instruction length in bytes.
3163 */
3164IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3165 uint8_t cbInstr)
3166{
3167 Assert(puNewCrX);
3168 Assert(iCrReg == 0 || iCrReg == 4);
3169
3170 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3171 Assert(pVmcs);
3172
3173 uint64_t uGuestCrX;
3174 uint64_t fGstHostMask;
3175 uint64_t fReadShadow;
3176 if (iCrReg == 0)
3177 {
3178 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3179 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3180 fGstHostMask = pVmcs->u64Cr0Mask.u;
3181 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3182 }
3183 else
3184 {
3185 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3186 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3187 fGstHostMask = pVmcs->u64Cr4Mask.u;
3188 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3189 }
3190
3191 /*
3192 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3193 * corresponding bits differ between the source operand and the read-shadow,
3194 * we must cause a VM-exit.
3195 *
3196 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3197 */
3198 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3199 {
3200 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3201
3202 VMXVEXITINFO ExitInfo;
3203 RT_ZERO(ExitInfo);
3204 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3205 ExitInfo.cbInstr = cbInstr;
3206
3207 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3208 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3209 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3210 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3211 }
3212
3213 /*
3214 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3215 * must not be modified the instruction.
3216 *
3217 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3218 */
3219 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3220
3221 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3222}
3223
3224
3225/**
3226 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3227 *
3228 * @returns VBox strict status code.
3229 * @param pVCpu The cross context virtual CPU structure.
3230 * @param iGReg The general register to which the CR3 value is being stored.
3231 * @param cbInstr The instruction length in bytes.
3232 */
3233IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3234{
3235 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3236 Assert(pVmcs);
3237 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3238
3239 /*
3240 * If the CR3-store exiting control is set, we must cause a VM-exit.
3241 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3242 */
3243 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3244 {
3245 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3246
3247 VMXVEXITINFO ExitInfo;
3248 RT_ZERO(ExitInfo);
3249 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3250 ExitInfo.cbInstr = cbInstr;
3251
3252 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3254 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3255 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3256 }
3257
3258 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3259}
3260
3261
3262/**
3263 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3264 *
3265 * @returns VBox strict status code.
3266 * @param pVCpu The cross context virtual CPU structure.
3267 * @param uNewCr3 The new CR3 value.
3268 * @param iGReg The general register from which the CR3 value is being
3269 * loaded.
3270 * @param cbInstr The instruction length in bytes.
3271 */
3272IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3273{
3274 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3275 Assert(pVmcs);
3276
3277 /*
3278 * If the CR3-load exiting control is set and the new CR3 value does not
3279 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3280 *
3281 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3282 */
3283 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3284 {
3285 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3286 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3287
3288 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3289 {
3290 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3291 if (uNewCr3 != uCr3TargetValue)
3292 {
3293 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3294
3295 VMXVEXITINFO ExitInfo;
3296 RT_ZERO(ExitInfo);
3297 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3298 ExitInfo.cbInstr = cbInstr;
3299
3300 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3301 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3302 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3303 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3304 }
3305 }
3306 }
3307
3308 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3309}
3310
3311
3312/**
3313 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3314 *
3315 * @returns VBox strict status code.
3316 * @param pVCpu The cross context virtual CPU structure.
3317 * @param iGReg The general register to which the CR8 value is being stored.
3318 * @param cbInstr The instruction length in bytes.
3319 */
3320IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3321{
3322 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3323 Assert(pVmcs);
3324
3325 /*
3326 * If the CR8-store exiting control is set, we must cause a VM-exit.
3327 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3328 */
3329 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3330 {
3331 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3332
3333 VMXVEXITINFO ExitInfo;
3334 RT_ZERO(ExitInfo);
3335 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3336 ExitInfo.cbInstr = cbInstr;
3337
3338 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3339 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3340 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3341 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3342 }
3343
3344 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3345}
3346
3347
3348/**
3349 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3350 *
3351 * @returns VBox strict status code.
3352 * @param pVCpu The cross context virtual CPU structure.
3353 * @param iGReg The general register from which the CR8 value is being
3354 * loaded.
3355 * @param cbInstr The instruction length in bytes.
3356 */
3357IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3358{
3359 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3360 Assert(pVmcs);
3361
3362 /*
3363 * If the CR8-load exiting control is set, we must cause a VM-exit.
3364 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3365 */
3366 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3367 {
3368 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3369
3370 VMXVEXITINFO ExitInfo;
3371 RT_ZERO(ExitInfo);
3372 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3373 ExitInfo.cbInstr = cbInstr;
3374
3375 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3376 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3377 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3378 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3379 }
3380
3381 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3382}
3383
3384
3385/**
3386 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3387 * GReg,DRx' (DRx read).
3388 *
3389 * @returns VBox strict status code.
3390 * @param pVCpu The cross context virtual CPU structure.
3391 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3392 * VMXINSTRID_MOV_FROM_DRX).
3393 * @param iDrReg The debug register being accessed.
3394 * @param iGReg The general register to/from which the DRx value is being
3395 * store/loaded.
3396 * @param cbInstr The instruction length in bytes.
3397 */
3398IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3399 uint8_t cbInstr)
3400{
3401 Assert(iDrReg <= 7);
3402 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3403
3404 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3405 Assert(pVmcs);
3406
3407 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3408 {
3409 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3410 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3411 VMXVEXITINFO ExitInfo;
3412 RT_ZERO(ExitInfo);
3413 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3414 ExitInfo.cbInstr = cbInstr;
3415 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3416 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3417 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3418 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3419 }
3420
3421 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3422}
3423
3424
3425/**
3426 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3427 *
3428 * @returns VBox strict status code.
3429 * @param pVCpu The cross context virtual CPU structure.
3430 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3431 * VMXINSTRID_IO_OUT).
3432 * @param u16Port The I/O port being accessed.
3433 * @param fImm Whether the I/O port was encoded using an immediate operand
3434 * or the implicit DX register.
3435 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3436 * @param cbInstr The instruction length in bytes.
3437 */
3438IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3439 uint8_t cbInstr)
3440{
3441 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3442 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3443
3444 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3445 if (fIntercept)
3446 {
3447 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3448 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3449 VMXVEXITINFO ExitInfo;
3450 RT_ZERO(ExitInfo);
3451 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3452 ExitInfo.cbInstr = cbInstr;
3453 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3454 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3455 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3456 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3457 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3458 }
3459
3460 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3461}
3462
3463
3464/**
3465 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3466 *
3467 * @returns VBox strict status code.
3468 * @param pVCpu The cross context virtual CPU structure.
3469 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3470 * VMXINSTRID_IO_OUTS).
3471 * @param u16Port The I/O port being accessed.
3472 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3473 * @param fRep Whether the instruction has a REP prefix or not.
3474 * @param ExitInstrInfo The VM-exit instruction info. field.
3475 * @param cbInstr The instruction length in bytes.
3476 */
3477IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3478 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3479{
3480 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3481 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3482 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3483 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3484 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3485
3486 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3487 if (fIntercept)
3488 {
3489 /*
3490 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3491 */
3492 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3493 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3494 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3495 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3496 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3497
3498 uint32_t uDirection;
3499 uint64_t uGuestLinearAddr;
3500 if (uInstrId == VMXINSTRID_IO_INS)
3501 {
3502 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3503 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3504 }
3505 else
3506 {
3507 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3508 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3509 }
3510
3511 /*
3512 * If the segment is ununsable, the guest-linear address in undefined.
3513 * We shall clear it for consistency.
3514 *
3515 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3516 */
3517 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3518 uGuestLinearAddr = 0;
3519
3520 VMXVEXITINFO ExitInfo;
3521 RT_ZERO(ExitInfo);
3522 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3523 ExitInfo.cbInstr = cbInstr;
3524 ExitInfo.InstrInfo = ExitInstrInfo;
3525 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3526 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3527 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3528 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3529 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3530 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3531 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3532 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3533 }
3534
3535 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3536}
3537
3538
3539/**
3540 * VMX VM-exit handler for VM-exits due to MWAIT.
3541 *
3542 * @returns VBox strict status code.
3543 * @param pVCpu The cross context virtual CPU structure.
3544 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3545 * @param cbInstr The instruction length in bytes.
3546 */
3547IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3548{
3549 VMXVEXITINFO ExitInfo;
3550 RT_ZERO(ExitInfo);
3551 ExitInfo.uReason = VMX_EXIT_MWAIT;
3552 ExitInfo.cbInstr = cbInstr;
3553 ExitInfo.u64Qual = fMonitorHwArmed;
3554 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3555}
3556
3557
3558/**
3559 * VMX VM-exit handler for VM-exits due to PAUSE.
3560 *
3561 * @returns VBox strict status code.
3562 * @param pVCpu The cross context virtual CPU structure.
3563 * @param cbInstr The instruction length in bytes.
3564 */
3565IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3566{
3567 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3568 Assert(pVmcs);
3569
3570 /*
3571 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3572 * "PAUSE-loop exiting" control.
3573 *
3574 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3575 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3576 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3577 * a VM-exit.
3578 *
3579 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3580 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3581 */
3582 bool fIntercept = false;
3583 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3584 fIntercept = true;
3585 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3586 && pVCpu->iem.s.uCpl == 0)
3587 {
3588 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3589
3590 /*
3591 * A previous-PAUSE-tick value of 0 is used to identify the first time
3592 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3593 * consider this to be the first execution of PAUSE in a loop according
3594 * to the Intel.
3595 *
3596 * All subsequent records for the previous-PAUSE-tick we ensure that it
3597 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3598 */
3599 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3600 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3601 uint64_t const uTick = TMCpuTickGet(pVCpu);
3602 uint32_t const uPleGap = pVmcs->u32PleGap;
3603 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3604 if ( *puPrevPauseTick == 0
3605 || uTick - *puPrevPauseTick > uPleGap)
3606 *puFirstPauseLoopTick = uTick;
3607 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3608 fIntercept = true;
3609
3610 *puPrevPauseTick = uTick | 1;
3611 }
3612
3613 if (fIntercept)
3614 {
3615 VMXVEXITINFO ExitInfo;
3616 RT_ZERO(ExitInfo);
3617 ExitInfo.uReason = VMX_EXIT_PAUSE;
3618 ExitInfo.cbInstr = cbInstr;
3619 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3620 }
3621
3622 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3623}
3624
3625
3626/**
3627 * VMX VM-exit handler for VM-exits due to task switches.
3628 *
3629 * @returns VBox strict status code.
3630 * @param pVCpu The cross context virtual CPU structure.
3631 * @param enmTaskSwitch The cause of the task switch.
3632 * @param SelNewTss The selector of the new TSS.
3633 * @param cbInstr The instruction length in bytes.
3634 */
3635IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3636{
3637 /*
3638 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3639 *
3640 * If the the cause of the task switch is due to execution of CALL, IRET or the JMP
3641 * instruction or delivery of the exception generated by one of these instructions
3642 * lead to a task switch through a task gate in the IDT, we need to provide the
3643 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3644 * leaves the VM-exit instruction length field undefined.
3645 *
3646 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3647 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3648 */
3649 Assert(cbInstr <= 15);
3650
3651 uint8_t uType;
3652 switch (enmTaskSwitch)
3653 {
3654 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3655 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3656 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3657 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3658 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3659 }
3660
3661 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3662 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3663 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3664 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3665 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3666}
3667
3668
3669/**
3670 * VMX VM-exit handler for VM-exits due to external interrupts.
3671 *
3672 * @returns VBox strict status code.
3673 * @param pVCpu The cross context virtual CPU structure.
3674 * @param uVector The external interrupt vector.
3675 * @param fIntPending Whether the external interrupt is pending or
3676 * acknowdledged in the interrupt controller.
3677 */
3678IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3679{
3680 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3681 Assert(pVmcs);
3682
3683 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3684 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3685 {
3686 if (fIntPending)
3687 {
3688 /*
3689 * If the interrupt is pending and we don't need to acknowledge the
3690 * interrupt on VM-exit, cause the VM-exit immediately.
3691 *
3692 * See Intel spec 25.2 "Other Causes Of VM Exits".
3693 */
3694 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3695 {
3696 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3697 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3698 iemVmxVmcsSetExitQual(pVCpu, 0);
3699 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3700 }
3701
3702 /*
3703 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3704 * on VM-exit, postpone VM-exit til after the interrupt controller has been
3705 * acknowledged that the interrupt has been consumed.
3706 */
3707 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3708 }
3709
3710 /*
3711 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3712 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3713 * all set, we cause the VM-exit now. We need to record the external interrupt that
3714 * just occurred in the VM-exit interruption information field.
3715 *
3716 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3717 */
3718 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3719 {
3720 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3721 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3722 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3723 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3724 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3725 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3726 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3727 iemVmxVmcsSetExitQual(pVCpu, 0);
3728 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3729 }
3730 }
3731
3732 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3733}
3734
3735
3736/**
3737 * VMX VM-exit handler for interrupt-window VM-exits.
3738 *
3739 * @returns VBox strict status code.
3740 * @param pVCpu The cross context virtual CPU structure.
3741 */
3742IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3743{
3744 iemVmxVmcsSetExitQual(pVCpu, 0);
3745 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3746}
3747
3748
3749/**
3750 * VMX VM-exit handler for VM-exits due to delivery of an event.
3751 *
3752 * @returns VBox strict status code.
3753 * @param pVCpu The cross context virtual CPU structure.
3754 * @param uVector The interrupt / exception vector.
3755 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3756 * @param uErrCode The error code associated with the event.
3757 * @param uCr2 The CR2 value in case of a \#PF exception.
3758 * @param cbInstr The instruction length in bytes.
3759 */
3760IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3761 uint8_t cbInstr)
3762{
3763 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3764 Assert(pVmcs);
3765
3766 /*
3767 * If the event is being injected as part of VM-entry, it isn't subject to event
3768 * intercepts in the nested-guest. However, secondary exceptions that occur during
3769 * injection of any event -are- subject to event interception.
3770 *
3771 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3772 */
3773 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3774 {
3775 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3776 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3777 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3778 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3779 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3780 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3781 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3782 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3783 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3784
3785 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3786 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3787 }
3788
3789 /*
3790 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3791 * If not, the caller will continue delivery of the external interrupt as it would
3792 * normally.
3793 */
3794 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3795 {
3796 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3797 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3798 }
3799
3800 /*
3801 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3802 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3803 */
3804 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3805 bool fIntercept = false;
3806 bool fIsHwXcpt = false;
3807 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3808 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3809 {
3810 fIsHwXcpt = true;
3811 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3812 if (uVector == X86_XCPT_NMI)
3813 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3814 else
3815 {
3816 /* Page-faults are subject to masking using its error code. */
3817 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3818 if (uVector == X86_XCPT_PF)
3819 {
3820 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
3821 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
3822 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
3823 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
3824 }
3825
3826 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
3827 if (fXcptBitmap & RT_BIT(uVector))
3828 fIntercept = true;
3829 }
3830 }
3831 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3832
3833 /*
3834 * Now that we've determined whether the software interrupt or hardware exception
3835 * causes a VM-exit, we need to construct the relevant VM-exit information and
3836 * cause the VM-exit.
3837 */
3838 if (fIntercept)
3839 {
3840 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3841
3842 /* Construct the rest of the event related information fields and cause the VM-exit. */
3843 uint64_t uExitQual = 0;
3844 if (fIsHwXcpt)
3845 {
3846 if (uVector == X86_XCPT_PF)
3847 uExitQual = uCr2;
3848 else if (uVector == X86_XCPT_DB)
3849 {
3850 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
3851 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3852 }
3853 }
3854
3855 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3856 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3857 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3858 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3859 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3860 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3861 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3862 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3863 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3864 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3865 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3866
3867 /*
3868 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
3869 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3870 * length.
3871 */
3872 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3873 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3874 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3875 else
3876 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3877
3878 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3879 }
3880
3881 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3882}
3883
3884
3885/**
3886 * VMX VM-exit handler for VM-exits due to a triple fault.
3887 *
3888 * @returns VBox strict status code.
3889 * @param pVCpu The cross context virtual CPU structure.
3890 */
3891IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3892{
3893 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3894 Assert(pVmcs);
3895 iemVmxVmcsSetExitQual(pVCpu, 0);
3896 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
3897}
3898
3899
3900/**
3901 * VMX VM-exit handler for TPR virtualization.
3902 *
3903 * @returns VBox strict status code.
3904 * @param pVCpu The cross context virtual CPU structure.
3905 * @param cbInstr The instruction length in bytes.
3906 */
3907IEM_STATIC VBOXSTRICTRC iemVmxVmexitTprVirtualization(PVMCPU pVCpu, uint8_t cbInstr)
3908{
3909 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3910 Assert(pVmcs);
3911
3912 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
3913 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)); /* We don't support virtual-interrupt delivery yet. */
3914
3915 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
3916 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
3917
3918 /*
3919 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
3920 * See Intel spec. 29.1.2 "TPR Virtualization".
3921 */
3922 if (((uVTpr >> 4) & 0xf) < uTprThreshold)
3923 {
3924 Log2(("tpr_virt: uVTpr=%u uTprThreshold=%u -> VM-exit\n", uVTpr, uTprThreshold));
3925
3926 /*
3927 * This is a trap-like VM-exit. We pass the instruction length along in the VM-exit
3928 * instruction length field and let the VM-exit handler update the RIP when appropriate.
3929 * It will then clear the VM-exit instruction length field before completing the VM-exit.
3930 *
3931 * The VM-exit qualification must be cleared.
3932 */
3933 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3934 iemVmxVmcsSetExitQual(pVCpu, 0);
3935 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
3936 }
3937
3938 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3939}
3940
3941
3942/**
3943 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
3944 *
3945 * @param pVCpu The cross context virtual CPU structure.
3946 * @param pszInstr The VMX instruction name (for logging purposes).
3947 */
3948IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
3949{
3950 /*
3951 * Guest Control Registers, Debug Registers, and MSRs.
3952 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
3953 */
3954 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3955 const char *const pszFailure = "VM-exit";
3956 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
3957
3958 /* CR0 reserved bits. */
3959 {
3960 /* CR0 MB1 bits. */
3961 uint64_t u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
3962 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
3963 if (fUnrestrictedGuest)
3964 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
3965 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
3966 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
3967
3968 /* CR0 MBZ bits. */
3969 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
3970 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
3971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
3972
3973 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
3974 if ( !fUnrestrictedGuest
3975 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
3976 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
3977 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
3978 }
3979
3980 /* CR4 reserved bits. */
3981 {
3982 /* CR4 MB1 bits. */
3983 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
3984 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
3985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
3986
3987 /* CR4 MBZ bits. */
3988 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
3989 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
3990 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
3991 }
3992
3993 /* DEBUGCTL MSR. */
3994 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
3995 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
3996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
3997
3998 /* 64-bit CPU checks. */
3999 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4000 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4001 {
4002 if (fGstInLongMode)
4003 {
4004 /* PAE must be set. */
4005 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4006 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4007 { /* likely */ }
4008 else
4009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4010 }
4011 else
4012 {
4013 /* PCIDE should not be set. */
4014 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4015 { /* likely */ }
4016 else
4017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4018 }
4019
4020 /* CR3. */
4021 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4022 { /* likely */ }
4023 else
4024 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4025
4026 /* DR7. */
4027 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4028 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4030
4031 /* SYSENTER ESP and SYSENTER EIP. */
4032 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4033 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4034 { /* likely */ }
4035 else
4036 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4037 }
4038
4039 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4040 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4041
4042 /* PAT MSR. */
4043 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4044 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4046
4047 /* EFER MSR. */
4048 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4049 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4050 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4051 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4052
4053 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
4054 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
4055 if ( fGstInLongMode == fGstLma
4056 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4057 || fGstLma == fGstLme))
4058 { /* likely */ }
4059 else
4060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4061
4062 /* We don't support IA32_BNDCFGS MSR yet. */
4063 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4064
4065 NOREF(pszInstr);
4066 NOREF(pszFailure);
4067 return VINF_SUCCESS;
4068}
4069
4070
4071/**
4072 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4073 *
4074 * @param pVCpu The cross context virtual CPU structure.
4075 * @param pszInstr The VMX instruction name (for logging purposes).
4076 */
4077IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4078{
4079 /*
4080 * Segment registers.
4081 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4082 */
4083 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4084 const char *const pszFailure = "VM-exit";
4085 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4086 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4087 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4088
4089 /* Selectors. */
4090 if ( !fGstInV86Mode
4091 && !fUnrestrictedGuest
4092 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4094
4095 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4096 {
4097 CPUMSELREG SelReg;
4098 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4099 if (RT_LIKELY(rc == VINF_SUCCESS))
4100 { /* likely */ }
4101 else
4102 return rc;
4103
4104 /*
4105 * Virtual-8086 mode checks.
4106 */
4107 if (fGstInV86Mode)
4108 {
4109 /* Base address. */
4110 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4111 { /* likely */ }
4112 else
4113 {
4114 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4115 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4116 }
4117
4118 /* Limit. */
4119 if (SelReg.u32Limit == 0xffff)
4120 { /* likely */ }
4121 else
4122 {
4123 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4125 }
4126
4127 /* Attribute. */
4128 if (SelReg.Attr.u == 0xf3)
4129 { /* likely */ }
4130 else
4131 {
4132 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4134 }
4135
4136 /* We're done; move to checking the next segment. */
4137 continue;
4138 }
4139
4140 /* Checks done by 64-bit CPUs. */
4141 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4142 {
4143 /* Base address. */
4144 if ( iSegReg == X86_SREG_FS
4145 || iSegReg == X86_SREG_GS)
4146 {
4147 if (X86_IS_CANONICAL(SelReg.u64Base))
4148 { /* likely */ }
4149 else
4150 {
4151 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4153 }
4154 }
4155 else if (iSegReg == X86_SREG_CS)
4156 {
4157 if (!RT_HI_U32(SelReg.u64Base))
4158 { /* likely */ }
4159 else
4160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4161 }
4162 else
4163 {
4164 if ( SelReg.Attr.n.u1Unusable
4165 || !RT_HI_U32(SelReg.u64Base))
4166 { /* likely */ }
4167 else
4168 {
4169 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4171 }
4172 }
4173 }
4174
4175 /*
4176 * Checks outside Virtual-8086 mode.
4177 */
4178 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4179 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4180 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4181 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4182 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4183 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4184 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4185 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4186
4187 /* Code or usable segment. */
4188 if ( iSegReg == X86_SREG_CS
4189 || fUsable)
4190 {
4191 /* Reserved bits (bits 31:17 and bits 11:8). */
4192 if (!(SelReg.Attr.u & 0xfffe0f00))
4193 { /* likely */ }
4194 else
4195 {
4196 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4198 }
4199
4200 /* Descriptor type. */
4201 if (fCodeDataSeg)
4202 { /* likely */ }
4203 else
4204 {
4205 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
4206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4207 }
4208
4209 /* Present. */
4210 if (fPresent)
4211 { /* likely */ }
4212 else
4213 {
4214 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
4215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4216 }
4217
4218 /* Granularity. */
4219 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
4220 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
4221 { /* likely */ }
4222 else
4223 {
4224 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
4225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4226 }
4227 }
4228
4229 if (iSegReg == X86_SREG_CS)
4230 {
4231 /* Segment Type and DPL. */
4232 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4233 && fUnrestrictedGuest)
4234 {
4235 if (uDpl == 0)
4236 { /* likely */ }
4237 else
4238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
4239 }
4240 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4241 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4242 {
4243 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4244 if (uDpl == AttrSs.n.u2Dpl)
4245 { /* likely */ }
4246 else
4247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
4248 }
4249 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4250 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
4251 {
4252 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4253 if (uDpl <= AttrSs.n.u2Dpl)
4254 { /* likely */ }
4255 else
4256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
4257 }
4258 else
4259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
4260
4261 /* Def/Big. */
4262 if ( fGstInLongMode
4263 && fSegLong)
4264 {
4265 if (uDefBig == 0)
4266 { /* likely */ }
4267 else
4268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
4269 }
4270 }
4271 else if (iSegReg == X86_SREG_SS)
4272 {
4273 /* Segment Type. */
4274 if ( !fUsable
4275 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4276 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
4277 { /* likely */ }
4278 else
4279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
4280
4281 /* DPL. */
4282 if (fUnrestrictedGuest)
4283 {
4284 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
4285 { /* likely */ }
4286 else
4287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
4288 }
4289 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4290 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
4291 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
4292 {
4293 if (uDpl == 0)
4294 { /* likely */ }
4295 else
4296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
4297 }
4298 }
4299 else
4300 {
4301 /* DS, ES, FS, GS. */
4302 if (fUsable)
4303 {
4304 /* Segment type. */
4305 if (uSegType & X86_SEL_TYPE_ACCESSED)
4306 { /* likely */ }
4307 else
4308 {
4309 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
4310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4311 }
4312
4313 if ( !(uSegType & X86_SEL_TYPE_CODE)
4314 || (uSegType & X86_SEL_TYPE_READ))
4315 { /* likely */ }
4316 else
4317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
4318
4319 /* DPL. */
4320 if ( !fUnrestrictedGuest
4321 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
4322 {
4323 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
4324 { /* likely */ }
4325 else
4326 {
4327 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
4328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4329 }
4330 }
4331 }
4332 }
4333 }
4334
4335 /*
4336 * LDTR.
4337 */
4338 {
4339 CPUMSELREG Ldtr;
4340 Ldtr.Sel = pVmcs->GuestLdtr;
4341 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
4342 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
4343 Ldtr.Attr.u = pVmcs->u32GuestLdtrLimit;
4344
4345 if (!Ldtr.Attr.n.u1Unusable)
4346 {
4347 /* Selector. */
4348 if (!(Ldtr.Sel & X86_SEL_LDT))
4349 { /* likely */ }
4350 else
4351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
4352
4353 /* Base. */
4354 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4355 {
4356 if (X86_IS_CANONICAL(Ldtr.u64Base))
4357 { /* likely */ }
4358 else
4359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
4360 }
4361
4362 /* Attributes. */
4363 /* Reserved bits (bits 31:17 and bits 11:8). */
4364 if (!(Ldtr.Attr.u & 0xfffe0f00))
4365 { /* likely */ }
4366 else
4367 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
4368
4369 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
4370 { /* likely */ }
4371 else
4372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
4373
4374 if (!Ldtr.Attr.n.u1DescType)
4375 { /* likely */ }
4376 else
4377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
4378
4379 if (Ldtr.Attr.n.u1Present)
4380 { /* likely */ }
4381 else
4382 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
4383
4384 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
4385 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
4386 { /* likely */ }
4387 else
4388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
4389 }
4390 }
4391
4392 /*
4393 * TR.
4394 */
4395 {
4396 CPUMSELREG Tr;
4397 Tr.Sel = pVmcs->GuestTr;
4398 Tr.u32Limit = pVmcs->u32GuestTrLimit;
4399 Tr.u64Base = pVmcs->u64GuestTrBase.u;
4400 Tr.Attr.u = pVmcs->u32GuestTrLimit;
4401
4402 /* Selector. */
4403 if (!(Tr.Sel & X86_SEL_LDT))
4404 { /* likely */ }
4405 else
4406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
4407
4408 /* Base. */
4409 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4410 {
4411 if (X86_IS_CANONICAL(Tr.u64Base))
4412 { /* likely */ }
4413 else
4414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
4415 }
4416
4417 /* Attributes. */
4418 /* Reserved bits (bits 31:17 and bits 11:8). */
4419 if (!(Tr.Attr.u & 0xfffe0f00))
4420 { /* likely */ }
4421 else
4422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
4423
4424 if (!Tr.Attr.n.u1Unusable)
4425 { /* likely */ }
4426 else
4427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
4428
4429 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
4430 || ( !fGstInLongMode
4431 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
4432 { /* likely */ }
4433 else
4434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
4435
4436 if (!Tr.Attr.n.u1DescType)
4437 { /* likely */ }
4438 else
4439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
4440
4441 if (Tr.Attr.n.u1Present)
4442 { /* likely */ }
4443 else
4444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
4445
4446 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
4447 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
4448 { /* likely */ }
4449 else
4450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
4451 }
4452
4453 NOREF(pszInstr);
4454 NOREF(pszFailure);
4455 return VINF_SUCCESS;
4456}
4457
4458
4459/**
4460 * Checks guest GDTR and IDTR as part of VM-entry.
4461 *
4462 * @param pVCpu The cross context virtual CPU structure.
4463 * @param pszInstr The VMX instruction name (for logging purposes).
4464 */
4465IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
4466{
4467 /*
4468 * GDTR and IDTR.
4469 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
4470 */
4471 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4472 const char *const pszFailure = "VM-exit";
4473
4474 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4475 {
4476 /* Base. */
4477 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
4478 { /* likely */ }
4479 else
4480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
4481
4482 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
4483 { /* likely */ }
4484 else
4485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
4486 }
4487
4488 /* Limit. */
4489 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
4490 { /* likely */ }
4491 else
4492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
4493
4494 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
4495 { /* likely */ }
4496 else
4497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
4498
4499 NOREF(pszInstr);
4500 NOREF(pszFailure);
4501 return VINF_SUCCESS;
4502}
4503
4504
4505/**
4506 * Checks guest RIP and RFLAGS as part of VM-entry.
4507 *
4508 * @param pVCpu The cross context virtual CPU structure.
4509 * @param pszInstr The VMX instruction name (for logging purposes).
4510 */
4511IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
4512{
4513 /*
4514 * RIP and RFLAGS.
4515 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
4516 */
4517 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4518 const char *const pszFailure = "VM-exit";
4519 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4520
4521 /* RIP. */
4522 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4523 {
4524 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
4525 if ( !fGstInLongMode
4526 || !AttrCs.n.u1Long)
4527 {
4528 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
4529 { /* likely */ }
4530 else
4531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
4532 }
4533
4534 if ( fGstInLongMode
4535 && AttrCs.n.u1Long)
4536 {
4537 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
4538 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
4539 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
4540 { /* likely */ }
4541 else
4542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
4543 }
4544 }
4545
4546 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
4547 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
4548 : pVmcs->u64GuestRFlags.s.Lo;
4549 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
4550 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
4551 { /* likely */ }
4552 else
4553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
4554
4555 if ( fGstInLongMode
4556 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4557 {
4558 if (!(uGuestRFlags & X86_EFL_VM))
4559 { /* likely */ }
4560 else
4561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
4562 }
4563
4564 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
4565 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4566 {
4567 if (uGuestRFlags & X86_EFL_IF)
4568 { /* likely */ }
4569 else
4570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
4571 }
4572
4573 NOREF(pszInstr);
4574 NOREF(pszFailure);
4575 return VINF_SUCCESS;
4576}
4577
4578
4579/**
4580 * Checks guest non-register state as part of VM-entry.
4581 *
4582 * @param pVCpu The cross context virtual CPU structure.
4583 * @param pszInstr The VMX instruction name (for logging purposes).
4584 */
4585IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
4586{
4587 /*
4588 * Guest non-register state.
4589 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
4590 */
4591 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4592 const char *const pszFailure = "VM-exit";
4593
4594 /*
4595 * Activity state.
4596 */
4597 uint64_t const u64GuestVmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
4598 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
4599 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
4600 { /* likely */ }
4601 else
4602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
4603
4604 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
4605 if ( !AttrSs.n.u2Dpl
4606 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
4607 { /* likely */ }
4608 else
4609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
4610
4611 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
4612 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
4613 {
4614 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
4615 { /* likely */ }
4616 else
4617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
4618 }
4619
4620 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4621 {
4622 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4623 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
4624 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
4625 switch (pVmcs->u32GuestActivityState)
4626 {
4627 case VMX_VMCS_GUEST_ACTIVITY_HLT:
4628 {
4629 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
4630 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4631 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4632 && ( uVector == X86_XCPT_DB
4633 || uVector == X86_XCPT_MC))
4634 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
4635 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
4636 { /* likely */ }
4637 else
4638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
4639 break;
4640 }
4641
4642 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
4643 {
4644 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
4645 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
4646 && uVector == X86_XCPT_MC))
4647 { /* likely */ }
4648 else
4649 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
4650 break;
4651 }
4652
4653 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
4654 default:
4655 break;
4656 }
4657 }
4658
4659 /*
4660 * Interruptibility state.
4661 */
4662 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
4663 { /* likely */ }
4664 else
4665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
4666
4667 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4668 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4669 { /* likely */ }
4670 else
4671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
4672
4673 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
4674 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4675 { /* likely */ }
4676 else
4677 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
4678
4679 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
4680 {
4681 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
4682 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
4683 {
4684 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4685 { /* likely */ }
4686 else
4687 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
4688 }
4689 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
4690 {
4691 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
4692 { /* likely */ }
4693 else
4694 {
4695 /*
4696 * We don't support injecting NMIs when blocking-by-STI would be in effect.
4697 * We update the VM-exit qualification only when blocking-by-STI is set
4698 * without blocking-by-MovSS being set. Although in practise it does not
4699 * make much difference since the order of checks are implementation defined.
4700 */
4701 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
4702 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
4703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
4704 }
4705
4706 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
4707 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
4708 { /* likely */ }
4709 else
4710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
4711 }
4712 }
4713
4714 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
4715 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
4716 { /* likely */ }
4717 else
4718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
4719
4720 /* We don't support SGX yet. So enclave-interruption must not be set. */
4721 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
4722 { /* likely */ }
4723 else
4724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
4725
4726 /*
4727 * Pending debug exceptions.
4728 */
4729 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
4730 ? pVmcs->u64GuestPendingDbgXcpt.u
4731 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
4732 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
4733 { /* likely */ }
4734 else
4735 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
4736
4737 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
4738 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
4739 {
4740 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4741 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
4742 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
4744
4745 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
4746 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
4747 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
4748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
4749 }
4750
4751 /* We don't support RTM (Real-time Transactional Memory) yet. */
4752 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
4753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
4754
4755 /*
4756 * VMCS link pointer.
4757 */
4758 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
4759 {
4760 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
4761 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
4762 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
4763 { /* likely */ }
4764 else
4765 {
4766 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
4768 }
4769
4770 /* Validate the address. */
4771 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
4772 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
4773 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
4774 {
4775 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4776 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
4777 }
4778
4779 /* Read the VMCS-link pointer from guest memory. */
4780 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
4781 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
4782 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
4783 if (RT_FAILURE(rc))
4784 {
4785 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
4787 }
4788
4789 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
4790 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
4791 { /* likely */ }
4792 else
4793 {
4794 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4795 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
4796 }
4797
4798 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
4799 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
4800 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
4801 { /* likely */ }
4802 else
4803 {
4804 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
4805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
4806 }
4807
4808 /* Finally update our cache of the guest physical address of the shadow VMCS. */
4809 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
4810 }
4811
4812 NOREF(pszInstr);
4813 NOREF(pszFailure);
4814 return VINF_SUCCESS;
4815}
4816
4817
4818/**
4819 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
4820 * VM-entry.
4821 *
4822 * @returns @c true if all PDPTEs are valid, @c false otherwise.
4823 * @param pVCpu The cross context virtual CPU structure.
4824 * @param pszInstr The VMX instruction name (for logging purposes).
4825 * @param pVmcs Pointer to the virtual VMCS.
4826 */
4827IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
4828{
4829 /*
4830 * Check PDPTEs.
4831 * See Intel spec. 4.4.1 "PDPTE Registers".
4832 */
4833 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
4834 const char *const pszFailure = "VM-exit";
4835
4836 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
4837 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
4838 if (RT_SUCCESS(rc))
4839 {
4840 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
4841 {
4842 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
4843 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
4844 { /* likely */ }
4845 else
4846 {
4847 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4848 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
4849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4850 }
4851 }
4852 }
4853 else
4854 {
4855 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
4856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
4857 }
4858
4859 NOREF(pszFailure);
4860 return rc;
4861}
4862
4863
4864/**
4865 * Checks guest PDPTEs as part of VM-entry.
4866 *
4867 * @param pVCpu The cross context virtual CPU structure.
4868 * @param pszInstr The VMX instruction name (for logging purposes).
4869 */
4870IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
4871{
4872 /*
4873 * Guest PDPTEs.
4874 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
4875 */
4876 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4877 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4878
4879 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
4880 int rc;
4881 if ( !fGstInLongMode
4882 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
4883 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
4884 {
4885 /*
4886 * We don't support nested-paging for nested-guests yet.
4887 *
4888 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
4889 * rather we need to check the PDPTEs referenced by the guest CR3.
4890 */
4891 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
4892 }
4893 else
4894 rc = VINF_SUCCESS;
4895 return rc;
4896}
4897
4898
4899/**
4900 * Checks guest-state as part of VM-entry.
4901 *
4902 * @returns VBox status code.
4903 * @param pVCpu The cross context virtual CPU structure.
4904 * @param pszInstr The VMX instruction name (for logging purposes).
4905 */
4906IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
4907{
4908 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
4909 if (RT_SUCCESS(rc))
4910 {
4911 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
4912 if (RT_SUCCESS(rc))
4913 {
4914 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
4915 if (RT_SUCCESS(rc))
4916 {
4917 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
4918 if (RT_SUCCESS(rc))
4919 {
4920 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
4921 if (RT_SUCCESS(rc))
4922 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
4923 }
4924 }
4925 }
4926 }
4927 return rc;
4928}
4929
4930
4931/**
4932 * Checks if an interrupt-window exiting occurs immediately as part of VM-entry.
4933 *
4934 * @returns VBox status code.
4935 * @param pVCpu The cross context virtual CPU structure.
4936 * @param pszInstr The VMX instruction name (for logging purposes).
4937 *
4938 * @remarks This must be called after loading the guest-state and switching
4939 * page-tables as part of VM-entry!
4940 */
4941IEM_STATIC int iemVmxVmentryCheckIntWindowExit(PVMCPU pVCpu, const char *pszInstr)
4942{
4943 /*
4944 * An interrupt-window exit occurs immediately after VM-entry if interrupts
4945 * are enabled and the interrupt-window exit control is set.
4946 *
4947 * See Intel spec. 25.2 "Other Causes Of VM Exits".
4948 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
4949 */
4950 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4951 Assert(pVmcs);
4952
4953 if ( (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
4954 && pVCpu->cpum.GstCtx.eflags.Bits.u1IF
4955 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
4956 {
4957 Log(("%s: Interrupt-window detected during VM-entry -> VM-exit\n", pszInstr));
4958 return iemVmxVmexitIntWindow(pVCpu);
4959 }
4960
4961 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4962}
4963
4964
4965/**
4966 * Checks host-state as part of VM-entry.
4967 *
4968 * @returns VBox status code.
4969 * @param pVCpu The cross context virtual CPU structure.
4970 * @param pszInstr The VMX instruction name (for logging purposes).
4971 */
4972IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
4973{
4974 /*
4975 * Host Control Registers and MSRs.
4976 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
4977 */
4978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4979 const char * const pszFailure = "VMFail";
4980
4981 /* CR0 reserved bits. */
4982 {
4983 /* CR0 MB1 bits. */
4984 uint64_t const u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
4985 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
4986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
4987
4988 /* CR0 MBZ bits. */
4989 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
4990 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
4991 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
4992 }
4993
4994 /* CR4 reserved bits. */
4995 {
4996 /* CR4 MB1 bits. */
4997 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
4998 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
4999 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5000
5001 /* CR4 MBZ bits. */
5002 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
5003 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
5004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5005 }
5006
5007 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5008 {
5009 /* CR3 reserved bits. */
5010 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5011 { /* likely */ }
5012 else
5013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5014
5015 /* SYSENTER ESP and SYSENTER EIP. */
5016 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5017 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5018 { /* likely */ }
5019 else
5020 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5021 }
5022
5023 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5024 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5025
5026 /* PAT MSR. */
5027 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5028 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5029 { /* likely */ }
5030 else
5031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5032
5033 /* EFER MSR. */
5034 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5035 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5036 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5037 { /* likely */ }
5038 else
5039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5040
5041 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5042 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5043 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5044 if ( fHostInLongMode == fHostLma
5045 && fHostInLongMode == fHostLme)
5046 { /* likely */ }
5047 else
5048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5049
5050 /*
5051 * Host Segment and Descriptor-Table Registers.
5052 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5053 */
5054 /* Selector RPL and TI. */
5055 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5056 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5057 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5058 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5059 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5060 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5061 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5062 { /* likely */ }
5063 else
5064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5065
5066 /* CS and TR selectors cannot be 0. */
5067 if ( pVmcs->HostCs
5068 && pVmcs->HostTr)
5069 { /* likely */ }
5070 else
5071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5072
5073 /* SS cannot be 0 if 32-bit host. */
5074 if ( fHostInLongMode
5075 || pVmcs->HostSs)
5076 { /* likely */ }
5077 else
5078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5079
5080 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5081 {
5082 /* FS, GS, GDTR, IDTR, TR base address. */
5083 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5084 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5085 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5086 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5087 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5091 }
5092
5093 /*
5094 * Host address-space size for 64-bit CPUs.
5095 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5096 */
5097 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5098 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5099 {
5100 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5101
5102 /* Logical processor in IA-32e mode. */
5103 if (fCpuInLongMode)
5104 {
5105 if (fHostInLongMode)
5106 {
5107 /* PAE must be set. */
5108 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5109 { /* likely */ }
5110 else
5111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5112
5113 /* RIP must be canonical. */
5114 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5115 { /* likely */ }
5116 else
5117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5118 }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5121 }
5122 else
5123 {
5124 /* Logical processor is outside IA-32e mode. */
5125 if ( !fGstInLongMode
5126 && !fHostInLongMode)
5127 {
5128 /* PCIDE should not be set. */
5129 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5130 { /* likely */ }
5131 else
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5133
5134 /* The high 32-bits of RIP MBZ. */
5135 if (!pVmcs->u64HostRip.s.Hi)
5136 { /* likely */ }
5137 else
5138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5139 }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5142 }
5143 }
5144 else
5145 {
5146 /* Host address-space size for 32-bit CPUs. */
5147 if ( !fGstInLongMode
5148 && !fHostInLongMode)
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5152 }
5153
5154 NOREF(pszInstr);
5155 NOREF(pszFailure);
5156 return VINF_SUCCESS;
5157}
5158
5159
5160/**
5161 * Checks VM-entry controls fields as part of VM-entry.
5162 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
5163 *
5164 * @returns VBox status code.
5165 * @param pVCpu The cross context virtual CPU structure.
5166 * @param pszInstr The VMX instruction name (for logging purposes).
5167 */
5168IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
5169{
5170 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5171 const char * const pszFailure = "VMFail";
5172
5173 /* VM-entry controls. */
5174 VMXCTLSMSR EntryCtls;
5175 EntryCtls.u = CPUMGetGuestIa32VmxEntryCtls(pVCpu);
5176 if (~pVmcs->u32EntryCtls & EntryCtls.n.disallowed0)
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
5178
5179 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
5181
5182 /* Event injection. */
5183 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
5184 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
5185 {
5186 /* Type and vector. */
5187 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
5188 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
5189 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
5190 if ( !uRsvd
5191 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
5192 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
5196
5197 /* Exception error code. */
5198 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
5199 {
5200 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
5201 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
5202 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
5203 { /* likely */ }
5204 else
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
5206
5207 /* Exceptions that provide an error code. */
5208 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5209 && ( uVector == X86_XCPT_DF
5210 || uVector == X86_XCPT_TS
5211 || uVector == X86_XCPT_NP
5212 || uVector == X86_XCPT_SS
5213 || uVector == X86_XCPT_GP
5214 || uVector == X86_XCPT_PF
5215 || uVector == X86_XCPT_AC))
5216 { /* likely */ }
5217 else
5218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
5219
5220 /* Exception error-code reserved bits. */
5221 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
5225
5226 /* Injecting a software interrupt, software exception or privileged software exception. */
5227 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
5228 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
5229 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
5230 {
5231 /* Instruction length must be in the range 0-15. */
5232 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
5236
5237 /* Instruction length of 0 is allowed only when its CPU feature is present. */
5238 if ( pVmcs->u32EntryInstrLen == 0
5239 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
5241 }
5242 }
5243 }
5244
5245 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
5246 if (pVmcs->u32EntryMsrLoadCount)
5247 {
5248 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5249 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5250 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
5251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
5252 }
5253
5254 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
5255 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
5256
5257 NOREF(pszInstr);
5258 NOREF(pszFailure);
5259 return VINF_SUCCESS;
5260}
5261
5262
5263/**
5264 * Checks VM-exit controls fields as part of VM-entry.
5265 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
5266 *
5267 * @returns VBox status code.
5268 * @param pVCpu The cross context virtual CPU structure.
5269 * @param pszInstr The VMX instruction name (for logging purposes).
5270 */
5271IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
5272{
5273 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5274 const char * const pszFailure = "VMFail";
5275
5276 /* VM-exit controls. */
5277 VMXCTLSMSR ExitCtls;
5278 ExitCtls.u = CPUMGetGuestIa32VmxExitCtls(pVCpu);
5279 if (~pVmcs->u32ExitCtls & ExitCtls.n.disallowed0)
5280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
5281
5282 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
5283 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
5284
5285 /* Save preemption timer without activating it. */
5286 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
5287 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
5288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
5289
5290 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
5291 if (pVmcs->u32ExitMsrStoreCount)
5292 {
5293 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
5294 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5295 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
5297 }
5298
5299 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
5300 if (pVmcs->u32ExitMsrLoadCount)
5301 {
5302 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
5303 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5304 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
5305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
5306 }
5307
5308 NOREF(pszInstr);
5309 NOREF(pszFailure);
5310 return VINF_SUCCESS;
5311}
5312
5313
5314/**
5315 * Checks VM-execution controls fields as part of VM-entry.
5316 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5317 *
5318 * @returns VBox status code.
5319 * @param pVCpu The cross context virtual CPU structure.
5320 * @param pszInstr The VMX instruction name (for logging purposes).
5321 *
5322 * @remarks This may update secondary-processor based VM-execution control fields
5323 * in the current VMCS if necessary.
5324 */
5325IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
5326{
5327 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5328 const char * const pszFailure = "VMFail";
5329
5330 /* Pin-based VM-execution controls. */
5331 {
5332 VMXCTLSMSR PinCtls;
5333 PinCtls.u = CPUMGetGuestIa32VmxPinbasedCtls(pVCpu);
5334 if (~pVmcs->u32PinCtls & PinCtls.n.disallowed0)
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5336
5337 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
5338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5339 }
5340
5341 /* Processor-based VM-execution controls. */
5342 {
5343 VMXCTLSMSR ProcCtls;
5344 ProcCtls.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
5345 if (~pVmcs->u32ProcCtls & ProcCtls.n.disallowed0)
5346 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5347
5348 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5350 }
5351
5352 /* Secondary processor-based VM-execution controls. */
5353 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5354 {
5355 VMXCTLSMSR ProcCtls2;
5356 ProcCtls2.u = CPUMGetGuestIa32VmxProcbasedCtls2(pVCpu);
5357 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.disallowed0)
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5359
5360 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
5361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
5362 }
5363 else
5364 Assert(!pVmcs->u32ProcCtls2);
5365
5366 /* CR3-target count. */
5367 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
5371
5372 /* I/O bitmaps physical addresses. */
5373 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
5374 {
5375 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
5376 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5377 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
5378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
5379
5380 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
5381 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5382 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
5383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
5384 }
5385
5386 /* MSR bitmap physical address. */
5387 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
5388 {
5389 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
5390 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
5391 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5392 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
5393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
5394
5395 /* Read the MSR bitmap. */
5396 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
5397 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
5398 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
5399 if (RT_FAILURE(rc))
5400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
5401 }
5402
5403 /* TPR shadow related controls. */
5404 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5405 {
5406 /* Virtual-APIC page physical address. */
5407 RTGCPHYS GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
5408 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
5409 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5410 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
5411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
5412
5413 /* Read the Virtual-APIC page. */
5414 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
5415 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
5416 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
5417 if (RT_FAILURE(rc))
5418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
5419
5420 /* TPR threshold without virtual-interrupt delivery. */
5421 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5422 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
5423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
5424
5425 /* TPR threshold and VTPR. */
5426 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
5427 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
5428 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5429 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5430 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
5432 }
5433 else
5434 {
5435 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5436 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5437 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
5438 { /* likely */ }
5439 else
5440 {
5441 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
5443 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
5444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
5445 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
5447 }
5448 }
5449
5450 /* NMI exiting and virtual-NMIs. */
5451 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
5452 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
5454
5455 /* Virtual-NMIs and NMI-window exiting. */
5456 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5457 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
5459
5460 /* Virtualize APIC accesses. */
5461 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
5462 {
5463 /* APIC-access physical address. */
5464 RTGCPHYS GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
5465 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
5466 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5467 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
5468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
5469 }
5470
5471 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
5472 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
5473 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
5474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5475
5476 /* Virtual-interrupt delivery requires external interrupt exiting. */
5477 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5478 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
5480
5481 /* VPID. */
5482 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
5483 || pVmcs->u16Vpid != 0)
5484 { /* likely */ }
5485 else
5486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
5487
5488 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
5489 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
5490 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
5491 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
5492 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
5493 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
5494 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
5495
5496 /* VMCS shadowing. */
5497 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5498 {
5499 /* VMREAD-bitmap physical address. */
5500 RTGCPHYS GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
5501 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
5502 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5503 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
5504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
5505
5506 /* VMWRITE-bitmap physical address. */
5507 RTGCPHYS GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
5508 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
5509 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5510 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
5512
5513 /* Read the VMREAD-bitmap. */
5514 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
5515 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
5516 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5517 if (RT_FAILURE(rc))
5518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
5519
5520 /* Read the VMWRITE-bitmap. */
5521 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
5522 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
5523 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
5524 if (RT_FAILURE(rc))
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
5526 }
5527
5528 NOREF(pszInstr);
5529 NOREF(pszFailure);
5530 return VINF_SUCCESS;
5531}
5532
5533
5534/**
5535 * Loads the guest control registers, debug register and some MSRs as part of
5536 * VM-entry.
5537 *
5538 * @param pVCpu The cross context virtual CPU structure.
5539 */
5540IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
5541{
5542 /*
5543 * Load guest control registers, debug registers and MSRs.
5544 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
5545 */
5546 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5547 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
5548 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
5549 CPUMSetGuestCR0(pVCpu, uGstCr0);
5550 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
5551 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
5552
5553 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5554 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
5555
5556 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
5557 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
5558 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
5559
5560 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5561 {
5562 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
5563
5564 /* EFER MSR. */
5565 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
5566 {
5567 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5568 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
5569 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
5570 if (fGstInLongMode)
5571 {
5572 /* If the nested-guest is in long mode, LMA and LME are both set. */
5573 Assert(fGstPaging);
5574 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
5575 }
5576 else
5577 {
5578 /*
5579 * If the nested-guest is outside long mode:
5580 * - With paging: LMA is cleared, LME is cleared.
5581 * - Without paging: LMA is cleared, LME is left unmodified.
5582 */
5583 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
5584 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
5585 }
5586 }
5587 /* else: see below. */
5588 }
5589
5590 /* PAT MSR. */
5591 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5592 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
5593
5594 /* EFER MSR. */
5595 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5596 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
5597
5598 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5599 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5600
5601 /* We don't support IA32_BNDCFGS MSR yet. */
5602 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5603
5604 /* Nothing to do for SMBASE register - We don't support SMM yet. */
5605}
5606
5607
5608/**
5609 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
5610 *
5611 * @param pVCpu The cross context virtual CPU structure.
5612 */
5613IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
5614{
5615 /*
5616 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
5617 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
5618 */
5619 /* CS, SS, ES, DS, FS, GS. */
5620 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5621 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5622 {
5623 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5624 CPUMSELREG VmcsSelReg;
5625 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
5626 AssertRC(rc); NOREF(rc);
5627 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
5628 {
5629 pGstSelReg->Sel = VmcsSelReg.Sel;
5630 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5631 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5632 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5633 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5634 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5635 }
5636 else
5637 {
5638 pGstSelReg->Sel = VmcsSelReg.Sel;
5639 pGstSelReg->ValidSel = VmcsSelReg.Sel;
5640 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5641 switch (iSegReg)
5642 {
5643 case X86_SREG_CS:
5644 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5645 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
5646 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
5647 break;
5648
5649 case X86_SREG_SS:
5650 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
5651 pGstSelReg->u32Limit = 0;
5652 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
5653 break;
5654
5655 case X86_SREG_ES:
5656 case X86_SREG_DS:
5657 pGstSelReg->u64Base = 0;
5658 pGstSelReg->u32Limit = 0;
5659 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5660 break;
5661
5662 case X86_SREG_FS:
5663 case X86_SREG_GS:
5664 pGstSelReg->u64Base = VmcsSelReg.u64Base;
5665 pGstSelReg->u32Limit = 0;
5666 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
5667 break;
5668 }
5669 Assert(pGstSelReg->Attr.n.u1Unusable);
5670 }
5671 }
5672
5673 /* LDTR. */
5674 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
5675 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
5676 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5677 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
5678 {
5679 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5680 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5681 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5682 }
5683 else
5684 {
5685 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5686 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
5687 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5688 }
5689
5690 /* TR. */
5691 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
5692 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
5693 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
5694 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5695 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
5696 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
5697 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
5698
5699 /* GDTR. */
5700 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
5701 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
5702
5703 /* IDTR. */
5704 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
5705 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
5706}
5707
5708
5709/**
5710 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
5711 *
5712 * @returns VBox status code.
5713 * @param pVCpu The cross context virtual CPU structure.
5714 * @param pszInstr The VMX instruction name (for logging purposes).
5715 */
5716IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
5717{
5718 /*
5719 * Load guest MSRs.
5720 * See Intel spec. 26.4 "Loading MSRs".
5721 */
5722 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5723 const char *const pszFailure = "VM-exit";
5724
5725 /*
5726 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
5727 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
5728 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
5729 */
5730 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
5731 if (!cMsrs)
5732 return VINF_SUCCESS;
5733
5734 /*
5735 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
5736 * exceeded including possibly raising #MC exceptions during VMX transition. Our
5737 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
5738 */
5739 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
5740 if (fIsMsrCountValid)
5741 { /* likely */ }
5742 else
5743 {
5744 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
5745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
5746 }
5747
5748 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
5749 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
5750 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
5751 if (RT_SUCCESS(rc))
5752 {
5753 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
5754 Assert(pMsr);
5755 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
5756 {
5757 if ( !pMsr->u32Reserved
5758 && pMsr->u32Msr != MSR_K8_FS_BASE
5759 && pMsr->u32Msr != MSR_K8_GS_BASE
5760 && pMsr->u32Msr != MSR_K6_EFER
5761 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
5762 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
5763 {
5764 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
5765 if (rcStrict == VINF_SUCCESS)
5766 continue;
5767
5768 /*
5769 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
5770 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
5771 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
5772 * further by our own, specific diagnostic code. Later, we can try implement handling of the
5773 * MSR in ring-0 if possible, or come up with a better, generic solution.
5774 */
5775 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5776 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
5777 ? kVmxVDiag_Vmentry_MsrLoadRing3
5778 : kVmxVDiag_Vmentry_MsrLoad;
5779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5780 }
5781 else
5782 {
5783 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
5784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
5785 }
5786 }
5787 }
5788 else
5789 {
5790 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
5791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
5792 }
5793
5794 NOREF(pszInstr);
5795 NOREF(pszFailure);
5796 return VINF_SUCCESS;
5797}
5798
5799
5800/**
5801 * Loads the guest-state non-register state as part of VM-entry.
5802 *
5803 * @returns VBox status code.
5804 * @param pVCpu The cross context virtual CPU structure.
5805 *
5806 * @remarks This must be called only after loading the nested-guest register state
5807 * (especially nested-guest RIP).
5808 */
5809IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
5810{
5811 /*
5812 * Load guest non-register state.
5813 * See Intel spec. 26.6 "Special Features of VM Entry"
5814 */
5815 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5816 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
5817 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5818 {
5819 /** @todo NSTVMX: Pending debug exceptions. */
5820 Assert(!(pVmcs->u64GuestPendingDbgXcpt.u));
5821
5822 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
5823 {
5824 /** @todo NSTVMX: Virtual-NMIs doesn't affect NMI blocking in the normal sense.
5825 * We probably need a different force flag for virtual-NMI
5826 * pending/blocking. */
5827 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI));
5828 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
5829 }
5830 else
5831 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
5832
5833 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5834 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
5835 else
5836 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
5837
5838 /* SMI blocking is irrelevant. We don't support SMIs yet. */
5839 }
5840
5841 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
5842 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
5843
5844 /* VPID is irrelevant. We don't support VPID yet. */
5845
5846 /* Clear address-range monitoring. */
5847 EMMonitorWaitClear(pVCpu);
5848}
5849
5850
5851/**
5852 * Loads the guest-state as part of VM-entry.
5853 *
5854 * @returns VBox status code.
5855 * @param pVCpu The cross context virtual CPU structure.
5856 * @param pszInstr The VMX instruction name (for logging purposes).
5857 *
5858 * @remarks This must be done after all the necessary steps prior to loading of
5859 * guest-state (e.g. checking various VMCS state).
5860 */
5861IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
5862{
5863 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
5864 iemVmxVmentryLoadGuestSegRegs(pVCpu);
5865
5866 /*
5867 * Load guest RIP, RSP and RFLAGS.
5868 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
5869 */
5870 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5871 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
5872 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
5873 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
5874
5875 /* Initialize the PAUSE-loop controls as part of VM-entry. */
5876 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
5877 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
5878
5879 iemVmxVmentryLoadGuestNonRegState(pVCpu);
5880
5881 NOREF(pszInstr);
5882 return VINF_SUCCESS;
5883}
5884
5885
5886/**
5887 * Performs event injection (if any) as part of VM-entry.
5888 *
5889 * @param pVCpu The cross context virtual CPU structure.
5890 * @param pszInstr The VMX instruction name (for logging purposes).
5891 */
5892IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
5893{
5894 /*
5895 * Inject events.
5896 * See Intel spec. 26.5 "Event Injection".
5897 */
5898 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5899 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
5900 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
5901 {
5902 /*
5903 * The event that is going to be made pending for injection is not subject to VMX intercepts,
5904 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
5905 * of the current event -are- subject to intercepts, hence this flag will be flipped during
5906 * the actually delivery of this event.
5907 */
5908 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = false;
5909
5910 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
5911 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
5912 {
5913 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
5914 VMCPU_FF_SET(pVCpu, VMCPU_FF_MTF);
5915 return VINF_SUCCESS;
5916 }
5917
5918 int rc = HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
5919 pVCpu->cpum.GstCtx.cr2);
5920 AssertRCReturn(rc, rc);
5921 }
5922
5923 NOREF(pszInstr);
5924 return VINF_SUCCESS;
5925}
5926
5927
5928/**
5929 * VMLAUNCH/VMRESUME instruction execution worker.
5930 *
5931 * @returns Strict VBox status code.
5932 * @param pVCpu The cross context virtual CPU structure.
5933 * @param cbInstr The instruction length in bytes.
5934 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
5935 * VMXINSTRID_VMRESUME).
5936 * @param pExitInfo Pointer to the VM-exit instruction information struct.
5937 * Optional, can be NULL.
5938 *
5939 * @remarks Common VMX instruction checks are already expected to by the caller,
5940 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
5941 */
5942IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId, PCVMXVEXITINFO pExitInfo)
5943{
5944 Assert( uInstrId == VMXINSTRID_VMLAUNCH
5945 || uInstrId == VMXINSTRID_VMRESUME);
5946 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
5947
5948 /* Nested-guest intercept. */
5949 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5950 {
5951 if (pExitInfo)
5952 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
5953 uint32_t const uExitReason = uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH;
5954 return iemVmxVmexitInstrNeedsInfo(pVCpu, uExitReason, uInstrId, cbInstr);
5955 }
5956
5957 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
5958
5959 /* CPL. */
5960 if (pVCpu->iem.s.uCpl > 0)
5961 {
5962 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
5963 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
5964 return iemRaiseGeneralProtectionFault0(pVCpu);
5965 }
5966
5967 /* Current VMCS valid. */
5968 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
5969 {
5970 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
5971 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
5972 iemVmxVmFailInvalid(pVCpu);
5973 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5974 return VINF_SUCCESS;
5975 }
5976
5977 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
5978 * use block-by-STI here which is not quite correct. */
5979 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5980 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
5981 {
5982 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
5983 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
5984 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
5985 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5986 return VINF_SUCCESS;
5987 }
5988
5989 if (uInstrId == VMXINSTRID_VMLAUNCH)
5990 {
5991 /* VMLAUNCH with non-clear VMCS. */
5992 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
5993 { /* likely */ }
5994 else
5995 {
5996 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
5997 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
5998 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
5999 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6000 return VINF_SUCCESS;
6001 }
6002 }
6003 else
6004 {
6005 /* VMRESUME with non-launched VMCS. */
6006 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
6007 { /* likely */ }
6008 else
6009 {
6010 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
6011 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
6012 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
6013 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6014 return VINF_SUCCESS;
6015 }
6016 }
6017
6018 /*
6019 * Load the current VMCS.
6020 */
6021 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6022 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
6023 IEM_VMX_GET_CURRENT_VMCS(pVCpu), VMX_V_VMCS_SIZE);
6024 if (RT_FAILURE(rc))
6025 {
6026 Log(("%s: Failed to read VMCS at %#RGp, rc=%Rrc\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu), rc));
6027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrReadPhys;
6028 return rc;
6029 }
6030
6031 /*
6032 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
6033 * while entering VMX non-root mode. We do some of this while checking VM-execution
6034 * controls. The guest hypervisor should not make assumptions and cannot expect
6035 * predictable behavior if changes to these structures are made in guest memory while
6036 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
6037 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
6038 *
6039 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6040 */
6041 rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
6042 if (RT_SUCCESS(rc))
6043 {
6044 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
6045 if (RT_SUCCESS(rc))
6046 {
6047 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
6048 if (RT_SUCCESS(rc))
6049 {
6050 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
6051 if (RT_SUCCESS(rc))
6052 {
6053 /* Save the guest force-flags as VM-exits can occur from this point on. */
6054 iemVmxVmentrySaveForceFlags(pVCpu);
6055
6056 /* Initialize the VM-exit qualification field as it MBZ for VM-exits where it isn't specified. */
6057 iemVmxVmcsSetExitQual(pVCpu, 0);
6058
6059 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
6060 if (RT_SUCCESS(rc))
6061 {
6062 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
6063 if (RT_SUCCESS(rc))
6064 {
6065 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
6066 if (RT_SUCCESS(rc))
6067 {
6068 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
6069
6070 /* VMLAUNCH instruction must update the VMCS launch state. */
6071 if (uInstrId == VMXINSTRID_VMLAUNCH)
6072 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
6073
6074 /* Perform the VMX transition (PGM updates). */
6075 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
6076 if (rcStrict == VINF_SUCCESS)
6077 { /* likely */ }
6078 else if (RT_SUCCESS(rcStrict))
6079 {
6080 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
6081 VBOXSTRICTRC_VAL(rcStrict)));
6082 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6083 }
6084 else
6085 {
6086 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
6087 return rcStrict;
6088 }
6089
6090 /* We've now entered nested-guest execution. */
6091 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
6092
6093 /** The priority of potential VM-exits during VM-entry is important. */
6094 /** @todo NSTVMX: Any debug trap exceptions must be handled here. */
6095 /** @todo NSTVMX: VMX preemption timer exiting. */
6096 /** @todo NSTVMX: TPR thresholding exiting. */
6097 /** @todo NSTVMX: NMI-window exiting. */
6098
6099 /* Check premature interrupt-window exiting. */
6100 rc = iemVmxVmentryCheckIntWindowExit(pVCpu, pszInstr);
6101 if (rc == VINF_VMX_INTERCEPT_NOT_ACTIVE)
6102 { /* likely */ }
6103 else if (rc == VINF_VMX_VMEXIT)
6104 return VINF_SUCCESS;
6105
6106 /** @todo NSTVMX: Pending MTF exiting. */
6107
6108 /* Now that we've switched page tables, we can inject events if any. */
6109 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
6110
6111 return VINF_SUCCESS;
6112 }
6113 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
6114 }
6115 }
6116 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
6117 }
6118
6119 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
6120 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6121 return VINF_SUCCESS;
6122 }
6123 }
6124 }
6125
6126 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
6127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6128 return VINF_SUCCESS;
6129}
6130
6131
6132/**
6133 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
6134 * (causes a VM-exit) or not.
6135 *
6136 * @returns @c true if the instruction is intercepted, @c false otherwise.
6137 * @param pVCpu The cross context virtual CPU structure.
6138 * @param uExitReason The VM-exit exit reason (VMX_EXIT_RDMSR or
6139 * VMX_EXIT_WRMSR).
6140 * @param idMsr The MSR.
6141 */
6142IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
6143{
6144 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6145 Assert( uExitReason == VMX_EXIT_RDMSR
6146 || uExitReason == VMX_EXIT_WRMSR);
6147
6148 /* Consult the MSR bitmap if the feature is supported. */
6149 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6150 Assert(pVmcs);
6151 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6152 {
6153 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6154 if (uExitReason == VMX_EXIT_RDMSR)
6155 {
6156 VMXMSREXITREAD enmRead;
6157 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
6158 NULL /* penmWrite */);
6159 AssertRC(rc);
6160 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
6161 return true;
6162 }
6163 else
6164 {
6165 VMXMSREXITWRITE enmWrite;
6166 int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
6167 &enmWrite);
6168 AssertRC(rc);
6169 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
6170 return true;
6171 }
6172 return false;
6173 }
6174
6175 /* Without MSR bitmaps, all MSR accesses are intercepted. */
6176 return true;
6177}
6178
6179
6180/**
6181 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
6182 * intercepted (causes a VM-exit) or not.
6183 *
6184 * @returns @c true if the instruction is intercepted, @c false otherwise.
6185 * @param pVCpu The cross context virtual CPU structure.
6186 * @param u64FieldEnc The VMCS field encoding.
6187 * @param uExitReason The VM-exit exit reason (VMX_EXIT_VMREAD or
6188 * VMX_EXIT_VMREAD).
6189 */
6190IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
6191{
6192 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
6193 Assert( uExitReason == VMX_EXIT_VMREAD
6194 || uExitReason == VMX_EXIT_VMWRITE);
6195
6196 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
6197 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
6198 return true;
6199
6200 /*
6201 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
6202 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
6203 */
6204 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
6205 return true;
6206
6207 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
6208 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
6209 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6210 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6211 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
6212 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
6213 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
6214 pbBitmap += (u32FieldEnc >> 3);
6215 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
6216 return true;
6217
6218 return false;
6219}
6220
6221
6222/**
6223 * VMREAD common (memory/register) instruction execution worker
6224 *
6225 * @returns Strict VBox status code.
6226 * @param pVCpu The cross context virtual CPU structure.
6227 * @param cbInstr The instruction length in bytes.
6228 * @param pu64Dst Where to write the VMCS value (only updated when
6229 * VINF_SUCCESS is returned).
6230 * @param u64FieldEnc The VMCS field encoding.
6231 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6232 * be NULL.
6233 */
6234IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6235 PCVMXVEXITINFO pExitInfo)
6236{
6237 /* Nested-guest intercept. */
6238 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6239 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
6240 {
6241 if (pExitInfo)
6242 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6243 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
6244 }
6245
6246 /* CPL. */
6247 if (pVCpu->iem.s.uCpl > 0)
6248 {
6249 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6250 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
6251 return iemRaiseGeneralProtectionFault0(pVCpu);
6252 }
6253
6254 /* VMCS pointer in root mode. */
6255 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6256 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6257 {
6258 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6259 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
6260 iemVmxVmFailInvalid(pVCpu);
6261 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6262 return VINF_SUCCESS;
6263 }
6264
6265 /* VMCS-link pointer in non-root mode. */
6266 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6267 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6268 {
6269 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6270 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
6271 iemVmxVmFailInvalid(pVCpu);
6272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6273 return VINF_SUCCESS;
6274 }
6275
6276 /* Supported VMCS field. */
6277 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6278 {
6279 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6280 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
6281 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
6282 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6283 return VINF_SUCCESS;
6284 }
6285
6286 /*
6287 * Setup reading from the current or shadow VMCS.
6288 */
6289 uint8_t *pbVmcs;
6290 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6291 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6292 else
6293 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6294 Assert(pbVmcs);
6295
6296 VMXVMCSFIELDENC FieldEnc;
6297 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6298 uint8_t const uWidth = FieldEnc.n.u2Width;
6299 uint8_t const uType = FieldEnc.n.u2Type;
6300 uint8_t const uWidthType = (uWidth << 2) | uType;
6301 uint8_t const uIndex = FieldEnc.n.u8Index;
6302 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6303 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6304
6305 /*
6306 * Read the VMCS component based on the field's effective width.
6307 *
6308 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6309 * indicates high bits (little endian).
6310 *
6311 * Note! The caller is responsible to trim the result and update registers
6312 * or memory locations are required. Here we just zero-extend to the largest
6313 * type (i.e. 64-bits).
6314 */
6315 uint8_t *pbField = pbVmcs + offField;
6316 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6317 switch (uEffWidth)
6318 {
6319 case VMX_VMCS_ENC_WIDTH_64BIT:
6320 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
6321 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
6322 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
6323 }
6324 return VINF_SUCCESS;
6325}
6326
6327
6328/**
6329 * VMREAD (64-bit register) instruction execution worker.
6330 *
6331 * @returns Strict VBox status code.
6332 * @param pVCpu The cross context virtual CPU structure.
6333 * @param cbInstr The instruction length in bytes.
6334 * @param pu64Dst Where to store the VMCS field's value.
6335 * @param u64FieldEnc The VMCS field encoding.
6336 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6337 * be NULL.
6338 */
6339IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
6340 PCVMXVEXITINFO pExitInfo)
6341{
6342 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
6343 if (rcStrict == VINF_SUCCESS)
6344 {
6345 iemVmxVmreadSuccess(pVCpu, cbInstr);
6346 return VINF_SUCCESS;
6347 }
6348
6349 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6350 return rcStrict;
6351}
6352
6353
6354/**
6355 * VMREAD (32-bit register) instruction execution worker.
6356 *
6357 * @returns Strict VBox status code.
6358 * @param pVCpu The cross context virtual CPU structure.
6359 * @param cbInstr The instruction length in bytes.
6360 * @param pu32Dst Where to store the VMCS field's value.
6361 * @param u32FieldEnc The VMCS field encoding.
6362 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6363 * be NULL.
6364 */
6365IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
6366 PCVMXVEXITINFO pExitInfo)
6367{
6368 uint64_t u64Dst;
6369 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
6370 if (rcStrict == VINF_SUCCESS)
6371 {
6372 *pu32Dst = u64Dst;
6373 iemVmxVmreadSuccess(pVCpu, cbInstr);
6374 return VINF_SUCCESS;
6375 }
6376
6377 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6378 return rcStrict;
6379}
6380
6381
6382/**
6383 * VMREAD (memory) instruction execution worker.
6384 *
6385 * @returns Strict VBox status code.
6386 * @param pVCpu The cross context virtual CPU structure.
6387 * @param cbInstr The instruction length in bytes.
6388 * @param iEffSeg The effective segment register to use with @a u64Val.
6389 * Pass UINT8_MAX if it is a register access.
6390 * @param enmEffAddrMode The effective addressing mode (only used with memory
6391 * operand).
6392 * @param GCPtrDst The guest linear address to store the VMCS field's
6393 * value.
6394 * @param u64FieldEnc The VMCS field encoding.
6395 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6396 * be NULL.
6397 */
6398IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
6399 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6400{
6401 uint64_t u64Dst;
6402 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
6403 if (rcStrict == VINF_SUCCESS)
6404 {
6405 /*
6406 * Write the VMCS field's value to the location specified in guest-memory.
6407 *
6408 * The pointer size depends on the address size (address-size prefix allowed).
6409 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
6410 */
6411 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6412 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6413 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
6414
6415 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6416 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6417 else
6418 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
6419 if (rcStrict == VINF_SUCCESS)
6420 {
6421 iemVmxVmreadSuccess(pVCpu, cbInstr);
6422 return VINF_SUCCESS;
6423 }
6424
6425 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
6426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
6427 return rcStrict;
6428 }
6429
6430 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6431 return rcStrict;
6432}
6433
6434
6435/**
6436 * VMWRITE instruction execution worker.
6437 *
6438 * @returns Strict VBox status code.
6439 * @param pVCpu The cross context virtual CPU structure.
6440 * @param cbInstr The instruction length in bytes.
6441 * @param iEffSeg The effective segment register to use with @a u64Val.
6442 * Pass UINT8_MAX if it is a register access.
6443 * @param enmEffAddrMode The effective addressing mode (only used with memory
6444 * operand).
6445 * @param u64Val The value to write (or guest linear address to the
6446 * value), @a iEffSeg will indicate if it's a memory
6447 * operand.
6448 * @param u64FieldEnc The VMCS field encoding.
6449 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6450 * be NULL.
6451 */
6452IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
6453 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
6454{
6455 /* Nested-guest intercept. */
6456 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6457 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
6458 {
6459 if (pExitInfo)
6460 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6461 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
6462 }
6463
6464 /* CPL. */
6465 if (pVCpu->iem.s.uCpl > 0)
6466 {
6467 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
6469 return iemRaiseGeneralProtectionFault0(pVCpu);
6470 }
6471
6472 /* VMCS pointer in root mode. */
6473 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
6474 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6475 {
6476 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
6478 iemVmxVmFailInvalid(pVCpu);
6479 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6480 return VINF_SUCCESS;
6481 }
6482
6483 /* VMCS-link pointer in non-root mode. */
6484 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6485 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
6486 {
6487 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
6488 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
6489 iemVmxVmFailInvalid(pVCpu);
6490 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6491 return VINF_SUCCESS;
6492 }
6493
6494 /* If the VMWRITE instruction references memory, access the specified memory operand. */
6495 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
6496 if (!fIsRegOperand)
6497 {
6498 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
6499 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
6500 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
6501
6502 /* Read the value from the specified guest memory location. */
6503 VBOXSTRICTRC rcStrict;
6504 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6505 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
6506 else
6507 {
6508 uint32_t u32Val;
6509 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
6510 u64Val = u32Val;
6511 }
6512 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6513 {
6514 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
6515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
6516 return rcStrict;
6517 }
6518 }
6519 else
6520 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
6521
6522 /* Supported VMCS field. */
6523 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
6524 {
6525 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
6526 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
6527 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
6528 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6529 return VINF_SUCCESS;
6530 }
6531
6532 /* Read-only VMCS field. */
6533 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
6534 if ( fIsFieldReadOnly
6535 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
6536 {
6537 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
6538 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
6539 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
6540 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6541 return VINF_SUCCESS;
6542 }
6543
6544 /*
6545 * Setup writing to the current or shadow VMCS.
6546 */
6547 uint8_t *pbVmcs;
6548 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6549 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
6550 else
6551 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6552 Assert(pbVmcs);
6553
6554 VMXVMCSFIELDENC FieldEnc;
6555 FieldEnc.u = RT_LO_U32(u64FieldEnc);
6556 uint8_t const uWidth = FieldEnc.n.u2Width;
6557 uint8_t const uType = FieldEnc.n.u2Type;
6558 uint8_t const uWidthType = (uWidth << 2) | uType;
6559 uint8_t const uIndex = FieldEnc.n.u8Index;
6560 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
6561 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
6562
6563 /*
6564 * Write the VMCS component based on the field's effective width.
6565 *
6566 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
6567 * indicates high bits (little endian).
6568 */
6569 uint8_t *pbField = pbVmcs + offField;
6570 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
6571 switch (uEffWidth)
6572 {
6573 case VMX_VMCS_ENC_WIDTH_64BIT:
6574 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
6575 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
6576 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
6577 }
6578
6579 iemVmxVmSucceed(pVCpu);
6580 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6581 return VINF_SUCCESS;
6582}
6583
6584
6585/**
6586 * VMCLEAR instruction execution worker.
6587 *
6588 * @returns Strict VBox status code.
6589 * @param pVCpu The cross context virtual CPU structure.
6590 * @param cbInstr The instruction length in bytes.
6591 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6592 * @param GCPtrVmcs The linear address of the VMCS pointer.
6593 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6594 * be NULL.
6595 *
6596 * @remarks Common VMX instruction checks are already expected to by the caller,
6597 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6598 */
6599IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6600 PCVMXVEXITINFO pExitInfo)
6601{
6602 /* Nested-guest intercept. */
6603 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6604 {
6605 if (pExitInfo)
6606 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6607 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
6608 }
6609
6610 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6611
6612 /* CPL. */
6613 if (pVCpu->iem.s.uCpl > 0)
6614 {
6615 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6616 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
6617 return iemRaiseGeneralProtectionFault0(pVCpu);
6618 }
6619
6620 /* Get the VMCS pointer from the location specified by the source memory operand. */
6621 RTGCPHYS GCPhysVmcs;
6622 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6623 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6624 {
6625 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
6627 return rcStrict;
6628 }
6629
6630 /* VMCS pointer alignment. */
6631 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6632 {
6633 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
6634 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
6635 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6636 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6637 return VINF_SUCCESS;
6638 }
6639
6640 /* VMCS physical-address width limits. */
6641 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6642 {
6643 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6644 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
6645 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6646 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6647 return VINF_SUCCESS;
6648 }
6649
6650 /* VMCS is not the VMXON region. */
6651 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6652 {
6653 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6654 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
6655 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
6656 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6657 return VINF_SUCCESS;
6658 }
6659
6660 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6661 restriction imposed by our implementation. */
6662 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6663 {
6664 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
6665 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
6666 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
6667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6668 return VINF_SUCCESS;
6669 }
6670
6671 /*
6672 * VMCLEAR allows committing and clearing any valid VMCS pointer.
6673 *
6674 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
6675 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
6676 * to 'clear'.
6677 */
6678 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
6679 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
6680 {
6681 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
6682 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6683 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
6684 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6685 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
6686 }
6687 else
6688 {
6689 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPtrVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
6690 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
6691 }
6692
6693 iemVmxVmSucceed(pVCpu);
6694 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6695 return rcStrict;
6696}
6697
6698
6699/**
6700 * VMPTRST instruction execution worker.
6701 *
6702 * @returns Strict VBox status code.
6703 * @param pVCpu The cross context virtual CPU structure.
6704 * @param cbInstr The instruction length in bytes.
6705 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
6706 * @param GCPtrVmcs The linear address of where to store the current VMCS
6707 * pointer.
6708 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6709 * be NULL.
6710 *
6711 * @remarks Common VMX instruction checks are already expected to by the caller,
6712 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6713 */
6714IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6715 PCVMXVEXITINFO pExitInfo)
6716{
6717 /* Nested-guest intercept. */
6718 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6719 {
6720 if (pExitInfo)
6721 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6722 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
6723 }
6724
6725 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6726
6727 /* CPL. */
6728 if (pVCpu->iem.s.uCpl > 0)
6729 {
6730 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6731 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
6732 return iemRaiseGeneralProtectionFault0(pVCpu);
6733 }
6734
6735 /* Set the VMCS pointer to the location specified by the destination memory operand. */
6736 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
6737 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
6738 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6739 {
6740 iemVmxVmSucceed(pVCpu);
6741 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6742 return rcStrict;
6743 }
6744
6745 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6746 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
6747 return rcStrict;
6748}
6749
6750
6751/**
6752 * VMPTRLD instruction execution worker.
6753 *
6754 * @returns Strict VBox status code.
6755 * @param pVCpu The cross context virtual CPU structure.
6756 * @param cbInstr The instruction length in bytes.
6757 * @param GCPtrVmcs The linear address of the current VMCS pointer.
6758 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
6759 * be NULL.
6760 *
6761 * @remarks Common VMX instruction checks are already expected to by the caller,
6762 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6763 */
6764IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
6765 PCVMXVEXITINFO pExitInfo)
6766{
6767 /* Nested-guest intercept. */
6768 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6769 {
6770 if (pExitInfo)
6771 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6772 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
6773 }
6774
6775 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6776
6777 /* CPL. */
6778 if (pVCpu->iem.s.uCpl > 0)
6779 {
6780 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6781 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
6782 return iemRaiseGeneralProtectionFault0(pVCpu);
6783 }
6784
6785 /* Get the VMCS pointer from the location specified by the source memory operand. */
6786 RTGCPHYS GCPhysVmcs;
6787 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
6788 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6789 {
6790 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
6791 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
6792 return rcStrict;
6793 }
6794
6795 /* VMCS pointer alignment. */
6796 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
6797 {
6798 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
6799 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
6800 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6801 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6802 return VINF_SUCCESS;
6803 }
6804
6805 /* VMCS physical-address width limits. */
6806 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6807 {
6808 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
6809 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
6810 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6811 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6812 return VINF_SUCCESS;
6813 }
6814
6815 /* VMCS is not the VMXON region. */
6816 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
6817 {
6818 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
6819 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
6820 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
6821 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6822 return VINF_SUCCESS;
6823 }
6824
6825 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
6826 restriction imposed by our implementation. */
6827 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
6828 {
6829 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
6830 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
6831 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
6832 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6833 return VINF_SUCCESS;
6834 }
6835
6836 /* Read the VMCS revision ID from the VMCS. */
6837 VMXVMCSREVID VmcsRevId;
6838 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
6839 if (RT_FAILURE(rc))
6840 {
6841 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
6842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
6843 return rc;
6844 }
6845
6846 /* Verify the VMCS revision specified by the guest matches what we reported to the guest,
6847 also check VMCS shadowing feature. */
6848 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
6849 || ( VmcsRevId.n.fIsShadowVmcs
6850 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
6851 {
6852 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
6853 {
6854 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFail()\n", VMX_V_VMCS_REVISION_ID,
6855 VmcsRevId.n.u31RevisionId));
6856 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
6857 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6858 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6859 return VINF_SUCCESS;
6860 }
6861
6862 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
6863 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
6864 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
6865 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6866 return VINF_SUCCESS;
6867 }
6868
6869 /*
6870 * We only maintain only the current VMCS in our virtual CPU context (CPUMCTX). Therefore,
6871 * VMPTRLD shall always flush any existing current VMCS back to guest memory before loading
6872 * a new VMCS as current.
6873 */
6874 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
6875 {
6876 iemVmxCommitCurrentVmcsToMemory(pVCpu);
6877 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
6878 }
6879
6880 iemVmxVmSucceed(pVCpu);
6881 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6882 return VINF_SUCCESS;
6883}
6884
6885
6886/**
6887 * VMXON instruction execution worker.
6888 *
6889 * @returns Strict VBox status code.
6890 * @param pVCpu The cross context virtual CPU structure.
6891 * @param cbInstr The instruction length in bytes.
6892 * @param iEffSeg The effective segment register to use with @a
6893 * GCPtrVmxon.
6894 * @param GCPtrVmxon The linear address of the VMXON pointer.
6895 * @param pExitInfo Pointer to the VM-exit instruction information struct.
6896 * Optional, can be NULL.
6897 *
6898 * @remarks Common VMX instruction checks are already expected to by the caller,
6899 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6900 */
6901IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
6902 PCVMXVEXITINFO pExitInfo)
6903{
6904#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
6905 RT_NOREF5(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
6906 return VINF_EM_RAW_EMULATE_INSTR;
6907#else
6908 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
6909 {
6910 /* CPL. */
6911 if (pVCpu->iem.s.uCpl > 0)
6912 {
6913 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6914 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
6915 return iemRaiseGeneralProtectionFault0(pVCpu);
6916 }
6917
6918 /* A20M (A20 Masked) mode. */
6919 if (!PGMPhysIsA20Enabled(pVCpu))
6920 {
6921 Log(("vmxon: A20M mode -> #GP(0)\n"));
6922 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
6923 return iemRaiseGeneralProtectionFault0(pVCpu);
6924 }
6925
6926 /* CR0. */
6927 {
6928 /* CR0 MB1 bits. */
6929 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
6930 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
6931 {
6932 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
6933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
6934 return iemRaiseGeneralProtectionFault0(pVCpu);
6935 }
6936
6937 /* CR0 MBZ bits. */
6938 uint64_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
6939 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
6940 {
6941 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
6942 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
6943 return iemRaiseGeneralProtectionFault0(pVCpu);
6944 }
6945 }
6946
6947 /* CR4. */
6948 {
6949 /* CR4 MB1 bits. */
6950 uint64_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
6951 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
6952 {
6953 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
6954 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
6955 return iemRaiseGeneralProtectionFault0(pVCpu);
6956 }
6957
6958 /* CR4 MBZ bits. */
6959 uint64_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
6960 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
6961 {
6962 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
6963 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
6964 return iemRaiseGeneralProtectionFault0(pVCpu);
6965 }
6966 }
6967
6968 /* Feature control MSR's LOCK and VMXON bits. */
6969 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatureControl(pVCpu);
6970 if (!(uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON)))
6971 {
6972 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
6973 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
6974 return iemRaiseGeneralProtectionFault0(pVCpu);
6975 }
6976
6977 /* Get the VMXON pointer from the location specified by the source memory operand. */
6978 RTGCPHYS GCPhysVmxon;
6979 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
6980 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
6981 {
6982 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
6983 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
6984 return rcStrict;
6985 }
6986
6987 /* VMXON region pointer alignment. */
6988 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
6989 {
6990 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
6991 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
6992 iemVmxVmFailInvalid(pVCpu);
6993 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6994 return VINF_SUCCESS;
6995 }
6996
6997 /* VMXON physical-address width limits. */
6998 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6999 {
7000 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
7001 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
7002 iemVmxVmFailInvalid(pVCpu);
7003 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7004 return VINF_SUCCESS;
7005 }
7006
7007 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
7008 restriction imposed by our implementation. */
7009 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
7010 {
7011 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
7012 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
7013 iemVmxVmFailInvalid(pVCpu);
7014 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7015 return VINF_SUCCESS;
7016 }
7017
7018 /* Read the VMCS revision ID from the VMXON region. */
7019 VMXVMCSREVID VmcsRevId;
7020 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
7021 if (RT_FAILURE(rc))
7022 {
7023 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
7024 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
7025 return rc;
7026 }
7027
7028 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7029 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
7030 {
7031 /* Revision ID mismatch. */
7032 if (!VmcsRevId.n.fIsShadowVmcs)
7033 {
7034 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
7035 VmcsRevId.n.u31RevisionId));
7036 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
7037 iemVmxVmFailInvalid(pVCpu);
7038 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7039 return VINF_SUCCESS;
7040 }
7041
7042 /* Shadow VMCS disallowed. */
7043 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
7044 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
7045 iemVmxVmFailInvalid(pVCpu);
7046 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7047 return VINF_SUCCESS;
7048 }
7049
7050 /*
7051 * Record that we're in VMX operation, block INIT, block and disable A20M.
7052 */
7053 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
7054 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7055 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
7056
7057 /* Clear address-range monitoring. */
7058 EMMonitorWaitClear(pVCpu);
7059 /** @todo NSTVMX: Intel PT. */
7060
7061 iemVmxVmSucceed(pVCpu);
7062 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7063# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7064 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7065# else
7066 return VINF_SUCCESS;
7067# endif
7068 }
7069 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7070 {
7071 /* Nested-guest intercept. */
7072 if (pExitInfo)
7073 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7074 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
7075 }
7076
7077 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7078
7079 /* CPL. */
7080 if (pVCpu->iem.s.uCpl > 0)
7081 {
7082 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7083 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
7084 return iemRaiseGeneralProtectionFault0(pVCpu);
7085 }
7086
7087 /* VMXON when already in VMX root mode. */
7088 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
7089 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
7090 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7091 return VINF_SUCCESS;
7092#endif
7093}
7094
7095
7096/**
7097 * Implements 'VMXOFF'.
7098 *
7099 * @remarks Common VMX instruction checks are already expected to by the caller,
7100 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7101 */
7102IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
7103{
7104# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7105 RT_NOREF2(pVCpu, cbInstr);
7106 return VINF_EM_RAW_EMULATE_INSTR;
7107# else
7108 /* Nested-guest intercept. */
7109 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7110 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
7111
7112 /* CPL. */
7113 if (pVCpu->iem.s.uCpl > 0)
7114 {
7115 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7116 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
7117 return iemRaiseGeneralProtectionFault0(pVCpu);
7118 }
7119
7120 /* Dual monitor treatment of SMIs and SMM. */
7121 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
7122 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
7123 {
7124 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
7125 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7126 return VINF_SUCCESS;
7127 }
7128
7129 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
7130 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
7131 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
7132
7133 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
7134 { /** @todo NSTVMX: Unblock SMI. */ }
7135
7136 EMMonitorWaitClear(pVCpu);
7137 /** @todo NSTVMX: Unblock and enable A20M. */
7138
7139 iemVmxVmSucceed(pVCpu);
7140 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7141# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7142 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
7143# else
7144 return VINF_SUCCESS;
7145# endif
7146# endif
7147}
7148
7149
7150/**
7151 * Implements 'VMXON'.
7152 */
7153IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
7154{
7155 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
7156}
7157
7158
7159/**
7160 * Implements 'VMLAUNCH'.
7161 */
7162IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
7163{
7164 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH, NULL /* pExitInfo */);
7165}
7166
7167
7168/**
7169 * Implements 'VMRESUME'.
7170 */
7171IEM_CIMPL_DEF_0(iemCImpl_vmresume)
7172{
7173 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME, NULL /* pExitInfo */);
7174}
7175
7176
7177/**
7178 * Implements 'VMPTRLD'.
7179 */
7180IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7181{
7182 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7183}
7184
7185
7186/**
7187 * Implements 'VMPTRST'.
7188 */
7189IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7190{
7191 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7192}
7193
7194
7195/**
7196 * Implements 'VMCLEAR'.
7197 */
7198IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
7199{
7200 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
7201}
7202
7203
7204/**
7205 * Implements 'VMWRITE' register.
7206 */
7207IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
7208{
7209 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
7210 NULL /* pExitInfo */);
7211}
7212
7213
7214/**
7215 * Implements 'VMWRITE' memory.
7216 */
7217IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
7218{
7219 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
7220}
7221
7222
7223/**
7224 * Implements 'VMREAD' 64-bit register.
7225 */
7226IEM_CIMPL_DEF_2(iemCImpl_vmread64_reg, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
7227{
7228 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
7229}
7230
7231
7232/**
7233 * Implements 'VMREAD' 32-bit register.
7234 */
7235IEM_CIMPL_DEF_2(iemCImpl_vmread32_reg, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
7236{
7237 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
7238}
7239
7240
7241/**
7242 * Implements 'VMREAD' memory.
7243 */
7244IEM_CIMPL_DEF_4(iemCImpl_vmread_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
7245{
7246 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
7247}
7248
7249
7250/**
7251 * Implements VMX's implementation of PAUSE.
7252 */
7253IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
7254{
7255 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7256 {
7257 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
7258 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7259 return rcStrict;
7260 }
7261
7262 /*
7263 * Outside VMX non-root operation or if the PAUSE instruction does not cause
7264 * a VM-exit, the instruction operates normally.
7265 */
7266 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7267 return VINF_SUCCESS;
7268}
7269
7270#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
7271
7272
7273/**
7274 * Implements 'VMCALL'.
7275 */
7276IEM_CIMPL_DEF_0(iemCImpl_vmcall)
7277{
7278#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7279 /* Nested-guest intercept. */
7280 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7281 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
7282#endif
7283
7284 /* Join forces with vmmcall. */
7285 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
7286}
7287
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette