VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 75573

Last change on this file since 75573 was 75565, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 More Virtual-APIC bits. Implement TPR, PPR, EOI virtualization. Not yet implemented full APIC-register virtualization.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 75565 2018-11-19 11:08:58Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
20/** @todo NSTVMX: The following VM-exit intercepts are pending:
21 * VMX_EXIT_IO_SMI
22 * VMX_EXIT_SMI
23 * VMX_EXIT_INT_WINDOW
24 * VMX_EXIT_NMI_WINDOW
25 * VMX_EXIT_GETSEC
26 * VMX_EXIT_RSM
27 * VMX_EXIT_MTF
28 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
29 * VMX_EXIT_ERR_MACHINE_CHECK
30 * VMX_EXIT_TPR_BELOW_THRESHOLD
31 * VMX_EXIT_APIC_ACCESS
32 * VMX_EXIT_VIRTUALIZED_EOI
33 * VMX_EXIT_EPT_VIOLATION
34 * VMX_EXIT_EPT_MISCONFIG
35 * VMX_EXIT_INVEPT
36 * VMX_EXIT_PREEMPT_TIMER
37 * VMX_EXIT_INVVPID
38 * VMX_EXIT_APIC_WRITE
39 * VMX_EXIT_RDRAND
40 * VMX_EXIT_VMFUNC
41 * VMX_EXIT_ENCLS
42 * VMX_EXIT_RDSEED
43 * VMX_EXIT_PML_FULL
44 * VMX_EXIT_XSAVES
45 * VMX_EXIT_XRSTORS
46 */
47
48/**
49 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
50 *
51 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
52 * second dimension is the Index, see VMXVMCSFIELDENC.
53 */
54uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
55{
56 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
57 {
58 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
59 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
60 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
61 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
62 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
63 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
64 },
65 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
66 {
67 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
68 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
69 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
70 /* 24-25 */ UINT16_MAX, UINT16_MAX
71 },
72 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
73 {
74 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
75 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
76 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
77 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
78 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
79 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
80 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
81 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
82 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
83 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
84 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
85 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
86 },
87 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
88 {
89 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
90 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
91 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
92 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
93 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
94 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
95 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
96 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
97 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
98 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
99 },
100 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
101 {
102 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
103 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
104 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
105 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
106 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
107 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
108 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
109 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
110 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
111 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
112 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
113 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
114 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
115 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
116 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
117 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
118 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
119 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
120 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
121 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
122 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
123 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
124 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
125 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
126 /* 24 */ UINT16_MAX,
127 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
128 },
129 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
130 {
131 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
132 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
133 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
134 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
135 /* 25 */ UINT16_MAX
136 },
137 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
138 {
139 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
140 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
141 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
142 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
143 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
144 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
145 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
146 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
147 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
148 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
149 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
150 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
151 },
152 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
153 {
154 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
155 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
156 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
157 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
158 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
159 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
160 },
161 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
162 {
163 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
164 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
165 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
166 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
167 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
168 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
169 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
170 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
171 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
172 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
173 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
174 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
175 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
176 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
177 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
178 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
179 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
180 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
181 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
182 },
183 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
184 {
185 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
186 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
187 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
188 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
189 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
190 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
191 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
192 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
193 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
194 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
195 /* 24-25 */ UINT16_MAX, UINT16_MAX
196 },
197 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
198 {
199 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
200 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
201 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
202 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
203 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
204 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
205 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
206 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
207 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
208 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
209 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
210 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
211 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
212 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
213 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
214 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
215 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
216 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
217 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
218 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
219 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
220 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
221 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
222 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
223 /* 24-25 */ UINT16_MAX, UINT16_MAX
224 },
225 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
226 {
227 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
228 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
230 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 25 */ UINT16_MAX
232 },
233 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
234 {
235 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
236 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
237 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
238 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
239 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
240 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
241 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
242 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
243 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 24-25 */ UINT16_MAX, UINT16_MAX
246 },
247 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
248 {
249 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
250 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
251 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
252 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
253 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
254 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
255 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
256 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
258 },
259 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
268 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
269 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
270 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
271 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
272 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
273 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
274 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
275 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
276 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
277 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
278 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
279 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
280 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
281 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
282 },
283 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
284 {
285 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
286 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
287 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
288 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
289 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
290 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
291 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
292 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
293 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
294 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
295 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
296 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
297 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
298 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
299 }
300};
301
302
303/**
304 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
305 * relative offsets.
306 */
307# ifdef IEM_WITH_CODE_TLB
308# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
309# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
310# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
311# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
312# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
313# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
314# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
315# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
316# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
317# else /* !IEM_WITH_CODE_TLB */
318# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
319 do \
320 { \
321 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
322 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
323 } while (0)
324
325# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
326
327# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
328 do \
329 { \
330 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
331 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
332 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
333 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
334 } while (0)
335
336# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
337 do \
338 { \
339 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
340 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
341 } while (0)
342
343# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
344 do \
345 { \
346 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
347 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
348 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
349 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
350 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
351 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
352 } while (0)
353
354# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
355 do \
356 { \
357 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
358 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
359 } while (0)
360
361# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
362 do \
363 { \
364 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
365 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
366 } while (0)
367
368# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
369 do \
370 { \
371 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
372 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
373 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
374 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
375 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
376 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
377 } while (0)
378# endif /* !IEM_WITH_CODE_TLB */
379
380/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
381#define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
382
383/** Whether a shadow VMCS is present for the given VCPU. */
384#define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
385
386/** Gets the VMXON region pointer. */
387#define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
388
389/** Gets the guest-physical address of the current VMCS for the given VCPU. */
390#define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
391
392/** Whether a current VMCS is present for the given VCPU. */
393#define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
394
395/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
396#define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
397 do \
398 { \
399 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
400 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
401 } while (0)
402
403/** Clears any current VMCS for the given VCPU. */
404#define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
405 do \
406 { \
407 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
408 } while (0)
409
410/** Check for VMX instructions requiring to be in VMX operation.
411 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
412#define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
413 do \
414 { \
415 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
416 { /* likely */ } \
417 else \
418 { \
419 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
420 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
421 return iemRaiseUndefinedOpcode(a_pVCpu); \
422 } \
423 } while (0)
424
425/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
426#define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
427 do \
428 { \
429 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
430 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
431 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
432 return VERR_VMX_VMENTRY_FAILED; \
433 } while (0)
434
435/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
436#define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
437 do \
438 { \
439 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
440 HMVmxGetDiagDesc(a_VmxDiag), (a_pszFailure))); \
441 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
442 return VERR_VMX_VMEXIT_FAILED; \
443 } while (0)
444
445
446/**
447 * Returns whether the given VMCS field is valid and supported by our emulation.
448 *
449 * @param pVCpu The cross context virtual CPU structure.
450 * @param u64FieldEnc The VMCS field encoding.
451 *
452 * @remarks This takes into account the CPU features exposed to the guest.
453 */
454IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
455{
456 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
457 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
458 if (!uFieldEncHi)
459 { /* likely */ }
460 else
461 return false;
462
463 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
464 switch (uFieldEncLo)
465 {
466 /*
467 * 16-bit fields.
468 */
469 /* Control fields. */
470 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
471 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
472 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
473
474 /* Guest-state fields. */
475 case VMX_VMCS16_GUEST_ES_SEL:
476 case VMX_VMCS16_GUEST_CS_SEL:
477 case VMX_VMCS16_GUEST_SS_SEL:
478 case VMX_VMCS16_GUEST_DS_SEL:
479 case VMX_VMCS16_GUEST_FS_SEL:
480 case VMX_VMCS16_GUEST_GS_SEL:
481 case VMX_VMCS16_GUEST_LDTR_SEL:
482 case VMX_VMCS16_GUEST_TR_SEL:
483 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
484 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
485
486 /* Host-state fields. */
487 case VMX_VMCS16_HOST_ES_SEL:
488 case VMX_VMCS16_HOST_CS_SEL:
489 case VMX_VMCS16_HOST_SS_SEL:
490 case VMX_VMCS16_HOST_DS_SEL:
491 case VMX_VMCS16_HOST_FS_SEL:
492 case VMX_VMCS16_HOST_GS_SEL:
493 case VMX_VMCS16_HOST_TR_SEL: return true;
494
495 /*
496 * 64-bit fields.
497 */
498 /* Control fields. */
499 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
500 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
501 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
502 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
503 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
504 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
505 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
506 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
507 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
508 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
509 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
510 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
511 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
512 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
513 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
514 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
515 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
516 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
517 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
518 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
519 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
520 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
521 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
522 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
523 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
524 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
525 case VMX_VMCS64_CTRL_EPTP_FULL:
526 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
527 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
532 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
533 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
534 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
535 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
536 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
537 {
538 uint64_t const uVmFuncMsr = CPUMGetGuestIa32VmxVmFunc(pVCpu);
539 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
540 }
541 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
542 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
543 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
545 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
546 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
547 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
548 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
549 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
550 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
551 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
552 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
553
554 /* Read-only data fields. */
555 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
556 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
557
558 /* Guest-state fields. */
559 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
560 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
561 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
562 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
563 case VMX_VMCS64_GUEST_PAT_FULL:
564 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
565 case VMX_VMCS64_GUEST_EFER_FULL:
566 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
567 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
568 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
569 case VMX_VMCS64_GUEST_PDPTE0_FULL:
570 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
571 case VMX_VMCS64_GUEST_PDPTE1_FULL:
572 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
573 case VMX_VMCS64_GUEST_PDPTE2_FULL:
574 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
575 case VMX_VMCS64_GUEST_PDPTE3_FULL:
576 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
577 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
578 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
579
580 /* Host-state fields. */
581 case VMX_VMCS64_HOST_PAT_FULL:
582 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
583 case VMX_VMCS64_HOST_EFER_FULL:
584 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
585 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
586 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
587
588 /*
589 * 32-bit fields.
590 */
591 /* Control fields. */
592 case VMX_VMCS32_CTRL_PIN_EXEC:
593 case VMX_VMCS32_CTRL_PROC_EXEC:
594 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
595 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
596 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
597 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
598 case VMX_VMCS32_CTRL_EXIT:
599 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
600 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
601 case VMX_VMCS32_CTRL_ENTRY:
602 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
603 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
604 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
605 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
606 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
607 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
608 case VMX_VMCS32_CTRL_PLE_GAP:
609 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
610
611 /* Read-only data fields. */
612 case VMX_VMCS32_RO_VM_INSTR_ERROR:
613 case VMX_VMCS32_RO_EXIT_REASON:
614 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
615 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
616 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
617 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
618 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
619 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
620
621 /* Guest-state fields. */
622 case VMX_VMCS32_GUEST_ES_LIMIT:
623 case VMX_VMCS32_GUEST_CS_LIMIT:
624 case VMX_VMCS32_GUEST_SS_LIMIT:
625 case VMX_VMCS32_GUEST_DS_LIMIT:
626 case VMX_VMCS32_GUEST_FS_LIMIT:
627 case VMX_VMCS32_GUEST_GS_LIMIT:
628 case VMX_VMCS32_GUEST_LDTR_LIMIT:
629 case VMX_VMCS32_GUEST_TR_LIMIT:
630 case VMX_VMCS32_GUEST_GDTR_LIMIT:
631 case VMX_VMCS32_GUEST_IDTR_LIMIT:
632 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
638 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
639 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
640 case VMX_VMCS32_GUEST_INT_STATE:
641 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
642 case VMX_VMCS32_GUEST_SMBASE:
643 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
644 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
645
646 /* Host-state fields. */
647 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
648
649 /*
650 * Natural-width fields.
651 */
652 /* Control fields. */
653 case VMX_VMCS_CTRL_CR0_MASK:
654 case VMX_VMCS_CTRL_CR4_MASK:
655 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
656 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
658 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
659 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
660 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
661
662 /* Read-only data fields. */
663 case VMX_VMCS_RO_EXIT_QUALIFICATION:
664 case VMX_VMCS_RO_IO_RCX:
665 case VMX_VMCS_RO_IO_RSX:
666 case VMX_VMCS_RO_IO_RDI:
667 case VMX_VMCS_RO_IO_RIP:
668 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
669
670 /* Guest-state fields. */
671 case VMX_VMCS_GUEST_CR0:
672 case VMX_VMCS_GUEST_CR3:
673 case VMX_VMCS_GUEST_CR4:
674 case VMX_VMCS_GUEST_ES_BASE:
675 case VMX_VMCS_GUEST_CS_BASE:
676 case VMX_VMCS_GUEST_SS_BASE:
677 case VMX_VMCS_GUEST_DS_BASE:
678 case VMX_VMCS_GUEST_FS_BASE:
679 case VMX_VMCS_GUEST_GS_BASE:
680 case VMX_VMCS_GUEST_LDTR_BASE:
681 case VMX_VMCS_GUEST_TR_BASE:
682 case VMX_VMCS_GUEST_GDTR_BASE:
683 case VMX_VMCS_GUEST_IDTR_BASE:
684 case VMX_VMCS_GUEST_DR7:
685 case VMX_VMCS_GUEST_RSP:
686 case VMX_VMCS_GUEST_RIP:
687 case VMX_VMCS_GUEST_RFLAGS:
688 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
689 case VMX_VMCS_GUEST_SYSENTER_ESP:
690 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
691
692 /* Host-state fields. */
693 case VMX_VMCS_HOST_CR0:
694 case VMX_VMCS_HOST_CR3:
695 case VMX_VMCS_HOST_CR4:
696 case VMX_VMCS_HOST_FS_BASE:
697 case VMX_VMCS_HOST_GS_BASE:
698 case VMX_VMCS_HOST_TR_BASE:
699 case VMX_VMCS_HOST_GDTR_BASE:
700 case VMX_VMCS_HOST_IDTR_BASE:
701 case VMX_VMCS_HOST_SYSENTER_ESP:
702 case VMX_VMCS_HOST_SYSENTER_EIP:
703 case VMX_VMCS_HOST_RSP:
704 case VMX_VMCS_HOST_RIP: return true;
705 }
706
707 return false;
708}
709
710
711/**
712 * Gets a host selector from the VMCS.
713 *
714 * @param pVmcs Pointer to the virtual VMCS.
715 * @param iSelReg The index of the segment register (X86_SREG_XXX).
716 */
717DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
718{
719 Assert(iSegReg < X86_SREG_COUNT);
720 RTSEL HostSel;
721 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
722 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
723 uint8_t const uWidthType = (uWidth << 2) | uType;
724 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
725 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
726 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
727 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
728 uint8_t const *pbField = pbVmcs + offField;
729 HostSel = *(uint16_t *)pbField;
730 return HostSel;
731}
732
733
734/**
735 * Sets a guest segment register in the VMCS.
736 *
737 * @param pVmcs Pointer to the virtual VMCS.
738 * @param iSegReg The index of the segment register (X86_SREG_XXX).
739 * @param pSelReg Pointer to the segment register.
740 */
741IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
742{
743 Assert(pSelReg);
744 Assert(iSegReg < X86_SREG_COUNT);
745
746 /* Selector. */
747 {
748 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
749 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
750 uint8_t const uWidthType = (uWidth << 2) | uType;
751 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
752 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
753 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
754 uint8_t *pbVmcs = (uint8_t *)pVmcs;
755 uint8_t *pbField = pbVmcs + offField;
756 *(uint16_t *)pbField = pSelReg->Sel;
757 }
758
759 /* Limit. */
760 {
761 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
762 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
763 uint8_t const uWidthType = (uWidth << 2) | uType;
764 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
765 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
766 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
767 uint8_t *pbVmcs = (uint8_t *)pVmcs;
768 uint8_t *pbField = pbVmcs + offField;
769 *(uint32_t *)pbField = pSelReg->u32Limit;
770 }
771
772 /* Base. */
773 {
774 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
775 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
776 uint8_t const uWidthType = (uWidth << 2) | uType;
777 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
778 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
779 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
780 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
781 uint8_t const *pbField = pbVmcs + offField;
782 *(uint64_t *)pbField = pSelReg->u64Base;
783 }
784
785 /* Attributes. */
786 {
787 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
788 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
789 | X86DESCATTR_UNUSABLE;
790 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
791 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
792 uint8_t const uWidthType = (uWidth << 2) | uType;
793 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
794 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
795 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
796 uint8_t *pbVmcs = (uint8_t *)pVmcs;
797 uint8_t *pbField = pbVmcs + offField;
798 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
799 }
800}
801
802
803/**
804 * Gets a guest segment register from the VMCS.
805 *
806 * @returns VBox status code.
807 * @param pVmcs Pointer to the virtual VMCS.
808 * @param iSegReg The index of the segment register (X86_SREG_XXX).
809 * @param pSelReg Where to store the segment register (only updated when
810 * VINF_SUCCESS is returned).
811 *
812 * @remarks Warning! This does not validate the contents of the retrieved segment
813 * register.
814 */
815IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
816{
817 Assert(pSelReg);
818 Assert(iSegReg < X86_SREG_COUNT);
819
820 /* Selector. */
821 uint16_t u16Sel;
822 {
823 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
824 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
825 uint8_t const uWidthType = (uWidth << 2) | uType;
826 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
827 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
828 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
829 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
830 uint8_t const *pbField = pbVmcs + offField;
831 u16Sel = *(uint16_t *)pbField;
832 }
833
834 /* Limit. */
835 uint32_t u32Limit;
836 {
837 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
838 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
839 uint8_t const uWidthType = (uWidth << 2) | uType;
840 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
841 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
842 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
843 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
844 uint8_t const *pbField = pbVmcs + offField;
845 u32Limit = *(uint32_t *)pbField;
846 }
847
848 /* Base. */
849 uint64_t u64Base;
850 {
851 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
852 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
853 uint8_t const uWidthType = (uWidth << 2) | uType;
854 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
855 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
856 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
857 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
858 uint8_t const *pbField = pbVmcs + offField;
859 u64Base = *(uint64_t *)pbField;
860 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
861 }
862
863 /* Attributes. */
864 uint32_t u32Attr;
865 {
866 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
867 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
868 uint8_t const uWidthType = (uWidth << 2) | uType;
869 uint8_t const uIndex = (iSegReg << 1) + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
870 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
871 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
872 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
873 uint8_t const *pbField = pbVmcs + offField;
874 u32Attr = *(uint32_t *)pbField;
875 }
876
877 pSelReg->Sel = u16Sel;
878 pSelReg->ValidSel = u16Sel;
879 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
880 pSelReg->u32Limit = u32Limit;
881 pSelReg->u64Base = u64Base;
882 pSelReg->Attr.u = u32Attr;
883 return VINF_SUCCESS;
884}
885
886
887/**
888 * Gets a CR3 target value from the VMCS.
889 *
890 * @returns VBox status code.
891 * @param pVmcs Pointer to the virtual VMCS.
892 * @param idxCr3Target The index of the CR3-target value to retrieve.
893 * @param puValue Where to store the CR3-target value.
894 */
895DECLINLINE(uint64_t) iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
896{
897 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
898 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
899 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
900 uint8_t const uWidthType = (uWidth << 2) | uType;
901 uint8_t const uIndex = (idxCr3Target << 1) + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
902 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
903 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
904 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
905 uint8_t const *pbField = pbVmcs + offField;
906 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
907
908 return uCr3TargetValue;
909}
910
911
912/**
913 * Signal that a virtual-APIC post instruction-execution action needs to be
914 * performed at a later time (post instruction execution).
915 *
916 * @param pVCpu The cross context virtual CPU structure.
917 * @param offApic The virtual-APIC page offset that was updated pertaining to
918 * the event.
919 */
920DECLINLINE(void) iemVmxVirtApicSetPostAction(PVMCPU pVCpu, uint16_t offApic)
921{
922 Assert(offApic < XAPIC_OFF_END + 4);
923
924 /*
925 * Record the currently updated APIC offset, as we need this later for figuring
926 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
927 * as for supplying the exit qualification when causing an APIC-write VM-exit.
928 */
929 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
930
931 /*
932 * Signal that we need to perform a virtual-APIC action (TPR/PPR/EOI/Self-IPI
933 * virtualization or APIC-write emulation).
934 */
935 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_UPDATE_VAPIC))
936 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_UPDATE_VAPIC);
937}
938
939
940/**
941 * Clears any virtual-APIC post instruction-execution action.
942 *
943 * @returns The virtual-APIC write offset before clearing it.
944 * @param pVCpu The cross context virtual CPU structure.
945 * @param offApic The virtual-APIC page offset that was updated pertaining to
946 * the event.
947 */
948DECLINLINE(uint16_t) iemVmxVirtApicClearPostAction(PVMCPU pVCpu)
949{
950 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
951 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
952 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_UPDATE_VAPIC));
953 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_UPDATE_VAPIC);
954 return offVirtApicWrite;
955}
956
957
958/**
959 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
960 * mask and the read-shadow (CR0/CR4 read).
961 *
962 * @returns The masked CR0/CR4.
963 * @param pVCpu The cross context virtual CPU structure.
964 * @param iCrReg The control register (either CR0 or CR4).
965 * @param uGuestCrX The current guest CR0 or guest CR4.
966 */
967IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
968{
969 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
970 Assert(iCrReg == 0 || iCrReg == 4);
971
972 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
973 Assert(pVmcs);
974
975 /*
976 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
977 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
978 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
979 *
980 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
981 */
982 uint64_t fGstHostMask;
983 uint64_t fReadShadow;
984 if (iCrReg == 0)
985 {
986 fGstHostMask = pVmcs->u64Cr0Mask.u;
987 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
988 }
989 else
990 {
991 fGstHostMask = pVmcs->u64Cr4Mask.u;
992 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
993 }
994
995 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
996 return fMaskedCrX;
997}
998
999
1000/**
1001 * Gets VM-exit instruction information along with any displacement for an
1002 * instruction VM-exit.
1003 *
1004 * @returns The VM-exit instruction information.
1005 * @param pVCpu The cross context virtual CPU structure.
1006 * @param uExitReason The VM-exit reason.
1007 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
1008 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
1009 * NULL.
1010 */
1011IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
1012{
1013 RTGCPTR GCPtrDisp;
1014 VMXEXITINSTRINFO ExitInstrInfo;
1015 ExitInstrInfo.u = 0;
1016
1017 /*
1018 * Get and parse the ModR/M byte from our decoded opcodes.
1019 */
1020 uint8_t bRm;
1021 uint8_t const offModRm = pVCpu->iem.s.offModRm;
1022 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
1023 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1024 {
1025 /*
1026 * ModR/M indicates register addressing.
1027 *
1028 * The primary/secondary register operands are reported in the iReg1 or iReg2
1029 * fields depending on whether it is a read/write form.
1030 */
1031 uint8_t idxReg1;
1032 uint8_t idxReg2;
1033 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1034 {
1035 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1036 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1037 }
1038 else
1039 {
1040 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
1041 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
1042 }
1043 ExitInstrInfo.All.u2Scaling = 0;
1044 ExitInstrInfo.All.iReg1 = idxReg1;
1045 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1046 ExitInstrInfo.All.fIsRegOperand = 1;
1047 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1048 ExitInstrInfo.All.iSegReg = 0;
1049 ExitInstrInfo.All.iIdxReg = 0;
1050 ExitInstrInfo.All.fIdxRegInvalid = 1;
1051 ExitInstrInfo.All.iBaseReg = 0;
1052 ExitInstrInfo.All.fBaseRegInvalid = 1;
1053 ExitInstrInfo.All.iReg2 = idxReg2;
1054
1055 /* Displacement not applicable for register addressing. */
1056 GCPtrDisp = 0;
1057 }
1058 else
1059 {
1060 /*
1061 * ModR/M indicates memory addressing.
1062 */
1063 uint8_t uScale = 0;
1064 bool fBaseRegValid = false;
1065 bool fIdxRegValid = false;
1066 uint8_t iBaseReg = 0;
1067 uint8_t iIdxReg = 0;
1068 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
1069 {
1070 /*
1071 * Parse the ModR/M, displacement for 16-bit addressing mode.
1072 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
1073 */
1074 uint16_t u16Disp = 0;
1075 uint8_t const offDisp = offModRm + sizeof(bRm);
1076 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
1077 {
1078 /* Displacement without any registers. */
1079 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
1080 }
1081 else
1082 {
1083 /* Register (index and base). */
1084 switch (bRm & X86_MODRM_RM_MASK)
1085 {
1086 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1087 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1088 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1089 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1090 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
1091 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
1092 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
1093 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
1094 }
1095
1096 /* Register + displacement. */
1097 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1098 {
1099 case 0: break;
1100 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
1101 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
1102 default:
1103 {
1104 /* Register addressing, handled at the beginning. */
1105 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1106 break;
1107 }
1108 }
1109 }
1110
1111 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
1112 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
1113 }
1114 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
1115 {
1116 /*
1117 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
1118 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
1119 */
1120 uint32_t u32Disp = 0;
1121 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
1122 {
1123 /* Displacement without any registers. */
1124 uint8_t const offDisp = offModRm + sizeof(bRm);
1125 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1126 }
1127 else
1128 {
1129 /* Register (and perhaps scale, index and base). */
1130 uint8_t offDisp = offModRm + sizeof(bRm);
1131 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1132 if (iBaseReg == 4)
1133 {
1134 /* An SIB byte follows the ModR/M byte, parse it. */
1135 uint8_t bSib;
1136 uint8_t const offSib = offModRm + sizeof(bRm);
1137 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1138
1139 /* A displacement may follow SIB, update its offset. */
1140 offDisp += sizeof(bSib);
1141
1142 /* Get the scale. */
1143 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1144
1145 /* Get the index register. */
1146 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
1147 fIdxRegValid = RT_BOOL(iIdxReg != 4);
1148
1149 /* Get the base register. */
1150 iBaseReg = bSib & X86_SIB_BASE_MASK;
1151 fBaseRegValid = true;
1152 if (iBaseReg == 5)
1153 {
1154 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1155 {
1156 /* Mod is 0 implies a 32-bit displacement with no base. */
1157 fBaseRegValid = false;
1158 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
1159 }
1160 else
1161 {
1162 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
1163 iBaseReg = X86_GREG_xBP;
1164 }
1165 }
1166 }
1167
1168 /* Register + displacement. */
1169 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1170 {
1171 case 0: /* Handled above */ break;
1172 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
1173 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
1174 default:
1175 {
1176 /* Register addressing, handled at the beginning. */
1177 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1178 break;
1179 }
1180 }
1181 }
1182
1183 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
1184 }
1185 else
1186 {
1187 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
1188
1189 /*
1190 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
1191 * See Intel instruction spec. 2.2 "IA-32e Mode".
1192 */
1193 uint64_t u64Disp = 0;
1194 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
1195 if (fRipRelativeAddr)
1196 {
1197 /*
1198 * RIP-relative addressing mode.
1199 *
1200 * The displacement is 32-bit signed implying an offset range of +/-2G.
1201 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
1202 */
1203 uint8_t const offDisp = offModRm + sizeof(bRm);
1204 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1205 }
1206 else
1207 {
1208 uint8_t offDisp = offModRm + sizeof(bRm);
1209
1210 /*
1211 * Register (and perhaps scale, index and base).
1212 *
1213 * REX.B extends the most-significant bit of the base register. However, REX.B
1214 * is ignored while determining whether an SIB follows the opcode. Hence, we
1215 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
1216 *
1217 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
1218 */
1219 iBaseReg = (bRm & X86_MODRM_RM_MASK);
1220 if (iBaseReg == 4)
1221 {
1222 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
1223 uint8_t bSib;
1224 uint8_t const offSib = offModRm + sizeof(bRm);
1225 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
1226
1227 /* Displacement may follow SIB, update its offset. */
1228 offDisp += sizeof(bSib);
1229
1230 /* Get the scale. */
1231 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
1232
1233 /* Get the index. */
1234 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
1235 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
1236
1237 /* Get the base. */
1238 iBaseReg = (bSib & X86_SIB_BASE_MASK);
1239 fBaseRegValid = true;
1240 if (iBaseReg == 5)
1241 {
1242 if ((bRm & X86_MODRM_MOD_MASK) == 0)
1243 {
1244 /* Mod is 0 implies a signed 32-bit displacement with no base. */
1245 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
1246 }
1247 else
1248 {
1249 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
1250 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
1251 }
1252 }
1253 }
1254 iBaseReg |= pVCpu->iem.s.uRexB;
1255
1256 /* Register + displacement. */
1257 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
1258 {
1259 case 0: /* Handled above */ break;
1260 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
1261 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
1262 default:
1263 {
1264 /* Register addressing, handled at the beginning. */
1265 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
1266 break;
1267 }
1268 }
1269 }
1270
1271 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
1272 }
1273
1274 /*
1275 * The primary or secondary register operand is reported in iReg2 depending
1276 * on whether the primary operand is in read/write form.
1277 */
1278 uint8_t idxReg2;
1279 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
1280 {
1281 idxReg2 = bRm & X86_MODRM_RM_MASK;
1282 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1283 idxReg2 |= pVCpu->iem.s.uRexB;
1284 }
1285 else
1286 {
1287 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
1288 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
1289 idxReg2 |= pVCpu->iem.s.uRexReg;
1290 }
1291 ExitInstrInfo.All.u2Scaling = uScale;
1292 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
1293 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
1294 ExitInstrInfo.All.fIsRegOperand = 0;
1295 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
1296 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
1297 ExitInstrInfo.All.iIdxReg = iIdxReg;
1298 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
1299 ExitInstrInfo.All.iBaseReg = iBaseReg;
1300 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
1301 ExitInstrInfo.All.iReg2 = idxReg2;
1302 }
1303
1304 /*
1305 * Handle exceptions to the norm for certain instructions.
1306 * (e.g. some instructions convey an instruction identity in place of iReg2).
1307 */
1308 switch (uExitReason)
1309 {
1310 case VMX_EXIT_GDTR_IDTR_ACCESS:
1311 {
1312 Assert(VMXINSTRID_IS_VALID(uInstrId));
1313 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1314 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1315 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
1316 break;
1317 }
1318
1319 case VMX_EXIT_LDTR_TR_ACCESS:
1320 {
1321 Assert(VMXINSTRID_IS_VALID(uInstrId));
1322 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
1323 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
1324 ExitInstrInfo.LdtTr.u2Undef0 = 0;
1325 break;
1326 }
1327
1328 case VMX_EXIT_RDRAND:
1329 case VMX_EXIT_RDSEED:
1330 {
1331 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
1332 break;
1333 }
1334 }
1335
1336 /* Update displacement and return the constructed VM-exit instruction information field. */
1337 if (pGCPtrDisp)
1338 *pGCPtrDisp = GCPtrDisp;
1339
1340 return ExitInstrInfo.u;
1341}
1342
1343
1344/**
1345 * Converts an IEM exception event type to a VMX event type.
1346 *
1347 * @returns The VMX event type.
1348 * @param uVector The interrupt / exception vector.
1349 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
1350 */
1351DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
1352{
1353 /* Paranoia (callers may use these interchangeably). */
1354 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
1355 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
1356 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
1357 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
1358 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
1359 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
1360 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
1361 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
1362 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
1363 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
1364 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
1365 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
1366
1367 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
1368 {
1369 if (uVector == X86_XCPT_NMI)
1370 return VMX_EXIT_INT_INFO_TYPE_NMI;
1371 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
1372 }
1373
1374 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
1375 {
1376 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
1377 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
1378 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
1379 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
1380 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
1381 }
1382
1383 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
1384 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
1385}
1386
1387
1388/**
1389 * Sets the VM-instruction error VMCS field.
1390 *
1391 * @param pVCpu The cross context virtual CPU structure.
1392 * @param enmInsErr The VM-instruction error.
1393 */
1394DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1395{
1396 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1397 pVmcs->u32RoVmInstrError = enmInsErr;
1398}
1399
1400
1401/**
1402 * Sets the VM-exit qualification VMCS field.
1403 *
1404 * @param pVCpu The cross context virtual CPU structure.
1405 * @param uExitQual The VM-exit qualification.
1406 */
1407DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
1408{
1409 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1410 pVmcs->u64RoExitQual.u = uExitQual;
1411}
1412
1413
1414/**
1415 * Sets the VM-exit interruption information field.
1416 *
1417 * @param pVCpu The cross context virtual CPU structure.
1418 * @param uExitQual The VM-exit interruption information.
1419 */
1420DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1421{
1422 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1423 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1424}
1425
1426
1427/**
1428 * Sets the VM-exit interruption error code.
1429 *
1430 * @param pVCpu The cross context virtual CPU structure.
1431 * @param uErrCode The error code.
1432 */
1433DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1434{
1435 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1436 pVmcs->u32RoExitIntErrCode = uErrCode;
1437}
1438
1439
1440/**
1441 * Sets the IDT-vectoring information field.
1442 *
1443 * @param pVCpu The cross context virtual CPU structure.
1444 * @param uIdtVectorInfo The IDT-vectoring information.
1445 */
1446DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1447{
1448 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1449 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1450}
1451
1452
1453/**
1454 * Sets the IDT-vectoring error code field.
1455 *
1456 * @param pVCpu The cross context virtual CPU structure.
1457 * @param uErrCode The error code.
1458 */
1459DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1460{
1461 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1462 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1463}
1464
1465
1466/**
1467 * Sets the VM-exit guest-linear address VMCS field.
1468 *
1469 * @param pVCpu The cross context virtual CPU structure.
1470 * @param uGuestLinearAddr The VM-exit guest-linear address.
1471 */
1472DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1473{
1474 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1475 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1476}
1477
1478
1479/**
1480 * Sets the VM-exit guest-physical address VMCS field.
1481 *
1482 * @param pVCpu The cross context virtual CPU structure.
1483 * @param uGuestPhysAddr The VM-exit guest-physical address.
1484 */
1485DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1486{
1487 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1488 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1489}
1490
1491
1492/**
1493 * Sets the VM-exit instruction length VMCS field.
1494 *
1495 * @param pVCpu The cross context virtual CPU structure.
1496 * @param cbInstr The VM-exit instruction length in bytes.
1497 *
1498 * @remarks Callers may clear this field to 0. Hence, this function does not check
1499 * the validity of the instruction length.
1500 */
1501DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1502{
1503 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1504 pVmcs->u32RoExitInstrLen = cbInstr;
1505}
1506
1507
1508/**
1509 * Sets the VM-exit instruction info. VMCS field.
1510 *
1511 * @param pVCpu The cross context virtual CPU structure.
1512 * @param uExitInstrInfo The VM-exit instruction information.
1513 */
1514DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1515{
1516 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1517 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1518}
1519
1520
1521/**
1522 * Implements VMSucceed for VMX instruction success.
1523 *
1524 * @param pVCpu The cross context virtual CPU structure.
1525 */
1526DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1527{
1528 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1529}
1530
1531
1532/**
1533 * Implements VMFailInvalid for VMX instruction failure.
1534 *
1535 * @param pVCpu The cross context virtual CPU structure.
1536 */
1537DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1538{
1539 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1540 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1541}
1542
1543
1544/**
1545 * Implements VMFailValid for VMX instruction failure.
1546 *
1547 * @param pVCpu The cross context virtual CPU structure.
1548 * @param enmInsErr The VM instruction error.
1549 */
1550DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1551{
1552 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1553 {
1554 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1555 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1556 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1557 }
1558}
1559
1560
1561/**
1562 * Implements VMFail for VMX instruction failure.
1563 *
1564 * @param pVCpu The cross context virtual CPU structure.
1565 * @param enmInsErr The VM instruction error.
1566 */
1567DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1568{
1569 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1570 iemVmxVmFailValid(pVCpu, enmInsErr);
1571 else
1572 iemVmxVmFailInvalid(pVCpu);
1573}
1574
1575
1576/**
1577 * Checks if the given auto-load/store MSR area count is valid for the
1578 * implementation.
1579 *
1580 * @returns @c true if it's within the valid limit, @c false otherwise.
1581 * @param pVCpu The cross context virtual CPU structure.
1582 * @param uMsrCount The MSR area count to check.
1583 */
1584DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1585{
1586 uint64_t const u64VmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
1587 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1588 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1589 if (uMsrCount <= cMaxSupportedMsrs)
1590 return true;
1591 return false;
1592}
1593
1594
1595/**
1596 * Flushes the current VMCS contents back to guest memory.
1597 *
1598 * @returns VBox status code.
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1602{
1603 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1604 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1605 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1606 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1607 return rc;
1608}
1609
1610
1611/**
1612 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1613 *
1614 * @param pVCpu The cross context virtual CPU structure.
1615 */
1616DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1617{
1618 iemVmxVmSucceed(pVCpu);
1619 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1620}
1621
1622
1623/**
1624 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1625 * nested-guest.
1626 *
1627 * @param iSegReg The segment index (X86_SREG_XXX).
1628 */
1629IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1630{
1631 switch (iSegReg)
1632 {
1633 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1634 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1635 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1636 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1637 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1638 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1639 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1640 }
1641}
1642
1643
1644/**
1645 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1646 * nested-guest that is in Virtual-8086 mode.
1647 *
1648 * @param iSegReg The segment index (X86_SREG_XXX).
1649 */
1650IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1651{
1652 switch (iSegReg)
1653 {
1654 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1655 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1656 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1657 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1658 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1659 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1660 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1661 }
1662}
1663
1664
1665/**
1666 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1667 * nested-guest that is in Virtual-8086 mode.
1668 *
1669 * @param iSegReg The segment index (X86_SREG_XXX).
1670 */
1671IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1672{
1673 switch (iSegReg)
1674 {
1675 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1676 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1677 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1678 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1679 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1680 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1681 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1682 }
1683}
1684
1685
1686/**
1687 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1688 * nested-guest that is in Virtual-8086 mode.
1689 *
1690 * @param iSegReg The segment index (X86_SREG_XXX).
1691 */
1692IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1693{
1694 switch (iSegReg)
1695 {
1696 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1697 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1698 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1699 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1700 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1701 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1702 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1703 }
1704}
1705
1706
1707/**
1708 * Gets the instruction diagnostic for segment attributes reserved bits failure
1709 * during VM-entry of a nested-guest.
1710 *
1711 * @param iSegReg The segment index (X86_SREG_XXX).
1712 */
1713IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1714{
1715 switch (iSegReg)
1716 {
1717 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1718 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1719 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1720 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1721 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1722 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1723 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1724 }
1725}
1726
1727
1728/**
1729 * Gets the instruction diagnostic for segment attributes descriptor-type
1730 * (code/segment or system) failure during VM-entry of a nested-guest.
1731 *
1732 * @param iSegReg The segment index (X86_SREG_XXX).
1733 */
1734IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1735{
1736 switch (iSegReg)
1737 {
1738 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1739 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1740 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1741 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1742 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1743 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1744 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1745 }
1746}
1747
1748
1749/**
1750 * Gets the instruction diagnostic for segment attributes descriptor-type
1751 * (code/segment or system) failure during VM-entry of a nested-guest.
1752 *
1753 * @param iSegReg The segment index (X86_SREG_XXX).
1754 */
1755IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1756{
1757 switch (iSegReg)
1758 {
1759 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1760 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1761 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1762 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1763 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1764 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1765 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1766 }
1767}
1768
1769
1770/**
1771 * Gets the instruction diagnostic for segment attribute granularity failure during
1772 * VM-entry of a nested-guest.
1773 *
1774 * @param iSegReg The segment index (X86_SREG_XXX).
1775 */
1776IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1777{
1778 switch (iSegReg)
1779 {
1780 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1781 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1782 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1783 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1784 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1785 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1786 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1787 }
1788}
1789
1790/**
1791 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1792 * VM-entry of a nested-guest.
1793 *
1794 * @param iSegReg The segment index (X86_SREG_XXX).
1795 */
1796IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1797{
1798 switch (iSegReg)
1799 {
1800 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1801 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1802 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1803 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1804 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1805 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1806 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1807 }
1808}
1809
1810
1811/**
1812 * Gets the instruction diagnostic for segment attribute type accessed failure
1813 * during VM-entry of a nested-guest.
1814 *
1815 * @param iSegReg The segment index (X86_SREG_XXX).
1816 */
1817IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1818{
1819 switch (iSegReg)
1820 {
1821 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1822 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1823 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1824 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1825 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1826 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1827 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1828 }
1829}
1830
1831
1832/**
1833 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1834 * failure during VM-entry of a nested-guest.
1835 *
1836 * @param iSegReg The PDPTE entry index.
1837 */
1838IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1839{
1840 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1841 switch (iPdpte)
1842 {
1843 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1844 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1845 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1846 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1847 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1848 }
1849}
1850
1851
1852/**
1853 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1854 * failure during VM-exit of a nested-guest.
1855 *
1856 * @param iSegReg The PDPTE entry index.
1857 */
1858IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1859{
1860 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1861 switch (iPdpte)
1862 {
1863 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1864 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1865 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1866 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1867 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1868 }
1869}
1870
1871
1872/**
1873 * Saves the guest control registers, debug registers and some MSRs are part of
1874 * VM-exit.
1875 *
1876 * @param pVCpu The cross context virtual CPU structure.
1877 */
1878IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1879{
1880 /*
1881 * Saves the guest control registers, debug registers and some MSRs.
1882 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1883 */
1884 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1885
1886 /* Save control registers. */
1887 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1888 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1889 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1890
1891 /* Save SYSENTER CS, ESP, EIP. */
1892 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1893 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1894 {
1895 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1896 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1897 }
1898 else
1899 {
1900 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1901 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1902 }
1903
1904 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1905 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1906 {
1907 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1908 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1909 }
1910
1911 /* Save PAT MSR. */
1912 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1913 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1914
1915 /* Save EFER MSR. */
1916 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1917 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1918
1919 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1920 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1921
1922 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1923}
1924
1925
1926/**
1927 * Saves the guest force-flags in preparation of entering the nested-guest.
1928 *
1929 * @param pVCpu The cross context virtual CPU structure.
1930 */
1931IEM_STATIC void iemVmxVmentrySaveForceFlags(PVMCPU pVCpu)
1932{
1933 /* We shouldn't be called multiple times during VM-entry. */
1934 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1935
1936 /* MTF should not be set outside VMX non-root mode. */
1937 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1938
1939 /*
1940 * Preserve the required force-flags.
1941 *
1942 * We cache and clear force-flags that would affect the execution of the
1943 * nested-guest. Cached flags are then restored while returning to the guest
1944 * if necessary.
1945 *
1946 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1947 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1948 * instruction. Interrupt inhibition for any nested-guest instruction
1949 * will be set later while loading the guest-interruptibility state.
1950 *
1951 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1952 * successful VM-entry needs to continue blocking NMIs if it was in effect
1953 * during VM-entry.
1954 *
1955 * - MTF need not be preserved as it's used only in VMX non-root mode and
1956 * is supplied on VM-entry through the VM-execution controls.
1957 *
1958 * The remaining FFs (e.g. timers, APIC updates) must stay in place so that
1959 * we will be able to generate interrupts that may cause VM-exits for
1960 * the nested-guest.
1961 */
1962 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1963
1964 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS))
1965 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS);
1966}
1967
1968
1969/**
1970 * Restores the guest force-flags in preparation of exiting the nested-guest.
1971 *
1972 * @param pVCpu The cross context virtual CPU structure.
1973 */
1974IEM_STATIC void iemVmxVmexitRestoreForceFlags(PVMCPU pVCpu)
1975{
1976 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1977 {
1978 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1979 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1980 }
1981}
1982
1983
1984/**
1985 * Perform a VMX transition updated PGM, IEM and CPUM.
1986 *
1987 * @param pVCpu The cross context virtual CPU structure.
1988 */
1989IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1990{
1991 /*
1992 * Inform PGM about paging mode changes.
1993 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1994 * see comment in iemMemPageTranslateAndCheckAccess().
1995 */
1996 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1997# ifdef IN_RING3
1998 Assert(rc != VINF_PGM_CHANGE_MODE);
1999# endif
2000 AssertRCReturn(rc, rc);
2001
2002 /* Inform CPUM (recompiler), can later be removed. */
2003 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
2004
2005 /*
2006 * Flush the TLB with new CR3. This is required in case the PGM mode change
2007 * above doesn't actually change anything.
2008 */
2009 if (rc == VINF_SUCCESS)
2010 {
2011 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
2012 AssertRCReturn(rc, rc);
2013 }
2014
2015 /* Re-initialize IEM cache/state after the drastic mode switch. */
2016 iemReInitExec(pVCpu);
2017 return rc;
2018}
2019
2020
2021/**
2022 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
2023 *
2024 * @param pVCpu The cross context virtual CPU structure.
2025 */
2026IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
2027{
2028 /*
2029 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
2030 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
2031 */
2032 /* CS, SS, ES, DS, FS, GS. */
2033 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2034 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2035 {
2036 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2037 if (!pSelReg->Attr.n.u1Unusable)
2038 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
2039 else
2040 {
2041 /*
2042 * For unusable segments the attributes are undefined except for CS and SS.
2043 * For the rest we don't bother preserving anything but the unusable bit.
2044 */
2045 switch (iSegReg)
2046 {
2047 case X86_SREG_CS:
2048 pVmcs->GuestCs = pSelReg->Sel;
2049 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
2050 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
2051 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
2052 | X86DESCATTR_UNUSABLE);
2053 break;
2054
2055 case X86_SREG_SS:
2056 pVmcs->GuestSs = pSelReg->Sel;
2057 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2058 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
2059 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
2060 break;
2061
2062 case X86_SREG_DS:
2063 pVmcs->GuestDs = pSelReg->Sel;
2064 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2065 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
2066 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
2067 break;
2068
2069 case X86_SREG_ES:
2070 pVmcs->GuestEs = pSelReg->Sel;
2071 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2072 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
2073 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
2074 break;
2075
2076 case X86_SREG_FS:
2077 pVmcs->GuestFs = pSelReg->Sel;
2078 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
2079 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
2080 break;
2081
2082 case X86_SREG_GS:
2083 pVmcs->GuestGs = pSelReg->Sel;
2084 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
2085 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
2086 break;
2087 }
2088 }
2089 }
2090
2091 /* Segment attribute bits 31:7 and 11:8 MBZ. */
2092 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
2093 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_UNUSABLE;
2094 /* LDTR. */
2095 {
2096 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
2097 pVmcs->GuestLdtr = pSelReg->Sel;
2098 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
2099 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
2100 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
2101 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
2102 }
2103
2104 /* TR. */
2105 {
2106 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
2107 pVmcs->GuestTr = pSelReg->Sel;
2108 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
2109 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
2110 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
2111 }
2112
2113 /* GDTR. */
2114 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
2115 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
2116
2117 /* IDTR. */
2118 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
2119 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
2120}
2121
2122
2123/**
2124 * Saves guest non-register state as part of VM-exit.
2125 *
2126 * @param pVCpu The cross context virtual CPU structure.
2127 * @param uExitReason The VM-exit reason.
2128 */
2129IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
2130{
2131 /*
2132 * Save guest non-register state.
2133 * See Intel spec. 27.3.4 "Saving Non-Register State".
2134 */
2135 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2136
2137 /* Activity-state: VM-exits occur before changing the activity state, nothing further to do */
2138
2139 /* Interruptibility-state. */
2140 pVmcs->u32GuestIntrState = 0;
2141 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
2142 { /** @todo NSTVMX: Virtual-NMI blocking. */ }
2143 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2144 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
2145
2146 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
2147 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
2148 {
2149 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
2150 * currently. */
2151 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
2152 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2153 }
2154 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
2155
2156 /* Pending debug exceptions. */
2157 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
2158 && uExitReason != VMX_EXIT_SMI
2159 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
2160 && !HMVmxIsTrapLikeVmexit(uExitReason))
2161 {
2162 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
2163 * block-by-MovSS is in effect. */
2164 pVmcs->u64GuestPendingDbgXcpt.u = 0;
2165 }
2166
2167 /* Save VMX-preemption timer value. */
2168 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
2169 {
2170 uint32_t uPreemptTimer;
2171 if (uExitReason == VMX_EXIT_PREEMPT_TIMER)
2172 uPreemptTimer = 0;
2173 else
2174 {
2175 /*
2176 * Assume the following:
2177 * PreemptTimerShift = 5
2178 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
2179 * VmentryTick = 50000 (TSC at time of VM-entry)
2180 *
2181 * CurTick Delta PreemptTimerVal
2182 * ----------------------------------
2183 * 60000 10000 2
2184 * 80000 30000 1
2185 * 90000 40000 0 -> VM-exit.
2186 *
2187 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
2188 *
2189 * The saved VMX-preemption timer value is calculated as follows:
2190 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
2191 * E.g.:
2192 * Delta = 10000
2193 * Tmp = 10000 / (2 * 10000) = 0.5
2194 * NewPt = 2 - 0.5 = 2
2195 * Delta = 30000
2196 * Tmp = 30000 / (2 * 10000) = 1.5
2197 * NewPt = 2 - 1.5 = 1
2198 * Delta = 40000
2199 * Tmp = 40000 / 20000 = 2
2200 * NewPt = 2 - 2 = 0
2201 */
2202 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
2203 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
2204 uint64_t const uDelta = uCurTick - uVmentryTick;
2205 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
2206 uPreemptTimer = uVmcsPreemptVal - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
2207 }
2208
2209 pVmcs->u32PreemptTimer = uPreemptTimer;
2210 }
2211
2212
2213 /* PDPTEs. */
2214 /* We don't support EPT yet. */
2215 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
2216 pVmcs->u64GuestPdpte0.u = 0;
2217 pVmcs->u64GuestPdpte1.u = 0;
2218 pVmcs->u64GuestPdpte2.u = 0;
2219 pVmcs->u64GuestPdpte3.u = 0;
2220}
2221
2222
2223/**
2224 * Saves the guest-state as part of VM-exit.
2225 *
2226 * @returns VBox status code.
2227 * @param pVCpu The cross context virtual CPU structure.
2228 * @param uExitReason The VM-exit reason.
2229 */
2230IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
2231{
2232 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2233 Assert(pVmcs);
2234
2235 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
2236 iemVmxVmexitSaveGuestSegRegs(pVCpu);
2237
2238#if 0
2239 /*
2240 * Save guest RIP, RSP and RFLAGS.
2241 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
2242 *
2243 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
2244 * Callers must pass the instruction length in the VM-exit instruction length
2245 * field though it is undefined for such VM-exits. After updating RIP here, we clear
2246 * the VM-exit instruction length field.
2247 *
2248 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
2249 */
2250 if (HMVmxIsTrapLikeVmexit(uExitReason))
2251 {
2252 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
2253 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
2254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2255 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
2256 }
2257#endif
2258
2259 /* We don't support enclave mode yet. */
2260 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
2261 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
2262 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
2263
2264 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
2265}
2266
2267
2268/**
2269 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
2270 *
2271 * @returns VBox status code.
2272 * @param pVCpu The cross context virtual CPU structure.
2273 * @param uExitReason The VM-exit reason (for diagnostic purposes).
2274 */
2275IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2276{
2277 /*
2278 * Save guest MSRs.
2279 * See Intel spec. 27.4 "Saving MSRs".
2280 */
2281 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2282 const char *const pszFailure = "VMX-abort";
2283
2284 /*
2285 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
2286 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
2287 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2288 */
2289 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
2290 if (!cMsrs)
2291 return VINF_SUCCESS;
2292
2293 /*
2294 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
2295 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2296 * implementation causes a VMX-abort followed by a triple-fault.
2297 */
2298 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2299 if (fIsMsrCountValid)
2300 { /* likely */ }
2301 else
2302 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
2303
2304 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2305 Assert(pMsr);
2306 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2307 {
2308 if ( !pMsr->u32Reserved
2309 && pMsr->u32Msr != MSR_IA32_SMBASE
2310 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2311 {
2312 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
2313 if (rcStrict == VINF_SUCCESS)
2314 continue;
2315
2316 /*
2317 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2318 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2319 * recording the MSR index in the auxiliary info. field and indicated further by our
2320 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2321 * if possible, or come up with a better, generic solution.
2322 */
2323 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2324 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2325 ? kVmxVDiag_Vmexit_MsrStoreRing3
2326 : kVmxVDiag_Vmexit_MsrStore;
2327 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2328 }
2329 else
2330 {
2331 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2332 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2333 }
2334 }
2335
2336 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2337 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2338 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), VMX_V_AUTOMSR_AREA_SIZE);
2339 if (RT_SUCCESS(rc))
2340 { /* likely */ }
2341 else
2342 {
2343 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2344 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2345 }
2346
2347 NOREF(uExitReason);
2348 NOREF(pszFailure);
2349 return VINF_SUCCESS;
2350}
2351
2352
2353/**
2354 * Performs a VMX abort (due to an fatal error during VM-exit).
2355 *
2356 * @returns Strict VBox status code.
2357 * @param pVCpu The cross context virtual CPU structure.
2358 * @param enmAbort The VMX abort reason.
2359 */
2360IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2361{
2362 /*
2363 * Perform the VMX abort.
2364 * See Intel spec. 27.7 "VMX Aborts".
2365 */
2366 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMVmxGetAbortDesc(enmAbort)));
2367
2368 /* We don't support SMX yet. */
2369 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2370 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2371 {
2372 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2373 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, u32VmxAbortId);
2374 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2375 }
2376
2377 return VINF_EM_TRIPLE_FAULT;
2378}
2379
2380
2381/**
2382 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2383 *
2384 * @param pVCpu The cross context virtual CPU structure.
2385 */
2386IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2387{
2388 /*
2389 * Load host control registers, debug registers and MSRs.
2390 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2391 */
2392 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2393 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2394
2395 /* CR0. */
2396 {
2397 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2398 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
2399 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2400 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2401 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2402 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2403 CPUMSetGuestCR0(pVCpu, uValidCr0);
2404 }
2405
2406 /* CR4. */
2407 {
2408 /* CR4 MB1 bits are not modified. */
2409 uint64_t const fCr4IgnMask = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
2410 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2411 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2412 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2413 if (fHostInLongMode)
2414 uValidCr4 |= X86_CR4_PAE;
2415 else
2416 uValidCr4 &= ~X86_CR4_PCIDE;
2417 CPUMSetGuestCR4(pVCpu, uValidCr4);
2418 }
2419
2420 /* CR3 (host value validated while checking host-state during VM-entry). */
2421 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2422
2423 /* DR7. */
2424 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2425
2426 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2427
2428 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2429 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2430 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2431 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2432
2433 /* FS, GS bases are loaded later while we load host segment registers. */
2434
2435 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2436 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2437 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2438 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2439 {
2440 if (fHostInLongMode)
2441 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2442 else
2443 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2444 }
2445
2446 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2447
2448 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2449 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2450 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2451
2452 /* We don't support IA32_BNDCFGS MSR yet. */
2453}
2454
2455
2456/**
2457 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2458 *
2459 * @param pVCpu The cross context virtual CPU structure.
2460 */
2461IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2462{
2463 /*
2464 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2465 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2466 *
2467 * Warning! Be careful to not touch fields that are reserved by VT-x,
2468 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2469 */
2470 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2471 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2472
2473 /* CS, SS, ES, DS, FS, GS. */
2474 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2475 {
2476 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2477 bool const fUnusable = RT_BOOL(HostSel == 0);
2478
2479 /* Selector. */
2480 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel = HostSel;
2481 pVCpu->cpum.GstCtx.aSRegs[iSegReg].ValidSel = HostSel;
2482 pVCpu->cpum.GstCtx.aSRegs[iSegReg].fFlags = CPUMSELREG_FLAGS_VALID;
2483
2484 /* Limit. */
2485 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u32Limit = 0xffffffff;
2486
2487 /* Base and Attributes. */
2488 switch (iSegReg)
2489 {
2490 case X86_SREG_CS:
2491 {
2492 pVCpu->cpum.GstCtx.cs.u64Base = 0;
2493 pVCpu->cpum.GstCtx.cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2494 pVCpu->cpum.GstCtx.ss.Attr.n.u1DescType = 1;
2495 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = 0;
2496 pVCpu->cpum.GstCtx.cs.Attr.n.u1Present = 1;
2497 pVCpu->cpum.GstCtx.cs.Attr.n.u1Long = fHostInLongMode;
2498 pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig = !fHostInLongMode;
2499 pVCpu->cpum.GstCtx.cs.Attr.n.u1Granularity = 1;
2500 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Unusable);
2501 Assert(!fUnusable);
2502 break;
2503 }
2504
2505 case X86_SREG_SS:
2506 case X86_SREG_ES:
2507 case X86_SREG_DS:
2508 {
2509 pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base = 0;
2510 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2511 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DescType = 1;
2512 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u2Dpl = 0;
2513 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Present = 1;
2514 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1DefBig = 1;
2515 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Granularity = 1;
2516 pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable = fUnusable;
2517 break;
2518 }
2519
2520 case X86_SREG_FS:
2521 {
2522 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2523 pVCpu->cpum.GstCtx.fs.u64Base = !fUnusable ? pVmcs->u64HostFsBase.u : 0;
2524 pVCpu->cpum.GstCtx.fs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2525 pVCpu->cpum.GstCtx.fs.Attr.n.u1DescType = 1;
2526 pVCpu->cpum.GstCtx.fs.Attr.n.u2Dpl = 0;
2527 pVCpu->cpum.GstCtx.fs.Attr.n.u1Present = 1;
2528 pVCpu->cpum.GstCtx.fs.Attr.n.u1DefBig = 1;
2529 pVCpu->cpum.GstCtx.fs.Attr.n.u1Granularity = 1;
2530 pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable = fUnusable;
2531 break;
2532 }
2533
2534 case X86_SREG_GS:
2535 {
2536 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2537 pVCpu->cpum.GstCtx.gs.u64Base = !fUnusable ? pVmcs->u64HostGsBase.u : 0;
2538 pVCpu->cpum.GstCtx.gs.Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2539 pVCpu->cpum.GstCtx.gs.Attr.n.u1DescType = 1;
2540 pVCpu->cpum.GstCtx.gs.Attr.n.u2Dpl = 0;
2541 pVCpu->cpum.GstCtx.gs.Attr.n.u1Present = 1;
2542 pVCpu->cpum.GstCtx.gs.Attr.n.u1DefBig = 1;
2543 pVCpu->cpum.GstCtx.gs.Attr.n.u1Granularity = 1;
2544 pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable = fUnusable;
2545 break;
2546 }
2547 }
2548 }
2549
2550 /* TR. */
2551 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2552 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2553 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2554 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2555 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2556 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2557 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2558 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2559 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2560 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2561 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2562 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2563 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2564
2565 /* LDTR. */
2566 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2567 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2568 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2569 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
2570 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
2571 pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Unusable = 1;
2572
2573 /* GDTR. */
2574 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2575 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2576 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xfff;
2577
2578 /* IDTR.*/
2579 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2580 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2581 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xfff;
2582}
2583
2584
2585/**
2586 * Checks host PDPTes as part of VM-exit.
2587 *
2588 * @param pVCpu The cross context virtual CPU structure.
2589 * @param uExitReason The VM-exit reason (for logging purposes).
2590 */
2591IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2592{
2593 /*
2594 * Check host PDPTEs.
2595 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2596 */
2597 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2598 const char *const pszFailure = "VMX-abort";
2599 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2600
2601 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2602 && !fHostInLongMode)
2603 {
2604 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2605 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2606 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2607 if (RT_SUCCESS(rc))
2608 {
2609 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2610 {
2611 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2612 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2613 { /* likely */ }
2614 else
2615 {
2616 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2617 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2618 }
2619 }
2620 }
2621 else
2622 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2623 }
2624
2625 NOREF(pszFailure);
2626 NOREF(uExitReason);
2627 return VINF_SUCCESS;
2628}
2629
2630
2631/**
2632 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2633 *
2634 * @returns VBox status code.
2635 * @param pVCpu The cross context virtual CPU structure.
2636 * @param pszInstr The VMX instruction name (for logging purposes).
2637 */
2638IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2639{
2640 /*
2641 * Load host MSRs.
2642 * See Intel spec. 27.6 "Loading MSRs".
2643 */
2644 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2645 const char *const pszFailure = "VMX-abort";
2646
2647 /*
2648 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2649 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2650 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2651 */
2652 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2653 if (!cMsrs)
2654 return VINF_SUCCESS;
2655
2656 /*
2657 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2658 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2659 * implementation causes a VMX-abort followed by a triple-fault.
2660 */
2661 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2662 if (fIsMsrCountValid)
2663 { /* likely */ }
2664 else
2665 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2666
2667 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2668 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2669 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
2670 if (RT_SUCCESS(rc))
2671 {
2672 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2673 Assert(pMsr);
2674 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2675 {
2676 if ( !pMsr->u32Reserved
2677 && pMsr->u32Msr != MSR_K8_FS_BASE
2678 && pMsr->u32Msr != MSR_K8_GS_BASE
2679 && pMsr->u32Msr != MSR_K6_EFER
2680 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2681 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2682 {
2683 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2684 if (rcStrict == VINF_SUCCESS)
2685 continue;
2686
2687 /*
2688 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2689 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2690 * recording the MSR index in the auxiliary info. field and indicated further by our
2691 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2692 * if possible, or come up with a better, generic solution.
2693 */
2694 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2695 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2696 ? kVmxVDiag_Vmexit_MsrLoadRing3
2697 : kVmxVDiag_Vmexit_MsrLoad;
2698 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2699 }
2700 else
2701 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2702 }
2703 }
2704 else
2705 {
2706 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2707 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2708 }
2709
2710 NOREF(uExitReason);
2711 NOREF(pszFailure);
2712 return VINF_SUCCESS;
2713}
2714
2715
2716/**
2717 * Loads the host state as part of VM-exit.
2718 *
2719 * @returns Strict VBox status code.
2720 * @param pVCpu The cross context virtual CPU structure.
2721 * @param uExitReason The VM-exit reason (for logging purposes).
2722 */
2723IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2724{
2725 /*
2726 * Load host state.
2727 * See Intel spec. 27.5 "Loading Host State".
2728 */
2729 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2730 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2731 bool const fVirtApicAccess = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
2732
2733 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2734 if ( CPUMIsGuestInLongMode(pVCpu)
2735 && !fHostInLongMode)
2736 {
2737 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2738 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2739 }
2740
2741 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2742 iemVmxVmexitLoadHostSegRegs(pVCpu);
2743
2744 /*
2745 * Load host RIP, RSP and RFLAGS.
2746 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2747 */
2748 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2749 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2750 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2751
2752 /* Update non-register state. */
2753 iemVmxVmexitRestoreForceFlags(pVCpu);
2754
2755 /* Clear address range monitoring. */
2756 EMMonitorWaitClear(pVCpu);
2757
2758 /* De-register the handler for the APIC-access page. */
2759 if (fVirtApicAccess)
2760 {
2761 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
2762 int rc = CPUMVmxApicAccessPageDeregister(pVCpu, GCPhysApicAccess);
2763 if (RT_FAILURE(rc))
2764 return rc;
2765 }
2766
2767 /* Perform the VMX transition (PGM updates). */
2768 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2769 if (rcStrict == VINF_SUCCESS)
2770 {
2771 /* Check host PDPTEs (only when we've fully switched page tables_. */
2772 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2773 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2774 if (RT_FAILURE(rc))
2775 {
2776 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2777 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2778 }
2779 }
2780 else if (RT_SUCCESS(rcStrict))
2781 {
2782 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2783 uExitReason));
2784 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2785 }
2786 else
2787 {
2788 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2789 return VBOXSTRICTRC_VAL(rcStrict);
2790 }
2791
2792 Assert(rcStrict == VINF_SUCCESS);
2793
2794 /* Load MSRs from the VM-exit auto-load MSR area. */
2795 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2796 if (RT_FAILURE(rc))
2797 {
2798 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2799 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2800 }
2801
2802 return rcStrict;
2803}
2804
2805
2806/**
2807 * VMX VM-exit handler.
2808 *
2809 * @returns Strict VBox status code.
2810 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2811 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2812 * triple-fault.
2813 *
2814 * @param pVCpu The cross context virtual CPU structure.
2815 * @param uExitReason The VM-exit reason.
2816 *
2817 * @remarks Make sure VM-exit qualification is updated before calling this
2818 * function!
2819 */
2820IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2821{
2822 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2823 Assert(pVmcs);
2824
2825 pVmcs->u32RoExitReason = uExitReason;
2826
2827 /** @todo NSTVMX: IEMGetCurrentXcpt will be VM-exit interruption info. */
2828 /** @todo NSTVMX: The source event should be recorded in IDT-vectoring info
2829 * during injection. */
2830
2831 /*
2832 * Save the guest state back into the VMCS.
2833 * We only need to save the state when the VM-entry was successful.
2834 */
2835 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2836 if (!fVmentryFailed)
2837 {
2838 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2839 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2840 if (RT_SUCCESS(rc))
2841 { /* likely */ }
2842 else
2843 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2844 }
2845
2846 /*
2847 * The high bits of the VM-exit reason are only relevant when the VM-exit occurs in
2848 * enclave mode/SMM which we don't support yet. If we ever add support for it, we can
2849 * pass just the lower bits, till then an assert should suffice.
2850 */
2851 Assert(!RT_HI_U16(uExitReason));
2852
2853 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2854 if (RT_FAILURE(rcStrict))
2855 LogFunc(("Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2856
2857 /* We're no longer in nested-guest execution mode. */
2858 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2859
2860 Assert(rcStrict == VINF_SUCCESS);
2861 return VINF_VMX_VMEXIT;
2862}
2863
2864
2865/**
2866 * VMX VM-exit handler for VM-exits due to instruction execution.
2867 *
2868 * This is intended for instructions where the caller provides all the relevant
2869 * VM-exit information.
2870 *
2871 * @returns Strict VBox status code.
2872 * @param pVCpu The cross context virtual CPU structure.
2873 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2874 */
2875DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2876{
2877 /*
2878 * For instructions where any of the following fields are not applicable:
2879 * - VM-exit instruction info. is undefined.
2880 * - VM-exit qualification must be cleared.
2881 * - VM-exit guest-linear address is undefined.
2882 * - VM-exit guest-physical address is undefined.
2883 *
2884 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2885 * instruction execution. For VM-exits that are not due to instruction execution this
2886 * field is undefined.
2887 *
2888 * In our implementation in IEM, all undefined fields are generally cleared. However,
2889 * if the caller supplies information (from say the physical CPU directly) it is
2890 * then possible that the undefined fields are not cleared.
2891 *
2892 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2893 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2894 */
2895 Assert(pExitInfo);
2896 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2897 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2898 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2899
2900 /* Update all the relevant fields from the VM-exit instruction information struct. */
2901 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2902 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2903 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2904 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2905 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2906
2907 /* Perform the VM-exit. */
2908 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2909}
2910
2911
2912/**
2913 * VMX VM-exit handler for VM-exits due to instruction execution.
2914 *
2915 * This is intended for instructions that only provide the VM-exit instruction
2916 * length.
2917 *
2918 * @param pVCpu The cross context virtual CPU structure.
2919 * @param uExitReason The VM-exit reason.
2920 * @param cbInstr The instruction length in bytes.
2921 */
2922IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2923{
2924 VMXVEXITINFO ExitInfo;
2925 RT_ZERO(ExitInfo);
2926 ExitInfo.uReason = uExitReason;
2927 ExitInfo.cbInstr = cbInstr;
2928
2929#ifdef VBOX_STRICT
2930 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2931 switch (uExitReason)
2932 {
2933 case VMX_EXIT_INVEPT:
2934 case VMX_EXIT_INVPCID:
2935 case VMX_EXIT_LDTR_TR_ACCESS:
2936 case VMX_EXIT_GDTR_IDTR_ACCESS:
2937 case VMX_EXIT_VMCLEAR:
2938 case VMX_EXIT_VMPTRLD:
2939 case VMX_EXIT_VMPTRST:
2940 case VMX_EXIT_VMREAD:
2941 case VMX_EXIT_VMWRITE:
2942 case VMX_EXIT_VMXON:
2943 case VMX_EXIT_XRSTORS:
2944 case VMX_EXIT_XSAVES:
2945 case VMX_EXIT_RDRAND:
2946 case VMX_EXIT_RDSEED:
2947 case VMX_EXIT_IO_INSTR:
2948 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2949 break;
2950 }
2951#endif
2952
2953 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2954}
2955
2956
2957/**
2958 * VMX VM-exit handler for VM-exits due to instruction execution.
2959 *
2960 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2961 * instruction information and VM-exit qualification fields.
2962 *
2963 * @param pVCpu The cross context virtual CPU structure.
2964 * @param uExitReason The VM-exit reason.
2965 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2966 * @param cbInstr The instruction length in bytes.
2967 *
2968 * @remarks Do not use this for INS/OUTS instruction.
2969 */
2970IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2971{
2972 VMXVEXITINFO ExitInfo;
2973 RT_ZERO(ExitInfo);
2974 ExitInfo.uReason = uExitReason;
2975 ExitInfo.cbInstr = cbInstr;
2976
2977 /*
2978 * Update the VM-exit qualification field with displacement bytes.
2979 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2980 */
2981 switch (uExitReason)
2982 {
2983 case VMX_EXIT_INVEPT:
2984 case VMX_EXIT_INVPCID:
2985 case VMX_EXIT_LDTR_TR_ACCESS:
2986 case VMX_EXIT_GDTR_IDTR_ACCESS:
2987 case VMX_EXIT_VMCLEAR:
2988 case VMX_EXIT_VMPTRLD:
2989 case VMX_EXIT_VMPTRST:
2990 case VMX_EXIT_VMREAD:
2991 case VMX_EXIT_VMWRITE:
2992 case VMX_EXIT_VMXON:
2993 case VMX_EXIT_XRSTORS:
2994 case VMX_EXIT_XSAVES:
2995 case VMX_EXIT_RDRAND:
2996 case VMX_EXIT_RDSEED:
2997 {
2998 /* Construct the VM-exit instruction information. */
2999 RTGCPTR GCPtrDisp;
3000 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3001
3002 /* Update the VM-exit instruction information. */
3003 ExitInfo.InstrInfo.u = uInstrInfo;
3004
3005 /* Update the VM-exit qualification. */
3006 ExitInfo.u64Qual = GCPtrDisp;
3007 break;
3008 }
3009
3010 default:
3011 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3012 break;
3013 }
3014
3015 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3016}
3017
3018
3019/**
3020 * Checks whether an I/O instruction for the given port is intercepted (causes a
3021 * VM-exit) or not.
3022 *
3023 * @returns @c true if the instruction is intercepted, @c false otherwise.
3024 * @param pVCpu The cross context virtual CPU structure.
3025 * @param u16Port The I/O port being accessed by the instruction.
3026 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3027 */
3028IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3029{
3030 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3031 Assert(pVmcs);
3032
3033 /*
3034 * Check whether the I/O instruction must cause a VM-exit or not.
3035 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3036 */
3037 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3038 return true;
3039
3040 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3041 {
3042 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3043 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3044 Assert(pbIoBitmapA);
3045 Assert(pbIoBitmapB);
3046 return CPUMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3047 }
3048
3049 return false;
3050}
3051
3052
3053/**
3054 * VMX VM-exit handler for VM-exits due to INVLPG.
3055 *
3056 * @param pVCpu The cross context virtual CPU structure.
3057 * @param GCPtrPage The guest-linear address of the page being invalidated.
3058 * @param cbInstr The instruction length in bytes.
3059 */
3060IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3061{
3062 VMXVEXITINFO ExitInfo;
3063 RT_ZERO(ExitInfo);
3064 ExitInfo.uReason = VMX_EXIT_INVLPG;
3065 ExitInfo.cbInstr = cbInstr;
3066 ExitInfo.u64Qual = GCPtrPage;
3067 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3068
3069 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to LMSW.
3075 *
3076 * @returns Strict VBox status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 * @param uGuestCr0 The current guest CR0.
3079 * @param pu16NewMsw The machine-status word specified in LMSW's source
3080 * operand. This will be updated depending on the VMX
3081 * guest/host CR0 mask if LMSW is not intercepted.
3082 * @param GCPtrEffDst The guest-linear address of the source operand in case
3083 * of a memory operand. For register operand, pass
3084 * NIL_RTGCPTR.
3085 * @param cbInstr The instruction length in bytes.
3086 */
3087IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3088 uint8_t cbInstr)
3089{
3090 /*
3091 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3092 *
3093 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3094 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3095 */
3096 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3097 Assert(pVmcs);
3098 Assert(pu16NewMsw);
3099
3100 bool fIntercept = false;
3101 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3102 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3103
3104 /*
3105 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3106 * CR0.PE case first, before the rest of the bits in the MSW.
3107 *
3108 * If CR0.PE is owned by the host and CR0.PE differs between the
3109 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3110 */
3111 if ( (fGstHostMask & X86_CR0_PE)
3112 && (*pu16NewMsw & X86_CR0_PE)
3113 && !(fReadShadow & X86_CR0_PE))
3114 fIntercept = true;
3115
3116 /*
3117 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3118 * bits differ between the MSW (source operand) and the read-shadow, we must
3119 * cause a VM-exit.
3120 */
3121 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3122 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3123 fIntercept = true;
3124
3125 if (fIntercept)
3126 {
3127 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3128
3129 VMXVEXITINFO ExitInfo;
3130 RT_ZERO(ExitInfo);
3131 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3132 ExitInfo.cbInstr = cbInstr;
3133
3134 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3135 if (fMemOperand)
3136 {
3137 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3138 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3139 }
3140
3141 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3142 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3143 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3144 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3145
3146 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3147 }
3148
3149 /*
3150 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3151 * CR0 guest/host mask must be left unmodified.
3152 *
3153 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3154 */
3155 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3156 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3157
3158 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3159}
3160
3161
3162/**
3163 * VMX VM-exit handler for VM-exits due to CLTS.
3164 *
3165 * @returns Strict VBox status code.
3166 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3167 * VM-exit but must not modify the guest CR0.TS bit.
3168 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3169 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3170 * CR0 fixed bits in VMX operation).
3171 * @param pVCpu The cross context virtual CPU structure.
3172 * @param cbInstr The instruction length in bytes.
3173 */
3174IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3175{
3176 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3177 Assert(pVmcs);
3178
3179 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3180 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3181
3182 /*
3183 * If CR0.TS is owned by the host:
3184 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3185 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3186 * CLTS instruction completes without clearing CR0.TS.
3187 *
3188 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3189 */
3190 if (fGstHostMask & X86_CR0_TS)
3191 {
3192 if (fReadShadow & X86_CR0_TS)
3193 {
3194 Log2(("clts: Guest intercept -> VM-exit\n"));
3195
3196 VMXVEXITINFO ExitInfo;
3197 RT_ZERO(ExitInfo);
3198 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3199 ExitInfo.cbInstr = cbInstr;
3200
3201 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3202 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3203 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3204 }
3205
3206 return VINF_VMX_MODIFIES_BEHAVIOR;
3207 }
3208
3209 /*
3210 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3211 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3212 */
3213 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3214}
3215
3216
3217/**
3218 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3219 * (CR0/CR4 write).
3220 *
3221 * @returns Strict VBox status code.
3222 * @param pVCpu The cross context virtual CPU structure.
3223 * @param iCrReg The control register (either CR0 or CR4).
3224 * @param uGuestCrX The current guest CR0/CR4.
3225 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3226 * if no VM-exit is caused.
3227 * @param iGReg The general register from which the CR0/CR4 value is
3228 * being loaded.
3229 * @param cbInstr The instruction length in bytes.
3230 */
3231IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3232 uint8_t cbInstr)
3233{
3234 Assert(puNewCrX);
3235 Assert(iCrReg == 0 || iCrReg == 4);
3236
3237 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3238 Assert(pVmcs);
3239
3240 uint64_t uGuestCrX;
3241 uint64_t fGstHostMask;
3242 uint64_t fReadShadow;
3243 if (iCrReg == 0)
3244 {
3245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3246 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3247 fGstHostMask = pVmcs->u64Cr0Mask.u;
3248 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3249 }
3250 else
3251 {
3252 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3253 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3254 fGstHostMask = pVmcs->u64Cr4Mask.u;
3255 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3256 }
3257
3258 /*
3259 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3260 * corresponding bits differ between the source operand and the read-shadow,
3261 * we must cause a VM-exit.
3262 *
3263 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3264 */
3265 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3266 {
3267 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3268
3269 VMXVEXITINFO ExitInfo;
3270 RT_ZERO(ExitInfo);
3271 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3272 ExitInfo.cbInstr = cbInstr;
3273
3274 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3277 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3278 }
3279
3280 /*
3281 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3282 * must not be modified the instruction.
3283 *
3284 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3285 */
3286 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3287
3288 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3289}
3290
3291
3292/**
3293 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3294 *
3295 * @returns VBox strict status code.
3296 * @param pVCpu The cross context virtual CPU structure.
3297 * @param iGReg The general register to which the CR3 value is being stored.
3298 * @param cbInstr The instruction length in bytes.
3299 */
3300IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3301{
3302 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3303 Assert(pVmcs);
3304 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3305
3306 /*
3307 * If the CR3-store exiting control is set, we must cause a VM-exit.
3308 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3309 */
3310 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3311 {
3312 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3313
3314 VMXVEXITINFO ExitInfo;
3315 RT_ZERO(ExitInfo);
3316 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3317 ExitInfo.cbInstr = cbInstr;
3318
3319 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3321 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3322 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3323 }
3324
3325 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3326}
3327
3328
3329/**
3330 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3331 *
3332 * @returns VBox strict status code.
3333 * @param pVCpu The cross context virtual CPU structure.
3334 * @param uNewCr3 The new CR3 value.
3335 * @param iGReg The general register from which the CR3 value is being
3336 * loaded.
3337 * @param cbInstr The instruction length in bytes.
3338 */
3339IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3340{
3341 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3342 Assert(pVmcs);
3343
3344 /*
3345 * If the CR3-load exiting control is set and the new CR3 value does not
3346 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3347 *
3348 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3349 */
3350 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3351 {
3352 uint32_t uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3353 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3354
3355 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3356 {
3357 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3358 if (uNewCr3 != uCr3TargetValue)
3359 {
3360 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3361
3362 VMXVEXITINFO ExitInfo;
3363 RT_ZERO(ExitInfo);
3364 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3365 ExitInfo.cbInstr = cbInstr;
3366
3367 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3368 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3369 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3370 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3371 }
3372 }
3373 }
3374
3375 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3376}
3377
3378
3379/**
3380 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3381 *
3382 * @returns VBox strict status code.
3383 * @param pVCpu The cross context virtual CPU structure.
3384 * @param iGReg The general register to which the CR8 value is being stored.
3385 * @param cbInstr The instruction length in bytes.
3386 */
3387IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3388{
3389 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3390 Assert(pVmcs);
3391
3392 /*
3393 * If the CR8-store exiting control is set, we must cause a VM-exit.
3394 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3395 */
3396 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3397 {
3398 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3399
3400 VMXVEXITINFO ExitInfo;
3401 RT_ZERO(ExitInfo);
3402 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3403 ExitInfo.cbInstr = cbInstr;
3404
3405 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3406 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3407 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3408 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3409 }
3410
3411 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3412}
3413
3414
3415/**
3416 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3417 *
3418 * @returns VBox strict status code.
3419 * @param pVCpu The cross context virtual CPU structure.
3420 * @param iGReg The general register from which the CR8 value is being
3421 * loaded.
3422 * @param cbInstr The instruction length in bytes.
3423 */
3424IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3425{
3426 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3427 Assert(pVmcs);
3428
3429 /*
3430 * If the CR8-load exiting control is set, we must cause a VM-exit.
3431 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3432 */
3433 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3434 {
3435 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3436
3437 VMXVEXITINFO ExitInfo;
3438 RT_ZERO(ExitInfo);
3439 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3440 ExitInfo.cbInstr = cbInstr;
3441
3442 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3443 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3444 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3445 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3446 }
3447
3448 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3449}
3450
3451
3452/**
3453 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3454 * GReg,DRx' (DRx read).
3455 *
3456 * @returns VBox strict status code.
3457 * @param pVCpu The cross context virtual CPU structure.
3458 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3459 * VMXINSTRID_MOV_FROM_DRX).
3460 * @param iDrReg The debug register being accessed.
3461 * @param iGReg The general register to/from which the DRx value is being
3462 * store/loaded.
3463 * @param cbInstr The instruction length in bytes.
3464 */
3465IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3466 uint8_t cbInstr)
3467{
3468 Assert(iDrReg <= 7);
3469 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3470
3471 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3472 Assert(pVmcs);
3473
3474 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3475 {
3476 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3477 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3478 VMXVEXITINFO ExitInfo;
3479 RT_ZERO(ExitInfo);
3480 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3481 ExitInfo.cbInstr = cbInstr;
3482 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3483 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3484 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3485 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3486 }
3487
3488 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3489}
3490
3491
3492/**
3493 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3494 *
3495 * @returns VBox strict status code.
3496 * @param pVCpu The cross context virtual CPU structure.
3497 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3498 * VMXINSTRID_IO_OUT).
3499 * @param u16Port The I/O port being accessed.
3500 * @param fImm Whether the I/O port was encoded using an immediate operand
3501 * or the implicit DX register.
3502 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3503 * @param cbInstr The instruction length in bytes.
3504 */
3505IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3506 uint8_t cbInstr)
3507{
3508 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3509 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3510
3511 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3512 if (fIntercept)
3513 {
3514 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3515 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3516 VMXVEXITINFO ExitInfo;
3517 RT_ZERO(ExitInfo);
3518 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3519 ExitInfo.cbInstr = cbInstr;
3520 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3521 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3522 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3523 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3524 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3525 }
3526
3527 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3528}
3529
3530
3531/**
3532 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3533 *
3534 * @returns VBox strict status code.
3535 * @param pVCpu The cross context virtual CPU structure.
3536 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3537 * VMXINSTRID_IO_OUTS).
3538 * @param u16Port The I/O port being accessed.
3539 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3540 * @param fRep Whether the instruction has a REP prefix or not.
3541 * @param ExitInstrInfo The VM-exit instruction info. field.
3542 * @param cbInstr The instruction length in bytes.
3543 */
3544IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3545 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3546{
3547 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3548 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3549 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3550 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3551 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3552
3553 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3554 if (fIntercept)
3555 {
3556 /*
3557 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3558 */
3559 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3560 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3561 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3562 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3563 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3564
3565 uint32_t uDirection;
3566 uint64_t uGuestLinearAddr;
3567 if (uInstrId == VMXINSTRID_IO_INS)
3568 {
3569 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3570 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3571 }
3572 else
3573 {
3574 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3575 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3576 }
3577
3578 /*
3579 * If the segment is ununsable, the guest-linear address in undefined.
3580 * We shall clear it for consistency.
3581 *
3582 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3583 */
3584 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3585 uGuestLinearAddr = 0;
3586
3587 VMXVEXITINFO ExitInfo;
3588 RT_ZERO(ExitInfo);
3589 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3590 ExitInfo.cbInstr = cbInstr;
3591 ExitInfo.InstrInfo = ExitInstrInfo;
3592 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3593 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3594 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3595 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3596 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3597 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3598 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3599 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3600 }
3601
3602 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3603}
3604
3605
3606/**
3607 * VMX VM-exit handler for VM-exits due to MWAIT.
3608 *
3609 * @returns VBox strict status code.
3610 * @param pVCpu The cross context virtual CPU structure.
3611 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3612 * @param cbInstr The instruction length in bytes.
3613 */
3614IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3615{
3616 VMXVEXITINFO ExitInfo;
3617 RT_ZERO(ExitInfo);
3618 ExitInfo.uReason = VMX_EXIT_MWAIT;
3619 ExitInfo.cbInstr = cbInstr;
3620 ExitInfo.u64Qual = fMonitorHwArmed;
3621 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3622}
3623
3624
3625/**
3626 * VMX VM-exit handler for VM-exits due to PAUSE.
3627 *
3628 * @returns VBox strict status code.
3629 * @param pVCpu The cross context virtual CPU structure.
3630 * @param cbInstr The instruction length in bytes.
3631 */
3632IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3633{
3634 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3635 Assert(pVmcs);
3636
3637 /*
3638 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3639 * "PAUSE-loop exiting" control.
3640 *
3641 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3642 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3643 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3644 * a VM-exit.
3645 *
3646 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3647 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3648 */
3649 bool fIntercept = false;
3650 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3651 fIntercept = true;
3652 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3653 && pVCpu->iem.s.uCpl == 0)
3654 {
3655 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3656
3657 /*
3658 * A previous-PAUSE-tick value of 0 is used to identify the first time
3659 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3660 * consider this to be the first execution of PAUSE in a loop according
3661 * to the Intel.
3662 *
3663 * All subsequent records for the previous-PAUSE-tick we ensure that it
3664 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3665 */
3666 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3667 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3668 uint64_t const uTick = TMCpuTickGet(pVCpu);
3669 uint32_t const uPleGap = pVmcs->u32PleGap;
3670 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3671 if ( *puPrevPauseTick == 0
3672 || uTick - *puPrevPauseTick > uPleGap)
3673 *puFirstPauseLoopTick = uTick;
3674 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3675 fIntercept = true;
3676
3677 *puPrevPauseTick = uTick | 1;
3678 }
3679
3680 if (fIntercept)
3681 {
3682 VMXVEXITINFO ExitInfo;
3683 RT_ZERO(ExitInfo);
3684 ExitInfo.uReason = VMX_EXIT_PAUSE;
3685 ExitInfo.cbInstr = cbInstr;
3686 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3687 }
3688
3689 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3690}
3691
3692
3693/**
3694 * VMX VM-exit handler for VM-exits due to task switches.
3695 *
3696 * @returns VBox strict status code.
3697 * @param pVCpu The cross context virtual CPU structure.
3698 * @param enmTaskSwitch The cause of the task switch.
3699 * @param SelNewTss The selector of the new TSS.
3700 * @param cbInstr The instruction length in bytes.
3701 */
3702IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3703{
3704 /*
3705 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3706 *
3707 * If the the cause of the task switch is due to execution of CALL, IRET or the JMP
3708 * instruction or delivery of the exception generated by one of these instructions
3709 * lead to a task switch through a task gate in the IDT, we need to provide the
3710 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3711 * leaves the VM-exit instruction length field undefined.
3712 *
3713 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3714 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3715 */
3716 Assert(cbInstr <= 15);
3717
3718 uint8_t uType;
3719 switch (enmTaskSwitch)
3720 {
3721 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3722 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3723 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3724 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3725 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3726 }
3727
3728 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3729 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3730 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3731 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3732 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3733}
3734
3735
3736/**
3737 * VMX VM-exit handler for VM-exits due to expiry of the preemption timer.
3738 *
3739 * @returns VBox strict status code.
3740 * @param pVCpu The cross context virtual CPU structure.
3741 */
3742IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3743{
3744 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3745 Assert(pVmcs);
3746 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3747 NOREF(pVmcs);
3748
3749 iemVmxVmcsSetExitQual(pVCpu, 0);
3750 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3751}
3752
3753
3754/**
3755 * VMX VM-exit handler for VM-exits due to external interrupts.
3756 *
3757 * @returns VBox strict status code.
3758 * @param pVCpu The cross context virtual CPU structure.
3759 * @param uVector The external interrupt vector.
3760 * @param fIntPending Whether the external interrupt is pending or
3761 * acknowdledged in the interrupt controller.
3762 */
3763IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3764{
3765 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3766 Assert(pVmcs);
3767
3768 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3769 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3770 {
3771 if (fIntPending)
3772 {
3773 /*
3774 * If the interrupt is pending and we don't need to acknowledge the
3775 * interrupt on VM-exit, cause the VM-exit immediately.
3776 *
3777 * See Intel spec 25.2 "Other Causes Of VM Exits".
3778 */
3779 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3780 {
3781 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3782 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3783 iemVmxVmcsSetExitQual(pVCpu, 0);
3784 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3785 }
3786
3787 /*
3788 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3789 * on VM-exit, postpone VM-exit til after the interrupt controller has been
3790 * acknowledged that the interrupt has been consumed.
3791 */
3792 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3793 }
3794
3795 /*
3796 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3797 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3798 * all set, we cause the VM-exit now. We need to record the external interrupt that
3799 * just occurred in the VM-exit interruption information field.
3800 *
3801 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3802 */
3803 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3804 {
3805 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3806 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3807 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3808 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3809 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3810 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3811 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3812 iemVmxVmcsSetExitQual(pVCpu, 0);
3813 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3814 }
3815 }
3816
3817 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3818}
3819
3820
3821/**
3822 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3823 *
3824 * @returns VBox strict status code.
3825 * @param pVCpu The cross context virtual CPU structure.
3826 * @param uVector The SIPI vector.
3827 */
3828IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3829{
3830 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3831 Assert(pVmcs);
3832
3833 iemVmxVmcsSetExitQual(pVCpu, uVector);
3834 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3835}
3836
3837
3838/**
3839 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3840 *
3841 * @returns VBox strict status code.
3842 * @param pVCpu The cross context virtual CPU structure.
3843 */
3844IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3845{
3846 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3847 Assert(pVmcs);
3848
3849 iemVmxVmcsSetExitQual(pVCpu, 0);
3850 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3851}
3852
3853
3854/**
3855 * VMX VM-exit handler for interrupt-window VM-exits.
3856 *
3857 * @returns VBox strict status code.
3858 * @param pVCpu The cross context virtual CPU structure.
3859 */
3860IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3861{
3862 iemVmxVmcsSetExitQual(pVCpu, 0);
3863 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3864}
3865
3866
3867/**
3868 * VMX VM-exit handler for VM-exits due to delivery of an event.
3869 *
3870 * @returns VBox strict status code.
3871 * @param pVCpu The cross context virtual CPU structure.
3872 * @param uVector The interrupt / exception vector.
3873 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3874 * @param uErrCode The error code associated with the event.
3875 * @param uCr2 The CR2 value in case of a \#PF exception.
3876 * @param cbInstr The instruction length in bytes.
3877 */
3878IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3879 uint8_t cbInstr)
3880{
3881 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3882 Assert(pVmcs);
3883
3884 /*
3885 * If the event is being injected as part of VM-entry, it isn't subject to event
3886 * intercepts in the nested-guest. However, secondary exceptions that occur during
3887 * injection of any event -are- subject to event interception.
3888 *
3889 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3890 */
3891 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3892 {
3893 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3894 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3895 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3896 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3897 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3898 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3899 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3900 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3901 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3902
3903 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3904 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3905 }
3906
3907 /*
3908 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3909 * If not, the caller will continue delivery of the external interrupt as it would
3910 * normally.
3911 */
3912 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3913 {
3914 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3915 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3916 }
3917
3918 /*
3919 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3920 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3921 */
3922 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3923 bool fIntercept = false;
3924 bool fIsHwXcpt = false;
3925 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3926 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3927 {
3928 fIsHwXcpt = true;
3929 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3930 if (uVector == X86_XCPT_NMI)
3931 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3932 else
3933 {
3934 /* Page-faults are subject to masking using its error code. */
3935 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3936 if (uVector == X86_XCPT_PF)
3937 {
3938 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
3939 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
3940 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
3941 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
3942 }
3943
3944 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
3945 if (fXcptBitmap & RT_BIT(uVector))
3946 fIntercept = true;
3947 }
3948 }
3949 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3950
3951 /*
3952 * Now that we've determined whether the software interrupt or hardware exception
3953 * causes a VM-exit, we need to construct the relevant VM-exit information and
3954 * cause the VM-exit.
3955 */
3956 if (fIntercept)
3957 {
3958 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3959
3960 /* Construct the rest of the event related information fields and cause the VM-exit. */
3961 uint64_t uExitQual = 0;
3962 if (fIsHwXcpt)
3963 {
3964 if (uVector == X86_XCPT_PF)
3965 uExitQual = uCr2;
3966 else if (uVector == X86_XCPT_DB)
3967 {
3968 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
3969 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3970 }
3971 }
3972
3973 uint8_t const fNmiUnblocking = 0; /** @todo NSTVMX: Implement NMI-unblocking due to IRET. */
3974 uint8_t const fErrCodeValid = (fFlags & IEM_XCPT_FLAGS_ERR);
3975 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3976 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3977 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3978 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3979 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3980 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3981 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3982 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3983 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3984
3985 /*
3986 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
3987 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3988 * length.
3989 */
3990 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3991 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3992 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3993 else
3994 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3995
3996 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3997 }
3998
3999 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4000}
4001
4002
4003/**
4004 * VMX VM-exit handler for VM-exits due to a triple fault.
4005 *
4006 * @returns VBox strict status code.
4007 * @param pVCpu The cross context virtual CPU structure.
4008 */
4009IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4010{
4011 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4012 Assert(pVmcs);
4013 iemVmxVmcsSetExitQual(pVCpu, 0);
4014 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4015}
4016
4017
4018/**
4019 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4020 *
4021 * @returns The register from the virtual-APIC page.
4022 * @param pVCpu The cross context virtual CPU structure.
4023 * @param offReg The offset of the register being read.
4024 */
4025DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4026{
4027 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4028 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4029 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4030 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4031 return uReg;
4032}
4033
4034
4035/**
4036 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4037 *
4038 * @returns The register from the virtual-APIC page.
4039 * @param pVCpu The cross context virtual CPU structure.
4040 * @param offReg The offset of the register being read.
4041 */
4042DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4043{
4044 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4045 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4046 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4047 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4048 return uReg;
4049}
4050
4051
4052/**
4053 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4054 *
4055 * @param pVCpu The cross context virtual CPU structure.
4056 * @param offReg The offset of the register being written.
4057 * @param uReg The register value to write.
4058 */
4059DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4060{
4061 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4062 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4063 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4064 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4065}
4066
4067
4068/**
4069 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4070 *
4071 * @param pVCpu The cross context virtual CPU structure.
4072 * @param offReg The offset of the register being written.
4073 * @param uReg The register value to write.
4074 */
4075DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4076{
4077 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4078 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4079 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4080 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4081}
4082
4083
4084/**
4085 * Sets the vector in a virtual-APIC 256-bit sparse register.
4086 *
4087 * @param pVCpu The cross context virtual CPU structure.
4088 * @param offReg The offset of the 256-bit spare register.
4089 * @param uVector The vector to set.
4090 *
4091 * @remarks This is based on our APIC device code.
4092 */
4093DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4094{
4095 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4096 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4097 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4098 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4099 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4100}
4101
4102
4103/**
4104 * Clears the vector in a virtual-APIC 256-bit sparse register.
4105 *
4106 * @param pVCpu The cross context virtual CPU structure.
4107 * @param offReg The offset of the 256-bit spare register.
4108 * @param uVector The vector to clear.
4109 *
4110 * @remarks This is based on our APIC device code.
4111 */
4112DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4113{
4114 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4115 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4116 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4117 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4118 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4119}
4120
4121
4122/**
4123 * Checks if a memory access to the APIC-access page must causes an APIC-access
4124 * VM-exit.
4125 *
4126 * @param pVCpu The cross context virtual CPU structure.
4127 * @param offAccess The offset of the register being accessed.
4128 * @param cbAccess The size of the access in bytes.
4129 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4130 * IEM_ACCESS_TYPE_WRITE).
4131 *
4132 * @remarks This must not be used for MSR-based APIC-access page accesses!
4133 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4134 */
4135IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4136{
4137 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4138 Assert(pVmcs);
4139 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4140
4141 /*
4142 * We must cause a VM-exit if any of the following are true:
4143 * - TPR shadowing isn't active.
4144 * - The access size exceeds 32-bits.
4145 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4146 *
4147 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4148 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4149 */
4150 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4151 || cbAccess > sizeof(uint32_t)
4152 || ((offAccess + cbAccess - 1) & 0xc)
4153 || offAccess >= XAPIC_OFF_END + 4)
4154 return true;
4155
4156 /*
4157 * If the access is part of an operation where we have already
4158 * virtualized a virtual-APIC write, we must cause a VM-exit.
4159 */
4160 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_UPDATE_VAPIC))
4161 return true;
4162
4163 /*
4164 * Check write accesses to the APIC-access page that cause VM-exits.
4165 */
4166 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4167 {
4168 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4169 {
4170 /*
4171 * With APIC-register virtualization, a write access to any of the
4172 * following registers are virtualized. Accessing any other register
4173 * causes a VM-exit.
4174 */
4175 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4176 switch (offAlignedAccess)
4177 {
4178 case XAPIC_OFF_ID:
4179 case XAPIC_OFF_TPR:
4180 case XAPIC_OFF_EOI:
4181 case XAPIC_OFF_LDR:
4182 case XAPIC_OFF_DFR:
4183 case XAPIC_OFF_SVR:
4184 case XAPIC_OFF_ESR:
4185 case XAPIC_OFF_ICR_LO:
4186 case XAPIC_OFF_ICR_HI:
4187 case XAPIC_OFF_LVT_TIMER:
4188 case XAPIC_OFF_LVT_THERMAL:
4189 case XAPIC_OFF_LVT_PERF:
4190 case XAPIC_OFF_LVT_LINT0:
4191 case XAPIC_OFF_LVT_LINT1:
4192 case XAPIC_OFF_LVT_ERROR:
4193 case XAPIC_OFF_TIMER_ICR:
4194 case XAPIC_OFF_TIMER_DCR:
4195 break;
4196 default:
4197 return true;
4198 }
4199 }
4200 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4201 {
4202 /*
4203 * With virtual-interrupt delivery, a write access to any of the
4204 * following registers are virtualized. Accessing any other register
4205 * causes a VM-exit.
4206 *
4207 * Note! The specification does not allow writing to offsets in-between
4208 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4209 */
4210 switch (offAccess)
4211 {
4212 case XAPIC_OFF_TPR:
4213 case XAPIC_OFF_EOI:
4214 case XAPIC_OFF_ICR_LO:
4215 break;
4216 default:
4217 return true;
4218 }
4219 }
4220 else
4221 {
4222 /*
4223 * Without APIC-register virtualization or virtual-interrupt delivery,
4224 * only TPR accesses are virtualized.
4225 */
4226 if (offAccess == XAPIC_OFF_TPR)
4227 { /* likely */ }
4228 else
4229 return true;
4230 }
4231 }
4232 else
4233 {
4234 /*
4235 * Check read accesses to the APIC-access page that cause VM-exits.
4236 */
4237 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4238 {
4239 /*
4240 * With APIC-register virtualization, a read access to any of the
4241 * following registers are virtualized. Accessing any other register
4242 * causes a VM-exit.
4243 */
4244 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4245 switch (offAlignedAccess)
4246 {
4247 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4248 case XAPIC_OFF_ID:
4249 case XAPIC_OFF_VERSION:
4250 case XAPIC_OFF_TPR:
4251 case XAPIC_OFF_EOI:
4252 case XAPIC_OFF_LDR:
4253 case XAPIC_OFF_DFR:
4254 case XAPIC_OFF_SVR:
4255 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4256 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4257 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4258 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4259 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4260 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4261 case XAPIC_OFF_ESR:
4262 case XAPIC_OFF_ICR_LO:
4263 case XAPIC_OFF_ICR_HI:
4264 case XAPIC_OFF_LVT_TIMER:
4265 case XAPIC_OFF_LVT_THERMAL:
4266 case XAPIC_OFF_LVT_PERF:
4267 case XAPIC_OFF_LVT_LINT0:
4268 case XAPIC_OFF_LVT_LINT1:
4269 case XAPIC_OFF_LVT_ERROR:
4270 case XAPIC_OFF_TIMER_ICR:
4271 case XAPIC_OFF_TIMER_DCR:
4272 break;
4273 default:
4274 return true;
4275 }
4276 }
4277 else
4278 {
4279 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4280 if (offAccess == XAPIC_OFF_TPR)
4281 { /* likely */ }
4282 else
4283 return true;
4284 }
4285 }
4286
4287 /* The APIC-access is virtualized, does not cause a VM-exit. */
4288 return false;
4289}
4290
4291
4292/**
4293 * VMX VM-exit handler for APIC-accesses.
4294 *
4295 * @param pVCpu The cross context virtual CPU structure.
4296 * @param offAccess The offset of the register being accessed.
4297 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4298 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4299 */
4300IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4301{
4302 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4303
4304 VMXAPICACCESS enmAccess;
4305 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4306 if (fInEventDelivery)
4307 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4308 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4309 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4310 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4311 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4312 else
4313 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4314
4315 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4316 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4317 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4318 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4319}
4320
4321
4322/**
4323 * VMX VM-exit handler for APIC-write VM-exits.
4324 *
4325 * @param pVCpu The cross context virtual CPU structure.
4326 */
4327IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu)
4328{
4329 iemVmxVmcsSetExitQual(pVCpu, pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite);
4330 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4331}
4332
4333
4334/**
4335 * VMX VM-exit handler for virtualized-EOIs.
4336 *
4337 * @param pVCpu The cross context virtual CPU structure.
4338 */
4339IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4340{
4341 iemVmxVmcsSetExitQual(pVCpu, uVector);
4342 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4343}
4344
4345
4346/**
4347 * Virtualizes a memory-based APIC-access where the address is not used to access
4348 * memory.
4349 *
4350 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4351 * page-faults but do not use the address to access memory.
4352 *
4353 * @param pVCpu The cross context virtual CPU structure.
4354 * @param pGCPhysAccess Pointer to the guest-physical address used.
4355 */
4356IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4357{
4358 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4359 Assert(pVmcs);
4360 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4361 Assert(pGCPhysAccess);
4362
4363 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4364 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4365 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4366
4367 if (GCPhysAccess == GCPhysApic)
4368 {
4369 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4370 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4371 uint16_t const cbAccess = 1;
4372 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4373 if (fIntercept)
4374 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4375
4376 *pGCPhysAccess = GCPhysApic | offAccess;
4377 return VINF_VMX_MODIFIES_BEHAVIOR;
4378 }
4379
4380 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4381}
4382
4383
4384/**
4385 * Virtualizes a memory-based APIC-access.
4386 *
4387 * @returns VBox strict status code.
4388 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4389 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4390 *
4391 * @param pVCpu The cross context virtual CPU structure.
4392 * @param offAccess The offset of the register being accessed (within the
4393 * APIC-access page).
4394 * @param cbAccess The size of the access in bytes.
4395 * @param pvData Pointer to the data being written or where to store the data
4396 * being read.
4397 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4398 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4399 */
4400IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4401 uint32_t fAccess)
4402{
4403 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4404 Assert(pVmcs);
4405 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4406 Assert(pvData);
4407 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4408 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4409 || (fAccess & IEM_ACCESS_INSTRUCTION));
4410
4411 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4412 if (fIntercept)
4413 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4414
4415 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4416 {
4417 /*
4418 * A write access to the APIC-access page that is virtualized (rather than
4419 * causing a VM-exit) writes data to the virtual-APIC page.
4420 */
4421 uint32_t const u32Data = *(uint32_t *)pvData;
4422 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4423
4424 /*
4425 * Record the currently updated APIC offset, as we need this later for figuring
4426 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4427 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4428 *
4429 * After completion of the current operation, we need to perform TPR virtualization,
4430 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4431 *
4432 * The current operation may be a REP-prefixed string instruction, execution of any
4433 * other instruction, or delivery of an event through the IDT.
4434 *
4435 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4436 * performed now but later after completion of the current operation.
4437 *
4438 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4439 */
4440 iemVmxVirtApicSetPostAction(pVCpu, offAccess);
4441 }
4442 else
4443 {
4444 /*
4445 * A read access from the APIC-access page that is virtualized (rather than
4446 * causing a VM-exit) returns data from the virtual-APIC page.
4447 *
4448 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4449 */
4450 Assert(cbAccess <= 4);
4451 Assert(offAccess < XAPIC_OFF_END + 4);
4452 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4453
4454 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4455 u32Data &= s_auAccessSizeMasks[cbAccess];
4456 *(uint32_t *)pvData = u32Data;
4457 }
4458
4459 return VINF_VMX_MODIFIES_BEHAVIOR;
4460}
4461
4462
4463/**
4464 * Virtualizes an MSR-based APIC read access.
4465 *
4466 * @returns VBox strict status code.
4467 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4468 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4469 * handled by the x2APIC device.
4470 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4471 * not within the range of valid MSRs, caller must raise \#GP(0).
4472 * @param pVCpu The cross context virtual CPU structure.
4473 * @param idMsr The x2APIC MSR being read.
4474 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4475 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4476 */
4477IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4478{
4479 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4480 Assert(pVmcs);
4481 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4482 Assert(pu64Value);
4483
4484 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4485 {
4486 /*
4487 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4488 * what the end of the valid x2APIC MSR range is. Hence the use of different
4489 * macros here.
4490 *
4491 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4492 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4493 */
4494 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4495 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4496 {
4497 uint16_t const offReg = (idMsr & 0xff) << 4;
4498 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4499 *pu64Value = u64Value;
4500 return VINF_VMX_MODIFIES_BEHAVIOR;
4501 }
4502 return VERR_OUT_OF_RANGE;
4503 }
4504
4505 if (idMsr == MSR_IA32_X2APIC_TPR)
4506 {
4507 uint16_t const offReg = (idMsr & 0xff) << 4;
4508 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4509 *pu64Value = u64Value;
4510 return VINF_VMX_MODIFIES_BEHAVIOR;
4511 }
4512
4513 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4514}
4515
4516
4517/**
4518 * Virtualizes an MSR-based APIC write access.
4519 *
4520 * @returns VBox strict status code.
4521 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4522 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4523 * not within the range of valid MSRs, caller must raise \#GP(0).
4524 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4525 *
4526 * @param pVCpu The cross context virtual CPU structure.
4527 * @param idMsr The x2APIC MSR being written.
4528 * @param u64Value The value of the x2APIC MSR being written.
4529 */
4530IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4531{
4532 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4533 Assert(pVmcs);
4534
4535 /*
4536 * Check if the access is to be virtualized.
4537 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4538 */
4539 if ( idMsr == MSR_IA32_X2APIC_TPR
4540 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4541 && ( idMsr == MSR_IA32_X2APIC_EOI
4542 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4543 {
4544 /* Validate the MSR write depending on the register. */
4545 switch (idMsr)
4546 {
4547 case MSR_IA32_X2APIC_TPR:
4548 case MSR_IA32_X2APIC_SELF_IPI:
4549 {
4550 if (u64Value & UINT64_C(0xffffffffffffff00))
4551 return VERR_OUT_OF_RANGE;
4552 break;
4553 }
4554 case MSR_IA32_X2APIC_EOI:
4555 {
4556 if (u64Value != 0)
4557 return VERR_OUT_OF_RANGE;
4558 break;
4559 }
4560 }
4561
4562 /* Write the MSR to the virtual-APIC page. */
4563 uint16_t const offReg = (idMsr & 0xff) << 4;
4564 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4565
4566 /*
4567 * Record the currently updated APIC offset, as we need this later for figuring
4568 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4569 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4570 */
4571 iemVmxVirtApicSetPostAction(pVCpu, offReg);
4572
4573 return VINF_VMX_MODIFIES_BEHAVIOR;
4574 }
4575
4576 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4577}
4578
4579
4580/**
4581 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4582 *
4583 * @returns VBox status code.
4584 * @retval VINF_SUCCES when the highest set bit is found.
4585 * @retval VERR_NOT_FOUND when no bit is set.
4586 *
4587 * @param pVCpu The cross context virtual CPU structure.
4588 * @param offReg The offset of the APIC 256-bit sparse register.
4589 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4590 * set in the register. Only valid when VINF_SUCCESS is
4591 * returned.
4592 *
4593 * @remarks The format of the 256-bit sparse register here mirrors that found in
4594 * real APIC hardware.
4595 */
4596static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4597{
4598 Assert(offReg < XAPIC_OFF_END + 4);
4599 Assert(pidxHighestBit);
4600
4601 /*
4602 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4603 * However, in each fragment only the first 4 bytes are used.
4604 */
4605 uint8_t const cFrags = 8;
4606 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4607 {
4608 uint16_t const offFrag = iFrag * 16;
4609 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offFrag);
4610 if (!u32Frag)
4611 continue;
4612
4613 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4614 Assert(idxHighestBit > 0);
4615 --idxHighestBit;
4616 Assert(idxHighestBit <= UINT8_MAX);
4617 *pidxHighestBit = idxHighestBit;
4618 return VINF_SUCCESS;
4619 }
4620 return VERR_NOT_FOUND;
4621}
4622
4623
4624/**
4625 * Evaluates pending virtual interrupts.
4626 *
4627 * @param pVCpu The cross context virtual CPU structure.
4628 */
4629IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4630{
4631 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4632 Assert(pVmcs);
4633 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4634
4635 /** @todo NSTVMX: evaluate pending virtual interrupts. */
4636 RT_NOREF(pVCpu);
4637}
4638
4639
4640/**
4641 * Performs PPR virtualization.
4642 *
4643 * @returns VBox strict status code.
4644 * @param pVCpu The cross context virtual CPU structure.
4645 */
4646IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4647{
4648 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4649 Assert(pVmcs);
4650 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4651 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4652
4653 /*
4654 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4655 * or EOI-virtualization.
4656 *
4657 * See Intel spec. 29.1.3 "PPR Virtualization".
4658 */
4659 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4660 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4661
4662 uint32_t uVPpr;
4663 if (((uVTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4664 uVPpr = uVTpr & 0xff;
4665 else
4666 uVPpr = uSvi & 0xf0;
4667 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uVPpr);
4668 Log2(("ppr_virt: uVTpr=%u uSvi=%u -> VM-exit\n", uVTpr, uSvi));
4669}
4670
4671
4672/**
4673 * Performs VMX TPR virtualization.
4674 *
4675 * @returns VBox strict status code.
4676 * @param pVCpu The cross context virtual CPU structure.
4677 */
4678IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4679{
4680 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4681 Assert(pVmcs);
4682 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4683
4684 /*
4685 * We should have already performed the virtual-APIC write to the TPR offset
4686 * in the virtual-APIC page. We now perform TPR virtualization.
4687 *
4688 * See Intel spec. 29.1.2 "TPR Virtualization".
4689 */
4690 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4691 {
4692 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4693 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4694
4695 /*
4696 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4697 * See Intel spec. 29.1.2 "TPR Virtualization".
4698 */
4699 if (((uVTpr >> 4) & 0xf) < uTprThreshold)
4700 {
4701 Log2(("tpr_virt: uVTpr=%u uTprThreshold=%u -> VM-exit\n", uVTpr, uTprThreshold));
4702 iemVmxVmcsSetExitQual(pVCpu, 0);
4703 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4704 }
4705 }
4706 else
4707 {
4708 iemVmxPprVirtualization(pVCpu);
4709 iemVmxEvalPendingVirtIntrs(pVCpu);
4710 }
4711
4712 return VINF_SUCCESS;
4713}
4714
4715
4716/**
4717 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4718 * not.
4719 *
4720 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4721 * @param pVCpu The cross context virtual CPU structure.
4722 * @param uVector The interrupt that was acknowledged using an EOI.
4723 */
4724IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4725{
4726 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4727 Assert(pVmcs);
4728 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4729
4730 if (uVector < 64)
4731 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4732 if (uVector < 128)
4733 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4734 if (uVector < 192)
4735 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4736 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4737}
4738
4739
4740/**
4741 * Performs EOI virtualization.
4742 *
4743 * @returns VBox strict status code.
4744 * @param pVCpu The cross context virtual CPU structure.
4745 */
4746IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4747{
4748 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4749 Assert(pVmcs);
4750 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4751
4752 /*
4753 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4754 * and get the next guest-interrupt that's in-service (if any).
4755 *
4756 * See Intel spec. 29.1.4 "EOI Virtualization".
4757 */
4758 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4759 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4760
4761 uint8_t uVector = uSvi;
4762 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4763
4764 uVector = 0;
4765 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4766
4767 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4768 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4769
4770 iemVmxPprVirtualization(pVCpu);
4771 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4772 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4773 iemVmxEvalPendingVirtIntrs(pVCpu);
4774 return VINF_SUCCESS;
4775}
4776
4777
4778/**
4779 * Performs self-IPI virtualization.
4780 *
4781 * @returns VBox strict status code.
4782 * @param pVCpu The cross context virtual CPU structure.
4783 */
4784IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4785{
4786 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4787 Assert(pVmcs);
4788 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4789
4790 /*
4791 * We should have already performed the virtual-APIC write to the self-IPI offset
4792 * in the virtual-APIC page. We now perform self-IPI virtualization.
4793 *
4794 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4795 */
4796 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, X2APIC_OFF_SELF_IPI);
4797
4798 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
4799 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4800 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4801 if (uVector > uRvi)
4802 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4803 iemVmxEvalPendingVirtIntrs(pVCpu);
4804 return VINF_SUCCESS;
4805}
4806
4807
4808/**
4809 * Performs VMX APIC-write emulation.
4810 *
4811 * @returns VBox strict status code.
4812 * @param pVCpu The cross context virtual CPU structure.
4813 */
4814IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4815{
4816 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4817 Assert(pVmcs);
4818 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
4819
4820 /** @todo NSTVMX: APIC-write emulation. */
4821 RT_NOREF(pVCpu);
4822
4823 return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
4824}
4825
4826
4827/**
4828 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4829 *
4830 * @param pVCpu The cross context virtual CPU structure.
4831 * @param pszInstr The VMX instruction name (for logging purposes).
4832 */
4833IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
4834{
4835 /*
4836 * Guest Control Registers, Debug Registers, and MSRs.
4837 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4838 */
4839 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4840 const char *const pszFailure = "VM-exit";
4841 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4842
4843 /* CR0 reserved bits. */
4844 {
4845 /* CR0 MB1 bits. */
4846 uint64_t u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
4847 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4848 if (fUnrestrictedGuest)
4849 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4850 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
4851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4852
4853 /* CR0 MBZ bits. */
4854 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
4855 if (pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1)
4856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4857
4858 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4859 if ( !fUnrestrictedGuest
4860 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4861 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4863 }
4864
4865 /* CR4 reserved bits. */
4866 {
4867 /* CR4 MB1 bits. */
4868 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
4869 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
4870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4871
4872 /* CR4 MBZ bits. */
4873 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
4874 if (pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1)
4875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4876 }
4877
4878 /* DEBUGCTL MSR. */
4879 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4880 && (pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4882
4883 /* 64-bit CPU checks. */
4884 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4885 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4886 {
4887 if (fGstInLongMode)
4888 {
4889 /* PAE must be set. */
4890 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4891 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4892 { /* likely */ }
4893 else
4894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4895 }
4896 else
4897 {
4898 /* PCIDE should not be set. */
4899 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4900 { /* likely */ }
4901 else
4902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4903 }
4904
4905 /* CR3. */
4906 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4907 { /* likely */ }
4908 else
4909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4910
4911 /* DR7. */
4912 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4913 && (pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4915
4916 /* SYSENTER ESP and SYSENTER EIP. */
4917 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4918 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4919 { /* likely */ }
4920 else
4921 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4922 }
4923
4924 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4925 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4926
4927 /* PAT MSR. */
4928 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4929 && !CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4931
4932 /* EFER MSR. */
4933 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4934 if ( (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4935 && (pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4936 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4937
4938 bool const fGstLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
4939 bool const fGstLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
4940 if ( fGstInLongMode == fGstLma
4941 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4942 || fGstLma == fGstLme))
4943 { /* likely */ }
4944 else
4945 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4946
4947 /* We don't support IA32_BNDCFGS MSR yet. */
4948 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4949
4950 NOREF(pszInstr);
4951 NOREF(pszFailure);
4952 return VINF_SUCCESS;
4953}
4954
4955
4956/**
4957 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4958 *
4959 * @param pVCpu The cross context virtual CPU structure.
4960 * @param pszInstr The VMX instruction name (for logging purposes).
4961 */
4962IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4963{
4964 /*
4965 * Segment registers.
4966 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4967 */
4968 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4969 const char *const pszFailure = "VM-exit";
4970 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4971 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4972 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4973
4974 /* Selectors. */
4975 if ( !fGstInV86Mode
4976 && !fUnrestrictedGuest
4977 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4979
4980 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4981 {
4982 CPUMSELREG SelReg;
4983 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4984 if (RT_LIKELY(rc == VINF_SUCCESS))
4985 { /* likely */ }
4986 else
4987 return rc;
4988
4989 /*
4990 * Virtual-8086 mode checks.
4991 */
4992 if (fGstInV86Mode)
4993 {
4994 /* Base address. */
4995 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4996 { /* likely */ }
4997 else
4998 {
4999 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5001 }
5002
5003 /* Limit. */
5004 if (SelReg.u32Limit == 0xffff)
5005 { /* likely */ }
5006 else
5007 {
5008 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5010 }
5011
5012 /* Attribute. */
5013 if (SelReg.Attr.u == 0xf3)
5014 { /* likely */ }
5015 else
5016 {
5017 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5019 }
5020
5021 /* We're done; move to checking the next segment. */
5022 continue;
5023 }
5024
5025 /* Checks done by 64-bit CPUs. */
5026 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5027 {
5028 /* Base address. */
5029 if ( iSegReg == X86_SREG_FS
5030 || iSegReg == X86_SREG_GS)
5031 {
5032 if (X86_IS_CANONICAL(SelReg.u64Base))
5033 { /* likely */ }
5034 else
5035 {
5036 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5038 }
5039 }
5040 else if (iSegReg == X86_SREG_CS)
5041 {
5042 if (!RT_HI_U32(SelReg.u64Base))
5043 { /* likely */ }
5044 else
5045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5046 }
5047 else
5048 {
5049 if ( SelReg.Attr.n.u1Unusable
5050 || !RT_HI_U32(SelReg.u64Base))
5051 { /* likely */ }
5052 else
5053 {
5054 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5056 }
5057 }
5058 }
5059
5060 /*
5061 * Checks outside Virtual-8086 mode.
5062 */
5063 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5064 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5065 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5066 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5067 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5068 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5069 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5070 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5071
5072 /* Code or usable segment. */
5073 if ( iSegReg == X86_SREG_CS
5074 || fUsable)
5075 {
5076 /* Reserved bits (bits 31:17 and bits 11:8). */
5077 if (!(SelReg.Attr.u & 0xfffe0f00))
5078 { /* likely */ }
5079 else
5080 {
5081 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5083 }
5084
5085 /* Descriptor type. */
5086 if (fCodeDataSeg)
5087 { /* likely */ }
5088 else
5089 {
5090 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5092 }
5093
5094 /* Present. */
5095 if (fPresent)
5096 { /* likely */ }
5097 else
5098 {
5099 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5101 }
5102
5103 /* Granularity. */
5104 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5105 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5106 { /* likely */ }
5107 else
5108 {
5109 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5111 }
5112 }
5113
5114 if (iSegReg == X86_SREG_CS)
5115 {
5116 /* Segment Type and DPL. */
5117 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5118 && fUnrestrictedGuest)
5119 {
5120 if (uDpl == 0)
5121 { /* likely */ }
5122 else
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5124 }
5125 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5126 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5127 {
5128 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5129 if (uDpl == AttrSs.n.u2Dpl)
5130 { /* likely */ }
5131 else
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5133 }
5134 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5135 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5136 {
5137 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5138 if (uDpl <= AttrSs.n.u2Dpl)
5139 { /* likely */ }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5142 }
5143 else
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5145
5146 /* Def/Big. */
5147 if ( fGstInLongMode
5148 && fSegLong)
5149 {
5150 if (uDefBig == 0)
5151 { /* likely */ }
5152 else
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5154 }
5155 }
5156 else if (iSegReg == X86_SREG_SS)
5157 {
5158 /* Segment Type. */
5159 if ( !fUsable
5160 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5161 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5165
5166 /* DPL. */
5167 if (fUnrestrictedGuest)
5168 {
5169 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5173 }
5174 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5175 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5176 || (pVmcs->u64GuestCr0.u & X86_CR0_PE))
5177 {
5178 if (uDpl == 0)
5179 { /* likely */ }
5180 else
5181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5182 }
5183 }
5184 else
5185 {
5186 /* DS, ES, FS, GS. */
5187 if (fUsable)
5188 {
5189 /* Segment type. */
5190 if (uSegType & X86_SEL_TYPE_ACCESSED)
5191 { /* likely */ }
5192 else
5193 {
5194 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5196 }
5197
5198 if ( !(uSegType & X86_SEL_TYPE_CODE)
5199 || (uSegType & X86_SEL_TYPE_READ))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5203
5204 /* DPL. */
5205 if ( !fUnrestrictedGuest
5206 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5207 {
5208 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5209 { /* likely */ }
5210 else
5211 {
5212 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5214 }
5215 }
5216 }
5217 }
5218 }
5219
5220 /*
5221 * LDTR.
5222 */
5223 {
5224 CPUMSELREG Ldtr;
5225 Ldtr.Sel = pVmcs->GuestLdtr;
5226 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5227 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5228 Ldtr.Attr.u = pVmcs->u32GuestLdtrLimit;
5229
5230 if (!Ldtr.Attr.n.u1Unusable)
5231 {
5232 /* Selector. */
5233 if (!(Ldtr.Sel & X86_SEL_LDT))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5237
5238 /* Base. */
5239 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5240 {
5241 if (X86_IS_CANONICAL(Ldtr.u64Base))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5245 }
5246
5247 /* Attributes. */
5248 /* Reserved bits (bits 31:17 and bits 11:8). */
5249 if (!(Ldtr.Attr.u & 0xfffe0f00))
5250 { /* likely */ }
5251 else
5252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5253
5254 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5258
5259 if (!Ldtr.Attr.n.u1DescType)
5260 { /* likely */ }
5261 else
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5263
5264 if (Ldtr.Attr.n.u1Present)
5265 { /* likely */ }
5266 else
5267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5268
5269 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5270 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5271 { /* likely */ }
5272 else
5273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5274 }
5275 }
5276
5277 /*
5278 * TR.
5279 */
5280 {
5281 CPUMSELREG Tr;
5282 Tr.Sel = pVmcs->GuestTr;
5283 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5284 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5285 Tr.Attr.u = pVmcs->u32GuestTrLimit;
5286
5287 /* Selector. */
5288 if (!(Tr.Sel & X86_SEL_LDT))
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5292
5293 /* Base. */
5294 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5295 {
5296 if (X86_IS_CANONICAL(Tr.u64Base))
5297 { /* likely */ }
5298 else
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5300 }
5301
5302 /* Attributes. */
5303 /* Reserved bits (bits 31:17 and bits 11:8). */
5304 if (!(Tr.Attr.u & 0xfffe0f00))
5305 { /* likely */ }
5306 else
5307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5308
5309 if (!Tr.Attr.n.u1Unusable)
5310 { /* likely */ }
5311 else
5312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5313
5314 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5315 || ( !fGstInLongMode
5316 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5317 { /* likely */ }
5318 else
5319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5320
5321 if (!Tr.Attr.n.u1DescType)
5322 { /* likely */ }
5323 else
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5325
5326 if (Tr.Attr.n.u1Present)
5327 { /* likely */ }
5328 else
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5330
5331 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5332 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5333 { /* likely */ }
5334 else
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5336 }
5337
5338 NOREF(pszInstr);
5339 NOREF(pszFailure);
5340 return VINF_SUCCESS;
5341}
5342
5343
5344/**
5345 * Checks guest GDTR and IDTR as part of VM-entry.
5346 *
5347 * @param pVCpu The cross context virtual CPU structure.
5348 * @param pszInstr The VMX instruction name (for logging purposes).
5349 */
5350IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5351{
5352 /*
5353 * GDTR and IDTR.
5354 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5355 */
5356 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5357 const char *const pszFailure = "VM-exit";
5358
5359 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5360 {
5361 /* Base. */
5362 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5363 { /* likely */ }
5364 else
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5366
5367 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5371 }
5372
5373 /* Limit. */
5374 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5375 { /* likely */ }
5376 else
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5378
5379 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5380 { /* likely */ }
5381 else
5382 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5383
5384 NOREF(pszInstr);
5385 NOREF(pszFailure);
5386 return VINF_SUCCESS;
5387}
5388
5389
5390/**
5391 * Checks guest RIP and RFLAGS as part of VM-entry.
5392 *
5393 * @param pVCpu The cross context virtual CPU structure.
5394 * @param pszInstr The VMX instruction name (for logging purposes).
5395 */
5396IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5397{
5398 /*
5399 * RIP and RFLAGS.
5400 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5401 */
5402 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5403 const char *const pszFailure = "VM-exit";
5404 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5405
5406 /* RIP. */
5407 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5408 {
5409 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5410 if ( !fGstInLongMode
5411 || !AttrCs.n.u1Long)
5412 {
5413 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5414 { /* likely */ }
5415 else
5416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5417 }
5418
5419 if ( fGstInLongMode
5420 && AttrCs.n.u1Long)
5421 {
5422 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5423 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5424 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5425 { /* likely */ }
5426 else
5427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5428 }
5429 }
5430
5431 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5432 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5433 : pVmcs->u64GuestRFlags.s.Lo;
5434 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5435 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5436 { /* likely */ }
5437 else
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5439
5440 if ( fGstInLongMode
5441 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5442 {
5443 if (!(uGuestRFlags & X86_EFL_VM))
5444 { /* likely */ }
5445 else
5446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5447 }
5448
5449 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5450 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5451 {
5452 if (uGuestRFlags & X86_EFL_IF)
5453 { /* likely */ }
5454 else
5455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5456 }
5457
5458 NOREF(pszInstr);
5459 NOREF(pszFailure);
5460 return VINF_SUCCESS;
5461}
5462
5463
5464/**
5465 * Checks guest non-register state as part of VM-entry.
5466 *
5467 * @param pVCpu The cross context virtual CPU structure.
5468 * @param pszInstr The VMX instruction name (for logging purposes).
5469 */
5470IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5471{
5472 /*
5473 * Guest non-register state.
5474 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5475 */
5476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5477 const char *const pszFailure = "VM-exit";
5478
5479 /*
5480 * Activity state.
5481 */
5482 uint64_t const u64GuestVmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu);
5483 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5484 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5488
5489 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5490 if ( !AttrSs.n.u2Dpl
5491 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5495
5496 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5497 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5498 {
5499 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5500 { /* likely */ }
5501 else
5502 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5503 }
5504
5505 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5506 {
5507 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5508 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5509 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5510 switch (pVmcs->u32GuestActivityState)
5511 {
5512 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5513 {
5514 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5515 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5516 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5517 && ( uVector == X86_XCPT_DB
5518 || uVector == X86_XCPT_MC))
5519 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5520 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5524 break;
5525 }
5526
5527 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5528 {
5529 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5530 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5531 && uVector == X86_XCPT_MC))
5532 { /* likely */ }
5533 else
5534 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5535 break;
5536 }
5537
5538 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5539 default:
5540 break;
5541 }
5542 }
5543
5544 /*
5545 * Interruptibility state.
5546 */
5547 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5548 { /* likely */ }
5549 else
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5551
5552 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5553 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5557
5558 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5559 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5560 { /* likely */ }
5561 else
5562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5563
5564 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5565 {
5566 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5567 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5568 {
5569 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5570 { /* likely */ }
5571 else
5572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5573 }
5574 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5575 {
5576 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5577 { /* likely */ }
5578 else
5579 {
5580 /*
5581 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5582 * We update the VM-exit qualification only when blocking-by-STI is set
5583 * without blocking-by-MovSS being set. Although in practise it does not
5584 * make much difference since the order of checks are implementation defined.
5585 */
5586 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5587 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5589 }
5590
5591 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5592 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5596 }
5597 }
5598
5599 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5600 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5601 { /* likely */ }
5602 else
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5604
5605 /* We don't support SGX yet. So enclave-interruption must not be set. */
5606 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5610
5611 /*
5612 * Pending debug exceptions.
5613 */
5614 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5615 ? pVmcs->u64GuestPendingDbgXcpt.u
5616 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5617 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5621
5622 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5623 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5624 {
5625 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5626 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5627 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5629
5630 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5631 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5632 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5634 }
5635
5636 /* We don't support RTM (Real-time Transactional Memory) yet. */
5637 if (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
5638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5639
5640 /*
5641 * VMCS link pointer.
5642 */
5643 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5644 {
5645 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5646 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5647 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5648 { /* likely */ }
5649 else
5650 {
5651 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5653 }
5654
5655 /* Validate the address. */
5656 if ( (GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5657 || (GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5658 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5659 {
5660 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5662 }
5663
5664 /* Read the VMCS-link pointer from guest memory. */
5665 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5666 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5667 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5668 if (RT_FAILURE(rc))
5669 {
5670 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5672 }
5673
5674 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5675 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5676 { /* likely */ }
5677 else
5678 {
5679 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5681 }
5682
5683 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5684 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5685 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5686 { /* likely */ }
5687 else
5688 {
5689 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5691 }
5692
5693 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5694 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5695 }
5696
5697 NOREF(pszInstr);
5698 NOREF(pszFailure);
5699 return VINF_SUCCESS;
5700}
5701
5702
5703/**
5704 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5705 * VM-entry.
5706 *
5707 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5708 * @param pVCpu The cross context virtual CPU structure.
5709 * @param pszInstr The VMX instruction name (for logging purposes).
5710 * @param pVmcs Pointer to the virtual VMCS.
5711 */
5712IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5713{
5714 /*
5715 * Check PDPTEs.
5716 * See Intel spec. 4.4.1 "PDPTE Registers".
5717 */
5718 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5719 const char *const pszFailure = "VM-exit";
5720
5721 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5722 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5723 if (RT_SUCCESS(rc))
5724 {
5725 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5726 {
5727 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5728 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5729 { /* likely */ }
5730 else
5731 {
5732 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5733 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5735 }
5736 }
5737 }
5738 else
5739 {
5740 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5742 }
5743
5744 NOREF(pszFailure);
5745 return rc;
5746}
5747
5748
5749/**
5750 * Checks guest PDPTEs as part of VM-entry.
5751 *
5752 * @param pVCpu The cross context virtual CPU structure.
5753 * @param pszInstr The VMX instruction name (for logging purposes).
5754 */
5755IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5756{
5757 /*
5758 * Guest PDPTEs.
5759 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5760 */
5761 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5762 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5763
5764 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5765 int rc;
5766 if ( !fGstInLongMode
5767 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5768 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5769 {
5770 /*
5771 * We don't support nested-paging for nested-guests yet.
5772 *
5773 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5774 * rather we need to check the PDPTEs referenced by the guest CR3.
5775 */
5776 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5777 }
5778 else
5779 rc = VINF_SUCCESS;
5780 return rc;
5781}
5782
5783
5784/**
5785 * Checks guest-state as part of VM-entry.
5786 *
5787 * @returns VBox status code.
5788 * @param pVCpu The cross context virtual CPU structure.
5789 * @param pszInstr The VMX instruction name (for logging purposes).
5790 */
5791IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5792{
5793 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5794 if (RT_SUCCESS(rc))
5795 {
5796 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5797 if (RT_SUCCESS(rc))
5798 {
5799 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5800 if (RT_SUCCESS(rc))
5801 {
5802 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5803 if (RT_SUCCESS(rc))
5804 {
5805 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5806 if (RT_SUCCESS(rc))
5807 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5808 }
5809 }
5810 }
5811 }
5812 return rc;
5813}
5814
5815
5816/**
5817 * Checks host-state as part of VM-entry.
5818 *
5819 * @returns VBox status code.
5820 * @param pVCpu The cross context virtual CPU structure.
5821 * @param pszInstr The VMX instruction name (for logging purposes).
5822 */
5823IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
5824{
5825 /*
5826 * Host Control Registers and MSRs.
5827 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5828 */
5829 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5830 const char * const pszFailure = "VMFail";
5831
5832 /* CR0 reserved bits. */
5833 {
5834 /* CR0 MB1 bits. */
5835 uint64_t const u64Cr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
5836 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) != u64Cr0Fixed0)
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5838
5839 /* CR0 MBZ bits. */
5840 uint64_t const u64Cr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
5841 if (pVmcs->u64HostCr0.u & ~u64Cr0Fixed1)
5842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5843 }
5844
5845 /* CR4 reserved bits. */
5846 {
5847 /* CR4 MB1 bits. */
5848 uint64_t const u64Cr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
5849 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) != u64Cr4Fixed0)
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5851
5852 /* CR4 MBZ bits. */
5853 uint64_t const u64Cr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
5854 if (pVmcs->u64HostCr4.u & ~u64Cr4Fixed1)
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5856 }
5857
5858 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5859 {
5860 /* CR3 reserved bits. */
5861 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5862 { /* likely */ }
5863 else
5864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5865
5866 /* SYSENTER ESP and SYSENTER EIP. */
5867 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5868 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5872 }
5873
5874 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5875 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5876
5877 /* PAT MSR. */
5878 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5879 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5883
5884 /* EFER MSR. */
5885 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5886 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5887 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5888 { /* likely */ }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5891
5892 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5893 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LMA);
5894 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_BIT_LME);
5895 if ( fHostInLongMode == fHostLma
5896 && fHostInLongMode == fHostLme)
5897 { /* likely */ }
5898 else
5899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5900
5901 /*
5902 * Host Segment and Descriptor-Table Registers.
5903 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5904 */
5905 /* Selector RPL and TI. */
5906 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5907 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5908 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5909 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5910 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5911 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5912 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5916
5917 /* CS and TR selectors cannot be 0. */
5918 if ( pVmcs->HostCs
5919 && pVmcs->HostTr)
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5923
5924 /* SS cannot be 0 if 32-bit host. */
5925 if ( fHostInLongMode
5926 || pVmcs->HostSs)
5927 { /* likely */ }
5928 else
5929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5930
5931 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5932 {
5933 /* FS, GS, GDTR, IDTR, TR base address. */
5934 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5935 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5936 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5937 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5938 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5942 }
5943
5944 /*
5945 * Host address-space size for 64-bit CPUs.
5946 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5947 */
5948 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5949 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5950 {
5951 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5952
5953 /* Logical processor in IA-32e mode. */
5954 if (fCpuInLongMode)
5955 {
5956 if (fHostInLongMode)
5957 {
5958 /* PAE must be set. */
5959 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5963
5964 /* RIP must be canonical. */
5965 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5966 { /* likely */ }
5967 else
5968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5969 }
5970 else
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5972 }
5973 else
5974 {
5975 /* Logical processor is outside IA-32e mode. */
5976 if ( !fGstInLongMode
5977 && !fHostInLongMode)
5978 {
5979 /* PCIDE should not be set. */
5980 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5981 { /* likely */ }
5982 else
5983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5984
5985 /* The high 32-bits of RIP MBZ. */
5986 if (!pVmcs->u64HostRip.s.Hi)
5987 { /* likely */ }
5988 else
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5990 }
5991 else
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5993 }
5994 }
5995 else
5996 {
5997 /* Host address-space size for 32-bit CPUs. */
5998 if ( !fGstInLongMode
5999 && !fHostInLongMode)
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6003 }
6004
6005 NOREF(pszInstr);
6006 NOREF(pszFailure);
6007 return VINF_SUCCESS;
6008}
6009
6010
6011/**
6012 * Checks VM-entry controls fields as part of VM-entry.
6013 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6014 *
6015 * @returns VBox status code.
6016 * @param pVCpu The cross context virtual CPU structure.
6017 * @param pszInstr The VMX instruction name (for logging purposes).
6018 */
6019IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6020{
6021 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6022 const char * const pszFailure = "VMFail";
6023
6024 /* VM-entry controls. */
6025 VMXCTLSMSR EntryCtls;
6026 EntryCtls.u = CPUMGetGuestIa32VmxEntryCtls(pVCpu);
6027 if (~pVmcs->u32EntryCtls & EntryCtls.n.disallowed0)
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6029
6030 if (pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1)
6031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6032
6033 /* Event injection. */
6034 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6035 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6036 {
6037 /* Type and vector. */
6038 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6039 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6040 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6041 if ( !uRsvd
6042 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6043 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6044 { /* likely */ }
6045 else
6046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6047
6048 /* Exception error code. */
6049 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6050 {
6051 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6052 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6053 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6054 { /* likely */ }
6055 else
6056 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6057
6058 /* Exceptions that provide an error code. */
6059 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6060 && ( uVector == X86_XCPT_DF
6061 || uVector == X86_XCPT_TS
6062 || uVector == X86_XCPT_NP
6063 || uVector == X86_XCPT_SS
6064 || uVector == X86_XCPT_GP
6065 || uVector == X86_XCPT_PF
6066 || uVector == X86_XCPT_AC))
6067 { /* likely */ }
6068 else
6069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6070
6071 /* Exception error-code reserved bits. */
6072 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6073 { /* likely */ }
6074 else
6075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6076
6077 /* Injecting a software interrupt, software exception or privileged software exception. */
6078 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6079 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6080 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6081 {
6082 /* Instruction length must be in the range 0-15. */
6083 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6084 { /* likely */ }
6085 else
6086 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6087
6088 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6089 if ( pVmcs->u32EntryInstrLen == 0
6090 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6092 }
6093 }
6094 }
6095
6096 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6097 if (pVmcs->u32EntryMsrLoadCount)
6098 {
6099 if ( (pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6100 || (pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6101 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6103 }
6104
6105 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6106 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6107
6108 NOREF(pszInstr);
6109 NOREF(pszFailure);
6110 return VINF_SUCCESS;
6111}
6112
6113
6114/**
6115 * Checks VM-exit controls fields as part of VM-entry.
6116 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6117 *
6118 * @returns VBox status code.
6119 * @param pVCpu The cross context virtual CPU structure.
6120 * @param pszInstr The VMX instruction name (for logging purposes).
6121 */
6122IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6123{
6124 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6125 const char * const pszFailure = "VMFail";
6126
6127 /* VM-exit controls. */
6128 VMXCTLSMSR ExitCtls;
6129 ExitCtls.u = CPUMGetGuestIa32VmxExitCtls(pVCpu);
6130 if (~pVmcs->u32ExitCtls & ExitCtls.n.disallowed0)
6131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6132
6133 if (pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1)
6134 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6135
6136 /* Save preemption timer without activating it. */
6137 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6138 && (pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6140
6141 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6142 if (pVmcs->u32ExitMsrStoreCount)
6143 {
6144 if ( (pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6145 || (pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6146 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6148 }
6149
6150 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6151 if (pVmcs->u32ExitMsrLoadCount)
6152 {
6153 if ( (pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6154 || (pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6155 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6157 }
6158
6159 NOREF(pszInstr);
6160 NOREF(pszFailure);
6161 return VINF_SUCCESS;
6162}
6163
6164
6165/**
6166 * Checks VM-execution controls fields as part of VM-entry.
6167 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6168 *
6169 * @returns VBox status code.
6170 * @param pVCpu The cross context virtual CPU structure.
6171 * @param pszInstr The VMX instruction name (for logging purposes).
6172 *
6173 * @remarks This may update secondary-processor based VM-execution control fields
6174 * in the current VMCS if necessary.
6175 */
6176IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6177{
6178 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6179 const char * const pszFailure = "VMFail";
6180
6181 /* Pin-based VM-execution controls. */
6182 {
6183 VMXCTLSMSR PinCtls;
6184 PinCtls.u = CPUMGetGuestIa32VmxPinbasedCtls(pVCpu);
6185 if (~pVmcs->u32PinCtls & PinCtls.n.disallowed0)
6186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6187
6188 if (pVmcs->u32PinCtls & ~PinCtls.n.allowed1)
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6190 }
6191
6192 /* Processor-based VM-execution controls. */
6193 {
6194 VMXCTLSMSR ProcCtls;
6195 ProcCtls.u = CPUMGetGuestIa32VmxProcbasedCtls(pVCpu);
6196 if (~pVmcs->u32ProcCtls & ProcCtls.n.disallowed0)
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6198
6199 if (pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1)
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6201 }
6202
6203 /* Secondary processor-based VM-execution controls. */
6204 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6205 {
6206 VMXCTLSMSR ProcCtls2;
6207 ProcCtls2.u = CPUMGetGuestIa32VmxProcbasedCtls2(pVCpu);
6208 if (~pVmcs->u32ProcCtls2 & ProcCtls2.n.disallowed0)
6209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6210
6211 if (pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1)
6212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6213 }
6214 else
6215 Assert(!pVmcs->u32ProcCtls2);
6216
6217 /* CR3-target count. */
6218 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6222
6223 /* I/O bitmaps physical addresses. */
6224 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6225 {
6226 if ( (pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6227 || (pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6228 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6230
6231 if ( (pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6232 || (pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6233 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6235 }
6236
6237 /* MSR bitmap physical address. */
6238 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6239 {
6240 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6241 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6242 || (GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6243 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6245
6246 /* Read the MSR bitmap. */
6247 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6248 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6249 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6250 if (RT_FAILURE(rc))
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6252 }
6253
6254 /* TPR shadow related controls. */
6255 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6256 {
6257 /* Virtual-APIC page physical address. */
6258 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6259 if ( (GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6260 || (GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6261 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6263
6264 /* Read the Virtual-APIC page. */
6265 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6266 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6267 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6268 if (RT_FAILURE(rc))
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6270
6271 /* TPR threshold without virtual-interrupt delivery. */
6272 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6273 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6275
6276 /* TPR threshold and VTPR. */
6277 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6278 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6279 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6280 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6281 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6283 }
6284 else
6285 {
6286 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6287 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6288 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6289 { /* likely */ }
6290 else
6291 {
6292 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6294 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6296 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6298 }
6299 }
6300
6301 /* NMI exiting and virtual-NMIs. */
6302 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6303 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6305
6306 /* Virtual-NMIs and NMI-window exiting. */
6307 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6308 && (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6310
6311 /* Virtualize APIC accesses. */
6312 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6313 {
6314 /* APIC-access physical address. */
6315 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6316 if ( (GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6317 || (GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6318 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6320
6321 /*
6322 * Disallow APIC-access page and virtual-APIC page from being the same address.
6323 * Note! This is not an Intel requirement, but one imposed by our implementation.
6324 */
6325 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6326 * redirecting accesses between the APIC-access page and the virtual-APIC
6327 * page. If any nested hypervisor requires this, we can implement it later. */
6328 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6329 {
6330 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6331 if (GCPhysVirtApic == GCPhysApicAccess)
6332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6333 }
6334
6335 /* Register the handler for the APIC-access page. */
6336 int rc = CPUMVmxApicAccessPageRegister(pVCpu, GCPhysApicAccess);
6337 if (RT_FAILURE(rc))
6338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6339 }
6340
6341 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6342 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6343 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6345
6346 /* Virtual-interrupt delivery requires external interrupt exiting. */
6347 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6348 && !(pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6350
6351 /* VPID. */
6352 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6353 || pVmcs->u16Vpid != 0)
6354 { /* likely */ }
6355 else
6356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6357
6358 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6359 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6360 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6361 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6362 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6363 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6364 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6365
6366 /* VMCS shadowing. */
6367 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6368 {
6369 /* VMREAD-bitmap physical address. */
6370 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6371 if ( ( GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6372 || ( GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6373 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6375
6376 /* VMWRITE-bitmap physical address. */
6377 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6378 if ( ( GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6379 || ( GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6380 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6382
6383 /* Read the VMREAD-bitmap. */
6384 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6385 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6386 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6387 if (RT_FAILURE(rc))
6388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6389
6390 /* Read the VMWRITE-bitmap. */
6391 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6392 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6393 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6394 if (RT_FAILURE(rc))
6395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6396 }
6397
6398 NOREF(pszInstr);
6399 NOREF(pszFailure);
6400 return VINF_SUCCESS;
6401}
6402
6403
6404/**
6405 * Loads the guest control registers, debug register and some MSRs as part of
6406 * VM-entry.
6407 *
6408 * @param pVCpu The cross context virtual CPU structure.
6409 */
6410IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6411{
6412 /*
6413 * Load guest control registers, debug registers and MSRs.
6414 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6415 */
6416 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6417 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6418 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6419 CPUMSetGuestCR0(pVCpu, uGstCr0);
6420 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6421 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6422
6423 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6424 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6425
6426 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6427 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6428 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6429
6430 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6431 {
6432 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6433
6434 /* EFER MSR. */
6435 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6436 {
6437 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6438 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6439 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6440 if (fGstInLongMode)
6441 {
6442 /* If the nested-guest is in long mode, LMA and LME are both set. */
6443 Assert(fGstPaging);
6444 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6445 }
6446 else
6447 {
6448 /*
6449 * If the nested-guest is outside long mode:
6450 * - With paging: LMA is cleared, LME is cleared.
6451 * - Without paging: LMA is cleared, LME is left unmodified.
6452 */
6453 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6454 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6455 }
6456 }
6457 /* else: see below. */
6458 }
6459
6460 /* PAT MSR. */
6461 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6462 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6463
6464 /* EFER MSR. */
6465 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6466 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6467
6468 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6469 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6470
6471 /* We don't support IA32_BNDCFGS MSR yet. */
6472 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6473
6474 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6475}
6476
6477
6478/**
6479 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6480 *
6481 * @param pVCpu The cross context virtual CPU structure.
6482 */
6483IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6484{
6485 /*
6486 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6487 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6488 */
6489 /* CS, SS, ES, DS, FS, GS. */
6490 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6491 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6492 {
6493 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6494 CPUMSELREG VmcsSelReg;
6495 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6496 AssertRC(rc); NOREF(rc);
6497 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6498 {
6499 pGstSelReg->Sel = VmcsSelReg.Sel;
6500 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6501 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6502 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6503 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6504 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6505 }
6506 else
6507 {
6508 pGstSelReg->Sel = VmcsSelReg.Sel;
6509 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6510 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6511 switch (iSegReg)
6512 {
6513 case X86_SREG_CS:
6514 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6515 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6516 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6517 break;
6518
6519 case X86_SREG_SS:
6520 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6521 pGstSelReg->u32Limit = 0;
6522 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6523 break;
6524
6525 case X86_SREG_ES:
6526 case X86_SREG_DS:
6527 pGstSelReg->u64Base = 0;
6528 pGstSelReg->u32Limit = 0;
6529 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6530 break;
6531
6532 case X86_SREG_FS:
6533 case X86_SREG_GS:
6534 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6535 pGstSelReg->u32Limit = 0;
6536 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6537 break;
6538 }
6539 Assert(pGstSelReg->Attr.n.u1Unusable);
6540 }
6541 }
6542
6543 /* LDTR. */
6544 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6545 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6546 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6547 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6548 {
6549 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6550 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6551 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6552 }
6553 else
6554 {
6555 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6556 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6557 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6558 }
6559
6560 /* TR. */
6561 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6562 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6563 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6564 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6565 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6566 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6567 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6568
6569 /* GDTR. */
6570 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6571 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6572
6573 /* IDTR. */
6574 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6575 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6576}
6577
6578
6579/**
6580 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6581 *
6582 * @returns VBox status code.
6583 * @param pVCpu The cross context virtual CPU structure.
6584 * @param pszInstr The VMX instruction name (for logging purposes).
6585 */
6586IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6587{
6588 /*
6589 * Load guest MSRs.
6590 * See Intel spec. 26.4 "Loading MSRs".
6591 */
6592 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6593 const char *const pszFailure = "VM-exit";
6594
6595 /*
6596 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6597 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6598 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6599 */
6600 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6601 if (!cMsrs)
6602 return VINF_SUCCESS;
6603
6604 /*
6605 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6606 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6607 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6608 */
6609 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6610 if (fIsMsrCountValid)
6611 { /* likely */ }
6612 else
6613 {
6614 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6616 }
6617
6618 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
6619 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
6620 GCPhysAutoMsrArea, VMX_V_AUTOMSR_AREA_SIZE);
6621 if (RT_SUCCESS(rc))
6622 {
6623 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
6624 Assert(pMsr);
6625 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6626 {
6627 if ( !pMsr->u32Reserved
6628 && pMsr->u32Msr != MSR_K8_FS_BASE
6629 && pMsr->u32Msr != MSR_K8_GS_BASE
6630 && pMsr->u32Msr != MSR_K6_EFER
6631 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6632 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6633 {
6634 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6635 if (rcStrict == VINF_SUCCESS)
6636 continue;
6637
6638 /*
6639 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6640 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6641 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
6642 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6643 * MSR in ring-0 if possible, or come up with a better, generic solution.
6644 */
6645 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6646 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6647 ? kVmxVDiag_Vmentry_MsrLoadRing3
6648 : kVmxVDiag_Vmentry_MsrLoad;
6649 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6650 }
6651 else
6652 {
6653 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6655 }
6656 }
6657 }
6658 else
6659 {
6660 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
6661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6662 }
6663
6664 NOREF(pszInstr);
6665 NOREF(pszFailure);
6666 return VINF_SUCCESS;
6667}
6668
6669
6670/**
6671 * Loads the guest-state non-register state as part of VM-entry.
6672 *
6673 * @returns VBox status code.
6674 * @param pVCpu The cross context virtual CPU structure.
6675 *
6676 * @remarks This must be called only after loading the nested-guest register state
6677 * (especially nested-guest RIP).
6678 */
6679IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6680{
6681 /*
6682 * Load guest non-register state.
6683 * See Intel spec. 26.6 "Special Features of VM Entry"
6684 */
6685 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6686 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
6687 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
6688 {
6689 /** @todo NSTVMX: Pending debug exceptions. */
6690 Assert(!(pVmcs->u64GuestPendingDbgXcpt.u));
6691
6692 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6693 {
6694 /** @todo NSTVMX: Virtual-NMIs doesn't affect NMI blocking in the normal sense.
6695 * We probably need a different force flag for virtual-NMI
6696 * pending/blocking. */
6697 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI));
6698 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6699 }
6700 else
6701 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
6702
6703 if (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6704 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
6705 else
6706 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6707
6708 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6709 }
6710
6711 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6712 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6713
6714 /* VPID is irrelevant. We don't support VPID yet. */
6715
6716 /* Clear address-range monitoring. */
6717 EMMonitorWaitClear(pVCpu);
6718}
6719
6720
6721/**
6722 * Loads the guest-state as part of VM-entry.
6723 *
6724 * @returns VBox status code.
6725 * @param pVCpu The cross context virtual CPU structure.
6726 * @param pszInstr The VMX instruction name (for logging purposes).
6727 *
6728 * @remarks This must be done after all the necessary steps prior to loading of
6729 * guest-state (e.g. checking various VMCS state).
6730 */
6731IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6732{
6733 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6734 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6735
6736 /*
6737 * Load guest RIP, RSP and RFLAGS.
6738 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6739 */
6740 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6741 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6742 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6743 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6744
6745 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6746 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6747 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6748
6749 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6750
6751 NOREF(pszInstr);
6752 return VINF_SUCCESS;
6753}
6754
6755
6756/**
6757 * Set up the VMX-preemption timer.
6758 *
6759 * @param pVCpu The cross context virtual CPU structure.
6760 * @param pszInstr The VMX instruction name (for logging purposes).
6761 */
6762IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
6763{
6764 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6765 Assert(pVmcs);
6766 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6767 {
6768 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
6769 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
6770 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
6771
6772 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
6773 }
6774 else
6775 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
6776
6777 NOREF(pszInstr);
6778}
6779
6780
6781/**
6782 * Performs event injection (if any) as part of VM-entry.
6783 *
6784 * @param pVCpu The cross context virtual CPU structure.
6785 * @param pszInstr The VMX instruction name (for logging purposes).
6786 */
6787IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
6788{
6789 /*
6790 * Inject events.
6791 * See Intel spec. 26.5 "Event Injection".
6792 */
6793 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6794 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
6795 if (VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
6796 {
6797 /*
6798 * The event that is going to be made pending for injection is not subject to VMX intercepts,
6799 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
6800 * of the current event -are- subject to intercepts, hence this flag will be flipped during
6801 * the actually delivery of this event.
6802 */
6803 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = false;
6804
6805 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
6806 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
6807 {
6808 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
6809 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6810 return VINF_SUCCESS;
6811 }
6812
6813 int rc = HMVmxEntryIntInfoInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
6814 pVCpu->cpum.GstCtx.cr2);
6815 AssertRCReturn(rc, rc);
6816 }
6817
6818 NOREF(pszInstr);
6819 return VINF_SUCCESS;
6820}
6821
6822
6823/**
6824 * VMLAUNCH/VMRESUME instruction execution worker.
6825 *
6826 * @returns Strict VBox status code.
6827 * @param pVCpu The cross context virtual CPU structure.
6828 * @param cbInstr The instruction length in bytes.
6829 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
6830 * VMXINSTRID_VMRESUME).
6831 * @param pExitInfo Pointer to the VM-exit instruction information struct.
6832 * Optional, can be NULL.
6833 *
6834 * @remarks Common VMX instruction checks are already expected to by the caller,
6835 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
6836 */
6837IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId, PCVMXVEXITINFO pExitInfo)
6838{
6839 Assert( uInstrId == VMXINSTRID_VMLAUNCH
6840 || uInstrId == VMXINSTRID_VMRESUME);
6841 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
6842
6843 /* Nested-guest intercept. */
6844 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6845 {
6846 if (pExitInfo)
6847 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
6848 uint32_t const uExitReason = uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH;
6849 return iemVmxVmexitInstrNeedsInfo(pVCpu, uExitReason, uInstrId, cbInstr);
6850 }
6851
6852 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
6853
6854 /* CPL. */
6855 if (pVCpu->iem.s.uCpl > 0)
6856 {
6857 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
6858 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
6859 return iemRaiseGeneralProtectionFault0(pVCpu);
6860 }
6861
6862 /* Current VMCS valid. */
6863 if (!IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
6864 {
6865 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
6866 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
6867 iemVmxVmFailInvalid(pVCpu);
6868 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6869 return VINF_SUCCESS;
6870 }
6871
6872 /** @todo Distinguish block-by-MOV-SS from block-by-STI. Currently we
6873 * use block-by-STI here which is not quite correct. */
6874 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
6875 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
6876 {
6877 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
6878 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
6879 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
6880 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6881 return VINF_SUCCESS;
6882 }
6883
6884 if (uInstrId == VMXINSTRID_VMLAUNCH)
6885 {
6886 /* VMLAUNCH with non-clear VMCS. */
6887 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
6888 { /* likely */ }
6889 else
6890 {
6891 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
6892 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
6893 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
6894 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6895 return VINF_SUCCESS;
6896 }
6897 }
6898 else
6899 {
6900 /* VMRESUME with non-launched VMCS. */
6901 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
6902 { /* likely */ }
6903 else
6904 {
6905 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
6906 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
6907 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
6908 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6909 return VINF_SUCCESS;
6910 }
6911 }
6912
6913 /*
6914 * Load the current VMCS.
6915 */
6916 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
6917 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
6918 IEM_VMX_GET_CURRENT_VMCS(pVCpu), VMX_V_VMCS_SIZE);
6919 if (RT_FAILURE(rc))
6920 {
6921 Log(("%s: Failed to read VMCS at %#RGp, rc=%Rrc\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu), rc));
6922 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrReadPhys;
6923 return rc;
6924 }
6925
6926 /*
6927 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
6928 * while entering VMX non-root mode. We do some of this while checking VM-execution
6929 * controls. The guest hypervisor should not make assumptions and cannot expect
6930 * predictable behavior if changes to these structures are made in guest memory while
6931 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
6932 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
6933 *
6934 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6935 */
6936 rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
6937 if (RT_SUCCESS(rc))
6938 {
6939 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
6940 if (RT_SUCCESS(rc))
6941 {
6942 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
6943 if (RT_SUCCESS(rc))
6944 {
6945 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
6946 if (RT_SUCCESS(rc))
6947 {
6948 /* Save the guest force-flags as VM-exits can occur from this point on. */
6949 iemVmxVmentrySaveForceFlags(pVCpu);
6950
6951 /* Initialize the VM-exit qualification field as it MBZ for VM-exits where it isn't specified. */
6952 iemVmxVmcsSetExitQual(pVCpu, 0);
6953
6954 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
6955 if (RT_SUCCESS(rc))
6956 {
6957 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
6958 if (RT_SUCCESS(rc))
6959 {
6960 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
6961 if (RT_SUCCESS(rc))
6962 {
6963 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
6964
6965 /* VMLAUNCH instruction must update the VMCS launch state. */
6966 if (uInstrId == VMXINSTRID_VMLAUNCH)
6967 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
6968
6969 /* Perform the VMX transition (PGM updates). */
6970 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
6971 if (rcStrict == VINF_SUCCESS)
6972 { /* likely */ }
6973 else if (RT_SUCCESS(rcStrict))
6974 {
6975 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
6976 VBOXSTRICTRC_VAL(rcStrict)));
6977 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6978 }
6979 else
6980 {
6981 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
6982 return rcStrict;
6983 }
6984
6985 /* We've now entered nested-guest execution. */
6986 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
6987
6988 /*
6989 * The priority of potential VM-exits during VM-entry is important.
6990 * The priorities of VM-exits and events are listed from highest
6991 * to lowest as follows:
6992 *
6993 * 1. Event injection.
6994 * 2. TPR below threshold / APIC-write.
6995 * 3. SMI.
6996 * 4. INIT.
6997 * 5. MTF exit.
6998 * 6. Pending debug exceptions.
6999 * 7. Debug-trap exceptions.
7000 * 8. VMX-preemption timer.
7001 * 9. NMI-window exit.
7002 * 10. NMI injection.
7003 * 11. Interrupt-window exit.
7004 * 12. Interrupt injection.
7005 */
7006
7007 /* Setup the VMX-preemption timer. */
7008 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7009
7010 /* Now that we've switched page tables, we can inject events if any. */
7011 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7012
7013 return VINF_SUCCESS;
7014 }
7015 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7016 }
7017 }
7018 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7019 }
7020
7021 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7022 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7023 return VINF_SUCCESS;
7024 }
7025 }
7026 }
7027
7028 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7029 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7030 return VINF_SUCCESS;
7031}
7032
7033
7034/**
7035 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7036 * (causes a VM-exit) or not.
7037 *
7038 * @returns @c true if the instruction is intercepted, @c false otherwise.
7039 * @param pVCpu The cross context virtual CPU structure.
7040 * @param uExitReason The VM-exit exit reason (VMX_EXIT_RDMSR or
7041 * VMX_EXIT_WRMSR).
7042 * @param idMsr The MSR.
7043 */
7044IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7045{
7046 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7047 Assert( uExitReason == VMX_EXIT_RDMSR
7048 || uExitReason == VMX_EXIT_WRMSR);
7049
7050 /* Consult the MSR bitmap if the feature is supported. */
7051 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7052 Assert(pVmcs);
7053 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7054 {
7055 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7056 if (uExitReason == VMX_EXIT_RDMSR)
7057 {
7058 VMXMSREXITREAD enmRead;
7059 int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7060 NULL /* penmWrite */);
7061 AssertRC(rc);
7062 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7063 return true;
7064 }
7065 else
7066 {
7067 VMXMSREXITWRITE enmWrite;
7068 int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7069 &enmWrite);
7070 AssertRC(rc);
7071 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7072 return true;
7073 }
7074 return false;
7075 }
7076
7077 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7078 return true;
7079}
7080
7081
7082/**
7083 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7084 * intercepted (causes a VM-exit) or not.
7085 *
7086 * @returns @c true if the instruction is intercepted, @c false otherwise.
7087 * @param pVCpu The cross context virtual CPU structure.
7088 * @param u64FieldEnc The VMCS field encoding.
7089 * @param uExitReason The VM-exit exit reason (VMX_EXIT_VMREAD or
7090 * VMX_EXIT_VMREAD).
7091 */
7092IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7093{
7094 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7095 Assert( uExitReason == VMX_EXIT_VMREAD
7096 || uExitReason == VMX_EXIT_VMWRITE);
7097
7098 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7099 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7100 return true;
7101
7102 /*
7103 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7104 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7105 */
7106 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7107 return true;
7108
7109 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7110 uint32_t u32FieldEnc = RT_LO_U32(u64FieldEnc);
7111 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7112 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7113 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7114 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7115 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7116 pbBitmap += (u32FieldEnc >> 3);
7117 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7118 return true;
7119
7120 return false;
7121}
7122
7123
7124/**
7125 * VMREAD common (memory/register) instruction execution worker
7126 *
7127 * @returns Strict VBox status code.
7128 * @param pVCpu The cross context virtual CPU structure.
7129 * @param cbInstr The instruction length in bytes.
7130 * @param pu64Dst Where to write the VMCS value (only updated when
7131 * VINF_SUCCESS is returned).
7132 * @param u64FieldEnc The VMCS field encoding.
7133 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7134 * be NULL.
7135 */
7136IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7137 PCVMXVEXITINFO pExitInfo)
7138{
7139 /* Nested-guest intercept. */
7140 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7141 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7142 {
7143 if (pExitInfo)
7144 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7145 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7146 }
7147
7148 /* CPL. */
7149 if (pVCpu->iem.s.uCpl > 0)
7150 {
7151 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7152 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7153 return iemRaiseGeneralProtectionFault0(pVCpu);
7154 }
7155
7156 /* VMCS pointer in root mode. */
7157 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7158 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7159 {
7160 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7161 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7162 iemVmxVmFailInvalid(pVCpu);
7163 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7164 return VINF_SUCCESS;
7165 }
7166
7167 /* VMCS-link pointer in non-root mode. */
7168 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7169 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7170 {
7171 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7172 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7173 iemVmxVmFailInvalid(pVCpu);
7174 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7175 return VINF_SUCCESS;
7176 }
7177
7178 /* Supported VMCS field. */
7179 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7180 {
7181 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7182 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7183 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7184 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7185 return VINF_SUCCESS;
7186 }
7187
7188 /*
7189 * Setup reading from the current or shadow VMCS.
7190 */
7191 uint8_t *pbVmcs;
7192 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7193 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7194 else
7195 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7196 Assert(pbVmcs);
7197
7198 VMXVMCSFIELDENC FieldEnc;
7199 FieldEnc.u = RT_LO_U32(u64FieldEnc);
7200 uint8_t const uWidth = FieldEnc.n.u2Width;
7201 uint8_t const uType = FieldEnc.n.u2Type;
7202 uint8_t const uWidthType = (uWidth << 2) | uType;
7203 uint8_t const uIndex = FieldEnc.n.u8Index;
7204 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7205 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7206
7207 /*
7208 * Read the VMCS component based on the field's effective width.
7209 *
7210 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7211 * indicates high bits (little endian).
7212 *
7213 * Note! The caller is responsible to trim the result and update registers
7214 * or memory locations are required. Here we just zero-extend to the largest
7215 * type (i.e. 64-bits).
7216 */
7217 uint8_t *pbField = pbVmcs + offField;
7218 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7219 switch (uEffWidth)
7220 {
7221 case VMX_VMCS_ENC_WIDTH_64BIT:
7222 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7223 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7224 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7225 }
7226 return VINF_SUCCESS;
7227}
7228
7229
7230/**
7231 * VMREAD (64-bit register) instruction execution worker.
7232 *
7233 * @returns Strict VBox status code.
7234 * @param pVCpu The cross context virtual CPU structure.
7235 * @param cbInstr The instruction length in bytes.
7236 * @param pu64Dst Where to store the VMCS field's value.
7237 * @param u64FieldEnc The VMCS field encoding.
7238 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7239 * be NULL.
7240 */
7241IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7242 PCVMXVEXITINFO pExitInfo)
7243{
7244 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7245 if (rcStrict == VINF_SUCCESS)
7246 {
7247 iemVmxVmreadSuccess(pVCpu, cbInstr);
7248 return VINF_SUCCESS;
7249 }
7250
7251 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7252 return rcStrict;
7253}
7254
7255
7256/**
7257 * VMREAD (32-bit register) instruction execution worker.
7258 *
7259 * @returns Strict VBox status code.
7260 * @param pVCpu The cross context virtual CPU structure.
7261 * @param cbInstr The instruction length in bytes.
7262 * @param pu32Dst Where to store the VMCS field's value.
7263 * @param u32FieldEnc The VMCS field encoding.
7264 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7265 * be NULL.
7266 */
7267IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7268 PCVMXVEXITINFO pExitInfo)
7269{
7270 uint64_t u64Dst;
7271 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7272 if (rcStrict == VINF_SUCCESS)
7273 {
7274 *pu32Dst = u64Dst;
7275 iemVmxVmreadSuccess(pVCpu, cbInstr);
7276 return VINF_SUCCESS;
7277 }
7278
7279 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7280 return rcStrict;
7281}
7282
7283
7284/**
7285 * VMREAD (memory) instruction execution worker.
7286 *
7287 * @returns Strict VBox status code.
7288 * @param pVCpu The cross context virtual CPU structure.
7289 * @param cbInstr The instruction length in bytes.
7290 * @param iEffSeg The effective segment register to use with @a u64Val.
7291 * Pass UINT8_MAX if it is a register access.
7292 * @param enmEffAddrMode The effective addressing mode (only used with memory
7293 * operand).
7294 * @param GCPtrDst The guest linear address to store the VMCS field's
7295 * value.
7296 * @param u64FieldEnc The VMCS field encoding.
7297 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7298 * be NULL.
7299 */
7300IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7301 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7302{
7303 uint64_t u64Dst;
7304 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7305 if (rcStrict == VINF_SUCCESS)
7306 {
7307 /*
7308 * Write the VMCS field's value to the location specified in guest-memory.
7309 *
7310 * The pointer size depends on the address size (address-size prefix allowed).
7311 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7312 */
7313 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7314 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7315 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7316
7317 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7318 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7319 else
7320 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7321 if (rcStrict == VINF_SUCCESS)
7322 {
7323 iemVmxVmreadSuccess(pVCpu, cbInstr);
7324 return VINF_SUCCESS;
7325 }
7326
7327 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7329 return rcStrict;
7330 }
7331
7332 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7333 return rcStrict;
7334}
7335
7336
7337/**
7338 * VMWRITE instruction execution worker.
7339 *
7340 * @returns Strict VBox status code.
7341 * @param pVCpu The cross context virtual CPU structure.
7342 * @param cbInstr The instruction length in bytes.
7343 * @param iEffSeg The effective segment register to use with @a u64Val.
7344 * Pass UINT8_MAX if it is a register access.
7345 * @param enmEffAddrMode The effective addressing mode (only used with memory
7346 * operand).
7347 * @param u64Val The value to write (or guest linear address to the
7348 * value), @a iEffSeg will indicate if it's a memory
7349 * operand.
7350 * @param u64FieldEnc The VMCS field encoding.
7351 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7352 * be NULL.
7353 */
7354IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7355 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7356{
7357 /* Nested-guest intercept. */
7358 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7359 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7360 {
7361 if (pExitInfo)
7362 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7363 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7364 }
7365
7366 /* CPL. */
7367 if (pVCpu->iem.s.uCpl > 0)
7368 {
7369 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7370 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7371 return iemRaiseGeneralProtectionFault0(pVCpu);
7372 }
7373
7374 /* VMCS pointer in root mode. */
7375 if ( IEM_VMX_IS_ROOT_MODE(pVCpu)
7376 && !IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7377 {
7378 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7379 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7380 iemVmxVmFailInvalid(pVCpu);
7381 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7382 return VINF_SUCCESS;
7383 }
7384
7385 /* VMCS-link pointer in non-root mode. */
7386 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7387 && !IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7388 {
7389 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7390 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7391 iemVmxVmFailInvalid(pVCpu);
7392 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7393 return VINF_SUCCESS;
7394 }
7395
7396 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7397 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7398 if (!fIsRegOperand)
7399 {
7400 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7401 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7402 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
7403
7404 /* Read the value from the specified guest memory location. */
7405 VBOXSTRICTRC rcStrict;
7406 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7407 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7408 else
7409 {
7410 uint32_t u32Val;
7411 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7412 u64Val = u32Val;
7413 }
7414 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7415 {
7416 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7417 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7418 return rcStrict;
7419 }
7420 }
7421 else
7422 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7423
7424 /* Supported VMCS field. */
7425 if (!iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7426 {
7427 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7428 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7429 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7430 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7431 return VINF_SUCCESS;
7432 }
7433
7434 /* Read-only VMCS field. */
7435 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
7436 if ( fIsFieldReadOnly
7437 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7438 {
7439 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
7440 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7441 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7442 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7443 return VINF_SUCCESS;
7444 }
7445
7446 /*
7447 * Setup writing to the current or shadow VMCS.
7448 */
7449 uint8_t *pbVmcs;
7450 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7451 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7452 else
7453 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7454 Assert(pbVmcs);
7455
7456 VMXVMCSFIELDENC FieldEnc;
7457 FieldEnc.u = RT_LO_U32(u64FieldEnc);
7458 uint8_t const uWidth = FieldEnc.n.u2Width;
7459 uint8_t const uType = FieldEnc.n.u2Type;
7460 uint8_t const uWidthType = (uWidth << 2) | uType;
7461 uint8_t const uIndex = FieldEnc.n.u8Index;
7462 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7463 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7464
7465 /*
7466 * Write the VMCS component based on the field's effective width.
7467 *
7468 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7469 * indicates high bits (little endian).
7470 */
7471 uint8_t *pbField = pbVmcs + offField;
7472 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7473 switch (uEffWidth)
7474 {
7475 case VMX_VMCS_ENC_WIDTH_64BIT:
7476 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7477 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7478 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7479 }
7480
7481 iemVmxVmSucceed(pVCpu);
7482 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7483 return VINF_SUCCESS;
7484}
7485
7486
7487/**
7488 * VMCLEAR instruction execution worker.
7489 *
7490 * @returns Strict VBox status code.
7491 * @param pVCpu The cross context virtual CPU structure.
7492 * @param cbInstr The instruction length in bytes.
7493 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7494 * @param GCPtrVmcs The linear address of the VMCS pointer.
7495 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7496 * be NULL.
7497 *
7498 * @remarks Common VMX instruction checks are already expected to by the caller,
7499 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7500 */
7501IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7502 PCVMXVEXITINFO pExitInfo)
7503{
7504 /* Nested-guest intercept. */
7505 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7506 {
7507 if (pExitInfo)
7508 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7509 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7510 }
7511
7512 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7513
7514 /* CPL. */
7515 if (pVCpu->iem.s.uCpl > 0)
7516 {
7517 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7518 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7519 return iemRaiseGeneralProtectionFault0(pVCpu);
7520 }
7521
7522 /* Get the VMCS pointer from the location specified by the source memory operand. */
7523 RTGCPHYS GCPhysVmcs;
7524 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7525 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7526 {
7527 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7528 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7529 return rcStrict;
7530 }
7531
7532 /* VMCS pointer alignment. */
7533 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
7534 {
7535 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7536 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7537 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7538 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7539 return VINF_SUCCESS;
7540 }
7541
7542 /* VMCS physical-address width limits. */
7543 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7544 {
7545 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7547 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7548 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7549 return VINF_SUCCESS;
7550 }
7551
7552 /* VMCS is not the VMXON region. */
7553 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7554 {
7555 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7557 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7558 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7559 return VINF_SUCCESS;
7560 }
7561
7562 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7563 restriction imposed by our implementation. */
7564 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7565 {
7566 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7567 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7568 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7569 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7570 return VINF_SUCCESS;
7571 }
7572
7573 /*
7574 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7575 *
7576 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7577 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7578 * to 'clear'.
7579 */
7580 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
7581 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7582 {
7583 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
7584 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7585 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
7586 iemVmxCommitCurrentVmcsToMemory(pVCpu);
7587 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7588 }
7589 else
7590 {
7591 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPtrVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7592 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
7593 }
7594
7595 iemVmxVmSucceed(pVCpu);
7596 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7597 return rcStrict;
7598}
7599
7600
7601/**
7602 * VMPTRST instruction execution worker.
7603 *
7604 * @returns Strict VBox status code.
7605 * @param pVCpu The cross context virtual CPU structure.
7606 * @param cbInstr The instruction length in bytes.
7607 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7608 * @param GCPtrVmcs The linear address of where to store the current VMCS
7609 * pointer.
7610 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7611 * be NULL.
7612 *
7613 * @remarks Common VMX instruction checks are already expected to by the caller,
7614 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7615 */
7616IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7617 PCVMXVEXITINFO pExitInfo)
7618{
7619 /* Nested-guest intercept. */
7620 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7621 {
7622 if (pExitInfo)
7623 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7624 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
7625 }
7626
7627 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7628
7629 /* CPL. */
7630 if (pVCpu->iem.s.uCpl > 0)
7631 {
7632 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
7634 return iemRaiseGeneralProtectionFault0(pVCpu);
7635 }
7636
7637 /* Set the VMCS pointer to the location specified by the destination memory operand. */
7638 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
7639 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
7640 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7641 {
7642 iemVmxVmSucceed(pVCpu);
7643 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7644 return rcStrict;
7645 }
7646
7647 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7648 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
7649 return rcStrict;
7650}
7651
7652
7653/**
7654 * VMPTRLD instruction execution worker.
7655 *
7656 * @returns Strict VBox status code.
7657 * @param pVCpu The cross context virtual CPU structure.
7658 * @param cbInstr The instruction length in bytes.
7659 * @param GCPtrVmcs The linear address of the current VMCS pointer.
7660 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7661 * be NULL.
7662 *
7663 * @remarks Common VMX instruction checks are already expected to by the caller,
7664 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7665 */
7666IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7667 PCVMXVEXITINFO pExitInfo)
7668{
7669 /* Nested-guest intercept. */
7670 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7671 {
7672 if (pExitInfo)
7673 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7674 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
7675 }
7676
7677 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7678
7679 /* CPL. */
7680 if (pVCpu->iem.s.uCpl > 0)
7681 {
7682 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
7684 return iemRaiseGeneralProtectionFault0(pVCpu);
7685 }
7686
7687 /* Get the VMCS pointer from the location specified by the source memory operand. */
7688 RTGCPHYS GCPhysVmcs;
7689 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7690 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7691 {
7692 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7693 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
7694 return rcStrict;
7695 }
7696
7697 /* VMCS pointer alignment. */
7698 if (GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK)
7699 {
7700 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
7701 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
7702 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
7703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7704 return VINF_SUCCESS;
7705 }
7706
7707 /* VMCS physical-address width limits. */
7708 if (GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7709 {
7710 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7711 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
7712 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
7713 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7714 return VINF_SUCCESS;
7715 }
7716
7717 /* VMCS is not the VMXON region. */
7718 if (GCPhysVmcs == pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7719 {
7720 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7721 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
7722 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
7723 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7724 return VINF_SUCCESS;
7725 }
7726
7727 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7728 restriction imposed by our implementation. */
7729 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7730 {
7731 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
7732 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
7733 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
7734 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7735 return VINF_SUCCESS;
7736 }
7737
7738 /* Read the VMCS revision ID from the VMCS. */
7739 VMXVMCSREVID VmcsRevId;
7740 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
7741 if (RT_FAILURE(rc))
7742 {
7743 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
7744 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
7745 return rc;
7746 }
7747
7748 /* Verify the VMCS revision specified by the guest matches what we reported to the guest,
7749 also check VMCS shadowing feature. */
7750 if ( VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID
7751 || ( VmcsRevId.n.fIsShadowVmcs
7752 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
7753 {
7754 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
7755 {
7756 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFail()\n", VMX_V_VMCS_REVISION_ID,
7757 VmcsRevId.n.u31RevisionId));
7758 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
7759 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
7760 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7761 return VINF_SUCCESS;
7762 }
7763
7764 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
7765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
7766 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
7767 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7768 return VINF_SUCCESS;
7769 }
7770
7771 /*
7772 * We only maintain only the current VMCS in our virtual CPU context (CPUMCTX). Therefore,
7773 * VMPTRLD shall always flush any existing current VMCS back to guest memory before loading
7774 * a new VMCS as current.
7775 */
7776 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
7777 {
7778 iemVmxCommitCurrentVmcsToMemory(pVCpu);
7779 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
7780 }
7781
7782 iemVmxVmSucceed(pVCpu);
7783 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7784 return VINF_SUCCESS;
7785}
7786
7787
7788/**
7789 * VMXON instruction execution worker.
7790 *
7791 * @returns Strict VBox status code.
7792 * @param pVCpu The cross context virtual CPU structure.
7793 * @param cbInstr The instruction length in bytes.
7794 * @param iEffSeg The effective segment register to use with @a
7795 * GCPtrVmxon.
7796 * @param GCPtrVmxon The linear address of the VMXON pointer.
7797 * @param pExitInfo Pointer to the VM-exit instruction information struct.
7798 * Optional, can be NULL.
7799 *
7800 * @remarks Common VMX instruction checks are already expected to by the caller,
7801 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7802 */
7803IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
7804 PCVMXVEXITINFO pExitInfo)
7805{
7806#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7807 RT_NOREF5(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
7808 return VINF_EM_RAW_EMULATE_INSTR;
7809#else
7810 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
7811 {
7812 /* CPL. */
7813 if (pVCpu->iem.s.uCpl > 0)
7814 {
7815 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7816 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
7817 return iemRaiseGeneralProtectionFault0(pVCpu);
7818 }
7819
7820 /* A20M (A20 Masked) mode. */
7821 if (!PGMPhysIsA20Enabled(pVCpu))
7822 {
7823 Log(("vmxon: A20M mode -> #GP(0)\n"));
7824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
7825 return iemRaiseGeneralProtectionFault0(pVCpu);
7826 }
7827
7828 /* CR0. */
7829 {
7830 /* CR0 MB1 bits. */
7831 uint64_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
7832 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) != uCr0Fixed0)
7833 {
7834 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
7835 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
7836 return iemRaiseGeneralProtectionFault0(pVCpu);
7837 }
7838
7839 /* CR0 MBZ bits. */
7840 uint64_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
7841 if (pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1)
7842 {
7843 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
7844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
7845 return iemRaiseGeneralProtectionFault0(pVCpu);
7846 }
7847 }
7848
7849 /* CR4. */
7850 {
7851 /* CR4 MB1 bits. */
7852 uint64_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
7853 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) != uCr4Fixed0)
7854 {
7855 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
7856 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
7857 return iemRaiseGeneralProtectionFault0(pVCpu);
7858 }
7859
7860 /* CR4 MBZ bits. */
7861 uint64_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
7862 if (pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1)
7863 {
7864 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
7865 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
7866 return iemRaiseGeneralProtectionFault0(pVCpu);
7867 }
7868 }
7869
7870 /* Feature control MSR's LOCK and VMXON bits. */
7871 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatureControl(pVCpu);
7872 if (!(uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON)))
7873 {
7874 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
7875 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
7876 return iemRaiseGeneralProtectionFault0(pVCpu);
7877 }
7878
7879 /* Get the VMXON pointer from the location specified by the source memory operand. */
7880 RTGCPHYS GCPhysVmxon;
7881 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
7882 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7883 {
7884 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
7885 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
7886 return rcStrict;
7887 }
7888
7889 /* VMXON region pointer alignment. */
7890 if (GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK)
7891 {
7892 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
7893 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
7894 iemVmxVmFailInvalid(pVCpu);
7895 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7896 return VINF_SUCCESS;
7897 }
7898
7899 /* VMXON physical-address width limits. */
7900 if (GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
7901 {
7902 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
7903 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
7904 iemVmxVmFailInvalid(pVCpu);
7905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7906 return VINF_SUCCESS;
7907 }
7908
7909 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
7910 restriction imposed by our implementation. */
7911 if (!PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
7912 {
7913 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
7914 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
7915 iemVmxVmFailInvalid(pVCpu);
7916 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7917 return VINF_SUCCESS;
7918 }
7919
7920 /* Read the VMCS revision ID from the VMXON region. */
7921 VMXVMCSREVID VmcsRevId;
7922 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
7923 if (RT_FAILURE(rc))
7924 {
7925 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
7926 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
7927 return rc;
7928 }
7929
7930 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7931 if (RT_UNLIKELY(VmcsRevId.u != VMX_V_VMCS_REVISION_ID))
7932 {
7933 /* Revision ID mismatch. */
7934 if (!VmcsRevId.n.fIsShadowVmcs)
7935 {
7936 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
7937 VmcsRevId.n.u31RevisionId));
7938 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
7939 iemVmxVmFailInvalid(pVCpu);
7940 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7941 return VINF_SUCCESS;
7942 }
7943
7944 /* Shadow VMCS disallowed. */
7945 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
7946 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
7947 iemVmxVmFailInvalid(pVCpu);
7948 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7949 return VINF_SUCCESS;
7950 }
7951
7952 /*
7953 * Record that we're in VMX operation, block INIT, block and disable A20M.
7954 */
7955 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
7956 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7957 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
7958
7959 /* Clear address-range monitoring. */
7960 EMMonitorWaitClear(pVCpu);
7961 /** @todo NSTVMX: Intel PT. */
7962
7963 iemVmxVmSucceed(pVCpu);
7964 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7965# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7966 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7967# else
7968 return VINF_SUCCESS;
7969# endif
7970 }
7971 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7972 {
7973 /* Nested-guest intercept. */
7974 if (pExitInfo)
7975 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7976 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
7977 }
7978
7979 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7980
7981 /* CPL. */
7982 if (pVCpu->iem.s.uCpl > 0)
7983 {
7984 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7985 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
7986 return iemRaiseGeneralProtectionFault0(pVCpu);
7987 }
7988
7989 /* VMXON when already in VMX root mode. */
7990 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
7991 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
7992 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7993 return VINF_SUCCESS;
7994#endif
7995}
7996
7997
7998/**
7999 * Implements 'VMXOFF'.
8000 *
8001 * @remarks Common VMX instruction checks are already expected to by the caller,
8002 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8003 */
8004IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8005{
8006# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
8007 RT_NOREF2(pVCpu, cbInstr);
8008 return VINF_EM_RAW_EMULATE_INSTR;
8009# else
8010 /* Nested-guest intercept. */
8011 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8012 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8013
8014 /* CPL. */
8015 if (pVCpu->iem.s.uCpl > 0)
8016 {
8017 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8018 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8019 return iemRaiseGeneralProtectionFault0(pVCpu);
8020 }
8021
8022 /* Dual monitor treatment of SMIs and SMM. */
8023 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8024 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID)
8025 {
8026 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8027 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8028 return VINF_SUCCESS;
8029 }
8030
8031 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8032 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8033 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8034
8035 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8036 { /** @todo NSTVMX: Unblock SMI. */ }
8037
8038 EMMonitorWaitClear(pVCpu);
8039 /** @todo NSTVMX: Unblock and enable A20M. */
8040
8041 iemVmxVmSucceed(pVCpu);
8042 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8043# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
8044 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
8045# else
8046 return VINF_SUCCESS;
8047# endif
8048# endif
8049}
8050
8051
8052/**
8053 * Implements 'VMXON'.
8054 */
8055IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8056{
8057 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8058}
8059
8060
8061/**
8062 * Implements 'VMLAUNCH'.
8063 */
8064IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8065{
8066 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH, NULL /* pExitInfo */);
8067}
8068
8069
8070/**
8071 * Implements 'VMRESUME'.
8072 */
8073IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8074{
8075 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME, NULL /* pExitInfo */);
8076}
8077
8078
8079/**
8080 * Implements 'VMPTRLD'.
8081 */
8082IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8083{
8084 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8085}
8086
8087
8088/**
8089 * Implements 'VMPTRST'.
8090 */
8091IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8092{
8093 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8094}
8095
8096
8097/**
8098 * Implements 'VMCLEAR'.
8099 */
8100IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8101{
8102 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8103}
8104
8105
8106/**
8107 * Implements 'VMWRITE' register.
8108 */
8109IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8110{
8111 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8112 NULL /* pExitInfo */);
8113}
8114
8115
8116/**
8117 * Implements 'VMWRITE' memory.
8118 */
8119IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8120{
8121 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8122}
8123
8124
8125/**
8126 * Implements 'VMREAD' 64-bit register.
8127 */
8128IEM_CIMPL_DEF_2(iemCImpl_vmread64_reg, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8129{
8130 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8131}
8132
8133
8134/**
8135 * Implements 'VMREAD' 32-bit register.
8136 */
8137IEM_CIMPL_DEF_2(iemCImpl_vmread32_reg, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8138{
8139 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8140}
8141
8142
8143/**
8144 * Implements 'VMREAD' memory.
8145 */
8146IEM_CIMPL_DEF_4(iemCImpl_vmread_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8147{
8148 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8149}
8150
8151
8152/**
8153 * Implements VMX's implementation of PAUSE.
8154 */
8155IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8156{
8157 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8158 {
8159 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8160 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8161 return rcStrict;
8162 }
8163
8164 /*
8165 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8166 * a VM-exit, the instruction operates normally.
8167 */
8168 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8169 return VINF_SUCCESS;
8170}
8171
8172#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8173
8174
8175/**
8176 * Implements 'VMCALL'.
8177 */
8178IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8179{
8180#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8181 /* Nested-guest intercept. */
8182 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8183 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8184#endif
8185
8186 /* Join forces with vmmcall. */
8187 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8188}
8189
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