VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 77459

Last change on this file since 77459 was 77459, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Clear IDT-vectoring information field when the VM-exit is not occurring during delivery of an event. Also clear the IDT-vectoring information field for triple-fault VM-exits.
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File size: 350.8 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 77459 2019-02-25 15:04:16Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 if (rcSched != VINF_SUCCESS) \
172 iemSetPassUpStatus(pVCpu, rcSched); \
173 return (a_rcStrictRet); \
174 } while (0)
175
176# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
177 do { \
178 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
179 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
180 if (rcSched != VINF_SUCCESS) \
181 iemSetPassUpStatus(pVCpu, rcSched); \
182 return (a_rcStrictRet); \
183 } while (0)
184# else
185# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
186# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
187# endif
188
189
190/*********************************************************************************************************************************
191* Global Variables *
192*********************************************************************************************************************************/
193/** @todo NSTVMX: The following VM-exit intercepts are pending:
194 * VMX_EXIT_IO_SMI
195 * VMX_EXIT_SMI
196 * VMX_EXIT_INT_WINDOW
197 * VMX_EXIT_NMI_WINDOW
198 * VMX_EXIT_GETSEC
199 * VMX_EXIT_RSM
200 * VMX_EXIT_MTF
201 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
202 * VMX_EXIT_ERR_MACHINE_CHECK
203 * VMX_EXIT_TPR_BELOW_THRESHOLD
204 * VMX_EXIT_APIC_ACCESS
205 * VMX_EXIT_VIRTUALIZED_EOI
206 * VMX_EXIT_EPT_VIOLATION
207 * VMX_EXIT_EPT_MISCONFIG
208 * VMX_EXIT_INVEPT
209 * VMX_EXIT_PREEMPT_TIMER
210 * VMX_EXIT_INVVPID
211 * VMX_EXIT_APIC_WRITE
212 * VMX_EXIT_RDRAND
213 * VMX_EXIT_VMFUNC
214 * VMX_EXIT_ENCLS
215 * VMX_EXIT_RDSEED
216 * VMX_EXIT_PML_FULL
217 * VMX_EXIT_XSAVES
218 * VMX_EXIT_XRSTORS
219 */
220/**
221 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
222 *
223 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
224 * second dimension is the Index, see VMXVMCSFIELDENC.
225 */
226uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
227{
228 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
233 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
236 },
237 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
238 {
239 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 24-25 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
253 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
254 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
255 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
256 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
258 },
259 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
268 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
270 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
271 },
272 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
275 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
276 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
277 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
278 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
279 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
280 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
281 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
282 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
283 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
284 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
285 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
286 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
287 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
288 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
289 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
290 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
291 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
292 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
293 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
294 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
295 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
296 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
297 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
298 /* 24 */ UINT16_MAX,
299 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
300 },
301 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
304 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 25 */ UINT16_MAX
308 },
309 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
329 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
330 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
331 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
332 },
333 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
334 {
335 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
336 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
337 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
338 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
339 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
340 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
341 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
342 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
343 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
344 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
345 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
346 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
347 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
348 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
349 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
350 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
351 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
352 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
353 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
354 },
355 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
356 {
357 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
358 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
359 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
360 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
361 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
362 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
363 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
364 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
365 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
366 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
367 /* 24-25 */ UINT16_MAX, UINT16_MAX
368 },
369 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
370 {
371 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
372 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
373 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
374 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
375 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
376 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
377 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
378 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
379 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
380 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
381 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
382 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
383 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
384 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
385 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
386 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
387 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
388 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
389 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
390 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
391 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
392 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
393 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
394 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
395 },
396 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
397 {
398 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
399 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
401 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
402 /* 25 */ UINT16_MAX
403 },
404 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
405 {
406 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
407 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
408 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
409 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
410 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
411 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
412 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
413 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
414 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
415 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
416 /* 24-25 */ UINT16_MAX, UINT16_MAX
417 },
418 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
419 {
420 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
421 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
422 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
423 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
424 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
425 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
426 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
429 },
430 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
431 {
432 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
433 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
434 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
435 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
436 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
437 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
438 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
439 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
440 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
441 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
442 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
443 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
444 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
445 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
446 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
447 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
448 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
449 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
450 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
451 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
452 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 },
454 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
455 {
456 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
457 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
458 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
459 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
460 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
461 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
462 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
463 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
464 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
465 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
466 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
467 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
468 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
469 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
470 }
471};
472
473
474/**
475 * Returns whether the given VMCS field is valid and supported by our emulation.
476 *
477 * @param pVCpu The cross context virtual CPU structure.
478 * @param u64FieldEnc The VMCS field encoding.
479 *
480 * @remarks This takes into account the CPU features exposed to the guest.
481 */
482IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
483{
484 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
485 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
486 if (!uFieldEncHi)
487 { /* likely */ }
488 else
489 return false;
490
491 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
492 switch (uFieldEncLo)
493 {
494 /*
495 * 16-bit fields.
496 */
497 /* Control fields. */
498 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
499 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
500 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
501
502 /* Guest-state fields. */
503 case VMX_VMCS16_GUEST_ES_SEL:
504 case VMX_VMCS16_GUEST_CS_SEL:
505 case VMX_VMCS16_GUEST_SS_SEL:
506 case VMX_VMCS16_GUEST_DS_SEL:
507 case VMX_VMCS16_GUEST_FS_SEL:
508 case VMX_VMCS16_GUEST_GS_SEL:
509 case VMX_VMCS16_GUEST_LDTR_SEL:
510 case VMX_VMCS16_GUEST_TR_SEL: return true;
511 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
512 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
513
514 /* Host-state fields. */
515 case VMX_VMCS16_HOST_ES_SEL:
516 case VMX_VMCS16_HOST_CS_SEL:
517 case VMX_VMCS16_HOST_SS_SEL:
518 case VMX_VMCS16_HOST_DS_SEL:
519 case VMX_VMCS16_HOST_FS_SEL:
520 case VMX_VMCS16_HOST_GS_SEL:
521 case VMX_VMCS16_HOST_TR_SEL: return true;
522
523 /*
524 * 64-bit fields.
525 */
526 /* Control fields. */
527 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
528 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
529 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
530 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
531 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
532 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
533 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
534 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
535 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
536 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
537 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
538 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
539 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
540 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
541 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
542 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
543 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
544 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
545 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
546 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
547 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
548 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
549 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
550 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
551 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
552 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
553 case VMX_VMCS64_CTRL_EPTP_FULL:
554 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
555 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
557 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
558 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
559 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
560 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
561 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
562 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
563 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
564 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
565 {
566 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
567 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
568 }
569 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
571 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
573 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
574 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
575 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
576 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
577 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
578 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
579 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
580 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
581
582 /* Read-only data fields. */
583 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
584 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
585
586 /* Guest-state fields. */
587 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
588 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
589 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
590 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
591 case VMX_VMCS64_GUEST_PAT_FULL:
592 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
593 case VMX_VMCS64_GUEST_EFER_FULL:
594 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
595 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
596 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
597 case VMX_VMCS64_GUEST_PDPTE0_FULL:
598 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
599 case VMX_VMCS64_GUEST_PDPTE1_FULL:
600 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
601 case VMX_VMCS64_GUEST_PDPTE2_FULL:
602 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
603 case VMX_VMCS64_GUEST_PDPTE3_FULL:
604 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
605 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
606 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
607
608 /* Host-state fields. */
609 case VMX_VMCS64_HOST_PAT_FULL:
610 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
611 case VMX_VMCS64_HOST_EFER_FULL:
612 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
613 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
614 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
615
616 /*
617 * 32-bit fields.
618 */
619 /* Control fields. */
620 case VMX_VMCS32_CTRL_PIN_EXEC:
621 case VMX_VMCS32_CTRL_PROC_EXEC:
622 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
623 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
624 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
625 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
626 case VMX_VMCS32_CTRL_EXIT:
627 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
628 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
629 case VMX_VMCS32_CTRL_ENTRY:
630 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
631 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
632 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
633 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
634 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
635 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
636 case VMX_VMCS32_CTRL_PLE_GAP:
637 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
638
639 /* Read-only data fields. */
640 case VMX_VMCS32_RO_VM_INSTR_ERROR:
641 case VMX_VMCS32_RO_EXIT_REASON:
642 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
643 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
644 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
645 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
646 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
647 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
648
649 /* Guest-state fields. */
650 case VMX_VMCS32_GUEST_ES_LIMIT:
651 case VMX_VMCS32_GUEST_CS_LIMIT:
652 case VMX_VMCS32_GUEST_SS_LIMIT:
653 case VMX_VMCS32_GUEST_DS_LIMIT:
654 case VMX_VMCS32_GUEST_FS_LIMIT:
655 case VMX_VMCS32_GUEST_GS_LIMIT:
656 case VMX_VMCS32_GUEST_LDTR_LIMIT:
657 case VMX_VMCS32_GUEST_TR_LIMIT:
658 case VMX_VMCS32_GUEST_GDTR_LIMIT:
659 case VMX_VMCS32_GUEST_IDTR_LIMIT:
660 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
663 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
664 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
665 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
666 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
667 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
668 case VMX_VMCS32_GUEST_INT_STATE:
669 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
670 case VMX_VMCS32_GUEST_SMBASE:
671 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
672 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
673
674 /* Host-state fields. */
675 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
676
677 /*
678 * Natural-width fields.
679 */
680 /* Control fields. */
681 case VMX_VMCS_CTRL_CR0_MASK:
682 case VMX_VMCS_CTRL_CR4_MASK:
683 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
684 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
685 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
686 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
687 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
688 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
689
690 /* Read-only data fields. */
691 case VMX_VMCS_RO_EXIT_QUALIFICATION:
692 case VMX_VMCS_RO_IO_RCX:
693 case VMX_VMCS_RO_IO_RSX:
694 case VMX_VMCS_RO_IO_RDI:
695 case VMX_VMCS_RO_IO_RIP:
696 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
697
698 /* Guest-state fields. */
699 case VMX_VMCS_GUEST_CR0:
700 case VMX_VMCS_GUEST_CR3:
701 case VMX_VMCS_GUEST_CR4:
702 case VMX_VMCS_GUEST_ES_BASE:
703 case VMX_VMCS_GUEST_CS_BASE:
704 case VMX_VMCS_GUEST_SS_BASE:
705 case VMX_VMCS_GUEST_DS_BASE:
706 case VMX_VMCS_GUEST_FS_BASE:
707 case VMX_VMCS_GUEST_GS_BASE:
708 case VMX_VMCS_GUEST_LDTR_BASE:
709 case VMX_VMCS_GUEST_TR_BASE:
710 case VMX_VMCS_GUEST_GDTR_BASE:
711 case VMX_VMCS_GUEST_IDTR_BASE:
712 case VMX_VMCS_GUEST_DR7:
713 case VMX_VMCS_GUEST_RSP:
714 case VMX_VMCS_GUEST_RIP:
715 case VMX_VMCS_GUEST_RFLAGS:
716 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
717 case VMX_VMCS_GUEST_SYSENTER_ESP:
718 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
719
720 /* Host-state fields. */
721 case VMX_VMCS_HOST_CR0:
722 case VMX_VMCS_HOST_CR3:
723 case VMX_VMCS_HOST_CR4:
724 case VMX_VMCS_HOST_FS_BASE:
725 case VMX_VMCS_HOST_GS_BASE:
726 case VMX_VMCS_HOST_TR_BASE:
727 case VMX_VMCS_HOST_GDTR_BASE:
728 case VMX_VMCS_HOST_IDTR_BASE:
729 case VMX_VMCS_HOST_SYSENTER_ESP:
730 case VMX_VMCS_HOST_SYSENTER_EIP:
731 case VMX_VMCS_HOST_RSP:
732 case VMX_VMCS_HOST_RIP: return true;
733 }
734
735 return false;
736}
737
738
739/**
740 * Gets a host selector from the VMCS.
741 *
742 * @param pVmcs Pointer to the virtual VMCS.
743 * @param iSelReg The index of the segment register (X86_SREG_XXX).
744 */
745DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
746{
747 Assert(iSegReg < X86_SREG_COUNT);
748 RTSEL HostSel;
749 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
750 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
751 uint8_t const uWidthType = (uWidth << 2) | uType;
752 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
753 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
754 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
755 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
756 uint8_t const *pbField = pbVmcs + offField;
757 HostSel = *(uint16_t *)pbField;
758 return HostSel;
759}
760
761
762/**
763 * Sets a guest segment register in the VMCS.
764 *
765 * @param pVmcs Pointer to the virtual VMCS.
766 * @param iSegReg The index of the segment register (X86_SREG_XXX).
767 * @param pSelReg Pointer to the segment register.
768 */
769IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
770{
771 Assert(pSelReg);
772 Assert(iSegReg < X86_SREG_COUNT);
773
774 /* Selector. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t *pbField = pbVmcs + offField;
784 *(uint16_t *)pbField = pSelReg->Sel;
785 }
786
787 /* Limit. */
788 {
789 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
790 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
791 uint8_t const uWidthType = (uWidth << 2) | uType;
792 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
793 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
794 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
795 uint8_t *pbVmcs = (uint8_t *)pVmcs;
796 uint8_t *pbField = pbVmcs + offField;
797 *(uint32_t *)pbField = pSelReg->u32Limit;
798 }
799
800 /* Base. */
801 {
802 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
803 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
804 uint8_t const uWidthType = (uWidth << 2) | uType;
805 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
806 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
807 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
808 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
809 uint8_t const *pbField = pbVmcs + offField;
810 *(uint64_t *)pbField = pSelReg->u64Base;
811 }
812
813 /* Attributes. */
814 {
815 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
816 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
817 | X86DESCATTR_UNUSABLE;
818 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
819 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
820 uint8_t const uWidthType = (uWidth << 2) | uType;
821 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
822 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
823 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
824 uint8_t *pbVmcs = (uint8_t *)pVmcs;
825 uint8_t *pbField = pbVmcs + offField;
826 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
827 }
828}
829
830
831/**
832 * Gets a guest segment register from the VMCS.
833 *
834 * @returns VBox status code.
835 * @param pVmcs Pointer to the virtual VMCS.
836 * @param iSegReg The index of the segment register (X86_SREG_XXX).
837 * @param pSelReg Where to store the segment register (only updated when
838 * VINF_SUCCESS is returned).
839 *
840 * @remarks Warning! This does not validate the contents of the retrieved segment
841 * register.
842 */
843IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
844{
845 Assert(pSelReg);
846 Assert(iSegReg < X86_SREG_COUNT);
847
848 /* Selector. */
849 uint16_t u16Sel;
850 {
851 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
852 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
853 uint8_t const uWidthType = (uWidth << 2) | uType;
854 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
855 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
856 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
857 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
858 uint8_t const *pbField = pbVmcs + offField;
859 u16Sel = *(uint16_t *)pbField;
860 }
861
862 /* Limit. */
863 uint32_t u32Limit;
864 {
865 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
866 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
867 uint8_t const uWidthType = (uWidth << 2) | uType;
868 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
869 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
870 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
871 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
872 uint8_t const *pbField = pbVmcs + offField;
873 u32Limit = *(uint32_t *)pbField;
874 }
875
876 /* Base. */
877 uint64_t u64Base;
878 {
879 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
880 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
881 uint8_t const uWidthType = (uWidth << 2) | uType;
882 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
883 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
884 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
885 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
886 uint8_t const *pbField = pbVmcs + offField;
887 u64Base = *(uint64_t *)pbField;
888 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
889 }
890
891 /* Attributes. */
892 uint32_t u32Attr;
893 {
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
898 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 u32Attr = *(uint32_t *)pbField;
903 }
904
905 pSelReg->Sel = u16Sel;
906 pSelReg->ValidSel = u16Sel;
907 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
908 pSelReg->u32Limit = u32Limit;
909 pSelReg->u64Base = u64Base;
910 pSelReg->Attr.u = u32Attr;
911 return VINF_SUCCESS;
912}
913
914
915/**
916 * Gets a CR3 target value from the VMCS.
917 *
918 * @returns VBox status code.
919 * @param pVmcs Pointer to the virtual VMCS.
920 * @param idxCr3Target The index of the CR3-target value to retrieve.
921 * @param puValue Where to store the CR3-target value.
922 */
923IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
924{
925 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
926 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
927 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
928 uint8_t const uWidthType = (uWidth << 2) | uType;
929 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
930 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
931 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
932 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
933 uint8_t const *pbField = pbVmcs + offField;
934 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
935 return uCr3TargetValue;
936}
937
938
939/**
940 * Converts an IEM exception event type to a VMX event type.
941 *
942 * @returns The VMX event type.
943 * @param uVector The interrupt / exception vector.
944 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
945 */
946DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
947{
948 /* Paranoia (callers may use these interchangeably). */
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
956 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
957 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
958 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
959 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
960 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
961
962 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
963 {
964 if (uVector == X86_XCPT_NMI)
965 return VMX_EXIT_INT_INFO_TYPE_NMI;
966 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
967 }
968
969 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
970 {
971 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
972 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
973 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
974 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
975 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
976 }
977
978 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
979 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
980}
981
982
983/**
984 * Sets the VM-instruction error VMCS field.
985 *
986 * @param pVCpu The cross context virtual CPU structure.
987 * @param enmInsErr The VM-instruction error.
988 */
989DECL_FORCE_INLINE(void) iemVmxVmcsSetVmInstrErr(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
990{
991 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
992 pVmcs->u32RoVmInstrError = enmInsErr;
993}
994
995
996/**
997 * Sets the VM-exit qualification VMCS field.
998 *
999 * @param pVCpu The cross context virtual CPU structure.
1000 * @param uExitQual The VM-exit qualification.
1001 */
1002DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
1003{
1004 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1005 pVmcs->u64RoExitQual.u = uExitQual;
1006}
1007
1008
1009/**
1010 * Sets the VM-exit interruption information field.
1011 *
1012 * @param pVCpu The cross context virtual CPU structure.
1013 * @param uExitQual The VM-exit interruption information.
1014 */
1015DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1016{
1017 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1018 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1019}
1020
1021
1022/**
1023 * Sets the VM-exit interruption error code.
1024 *
1025 * @param pVCpu The cross context virtual CPU structure.
1026 * @param uErrCode The error code.
1027 */
1028DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1029{
1030 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1031 pVmcs->u32RoExitIntErrCode = uErrCode;
1032}
1033
1034
1035/**
1036 * Sets the IDT-vectoring information field.
1037 *
1038 * @param pVCpu The cross context virtual CPU structure.
1039 * @param uIdtVectorInfo The IDT-vectoring information.
1040 */
1041DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1042{
1043 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1044 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1045}
1046
1047
1048/**
1049 * Sets the IDT-vectoring error code field.
1050 *
1051 * @param pVCpu The cross context virtual CPU structure.
1052 * @param uErrCode The error code.
1053 */
1054DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1055{
1056 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1057 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1058}
1059
1060
1061/**
1062 * Sets the VM-exit guest-linear address VMCS field.
1063 *
1064 * @param pVCpu The cross context virtual CPU structure.
1065 * @param uGuestLinearAddr The VM-exit guest-linear address.
1066 */
1067DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1068{
1069 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1070 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1071}
1072
1073
1074/**
1075 * Sets the VM-exit guest-physical address VMCS field.
1076 *
1077 * @param pVCpu The cross context virtual CPU structure.
1078 * @param uGuestPhysAddr The VM-exit guest-physical address.
1079 */
1080DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1081{
1082 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1083 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1084}
1085
1086
1087/**
1088 * Sets the VM-exit instruction length VMCS field.
1089 *
1090 * @param pVCpu The cross context virtual CPU structure.
1091 * @param cbInstr The VM-exit instruction length in bytes.
1092 *
1093 * @remarks Callers may clear this field to 0. Hence, this function does not check
1094 * the validity of the instruction length.
1095 */
1096DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1097{
1098 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1099 pVmcs->u32RoExitInstrLen = cbInstr;
1100}
1101
1102
1103/**
1104 * Sets the VM-exit instruction info. VMCS field.
1105 *
1106 * @param pVCpu The cross context virtual CPU structure.
1107 * @param uExitInstrInfo The VM-exit instruction information.
1108 */
1109DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1110{
1111 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1112 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1113}
1114
1115
1116/**
1117 * Implements VMSucceed for VMX instruction success.
1118 *
1119 * @param pVCpu The cross context virtual CPU structure.
1120 */
1121DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1122{
1123 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1124}
1125
1126
1127/**
1128 * Implements VMFailInvalid for VMX instruction failure.
1129 *
1130 * @param pVCpu The cross context virtual CPU structure.
1131 */
1132DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1133{
1134 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1135 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_CF;
1136}
1137
1138
1139/**
1140 * Implements VMFailValid for VMX instruction failure.
1141 *
1142 * @param pVCpu The cross context virtual CPU structure.
1143 * @param enmInsErr The VM instruction error.
1144 */
1145DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1146{
1147 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1148 {
1149 pVCpu->cpum.GstCtx.eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
1150 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_ZF;
1151 iemVmxVmcsSetVmInstrErr(pVCpu, enmInsErr);
1152 }
1153}
1154
1155
1156/**
1157 * Implements VMFail for VMX instruction failure.
1158 *
1159 * @param pVCpu The cross context virtual CPU structure.
1160 * @param enmInsErr The VM instruction error.
1161 */
1162DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1163{
1164 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1165 iemVmxVmFailValid(pVCpu, enmInsErr);
1166 else
1167 iemVmxVmFailInvalid(pVCpu);
1168}
1169
1170
1171/**
1172 * Checks if the given auto-load/store MSR area count is valid for the
1173 * implementation.
1174 *
1175 * @returns @c true if it's within the valid limit, @c false otherwise.
1176 * @param pVCpu The cross context virtual CPU structure.
1177 * @param uMsrCount The MSR area count to check.
1178 */
1179DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1180{
1181 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1182 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1183 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1184 if (uMsrCount <= cMaxSupportedMsrs)
1185 return true;
1186 return false;
1187}
1188
1189
1190/**
1191 * Flushes the current VMCS contents back to guest memory.
1192 *
1193 * @returns VBox status code.
1194 * @param pVCpu The cross context virtual CPU structure.
1195 */
1196DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1197{
1198 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1199 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1200 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1201 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1202 return rc;
1203}
1204
1205
1206/**
1207 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1208 *
1209 * @param pVCpu The cross context virtual CPU structure.
1210 */
1211DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1212{
1213 iemVmxVmSucceed(pVCpu);
1214 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1215}
1216
1217
1218/**
1219 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1220 * nested-guest.
1221 *
1222 * @param iSegReg The segment index (X86_SREG_XXX).
1223 */
1224IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1225{
1226 switch (iSegReg)
1227 {
1228 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1229 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1230 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1231 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1232 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1233 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1234 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1235 }
1236}
1237
1238
1239/**
1240 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1241 * nested-guest that is in Virtual-8086 mode.
1242 *
1243 * @param iSegReg The segment index (X86_SREG_XXX).
1244 */
1245IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1246{
1247 switch (iSegReg)
1248 {
1249 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1250 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1251 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1252 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1253 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1254 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1255 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1256 }
1257}
1258
1259
1260/**
1261 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1262 * nested-guest that is in Virtual-8086 mode.
1263 *
1264 * @param iSegReg The segment index (X86_SREG_XXX).
1265 */
1266IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1267{
1268 switch (iSegReg)
1269 {
1270 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1271 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1272 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1273 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1274 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1275 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1276 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1277 }
1278}
1279
1280
1281/**
1282 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1283 * nested-guest that is in Virtual-8086 mode.
1284 *
1285 * @param iSegReg The segment index (X86_SREG_XXX).
1286 */
1287IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1288{
1289 switch (iSegReg)
1290 {
1291 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1292 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1293 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1294 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1295 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1296 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1297 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1298 }
1299}
1300
1301
1302/**
1303 * Gets the instruction diagnostic for segment attributes reserved bits failure
1304 * during VM-entry of a nested-guest.
1305 *
1306 * @param iSegReg The segment index (X86_SREG_XXX).
1307 */
1308IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1309{
1310 switch (iSegReg)
1311 {
1312 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1313 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1314 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1315 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1316 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1317 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1318 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1319 }
1320}
1321
1322
1323/**
1324 * Gets the instruction diagnostic for segment attributes descriptor-type
1325 * (code/segment or system) failure during VM-entry of a nested-guest.
1326 *
1327 * @param iSegReg The segment index (X86_SREG_XXX).
1328 */
1329IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1330{
1331 switch (iSegReg)
1332 {
1333 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1334 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1335 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1336 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1337 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1338 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1339 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1340 }
1341}
1342
1343
1344/**
1345 * Gets the instruction diagnostic for segment attributes descriptor-type
1346 * (code/segment or system) failure during VM-entry of a nested-guest.
1347 *
1348 * @param iSegReg The segment index (X86_SREG_XXX).
1349 */
1350IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1351{
1352 switch (iSegReg)
1353 {
1354 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1355 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1356 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1357 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1358 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1359 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1360 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1361 }
1362}
1363
1364
1365/**
1366 * Gets the instruction diagnostic for segment attribute granularity failure during
1367 * VM-entry of a nested-guest.
1368 *
1369 * @param iSegReg The segment index (X86_SREG_XXX).
1370 */
1371IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1372{
1373 switch (iSegReg)
1374 {
1375 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1376 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1377 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1378 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1379 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1380 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1381 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1382 }
1383}
1384
1385/**
1386 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1387 * VM-entry of a nested-guest.
1388 *
1389 * @param iSegReg The segment index (X86_SREG_XXX).
1390 */
1391IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1392{
1393 switch (iSegReg)
1394 {
1395 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1396 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1397 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1398 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1399 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1400 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1401 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1402 }
1403}
1404
1405
1406/**
1407 * Gets the instruction diagnostic for segment attribute type accessed failure
1408 * during VM-entry of a nested-guest.
1409 *
1410 * @param iSegReg The segment index (X86_SREG_XXX).
1411 */
1412IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1413{
1414 switch (iSegReg)
1415 {
1416 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1417 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1418 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1419 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1420 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1421 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1422 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1423 }
1424}
1425
1426
1427/**
1428 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1429 * failure during VM-entry of a nested-guest.
1430 *
1431 * @param iSegReg The PDPTE entry index.
1432 */
1433IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1434{
1435 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1436 switch (iPdpte)
1437 {
1438 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1439 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1440 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1441 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1442 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1443 }
1444}
1445
1446
1447/**
1448 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1449 * failure during VM-exit of a nested-guest.
1450 *
1451 * @param iSegReg The PDPTE entry index.
1452 */
1453IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1454{
1455 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1456 switch (iPdpte)
1457 {
1458 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1459 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1460 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1461 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1462 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1463 }
1464}
1465
1466
1467/**
1468 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1469 * mask and the read-shadow (CR0/CR4 read).
1470 *
1471 * @returns The masked CR0/CR4.
1472 * @param pVCpu The cross context virtual CPU structure.
1473 * @param iCrReg The control register (either CR0 or CR4).
1474 * @param uGuestCrX The current guest CR0 or guest CR4.
1475 */
1476IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1477{
1478 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1479 Assert(iCrReg == 0 || iCrReg == 4);
1480
1481 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1482 Assert(pVmcs);
1483
1484 /*
1485 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1486 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1487 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1488 *
1489 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1490 */
1491 uint64_t fGstHostMask;
1492 uint64_t fReadShadow;
1493 if (iCrReg == 0)
1494 {
1495 fGstHostMask = pVmcs->u64Cr0Mask.u;
1496 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1497 }
1498 else
1499 {
1500 fGstHostMask = pVmcs->u64Cr4Mask.u;
1501 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1502 }
1503
1504 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1505 return fMaskedCrX;
1506}
1507
1508
1509/**
1510 * Saves the guest control registers, debug registers and some MSRs are part of
1511 * VM-exit.
1512 *
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1516{
1517 /*
1518 * Saves the guest control registers, debug registers and some MSRs.
1519 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1520 */
1521 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1522
1523 /* Save control registers. */
1524 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1525 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1526 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1527
1528 /* Save SYSENTER CS, ESP, EIP. */
1529 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1530 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1531 {
1532 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1533 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1534 }
1535 else
1536 {
1537 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1538 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1539 }
1540
1541 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1542 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1543 {
1544 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1545 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1546 }
1547
1548 /* Save PAT MSR. */
1549 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1550 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1551
1552 /* Save EFER MSR. */
1553 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1554 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1555
1556 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1557 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1558
1559 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1560}
1561
1562
1563/**
1564 * Saves the guest force-flags in preparation of entering the nested-guest.
1565 *
1566 * @param pVCpu The cross context virtual CPU structure.
1567 */
1568IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1569{
1570 /* We shouldn't be called multiple times during VM-entry. */
1571 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1572
1573 /* MTF should not be set outside VMX non-root mode. */
1574 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1575
1576 /*
1577 * Preserve the required force-flags.
1578 *
1579 * We cache and clear force-flags that would affect the execution of the
1580 * nested-guest. Cached flags are then restored while returning to the guest
1581 * if necessary.
1582 *
1583 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1584 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1585 * instruction. Interrupt inhibition for any nested-guest instruction
1586 * is supplied by the guest-interruptibility state VMCS field and will
1587 * be set up as part of loading the guest state.
1588 *
1589 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1590 * successful VM-entry (due to invalid guest-state) need to continue
1591 * blocking NMIs if it was in effect before VM-entry.
1592 *
1593 * - MTF need not be preserved as it's used only in VMX non-root mode and
1594 * is supplied through the VM-execution controls.
1595 *
1596 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1597 * we will be able to generate interrupts that may cause VM-exits for
1598 * the nested-guest.
1599 */
1600 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1601}
1602
1603
1604/**
1605 * Restores the guest force-flags in preparation of exiting the nested-guest.
1606 *
1607 * @param pVCpu The cross context virtual CPU structure.
1608 */
1609IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1610{
1611 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1612 {
1613 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1614 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1615 }
1616}
1617
1618
1619/**
1620 * Perform a VMX transition updated PGM, IEM and CPUM.
1621 *
1622 * @param pVCpu The cross context virtual CPU structure.
1623 */
1624IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1625{
1626 /*
1627 * Inform PGM about paging mode changes.
1628 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1629 * see comment in iemMemPageTranslateAndCheckAccess().
1630 */
1631 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1632# ifdef IN_RING3
1633 Assert(rc != VINF_PGM_CHANGE_MODE);
1634# endif
1635 AssertRCReturn(rc, rc);
1636
1637 /* Inform CPUM (recompiler), can later be removed. */
1638 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1639
1640 /*
1641 * Flush the TLB with new CR3. This is required in case the PGM mode change
1642 * above doesn't actually change anything.
1643 */
1644 if (rc == VINF_SUCCESS)
1645 {
1646 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1647 AssertRCReturn(rc, rc);
1648 }
1649
1650 /* Re-initialize IEM cache/state after the drastic mode switch. */
1651 iemReInitExec(pVCpu);
1652 return rc;
1653}
1654
1655
1656/**
1657 * Calculates the current VMX-preemption timer value.
1658 *
1659 * @param pVCpu The cross context virtual CPU structure.
1660 */
1661IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1662{
1663 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1664 Assert(pVmcs);
1665
1666 /*
1667 * Assume the following:
1668 * PreemptTimerShift = 5
1669 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1670 * VmentryTick = 50000 (TSC at time of VM-entry)
1671 *
1672 * CurTick Delta PreemptTimerVal
1673 * ----------------------------------
1674 * 60000 10000 2
1675 * 80000 30000 1
1676 * 90000 40000 0 -> VM-exit.
1677 *
1678 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1679 * The saved VMX-preemption timer value is calculated as follows:
1680 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1681 * E.g.:
1682 * Delta = 10000
1683 * Tmp = 10000 / (2 * 10000) = 0.5
1684 * NewPt = 2 - 0.5 = 2
1685 * Delta = 30000
1686 * Tmp = 30000 / (2 * 10000) = 1.5
1687 * NewPt = 2 - 1.5 = 1
1688 * Delta = 40000
1689 * Tmp = 40000 / 20000 = 2
1690 * NewPt = 2 - 2 = 0
1691 */
1692 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1693 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1694 uint64_t const uDelta = uCurTick - uVmentryTick;
1695 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1696 uint32_t const uPreemptTimer = uVmcsPreemptVal
1697 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1698 return uPreemptTimer;
1699}
1700
1701
1702/**
1703 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1704 *
1705 * @param pVCpu The cross context virtual CPU structure.
1706 */
1707IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1708{
1709 /*
1710 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1711 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1712 */
1713 /* CS, SS, ES, DS, FS, GS. */
1714 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1715 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1716 {
1717 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1718 if (!pSelReg->Attr.n.u1Unusable)
1719 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1720 else
1721 {
1722 /*
1723 * For unusable segments the attributes are undefined except for CS and SS.
1724 * For the rest we don't bother preserving anything but the unusable bit.
1725 */
1726 switch (iSegReg)
1727 {
1728 case X86_SREG_CS:
1729 pVmcs->GuestCs = pSelReg->Sel;
1730 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1731 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1732 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1733 | X86DESCATTR_UNUSABLE);
1734 break;
1735
1736 case X86_SREG_SS:
1737 pVmcs->GuestSs = pSelReg->Sel;
1738 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1739 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1740 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1741 break;
1742
1743 case X86_SREG_DS:
1744 pVmcs->GuestDs = pSelReg->Sel;
1745 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1746 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1747 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1748 break;
1749
1750 case X86_SREG_ES:
1751 pVmcs->GuestEs = pSelReg->Sel;
1752 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1753 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1754 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1755 break;
1756
1757 case X86_SREG_FS:
1758 pVmcs->GuestFs = pSelReg->Sel;
1759 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1760 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1761 break;
1762
1763 case X86_SREG_GS:
1764 pVmcs->GuestGs = pSelReg->Sel;
1765 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1766 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1767 break;
1768 }
1769 }
1770 }
1771
1772 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1773 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1774 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1775 | X86DESCATTR_UNUSABLE;
1776 /* LDTR. */
1777 {
1778 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1779 pVmcs->GuestLdtr = pSelReg->Sel;
1780 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1781 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1782 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1783 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1784 }
1785
1786 /* TR. */
1787 {
1788 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1789 pVmcs->GuestTr = pSelReg->Sel;
1790 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1791 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1792 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1793 }
1794
1795 /* GDTR. */
1796 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1797 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1798
1799 /* IDTR. */
1800 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1801 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1802}
1803
1804
1805/**
1806 * Saves guest non-register state as part of VM-exit.
1807 *
1808 * @param pVCpu The cross context virtual CPU structure.
1809 * @param uExitReason The VM-exit reason.
1810 */
1811IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1812{
1813 /*
1814 * Save guest non-register state.
1815 * See Intel spec. 27.3.4 "Saving Non-Register State".
1816 */
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818
1819 /*
1820 * Activity state.
1821 * Most VM-exits will occur in the active state. However, if the first instruction
1822 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1823 * the VM-exit will be from the HLT activity state.
1824 *
1825 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1826 */
1827 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1828 * not? */
1829 EMSTATE enmActivityState = EMGetState(pVCpu);
1830 switch (enmActivityState)
1831 {
1832 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1833 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1834 }
1835
1836 /* Interruptibility-state. */
1837 pVmcs->u32GuestIntrState = 0;
1838 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1839 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1840
1841 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1842 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1843 {
1844 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1845 * currently. */
1846 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1847 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1848 }
1849 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1850
1851 /*
1852 * Pending debug exceptions.
1853 */
1854 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1855 && uExitReason != VMX_EXIT_SMI
1856 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1857 && !HMVmxIsVmexitTrapLike(uExitReason))
1858 {
1859 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1860 * block-by-MovSS is in effect. */
1861 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1862 }
1863 else
1864 {
1865 /*
1866 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1867 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1868 *
1869 * See Intel spec. 24.4.2 "Guest Non-Register State".
1870 */
1871 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1872 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1873 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1874 if (fPendingDbgMask & fBpHitMask)
1875 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1876 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1877 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1878 }
1879
1880 /*
1881 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1882 *
1883 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1884 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1885 */
1886 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1887 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1888 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1889
1890 /* PDPTEs. */
1891 /* We don't support EPT yet. */
1892 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1893 pVmcs->u64GuestPdpte0.u = 0;
1894 pVmcs->u64GuestPdpte1.u = 0;
1895 pVmcs->u64GuestPdpte2.u = 0;
1896 pVmcs->u64GuestPdpte3.u = 0;
1897}
1898
1899
1900/**
1901 * Saves the guest-state as part of VM-exit.
1902 *
1903 * @returns VBox status code.
1904 * @param pVCpu The cross context virtual CPU structure.
1905 * @param uExitReason The VM-exit reason.
1906 */
1907IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1908{
1909 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1910 Assert(pVmcs);
1911
1912 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1913 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1914
1915 /** @todo r=ramshankar: The below hack is no longer necessary because we invoke the
1916 * VM-exit after updating RIP. I'm leaving it in-place temporarily in case
1917 * we need to fix missing exit information or callers still setting
1918 * instruction-length field when it is not necessary. */
1919#if 0
1920 /*
1921 * Save guest RIP, RSP and RFLAGS.
1922 * See Intel spec. 27.3.3 "Saving RIP, RSP and RFLAGS".
1923 *
1924 * For trap-like VM-exits we must advance the RIP by the length of the instruction.
1925 * Callers must pass the instruction length in the VM-exit instruction length
1926 * field though it is undefined for such VM-exits. After updating RIP here, we clear
1927 * the VM-exit instruction length field.
1928 *
1929 * See Intel spec. 27.1 "Architectural State Before A VM Exit"
1930 */
1931 if (HMVmxIsTrapLikeVmexit(uExitReason))
1932 {
1933 uint8_t const cbInstr = pVmcs->u32RoExitInstrLen;
1934 AssertMsg(cbInstr >= 1 && cbInstr <= 15, ("uReason=%u cbInstr=%u\n", uExitReason, cbInstr));
1935 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1936 iemVmxVmcsSetExitInstrLen(pVCpu, 0 /* cbInstr */);
1937 }
1938#endif
1939
1940 /* We don't support enclave mode yet. */
1941 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1942 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1943 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1944
1945 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1946}
1947
1948
1949/**
1950 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1951 *
1952 * @returns VBox status code.
1953 * @param pVCpu The cross context virtual CPU structure.
1954 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1955 */
1956IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1957{
1958 /*
1959 * Save guest MSRs.
1960 * See Intel spec. 27.4 "Saving MSRs".
1961 */
1962 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1963 const char *const pszFailure = "VMX-abort";
1964
1965 /*
1966 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1967 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1968 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1969 */
1970 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1971 if (!cMsrs)
1972 return VINF_SUCCESS;
1973
1974 /*
1975 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1976 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1977 * implementation causes a VMX-abort followed by a triple-fault.
1978 */
1979 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1980 if (fIsMsrCountValid)
1981 { /* likely */ }
1982 else
1983 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1984
1985 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1986 Assert(pMsr);
1987 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1988 {
1989 if ( !pMsr->u32Reserved
1990 && pMsr->u32Msr != MSR_IA32_SMBASE
1991 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1992 {
1993 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1994 if (rcStrict == VINF_SUCCESS)
1995 continue;
1996
1997 /*
1998 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1999 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2000 * recording the MSR index in the auxiliary info. field and indicated further by our
2001 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2002 * if possible, or come up with a better, generic solution.
2003 */
2004 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2005 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
2006 ? kVmxVDiag_Vmexit_MsrStoreRing3
2007 : kVmxVDiag_Vmexit_MsrStore;
2008 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2009 }
2010 else
2011 {
2012 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2013 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
2014 }
2015 }
2016
2017 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
2018 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
2019 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
2020 if (RT_SUCCESS(rc))
2021 { /* likely */ }
2022 else
2023 {
2024 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2025 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
2026 }
2027
2028 NOREF(uExitReason);
2029 NOREF(pszFailure);
2030 return VINF_SUCCESS;
2031}
2032
2033
2034/**
2035 * Performs a VMX abort (due to an fatal error during VM-exit).
2036 *
2037 * @returns Strict VBox status code.
2038 * @param pVCpu The cross context virtual CPU structure.
2039 * @param enmAbort The VMX abort reason.
2040 */
2041IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2042{
2043 /*
2044 * Perform the VMX abort.
2045 * See Intel spec. 27.7 "VMX Aborts".
2046 */
2047 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
2048
2049 /* We don't support SMX yet. */
2050 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2051 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2052 {
2053 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2054 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2055 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2056 }
2057
2058 return VINF_EM_TRIPLE_FAULT;
2059}
2060
2061
2062/**
2063 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2064 *
2065 * @param pVCpu The cross context virtual CPU structure.
2066 */
2067IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2068{
2069 /*
2070 * Load host control registers, debug registers and MSRs.
2071 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2072 */
2073 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2074 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2075
2076 /* CR0. */
2077 {
2078 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2079 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2080 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2081 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2082 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2083 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2084 CPUMSetGuestCR0(pVCpu, uValidCr0);
2085 }
2086
2087 /* CR4. */
2088 {
2089 /* CR4 MB1 bits are not modified. */
2090 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2091 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2092 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2093 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2094 if (fHostInLongMode)
2095 uValidCr4 |= X86_CR4_PAE;
2096 else
2097 uValidCr4 &= ~X86_CR4_PCIDE;
2098 CPUMSetGuestCR4(pVCpu, uValidCr4);
2099 }
2100
2101 /* CR3 (host value validated while checking host-state during VM-entry). */
2102 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2103
2104 /* DR7. */
2105 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2106
2107 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2108
2109 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2110 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2111 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2112 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2113
2114 /* FS, GS bases are loaded later while we load host segment registers. */
2115
2116 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2117 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2118 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2119 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2120 {
2121 if (fHostInLongMode)
2122 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2123 else
2124 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2125 }
2126
2127 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2128
2129 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2130 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2131 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2132
2133 /* We don't support IA32_BNDCFGS MSR yet. */
2134}
2135
2136
2137/**
2138 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2139 *
2140 * @param pVCpu The cross context virtual CPU structure.
2141 */
2142IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2143{
2144 /*
2145 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2146 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2147 *
2148 * Warning! Be careful to not touch fields that are reserved by VT-x,
2149 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2150 */
2151 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2152 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2153
2154 /* CS, SS, ES, DS, FS, GS. */
2155 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2156 {
2157 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2158 bool const fUnusable = RT_BOOL(HostSel == 0);
2159 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2160
2161 /* Selector. */
2162 pSelReg->Sel = HostSel;
2163 pSelReg->ValidSel = HostSel;
2164 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2165
2166 /* Limit. */
2167 pSelReg->u32Limit = 0xffffffff;
2168
2169 /* Base. */
2170 pSelReg->u64Base = 0;
2171
2172 /* Attributes. */
2173 if (iSegReg == X86_SREG_CS)
2174 {
2175 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2176 pSelReg->Attr.n.u1DescType = 1;
2177 pSelReg->Attr.n.u2Dpl = 0;
2178 pSelReg->Attr.n.u1Present = 1;
2179 pSelReg->Attr.n.u1Long = fHostInLongMode;
2180 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2181 pSelReg->Attr.n.u1Granularity = 1;
2182 Assert(!pSelReg->Attr.n.u1Unusable);
2183 Assert(!fUnusable);
2184 }
2185 else
2186 {
2187 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2188 pSelReg->Attr.n.u1DescType = 1;
2189 pSelReg->Attr.n.u2Dpl = 0;
2190 pSelReg->Attr.n.u1Present = 1;
2191 pSelReg->Attr.n.u1DefBig = 1;
2192 pSelReg->Attr.n.u1Granularity = 1;
2193 pSelReg->Attr.n.u1Unusable = fUnusable;
2194 }
2195 }
2196
2197 /* FS base. */
2198 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2199 || fHostInLongMode)
2200 {
2201 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2202 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2203 }
2204
2205 /* GS base. */
2206 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2207 || fHostInLongMode)
2208 {
2209 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2210 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2211 }
2212
2213 /* TR. */
2214 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2215 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2216 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2217 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2218 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2219 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2220 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2221 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2222 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2223 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2224 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2225 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2226 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2227
2228 /* LDTR (Warning! do not touch the base and limits here). */
2229 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2230 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2231 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2232 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2233
2234 /* GDTR. */
2235 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2236 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2237 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2238
2239 /* IDTR.*/
2240 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2241 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2242 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2243}
2244
2245
2246/**
2247 * Checks host PDPTes as part of VM-exit.
2248 *
2249 * @param pVCpu The cross context virtual CPU structure.
2250 * @param uExitReason The VM-exit reason (for logging purposes).
2251 */
2252IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2253{
2254 /*
2255 * Check host PDPTEs.
2256 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2257 */
2258 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2259 const char *const pszFailure = "VMX-abort";
2260 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2261
2262 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2263 && !fHostInLongMode)
2264 {
2265 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2266 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2267 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2268 if (RT_SUCCESS(rc))
2269 {
2270 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2271 {
2272 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2273 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2274 { /* likely */ }
2275 else
2276 {
2277 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2278 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2279 }
2280 }
2281 }
2282 else
2283 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2284 }
2285
2286 NOREF(pszFailure);
2287 NOREF(uExitReason);
2288 return VINF_SUCCESS;
2289}
2290
2291
2292/**
2293 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2294 *
2295 * @returns VBox status code.
2296 * @param pVCpu The cross context virtual CPU structure.
2297 * @param pszInstr The VMX instruction name (for logging purposes).
2298 */
2299IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2300{
2301 /*
2302 * Load host MSRs.
2303 * See Intel spec. 27.6 "Loading MSRs".
2304 */
2305 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2306 const char *const pszFailure = "VMX-abort";
2307
2308 /*
2309 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2310 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2311 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2312 */
2313 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2314 if (!cMsrs)
2315 return VINF_SUCCESS;
2316
2317 /*
2318 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2319 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2320 * implementation causes a VMX-abort followed by a triple-fault.
2321 */
2322 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2323 if (fIsMsrCountValid)
2324 { /* likely */ }
2325 else
2326 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2327
2328 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2329 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2330 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2331 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2332 if (RT_SUCCESS(rc))
2333 {
2334 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2335 Assert(pMsr);
2336 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2337 {
2338 if ( !pMsr->u32Reserved
2339 && pMsr->u32Msr != MSR_K8_FS_BASE
2340 && pMsr->u32Msr != MSR_K8_GS_BASE
2341 && pMsr->u32Msr != MSR_K6_EFER
2342 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2343 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2344 {
2345 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2346 if (rcStrict == VINF_SUCCESS)
2347 continue;
2348
2349 /*
2350 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2351 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2352 * recording the MSR index in the auxiliary info. field and indicated further by our
2353 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2354 * if possible, or come up with a better, generic solution.
2355 */
2356 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2357 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2358 ? kVmxVDiag_Vmexit_MsrLoadRing3
2359 : kVmxVDiag_Vmexit_MsrLoad;
2360 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2361 }
2362 else
2363 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2364 }
2365 }
2366 else
2367 {
2368 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2369 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2370 }
2371
2372 NOREF(uExitReason);
2373 NOREF(pszFailure);
2374 return VINF_SUCCESS;
2375}
2376
2377
2378/**
2379 * Loads the host state as part of VM-exit.
2380 *
2381 * @returns Strict VBox status code.
2382 * @param pVCpu The cross context virtual CPU structure.
2383 * @param uExitReason The VM-exit reason (for logging purposes).
2384 */
2385IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2386{
2387 /*
2388 * Load host state.
2389 * See Intel spec. 27.5 "Loading Host State".
2390 */
2391 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2392 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2393
2394 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2395 if ( CPUMIsGuestInLongMode(pVCpu)
2396 && !fHostInLongMode)
2397 {
2398 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2399 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2400 }
2401
2402 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2403 iemVmxVmexitLoadHostSegRegs(pVCpu);
2404
2405 /*
2406 * Load host RIP, RSP and RFLAGS.
2407 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2408 */
2409 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2410 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2411 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2412
2413 /* Clear address range monitoring. */
2414 EMMonitorWaitClear(pVCpu);
2415
2416 /* Perform the VMX transition (PGM updates). */
2417 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2418 if (rcStrict == VINF_SUCCESS)
2419 {
2420 /* Check host PDPTEs (only when we've fully switched page tables_. */
2421 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2422 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2423 if (RT_FAILURE(rc))
2424 {
2425 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2426 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2427 }
2428 }
2429 else if (RT_SUCCESS(rcStrict))
2430 {
2431 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2432 uExitReason));
2433 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2434 }
2435 else
2436 {
2437 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2438 return VBOXSTRICTRC_VAL(rcStrict);
2439 }
2440
2441 Assert(rcStrict == VINF_SUCCESS);
2442
2443 /* Load MSRs from the VM-exit auto-load MSR area. */
2444 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2445 if (RT_FAILURE(rc))
2446 {
2447 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2448 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2449 }
2450 return VINF_SUCCESS;
2451}
2452
2453
2454/**
2455 * Gets VM-exit instruction information along with any displacement for an
2456 * instruction VM-exit.
2457 *
2458 * @returns The VM-exit instruction information.
2459 * @param pVCpu The cross context virtual CPU structure.
2460 * @param uExitReason The VM-exit reason.
2461 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2462 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2463 * NULL.
2464 */
2465IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2466{
2467 RTGCPTR GCPtrDisp;
2468 VMXEXITINSTRINFO ExitInstrInfo;
2469 ExitInstrInfo.u = 0;
2470
2471 /*
2472 * Get and parse the ModR/M byte from our decoded opcodes.
2473 */
2474 uint8_t bRm;
2475 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2476 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2477 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2478 {
2479 /*
2480 * ModR/M indicates register addressing.
2481 *
2482 * The primary/secondary register operands are reported in the iReg1 or iReg2
2483 * fields depending on whether it is a read/write form.
2484 */
2485 uint8_t idxReg1;
2486 uint8_t idxReg2;
2487 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2488 {
2489 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2490 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2491 }
2492 else
2493 {
2494 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2495 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2496 }
2497 ExitInstrInfo.All.u2Scaling = 0;
2498 ExitInstrInfo.All.iReg1 = idxReg1;
2499 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2500 ExitInstrInfo.All.fIsRegOperand = 1;
2501 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2502 ExitInstrInfo.All.iSegReg = 0;
2503 ExitInstrInfo.All.iIdxReg = 0;
2504 ExitInstrInfo.All.fIdxRegInvalid = 1;
2505 ExitInstrInfo.All.iBaseReg = 0;
2506 ExitInstrInfo.All.fBaseRegInvalid = 1;
2507 ExitInstrInfo.All.iReg2 = idxReg2;
2508
2509 /* Displacement not applicable for register addressing. */
2510 GCPtrDisp = 0;
2511 }
2512 else
2513 {
2514 /*
2515 * ModR/M indicates memory addressing.
2516 */
2517 uint8_t uScale = 0;
2518 bool fBaseRegValid = false;
2519 bool fIdxRegValid = false;
2520 uint8_t iBaseReg = 0;
2521 uint8_t iIdxReg = 0;
2522 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2523 {
2524 /*
2525 * Parse the ModR/M, displacement for 16-bit addressing mode.
2526 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2527 */
2528 uint16_t u16Disp = 0;
2529 uint8_t const offDisp = offModRm + sizeof(bRm);
2530 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2531 {
2532 /* Displacement without any registers. */
2533 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2534 }
2535 else
2536 {
2537 /* Register (index and base). */
2538 switch (bRm & X86_MODRM_RM_MASK)
2539 {
2540 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2541 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2542 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2543 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2544 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2545 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2546 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2547 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2548 }
2549
2550 /* Register + displacement. */
2551 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2552 {
2553 case 0: break;
2554 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2555 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2556 default:
2557 {
2558 /* Register addressing, handled at the beginning. */
2559 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2560 break;
2561 }
2562 }
2563 }
2564
2565 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2566 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2567 }
2568 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2569 {
2570 /*
2571 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2572 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2573 */
2574 uint32_t u32Disp = 0;
2575 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2576 {
2577 /* Displacement without any registers. */
2578 uint8_t const offDisp = offModRm + sizeof(bRm);
2579 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2580 }
2581 else
2582 {
2583 /* Register (and perhaps scale, index and base). */
2584 uint8_t offDisp = offModRm + sizeof(bRm);
2585 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2586 if (iBaseReg == 4)
2587 {
2588 /* An SIB byte follows the ModR/M byte, parse it. */
2589 uint8_t bSib;
2590 uint8_t const offSib = offModRm + sizeof(bRm);
2591 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2592
2593 /* A displacement may follow SIB, update its offset. */
2594 offDisp += sizeof(bSib);
2595
2596 /* Get the scale. */
2597 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2598
2599 /* Get the index register. */
2600 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2601 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2602
2603 /* Get the base register. */
2604 iBaseReg = bSib & X86_SIB_BASE_MASK;
2605 fBaseRegValid = true;
2606 if (iBaseReg == 5)
2607 {
2608 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2609 {
2610 /* Mod is 0 implies a 32-bit displacement with no base. */
2611 fBaseRegValid = false;
2612 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2613 }
2614 else
2615 {
2616 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2617 iBaseReg = X86_GREG_xBP;
2618 }
2619 }
2620 }
2621
2622 /* Register + displacement. */
2623 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2624 {
2625 case 0: /* Handled above */ break;
2626 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2627 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2628 default:
2629 {
2630 /* Register addressing, handled at the beginning. */
2631 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2632 break;
2633 }
2634 }
2635 }
2636
2637 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2638 }
2639 else
2640 {
2641 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2642
2643 /*
2644 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2645 * See Intel instruction spec. 2.2 "IA-32e Mode".
2646 */
2647 uint64_t u64Disp = 0;
2648 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2649 if (fRipRelativeAddr)
2650 {
2651 /*
2652 * RIP-relative addressing mode.
2653 *
2654 * The displacement is 32-bit signed implying an offset range of +/-2G.
2655 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2656 */
2657 uint8_t const offDisp = offModRm + sizeof(bRm);
2658 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2659 }
2660 else
2661 {
2662 uint8_t offDisp = offModRm + sizeof(bRm);
2663
2664 /*
2665 * Register (and perhaps scale, index and base).
2666 *
2667 * REX.B extends the most-significant bit of the base register. However, REX.B
2668 * is ignored while determining whether an SIB follows the opcode. Hence, we
2669 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2670 *
2671 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2672 */
2673 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2674 if (iBaseReg == 4)
2675 {
2676 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2677 uint8_t bSib;
2678 uint8_t const offSib = offModRm + sizeof(bRm);
2679 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2680
2681 /* Displacement may follow SIB, update its offset. */
2682 offDisp += sizeof(bSib);
2683
2684 /* Get the scale. */
2685 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2686
2687 /* Get the index. */
2688 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2689 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2690
2691 /* Get the base. */
2692 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2693 fBaseRegValid = true;
2694 if (iBaseReg == 5)
2695 {
2696 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2697 {
2698 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2699 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2700 }
2701 else
2702 {
2703 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2704 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2705 }
2706 }
2707 }
2708 iBaseReg |= pVCpu->iem.s.uRexB;
2709
2710 /* Register + displacement. */
2711 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2712 {
2713 case 0: /* Handled above */ break;
2714 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2715 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2716 default:
2717 {
2718 /* Register addressing, handled at the beginning. */
2719 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2720 break;
2721 }
2722 }
2723 }
2724
2725 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2726 }
2727
2728 /*
2729 * The primary or secondary register operand is reported in iReg2 depending
2730 * on whether the primary operand is in read/write form.
2731 */
2732 uint8_t idxReg2;
2733 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2734 {
2735 idxReg2 = bRm & X86_MODRM_RM_MASK;
2736 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2737 idxReg2 |= pVCpu->iem.s.uRexB;
2738 }
2739 else
2740 {
2741 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2742 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2743 idxReg2 |= pVCpu->iem.s.uRexReg;
2744 }
2745 ExitInstrInfo.All.u2Scaling = uScale;
2746 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2747 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2748 ExitInstrInfo.All.fIsRegOperand = 0;
2749 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2750 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2751 ExitInstrInfo.All.iIdxReg = iIdxReg;
2752 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2753 ExitInstrInfo.All.iBaseReg = iBaseReg;
2754 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2755 ExitInstrInfo.All.iReg2 = idxReg2;
2756 }
2757
2758 /*
2759 * Handle exceptions to the norm for certain instructions.
2760 * (e.g. some instructions convey an instruction identity in place of iReg2).
2761 */
2762 switch (uExitReason)
2763 {
2764 case VMX_EXIT_GDTR_IDTR_ACCESS:
2765 {
2766 Assert(VMXINSTRID_IS_VALID(uInstrId));
2767 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2768 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2769 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2770 break;
2771 }
2772
2773 case VMX_EXIT_LDTR_TR_ACCESS:
2774 {
2775 Assert(VMXINSTRID_IS_VALID(uInstrId));
2776 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2777 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2778 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2779 break;
2780 }
2781
2782 case VMX_EXIT_RDRAND:
2783 case VMX_EXIT_RDSEED:
2784 {
2785 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2786 break;
2787 }
2788 }
2789
2790 /* Update displacement and return the constructed VM-exit instruction information field. */
2791 if (pGCPtrDisp)
2792 *pGCPtrDisp = GCPtrDisp;
2793
2794 return ExitInstrInfo.u;
2795}
2796
2797
2798/**
2799 * VMX VM-exit handler.
2800 *
2801 * @returns Strict VBox status code.
2802 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2803 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2804 * triple-fault.
2805 *
2806 * @param pVCpu The cross context virtual CPU structure.
2807 * @param uExitReason The VM-exit reason.
2808 *
2809 * @remarks Make sure VM-exit qualification is updated before calling this
2810 * function!
2811 */
2812IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2813{
2814# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2815 RT_NOREF2(pVCpu, uExitReason);
2816 return VINF_EM_RAW_EMULATE_INSTR;
2817# else
2818 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
2819
2820 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2821 Assert(pVmcs);
2822
2823 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2824 pVmcs->u32RoExitReason = uExitReason;
2825 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2826 IEM_GET_CTX(pVCpu)->cs.Sel, IEM_GET_CTX(pVCpu)->rip));
2827
2828 /*
2829 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
2830 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
2831 */
2832 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2833
2834 /*
2835 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2836 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2837 */
2838 {
2839 uint8_t uVector;
2840 uint32_t fFlags;
2841 uint32_t uErrCode;
2842 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2843 if (!fInEventDelivery)
2844 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2845 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2846 }
2847
2848 /*
2849 * Save the guest state back into the VMCS.
2850 * We only need to save the state when the VM-entry was successful.
2851 */
2852 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2853 if (!fVmentryFailed)
2854 {
2855 /*
2856 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2857 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2858 *
2859 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2860 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2861 * as guest-CPU state would not been modified. Hence for now, we do this only when
2862 * the VM-entry succeeded.
2863 */
2864 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2865 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2866 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2867 {
2868 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2869 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2870 else
2871 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2872 }
2873
2874 /*
2875 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2876 * occurs in enclave mode/SMM which we don't support yet.
2877 *
2878 * If we ever add support for it, we can pass just the lower bits to the functions
2879 * below, till then an assert should suffice.
2880 */
2881 Assert(!RT_HI_U16(uExitReason));
2882
2883 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2884 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2885 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2886 if (RT_SUCCESS(rc))
2887 { /* likely */ }
2888 else
2889 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2890
2891 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2892 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2893 }
2894 else
2895 {
2896 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2897 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2898 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2899 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2900 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2901 }
2902
2903 /* Restore the host (outer guest) state. */
2904 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2905 if (RT_SUCCESS(rcStrict))
2906 {
2907 Assert(rcStrict == VINF_SUCCESS);
2908 rcStrict = VINF_VMX_VMEXIT;
2909 }
2910 else
2911 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2912
2913 /* We're no longer in nested-guest execution mode. */
2914 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2915
2916 /* Revert any IEM-only nested-guest execution policy if it was set earlier, otherwise return rcStrict. */
2917 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(pVCpu, "VM-exit", rcStrict);
2918# endif
2919}
2920
2921
2922/**
2923 * VMX VM-exit handler for VM-exits due to instruction execution.
2924 *
2925 * This is intended for instructions where the caller provides all the relevant
2926 * VM-exit information.
2927 *
2928 * @returns Strict VBox status code.
2929 * @param pVCpu The cross context virtual CPU structure.
2930 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2931 */
2932DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2933{
2934 /*
2935 * For instructions where any of the following fields are not applicable:
2936 * - VM-exit instruction info. is undefined.
2937 * - VM-exit qualification must be cleared.
2938 * - VM-exit guest-linear address is undefined.
2939 * - VM-exit guest-physical address is undefined.
2940 *
2941 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2942 * instruction execution. For VM-exits that are not due to instruction execution this
2943 * field is undefined.
2944 *
2945 * In our implementation in IEM, all undefined fields are generally cleared. However,
2946 * if the caller supplies information (from say the physical CPU directly) it is
2947 * then possible that the undefined fields are not cleared.
2948 *
2949 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2950 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2951 */
2952 Assert(pExitInfo);
2953 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2954 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2955 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2956
2957 /* Update all the relevant fields from the VM-exit instruction information struct. */
2958 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2959 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2960 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2961 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2962 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2963
2964 /* Perform the VM-exit. */
2965 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2966}
2967
2968
2969/**
2970 * VMX VM-exit handler for VM-exits due to instruction execution.
2971 *
2972 * This is intended for instructions that only provide the VM-exit instruction
2973 * length.
2974 *
2975 * @param pVCpu The cross context virtual CPU structure.
2976 * @param uExitReason The VM-exit reason.
2977 * @param cbInstr The instruction length in bytes.
2978 */
2979IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2980{
2981 VMXVEXITINFO ExitInfo;
2982 RT_ZERO(ExitInfo);
2983 ExitInfo.uReason = uExitReason;
2984 ExitInfo.cbInstr = cbInstr;
2985
2986#ifdef VBOX_STRICT
2987 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2988 switch (uExitReason)
2989 {
2990 case VMX_EXIT_INVEPT:
2991 case VMX_EXIT_INVPCID:
2992 case VMX_EXIT_LDTR_TR_ACCESS:
2993 case VMX_EXIT_GDTR_IDTR_ACCESS:
2994 case VMX_EXIT_VMCLEAR:
2995 case VMX_EXIT_VMPTRLD:
2996 case VMX_EXIT_VMPTRST:
2997 case VMX_EXIT_VMREAD:
2998 case VMX_EXIT_VMWRITE:
2999 case VMX_EXIT_VMXON:
3000 case VMX_EXIT_XRSTORS:
3001 case VMX_EXIT_XSAVES:
3002 case VMX_EXIT_RDRAND:
3003 case VMX_EXIT_RDSEED:
3004 case VMX_EXIT_IO_INSTR:
3005 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
3006 break;
3007 }
3008#endif
3009
3010 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3011}
3012
3013
3014/**
3015 * VMX VM-exit handler for VM-exits due to instruction execution.
3016 *
3017 * This is intended for instructions that have a ModR/M byte and update the VM-exit
3018 * instruction information and VM-exit qualification fields.
3019 *
3020 * @param pVCpu The cross context virtual CPU structure.
3021 * @param uExitReason The VM-exit reason.
3022 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
3023 * @param cbInstr The instruction length in bytes.
3024 *
3025 * @remarks Do not use this for INS/OUTS instruction.
3026 */
3027IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
3028{
3029 VMXVEXITINFO ExitInfo;
3030 RT_ZERO(ExitInfo);
3031 ExitInfo.uReason = uExitReason;
3032 ExitInfo.cbInstr = cbInstr;
3033
3034 /*
3035 * Update the VM-exit qualification field with displacement bytes.
3036 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3037 */
3038 switch (uExitReason)
3039 {
3040 case VMX_EXIT_INVEPT:
3041 case VMX_EXIT_INVPCID:
3042 case VMX_EXIT_LDTR_TR_ACCESS:
3043 case VMX_EXIT_GDTR_IDTR_ACCESS:
3044 case VMX_EXIT_VMCLEAR:
3045 case VMX_EXIT_VMPTRLD:
3046 case VMX_EXIT_VMPTRST:
3047 case VMX_EXIT_VMREAD:
3048 case VMX_EXIT_VMWRITE:
3049 case VMX_EXIT_VMXON:
3050 case VMX_EXIT_XRSTORS:
3051 case VMX_EXIT_XSAVES:
3052 case VMX_EXIT_RDRAND:
3053 case VMX_EXIT_RDSEED:
3054 {
3055 /* Construct the VM-exit instruction information. */
3056 RTGCPTR GCPtrDisp;
3057 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3058
3059 /* Update the VM-exit instruction information. */
3060 ExitInfo.InstrInfo.u = uInstrInfo;
3061
3062 /* Update the VM-exit qualification. */
3063 ExitInfo.u64Qual = GCPtrDisp;
3064 break;
3065 }
3066
3067 default:
3068 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3069 break;
3070 }
3071
3072 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3073}
3074
3075
3076/**
3077 * Checks whether an I/O instruction for the given port is intercepted (causes a
3078 * VM-exit) or not.
3079 *
3080 * @returns @c true if the instruction is intercepted, @c false otherwise.
3081 * @param pVCpu The cross context virtual CPU structure.
3082 * @param u16Port The I/O port being accessed by the instruction.
3083 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3084 */
3085IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3086{
3087 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3088 Assert(pVmcs);
3089
3090 /*
3091 * Check whether the I/O instruction must cause a VM-exit or not.
3092 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3093 */
3094 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3095 return true;
3096
3097 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3098 {
3099 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3100 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3101 Assert(pbIoBitmapA);
3102 Assert(pbIoBitmapB);
3103 return HMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3104 }
3105
3106 return false;
3107}
3108
3109
3110/**
3111 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3112 *
3113 * @returns Strict VBox status code.
3114 * @param pVCpu The cross context virtual CPU structure.
3115 */
3116IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3117{
3118 /*
3119 * The MTF VM-exit can occur even when the MTF VM-execution control is
3120 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3121 * check for it here.
3122 */
3123
3124 /* Clear the force-flag indicating that monitor-trap flag is no longer active. */
3125 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_MTF);
3126
3127 /* Cause the MTF VM-exit. The VM-exit qualification MBZ. */
3128 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3129}
3130
3131
3132/**
3133 * VMX VM-exit handler for VM-exits due to INVLPG.
3134 *
3135 * @returns Strict VBox status code.
3136 * @param pVCpu The cross context virtual CPU structure.
3137 * @param GCPtrPage The guest-linear address of the page being invalidated.
3138 * @param cbInstr The instruction length in bytes.
3139 */
3140IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3141{
3142 VMXVEXITINFO ExitInfo;
3143 RT_ZERO(ExitInfo);
3144 ExitInfo.uReason = VMX_EXIT_INVLPG;
3145 ExitInfo.cbInstr = cbInstr;
3146 ExitInfo.u64Qual = GCPtrPage;
3147 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3148
3149 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3150}
3151
3152
3153/**
3154 * VMX VM-exit handler for VM-exits due to LMSW.
3155 *
3156 * @returns Strict VBox status code.
3157 * @param pVCpu The cross context virtual CPU structure.
3158 * @param uGuestCr0 The current guest CR0.
3159 * @param pu16NewMsw The machine-status word specified in LMSW's source
3160 * operand. This will be updated depending on the VMX
3161 * guest/host CR0 mask if LMSW is not intercepted.
3162 * @param GCPtrEffDst The guest-linear address of the source operand in case
3163 * of a memory operand. For register operand, pass
3164 * NIL_RTGCPTR.
3165 * @param cbInstr The instruction length in bytes.
3166 */
3167IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3168 uint8_t cbInstr)
3169{
3170 /*
3171 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3172 *
3173 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3174 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3175 */
3176 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3177 Assert(pVmcs);
3178 Assert(pu16NewMsw);
3179
3180 bool fIntercept = false;
3181 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3182 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3183
3184 /*
3185 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3186 * CR0.PE case first, before the rest of the bits in the MSW.
3187 *
3188 * If CR0.PE is owned by the host and CR0.PE differs between the
3189 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3190 */
3191 if ( (fGstHostMask & X86_CR0_PE)
3192 && (*pu16NewMsw & X86_CR0_PE)
3193 && !(fReadShadow & X86_CR0_PE))
3194 fIntercept = true;
3195
3196 /*
3197 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3198 * bits differ between the MSW (source operand) and the read-shadow, we must
3199 * cause a VM-exit.
3200 */
3201 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3202 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3203 fIntercept = true;
3204
3205 if (fIntercept)
3206 {
3207 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3208
3209 VMXVEXITINFO ExitInfo;
3210 RT_ZERO(ExitInfo);
3211 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3212 ExitInfo.cbInstr = cbInstr;
3213
3214 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3215 if (fMemOperand)
3216 {
3217 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3218 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3219 }
3220
3221 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3222 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3223 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3224 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3225
3226 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3227 }
3228
3229 /*
3230 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3231 * CR0 guest/host mask must be left unmodified.
3232 *
3233 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3234 */
3235 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3236 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3237
3238 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3239}
3240
3241
3242/**
3243 * VMX VM-exit handler for VM-exits due to CLTS.
3244 *
3245 * @returns Strict VBox status code.
3246 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3247 * VM-exit but must not modify the guest CR0.TS bit.
3248 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3249 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3250 * CR0 fixed bits in VMX operation).
3251 * @param pVCpu The cross context virtual CPU structure.
3252 * @param cbInstr The instruction length in bytes.
3253 */
3254IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3255{
3256 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3257 Assert(pVmcs);
3258
3259 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3260 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3261
3262 /*
3263 * If CR0.TS is owned by the host:
3264 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3265 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3266 * CLTS instruction completes without clearing CR0.TS.
3267 *
3268 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3269 */
3270 if (fGstHostMask & X86_CR0_TS)
3271 {
3272 if (fReadShadow & X86_CR0_TS)
3273 {
3274 Log2(("clts: Guest intercept -> VM-exit\n"));
3275
3276 VMXVEXITINFO ExitInfo;
3277 RT_ZERO(ExitInfo);
3278 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3279 ExitInfo.cbInstr = cbInstr;
3280 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3282 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3283 }
3284
3285 return VINF_VMX_MODIFIES_BEHAVIOR;
3286 }
3287
3288 /*
3289 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3290 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3291 */
3292 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3293}
3294
3295
3296/**
3297 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3298 * (CR0/CR4 write).
3299 *
3300 * @returns Strict VBox status code.
3301 * @param pVCpu The cross context virtual CPU structure.
3302 * @param iCrReg The control register (either CR0 or CR4).
3303 * @param uGuestCrX The current guest CR0/CR4.
3304 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3305 * if no VM-exit is caused.
3306 * @param iGReg The general register from which the CR0/CR4 value is
3307 * being loaded.
3308 * @param cbInstr The instruction length in bytes.
3309 */
3310IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3311 uint8_t cbInstr)
3312{
3313 Assert(puNewCrX);
3314 Assert(iCrReg == 0 || iCrReg == 4);
3315 Assert(iGReg < X86_GREG_COUNT);
3316
3317 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3318 Assert(pVmcs);
3319
3320 uint64_t uGuestCrX;
3321 uint64_t fGstHostMask;
3322 uint64_t fReadShadow;
3323 if (iCrReg == 0)
3324 {
3325 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3326 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3327 fGstHostMask = pVmcs->u64Cr0Mask.u;
3328 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3329 }
3330 else
3331 {
3332 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3333 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3334 fGstHostMask = pVmcs->u64Cr4Mask.u;
3335 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3336 }
3337
3338 /*
3339 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3340 * corresponding bits differ between the source operand and the read-shadow,
3341 * we must cause a VM-exit.
3342 *
3343 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3344 */
3345 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3346 {
3347 Assert(fGstHostMask != 0);
3348 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3349
3350 VMXVEXITINFO ExitInfo;
3351 RT_ZERO(ExitInfo);
3352 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3353 ExitInfo.cbInstr = cbInstr;
3354 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3355 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3356 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3357 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3358 }
3359
3360 /*
3361 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3362 * must not be modified the instruction.
3363 *
3364 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3365 */
3366 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3367
3368 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3369}
3370
3371
3372/**
3373 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3374 *
3375 * @returns VBox strict status code.
3376 * @param pVCpu The cross context virtual CPU structure.
3377 * @param iGReg The general register to which the CR3 value is being stored.
3378 * @param cbInstr The instruction length in bytes.
3379 */
3380IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3381{
3382 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3383 Assert(pVmcs);
3384 Assert(iGReg < X86_GREG_COUNT);
3385 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3386
3387 /*
3388 * If the CR3-store exiting control is set, we must cause a VM-exit.
3389 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3390 */
3391 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3392 {
3393 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3394
3395 VMXVEXITINFO ExitInfo;
3396 RT_ZERO(ExitInfo);
3397 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3398 ExitInfo.cbInstr = cbInstr;
3399 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3400 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3401 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3402 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3403 }
3404
3405 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3406}
3407
3408
3409/**
3410 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3411 *
3412 * @returns VBox strict status code.
3413 * @param pVCpu The cross context virtual CPU structure.
3414 * @param uNewCr3 The new CR3 value.
3415 * @param iGReg The general register from which the CR3 value is being
3416 * loaded.
3417 * @param cbInstr The instruction length in bytes.
3418 */
3419IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3420{
3421 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3422 Assert(pVmcs);
3423 Assert(iGReg < X86_GREG_COUNT);
3424
3425 /*
3426 * If the CR3-load exiting control is set and the new CR3 value does not
3427 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3428 *
3429 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3430 */
3431 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3432 {
3433 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3434 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3435
3436 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3437 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3438 if (!fIntercept)
3439 {
3440 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3441 {
3442 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3443 if (uNewCr3 != uCr3TargetValue)
3444 {
3445 fIntercept = true;
3446 break;
3447 }
3448 }
3449 }
3450
3451 if (fIntercept)
3452 {
3453 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3454
3455 VMXVEXITINFO ExitInfo;
3456 RT_ZERO(ExitInfo);
3457 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3458 ExitInfo.cbInstr = cbInstr;
3459 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3460 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3461 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3462 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3463 }
3464 }
3465
3466 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3467}
3468
3469
3470/**
3471 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3472 *
3473 * @returns VBox strict status code.
3474 * @param pVCpu The cross context virtual CPU structure.
3475 * @param iGReg The general register to which the CR8 value is being stored.
3476 * @param cbInstr The instruction length in bytes.
3477 */
3478IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3479{
3480 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3481 Assert(pVmcs);
3482 Assert(iGReg < X86_GREG_COUNT);
3483
3484 /*
3485 * If the CR8-store exiting control is set, we must cause a VM-exit.
3486 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3487 */
3488 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3489 {
3490 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3491
3492 VMXVEXITINFO ExitInfo;
3493 RT_ZERO(ExitInfo);
3494 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3495 ExitInfo.cbInstr = cbInstr;
3496 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3497 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3498 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3499 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3500 }
3501
3502 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3503}
3504
3505
3506/**
3507 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3508 *
3509 * @returns VBox strict status code.
3510 * @param pVCpu The cross context virtual CPU structure.
3511 * @param iGReg The general register from which the CR8 value is being
3512 * loaded.
3513 * @param cbInstr The instruction length in bytes.
3514 */
3515IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3516{
3517 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3518 Assert(pVmcs);
3519 Assert(iGReg < X86_GREG_COUNT);
3520
3521 /*
3522 * If the CR8-load exiting control is set, we must cause a VM-exit.
3523 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3524 */
3525 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3526 {
3527 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3528
3529 VMXVEXITINFO ExitInfo;
3530 RT_ZERO(ExitInfo);
3531 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3532 ExitInfo.cbInstr = cbInstr;
3533 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3534 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3535 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3536 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3537 }
3538
3539 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3540}
3541
3542
3543/**
3544 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3545 * GReg,DRx' (DRx read).
3546 *
3547 * @returns VBox strict status code.
3548 * @param pVCpu The cross context virtual CPU structure.
3549 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3550 * VMXINSTRID_MOV_FROM_DRX).
3551 * @param iDrReg The debug register being accessed.
3552 * @param iGReg The general register to/from which the DRx value is being
3553 * store/loaded.
3554 * @param cbInstr The instruction length in bytes.
3555 */
3556IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3557 uint8_t cbInstr)
3558{
3559 Assert(iDrReg <= 7);
3560 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3561 Assert(iGReg < X86_GREG_COUNT);
3562
3563 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3564 Assert(pVmcs);
3565
3566 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3567 {
3568 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3569 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3570 VMXVEXITINFO ExitInfo;
3571 RT_ZERO(ExitInfo);
3572 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3573 ExitInfo.cbInstr = cbInstr;
3574 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3575 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3576 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3577 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3578 }
3579
3580 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3581}
3582
3583
3584/**
3585 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3586 *
3587 * @returns VBox strict status code.
3588 * @param pVCpu The cross context virtual CPU structure.
3589 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3590 * VMXINSTRID_IO_OUT).
3591 * @param u16Port The I/O port being accessed.
3592 * @param fImm Whether the I/O port was encoded using an immediate operand
3593 * or the implicit DX register.
3594 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3595 * @param cbInstr The instruction length in bytes.
3596 */
3597IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3598 uint8_t cbInstr)
3599{
3600 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3601 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3602
3603 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3604 if (fIntercept)
3605 {
3606 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3607 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3608 VMXVEXITINFO ExitInfo;
3609 RT_ZERO(ExitInfo);
3610 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3611 ExitInfo.cbInstr = cbInstr;
3612 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3613 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3614 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3615 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3616 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3617 }
3618
3619 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3620}
3621
3622
3623/**
3624 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3625 *
3626 * @returns VBox strict status code.
3627 * @param pVCpu The cross context virtual CPU structure.
3628 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3629 * VMXINSTRID_IO_OUTS).
3630 * @param u16Port The I/O port being accessed.
3631 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3632 * @param fRep Whether the instruction has a REP prefix or not.
3633 * @param ExitInstrInfo The VM-exit instruction info. field.
3634 * @param cbInstr The instruction length in bytes.
3635 */
3636IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3637 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3638{
3639 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3640 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3641 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3642 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3643 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3644
3645 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3646 if (fIntercept)
3647 {
3648 /*
3649 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3650 */
3651 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3652 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3653 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3654 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3655 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3656
3657 uint32_t uDirection;
3658 uint64_t uGuestLinearAddr;
3659 if (uInstrId == VMXINSTRID_IO_INS)
3660 {
3661 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3662 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3663 }
3664 else
3665 {
3666 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3667 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3668 }
3669
3670 /*
3671 * If the segment is ununsable, the guest-linear address in undefined.
3672 * We shall clear it for consistency.
3673 *
3674 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3675 */
3676 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3677 uGuestLinearAddr = 0;
3678
3679 VMXVEXITINFO ExitInfo;
3680 RT_ZERO(ExitInfo);
3681 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3682 ExitInfo.cbInstr = cbInstr;
3683 ExitInfo.InstrInfo = ExitInstrInfo;
3684 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3685 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3686 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3687 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3688 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3689 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3690 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3691 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3692 }
3693
3694 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3695}
3696
3697
3698/**
3699 * VMX VM-exit handler for VM-exits due to MWAIT.
3700 *
3701 * @returns VBox strict status code.
3702 * @param pVCpu The cross context virtual CPU structure.
3703 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3704 * @param cbInstr The instruction length in bytes.
3705 */
3706IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3707{
3708 VMXVEXITINFO ExitInfo;
3709 RT_ZERO(ExitInfo);
3710 ExitInfo.uReason = VMX_EXIT_MWAIT;
3711 ExitInfo.cbInstr = cbInstr;
3712 ExitInfo.u64Qual = fMonitorHwArmed;
3713 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3714}
3715
3716
3717/**
3718 * VMX VM-exit handler for VM-exits due to PAUSE.
3719 *
3720 * @returns VBox strict status code.
3721 * @param pVCpu The cross context virtual CPU structure.
3722 * @param cbInstr The instruction length in bytes.
3723 */
3724IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3725{
3726 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3727 Assert(pVmcs);
3728
3729 /*
3730 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3731 * "PAUSE-loop exiting" control.
3732 *
3733 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3734 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3735 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3736 * a VM-exit.
3737 *
3738 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3739 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3740 */
3741 bool fIntercept = false;
3742 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3743 fIntercept = true;
3744 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3745 && pVCpu->iem.s.uCpl == 0)
3746 {
3747 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3748
3749 /*
3750 * A previous-PAUSE-tick value of 0 is used to identify the first time
3751 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3752 * consider this to be the first execution of PAUSE in a loop according
3753 * to the Intel.
3754 *
3755 * All subsequent records for the previous-PAUSE-tick we ensure that it
3756 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3757 */
3758 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3759 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3760 uint64_t const uTick = TMCpuTickGet(pVCpu);
3761 uint32_t const uPleGap = pVmcs->u32PleGap;
3762 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3763 if ( *puPrevPauseTick == 0
3764 || uTick - *puPrevPauseTick > uPleGap)
3765 *puFirstPauseLoopTick = uTick;
3766 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3767 fIntercept = true;
3768
3769 *puPrevPauseTick = uTick | 1;
3770 }
3771
3772 if (fIntercept)
3773 {
3774 VMXVEXITINFO ExitInfo;
3775 RT_ZERO(ExitInfo);
3776 ExitInfo.uReason = VMX_EXIT_PAUSE;
3777 ExitInfo.cbInstr = cbInstr;
3778 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3779 }
3780
3781 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3782}
3783
3784
3785/**
3786 * VMX VM-exit handler for VM-exits due to task switches.
3787 *
3788 * @returns VBox strict status code.
3789 * @param pVCpu The cross context virtual CPU structure.
3790 * @param enmTaskSwitch The cause of the task switch.
3791 * @param SelNewTss The selector of the new TSS.
3792 * @param cbInstr The instruction length in bytes.
3793 */
3794IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3795{
3796 /*
3797 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3798 *
3799 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3800 * instruction or delivery of the exception generated by one of these instructions
3801 * lead to a task switch through a task gate in the IDT, we need to provide the
3802 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3803 * leaves the VM-exit instruction length field undefined.
3804 *
3805 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3806 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3807 */
3808 Assert(cbInstr <= 15);
3809
3810 uint8_t uType;
3811 switch (enmTaskSwitch)
3812 {
3813 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3814 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3815 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3816 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3817 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3818 }
3819
3820 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3821 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3822 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3823 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3824 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3825}
3826
3827
3828/**
3829 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3830 *
3831 * @returns VBox strict status code.
3832 * @param pVCpu The cross context virtual CPU structure.
3833 */
3834IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3835{
3836 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3837 Assert(pVmcs);
3838
3839 /* Check if the guest has enabled VMX-preemption timers in the first place. */
3840 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3841 {
3842 /*
3843 * Calculate the current VMX-preemption timer value.
3844 * Only if the value has reached zero, we cause the VM-exit.
3845 */
3846 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3847 if (!uPreemptTimer)
3848 {
3849 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3850 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3851 pVmcs->u32PreemptTimer = 0;
3852
3853 /* Clear the force-flag indicating the VMX-preemption timer no longer active. */
3854 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3855
3856 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3857 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3858 }
3859 }
3860
3861 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3862}
3863
3864
3865/**
3866 * VMX VM-exit handler for VM-exits due to external interrupts.
3867 *
3868 * @returns VBox strict status code.
3869 * @param pVCpu The cross context virtual CPU structure.
3870 * @param uVector The external interrupt vector (pass 0 if the interrupt
3871 * is still pending since we typically won't know the
3872 * vector).
3873 * @param fIntPending Whether the external interrupt is pending or
3874 * acknowledged in the interrupt controller.
3875 */
3876IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3877{
3878 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3879 Assert(pVmcs);
3880 Assert(fIntPending || uVector == 0);
3881
3882 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3883 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3884 {
3885 if (fIntPending)
3886 {
3887 /*
3888 * If the interrupt is pending and we don't need to acknowledge the
3889 * interrupt on VM-exit, cause the VM-exit immediately.
3890 *
3891 * See Intel spec 25.2 "Other Causes Of VM Exits".
3892 */
3893 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3894 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3895
3896 /*
3897 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3898 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3899 * acknowledged that the interrupt has been consumed.
3900 */
3901 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3902 }
3903
3904 /*
3905 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3906 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3907 * all set, we cause the VM-exit now. We need to record the external interrupt that
3908 * just occurred in the VM-exit interruption information field.
3909 *
3910 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3911 */
3912 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3913 {
3914 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3915 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3916 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3917 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3918 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3919 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3920 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3921 }
3922 }
3923
3924 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3925}
3926
3927
3928/**
3929 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3930 *
3931 * @returns VBox strict status code.
3932 * @param pVCpu The cross context virtual CPU structure.
3933 * @param uVector The SIPI vector.
3934 */
3935IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3936{
3937 iemVmxVmcsSetExitQual(pVCpu, uVector);
3938 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3939}
3940
3941
3942/**
3943 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3944 *
3945 * @returns VBox strict status code.
3946 * @param pVCpu The cross context virtual CPU structure.
3947 */
3948IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3949{
3950 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3951}
3952
3953
3954/**
3955 * VMX VM-exit handler for interrupt-window VM-exits.
3956 *
3957 * @returns VBox strict status code.
3958 * @param pVCpu The cross context virtual CPU structure.
3959 */
3960IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3961{
3962 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3963}
3964
3965
3966/**
3967 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3968 * an event.
3969 *
3970 * @returns VBox strict status code.
3971 * @param pVCpu The cross context virtual CPU structure.
3972 */
3973IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3974{
3975 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3976 Assert(pVmcs);
3977
3978 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3979 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3980 {
3981 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3982 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3983 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3984 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3985 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3986 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3987 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3988 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3989 iemVmxVmcsSetExitQual(pVCpu, 0);
3990 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3991
3992 /*
3993 * A VM-exit is not considered to occur during event delivery when the original
3994 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3995 * using the exception bitmap).
3996 *
3997 * Therefore, we must clear the original event from the IDT-vectoring fields which
3998 * would've been recorded before causing the VM-exit.
3999 *
4000 * 27.2.3 "Information for VM Exits During Event Delivery"
4001 */
4002 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4003 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4004
4005 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4006 }
4007
4008 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4009}
4010
4011
4012/**
4013 * VMX VM-exit handler for VM-exits due to delivery of an event.
4014 *
4015 * @returns VBox strict status code.
4016 * @param pVCpu The cross context virtual CPU structure.
4017 * @param uVector The interrupt / exception vector.
4018 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
4019 * @param uErrCode The error code associated with the event.
4020 * @param uCr2 The CR2 value in case of a \#PF exception.
4021 * @param cbInstr The instruction length in bytes.
4022 */
4023IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
4024 uint8_t cbInstr)
4025{
4026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4027 Assert(pVmcs);
4028
4029 /*
4030 * If the event is being injected as part of VM-entry, it isn't subject to event
4031 * intercepts in the nested-guest. However, secondary exceptions that occur during
4032 * injection of any event -are- subject to event interception.
4033 *
4034 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
4035 */
4036 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
4037 {
4038 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
4039 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
4040 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4041 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
4042 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
4043 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
4044 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
4045 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
4046 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
4047
4048 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4049 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4050 }
4051
4052 /*
4053 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4054 * If not, the caller will continue delivery of the external interrupt as it would
4055 * normally. The interrupt is no longer pending in the interrupt controller at this
4056 * point.
4057 */
4058 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4059 {
4060 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4061 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4062 }
4063
4064 /*
4065 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4066 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4067 */
4068 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4069 bool fIntercept = false;
4070 bool fIsHwXcpt = false;
4071 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4072 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4073 {
4074 fIsHwXcpt = true;
4075 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4076 if (uVector == X86_XCPT_NMI)
4077 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
4078 else
4079 {
4080 /* Page-faults are subject to masking using its error code. */
4081 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4082 if (uVector == X86_XCPT_PF)
4083 {
4084 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4085 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4086 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4087 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4088 }
4089
4090 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4091 if (fXcptBitmap & RT_BIT(uVector))
4092 fIntercept = true;
4093 }
4094 }
4095 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4096
4097 /*
4098 * Now that we've determined whether the software interrupt or hardware exception
4099 * causes a VM-exit, we need to construct the relevant VM-exit information and
4100 * cause the VM-exit.
4101 */
4102 if (fIntercept)
4103 {
4104 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4105
4106 /* Construct the rest of the event related information fields and cause the VM-exit. */
4107 uint64_t uExitQual = 0;
4108 if (fIsHwXcpt)
4109 {
4110 if (uVector == X86_XCPT_PF)
4111 {
4112 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4113 uExitQual = uCr2;
4114 }
4115 else if (uVector == X86_XCPT_DB)
4116 {
4117 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
4118 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4119 }
4120 }
4121
4122 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4123 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4124 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4125 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4126 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4127 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4128 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4129 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4130 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4131 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4132 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4133
4134 /*
4135 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4136 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4137 * length.
4138 */
4139 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4140 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4141 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4142 else
4143 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4144
4145 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4146 }
4147
4148 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4149}
4150
4151
4152/**
4153 * VMX VM-exit handler for VM-exits due to a triple fault.
4154 *
4155 * @returns VBox strict status code.
4156 * @param pVCpu The cross context virtual CPU structure.
4157 */
4158IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4159{
4160 /*
4161 * A VM-exit is not considered to occur during event delivery when the original
4162 * event results in a triple-fault.
4163 *
4164 * Therefore, we must clear the original event from the IDT-vectoring fields which
4165 * would've been recorded before causing the VM-exit.
4166 *
4167 * 27.2.3 "Information for VM Exits During Event Delivery"
4168 */
4169 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4170 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4171
4172 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4173}
4174
4175
4176/**
4177 * VMX VM-exit handler for APIC-accesses.
4178 *
4179 * @param pVCpu The cross context virtual CPU structure.
4180 * @param offAccess The offset of the register being accessed.
4181 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4182 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4183 */
4184IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4185{
4186 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4187
4188 VMXAPICACCESS enmAccess;
4189 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4190 if (fInEventDelivery)
4191 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4192 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4193 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4194 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4195 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4196 else
4197 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4198
4199 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4201 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4202 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4203}
4204
4205
4206/**
4207 * VMX VM-exit handler for APIC-write VM-exits.
4208 *
4209 * @param pVCpu The cross context virtual CPU structure.
4210 * @param offApic The write to the virtual-APIC page offset that caused this
4211 * VM-exit.
4212 */
4213IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4214{
4215 Assert(offApic < XAPIC_OFF_END + 4);
4216
4217 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4218 offApic &= UINT16_C(0xfff);
4219 iemVmxVmcsSetExitQual(pVCpu, offApic);
4220 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4221}
4222
4223
4224/**
4225 * VMX VM-exit handler for virtualized-EOIs.
4226 *
4227 * @param pVCpu The cross context virtual CPU structure.
4228 */
4229IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4230{
4231 iemVmxVmcsSetExitQual(pVCpu, uVector);
4232 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4233}
4234
4235
4236/**
4237 * Sets virtual-APIC write emulation as pending.
4238 *
4239 * @param pVCpu The cross context virtual CPU structure.
4240 * @param offApic The offset in the virtual-APIC page that was written.
4241 */
4242DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4243{
4244 Assert(offApic < XAPIC_OFF_END + 4);
4245
4246 /*
4247 * Record the currently updated APIC offset, as we need this later for figuring
4248 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4249 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4250 */
4251 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4252
4253 /*
4254 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4255 * virtualization or APIC-write emulation).
4256 */
4257 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4258 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4259}
4260
4261
4262/**
4263 * Clears any pending virtual-APIC write emulation.
4264 *
4265 * @returns The virtual-APIC offset that was written before clearing it.
4266 * @param pVCpu The cross context virtual CPU structure.
4267 */
4268DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4269{
4270 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4271 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4272 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4273 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4274 return offVirtApicWrite;
4275}
4276
4277
4278/**
4279 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4280 *
4281 * @returns The register from the virtual-APIC page.
4282 * @param pVCpu The cross context virtual CPU structure.
4283 * @param offReg The offset of the register being read.
4284 */
4285DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4286{
4287 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4288 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4289 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4290 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4291 return uReg;
4292}
4293
4294
4295/**
4296 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4297 *
4298 * @returns The register from the virtual-APIC page.
4299 * @param pVCpu The cross context virtual CPU structure.
4300 * @param offReg The offset of the register being read.
4301 */
4302DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4303{
4304 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4305 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4306 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4307 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4308 return uReg;
4309}
4310
4311
4312/**
4313 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4314 *
4315 * @param pVCpu The cross context virtual CPU structure.
4316 * @param offReg The offset of the register being written.
4317 * @param uReg The register value to write.
4318 */
4319DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4320{
4321 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4322 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4323 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4324 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4325}
4326
4327
4328/**
4329 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4330 *
4331 * @param pVCpu The cross context virtual CPU structure.
4332 * @param offReg The offset of the register being written.
4333 * @param uReg The register value to write.
4334 */
4335DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4336{
4337 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4338 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4339 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4340 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4341}
4342
4343
4344/**
4345 * Sets the vector in a virtual-APIC 256-bit sparse register.
4346 *
4347 * @param pVCpu The cross context virtual CPU structure.
4348 * @param offReg The offset of the 256-bit spare register.
4349 * @param uVector The vector to set.
4350 *
4351 * @remarks This is based on our APIC device code.
4352 */
4353DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4354{
4355 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4356 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4357 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4358 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4359 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4360}
4361
4362
4363/**
4364 * Clears the vector in a virtual-APIC 256-bit sparse register.
4365 *
4366 * @param pVCpu The cross context virtual CPU structure.
4367 * @param offReg The offset of the 256-bit spare register.
4368 * @param uVector The vector to clear.
4369 *
4370 * @remarks This is based on our APIC device code.
4371 */
4372DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4373{
4374 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4375 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4376 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4377 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4378 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4379}
4380
4381
4382/**
4383 * Checks if a memory access to the APIC-access page must causes an APIC-access
4384 * VM-exit.
4385 *
4386 * @param pVCpu The cross context virtual CPU structure.
4387 * @param offAccess The offset of the register being accessed.
4388 * @param cbAccess The size of the access in bytes.
4389 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4390 * IEM_ACCESS_TYPE_WRITE).
4391 *
4392 * @remarks This must not be used for MSR-based APIC-access page accesses!
4393 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4394 */
4395IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4396{
4397 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4398 Assert(pVmcs);
4399 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4400
4401 /*
4402 * We must cause a VM-exit if any of the following are true:
4403 * - TPR shadowing isn't active.
4404 * - The access size exceeds 32-bits.
4405 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4406 *
4407 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4408 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4409 */
4410 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4411 || cbAccess > sizeof(uint32_t)
4412 || ((offAccess + cbAccess - 1) & 0xc)
4413 || offAccess >= XAPIC_OFF_END + 4)
4414 return true;
4415
4416 /*
4417 * If the access is part of an operation where we have already
4418 * virtualized a virtual-APIC write, we must cause a VM-exit.
4419 */
4420 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4421 return true;
4422
4423 /*
4424 * Check write accesses to the APIC-access page that cause VM-exits.
4425 */
4426 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4427 {
4428 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4429 {
4430 /*
4431 * With APIC-register virtualization, a write access to any of the
4432 * following registers are virtualized. Accessing any other register
4433 * causes a VM-exit.
4434 */
4435 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4436 switch (offAlignedAccess)
4437 {
4438 case XAPIC_OFF_ID:
4439 case XAPIC_OFF_TPR:
4440 case XAPIC_OFF_EOI:
4441 case XAPIC_OFF_LDR:
4442 case XAPIC_OFF_DFR:
4443 case XAPIC_OFF_SVR:
4444 case XAPIC_OFF_ESR:
4445 case XAPIC_OFF_ICR_LO:
4446 case XAPIC_OFF_ICR_HI:
4447 case XAPIC_OFF_LVT_TIMER:
4448 case XAPIC_OFF_LVT_THERMAL:
4449 case XAPIC_OFF_LVT_PERF:
4450 case XAPIC_OFF_LVT_LINT0:
4451 case XAPIC_OFF_LVT_LINT1:
4452 case XAPIC_OFF_LVT_ERROR:
4453 case XAPIC_OFF_TIMER_ICR:
4454 case XAPIC_OFF_TIMER_DCR:
4455 break;
4456 default:
4457 return true;
4458 }
4459 }
4460 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4461 {
4462 /*
4463 * With virtual-interrupt delivery, a write access to any of the
4464 * following registers are virtualized. Accessing any other register
4465 * causes a VM-exit.
4466 *
4467 * Note! The specification does not allow writing to offsets in-between
4468 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4469 */
4470 switch (offAccess)
4471 {
4472 case XAPIC_OFF_TPR:
4473 case XAPIC_OFF_EOI:
4474 case XAPIC_OFF_ICR_LO:
4475 break;
4476 default:
4477 return true;
4478 }
4479 }
4480 else
4481 {
4482 /*
4483 * Without APIC-register virtualization or virtual-interrupt delivery,
4484 * only TPR accesses are virtualized.
4485 */
4486 if (offAccess == XAPIC_OFF_TPR)
4487 { /* likely */ }
4488 else
4489 return true;
4490 }
4491 }
4492 else
4493 {
4494 /*
4495 * Check read accesses to the APIC-access page that cause VM-exits.
4496 */
4497 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4498 {
4499 /*
4500 * With APIC-register virtualization, a read access to any of the
4501 * following registers are virtualized. Accessing any other register
4502 * causes a VM-exit.
4503 */
4504 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4505 switch (offAlignedAccess)
4506 {
4507 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4508 case XAPIC_OFF_ID:
4509 case XAPIC_OFF_VERSION:
4510 case XAPIC_OFF_TPR:
4511 case XAPIC_OFF_EOI:
4512 case XAPIC_OFF_LDR:
4513 case XAPIC_OFF_DFR:
4514 case XAPIC_OFF_SVR:
4515 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4516 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4517 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4518 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4519 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4520 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4521 case XAPIC_OFF_ESR:
4522 case XAPIC_OFF_ICR_LO:
4523 case XAPIC_OFF_ICR_HI:
4524 case XAPIC_OFF_LVT_TIMER:
4525 case XAPIC_OFF_LVT_THERMAL:
4526 case XAPIC_OFF_LVT_PERF:
4527 case XAPIC_OFF_LVT_LINT0:
4528 case XAPIC_OFF_LVT_LINT1:
4529 case XAPIC_OFF_LVT_ERROR:
4530 case XAPIC_OFF_TIMER_ICR:
4531 case XAPIC_OFF_TIMER_DCR:
4532 break;
4533 default:
4534 return true;
4535 }
4536 }
4537 else
4538 {
4539 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4540 if (offAccess == XAPIC_OFF_TPR)
4541 { /* likely */ }
4542 else
4543 return true;
4544 }
4545 }
4546
4547 /* The APIC-access is virtualized, does not cause a VM-exit. */
4548 return false;
4549}
4550
4551
4552/**
4553 * Virtualizes a memory-based APIC-access where the address is not used to access
4554 * memory.
4555 *
4556 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4557 * page-faults but do not use the address to access memory.
4558 *
4559 * @param pVCpu The cross context virtual CPU structure.
4560 * @param pGCPhysAccess Pointer to the guest-physical address used.
4561 */
4562IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4563{
4564 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4565 Assert(pVmcs);
4566 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4567 Assert(pGCPhysAccess);
4568
4569 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4570 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4571 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4572
4573 if (GCPhysAccess == GCPhysApic)
4574 {
4575 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4576 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4577 uint16_t const cbAccess = 1;
4578 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4579 if (fIntercept)
4580 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4581
4582 *pGCPhysAccess = GCPhysApic | offAccess;
4583 return VINF_VMX_MODIFIES_BEHAVIOR;
4584 }
4585
4586 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4587}
4588
4589
4590/**
4591 * Virtualizes a memory-based APIC-access.
4592 *
4593 * @returns VBox strict status code.
4594 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4595 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4596 *
4597 * @param pVCpu The cross context virtual CPU structure.
4598 * @param offAccess The offset of the register being accessed (within the
4599 * APIC-access page).
4600 * @param cbAccess The size of the access in bytes.
4601 * @param pvData Pointer to the data being written or where to store the data
4602 * being read.
4603 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4604 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4605 */
4606IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4607 uint32_t fAccess)
4608{
4609 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4610 Assert(pVmcs);
4611 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4612 Assert(pvData);
4613 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4614 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4615 || (fAccess & IEM_ACCESS_INSTRUCTION));
4616
4617 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4618 if (fIntercept)
4619 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4620
4621 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4622 {
4623 /*
4624 * A write access to the APIC-access page that is virtualized (rather than
4625 * causing a VM-exit) writes data to the virtual-APIC page.
4626 */
4627 uint32_t const u32Data = *(uint32_t *)pvData;
4628 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4629
4630 /*
4631 * Record the currently updated APIC offset, as we need this later for figuring
4632 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4633 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4634 *
4635 * After completion of the current operation, we need to perform TPR virtualization,
4636 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4637 *
4638 * The current operation may be a REP-prefixed string instruction, execution of any
4639 * other instruction, or delivery of an event through the IDT.
4640 *
4641 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4642 * performed now but later after completion of the current operation.
4643 *
4644 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4645 */
4646 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4647 }
4648 else
4649 {
4650 /*
4651 * A read access from the APIC-access page that is virtualized (rather than
4652 * causing a VM-exit) returns data from the virtual-APIC page.
4653 *
4654 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4655 */
4656 Assert(cbAccess <= 4);
4657 Assert(offAccess < XAPIC_OFF_END + 4);
4658 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4659
4660 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4661 u32Data &= s_auAccessSizeMasks[cbAccess];
4662 *(uint32_t *)pvData = u32Data;
4663 }
4664
4665 return VINF_VMX_MODIFIES_BEHAVIOR;
4666}
4667
4668
4669/**
4670 * Virtualizes an MSR-based APIC read access.
4671 *
4672 * @returns VBox strict status code.
4673 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4674 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4675 * handled by the x2APIC device.
4676 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4677 * not within the range of valid MSRs, caller must raise \#GP(0).
4678 * @param pVCpu The cross context virtual CPU structure.
4679 * @param idMsr The x2APIC MSR being read.
4680 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4681 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4682 */
4683IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4684{
4685 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4686 Assert(pVmcs);
4687 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4688 Assert(pu64Value);
4689
4690 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4691 {
4692 /*
4693 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4694 * what the end of the valid x2APIC MSR range is. Hence the use of different
4695 * macros here.
4696 *
4697 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4698 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4699 */
4700 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4701 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4702 {
4703 uint16_t const offReg = (idMsr & 0xff) << 4;
4704 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4705 *pu64Value = u64Value;
4706 return VINF_VMX_MODIFIES_BEHAVIOR;
4707 }
4708 return VERR_OUT_OF_RANGE;
4709 }
4710
4711 if (idMsr == MSR_IA32_X2APIC_TPR)
4712 {
4713 uint16_t const offReg = (idMsr & 0xff) << 4;
4714 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4715 *pu64Value = u64Value;
4716 return VINF_VMX_MODIFIES_BEHAVIOR;
4717 }
4718
4719 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4720}
4721
4722
4723/**
4724 * Virtualizes an MSR-based APIC write access.
4725 *
4726 * @returns VBox strict status code.
4727 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4728 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4729 * not within the range of valid MSRs, caller must raise \#GP(0).
4730 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4731 *
4732 * @param pVCpu The cross context virtual CPU structure.
4733 * @param idMsr The x2APIC MSR being written.
4734 * @param u64Value The value of the x2APIC MSR being written.
4735 */
4736IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4737{
4738 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4739 Assert(pVmcs);
4740
4741 /*
4742 * Check if the access is to be virtualized.
4743 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4744 */
4745 if ( idMsr == MSR_IA32_X2APIC_TPR
4746 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4747 && ( idMsr == MSR_IA32_X2APIC_EOI
4748 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4749 {
4750 /* Validate the MSR write depending on the register. */
4751 switch (idMsr)
4752 {
4753 case MSR_IA32_X2APIC_TPR:
4754 case MSR_IA32_X2APIC_SELF_IPI:
4755 {
4756 if (u64Value & UINT64_C(0xffffffffffffff00))
4757 return VERR_OUT_OF_RANGE;
4758 break;
4759 }
4760 case MSR_IA32_X2APIC_EOI:
4761 {
4762 if (u64Value != 0)
4763 return VERR_OUT_OF_RANGE;
4764 break;
4765 }
4766 }
4767
4768 /* Write the MSR to the virtual-APIC page. */
4769 uint16_t const offReg = (idMsr & 0xff) << 4;
4770 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4771
4772 /*
4773 * Record the currently updated APIC offset, as we need this later for figuring
4774 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4775 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4776 */
4777 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4778
4779 return VINF_VMX_MODIFIES_BEHAVIOR;
4780 }
4781
4782 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4783}
4784
4785
4786/**
4787 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4788 *
4789 * @returns VBox status code.
4790 * @retval VINF_SUCCES when the highest set bit is found.
4791 * @retval VERR_NOT_FOUND when no bit is set.
4792 *
4793 * @param pVCpu The cross context virtual CPU structure.
4794 * @param offReg The offset of the APIC 256-bit sparse register.
4795 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4796 * set in the register. Only valid when VINF_SUCCESS is
4797 * returned.
4798 *
4799 * @remarks The format of the 256-bit sparse register here mirrors that found in
4800 * real APIC hardware.
4801 */
4802static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4803{
4804 Assert(offReg < XAPIC_OFF_END + 4);
4805 Assert(pidxHighestBit);
4806
4807 /*
4808 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4809 * However, in each fragment only the first 4 bytes are used.
4810 */
4811 uint8_t const cFrags = 8;
4812 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4813 {
4814 uint16_t const offFrag = iFrag * 16;
4815 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4816 if (!u32Frag)
4817 continue;
4818
4819 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4820 Assert(idxHighestBit > 0);
4821 --idxHighestBit;
4822 Assert(idxHighestBit <= UINT8_MAX);
4823 *pidxHighestBit = idxHighestBit;
4824 return VINF_SUCCESS;
4825 }
4826 return VERR_NOT_FOUND;
4827}
4828
4829
4830/**
4831 * Evaluates pending virtual interrupts.
4832 *
4833 * @param pVCpu The cross context virtual CPU structure.
4834 */
4835IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4836{
4837 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4838 Assert(pVmcs);
4839 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4840
4841 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4842 {
4843 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4844 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4845
4846 if ((uRvi >> 4) > (uPpr >> 4))
4847 {
4848 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4849 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4850 }
4851 else
4852 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4853 }
4854}
4855
4856
4857/**
4858 * Performs PPR virtualization.
4859 *
4860 * @returns VBox strict status code.
4861 * @param pVCpu The cross context virtual CPU structure.
4862 */
4863IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4864{
4865 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4866 Assert(pVmcs);
4867 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4868 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4869
4870 /*
4871 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4872 * or EOI-virtualization.
4873 *
4874 * See Intel spec. 29.1.3 "PPR Virtualization".
4875 */
4876 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4877 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4878
4879 uint32_t uPpr;
4880 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4881 uPpr = uTpr & 0xff;
4882 else
4883 uPpr = uSvi & 0xf0;
4884
4885 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4886 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4887}
4888
4889
4890/**
4891 * Performs VMX TPR virtualization.
4892 *
4893 * @returns VBox strict status code.
4894 * @param pVCpu The cross context virtual CPU structure.
4895 */
4896IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4897{
4898 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4899 Assert(pVmcs);
4900 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4901
4902 /*
4903 * We should have already performed the virtual-APIC write to the TPR offset
4904 * in the virtual-APIC page. We now perform TPR virtualization.
4905 *
4906 * See Intel spec. 29.1.2 "TPR Virtualization".
4907 */
4908 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4909 {
4910 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4911 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4912
4913 /*
4914 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4915 * See Intel spec. 29.1.2 "TPR Virtualization".
4916 */
4917 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4918 {
4919 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4920 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4921 }
4922 }
4923 else
4924 {
4925 iemVmxPprVirtualization(pVCpu);
4926 iemVmxEvalPendingVirtIntrs(pVCpu);
4927 }
4928
4929 return VINF_SUCCESS;
4930}
4931
4932
4933/**
4934 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4935 * not.
4936 *
4937 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4938 * @param pVCpu The cross context virtual CPU structure.
4939 * @param uVector The interrupt that was acknowledged using an EOI.
4940 */
4941IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4942{
4943 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4944 Assert(pVmcs);
4945 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4946
4947 if (uVector < 64)
4948 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4949 if (uVector < 128)
4950 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4951 if (uVector < 192)
4952 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4953 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4954}
4955
4956
4957/**
4958 * Performs EOI virtualization.
4959 *
4960 * @returns VBox strict status code.
4961 * @param pVCpu The cross context virtual CPU structure.
4962 */
4963IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4964{
4965 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4966 Assert(pVmcs);
4967 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4968
4969 /*
4970 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4971 * and get the next guest-interrupt that's in-service (if any).
4972 *
4973 * See Intel spec. 29.1.4 "EOI Virtualization".
4974 */
4975 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4976 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4977 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4978
4979 uint8_t uVector = uSvi;
4980 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4981
4982 uVector = 0;
4983 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4984
4985 if (uVector)
4986 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4987 else
4988 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4989
4990 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4991 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4992
4993 iemVmxPprVirtualization(pVCpu);
4994 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4995 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4996 iemVmxEvalPendingVirtIntrs(pVCpu);
4997 return VINF_SUCCESS;
4998}
4999
5000
5001/**
5002 * Performs self-IPI virtualization.
5003 *
5004 * @returns VBox strict status code.
5005 * @param pVCpu The cross context virtual CPU structure.
5006 */
5007IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5008{
5009 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5010 Assert(pVmcs);
5011 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5012
5013 /*
5014 * We should have already performed the virtual-APIC write to the self-IPI offset
5015 * in the virtual-APIC page. We now perform self-IPI virtualization.
5016 *
5017 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5018 */
5019 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5020 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5021 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
5022 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5023 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5024 if (uVector > uRvi)
5025 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5026 iemVmxEvalPendingVirtIntrs(pVCpu);
5027 return VINF_SUCCESS;
5028}
5029
5030
5031/**
5032 * Performs VMX APIC-write emulation.
5033 *
5034 * @returns VBox strict status code.
5035 * @param pVCpu The cross context virtual CPU structure.
5036 */
5037IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5038{
5039 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5040 Assert(pVmcs);
5041
5042 /*
5043 * Perform APIC-write emulation based on the virtual-APIC register written.
5044 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5045 */
5046 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5047 VBOXSTRICTRC rcStrict;
5048 switch (offApicWrite)
5049 {
5050 case XAPIC_OFF_TPR:
5051 {
5052 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5053 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5054 uTpr &= UINT32_C(0x000000ff);
5055 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5056 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5057 rcStrict = iemVmxTprVirtualization(pVCpu);
5058 break;
5059 }
5060
5061 case XAPIC_OFF_EOI:
5062 {
5063 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5064 {
5065 /* Clear VEOI and perform EOI virtualization. */
5066 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5067 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5068 rcStrict = iemVmxEoiVirtualization(pVCpu);
5069 }
5070 else
5071 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5072 break;
5073 }
5074
5075 case XAPIC_OFF_ICR_LO:
5076 {
5077 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5078 {
5079 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5080 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5081 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5082 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5083 if ( !(uIcrLo & fIcrLoMb0)
5084 && (uIcrLo & fIcrLoMb1))
5085 {
5086 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5087 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5088 }
5089 else
5090 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5091 }
5092 else
5093 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5094 break;
5095 }
5096
5097 case XAPIC_OFF_ICR_HI:
5098 {
5099 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5100 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5101 uIcrHi &= UINT32_C(0xff000000);
5102 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5103 rcStrict = VINF_SUCCESS;
5104 break;
5105 }
5106
5107 default:
5108 {
5109 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5110 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5111 break;
5112 }
5113 }
5114
5115 return rcStrict;
5116}
5117
5118
5119/**
5120 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5121 *
5122 * @param pVCpu The cross context virtual CPU structure.
5123 * @param pszInstr The VMX instruction name (for logging purposes).
5124 */
5125IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5126{
5127 /*
5128 * Guest Control Registers, Debug Registers, and MSRs.
5129 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5130 */
5131 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5132 const char *const pszFailure = "VM-exit";
5133 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5134
5135 /* CR0 reserved bits. */
5136 {
5137 /* CR0 MB1 bits. */
5138 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5139 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5140 if (fUnrestrictedGuest)
5141 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5142 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5143 { /* likely */ }
5144 else
5145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5146
5147 /* CR0 MBZ bits. */
5148 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5149 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5153
5154 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5155 if ( !fUnrestrictedGuest
5156 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5157 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5159 }
5160
5161 /* CR4 reserved bits. */
5162 {
5163 /* CR4 MB1 bits. */
5164 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5165 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5166 { /* likely */ }
5167 else
5168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5169
5170 /* CR4 MBZ bits. */
5171 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5172 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5173 { /* likely */ }
5174 else
5175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5176 }
5177
5178 /* DEBUGCTL MSR. */
5179 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5180 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5181 { /* likely */ }
5182 else
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5184
5185 /* 64-bit CPU checks. */
5186 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5187 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5188 {
5189 if (fGstInLongMode)
5190 {
5191 /* PAE must be set. */
5192 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5193 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5194 { /* likely */ }
5195 else
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5197 }
5198 else
5199 {
5200 /* PCIDE should not be set. */
5201 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5205 }
5206
5207 /* CR3. */
5208 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5209 { /* likely */ }
5210 else
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5212
5213 /* DR7. */
5214 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5215 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5216 { /* likely */ }
5217 else
5218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5219
5220 /* SYSENTER ESP and SYSENTER EIP. */
5221 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5222 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5226 }
5227
5228 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5229 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5230
5231 /* PAT MSR. */
5232 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5233 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5237
5238 /* EFER MSR. */
5239 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5240 {
5241 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5242 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5243 { /* likely */ }
5244 else
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5246
5247 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5248 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5249 if ( fGstLma == fGstInLongMode
5250 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5251 || fGstLma == fGstLme))
5252 { /* likely */ }
5253 else
5254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5255 }
5256
5257 /* We don't support IA32_BNDCFGS MSR yet. */
5258 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5259
5260 NOREF(pszInstr);
5261 NOREF(pszFailure);
5262 return VINF_SUCCESS;
5263}
5264
5265
5266/**
5267 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5268 *
5269 * @param pVCpu The cross context virtual CPU structure.
5270 * @param pszInstr The VMX instruction name (for logging purposes).
5271 */
5272IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5273{
5274 /*
5275 * Segment registers.
5276 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5277 */
5278 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5279 const char *const pszFailure = "VM-exit";
5280 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5281 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5282 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5283
5284 /* Selectors. */
5285 if ( !fGstInV86Mode
5286 && !fUnrestrictedGuest
5287 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5289
5290 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5291 {
5292 CPUMSELREG SelReg;
5293 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5294 if (RT_LIKELY(rc == VINF_SUCCESS))
5295 { /* likely */ }
5296 else
5297 return rc;
5298
5299 /*
5300 * Virtual-8086 mode checks.
5301 */
5302 if (fGstInV86Mode)
5303 {
5304 /* Base address. */
5305 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5306 { /* likely */ }
5307 else
5308 {
5309 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5311 }
5312
5313 /* Limit. */
5314 if (SelReg.u32Limit == 0xffff)
5315 { /* likely */ }
5316 else
5317 {
5318 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5320 }
5321
5322 /* Attribute. */
5323 if (SelReg.Attr.u == 0xf3)
5324 { /* likely */ }
5325 else
5326 {
5327 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5329 }
5330
5331 /* We're done; move to checking the next segment. */
5332 continue;
5333 }
5334
5335 /* Checks done by 64-bit CPUs. */
5336 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5337 {
5338 /* Base address. */
5339 if ( iSegReg == X86_SREG_FS
5340 || iSegReg == X86_SREG_GS)
5341 {
5342 if (X86_IS_CANONICAL(SelReg.u64Base))
5343 { /* likely */ }
5344 else
5345 {
5346 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5347 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5348 }
5349 }
5350 else if (iSegReg == X86_SREG_CS)
5351 {
5352 if (!RT_HI_U32(SelReg.u64Base))
5353 { /* likely */ }
5354 else
5355 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5356 }
5357 else
5358 {
5359 if ( SelReg.Attr.n.u1Unusable
5360 || !RT_HI_U32(SelReg.u64Base))
5361 { /* likely */ }
5362 else
5363 {
5364 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5366 }
5367 }
5368 }
5369
5370 /*
5371 * Checks outside Virtual-8086 mode.
5372 */
5373 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5374 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5375 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5376 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5377 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5378 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5379 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5380 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5381
5382 /* Code or usable segment. */
5383 if ( iSegReg == X86_SREG_CS
5384 || fUsable)
5385 {
5386 /* Reserved bits (bits 31:17 and bits 11:8). */
5387 if (!(SelReg.Attr.u & 0xfffe0f00))
5388 { /* likely */ }
5389 else
5390 {
5391 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5393 }
5394
5395 /* Descriptor type. */
5396 if (fCodeDataSeg)
5397 { /* likely */ }
5398 else
5399 {
5400 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5402 }
5403
5404 /* Present. */
5405 if (fPresent)
5406 { /* likely */ }
5407 else
5408 {
5409 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5411 }
5412
5413 /* Granularity. */
5414 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5415 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5416 { /* likely */ }
5417 else
5418 {
5419 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5421 }
5422 }
5423
5424 if (iSegReg == X86_SREG_CS)
5425 {
5426 /* Segment Type and DPL. */
5427 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5428 && fUnrestrictedGuest)
5429 {
5430 if (uDpl == 0)
5431 { /* likely */ }
5432 else
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5434 }
5435 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5436 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5437 {
5438 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5439 if (uDpl == AttrSs.n.u2Dpl)
5440 { /* likely */ }
5441 else
5442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5443 }
5444 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5445 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5446 {
5447 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5448 if (uDpl <= AttrSs.n.u2Dpl)
5449 { /* likely */ }
5450 else
5451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5452 }
5453 else
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5455
5456 /* Def/Big. */
5457 if ( fGstInLongMode
5458 && fSegLong)
5459 {
5460 if (uDefBig == 0)
5461 { /* likely */ }
5462 else
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5464 }
5465 }
5466 else if (iSegReg == X86_SREG_SS)
5467 {
5468 /* Segment Type. */
5469 if ( !fUsable
5470 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5471 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5472 { /* likely */ }
5473 else
5474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5475
5476 /* DPL. */
5477 if (!fUnrestrictedGuest)
5478 {
5479 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5480 { /* likely */ }
5481 else
5482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5483 }
5484 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5485 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5486 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5487 {
5488 if (uDpl == 0)
5489 { /* likely */ }
5490 else
5491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5492 }
5493 }
5494 else
5495 {
5496 /* DS, ES, FS, GS. */
5497 if (fUsable)
5498 {
5499 /* Segment type. */
5500 if (uSegType & X86_SEL_TYPE_ACCESSED)
5501 { /* likely */ }
5502 else
5503 {
5504 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5506 }
5507
5508 if ( !(uSegType & X86_SEL_TYPE_CODE)
5509 || (uSegType & X86_SEL_TYPE_READ))
5510 { /* likely */ }
5511 else
5512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5513
5514 /* DPL. */
5515 if ( !fUnrestrictedGuest
5516 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5517 {
5518 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5519 { /* likely */ }
5520 else
5521 {
5522 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5524 }
5525 }
5526 }
5527 }
5528 }
5529
5530 /*
5531 * LDTR.
5532 */
5533 {
5534 CPUMSELREG Ldtr;
5535 Ldtr.Sel = pVmcs->GuestLdtr;
5536 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5537 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5538 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5539
5540 if (!Ldtr.Attr.n.u1Unusable)
5541 {
5542 /* Selector. */
5543 if (!(Ldtr.Sel & X86_SEL_LDT))
5544 { /* likely */ }
5545 else
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5547
5548 /* Base. */
5549 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5550 {
5551 if (X86_IS_CANONICAL(Ldtr.u64Base))
5552 { /* likely */ }
5553 else
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5555 }
5556
5557 /* Attributes. */
5558 /* Reserved bits (bits 31:17 and bits 11:8). */
5559 if (!(Ldtr.Attr.u & 0xfffe0f00))
5560 { /* likely */ }
5561 else
5562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5563
5564 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5565 { /* likely */ }
5566 else
5567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5568
5569 if (!Ldtr.Attr.n.u1DescType)
5570 { /* likely */ }
5571 else
5572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5573
5574 if (Ldtr.Attr.n.u1Present)
5575 { /* likely */ }
5576 else
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5578
5579 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5580 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5581 { /* likely */ }
5582 else
5583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5584 }
5585 }
5586
5587 /*
5588 * TR.
5589 */
5590 {
5591 CPUMSELREG Tr;
5592 Tr.Sel = pVmcs->GuestTr;
5593 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5594 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5595 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5596
5597 /* Selector. */
5598 if (!(Tr.Sel & X86_SEL_LDT))
5599 { /* likely */ }
5600 else
5601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5602
5603 /* Base. */
5604 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5605 {
5606 if (X86_IS_CANONICAL(Tr.u64Base))
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5610 }
5611
5612 /* Attributes. */
5613 /* Reserved bits (bits 31:17 and bits 11:8). */
5614 if (!(Tr.Attr.u & 0xfffe0f00))
5615 { /* likely */ }
5616 else
5617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5618
5619 if (!Tr.Attr.n.u1Unusable)
5620 { /* likely */ }
5621 else
5622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5623
5624 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5625 || ( !fGstInLongMode
5626 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5627 { /* likely */ }
5628 else
5629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5630
5631 if (!Tr.Attr.n.u1DescType)
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5635
5636 if (Tr.Attr.n.u1Present)
5637 { /* likely */ }
5638 else
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5640
5641 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5642 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5646 }
5647
5648 NOREF(pszInstr);
5649 NOREF(pszFailure);
5650 return VINF_SUCCESS;
5651}
5652
5653
5654/**
5655 * Checks guest GDTR and IDTR as part of VM-entry.
5656 *
5657 * @param pVCpu The cross context virtual CPU structure.
5658 * @param pszInstr The VMX instruction name (for logging purposes).
5659 */
5660IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5661{
5662 /*
5663 * GDTR and IDTR.
5664 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5665 */
5666 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5667 const char *const pszFailure = "VM-exit";
5668
5669 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5670 {
5671 /* Base. */
5672 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5673 { /* likely */ }
5674 else
5675 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5676
5677 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5678 { /* likely */ }
5679 else
5680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5681 }
5682
5683 /* Limit. */
5684 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5685 { /* likely */ }
5686 else
5687 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5688
5689 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5690 { /* likely */ }
5691 else
5692 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5693
5694 NOREF(pszInstr);
5695 NOREF(pszFailure);
5696 return VINF_SUCCESS;
5697}
5698
5699
5700/**
5701 * Checks guest RIP and RFLAGS as part of VM-entry.
5702 *
5703 * @param pVCpu The cross context virtual CPU structure.
5704 * @param pszInstr The VMX instruction name (for logging purposes).
5705 */
5706IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5707{
5708 /*
5709 * RIP and RFLAGS.
5710 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5711 */
5712 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5713 const char *const pszFailure = "VM-exit";
5714 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5715
5716 /* RIP. */
5717 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5718 {
5719 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5720 if ( !fGstInLongMode
5721 || !AttrCs.n.u1Long)
5722 {
5723 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5724 { /* likely */ }
5725 else
5726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5727 }
5728
5729 if ( fGstInLongMode
5730 && AttrCs.n.u1Long)
5731 {
5732 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5733 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5734 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5735 { /* likely */ }
5736 else
5737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5738 }
5739 }
5740
5741 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5742 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5743 : pVmcs->u64GuestRFlags.s.Lo;
5744 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5745 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5749
5750 if ( fGstInLongMode
5751 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5752 {
5753 if (!(uGuestRFlags & X86_EFL_VM))
5754 { /* likely */ }
5755 else
5756 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5757 }
5758
5759 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5760 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5761 {
5762 if (uGuestRFlags & X86_EFL_IF)
5763 { /* likely */ }
5764 else
5765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5766 }
5767
5768 NOREF(pszInstr);
5769 NOREF(pszFailure);
5770 return VINF_SUCCESS;
5771}
5772
5773
5774/**
5775 * Checks guest non-register state as part of VM-entry.
5776 *
5777 * @param pVCpu The cross context virtual CPU structure.
5778 * @param pszInstr The VMX instruction name (for logging purposes).
5779 */
5780IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5781{
5782 /*
5783 * Guest non-register state.
5784 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5785 */
5786 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5787 const char *const pszFailure = "VM-exit";
5788
5789 /*
5790 * Activity state.
5791 */
5792 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5793 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5794 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5795 { /* likely */ }
5796 else
5797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5798
5799 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5800 if ( !AttrSs.n.u2Dpl
5801 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5805
5806 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5807 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5808 {
5809 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5810 { /* likely */ }
5811 else
5812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5813 }
5814
5815 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5816 {
5817 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5818 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5819 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5820 switch (pVmcs->u32GuestActivityState)
5821 {
5822 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5823 {
5824 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5825 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5826 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5827 && ( uVector == X86_XCPT_DB
5828 || uVector == X86_XCPT_MC))
5829 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5830 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5831 { /* likely */ }
5832 else
5833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5834 break;
5835 }
5836
5837 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5838 {
5839 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5840 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5841 && uVector == X86_XCPT_MC))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5845 break;
5846 }
5847
5848 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5849 default:
5850 break;
5851 }
5852 }
5853
5854 /*
5855 * Interruptibility state.
5856 */
5857 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5858 { /* likely */ }
5859 else
5860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5861
5862 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5863 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5867
5868 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5869 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5873
5874 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5875 {
5876 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5877 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5878 {
5879 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5883 }
5884 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5885 {
5886 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5887 { /* likely */ }
5888 else
5889 {
5890 /*
5891 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5892 * We update the VM-exit qualification only when blocking-by-STI is set
5893 * without blocking-by-MovSS being set. Although in practise it does not
5894 * make much difference since the order of checks are implementation defined.
5895 */
5896 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5897 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5898 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5899 }
5900
5901 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5902 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5903 { /* likely */ }
5904 else
5905 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5906 }
5907 }
5908
5909 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5910 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5911 { /* likely */ }
5912 else
5913 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5914
5915 /* We don't support SGX yet. So enclave-interruption must not be set. */
5916 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5917 { /* likely */ }
5918 else
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5920
5921 /*
5922 * Pending debug exceptions.
5923 */
5924 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5925 ? pVmcs->u64GuestPendingDbgXcpt.u
5926 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5927 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5931
5932 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5933 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5934 {
5935 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5936 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5937 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5938 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5939
5940 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5941 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5942 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5943 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5944 }
5945
5946 /* We don't support RTM (Real-time Transactional Memory) yet. */
5947 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5948 { /* likely */ }
5949 else
5950 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5951
5952 /*
5953 * VMCS link pointer.
5954 */
5955 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5956 {
5957 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5958 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5959 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5960 { /* likely */ }
5961 else
5962 {
5963 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5965 }
5966
5967 /* Validate the address. */
5968 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5969 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5970 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5971 { /* likely */ }
5972 else
5973 {
5974 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5976 }
5977
5978 /* Read the VMCS-link pointer from guest memory. */
5979 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5980 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5981 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5982 if (RT_SUCCESS(rc))
5983 { /* likely */ }
5984 else
5985 {
5986 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5988 }
5989
5990 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5991 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5992 { /* likely */ }
5993 else
5994 {
5995 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5997 }
5998
5999 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6000 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6001 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6002 { /* likely */ }
6003 else
6004 {
6005 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6007 }
6008
6009 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6010 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6011 }
6012
6013 NOREF(pszInstr);
6014 NOREF(pszFailure);
6015 return VINF_SUCCESS;
6016}
6017
6018
6019/**
6020 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6021 * VM-entry.
6022 *
6023 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6024 * @param pVCpu The cross context virtual CPU structure.
6025 * @param pszInstr The VMX instruction name (for logging purposes).
6026 * @param pVmcs Pointer to the virtual VMCS.
6027 */
6028IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6029{
6030 /*
6031 * Check PDPTEs.
6032 * See Intel spec. 4.4.1 "PDPTE Registers".
6033 */
6034 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6035 const char *const pszFailure = "VM-exit";
6036
6037 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6038 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6039 if (RT_SUCCESS(rc))
6040 {
6041 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6042 {
6043 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6044 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6045 { /* likely */ }
6046 else
6047 {
6048 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6049 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6050 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6051 }
6052 }
6053 }
6054 else
6055 {
6056 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6058 }
6059
6060 NOREF(pszFailure);
6061 NOREF(pszInstr);
6062 return rc;
6063}
6064
6065
6066/**
6067 * Checks guest PDPTEs as part of VM-entry.
6068 *
6069 * @param pVCpu The cross context virtual CPU structure.
6070 * @param pszInstr The VMX instruction name (for logging purposes).
6071 */
6072IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6073{
6074 /*
6075 * Guest PDPTEs.
6076 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6077 */
6078 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6079 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6080
6081 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6082 int rc;
6083 if ( !fGstInLongMode
6084 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6085 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6086 {
6087 /*
6088 * We don't support nested-paging for nested-guests yet.
6089 *
6090 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6091 * rather we need to check the PDPTEs referenced by the guest CR3.
6092 */
6093 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6094 }
6095 else
6096 rc = VINF_SUCCESS;
6097 return rc;
6098}
6099
6100
6101/**
6102 * Checks guest-state as part of VM-entry.
6103 *
6104 * @returns VBox status code.
6105 * @param pVCpu The cross context virtual CPU structure.
6106 * @param pszInstr The VMX instruction name (for logging purposes).
6107 */
6108IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6109{
6110 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6111 if (RT_SUCCESS(rc))
6112 {
6113 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6114 if (RT_SUCCESS(rc))
6115 {
6116 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6117 if (RT_SUCCESS(rc))
6118 {
6119 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6120 if (RT_SUCCESS(rc))
6121 {
6122 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6123 if (RT_SUCCESS(rc))
6124 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6125 }
6126 }
6127 }
6128 }
6129 return rc;
6130}
6131
6132
6133/**
6134 * Checks host-state as part of VM-entry.
6135 *
6136 * @returns VBox status code.
6137 * @param pVCpu The cross context virtual CPU structure.
6138 * @param pszInstr The VMX instruction name (for logging purposes).
6139 */
6140IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6141{
6142 /*
6143 * Host Control Registers and MSRs.
6144 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6145 */
6146 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6147 const char * const pszFailure = "VMFail";
6148
6149 /* CR0 reserved bits. */
6150 {
6151 /* CR0 MB1 bits. */
6152 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6153 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6154 { /* likely */ }
6155 else
6156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6157
6158 /* CR0 MBZ bits. */
6159 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6160 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6161 { /* likely */ }
6162 else
6163 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6164 }
6165
6166 /* CR4 reserved bits. */
6167 {
6168 /* CR4 MB1 bits. */
6169 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6170 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6171 { /* likely */ }
6172 else
6173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6174
6175 /* CR4 MBZ bits. */
6176 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6177 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6181 }
6182
6183 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6184 {
6185 /* CR3 reserved bits. */
6186 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6190
6191 /* SYSENTER ESP and SYSENTER EIP. */
6192 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6193 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6194 { /* likely */ }
6195 else
6196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6197 }
6198
6199 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6200 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6201
6202 /* PAT MSR. */
6203 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6204 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6205 { /* likely */ }
6206 else
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6208
6209 /* EFER MSR. */
6210 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6211 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6212 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6213 { /* likely */ }
6214 else
6215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6216
6217 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6218 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6219 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6220 if ( fHostInLongMode == fHostLma
6221 && fHostInLongMode == fHostLme)
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6225
6226 /*
6227 * Host Segment and Descriptor-Table Registers.
6228 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6229 */
6230 /* Selector RPL and TI. */
6231 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6232 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6233 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6234 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6235 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6236 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6237 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6241
6242 /* CS and TR selectors cannot be 0. */
6243 if ( pVmcs->HostCs
6244 && pVmcs->HostTr)
6245 { /* likely */ }
6246 else
6247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6248
6249 /* SS cannot be 0 if 32-bit host. */
6250 if ( fHostInLongMode
6251 || pVmcs->HostSs)
6252 { /* likely */ }
6253 else
6254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6255
6256 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6257 {
6258 /* FS, GS, GDTR, IDTR, TR base address. */
6259 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6260 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6261 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6262 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6263 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6264 { /* likely */ }
6265 else
6266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6267 }
6268
6269 /*
6270 * Host address-space size for 64-bit CPUs.
6271 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6272 */
6273 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6274 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6275 {
6276 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6277
6278 /* Logical processor in IA-32e mode. */
6279 if (fCpuInLongMode)
6280 {
6281 if (fHostInLongMode)
6282 {
6283 /* PAE must be set. */
6284 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6285 { /* likely */ }
6286 else
6287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6288
6289 /* RIP must be canonical. */
6290 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6291 { /* likely */ }
6292 else
6293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6294 }
6295 else
6296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6297 }
6298 else
6299 {
6300 /* Logical processor is outside IA-32e mode. */
6301 if ( !fGstInLongMode
6302 && !fHostInLongMode)
6303 {
6304 /* PCIDE should not be set. */
6305 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6306 { /* likely */ }
6307 else
6308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6309
6310 /* The high 32-bits of RIP MBZ. */
6311 if (!pVmcs->u64HostRip.s.Hi)
6312 { /* likely */ }
6313 else
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6315 }
6316 else
6317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6318 }
6319 }
6320 else
6321 {
6322 /* Host address-space size for 32-bit CPUs. */
6323 if ( !fGstInLongMode
6324 && !fHostInLongMode)
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6328 }
6329
6330 NOREF(pszInstr);
6331 NOREF(pszFailure);
6332 return VINF_SUCCESS;
6333}
6334
6335
6336/**
6337 * Checks VM-entry controls fields as part of VM-entry.
6338 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6339 *
6340 * @returns VBox status code.
6341 * @param pVCpu The cross context virtual CPU structure.
6342 * @param pszInstr The VMX instruction name (for logging purposes).
6343 */
6344IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6345{
6346 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6347 const char * const pszFailure = "VMFail";
6348
6349 /* VM-entry controls. */
6350 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6351 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6352 { /* likely */ }
6353 else
6354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6355
6356 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6360
6361 /* Event injection. */
6362 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6363 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6364 {
6365 /* Type and vector. */
6366 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6367 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6368 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6369 if ( !uRsvd
6370 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6371 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6372 { /* likely */ }
6373 else
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6375
6376 /* Exception error code. */
6377 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6378 {
6379 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6380 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6381 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6382 { /* likely */ }
6383 else
6384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6385
6386 /* Exceptions that provide an error code. */
6387 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6388 && ( uVector == X86_XCPT_DF
6389 || uVector == X86_XCPT_TS
6390 || uVector == X86_XCPT_NP
6391 || uVector == X86_XCPT_SS
6392 || uVector == X86_XCPT_GP
6393 || uVector == X86_XCPT_PF
6394 || uVector == X86_XCPT_AC))
6395 { /* likely */ }
6396 else
6397 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6398
6399 /* Exception error-code reserved bits. */
6400 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6401 { /* likely */ }
6402 else
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6404
6405 /* Injecting a software interrupt, software exception or privileged software exception. */
6406 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6407 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6408 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6409 {
6410 /* Instruction length must be in the range 0-15. */
6411 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6415
6416 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6417 if ( pVmcs->u32EntryInstrLen == 0
6418 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6420 }
6421 }
6422 }
6423
6424 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6425 if (pVmcs->u32EntryMsrLoadCount)
6426 {
6427 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6428 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6429 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6430 { /* likely */ }
6431 else
6432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6433 }
6434
6435 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6436 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6437
6438 NOREF(pszInstr);
6439 NOREF(pszFailure);
6440 return VINF_SUCCESS;
6441}
6442
6443
6444/**
6445 * Checks VM-exit controls fields as part of VM-entry.
6446 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6447 *
6448 * @returns VBox status code.
6449 * @param pVCpu The cross context virtual CPU structure.
6450 * @param pszInstr The VMX instruction name (for logging purposes).
6451 */
6452IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6453{
6454 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6455 const char * const pszFailure = "VMFail";
6456
6457 /* VM-exit controls. */
6458 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6459 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6460 { /* likely */ }
6461 else
6462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6463
6464 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6465 { /* likely */ }
6466 else
6467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6468
6469 /* Save preemption timer without activating it. */
6470 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6471 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6472 { /* likely */ }
6473 else
6474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6475
6476 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6477 if (pVmcs->u32ExitMsrStoreCount)
6478 {
6479 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6480 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6481 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6482 { /* likely */ }
6483 else
6484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6485 }
6486
6487 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6488 if (pVmcs->u32ExitMsrLoadCount)
6489 {
6490 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6491 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6492 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6493 { /* likely */ }
6494 else
6495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6496 }
6497
6498 NOREF(pszInstr);
6499 NOREF(pszFailure);
6500 return VINF_SUCCESS;
6501}
6502
6503
6504/**
6505 * Checks VM-execution controls fields as part of VM-entry.
6506 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6507 *
6508 * @returns VBox status code.
6509 * @param pVCpu The cross context virtual CPU structure.
6510 * @param pszInstr The VMX instruction name (for logging purposes).
6511 *
6512 * @remarks This may update secondary-processor based VM-execution control fields
6513 * in the current VMCS if necessary.
6514 */
6515IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6516{
6517 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6518 const char * const pszFailure = "VMFail";
6519
6520 /* Pin-based VM-execution controls. */
6521 {
6522 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6523 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6524 { /* likely */ }
6525 else
6526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6527
6528 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6529 { /* likely */ }
6530 else
6531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6532 }
6533
6534 /* Processor-based VM-execution controls. */
6535 {
6536 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6537 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6538 { /* likely */ }
6539 else
6540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6541
6542 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6543 { /* likely */ }
6544 else
6545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6546 }
6547
6548 /* Secondary processor-based VM-execution controls. */
6549 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6550 {
6551 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6552 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6553 { /* likely */ }
6554 else
6555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6556
6557 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6558 { /* likely */ }
6559 else
6560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6561 }
6562 else
6563 Assert(!pVmcs->u32ProcCtls2);
6564
6565 /* CR3-target count. */
6566 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6567 { /* likely */ }
6568 else
6569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6570
6571 /* I/O bitmaps physical addresses. */
6572 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6573 {
6574 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6575 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6576 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6577 { /* likely */ }
6578 else
6579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6580
6581 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6582 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6583 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6584 { /* likely */ }
6585 else
6586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6587 }
6588
6589 /* MSR bitmap physical address. */
6590 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6591 {
6592 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6593 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6594 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6595 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6596 { /* likely */ }
6597 else
6598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6599
6600 /* Read the MSR bitmap. */
6601 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6602 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6603 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6604 if (RT_SUCCESS(rc))
6605 { /* likely */ }
6606 else
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6608 }
6609
6610 /* TPR shadow related controls. */
6611 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6612 {
6613 /* Virtual-APIC page physical address. */
6614 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6615 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6616 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6617 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6618 { /* likely */ }
6619 else
6620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6621
6622 /* Read the Virtual-APIC page. */
6623 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6624 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6625 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6626 if (RT_SUCCESS(rc))
6627 { /* likely */ }
6628 else
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6630
6631 /* TPR threshold without virtual-interrupt delivery. */
6632 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6633 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6635
6636 /* TPR threshold and VTPR. */
6637 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6638 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6639 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6640 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6641 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6643 }
6644 else
6645 {
6646 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6647 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6648 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6649 { /* likely */ }
6650 else
6651 {
6652 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6654 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6656 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6658 }
6659 }
6660
6661 /* NMI exiting and virtual-NMIs. */
6662 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6663 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6664 { /* likely */ }
6665 else
6666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6667
6668 /* Virtual-NMIs and NMI-window exiting. */
6669 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6670 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6671 { /* likely */ }
6672 else
6673 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6674
6675 /* Virtualize APIC accesses. */
6676 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6677 {
6678 /* APIC-access physical address. */
6679 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6680 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6681 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6682 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6683 { /* likely */ }
6684 else
6685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6686
6687 /*
6688 * Disallow APIC-access page and virtual-APIC page from being the same address.
6689 * Note! This is not an Intel requirement, but one imposed by our implementation.
6690 */
6691 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6692 * redirecting accesses between the APIC-access page and the virtual-APIC
6693 * page. If any nested hypervisor requires this, we can implement it later. */
6694 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6695 {
6696 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6697 if (GCPhysVirtApic != GCPhysApicAccess)
6698 { /* likely */ }
6699 else
6700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6701 }
6702
6703 /*
6704 * Register the handler for the APIC-access page.
6705 *
6706 * We don't deregister the APIC-access page handler during the VM-exit as a different
6707 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6708 *
6709 * We leave the page registered until the first access that happens outside VMX non-root
6710 * mode. Guest software is allowed to access structures such as the APIC-access page
6711 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6712 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6713 *
6714 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6715 */
6716 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6717 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6718 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6719 if (RT_SUCCESS(rc))
6720 { /* likely */ }
6721 else
6722 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6723 }
6724
6725 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6726 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6727 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6728 { /* likely */ }
6729 else
6730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6731
6732 /* Virtual-interrupt delivery requires external interrupt exiting. */
6733 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6734 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6735 { /* likely */ }
6736 else
6737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6738
6739 /* VPID. */
6740 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6741 || pVmcs->u16Vpid != 0)
6742 { /* likely */ }
6743 else
6744 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6745
6746 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6747 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6748 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6749 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6750 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6751 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6752 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6753
6754 /* VMCS shadowing. */
6755 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6756 {
6757 /* VMREAD-bitmap physical address. */
6758 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6759 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6760 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6761 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6762 { /* likely */ }
6763 else
6764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6765
6766 /* VMWRITE-bitmap physical address. */
6767 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6768 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6769 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6770 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6771 { /* likely */ }
6772 else
6773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6774
6775 /* Read the VMREAD-bitmap. */
6776 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6777 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6778 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6779 if (RT_SUCCESS(rc))
6780 { /* likely */ }
6781 else
6782 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6783
6784 /* Read the VMWRITE-bitmap. */
6785 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6786 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6787 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6788 if (RT_SUCCESS(rc))
6789 { /* likely */ }
6790 else
6791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6792 }
6793
6794 NOREF(pszInstr);
6795 NOREF(pszFailure);
6796 return VINF_SUCCESS;
6797}
6798
6799
6800/**
6801 * Loads the guest control registers, debug register and some MSRs as part of
6802 * VM-entry.
6803 *
6804 * @param pVCpu The cross context virtual CPU structure.
6805 */
6806IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6807{
6808 /*
6809 * Load guest control registers, debug registers and MSRs.
6810 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6811 */
6812 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6813 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6814 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6815 CPUMSetGuestCR0(pVCpu, uGstCr0);
6816 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6817 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6818
6819 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6820 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6821
6822 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6823 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6824 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6825
6826 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6827 {
6828 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6829
6830 /* EFER MSR. */
6831 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6832 {
6833 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6834 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6835 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6836 if (fGstInLongMode)
6837 {
6838 /* If the nested-guest is in long mode, LMA and LME are both set. */
6839 Assert(fGstPaging);
6840 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6841 }
6842 else
6843 {
6844 /*
6845 * If the nested-guest is outside long mode:
6846 * - With paging: LMA is cleared, LME is cleared.
6847 * - Without paging: LMA is cleared, LME is left unmodified.
6848 */
6849 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6850 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6851 }
6852 }
6853 /* else: see below. */
6854 }
6855
6856 /* PAT MSR. */
6857 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6858 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6859
6860 /* EFER MSR. */
6861 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6862 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6863
6864 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6865 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6866
6867 /* We don't support IA32_BNDCFGS MSR yet. */
6868 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6869
6870 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6871}
6872
6873
6874/**
6875 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6876 *
6877 * @param pVCpu The cross context virtual CPU structure.
6878 */
6879IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6880{
6881 /*
6882 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6883 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6884 */
6885 /* CS, SS, ES, DS, FS, GS. */
6886 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6887 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6888 {
6889 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6890 CPUMSELREG VmcsSelReg;
6891 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6892 AssertRC(rc); NOREF(rc);
6893 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6894 {
6895 pGstSelReg->Sel = VmcsSelReg.Sel;
6896 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6897 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6898 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6899 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6900 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6901 }
6902 else
6903 {
6904 pGstSelReg->Sel = VmcsSelReg.Sel;
6905 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6906 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6907 switch (iSegReg)
6908 {
6909 case X86_SREG_CS:
6910 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6911 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6912 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6913 break;
6914
6915 case X86_SREG_SS:
6916 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6917 pGstSelReg->u32Limit = 0;
6918 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6919 break;
6920
6921 case X86_SREG_ES:
6922 case X86_SREG_DS:
6923 pGstSelReg->u64Base = 0;
6924 pGstSelReg->u32Limit = 0;
6925 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6926 break;
6927
6928 case X86_SREG_FS:
6929 case X86_SREG_GS:
6930 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6931 pGstSelReg->u32Limit = 0;
6932 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6933 break;
6934 }
6935 Assert(pGstSelReg->Attr.n.u1Unusable);
6936 }
6937 }
6938
6939 /* LDTR. */
6940 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6941 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6942 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6943 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6944 {
6945 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6946 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6947 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6948 }
6949 else
6950 {
6951 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6952 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6953 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6954 }
6955
6956 /* TR. */
6957 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6958 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6959 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6960 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6961 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6962 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6963 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6964
6965 /* GDTR. */
6966 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6967 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6968
6969 /* IDTR. */
6970 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6971 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6972}
6973
6974
6975/**
6976 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6977 *
6978 * @returns VBox status code.
6979 * @param pVCpu The cross context virtual CPU structure.
6980 * @param pszInstr The VMX instruction name (for logging purposes).
6981 */
6982IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6983{
6984 /*
6985 * Load guest MSRs.
6986 * See Intel spec. 26.4 "Loading MSRs".
6987 */
6988 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6989 const char *const pszFailure = "VM-exit";
6990
6991 /*
6992 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6993 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6994 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6995 */
6996 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6997 if (!cMsrs)
6998 return VINF_SUCCESS;
6999
7000 /*
7001 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7002 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7003 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7004 */
7005 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7006 if (fIsMsrCountValid)
7007 { /* likely */ }
7008 else
7009 {
7010 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7012 }
7013
7014 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
7015 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
7016 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
7017 if (RT_SUCCESS(rc))
7018 {
7019 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
7020 Assert(pMsr);
7021 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7022 {
7023 if ( !pMsr->u32Reserved
7024 && pMsr->u32Msr != MSR_K8_FS_BASE
7025 && pMsr->u32Msr != MSR_K8_GS_BASE
7026 && pMsr->u32Msr != MSR_K6_EFER
7027 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7028 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7029 {
7030 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7031 if (rcStrict == VINF_SUCCESS)
7032 continue;
7033
7034 /*
7035 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7036 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7037 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7038 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7039 * MSR in ring-0 if possible, or come up with a better, generic solution.
7040 */
7041 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7042 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7043 ? kVmxVDiag_Vmentry_MsrLoadRing3
7044 : kVmxVDiag_Vmentry_MsrLoad;
7045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7046 }
7047 else
7048 {
7049 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7050 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7051 }
7052 }
7053 }
7054 else
7055 {
7056 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
7057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7058 }
7059
7060 NOREF(pszInstr);
7061 NOREF(pszFailure);
7062 return VINF_SUCCESS;
7063}
7064
7065
7066/**
7067 * Loads the guest-state non-register state as part of VM-entry.
7068 *
7069 * @returns VBox status code.
7070 * @param pVCpu The cross context virtual CPU structure.
7071 *
7072 * @remarks This must be called only after loading the nested-guest register state
7073 * (especially nested-guest RIP).
7074 */
7075IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7076{
7077 /*
7078 * Load guest non-register state.
7079 * See Intel spec. 26.6 "Special Features of VM Entry"
7080 */
7081 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7082
7083 /*
7084 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7085 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7086 *
7087 * See Intel spec. 26.6.1 "Interruptibility State".
7088 */
7089 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7090 if ( !fEntryVectoring
7091 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7092 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7093 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7094 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7095
7096 /* NMI blocking. */
7097 if ( (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7098 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7099 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7100
7101 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7102
7103 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7104 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7105
7106 /* VPID is irrelevant. We don't support VPID yet. */
7107
7108 /* Clear address-range monitoring. */
7109 EMMonitorWaitClear(pVCpu);
7110}
7111
7112
7113/**
7114 * Loads the guest-state as part of VM-entry.
7115 *
7116 * @returns VBox status code.
7117 * @param pVCpu The cross context virtual CPU structure.
7118 * @param pszInstr The VMX instruction name (for logging purposes).
7119 *
7120 * @remarks This must be done after all the necessary steps prior to loading of
7121 * guest-state (e.g. checking various VMCS state).
7122 */
7123IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7124{
7125 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7126 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7127
7128 /*
7129 * Load guest RIP, RSP and RFLAGS.
7130 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7131 */
7132 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7133 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7134 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7135 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7136
7137 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7138 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7139 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7140
7141 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7142
7143 NOREF(pszInstr);
7144 return VINF_SUCCESS;
7145}
7146
7147
7148/**
7149 * Returns whether there are is a pending debug exception on VM-entry.
7150 *
7151 * @param pVCpu The cross context virtual CPU structure.
7152 * @param pszInstr The VMX instruction name (for logging purposes).
7153 */
7154IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7155{
7156 /*
7157 * Pending debug exceptions.
7158 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7159 */
7160 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7161 Assert(pVmcs);
7162
7163 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7164 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7165 if (fPendingDbgXcpt)
7166 {
7167 uint8_t uEntryIntInfoType;
7168 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7169 if (fEntryVectoring)
7170 {
7171 switch (uEntryIntInfoType)
7172 {
7173 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7174 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7175 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7176 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7177 fPendingDbgXcpt = false;
7178 break;
7179
7180 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7181 {
7182 /*
7183 * Whether the pending debug exception for software exceptions other than
7184 * #BP and #OF is delivered after injecting the exception or is discard
7185 * is CPU implementation specific. We will discard them (easier).
7186 */
7187 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7188 if ( uVector != X86_XCPT_BP
7189 && uVector != X86_XCPT_OF)
7190 fPendingDbgXcpt = false;
7191 RT_FALL_THRU();
7192 }
7193 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7194 {
7195 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7196 fPendingDbgXcpt = false;
7197 break;
7198 }
7199 }
7200 }
7201 else
7202 {
7203 /*
7204 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7205 * pending debug exception is held pending or is discarded is CPU implementation
7206 * specific. We will discard them (easier).
7207 */
7208 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7209 fPendingDbgXcpt = false;
7210
7211 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7212 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7213 fPendingDbgXcpt = false;
7214 }
7215 }
7216
7217 NOREF(pszInstr);
7218 return fPendingDbgXcpt;
7219}
7220
7221
7222/**
7223 * Set up the monitor-trap flag (MTF).
7224 *
7225 * @param pVCpu The cross context virtual CPU structure.
7226 * @param pszInstr The VMX instruction name (for logging purposes).
7227 */
7228IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7229{
7230 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7231 Assert(pVmcs);
7232 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7233 {
7234 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7235 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7236 }
7237 else
7238 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7239 NOREF(pszInstr);
7240}
7241
7242
7243/**
7244 * Set up the VMX-preemption timer.
7245 *
7246 * @param pVCpu The cross context virtual CPU structure.
7247 * @param pszInstr The VMX instruction name (for logging purposes).
7248 */
7249IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7250{
7251 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7252 Assert(pVmcs);
7253 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7254 {
7255 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7256 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7257 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7258
7259 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7260 }
7261 else
7262 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7263
7264 NOREF(pszInstr);
7265}
7266
7267
7268/**
7269 * Injects an event using TRPM given a VM-entry interruption info. and related
7270 * fields.
7271 *
7272 * @returns VBox status code.
7273 * @param pVCpu The cross context virtual CPU structure.
7274 * @param uEntryIntInfo The VM-entry interruption info.
7275 * @param uErrCode The error code associated with the event if any.
7276 * @param cbInstr The VM-entry instruction length (for software
7277 * interrupts and software exceptions). Pass 0
7278 * otherwise.
7279 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7280 */
7281IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7282 RTGCUINTPTR GCPtrFaultAddress)
7283{
7284 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7285
7286 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7287 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7288 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7289
7290 TRPMEVENT enmTrapType;
7291 switch (uType)
7292 {
7293 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7294 enmTrapType = TRPM_HARDWARE_INT;
7295 break;
7296
7297 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7298 enmTrapType = TRPM_SOFTWARE_INT;
7299 break;
7300
7301 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7302 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
7303 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7304 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7305 enmTrapType = TRPM_TRAP;
7306 break;
7307
7308 default:
7309 /* Shouldn't really happen. */
7310 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7311 break;
7312 }
7313
7314 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7315 AssertRCReturn(rc, rc);
7316
7317 if (fErrCodeValid)
7318 TRPMSetErrorCode(pVCpu, uErrCode);
7319
7320 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7321 && uVector == X86_XCPT_PF)
7322 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7323 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7324 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7325 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7326 {
7327 AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7328 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7329 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
7330 TRPMSetInstrLength(pVCpu, cbInstr);
7331 }
7332
7333 return VINF_SUCCESS;
7334}
7335
7336
7337/**
7338 * Performs event injection (if any) as part of VM-entry.
7339 *
7340 * @param pVCpu The cross context virtual CPU structure.
7341 * @param pszInstr The VMX instruction name (for logging purposes).
7342 */
7343IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7344{
7345 /*
7346 * Inject events.
7347 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7348 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7349 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7350 * the actually delivery of this event.
7351 *
7352 * See Intel spec. 26.5 "Event Injection".
7353 */
7354 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7355 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7356 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7357
7358 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7359 if (fEntryIntInfoValid)
7360 {
7361 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7362 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7363 {
7364 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7365 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7366 return VINF_SUCCESS;
7367 }
7368
7369 return iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7370 pVCpu->cpum.GstCtx.cr2);
7371 }
7372
7373 /*
7374 * Inject any pending guest debug exception.
7375 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7376 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7377 */
7378 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7379 if (fPendingDbgXcpt)
7380 {
7381 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7382 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7383 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7384 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7385 0 /* GCPtrFaultAddress */);
7386 }
7387
7388 NOREF(pszInstr);
7389 return VINF_SUCCESS;
7390}
7391
7392
7393/**
7394 * Initializes all read-only VMCS fields as part of VM-entry.
7395 *
7396 * @param pVCpu The cross context virtual CPU structure.
7397 */
7398IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7399{
7400 /*
7401 * Any VMCS field which we do not establish on every VM-exit but may potentially
7402 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7403 * specified to be undefined needs to be initialized here.
7404 *
7405 * Thus, it is especially important to clear the VM-exit qualification field
7406 * since it must be zero for VM-exits where it is not used. Similarly, the
7407 * VM-exit interruption information field's valid bit needs to be cleared for
7408 * the same reasons.
7409 */
7410 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7411 Assert(pVmcs);
7412
7413 /* 16-bit (none currently). */
7414 /* 32-bit. */
7415 pVmcs->u32RoVmInstrError = 0;
7416 pVmcs->u32RoExitReason = 0;
7417 pVmcs->u32RoExitIntInfo = 0;
7418 pVmcs->u32RoExitIntErrCode = 0;
7419 pVmcs->u32RoIdtVectoringInfo = 0;
7420 pVmcs->u32RoIdtVectoringErrCode = 0;
7421 pVmcs->u32RoExitInstrLen = 0;
7422 pVmcs->u32RoExitInstrInfo = 0;
7423
7424 /* 64-bit. */
7425 pVmcs->u64RoGuestPhysAddr.u = 0;
7426
7427 /* Natural-width. */
7428 pVmcs->u64RoExitQual.u = 0;
7429 pVmcs->u64RoIoRcx.u = 0;
7430 pVmcs->u64RoIoRsi.u = 0;
7431 pVmcs->u64RoIoRdi.u = 0;
7432 pVmcs->u64RoIoRip.u = 0;
7433 pVmcs->u64RoGuestLinearAddr.u = 0;
7434}
7435
7436
7437/**
7438 * VMLAUNCH/VMRESUME instruction execution worker.
7439 *
7440 * @returns Strict VBox status code.
7441 * @param pVCpu The cross context virtual CPU structure.
7442 * @param cbInstr The instruction length in bytes.
7443 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7444 * VMXINSTRID_VMRESUME).
7445 *
7446 * @remarks Common VMX instruction checks are already expected to by the caller,
7447 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7448 */
7449IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7450{
7451# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7452 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7453 return VINF_EM_RAW_EMULATE_INSTR;
7454# else
7455 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7456 || uInstrId == VMXINSTRID_VMRESUME);
7457 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7458
7459 /* Nested-guest intercept. */
7460 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7461 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7462
7463 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7464
7465 /* CPL. */
7466 if (pVCpu->iem.s.uCpl == 0)
7467 { /* likely */ }
7468 else
7469 {
7470 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7471 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7472 return iemRaiseGeneralProtectionFault0(pVCpu);
7473 }
7474
7475 /* Current VMCS valid. */
7476 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7477 { /* likely */ }
7478 else
7479 {
7480 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7481 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7482 iemVmxVmFailInvalid(pVCpu);
7483 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7484 return VINF_SUCCESS;
7485 }
7486
7487 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7488 * use block-by-STI here which is not quite correct. */
7489 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7490 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7491 { /* likely */ }
7492 else
7493 {
7494 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7496 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7498 return VINF_SUCCESS;
7499 }
7500
7501 if (uInstrId == VMXINSTRID_VMLAUNCH)
7502 {
7503 /* VMLAUNCH with non-clear VMCS. */
7504 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
7505 { /* likely */ }
7506 else
7507 {
7508 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7509 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7510 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7511 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7512 return VINF_SUCCESS;
7513 }
7514 }
7515 else
7516 {
7517 /* VMRESUME with non-launched VMCS. */
7518 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
7519 { /* likely */ }
7520 else
7521 {
7522 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7523 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7524 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7525 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7526 return VINF_SUCCESS;
7527 }
7528 }
7529
7530 /*
7531 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7532 * while entering VMX non-root mode. We do some of this while checking VM-execution
7533 * controls. The guest hypervisor should not make assumptions and cannot expect
7534 * predictable behavior if changes to these structures are made in guest memory while
7535 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7536 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7537 *
7538 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7539 */
7540 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7541 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7542 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7543 if (RT_SUCCESS(rc))
7544 {
7545 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7546 if (RT_SUCCESS(rc))
7547 {
7548 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7549 if (RT_SUCCESS(rc))
7550 {
7551 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7552 if (RT_SUCCESS(rc))
7553 {
7554 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7555 iemVmxVmentryInitReadOnlyFields(pVCpu);
7556
7557 /*
7558 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7559 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7560 * VM-exit when required.
7561 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7562 */
7563 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7564
7565 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7566 if (RT_SUCCESS(rc))
7567 {
7568 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7569 if (RT_SUCCESS(rc))
7570 {
7571 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7572 if (RT_SUCCESS(rc))
7573 {
7574 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7575
7576 /* VMLAUNCH instruction must update the VMCS launch state. */
7577 if (uInstrId == VMXINSTRID_VMLAUNCH)
7578 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
7579
7580 /* Perform the VMX transition (PGM updates). */
7581 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7582 if (rcStrict == VINF_SUCCESS)
7583 { /* likely */ }
7584 else if (RT_SUCCESS(rcStrict))
7585 {
7586 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7587 VBOXSTRICTRC_VAL(rcStrict)));
7588 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7589 }
7590 else
7591 {
7592 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7593 return rcStrict;
7594 }
7595
7596 /* We've now entered nested-guest execution. */
7597 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7598
7599 /*
7600 * The priority of potential VM-exits during VM-entry is important.
7601 * The priorities of VM-exits and events are listed from highest
7602 * to lowest as follows:
7603 *
7604 * 1. Event injection.
7605 * 2. Trap on task-switch (T flag set in TSS).
7606 * 3. TPR below threshold / APIC-write.
7607 * 4. SMI, INIT.
7608 * 5. MTF exit.
7609 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7610 * 7. VMX-preemption timer.
7611 * 9. NMI-window exit.
7612 * 10. NMI injection.
7613 * 11. Interrupt-window exit.
7614 * 12. Virtual-interrupt injection.
7615 * 13. Interrupt injection.
7616 * 14. Process next instruction (fetch, decode, execute).
7617 */
7618
7619 /* Setup the VMX-preemption timer. */
7620 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7621
7622 /* Setup monitor-trap flag. */
7623 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7624
7625 /* Now that we've switched page tables, we can go ahead and inject any event. */
7626 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7627 if (RT_SUCCESS(rcStrict))
7628 {
7629 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7630 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr, VINF_SUCCESS);
7631 }
7632
7633 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7634 return rcStrict;
7635 }
7636 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7637 }
7638 }
7639 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7640 }
7641
7642 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7643 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7644 return VINF_SUCCESS;
7645 }
7646 }
7647 }
7648
7649 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7651 return VINF_SUCCESS;
7652# endif
7653}
7654
7655
7656/**
7657 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7658 * (causes a VM-exit) or not.
7659 *
7660 * @returns @c true if the instruction is intercepted, @c false otherwise.
7661 * @param pVCpu The cross context virtual CPU structure.
7662 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7663 * VMX_EXIT_WRMSR).
7664 * @param idMsr The MSR.
7665 */
7666IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7667{
7668 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7669 Assert( uExitReason == VMX_EXIT_RDMSR
7670 || uExitReason == VMX_EXIT_WRMSR);
7671
7672 /* Consult the MSR bitmap if the feature is supported. */
7673 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7674 Assert(pVmcs);
7675 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7676 {
7677 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7678 if (uExitReason == VMX_EXIT_RDMSR)
7679 {
7680 VMXMSREXITREAD enmRead;
7681 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7682 NULL /* penmWrite */);
7683 AssertRC(rc);
7684 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7685 return true;
7686 }
7687 else
7688 {
7689 VMXMSREXITWRITE enmWrite;
7690 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7691 &enmWrite);
7692 AssertRC(rc);
7693 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7694 return true;
7695 }
7696 return false;
7697 }
7698
7699 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7700 return true;
7701}
7702
7703
7704/**
7705 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7706 * intercepted (causes a VM-exit) or not.
7707 *
7708 * @returns @c true if the instruction is intercepted, @c false otherwise.
7709 * @param pVCpu The cross context virtual CPU structure.
7710 * @param u64FieldEnc The VMCS field encoding.
7711 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7712 * VMX_EXIT_VMREAD).
7713 */
7714IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7715{
7716 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7717 Assert( uExitReason == VMX_EXIT_VMREAD
7718 || uExitReason == VMX_EXIT_VMWRITE);
7719
7720 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7721 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7722 return true;
7723
7724 /*
7725 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7726 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7727 */
7728 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7729 return true;
7730
7731 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7732 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7733 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7734 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7735 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7736 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7737 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7738 pbBitmap += (u32FieldEnc >> 3);
7739 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7740 return true;
7741
7742 return false;
7743}
7744
7745
7746/**
7747 * VMREAD common (memory/register) instruction execution worker
7748 *
7749 * @returns Strict VBox status code.
7750 * @param pVCpu The cross context virtual CPU structure.
7751 * @param cbInstr The instruction length in bytes.
7752 * @param pu64Dst Where to write the VMCS value (only updated when
7753 * VINF_SUCCESS is returned).
7754 * @param u64FieldEnc The VMCS field encoding.
7755 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7756 * be NULL.
7757 */
7758IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7759 PCVMXVEXITINFO pExitInfo)
7760{
7761 /* Nested-guest intercept. */
7762 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7763 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7764 {
7765 if (pExitInfo)
7766 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7767 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7768 }
7769
7770 /* CPL. */
7771 if (pVCpu->iem.s.uCpl == 0)
7772 { /* likely */ }
7773 else
7774 {
7775 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7776 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7777 return iemRaiseGeneralProtectionFault0(pVCpu);
7778 }
7779
7780 /* VMCS pointer in root mode. */
7781 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7782 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7783 { /* likely */ }
7784 else
7785 {
7786 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7788 iemVmxVmFailInvalid(pVCpu);
7789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7790 return VINF_SUCCESS;
7791 }
7792
7793 /* VMCS-link pointer in non-root mode. */
7794 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7795 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7796 { /* likely */ }
7797 else
7798 {
7799 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7801 iemVmxVmFailInvalid(pVCpu);
7802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7803 return VINF_SUCCESS;
7804 }
7805
7806 /* Supported VMCS field. */
7807 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7808 { /* likely */ }
7809 else
7810 {
7811 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7813 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7814 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7815 return VINF_SUCCESS;
7816 }
7817
7818 /*
7819 * Setup reading from the current or shadow VMCS.
7820 */
7821 uint8_t *pbVmcs;
7822 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7823 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7824 else
7825 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7826 Assert(pbVmcs);
7827
7828 VMXVMCSFIELDENC FieldEnc;
7829 FieldEnc.u = u64FieldEnc;
7830 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7831 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7832 uint8_t const uWidthType = (uWidth << 2) | uType;
7833 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7834 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7835 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7836 Assert(offField < VMX_V_VMCS_SIZE);
7837
7838 /*
7839 * Read the VMCS component based on the field's effective width.
7840 *
7841 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7842 * indicates high bits (little endian).
7843 *
7844 * Note! The caller is responsible to trim the result and update registers
7845 * or memory locations are required. Here we just zero-extend to the largest
7846 * type (i.e. 64-bits).
7847 */
7848 uint8_t *pbField = pbVmcs + offField;
7849 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7850 switch (uEffWidth)
7851 {
7852 case VMX_VMCS_ENC_WIDTH_64BIT:
7853 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7854 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7855 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7856 }
7857 return VINF_SUCCESS;
7858}
7859
7860
7861/**
7862 * VMREAD (64-bit register) instruction execution worker.
7863 *
7864 * @returns Strict VBox status code.
7865 * @param pVCpu The cross context virtual CPU structure.
7866 * @param cbInstr The instruction length in bytes.
7867 * @param pu64Dst Where to store the VMCS field's value.
7868 * @param u64FieldEnc The VMCS field encoding.
7869 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7870 * be NULL.
7871 */
7872IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7873 PCVMXVEXITINFO pExitInfo)
7874{
7875 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7876 if (rcStrict == VINF_SUCCESS)
7877 {
7878 iemVmxVmreadSuccess(pVCpu, cbInstr);
7879 return VINF_SUCCESS;
7880 }
7881
7882 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7883 return rcStrict;
7884}
7885
7886
7887/**
7888 * VMREAD (32-bit register) instruction execution worker.
7889 *
7890 * @returns Strict VBox status code.
7891 * @param pVCpu The cross context virtual CPU structure.
7892 * @param cbInstr The instruction length in bytes.
7893 * @param pu32Dst Where to store the VMCS field's value.
7894 * @param u32FieldEnc The VMCS field encoding.
7895 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7896 * be NULL.
7897 */
7898IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7899 PCVMXVEXITINFO pExitInfo)
7900{
7901 uint64_t u64Dst;
7902 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7903 if (rcStrict == VINF_SUCCESS)
7904 {
7905 *pu32Dst = u64Dst;
7906 iemVmxVmreadSuccess(pVCpu, cbInstr);
7907 return VINF_SUCCESS;
7908 }
7909
7910 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7911 return rcStrict;
7912}
7913
7914
7915/**
7916 * VMREAD (memory) instruction execution worker.
7917 *
7918 * @returns Strict VBox status code.
7919 * @param pVCpu The cross context virtual CPU structure.
7920 * @param cbInstr The instruction length in bytes.
7921 * @param iEffSeg The effective segment register to use with @a u64Val.
7922 * Pass UINT8_MAX if it is a register access.
7923 * @param enmEffAddrMode The effective addressing mode (only used with memory
7924 * operand).
7925 * @param GCPtrDst The guest linear address to store the VMCS field's
7926 * value.
7927 * @param u64FieldEnc The VMCS field encoding.
7928 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7929 * be NULL.
7930 */
7931IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7932 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7933{
7934 uint64_t u64Dst;
7935 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7936 if (rcStrict == VINF_SUCCESS)
7937 {
7938 /*
7939 * Write the VMCS field's value to the location specified in guest-memory.
7940 *
7941 * The pointer size depends on the address size (address-size prefix allowed).
7942 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7943 */
7944 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7945 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7946 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7947
7948 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7949 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7950 else
7951 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7952 if (rcStrict == VINF_SUCCESS)
7953 {
7954 iemVmxVmreadSuccess(pVCpu, cbInstr);
7955 return VINF_SUCCESS;
7956 }
7957
7958 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7959 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7960 return rcStrict;
7961 }
7962
7963 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7964 return rcStrict;
7965}
7966
7967
7968/**
7969 * VMWRITE instruction execution worker.
7970 *
7971 * @returns Strict VBox status code.
7972 * @param pVCpu The cross context virtual CPU structure.
7973 * @param cbInstr The instruction length in bytes.
7974 * @param iEffSeg The effective segment register to use with @a u64Val.
7975 * Pass UINT8_MAX if it is a register access.
7976 * @param enmEffAddrMode The effective addressing mode (only used with memory
7977 * operand).
7978 * @param u64Val The value to write (or guest linear address to the
7979 * value), @a iEffSeg will indicate if it's a memory
7980 * operand.
7981 * @param u64FieldEnc The VMCS field encoding.
7982 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7983 * be NULL.
7984 */
7985IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7986 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7987{
7988 /* Nested-guest intercept. */
7989 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7990 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7991 {
7992 if (pExitInfo)
7993 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7994 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7995 }
7996
7997 /* CPL. */
7998 if (pVCpu->iem.s.uCpl == 0)
7999 { /* likely */ }
8000 else
8001 {
8002 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8003 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8004 return iemRaiseGeneralProtectionFault0(pVCpu);
8005 }
8006
8007 /* VMCS pointer in root mode. */
8008 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8009 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8010 { /* likely */ }
8011 else
8012 {
8013 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8014 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8015 iemVmxVmFailInvalid(pVCpu);
8016 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8017 return VINF_SUCCESS;
8018 }
8019
8020 /* VMCS-link pointer in non-root mode. */
8021 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8022 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8023 { /* likely */ }
8024 else
8025 {
8026 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8028 iemVmxVmFailInvalid(pVCpu);
8029 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8030 return VINF_SUCCESS;
8031 }
8032
8033 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8034 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8035 if (!fIsRegOperand)
8036 {
8037 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8038 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8039 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8040
8041 /* Read the value from the specified guest memory location. */
8042 VBOXSTRICTRC rcStrict;
8043 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8044 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8045 else
8046 {
8047 uint32_t u32Val;
8048 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8049 u64Val = u32Val;
8050 }
8051 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8052 {
8053 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8054 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8055 return rcStrict;
8056 }
8057 }
8058 else
8059 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8060
8061 /* Supported VMCS field. */
8062 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8063 { /* likely */ }
8064 else
8065 {
8066 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8067 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8068 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8069 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8070 return VINF_SUCCESS;
8071 }
8072
8073 /* Read-only VMCS field. */
8074 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8075 if ( !fIsFieldReadOnly
8076 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8077 { /* likely */ }
8078 else
8079 {
8080 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8081 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8082 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8083 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8084 return VINF_SUCCESS;
8085 }
8086
8087 /*
8088 * Setup writing to the current or shadow VMCS.
8089 */
8090 uint8_t *pbVmcs;
8091 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8092 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8093 else
8094 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8095 Assert(pbVmcs);
8096
8097 VMXVMCSFIELDENC FieldEnc;
8098 FieldEnc.u = u64FieldEnc;
8099 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8100 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8101 uint8_t const uWidthType = (uWidth << 2) | uType;
8102 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8103 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8104 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8105 Assert(offField < VMX_V_VMCS_SIZE);
8106
8107 /*
8108 * Write the VMCS component based on the field's effective width.
8109 *
8110 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8111 * indicates high bits (little endian).
8112 */
8113 uint8_t *pbField = pbVmcs + offField;
8114 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8115 switch (uEffWidth)
8116 {
8117 case VMX_VMCS_ENC_WIDTH_64BIT:
8118 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8119 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8120 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8121 }
8122
8123 iemVmxVmSucceed(pVCpu);
8124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8125 return VINF_SUCCESS;
8126}
8127
8128
8129/**
8130 * VMCLEAR instruction execution worker.
8131 *
8132 * @returns Strict VBox status code.
8133 * @param pVCpu The cross context virtual CPU structure.
8134 * @param cbInstr The instruction length in bytes.
8135 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8136 * @param GCPtrVmcs The linear address of the VMCS pointer.
8137 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8138 * be NULL.
8139 *
8140 * @remarks Common VMX instruction checks are already expected to by the caller,
8141 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8142 */
8143IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8144 PCVMXVEXITINFO pExitInfo)
8145{
8146 /* Nested-guest intercept. */
8147 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8148 {
8149 if (pExitInfo)
8150 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8151 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8152 }
8153
8154 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8155
8156 /* CPL. */
8157 if (pVCpu->iem.s.uCpl == 0)
8158 { /* likely */ }
8159 else
8160 {
8161 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8163 return iemRaiseGeneralProtectionFault0(pVCpu);
8164 }
8165
8166 /* Get the VMCS pointer from the location specified by the source memory operand. */
8167 RTGCPHYS GCPhysVmcs;
8168 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8169 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8170 { /* likely */ }
8171 else
8172 {
8173 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8174 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8175 return rcStrict;
8176 }
8177
8178 /* VMCS pointer alignment. */
8179 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8180 { /* likely */ }
8181 else
8182 {
8183 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8185 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8186 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8187 return VINF_SUCCESS;
8188 }
8189
8190 /* VMCS physical-address width limits. */
8191 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8192 { /* likely */ }
8193 else
8194 {
8195 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8196 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8197 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8198 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8199 return VINF_SUCCESS;
8200 }
8201
8202 /* VMCS is not the VMXON region. */
8203 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8204 { /* likely */ }
8205 else
8206 {
8207 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8209 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8210 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8211 return VINF_SUCCESS;
8212 }
8213
8214 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8215 restriction imposed by our implementation. */
8216 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8217 { /* likely */ }
8218 else
8219 {
8220 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8221 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8222 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8223 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8224 return VINF_SUCCESS;
8225 }
8226
8227 /*
8228 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8229 *
8230 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8231 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8232 * to 'clear'.
8233 */
8234 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
8235 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8236 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8237 {
8238 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8239 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8240 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
8241 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8242 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8243 }
8244 else
8245 {
8246 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsStateClear));
8247 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8248 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
8249 if (RT_FAILURE(rcStrict))
8250 return rcStrict;
8251 }
8252
8253 iemVmxVmSucceed(pVCpu);
8254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8255 return VINF_SUCCESS;
8256}
8257
8258
8259/**
8260 * VMPTRST instruction execution worker.
8261 *
8262 * @returns Strict VBox status code.
8263 * @param pVCpu The cross context virtual CPU structure.
8264 * @param cbInstr The instruction length in bytes.
8265 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8266 * @param GCPtrVmcs The linear address of where to store the current VMCS
8267 * pointer.
8268 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8269 * be NULL.
8270 *
8271 * @remarks Common VMX instruction checks are already expected to by the caller,
8272 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8273 */
8274IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8275 PCVMXVEXITINFO pExitInfo)
8276{
8277 /* Nested-guest intercept. */
8278 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8279 {
8280 if (pExitInfo)
8281 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8282 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8283 }
8284
8285 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8286
8287 /* CPL. */
8288 if (pVCpu->iem.s.uCpl == 0)
8289 { /* likely */ }
8290 else
8291 {
8292 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8293 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8294 return iemRaiseGeneralProtectionFault0(pVCpu);
8295 }
8296
8297 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8298 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8299 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8300 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8301 {
8302 iemVmxVmSucceed(pVCpu);
8303 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8304 return rcStrict;
8305 }
8306
8307 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8309 return rcStrict;
8310}
8311
8312
8313/**
8314 * VMPTRLD instruction execution worker.
8315 *
8316 * @returns Strict VBox status code.
8317 * @param pVCpu The cross context virtual CPU structure.
8318 * @param cbInstr The instruction length in bytes.
8319 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8320 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8321 * be NULL.
8322 *
8323 * @remarks Common VMX instruction checks are already expected to by the caller,
8324 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8325 */
8326IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8327 PCVMXVEXITINFO pExitInfo)
8328{
8329 /* Nested-guest intercept. */
8330 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8331 {
8332 if (pExitInfo)
8333 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8334 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8335 }
8336
8337 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8338
8339 /* CPL. */
8340 if (pVCpu->iem.s.uCpl == 0)
8341 { /* likely */ }
8342 else
8343 {
8344 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8345 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8346 return iemRaiseGeneralProtectionFault0(pVCpu);
8347 }
8348
8349 /* Get the VMCS pointer from the location specified by the source memory operand. */
8350 RTGCPHYS GCPhysVmcs;
8351 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8352 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8353 { /* likely */ }
8354 else
8355 {
8356 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8357 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8358 return rcStrict;
8359 }
8360
8361 /* VMCS pointer alignment. */
8362 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8363 { /* likely */ }
8364 else
8365 {
8366 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8368 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8370 return VINF_SUCCESS;
8371 }
8372
8373 /* VMCS physical-address width limits. */
8374 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8375 { /* likely */ }
8376 else
8377 {
8378 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8379 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8380 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8381 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8382 return VINF_SUCCESS;
8383 }
8384
8385 /* VMCS is not the VMXON region. */
8386 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8387 { /* likely */ }
8388 else
8389 {
8390 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8391 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8392 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8393 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8394 return VINF_SUCCESS;
8395 }
8396
8397 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8398 restriction imposed by our implementation. */
8399 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8400 { /* likely */ }
8401 else
8402 {
8403 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8405 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8406 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8407 return VINF_SUCCESS;
8408 }
8409
8410 /* Read just the VMCS revision from the VMCS. */
8411 VMXVMCSREVID VmcsRevId;
8412 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8413 if (RT_SUCCESS(rc))
8414 { /* likely */ }
8415 else
8416 {
8417 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8419 return rc;
8420 }
8421
8422 /*
8423 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8424 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8425 */
8426 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8427 && ( !VmcsRevId.n.fIsShadowVmcs
8428 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8429 { /* likely */ }
8430 else
8431 {
8432 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8433 {
8434 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8435 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8436 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8437 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8438 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8439 return VINF_SUCCESS;
8440 }
8441
8442 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8444 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8445 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8446 return VINF_SUCCESS;
8447 }
8448
8449 /*
8450 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8451 * the cache of an existing, current VMCS back to guest memory before loading a new,
8452 * different current VMCS.
8453 */
8454 bool fLoadVmcsFromMem;
8455 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8456 {
8457 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8458 {
8459 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8460 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8461 fLoadVmcsFromMem = true;
8462 }
8463 else
8464 fLoadVmcsFromMem = false;
8465 }
8466 else
8467 fLoadVmcsFromMem = true;
8468
8469 if (fLoadVmcsFromMem)
8470 {
8471 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8472 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8473 sizeof(VMXVVMCS));
8474 if (RT_SUCCESS(rc))
8475 { /* likely */ }
8476 else
8477 {
8478 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8480 return rc;
8481 }
8482 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8483 }
8484
8485 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8486 iemVmxVmSucceed(pVCpu);
8487 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8488 return VINF_SUCCESS;
8489}
8490
8491
8492/**
8493 * VMXON instruction execution worker.
8494 *
8495 * @returns Strict VBox status code.
8496 * @param pVCpu The cross context virtual CPU structure.
8497 * @param cbInstr The instruction length in bytes.
8498 * @param iEffSeg The effective segment register to use with @a
8499 * GCPtrVmxon.
8500 * @param GCPtrVmxon The linear address of the VMXON pointer.
8501 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8502 * Optional, can be NULL.
8503 *
8504 * @remarks Common VMX instruction checks are already expected to by the caller,
8505 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8506 */
8507IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8508 PCVMXVEXITINFO pExitInfo)
8509{
8510 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8511 {
8512 /* CPL. */
8513 if (pVCpu->iem.s.uCpl == 0)
8514 { /* likely */ }
8515 else
8516 {
8517 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8518 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8519 return iemRaiseGeneralProtectionFault0(pVCpu);
8520 }
8521
8522 /* A20M (A20 Masked) mode. */
8523 if (PGMPhysIsA20Enabled(pVCpu))
8524 { /* likely */ }
8525 else
8526 {
8527 Log(("vmxon: A20M mode -> #GP(0)\n"));
8528 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8529 return iemRaiseGeneralProtectionFault0(pVCpu);
8530 }
8531
8532 /* CR0. */
8533 {
8534 /* CR0 MB1 bits. */
8535 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8536 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8537 { /* likely */ }
8538 else
8539 {
8540 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8541 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8542 return iemRaiseGeneralProtectionFault0(pVCpu);
8543 }
8544
8545 /* CR0 MBZ bits. */
8546 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8547 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8548 { /* likely */ }
8549 else
8550 {
8551 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8552 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8553 return iemRaiseGeneralProtectionFault0(pVCpu);
8554 }
8555 }
8556
8557 /* CR4. */
8558 {
8559 /* CR4 MB1 bits. */
8560 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8561 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8562 { /* likely */ }
8563 else
8564 {
8565 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8566 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8567 return iemRaiseGeneralProtectionFault0(pVCpu);
8568 }
8569
8570 /* CR4 MBZ bits. */
8571 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8572 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8573 { /* likely */ }
8574 else
8575 {
8576 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8578 return iemRaiseGeneralProtectionFault0(pVCpu);
8579 }
8580 }
8581
8582 /* Feature control MSR's LOCK and VMXON bits. */
8583 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8584 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8585 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8586 { /* likely */ }
8587 else
8588 {
8589 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8591 return iemRaiseGeneralProtectionFault0(pVCpu);
8592 }
8593
8594 /* Get the VMXON pointer from the location specified by the source memory operand. */
8595 RTGCPHYS GCPhysVmxon;
8596 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8597 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8598 { /* likely */ }
8599 else
8600 {
8601 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8603 return rcStrict;
8604 }
8605
8606 /* VMXON region pointer alignment. */
8607 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8608 { /* likely */ }
8609 else
8610 {
8611 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8613 iemVmxVmFailInvalid(pVCpu);
8614 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8615 return VINF_SUCCESS;
8616 }
8617
8618 /* VMXON physical-address width limits. */
8619 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8620 { /* likely */ }
8621 else
8622 {
8623 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8624 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8625 iemVmxVmFailInvalid(pVCpu);
8626 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8627 return VINF_SUCCESS;
8628 }
8629
8630 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8631 restriction imposed by our implementation. */
8632 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8633 { /* likely */ }
8634 else
8635 {
8636 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8638 iemVmxVmFailInvalid(pVCpu);
8639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8640 return VINF_SUCCESS;
8641 }
8642
8643 /* Read the VMCS revision ID from the VMXON region. */
8644 VMXVMCSREVID VmcsRevId;
8645 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8646 if (RT_SUCCESS(rc))
8647 { /* likely */ }
8648 else
8649 {
8650 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8652 return rc;
8653 }
8654
8655 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8656 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8657 { /* likely */ }
8658 else
8659 {
8660 /* Revision ID mismatch. */
8661 if (!VmcsRevId.n.fIsShadowVmcs)
8662 {
8663 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8664 VmcsRevId.n.u31RevisionId));
8665 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8666 iemVmxVmFailInvalid(pVCpu);
8667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8668 return VINF_SUCCESS;
8669 }
8670
8671 /* Shadow VMCS disallowed. */
8672 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8673 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8674 iemVmxVmFailInvalid(pVCpu);
8675 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8676 return VINF_SUCCESS;
8677 }
8678
8679 /*
8680 * Record that we're in VMX operation, block INIT, block and disable A20M.
8681 */
8682 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8683 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8684 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8685
8686 /* Clear address-range monitoring. */
8687 EMMonitorWaitClear(pVCpu);
8688 /** @todo NSTVMX: Intel PT. */
8689
8690 iemVmxVmSucceed(pVCpu);
8691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8692 return VINF_SUCCESS;
8693 }
8694 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8695 {
8696 /* Nested-guest intercept. */
8697 if (pExitInfo)
8698 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8699 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8700 }
8701
8702 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8703
8704 /* CPL. */
8705 if (pVCpu->iem.s.uCpl > 0)
8706 {
8707 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8709 return iemRaiseGeneralProtectionFault0(pVCpu);
8710 }
8711
8712 /* VMXON when already in VMX root mode. */
8713 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8714 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8716 return VINF_SUCCESS;
8717}
8718
8719
8720/**
8721 * Implements 'VMXOFF'.
8722 *
8723 * @remarks Common VMX instruction checks are already expected to by the caller,
8724 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8725 */
8726IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8727{
8728 /* Nested-guest intercept. */
8729 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8730 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8731
8732 /* CPL. */
8733 if (pVCpu->iem.s.uCpl == 0)
8734 { /* likely */ }
8735 else
8736 {
8737 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8738 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8739 return iemRaiseGeneralProtectionFault0(pVCpu);
8740 }
8741
8742 /* Dual monitor treatment of SMIs and SMM. */
8743 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8744 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8745 { /* likely */ }
8746 else
8747 {
8748 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8749 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8750 return VINF_SUCCESS;
8751 }
8752
8753 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8755 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8756
8757 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8758 { /** @todo NSTVMX: Unblock SMI. */ }
8759
8760 EMMonitorWaitClear(pVCpu);
8761 /** @todo NSTVMX: Unblock and enable A20M. */
8762
8763 iemVmxVmSucceed(pVCpu);
8764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8765 return VINF_SUCCESS;
8766}
8767
8768
8769/**
8770 * Implements 'VMXON'.
8771 */
8772IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8773{
8774 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8775}
8776
8777
8778/**
8779 * Implements 'VMLAUNCH'.
8780 */
8781IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8782{
8783 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8784}
8785
8786
8787/**
8788 * Implements 'VMRESUME'.
8789 */
8790IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8791{
8792 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8793}
8794
8795
8796/**
8797 * Implements 'VMPTRLD'.
8798 */
8799IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8800{
8801 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8802}
8803
8804
8805/**
8806 * Implements 'VMPTRST'.
8807 */
8808IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8809{
8810 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8811}
8812
8813
8814/**
8815 * Implements 'VMCLEAR'.
8816 */
8817IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8818{
8819 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8820}
8821
8822
8823/**
8824 * Implements 'VMWRITE' register.
8825 */
8826IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8827{
8828 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8829 NULL /* pExitInfo */);
8830}
8831
8832
8833/**
8834 * Implements 'VMWRITE' memory.
8835 */
8836IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8837{
8838 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8839}
8840
8841
8842/**
8843 * Implements 'VMREAD' register (64-bit).
8844 */
8845IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8846{
8847 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8848}
8849
8850
8851/**
8852 * Implements 'VMREAD' register (32-bit).
8853 */
8854IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8855{
8856 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8857}
8858
8859
8860/**
8861 * Implements 'VMREAD' memory, 64-bit register.
8862 */
8863IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8864{
8865 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8866}
8867
8868
8869/**
8870 * Implements 'VMREAD' memory, 32-bit register.
8871 */
8872IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8873{
8874 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8875}
8876
8877
8878/**
8879 * Implements VMX's implementation of PAUSE.
8880 */
8881IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8882{
8883 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8884 {
8885 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8886 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8887 return rcStrict;
8888 }
8889
8890 /*
8891 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8892 * a VM-exit, the instruction operates normally.
8893 */
8894 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8895 return VINF_SUCCESS;
8896}
8897
8898#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8899
8900
8901/**
8902 * Implements 'VMCALL'.
8903 */
8904IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8905{
8906#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8907 /* Nested-guest intercept. */
8908 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8909 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8910#endif
8911
8912 /* Join forces with vmmcall. */
8913 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8914}
8915
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