VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 77548

Last change on this file since 77548 was 77548, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 VM-entry check; current VMCS cannot be a shadow VMCS during VM-entry.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 349.5 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp.h 77548 2019-03-04 05:36:46Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 if (rcSched != VINF_SUCCESS) \
172 iemSetPassUpStatus(pVCpu, rcSched); \
173 return (a_rcStrictRet); \
174 } while (0)
175
176# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
177 do { \
178 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
179 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
180 if (rcSched != VINF_SUCCESS) \
181 iemSetPassUpStatus(pVCpu, rcSched); \
182 return (a_rcStrictRet); \
183 } while (0)
184# else
185# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
186# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
187# endif
188
189
190/*********************************************************************************************************************************
191* Global Variables *
192*********************************************************************************************************************************/
193/** @todo NSTVMX: The following VM-exit intercepts are pending:
194 * VMX_EXIT_IO_SMI
195 * VMX_EXIT_SMI
196 * VMX_EXIT_INT_WINDOW
197 * VMX_EXIT_NMI_WINDOW
198 * VMX_EXIT_GETSEC
199 * VMX_EXIT_RSM
200 * VMX_EXIT_MTF
201 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
202 * VMX_EXIT_ERR_MACHINE_CHECK
203 * VMX_EXIT_TPR_BELOW_THRESHOLD
204 * VMX_EXIT_APIC_ACCESS
205 * VMX_EXIT_VIRTUALIZED_EOI
206 * VMX_EXIT_EPT_VIOLATION
207 * VMX_EXIT_EPT_MISCONFIG
208 * VMX_EXIT_INVEPT
209 * VMX_EXIT_PREEMPT_TIMER
210 * VMX_EXIT_INVVPID
211 * VMX_EXIT_APIC_WRITE
212 * VMX_EXIT_RDRAND
213 * VMX_EXIT_VMFUNC
214 * VMX_EXIT_ENCLS
215 * VMX_EXIT_RDSEED
216 * VMX_EXIT_PML_FULL
217 * VMX_EXIT_XSAVES
218 * VMX_EXIT_XRSTORS
219 */
220/**
221 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
222 *
223 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
224 * second dimension is the Index, see VMXVMCSFIELDENC.
225 */
226uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
227{
228 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
233 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
236 },
237 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
238 {
239 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 24-25 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
253 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
254 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
255 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
256 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
258 },
259 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
268 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
270 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
271 },
272 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
275 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
276 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
277 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
278 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
279 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
280 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
281 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
282 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
283 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
284 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
285 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
286 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
287 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
288 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
289 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
290 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
291 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
292 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
293 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
294 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
295 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
296 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
297 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
298 /* 24 */ UINT16_MAX,
299 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
300 },
301 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
304 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 25 */ UINT16_MAX
308 },
309 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
329 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
330 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
331 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
332 },
333 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
334 {
335 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
336 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
337 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
338 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
339 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
340 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
341 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
342 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
343 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
344 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
345 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
346 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
347 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
348 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
349 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
350 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
351 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
352 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
353 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
354 },
355 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
356 {
357 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
358 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
359 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
360 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
361 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
362 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
363 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
364 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
365 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
366 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
367 /* 24-25 */ UINT16_MAX, UINT16_MAX
368 },
369 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
370 {
371 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
372 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
373 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
374 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
375 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
376 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
377 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
378 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
379 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
380 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
381 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
382 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
383 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
384 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
385 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
386 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
387 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
388 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
389 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
390 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
391 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
392 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
393 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
394 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
395 },
396 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
397 {
398 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
399 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
401 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
402 /* 25 */ UINT16_MAX
403 },
404 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
405 {
406 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
407 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
408 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
409 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
410 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
411 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
412 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
413 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
414 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
415 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
416 /* 24-25 */ UINT16_MAX, UINT16_MAX
417 },
418 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
419 {
420 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
421 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
422 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
423 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
424 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
425 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
426 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
429 },
430 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
431 {
432 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
433 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
434 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
435 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
436 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
437 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
438 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
439 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
440 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
441 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
442 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
443 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
444 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
445 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
446 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
447 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
448 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
449 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
450 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
451 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
452 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 },
454 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
455 {
456 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
457 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
458 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
459 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
460 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
461 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
462 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
463 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
464 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
465 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
466 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
467 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
468 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
469 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
470 }
471};
472
473
474/**
475 * Returns whether the given VMCS field is valid and supported by our emulation.
476 *
477 * @param pVCpu The cross context virtual CPU structure.
478 * @param u64FieldEnc The VMCS field encoding.
479 *
480 * @remarks This takes into account the CPU features exposed to the guest.
481 */
482IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
483{
484 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
485 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
486 if (!uFieldEncHi)
487 { /* likely */ }
488 else
489 return false;
490
491 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
492 switch (uFieldEncLo)
493 {
494 /*
495 * 16-bit fields.
496 */
497 /* Control fields. */
498 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
499 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
500 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
501
502 /* Guest-state fields. */
503 case VMX_VMCS16_GUEST_ES_SEL:
504 case VMX_VMCS16_GUEST_CS_SEL:
505 case VMX_VMCS16_GUEST_SS_SEL:
506 case VMX_VMCS16_GUEST_DS_SEL:
507 case VMX_VMCS16_GUEST_FS_SEL:
508 case VMX_VMCS16_GUEST_GS_SEL:
509 case VMX_VMCS16_GUEST_LDTR_SEL:
510 case VMX_VMCS16_GUEST_TR_SEL: return true;
511 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
512 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
513
514 /* Host-state fields. */
515 case VMX_VMCS16_HOST_ES_SEL:
516 case VMX_VMCS16_HOST_CS_SEL:
517 case VMX_VMCS16_HOST_SS_SEL:
518 case VMX_VMCS16_HOST_DS_SEL:
519 case VMX_VMCS16_HOST_FS_SEL:
520 case VMX_VMCS16_HOST_GS_SEL:
521 case VMX_VMCS16_HOST_TR_SEL: return true;
522
523 /*
524 * 64-bit fields.
525 */
526 /* Control fields. */
527 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
528 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
529 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
530 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
531 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
532 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
533 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
534 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
535 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
536 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
537 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
538 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
539 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
540 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
541 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
542 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
543 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
544 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
545 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
546 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
547 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
548 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
549 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
550 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
551 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
552 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
553 case VMX_VMCS64_CTRL_EPTP_FULL:
554 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
555 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
557 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
558 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
559 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
560 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
561 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
562 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
563 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
564 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
565 {
566 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
567 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
568 }
569 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
571 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
573 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
574 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
575 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
576 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
577 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
578 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
579 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
580 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
581
582 /* Read-only data fields. */
583 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
584 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
585
586 /* Guest-state fields. */
587 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
588 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
589 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
590 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
591 case VMX_VMCS64_GUEST_PAT_FULL:
592 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
593 case VMX_VMCS64_GUEST_EFER_FULL:
594 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
595 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
596 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
597 case VMX_VMCS64_GUEST_PDPTE0_FULL:
598 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
599 case VMX_VMCS64_GUEST_PDPTE1_FULL:
600 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
601 case VMX_VMCS64_GUEST_PDPTE2_FULL:
602 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
603 case VMX_VMCS64_GUEST_PDPTE3_FULL:
604 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
605 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
606 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
607
608 /* Host-state fields. */
609 case VMX_VMCS64_HOST_PAT_FULL:
610 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
611 case VMX_VMCS64_HOST_EFER_FULL:
612 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
613 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
614 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
615
616 /*
617 * 32-bit fields.
618 */
619 /* Control fields. */
620 case VMX_VMCS32_CTRL_PIN_EXEC:
621 case VMX_VMCS32_CTRL_PROC_EXEC:
622 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
623 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
624 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
625 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
626 case VMX_VMCS32_CTRL_EXIT:
627 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
628 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
629 case VMX_VMCS32_CTRL_ENTRY:
630 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
631 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
632 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
633 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
634 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
635 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
636 case VMX_VMCS32_CTRL_PLE_GAP:
637 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
638
639 /* Read-only data fields. */
640 case VMX_VMCS32_RO_VM_INSTR_ERROR:
641 case VMX_VMCS32_RO_EXIT_REASON:
642 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
643 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
644 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
645 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
646 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
647 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
648
649 /* Guest-state fields. */
650 case VMX_VMCS32_GUEST_ES_LIMIT:
651 case VMX_VMCS32_GUEST_CS_LIMIT:
652 case VMX_VMCS32_GUEST_SS_LIMIT:
653 case VMX_VMCS32_GUEST_DS_LIMIT:
654 case VMX_VMCS32_GUEST_FS_LIMIT:
655 case VMX_VMCS32_GUEST_GS_LIMIT:
656 case VMX_VMCS32_GUEST_LDTR_LIMIT:
657 case VMX_VMCS32_GUEST_TR_LIMIT:
658 case VMX_VMCS32_GUEST_GDTR_LIMIT:
659 case VMX_VMCS32_GUEST_IDTR_LIMIT:
660 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
663 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
664 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
665 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
666 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
667 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
668 case VMX_VMCS32_GUEST_INT_STATE:
669 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
670 case VMX_VMCS32_GUEST_SMBASE:
671 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
672 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
673
674 /* Host-state fields. */
675 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
676
677 /*
678 * Natural-width fields.
679 */
680 /* Control fields. */
681 case VMX_VMCS_CTRL_CR0_MASK:
682 case VMX_VMCS_CTRL_CR4_MASK:
683 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
684 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
685 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
686 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
687 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
688 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
689
690 /* Read-only data fields. */
691 case VMX_VMCS_RO_EXIT_QUALIFICATION:
692 case VMX_VMCS_RO_IO_RCX:
693 case VMX_VMCS_RO_IO_RSX:
694 case VMX_VMCS_RO_IO_RDI:
695 case VMX_VMCS_RO_IO_RIP:
696 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
697
698 /* Guest-state fields. */
699 case VMX_VMCS_GUEST_CR0:
700 case VMX_VMCS_GUEST_CR3:
701 case VMX_VMCS_GUEST_CR4:
702 case VMX_VMCS_GUEST_ES_BASE:
703 case VMX_VMCS_GUEST_CS_BASE:
704 case VMX_VMCS_GUEST_SS_BASE:
705 case VMX_VMCS_GUEST_DS_BASE:
706 case VMX_VMCS_GUEST_FS_BASE:
707 case VMX_VMCS_GUEST_GS_BASE:
708 case VMX_VMCS_GUEST_LDTR_BASE:
709 case VMX_VMCS_GUEST_TR_BASE:
710 case VMX_VMCS_GUEST_GDTR_BASE:
711 case VMX_VMCS_GUEST_IDTR_BASE:
712 case VMX_VMCS_GUEST_DR7:
713 case VMX_VMCS_GUEST_RSP:
714 case VMX_VMCS_GUEST_RIP:
715 case VMX_VMCS_GUEST_RFLAGS:
716 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
717 case VMX_VMCS_GUEST_SYSENTER_ESP:
718 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
719
720 /* Host-state fields. */
721 case VMX_VMCS_HOST_CR0:
722 case VMX_VMCS_HOST_CR3:
723 case VMX_VMCS_HOST_CR4:
724 case VMX_VMCS_HOST_FS_BASE:
725 case VMX_VMCS_HOST_GS_BASE:
726 case VMX_VMCS_HOST_TR_BASE:
727 case VMX_VMCS_HOST_GDTR_BASE:
728 case VMX_VMCS_HOST_IDTR_BASE:
729 case VMX_VMCS_HOST_SYSENTER_ESP:
730 case VMX_VMCS_HOST_SYSENTER_EIP:
731 case VMX_VMCS_HOST_RSP:
732 case VMX_VMCS_HOST_RIP: return true;
733 }
734
735 return false;
736}
737
738
739/**
740 * Gets a host selector from the VMCS.
741 *
742 * @param pVmcs Pointer to the virtual VMCS.
743 * @param iSelReg The index of the segment register (X86_SREG_XXX).
744 */
745DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
746{
747 Assert(iSegReg < X86_SREG_COUNT);
748 RTSEL HostSel;
749 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
750 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
751 uint8_t const uWidthType = (uWidth << 2) | uType;
752 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
753 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
754 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
755 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
756 uint8_t const *pbField = pbVmcs + offField;
757 HostSel = *(uint16_t *)pbField;
758 return HostSel;
759}
760
761
762/**
763 * Sets a guest segment register in the VMCS.
764 *
765 * @param pVmcs Pointer to the virtual VMCS.
766 * @param iSegReg The index of the segment register (X86_SREG_XXX).
767 * @param pSelReg Pointer to the segment register.
768 */
769IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
770{
771 Assert(pSelReg);
772 Assert(iSegReg < X86_SREG_COUNT);
773
774 /* Selector. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t *pbField = pbVmcs + offField;
784 *(uint16_t *)pbField = pSelReg->Sel;
785 }
786
787 /* Limit. */
788 {
789 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
790 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
791 uint8_t const uWidthType = (uWidth << 2) | uType;
792 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
793 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
794 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
795 uint8_t *pbVmcs = (uint8_t *)pVmcs;
796 uint8_t *pbField = pbVmcs + offField;
797 *(uint32_t *)pbField = pSelReg->u32Limit;
798 }
799
800 /* Base. */
801 {
802 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
803 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
804 uint8_t const uWidthType = (uWidth << 2) | uType;
805 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
806 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
807 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
808 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
809 uint8_t const *pbField = pbVmcs + offField;
810 *(uint64_t *)pbField = pSelReg->u64Base;
811 }
812
813 /* Attributes. */
814 {
815 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
816 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
817 | X86DESCATTR_UNUSABLE;
818 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
819 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
820 uint8_t const uWidthType = (uWidth << 2) | uType;
821 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
822 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
823 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
824 uint8_t *pbVmcs = (uint8_t *)pVmcs;
825 uint8_t *pbField = pbVmcs + offField;
826 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
827 }
828}
829
830
831/**
832 * Gets a guest segment register from the VMCS.
833 *
834 * @returns VBox status code.
835 * @param pVmcs Pointer to the virtual VMCS.
836 * @param iSegReg The index of the segment register (X86_SREG_XXX).
837 * @param pSelReg Where to store the segment register (only updated when
838 * VINF_SUCCESS is returned).
839 *
840 * @remarks Warning! This does not validate the contents of the retrieved segment
841 * register.
842 */
843IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
844{
845 Assert(pSelReg);
846 Assert(iSegReg < X86_SREG_COUNT);
847
848 /* Selector. */
849 uint16_t u16Sel;
850 {
851 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
852 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
853 uint8_t const uWidthType = (uWidth << 2) | uType;
854 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
855 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
856 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
857 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
858 uint8_t const *pbField = pbVmcs + offField;
859 u16Sel = *(uint16_t *)pbField;
860 }
861
862 /* Limit. */
863 uint32_t u32Limit;
864 {
865 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
866 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
867 uint8_t const uWidthType = (uWidth << 2) | uType;
868 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
869 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
870 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
871 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
872 uint8_t const *pbField = pbVmcs + offField;
873 u32Limit = *(uint32_t *)pbField;
874 }
875
876 /* Base. */
877 uint64_t u64Base;
878 {
879 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
880 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
881 uint8_t const uWidthType = (uWidth << 2) | uType;
882 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
883 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
884 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
885 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
886 uint8_t const *pbField = pbVmcs + offField;
887 u64Base = *(uint64_t *)pbField;
888 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
889 }
890
891 /* Attributes. */
892 uint32_t u32Attr;
893 {
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
898 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 u32Attr = *(uint32_t *)pbField;
903 }
904
905 pSelReg->Sel = u16Sel;
906 pSelReg->ValidSel = u16Sel;
907 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
908 pSelReg->u32Limit = u32Limit;
909 pSelReg->u64Base = u64Base;
910 pSelReg->Attr.u = u32Attr;
911 return VINF_SUCCESS;
912}
913
914
915/**
916 * Gets a CR3 target value from the VMCS.
917 *
918 * @returns VBox status code.
919 * @param pVmcs Pointer to the virtual VMCS.
920 * @param idxCr3Target The index of the CR3-target value to retrieve.
921 * @param puValue Where to store the CR3-target value.
922 */
923IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
924{
925 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
926 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
927 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
928 uint8_t const uWidthType = (uWidth << 2) | uType;
929 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
930 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
931 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
932 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
933 uint8_t const *pbField = pbVmcs + offField;
934 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
935 return uCr3TargetValue;
936}
937
938
939/**
940 * Converts an IEM exception event type to a VMX event type.
941 *
942 * @returns The VMX event type.
943 * @param uVector The interrupt / exception vector.
944 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
945 */
946DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
947{
948 /* Paranoia (callers may use these interchangeably). */
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
956 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
957 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
958 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
959 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
960 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
961
962 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
963 {
964 if (uVector == X86_XCPT_NMI)
965 return VMX_EXIT_INT_INFO_TYPE_NMI;
966 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
967 }
968
969 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
970 {
971 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
972 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
973 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
974 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
975 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
976 }
977
978 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
979 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
980}
981
982
983/**
984 * Sets the VM-exit qualification VMCS field.
985 *
986 * @param pVCpu The cross context virtual CPU structure.
987 * @param uExitQual The VM-exit qualification.
988 */
989DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
990{
991 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
992 pVmcs->u64RoExitQual.u = uExitQual;
993}
994
995
996/**
997 * Sets the VM-exit interruption information field.
998 *
999 * @param pVCpu The cross context virtual CPU structure.
1000 * @param uExitQual The VM-exit interruption information.
1001 */
1002DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1003{
1004 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1005 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1006}
1007
1008
1009/**
1010 * Sets the VM-exit interruption error code.
1011 *
1012 * @param pVCpu The cross context virtual CPU structure.
1013 * @param uErrCode The error code.
1014 */
1015DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1016{
1017 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1018 pVmcs->u32RoExitIntErrCode = uErrCode;
1019}
1020
1021
1022/**
1023 * Sets the IDT-vectoring information field.
1024 *
1025 * @param pVCpu The cross context virtual CPU structure.
1026 * @param uIdtVectorInfo The IDT-vectoring information.
1027 */
1028DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1029{
1030 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1031 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1032}
1033
1034
1035/**
1036 * Sets the IDT-vectoring error code field.
1037 *
1038 * @param pVCpu The cross context virtual CPU structure.
1039 * @param uErrCode The error code.
1040 */
1041DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1042{
1043 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1044 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1045}
1046
1047
1048/**
1049 * Sets the VM-exit guest-linear address VMCS field.
1050 *
1051 * @param pVCpu The cross context virtual CPU structure.
1052 * @param uGuestLinearAddr The VM-exit guest-linear address.
1053 */
1054DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1055{
1056 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1057 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1058}
1059
1060
1061/**
1062 * Sets the VM-exit guest-physical address VMCS field.
1063 *
1064 * @param pVCpu The cross context virtual CPU structure.
1065 * @param uGuestPhysAddr The VM-exit guest-physical address.
1066 */
1067DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1068{
1069 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1070 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1071}
1072
1073
1074/**
1075 * Sets the VM-exit instruction length VMCS field.
1076 *
1077 * @param pVCpu The cross context virtual CPU structure.
1078 * @param cbInstr The VM-exit instruction length in bytes.
1079 *
1080 * @remarks Callers may clear this field to 0. Hence, this function does not check
1081 * the validity of the instruction length.
1082 */
1083DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1084{
1085 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1086 pVmcs->u32RoExitInstrLen = cbInstr;
1087}
1088
1089
1090/**
1091 * Sets the VM-exit instruction info. VMCS field.
1092 *
1093 * @param pVCpu The cross context virtual CPU structure.
1094 * @param uExitInstrInfo The VM-exit instruction information.
1095 */
1096DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1097{
1098 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1099 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1100}
1101
1102
1103/**
1104 * Implements VMSucceed for VMX instruction success.
1105 *
1106 * @param pVCpu The cross context virtual CPU structure.
1107 */
1108DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1109{
1110 return CPUMSetGuestVmxVmSucceed(IEM_GET_CTX(pVCpu));
1111}
1112
1113
1114/**
1115 * Implements VMFailInvalid for VMX instruction failure.
1116 *
1117 * @param pVCpu The cross context virtual CPU structure.
1118 */
1119DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1120{
1121 return CPUMSetGuestVmxVmFailInvalid(IEM_GET_CTX(pVCpu));
1122}
1123
1124
1125/**
1126 * Implements VMFailValid for VMX instruction failure.
1127 *
1128 * @param pVCpu The cross context virtual CPU structure.
1129 * @param enmInsErr The VM instruction error.
1130 */
1131DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1132{
1133 return CPUMSetGuestVmxVmFailValid(IEM_GET_CTX(pVCpu), enmInsErr);
1134}
1135
1136
1137/**
1138 * Implements VMFail for VMX instruction failure.
1139 *
1140 * @param pVCpu The cross context virtual CPU structure.
1141 * @param enmInsErr The VM instruction error.
1142 */
1143DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1144{
1145 return CPUMSetGuestVmxVmFail(IEM_GET_CTX(pVCpu), enmInsErr);
1146}
1147
1148
1149/**
1150 * Checks if the given auto-load/store MSR area count is valid for the
1151 * implementation.
1152 *
1153 * @returns @c true if it's within the valid limit, @c false otherwise.
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param uMsrCount The MSR area count to check.
1156 */
1157DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1158{
1159 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1160 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1161 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1162 if (uMsrCount <= cMaxSupportedMsrs)
1163 return true;
1164 return false;
1165}
1166
1167
1168/**
1169 * Flushes the current VMCS contents back to guest memory.
1170 *
1171 * @returns VBox status code.
1172 * @param pVCpu The cross context virtual CPU structure.
1173 */
1174DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1175{
1176 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1177 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1178 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1179 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1180 return rc;
1181}
1182
1183
1184/**
1185 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1186 *
1187 * @param pVCpu The cross context virtual CPU structure.
1188 */
1189DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1190{
1191 iemVmxVmSucceed(pVCpu);
1192 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1193}
1194
1195
1196/**
1197 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1198 * nested-guest.
1199 *
1200 * @param iSegReg The segment index (X86_SREG_XXX).
1201 */
1202IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1203{
1204 switch (iSegReg)
1205 {
1206 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1207 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1208 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1209 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1210 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1211 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1212 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1213 }
1214}
1215
1216
1217/**
1218 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1219 * nested-guest that is in Virtual-8086 mode.
1220 *
1221 * @param iSegReg The segment index (X86_SREG_XXX).
1222 */
1223IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1224{
1225 switch (iSegReg)
1226 {
1227 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1228 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1229 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1230 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1231 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1232 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1233 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1234 }
1235}
1236
1237
1238/**
1239 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1240 * nested-guest that is in Virtual-8086 mode.
1241 *
1242 * @param iSegReg The segment index (X86_SREG_XXX).
1243 */
1244IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1245{
1246 switch (iSegReg)
1247 {
1248 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1249 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1250 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1251 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1252 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1253 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1254 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1255 }
1256}
1257
1258
1259/**
1260 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1261 * nested-guest that is in Virtual-8086 mode.
1262 *
1263 * @param iSegReg The segment index (X86_SREG_XXX).
1264 */
1265IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1266{
1267 switch (iSegReg)
1268 {
1269 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1270 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1271 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1272 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1273 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1274 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1275 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1276 }
1277}
1278
1279
1280/**
1281 * Gets the instruction diagnostic for segment attributes reserved bits failure
1282 * during VM-entry of a nested-guest.
1283 *
1284 * @param iSegReg The segment index (X86_SREG_XXX).
1285 */
1286IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1287{
1288 switch (iSegReg)
1289 {
1290 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1291 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1292 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1293 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1294 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1295 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1296 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1297 }
1298}
1299
1300
1301/**
1302 * Gets the instruction diagnostic for segment attributes descriptor-type
1303 * (code/segment or system) failure during VM-entry of a nested-guest.
1304 *
1305 * @param iSegReg The segment index (X86_SREG_XXX).
1306 */
1307IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1308{
1309 switch (iSegReg)
1310 {
1311 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1312 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1313 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1314 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1315 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1316 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1317 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1318 }
1319}
1320
1321
1322/**
1323 * Gets the instruction diagnostic for segment attributes descriptor-type
1324 * (code/segment or system) failure during VM-entry of a nested-guest.
1325 *
1326 * @param iSegReg The segment index (X86_SREG_XXX).
1327 */
1328IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1329{
1330 switch (iSegReg)
1331 {
1332 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1333 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1334 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1335 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1336 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1337 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1338 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1339 }
1340}
1341
1342
1343/**
1344 * Gets the instruction diagnostic for segment attribute granularity failure during
1345 * VM-entry of a nested-guest.
1346 *
1347 * @param iSegReg The segment index (X86_SREG_XXX).
1348 */
1349IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1350{
1351 switch (iSegReg)
1352 {
1353 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1354 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1355 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1356 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1357 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1358 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1359 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1360 }
1361}
1362
1363/**
1364 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1365 * VM-entry of a nested-guest.
1366 *
1367 * @param iSegReg The segment index (X86_SREG_XXX).
1368 */
1369IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1370{
1371 switch (iSegReg)
1372 {
1373 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1374 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1375 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1376 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1377 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1378 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1379 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1380 }
1381}
1382
1383
1384/**
1385 * Gets the instruction diagnostic for segment attribute type accessed failure
1386 * during VM-entry of a nested-guest.
1387 *
1388 * @param iSegReg The segment index (X86_SREG_XXX).
1389 */
1390IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1391{
1392 switch (iSegReg)
1393 {
1394 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1395 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1396 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1397 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1398 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1399 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1400 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1401 }
1402}
1403
1404
1405/**
1406 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1407 * failure during VM-entry of a nested-guest.
1408 *
1409 * @param iSegReg The PDPTE entry index.
1410 */
1411IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1412{
1413 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1414 switch (iPdpte)
1415 {
1416 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1417 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1418 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1419 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1420 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1421 }
1422}
1423
1424
1425/**
1426 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1427 * failure during VM-exit of a nested-guest.
1428 *
1429 * @param iSegReg The PDPTE entry index.
1430 */
1431IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1432{
1433 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1434 switch (iPdpte)
1435 {
1436 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1437 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1438 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1439 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1440 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1441 }
1442}
1443
1444
1445/**
1446 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1447 * mask and the read-shadow (CR0/CR4 read).
1448 *
1449 * @returns The masked CR0/CR4.
1450 * @param pVCpu The cross context virtual CPU structure.
1451 * @param iCrReg The control register (either CR0 or CR4).
1452 * @param uGuestCrX The current guest CR0 or guest CR4.
1453 */
1454IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1455{
1456 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1457 Assert(iCrReg == 0 || iCrReg == 4);
1458
1459 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1460 Assert(pVmcs);
1461
1462 /*
1463 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1464 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1465 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1466 *
1467 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1468 */
1469 uint64_t fGstHostMask;
1470 uint64_t fReadShadow;
1471 if (iCrReg == 0)
1472 {
1473 fGstHostMask = pVmcs->u64Cr0Mask.u;
1474 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1475 }
1476 else
1477 {
1478 fGstHostMask = pVmcs->u64Cr4Mask.u;
1479 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1480 }
1481
1482 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1483 return fMaskedCrX;
1484}
1485
1486
1487/**
1488 * Saves the guest control registers, debug registers and some MSRs are part of
1489 * VM-exit.
1490 *
1491 * @param pVCpu The cross context virtual CPU structure.
1492 */
1493IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1494{
1495 /*
1496 * Saves the guest control registers, debug registers and some MSRs.
1497 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1498 */
1499 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1500
1501 /* Save control registers. */
1502 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1503 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1504 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1505
1506 /* Save SYSENTER CS, ESP, EIP. */
1507 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1508 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1509 {
1510 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1511 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1512 }
1513 else
1514 {
1515 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1516 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1517 }
1518
1519 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1520 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1521 {
1522 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1523 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1524 }
1525
1526 /* Save PAT MSR. */
1527 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1528 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1529
1530 /* Save EFER MSR. */
1531 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1532 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1533
1534 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1535 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1536
1537 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1538}
1539
1540
1541/**
1542 * Saves the guest force-flags in preparation of entering the nested-guest.
1543 *
1544 * @param pVCpu The cross context virtual CPU structure.
1545 */
1546IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1547{
1548 /* We shouldn't be called multiple times during VM-entry. */
1549 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1550
1551 /* MTF should not be set outside VMX non-root mode. */
1552 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1553
1554 /*
1555 * Preserve the required force-flags.
1556 *
1557 * We cache and clear force-flags that would affect the execution of the
1558 * nested-guest. Cached flags are then restored while returning to the guest
1559 * if necessary.
1560 *
1561 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1562 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1563 * instruction. Interrupt inhibition for any nested-guest instruction
1564 * is supplied by the guest-interruptibility state VMCS field and will
1565 * be set up as part of loading the guest state.
1566 *
1567 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1568 * successful VM-entry (due to invalid guest-state) need to continue
1569 * blocking NMIs if it was in effect before VM-entry.
1570 *
1571 * - MTF need not be preserved as it's used only in VMX non-root mode and
1572 * is supplied through the VM-execution controls.
1573 *
1574 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1575 * we will be able to generate interrupts that may cause VM-exits for
1576 * the nested-guest.
1577 */
1578 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1579}
1580
1581
1582/**
1583 * Restores the guest force-flags in preparation of exiting the nested-guest.
1584 *
1585 * @param pVCpu The cross context virtual CPU structure.
1586 */
1587IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1588{
1589 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1590 {
1591 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1592 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1593 }
1594}
1595
1596
1597/**
1598 * Perform a VMX transition updated PGM, IEM and CPUM.
1599 *
1600 * @param pVCpu The cross context virtual CPU structure.
1601 */
1602IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1603{
1604 /*
1605 * Inform PGM about paging mode changes.
1606 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1607 * see comment in iemMemPageTranslateAndCheckAccess().
1608 */
1609 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1610# ifdef IN_RING3
1611 Assert(rc != VINF_PGM_CHANGE_MODE);
1612# endif
1613 AssertRCReturn(rc, rc);
1614
1615 /* Inform CPUM (recompiler), can later be removed. */
1616 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1617
1618 /*
1619 * Flush the TLB with new CR3. This is required in case the PGM mode change
1620 * above doesn't actually change anything.
1621 */
1622 if (rc == VINF_SUCCESS)
1623 {
1624 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1625 AssertRCReturn(rc, rc);
1626 }
1627
1628 /* Re-initialize IEM cache/state after the drastic mode switch. */
1629 iemReInitExec(pVCpu);
1630 return rc;
1631}
1632
1633
1634/**
1635 * Calculates the current VMX-preemption timer value.
1636 *
1637 * @param pVCpu The cross context virtual CPU structure.
1638 */
1639IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1640{
1641 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1642 Assert(pVmcs);
1643
1644 /*
1645 * Assume the following:
1646 * PreemptTimerShift = 5
1647 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1648 * VmentryTick = 50000 (TSC at time of VM-entry)
1649 *
1650 * CurTick Delta PreemptTimerVal
1651 * ----------------------------------
1652 * 60000 10000 2
1653 * 80000 30000 1
1654 * 90000 40000 0 -> VM-exit.
1655 *
1656 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1657 * The saved VMX-preemption timer value is calculated as follows:
1658 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1659 * E.g.:
1660 * Delta = 10000
1661 * Tmp = 10000 / (2 * 10000) = 0.5
1662 * NewPt = 2 - 0.5 = 2
1663 * Delta = 30000
1664 * Tmp = 30000 / (2 * 10000) = 1.5
1665 * NewPt = 2 - 1.5 = 1
1666 * Delta = 40000
1667 * Tmp = 40000 / 20000 = 2
1668 * NewPt = 2 - 2 = 0
1669 */
1670 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1671 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1672 uint64_t const uDelta = uCurTick - uVmentryTick;
1673 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1674 uint32_t const uPreemptTimer = uVmcsPreemptVal
1675 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1676 return uPreemptTimer;
1677}
1678
1679
1680/**
1681 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1682 *
1683 * @param pVCpu The cross context virtual CPU structure.
1684 */
1685IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1686{
1687 /*
1688 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1689 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1690 */
1691 /* CS, SS, ES, DS, FS, GS. */
1692 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1693 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1694 {
1695 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1696 if (!pSelReg->Attr.n.u1Unusable)
1697 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1698 else
1699 {
1700 /*
1701 * For unusable segments the attributes are undefined except for CS and SS.
1702 * For the rest we don't bother preserving anything but the unusable bit.
1703 */
1704 switch (iSegReg)
1705 {
1706 case X86_SREG_CS:
1707 pVmcs->GuestCs = pSelReg->Sel;
1708 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1709 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1710 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1711 | X86DESCATTR_UNUSABLE);
1712 break;
1713
1714 case X86_SREG_SS:
1715 pVmcs->GuestSs = pSelReg->Sel;
1716 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1717 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1718 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1719 break;
1720
1721 case X86_SREG_DS:
1722 pVmcs->GuestDs = pSelReg->Sel;
1723 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1724 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1725 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1726 break;
1727
1728 case X86_SREG_ES:
1729 pVmcs->GuestEs = pSelReg->Sel;
1730 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1731 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1732 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1733 break;
1734
1735 case X86_SREG_FS:
1736 pVmcs->GuestFs = pSelReg->Sel;
1737 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1738 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1739 break;
1740
1741 case X86_SREG_GS:
1742 pVmcs->GuestGs = pSelReg->Sel;
1743 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1744 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1745 break;
1746 }
1747 }
1748 }
1749
1750 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1751 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1752 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1753 | X86DESCATTR_UNUSABLE;
1754 /* LDTR. */
1755 {
1756 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1757 pVmcs->GuestLdtr = pSelReg->Sel;
1758 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1759 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1760 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1761 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1762 }
1763
1764 /* TR. */
1765 {
1766 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1767 pVmcs->GuestTr = pSelReg->Sel;
1768 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1769 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1770 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1771 }
1772
1773 /* GDTR. */
1774 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1775 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1776
1777 /* IDTR. */
1778 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1779 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1780}
1781
1782
1783/**
1784 * Saves guest non-register state as part of VM-exit.
1785 *
1786 * @param pVCpu The cross context virtual CPU structure.
1787 * @param uExitReason The VM-exit reason.
1788 */
1789IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1790{
1791 /*
1792 * Save guest non-register state.
1793 * See Intel spec. 27.3.4 "Saving Non-Register State".
1794 */
1795 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1796
1797 /*
1798 * Activity state.
1799 * Most VM-exits will occur in the active state. However, if the first instruction
1800 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1801 * the VM-exit will be from the HLT activity state.
1802 *
1803 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1804 */
1805 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1806 * not? */
1807 EMSTATE enmActivityState = EMGetState(pVCpu);
1808 switch (enmActivityState)
1809 {
1810 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1811 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1812 }
1813
1814 /* Interruptibility-state. */
1815 pVmcs->u32GuestIntrState = 0;
1816 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1817 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1818
1819 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1820 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1821 {
1822 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1823 * currently. */
1824 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1825 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1826 }
1827 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1828
1829 /*
1830 * Pending debug exceptions.
1831 */
1832 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1833 && uExitReason != VMX_EXIT_SMI
1834 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1835 && !HMVmxIsVmexitTrapLike(uExitReason))
1836 {
1837 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1838 * block-by-MovSS is in effect. */
1839 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1840 }
1841 else
1842 {
1843 /*
1844 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1845 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1846 *
1847 * See Intel spec. 24.4.2 "Guest Non-Register State".
1848 */
1849 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1850 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1851 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1852 if (fPendingDbgMask & fBpHitMask)
1853 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1854 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1855 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1856 }
1857
1858 /*
1859 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1860 *
1861 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1862 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1863 */
1864 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1865 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1866 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1867
1868 /* PDPTEs. */
1869 /* We don't support EPT yet. */
1870 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1871 pVmcs->u64GuestPdpte0.u = 0;
1872 pVmcs->u64GuestPdpte1.u = 0;
1873 pVmcs->u64GuestPdpte2.u = 0;
1874 pVmcs->u64GuestPdpte3.u = 0;
1875}
1876
1877
1878/**
1879 * Saves the guest-state as part of VM-exit.
1880 *
1881 * @returns VBox status code.
1882 * @param pVCpu The cross context virtual CPU structure.
1883 * @param uExitReason The VM-exit reason.
1884 */
1885IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1886{
1887 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1888 Assert(pVmcs);
1889
1890 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1891 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1892
1893 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1894 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1895 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1896
1897 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1898}
1899
1900
1901/**
1902 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1903 *
1904 * @returns VBox status code.
1905 * @param pVCpu The cross context virtual CPU structure.
1906 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1907 */
1908IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1909{
1910 /*
1911 * Save guest MSRs.
1912 * See Intel spec. 27.4 "Saving MSRs".
1913 */
1914 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1915 const char *const pszFailure = "VMX-abort";
1916
1917 /*
1918 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1919 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1920 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1921 */
1922 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1923 if (!cMsrs)
1924 return VINF_SUCCESS;
1925
1926 /*
1927 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1928 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1929 * implementation causes a VMX-abort followed by a triple-fault.
1930 */
1931 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1932 if (fIsMsrCountValid)
1933 { /* likely */ }
1934 else
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1936
1937 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1938 Assert(pMsr);
1939 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1940 {
1941 if ( !pMsr->u32Reserved
1942 && pMsr->u32Msr != MSR_IA32_SMBASE
1943 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1944 {
1945 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1946 if (rcStrict == VINF_SUCCESS)
1947 continue;
1948
1949 /*
1950 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1951 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1952 * recording the MSR index in the auxiliary info. field and indicated further by our
1953 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1954 * if possible, or come up with a better, generic solution.
1955 */
1956 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1957 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1958 ? kVmxVDiag_Vmexit_MsrStoreRing3
1959 : kVmxVDiag_Vmexit_MsrStore;
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1961 }
1962 else
1963 {
1964 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1965 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1966 }
1967 }
1968
1969 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
1970 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
1971 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
1972 if (RT_SUCCESS(rc))
1973 { /* likely */ }
1974 else
1975 {
1976 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
1977 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1978 }
1979
1980 NOREF(uExitReason);
1981 NOREF(pszFailure);
1982 return VINF_SUCCESS;
1983}
1984
1985
1986/**
1987 * Performs a VMX abort (due to an fatal error during VM-exit).
1988 *
1989 * @returns Strict VBox status code.
1990 * @param pVCpu The cross context virtual CPU structure.
1991 * @param enmAbort The VMX abort reason.
1992 */
1993IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1994{
1995 /*
1996 * Perform the VMX abort.
1997 * See Intel spec. 27.7 "VMX Aborts".
1998 */
1999 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
2000
2001 /* We don't support SMX yet. */
2002 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2003 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2004 {
2005 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2006 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2007 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2008 }
2009
2010 return VINF_EM_TRIPLE_FAULT;
2011}
2012
2013
2014/**
2015 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2016 *
2017 * @param pVCpu The cross context virtual CPU structure.
2018 */
2019IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2020{
2021 /*
2022 * Load host control registers, debug registers and MSRs.
2023 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2024 */
2025 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2026 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2027
2028 /* CR0. */
2029 {
2030 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2031 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2032 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2033 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2034 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2035 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2036 CPUMSetGuestCR0(pVCpu, uValidCr0);
2037 }
2038
2039 /* CR4. */
2040 {
2041 /* CR4 MB1 bits are not modified. */
2042 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2043 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2044 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2045 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2046 if (fHostInLongMode)
2047 uValidCr4 |= X86_CR4_PAE;
2048 else
2049 uValidCr4 &= ~X86_CR4_PCIDE;
2050 CPUMSetGuestCR4(pVCpu, uValidCr4);
2051 }
2052
2053 /* CR3 (host value validated while checking host-state during VM-entry). */
2054 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2055
2056 /* DR7. */
2057 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2058
2059 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2060
2061 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2062 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2063 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2064 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2065
2066 /* FS, GS bases are loaded later while we load host segment registers. */
2067
2068 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2069 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2070 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2071 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2072 {
2073 if (fHostInLongMode)
2074 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2075 else
2076 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2077 }
2078
2079 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2080
2081 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2082 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2083 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2084
2085 /* We don't support IA32_BNDCFGS MSR yet. */
2086}
2087
2088
2089/**
2090 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2091 *
2092 * @param pVCpu The cross context virtual CPU structure.
2093 */
2094IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2095{
2096 /*
2097 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2098 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2099 *
2100 * Warning! Be careful to not touch fields that are reserved by VT-x,
2101 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2102 */
2103 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2104 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2105
2106 /* CS, SS, ES, DS, FS, GS. */
2107 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2108 {
2109 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2110 bool const fUnusable = RT_BOOL(HostSel == 0);
2111 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2112
2113 /* Selector. */
2114 pSelReg->Sel = HostSel;
2115 pSelReg->ValidSel = HostSel;
2116 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2117
2118 /* Limit. */
2119 pSelReg->u32Limit = 0xffffffff;
2120
2121 /* Base. */
2122 pSelReg->u64Base = 0;
2123
2124 /* Attributes. */
2125 if (iSegReg == X86_SREG_CS)
2126 {
2127 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2128 pSelReg->Attr.n.u1DescType = 1;
2129 pSelReg->Attr.n.u2Dpl = 0;
2130 pSelReg->Attr.n.u1Present = 1;
2131 pSelReg->Attr.n.u1Long = fHostInLongMode;
2132 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2133 pSelReg->Attr.n.u1Granularity = 1;
2134 Assert(!pSelReg->Attr.n.u1Unusable);
2135 Assert(!fUnusable);
2136 }
2137 else
2138 {
2139 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2140 pSelReg->Attr.n.u1DescType = 1;
2141 pSelReg->Attr.n.u2Dpl = 0;
2142 pSelReg->Attr.n.u1Present = 1;
2143 pSelReg->Attr.n.u1DefBig = 1;
2144 pSelReg->Attr.n.u1Granularity = 1;
2145 pSelReg->Attr.n.u1Unusable = fUnusable;
2146 }
2147 }
2148
2149 /* FS base. */
2150 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2151 || fHostInLongMode)
2152 {
2153 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2154 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2155 }
2156
2157 /* GS base. */
2158 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2159 || fHostInLongMode)
2160 {
2161 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2162 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2163 }
2164
2165 /* TR. */
2166 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2167 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2168 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2169 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2170 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2171 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2172 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2173 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2174 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2175 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2176 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2177 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2178 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2179
2180 /* LDTR (Warning! do not touch the base and limits here). */
2181 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2182 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2183 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2184 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2185
2186 /* GDTR. */
2187 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2188 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2189 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2190
2191 /* IDTR.*/
2192 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2193 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2194 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2195}
2196
2197
2198/**
2199 * Checks host PDPTes as part of VM-exit.
2200 *
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param uExitReason The VM-exit reason (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Check host PDPTEs.
2208 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2213
2214 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2215 && !fHostInLongMode)
2216 {
2217 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2218 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2219 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2220 if (RT_SUCCESS(rc))
2221 {
2222 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2223 {
2224 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2225 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2226 { /* likely */ }
2227 else
2228 {
2229 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2230 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2231 }
2232 }
2233 }
2234 else
2235 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2236 }
2237
2238 NOREF(pszFailure);
2239 NOREF(uExitReason);
2240 return VINF_SUCCESS;
2241}
2242
2243
2244/**
2245 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2246 *
2247 * @returns VBox status code.
2248 * @param pVCpu The cross context virtual CPU structure.
2249 * @param pszInstr The VMX instruction name (for logging purposes).
2250 */
2251IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2252{
2253 /*
2254 * Load host MSRs.
2255 * See Intel spec. 27.6 "Loading MSRs".
2256 */
2257 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2258 const char *const pszFailure = "VMX-abort";
2259
2260 /*
2261 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2262 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2263 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2264 */
2265 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2266 if (!cMsrs)
2267 return VINF_SUCCESS;
2268
2269 /*
2270 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2271 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2272 * implementation causes a VMX-abort followed by a triple-fault.
2273 */
2274 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2275 if (fIsMsrCountValid)
2276 { /* likely */ }
2277 else
2278 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2279
2280 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2281 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2282 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2283 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2284 if (RT_SUCCESS(rc))
2285 {
2286 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2287 Assert(pMsr);
2288 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2289 {
2290 if ( !pMsr->u32Reserved
2291 && pMsr->u32Msr != MSR_K8_FS_BASE
2292 && pMsr->u32Msr != MSR_K8_GS_BASE
2293 && pMsr->u32Msr != MSR_K6_EFER
2294 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2295 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2296 {
2297 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2298 if (rcStrict == VINF_SUCCESS)
2299 continue;
2300
2301 /*
2302 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2303 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2304 * recording the MSR index in the auxiliary info. field and indicated further by our
2305 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2306 * if possible, or come up with a better, generic solution.
2307 */
2308 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2309 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2310 ? kVmxVDiag_Vmexit_MsrLoadRing3
2311 : kVmxVDiag_Vmexit_MsrLoad;
2312 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2313 }
2314 else
2315 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2316 }
2317 }
2318 else
2319 {
2320 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2321 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2322 }
2323
2324 NOREF(uExitReason);
2325 NOREF(pszFailure);
2326 return VINF_SUCCESS;
2327}
2328
2329
2330/**
2331 * Loads the host state as part of VM-exit.
2332 *
2333 * @returns Strict VBox status code.
2334 * @param pVCpu The cross context virtual CPU structure.
2335 * @param uExitReason The VM-exit reason (for logging purposes).
2336 */
2337IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2338{
2339 /*
2340 * Load host state.
2341 * See Intel spec. 27.5 "Loading Host State".
2342 */
2343 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2344 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2345
2346 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2347 if ( CPUMIsGuestInLongMode(pVCpu)
2348 && !fHostInLongMode)
2349 {
2350 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2351 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2352 }
2353
2354 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2355 iemVmxVmexitLoadHostSegRegs(pVCpu);
2356
2357 /*
2358 * Load host RIP, RSP and RFLAGS.
2359 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2360 */
2361 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2362 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2363 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2364
2365 /* Clear address range monitoring. */
2366 EMMonitorWaitClear(pVCpu);
2367
2368 /* Perform the VMX transition (PGM updates). */
2369 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2370 if (rcStrict == VINF_SUCCESS)
2371 {
2372 /* Check host PDPTEs (only when we've fully switched page tables_. */
2373 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2374 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2375 if (RT_FAILURE(rc))
2376 {
2377 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2378 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2379 }
2380 }
2381 else if (RT_SUCCESS(rcStrict))
2382 {
2383 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2384 uExitReason));
2385 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2386 }
2387 else
2388 {
2389 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2390 return VBOXSTRICTRC_VAL(rcStrict);
2391 }
2392
2393 Assert(rcStrict == VINF_SUCCESS);
2394
2395 /* Load MSRs from the VM-exit auto-load MSR area. */
2396 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2397 if (RT_FAILURE(rc))
2398 {
2399 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2400 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2401 }
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/**
2407 * Gets VM-exit instruction information along with any displacement for an
2408 * instruction VM-exit.
2409 *
2410 * @returns The VM-exit instruction information.
2411 * @param pVCpu The cross context virtual CPU structure.
2412 * @param uExitReason The VM-exit reason.
2413 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2414 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2415 * NULL.
2416 */
2417IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2418{
2419 RTGCPTR GCPtrDisp;
2420 VMXEXITINSTRINFO ExitInstrInfo;
2421 ExitInstrInfo.u = 0;
2422
2423 /*
2424 * Get and parse the ModR/M byte from our decoded opcodes.
2425 */
2426 uint8_t bRm;
2427 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2428 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2429 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2430 {
2431 /*
2432 * ModR/M indicates register addressing.
2433 *
2434 * The primary/secondary register operands are reported in the iReg1 or iReg2
2435 * fields depending on whether it is a read/write form.
2436 */
2437 uint8_t idxReg1;
2438 uint8_t idxReg2;
2439 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2440 {
2441 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2442 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2443 }
2444 else
2445 {
2446 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2447 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2448 }
2449 ExitInstrInfo.All.u2Scaling = 0;
2450 ExitInstrInfo.All.iReg1 = idxReg1;
2451 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2452 ExitInstrInfo.All.fIsRegOperand = 1;
2453 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2454 ExitInstrInfo.All.iSegReg = 0;
2455 ExitInstrInfo.All.iIdxReg = 0;
2456 ExitInstrInfo.All.fIdxRegInvalid = 1;
2457 ExitInstrInfo.All.iBaseReg = 0;
2458 ExitInstrInfo.All.fBaseRegInvalid = 1;
2459 ExitInstrInfo.All.iReg2 = idxReg2;
2460
2461 /* Displacement not applicable for register addressing. */
2462 GCPtrDisp = 0;
2463 }
2464 else
2465 {
2466 /*
2467 * ModR/M indicates memory addressing.
2468 */
2469 uint8_t uScale = 0;
2470 bool fBaseRegValid = false;
2471 bool fIdxRegValid = false;
2472 uint8_t iBaseReg = 0;
2473 uint8_t iIdxReg = 0;
2474 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2475 {
2476 /*
2477 * Parse the ModR/M, displacement for 16-bit addressing mode.
2478 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2479 */
2480 uint16_t u16Disp = 0;
2481 uint8_t const offDisp = offModRm + sizeof(bRm);
2482 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2483 {
2484 /* Displacement without any registers. */
2485 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2486 }
2487 else
2488 {
2489 /* Register (index and base). */
2490 switch (bRm & X86_MODRM_RM_MASK)
2491 {
2492 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2493 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2494 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2495 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2496 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2497 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2498 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2499 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2500 }
2501
2502 /* Register + displacement. */
2503 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2504 {
2505 case 0: break;
2506 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2507 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2508 default:
2509 {
2510 /* Register addressing, handled at the beginning. */
2511 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2512 break;
2513 }
2514 }
2515 }
2516
2517 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2518 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2519 }
2520 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2521 {
2522 /*
2523 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2524 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2525 */
2526 uint32_t u32Disp = 0;
2527 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2528 {
2529 /* Displacement without any registers. */
2530 uint8_t const offDisp = offModRm + sizeof(bRm);
2531 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2532 }
2533 else
2534 {
2535 /* Register (and perhaps scale, index and base). */
2536 uint8_t offDisp = offModRm + sizeof(bRm);
2537 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2538 if (iBaseReg == 4)
2539 {
2540 /* An SIB byte follows the ModR/M byte, parse it. */
2541 uint8_t bSib;
2542 uint8_t const offSib = offModRm + sizeof(bRm);
2543 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2544
2545 /* A displacement may follow SIB, update its offset. */
2546 offDisp += sizeof(bSib);
2547
2548 /* Get the scale. */
2549 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2550
2551 /* Get the index register. */
2552 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2553 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2554
2555 /* Get the base register. */
2556 iBaseReg = bSib & X86_SIB_BASE_MASK;
2557 fBaseRegValid = true;
2558 if (iBaseReg == 5)
2559 {
2560 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2561 {
2562 /* Mod is 0 implies a 32-bit displacement with no base. */
2563 fBaseRegValid = false;
2564 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2565 }
2566 else
2567 {
2568 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2569 iBaseReg = X86_GREG_xBP;
2570 }
2571 }
2572 }
2573
2574 /* Register + displacement. */
2575 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2576 {
2577 case 0: /* Handled above */ break;
2578 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2579 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2580 default:
2581 {
2582 /* Register addressing, handled at the beginning. */
2583 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2584 break;
2585 }
2586 }
2587 }
2588
2589 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2590 }
2591 else
2592 {
2593 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2594
2595 /*
2596 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2597 * See Intel instruction spec. 2.2 "IA-32e Mode".
2598 */
2599 uint64_t u64Disp = 0;
2600 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2601 if (fRipRelativeAddr)
2602 {
2603 /*
2604 * RIP-relative addressing mode.
2605 *
2606 * The displacement is 32-bit signed implying an offset range of +/-2G.
2607 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2608 */
2609 uint8_t const offDisp = offModRm + sizeof(bRm);
2610 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2611 }
2612 else
2613 {
2614 uint8_t offDisp = offModRm + sizeof(bRm);
2615
2616 /*
2617 * Register (and perhaps scale, index and base).
2618 *
2619 * REX.B extends the most-significant bit of the base register. However, REX.B
2620 * is ignored while determining whether an SIB follows the opcode. Hence, we
2621 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2622 *
2623 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2624 */
2625 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2626 if (iBaseReg == 4)
2627 {
2628 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2629 uint8_t bSib;
2630 uint8_t const offSib = offModRm + sizeof(bRm);
2631 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2632
2633 /* Displacement may follow SIB, update its offset. */
2634 offDisp += sizeof(bSib);
2635
2636 /* Get the scale. */
2637 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2638
2639 /* Get the index. */
2640 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2641 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2642
2643 /* Get the base. */
2644 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2645 fBaseRegValid = true;
2646 if (iBaseReg == 5)
2647 {
2648 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2649 {
2650 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2651 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2652 }
2653 else
2654 {
2655 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2656 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2657 }
2658 }
2659 }
2660 iBaseReg |= pVCpu->iem.s.uRexB;
2661
2662 /* Register + displacement. */
2663 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2664 {
2665 case 0: /* Handled above */ break;
2666 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2667 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2668 default:
2669 {
2670 /* Register addressing, handled at the beginning. */
2671 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2672 break;
2673 }
2674 }
2675 }
2676
2677 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2678 }
2679
2680 /*
2681 * The primary or secondary register operand is reported in iReg2 depending
2682 * on whether the primary operand is in read/write form.
2683 */
2684 uint8_t idxReg2;
2685 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2686 {
2687 idxReg2 = bRm & X86_MODRM_RM_MASK;
2688 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2689 idxReg2 |= pVCpu->iem.s.uRexB;
2690 }
2691 else
2692 {
2693 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2694 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2695 idxReg2 |= pVCpu->iem.s.uRexReg;
2696 }
2697 ExitInstrInfo.All.u2Scaling = uScale;
2698 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2699 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2700 ExitInstrInfo.All.fIsRegOperand = 0;
2701 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2702 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2703 ExitInstrInfo.All.iIdxReg = iIdxReg;
2704 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2705 ExitInstrInfo.All.iBaseReg = iBaseReg;
2706 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2707 ExitInstrInfo.All.iReg2 = idxReg2;
2708 }
2709
2710 /*
2711 * Handle exceptions to the norm for certain instructions.
2712 * (e.g. some instructions convey an instruction identity in place of iReg2).
2713 */
2714 switch (uExitReason)
2715 {
2716 case VMX_EXIT_GDTR_IDTR_ACCESS:
2717 {
2718 Assert(VMXINSTRID_IS_VALID(uInstrId));
2719 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2720 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2721 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2722 break;
2723 }
2724
2725 case VMX_EXIT_LDTR_TR_ACCESS:
2726 {
2727 Assert(VMXINSTRID_IS_VALID(uInstrId));
2728 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2729 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2730 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2731 break;
2732 }
2733
2734 case VMX_EXIT_RDRAND:
2735 case VMX_EXIT_RDSEED:
2736 {
2737 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2738 break;
2739 }
2740 }
2741
2742 /* Update displacement and return the constructed VM-exit instruction information field. */
2743 if (pGCPtrDisp)
2744 *pGCPtrDisp = GCPtrDisp;
2745
2746 return ExitInstrInfo.u;
2747}
2748
2749
2750/**
2751 * VMX VM-exit handler.
2752 *
2753 * @returns Strict VBox status code.
2754 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2755 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2756 * triple-fault.
2757 *
2758 * @param pVCpu The cross context virtual CPU structure.
2759 * @param uExitReason The VM-exit reason.
2760 *
2761 * @remarks Make sure VM-exit qualification is updated before calling this
2762 * function!
2763 */
2764IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2765{
2766# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2767 RT_NOREF2(pVCpu, uExitReason);
2768 return VINF_EM_RAW_EMULATE_INSTR;
2769# else
2770 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
2771
2772 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2773 Assert(pVmcs);
2774
2775 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2776 pVmcs->u32RoExitReason = uExitReason;
2777 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2778 IEM_GET_CTX(pVCpu)->cs.Sel, IEM_GET_CTX(pVCpu)->rip));
2779
2780 /*
2781 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
2782 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
2783 */
2784 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2785
2786 /*
2787 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2788 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2789 */
2790 {
2791 uint8_t uVector;
2792 uint32_t fFlags;
2793 uint32_t uErrCode;
2794 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2795 if (!fInEventDelivery)
2796 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2797 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2798 }
2799
2800 /*
2801 * Save the guest state back into the VMCS.
2802 * We only need to save the state when the VM-entry was successful.
2803 */
2804 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2805 if (!fVmentryFailed)
2806 {
2807 /*
2808 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2809 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2810 *
2811 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2812 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2813 * as guest-CPU state would not been modified. Hence for now, we do this only when
2814 * the VM-entry succeeded.
2815 */
2816 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2817 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2818 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2819 {
2820 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2821 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2822 else
2823 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2824 }
2825
2826 /*
2827 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2828 * occurs in enclave mode/SMM which we don't support yet.
2829 *
2830 * If we ever add support for it, we can pass just the lower bits to the functions
2831 * below, till then an assert should suffice.
2832 */
2833 Assert(!RT_HI_U16(uExitReason));
2834
2835 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2836 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2837 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2838 if (RT_SUCCESS(rc))
2839 { /* likely */ }
2840 else
2841 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2842
2843 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2844 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2845 }
2846 else
2847 {
2848 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2849 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2850 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2851 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2852 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2853 }
2854
2855 /* Restore the host (outer guest) state. */
2856 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2857 if (RT_SUCCESS(rcStrict))
2858 {
2859 Assert(rcStrict == VINF_SUCCESS);
2860 rcStrict = VINF_VMX_VMEXIT;
2861 }
2862 else
2863 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2864
2865 /* We're no longer in nested-guest execution mode. */
2866 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2867
2868 /* Revert any IEM-only nested-guest execution policy if it was set earlier, otherwise return rcStrict. */
2869 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(pVCpu, "VM-exit", rcStrict);
2870# endif
2871}
2872
2873
2874/**
2875 * VMX VM-exit handler for VM-exits due to instruction execution.
2876 *
2877 * This is intended for instructions where the caller provides all the relevant
2878 * VM-exit information.
2879 *
2880 * @returns Strict VBox status code.
2881 * @param pVCpu The cross context virtual CPU structure.
2882 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2883 */
2884DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2885{
2886 /*
2887 * For instructions where any of the following fields are not applicable:
2888 * - VM-exit instruction info. is undefined.
2889 * - VM-exit qualification must be cleared.
2890 * - VM-exit guest-linear address is undefined.
2891 * - VM-exit guest-physical address is undefined.
2892 *
2893 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2894 * instruction execution. For VM-exits that are not due to instruction execution this
2895 * field is undefined.
2896 *
2897 * In our implementation in IEM, all undefined fields are generally cleared. However,
2898 * if the caller supplies information (from say the physical CPU directly) it is
2899 * then possible that the undefined fields are not cleared.
2900 *
2901 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2902 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2903 */
2904 Assert(pExitInfo);
2905 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2906 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2907 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2908
2909 /* Update all the relevant fields from the VM-exit instruction information struct. */
2910 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2911 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2912 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2913 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2914 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2915
2916 /* Perform the VM-exit. */
2917 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2918}
2919
2920
2921/**
2922 * VMX VM-exit handler for VM-exits due to instruction execution.
2923 *
2924 * This is intended for instructions that only provide the VM-exit instruction
2925 * length.
2926 *
2927 * @param pVCpu The cross context virtual CPU structure.
2928 * @param uExitReason The VM-exit reason.
2929 * @param cbInstr The instruction length in bytes.
2930 */
2931IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2932{
2933 VMXVEXITINFO ExitInfo;
2934 RT_ZERO(ExitInfo);
2935 ExitInfo.uReason = uExitReason;
2936 ExitInfo.cbInstr = cbInstr;
2937
2938#ifdef VBOX_STRICT
2939 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2940 switch (uExitReason)
2941 {
2942 case VMX_EXIT_INVEPT:
2943 case VMX_EXIT_INVPCID:
2944 case VMX_EXIT_LDTR_TR_ACCESS:
2945 case VMX_EXIT_GDTR_IDTR_ACCESS:
2946 case VMX_EXIT_VMCLEAR:
2947 case VMX_EXIT_VMPTRLD:
2948 case VMX_EXIT_VMPTRST:
2949 case VMX_EXIT_VMREAD:
2950 case VMX_EXIT_VMWRITE:
2951 case VMX_EXIT_VMXON:
2952 case VMX_EXIT_XRSTORS:
2953 case VMX_EXIT_XSAVES:
2954 case VMX_EXIT_RDRAND:
2955 case VMX_EXIT_RDSEED:
2956 case VMX_EXIT_IO_INSTR:
2957 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2958 break;
2959 }
2960#endif
2961
2962 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2963}
2964
2965
2966/**
2967 * VMX VM-exit handler for VM-exits due to instruction execution.
2968 *
2969 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2970 * instruction information and VM-exit qualification fields.
2971 *
2972 * @param pVCpu The cross context virtual CPU structure.
2973 * @param uExitReason The VM-exit reason.
2974 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2975 * @param cbInstr The instruction length in bytes.
2976 *
2977 * @remarks Do not use this for INS/OUTS instruction.
2978 */
2979IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2980{
2981 VMXVEXITINFO ExitInfo;
2982 RT_ZERO(ExitInfo);
2983 ExitInfo.uReason = uExitReason;
2984 ExitInfo.cbInstr = cbInstr;
2985
2986 /*
2987 * Update the VM-exit qualification field with displacement bytes.
2988 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2989 */
2990 switch (uExitReason)
2991 {
2992 case VMX_EXIT_INVEPT:
2993 case VMX_EXIT_INVPCID:
2994 case VMX_EXIT_LDTR_TR_ACCESS:
2995 case VMX_EXIT_GDTR_IDTR_ACCESS:
2996 case VMX_EXIT_VMCLEAR:
2997 case VMX_EXIT_VMPTRLD:
2998 case VMX_EXIT_VMPTRST:
2999 case VMX_EXIT_VMREAD:
3000 case VMX_EXIT_VMWRITE:
3001 case VMX_EXIT_VMXON:
3002 case VMX_EXIT_XRSTORS:
3003 case VMX_EXIT_XSAVES:
3004 case VMX_EXIT_RDRAND:
3005 case VMX_EXIT_RDSEED:
3006 {
3007 /* Construct the VM-exit instruction information. */
3008 RTGCPTR GCPtrDisp;
3009 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3010
3011 /* Update the VM-exit instruction information. */
3012 ExitInfo.InstrInfo.u = uInstrInfo;
3013
3014 /* Update the VM-exit qualification. */
3015 ExitInfo.u64Qual = GCPtrDisp;
3016 break;
3017 }
3018
3019 default:
3020 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3021 break;
3022 }
3023
3024 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3025}
3026
3027
3028/**
3029 * Checks whether an I/O instruction for the given port is intercepted (causes a
3030 * VM-exit) or not.
3031 *
3032 * @returns @c true if the instruction is intercepted, @c false otherwise.
3033 * @param pVCpu The cross context virtual CPU structure.
3034 * @param u16Port The I/O port being accessed by the instruction.
3035 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3036 */
3037IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3038{
3039 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3040 Assert(pVmcs);
3041
3042 /*
3043 * Check whether the I/O instruction must cause a VM-exit or not.
3044 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3045 */
3046 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3047 return true;
3048
3049 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3050 {
3051 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3052 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3053 Assert(pbIoBitmapA);
3054 Assert(pbIoBitmapB);
3055 return HMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3056 }
3057
3058 return false;
3059}
3060
3061
3062/**
3063 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3064 *
3065 * @returns Strict VBox status code.
3066 * @param pVCpu The cross context virtual CPU structure.
3067 */
3068IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3069{
3070 /*
3071 * The MTF VM-exit can occur even when the MTF VM-execution control is
3072 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3073 * check for it here.
3074 */
3075
3076 /* Clear the force-flag indicating that monitor-trap flag is no longer active. */
3077 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_MTF);
3078
3079 /* Cause the MTF VM-exit. The VM-exit qualification MBZ. */
3080 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3081}
3082
3083
3084/**
3085 * VMX VM-exit handler for VM-exits due to INVLPG.
3086 *
3087 * @returns Strict VBox status code.
3088 * @param pVCpu The cross context virtual CPU structure.
3089 * @param GCPtrPage The guest-linear address of the page being invalidated.
3090 * @param cbInstr The instruction length in bytes.
3091 */
3092IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3093{
3094 VMXVEXITINFO ExitInfo;
3095 RT_ZERO(ExitInfo);
3096 ExitInfo.uReason = VMX_EXIT_INVLPG;
3097 ExitInfo.cbInstr = cbInstr;
3098 ExitInfo.u64Qual = GCPtrPage;
3099 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3100
3101 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3102}
3103
3104
3105/**
3106 * VMX VM-exit handler for VM-exits due to LMSW.
3107 *
3108 * @returns Strict VBox status code.
3109 * @param pVCpu The cross context virtual CPU structure.
3110 * @param uGuestCr0 The current guest CR0.
3111 * @param pu16NewMsw The machine-status word specified in LMSW's source
3112 * operand. This will be updated depending on the VMX
3113 * guest/host CR0 mask if LMSW is not intercepted.
3114 * @param GCPtrEffDst The guest-linear address of the source operand in case
3115 * of a memory operand. For register operand, pass
3116 * NIL_RTGCPTR.
3117 * @param cbInstr The instruction length in bytes.
3118 */
3119IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3120 uint8_t cbInstr)
3121{
3122 /*
3123 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3124 *
3125 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3126 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3127 */
3128 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3129 Assert(pVmcs);
3130 Assert(pu16NewMsw);
3131
3132 bool fIntercept = false;
3133 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3134 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3135
3136 /*
3137 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3138 * CR0.PE case first, before the rest of the bits in the MSW.
3139 *
3140 * If CR0.PE is owned by the host and CR0.PE differs between the
3141 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3142 */
3143 if ( (fGstHostMask & X86_CR0_PE)
3144 && (*pu16NewMsw & X86_CR0_PE)
3145 && !(fReadShadow & X86_CR0_PE))
3146 fIntercept = true;
3147
3148 /*
3149 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3150 * bits differ between the MSW (source operand) and the read-shadow, we must
3151 * cause a VM-exit.
3152 */
3153 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3154 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3155 fIntercept = true;
3156
3157 if (fIntercept)
3158 {
3159 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3160
3161 VMXVEXITINFO ExitInfo;
3162 RT_ZERO(ExitInfo);
3163 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3164 ExitInfo.cbInstr = cbInstr;
3165
3166 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3167 if (fMemOperand)
3168 {
3169 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3170 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3171 }
3172
3173 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3175 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3176 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3177
3178 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3179 }
3180
3181 /*
3182 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3183 * CR0 guest/host mask must be left unmodified.
3184 *
3185 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3186 */
3187 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3188 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3189
3190 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3191}
3192
3193
3194/**
3195 * VMX VM-exit handler for VM-exits due to CLTS.
3196 *
3197 * @returns Strict VBox status code.
3198 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3199 * VM-exit but must not modify the guest CR0.TS bit.
3200 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3201 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3202 * CR0 fixed bits in VMX operation).
3203 * @param pVCpu The cross context virtual CPU structure.
3204 * @param cbInstr The instruction length in bytes.
3205 */
3206IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3207{
3208 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3209 Assert(pVmcs);
3210
3211 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3212 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3213
3214 /*
3215 * If CR0.TS is owned by the host:
3216 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3217 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3218 * CLTS instruction completes without clearing CR0.TS.
3219 *
3220 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3221 */
3222 if (fGstHostMask & X86_CR0_TS)
3223 {
3224 if (fReadShadow & X86_CR0_TS)
3225 {
3226 Log2(("clts: Guest intercept -> VM-exit\n"));
3227
3228 VMXVEXITINFO ExitInfo;
3229 RT_ZERO(ExitInfo);
3230 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3231 ExitInfo.cbInstr = cbInstr;
3232 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3233 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3234 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3235 }
3236
3237 return VINF_VMX_MODIFIES_BEHAVIOR;
3238 }
3239
3240 /*
3241 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3242 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3243 */
3244 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3245}
3246
3247
3248/**
3249 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3250 * (CR0/CR4 write).
3251 *
3252 * @returns Strict VBox status code.
3253 * @param pVCpu The cross context virtual CPU structure.
3254 * @param iCrReg The control register (either CR0 or CR4).
3255 * @param uGuestCrX The current guest CR0/CR4.
3256 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3257 * if no VM-exit is caused.
3258 * @param iGReg The general register from which the CR0/CR4 value is
3259 * being loaded.
3260 * @param cbInstr The instruction length in bytes.
3261 */
3262IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3263 uint8_t cbInstr)
3264{
3265 Assert(puNewCrX);
3266 Assert(iCrReg == 0 || iCrReg == 4);
3267 Assert(iGReg < X86_GREG_COUNT);
3268
3269 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3270 Assert(pVmcs);
3271
3272 uint64_t uGuestCrX;
3273 uint64_t fGstHostMask;
3274 uint64_t fReadShadow;
3275 if (iCrReg == 0)
3276 {
3277 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3278 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3279 fGstHostMask = pVmcs->u64Cr0Mask.u;
3280 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3281 }
3282 else
3283 {
3284 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3285 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3286 fGstHostMask = pVmcs->u64Cr4Mask.u;
3287 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3288 }
3289
3290 /*
3291 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3292 * corresponding bits differ between the source operand and the read-shadow,
3293 * we must cause a VM-exit.
3294 *
3295 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3296 */
3297 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3298 {
3299 Assert(fGstHostMask != 0);
3300 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3301
3302 VMXVEXITINFO ExitInfo;
3303 RT_ZERO(ExitInfo);
3304 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3305 ExitInfo.cbInstr = cbInstr;
3306 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3307 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3308 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3309 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3310 }
3311
3312 /*
3313 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3314 * must not be modified the instruction.
3315 *
3316 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3317 */
3318 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3319
3320 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3321}
3322
3323
3324/**
3325 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3326 *
3327 * @returns VBox strict status code.
3328 * @param pVCpu The cross context virtual CPU structure.
3329 * @param iGReg The general register to which the CR3 value is being stored.
3330 * @param cbInstr The instruction length in bytes.
3331 */
3332IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3333{
3334 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3335 Assert(pVmcs);
3336 Assert(iGReg < X86_GREG_COUNT);
3337 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3338
3339 /*
3340 * If the CR3-store exiting control is set, we must cause a VM-exit.
3341 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3342 */
3343 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3344 {
3345 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3346
3347 VMXVEXITINFO ExitInfo;
3348 RT_ZERO(ExitInfo);
3349 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3350 ExitInfo.cbInstr = cbInstr;
3351 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3352 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3353 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3354 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3355 }
3356
3357 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3358}
3359
3360
3361/**
3362 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3363 *
3364 * @returns VBox strict status code.
3365 * @param pVCpu The cross context virtual CPU structure.
3366 * @param uNewCr3 The new CR3 value.
3367 * @param iGReg The general register from which the CR3 value is being
3368 * loaded.
3369 * @param cbInstr The instruction length in bytes.
3370 */
3371IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3372{
3373 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3374 Assert(pVmcs);
3375 Assert(iGReg < X86_GREG_COUNT);
3376
3377 /*
3378 * If the CR3-load exiting control is set and the new CR3 value does not
3379 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3380 *
3381 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3382 */
3383 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3384 {
3385 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3386 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3387
3388 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3389 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3390 if (!fIntercept)
3391 {
3392 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3393 {
3394 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3395 if (uNewCr3 != uCr3TargetValue)
3396 {
3397 fIntercept = true;
3398 break;
3399 }
3400 }
3401 }
3402
3403 if (fIntercept)
3404 {
3405 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3406
3407 VMXVEXITINFO ExitInfo;
3408 RT_ZERO(ExitInfo);
3409 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3410 ExitInfo.cbInstr = cbInstr;
3411 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3412 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3413 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3414 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3415 }
3416 }
3417
3418 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3419}
3420
3421
3422/**
3423 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3424 *
3425 * @returns VBox strict status code.
3426 * @param pVCpu The cross context virtual CPU structure.
3427 * @param iGReg The general register to which the CR8 value is being stored.
3428 * @param cbInstr The instruction length in bytes.
3429 */
3430IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3431{
3432 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3433 Assert(pVmcs);
3434 Assert(iGReg < X86_GREG_COUNT);
3435
3436 /*
3437 * If the CR8-store exiting control is set, we must cause a VM-exit.
3438 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3439 */
3440 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3441 {
3442 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3443
3444 VMXVEXITINFO ExitInfo;
3445 RT_ZERO(ExitInfo);
3446 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3447 ExitInfo.cbInstr = cbInstr;
3448 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3449 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3450 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3451 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3452 }
3453
3454 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3455}
3456
3457
3458/**
3459 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3460 *
3461 * @returns VBox strict status code.
3462 * @param pVCpu The cross context virtual CPU structure.
3463 * @param iGReg The general register from which the CR8 value is being
3464 * loaded.
3465 * @param cbInstr The instruction length in bytes.
3466 */
3467IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3468{
3469 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3470 Assert(pVmcs);
3471 Assert(iGReg < X86_GREG_COUNT);
3472
3473 /*
3474 * If the CR8-load exiting control is set, we must cause a VM-exit.
3475 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3476 */
3477 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3478 {
3479 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3480
3481 VMXVEXITINFO ExitInfo;
3482 RT_ZERO(ExitInfo);
3483 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3484 ExitInfo.cbInstr = cbInstr;
3485 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3486 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3487 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3488 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3489 }
3490
3491 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3492}
3493
3494
3495/**
3496 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3497 * GReg,DRx' (DRx read).
3498 *
3499 * @returns VBox strict status code.
3500 * @param pVCpu The cross context virtual CPU structure.
3501 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3502 * VMXINSTRID_MOV_FROM_DRX).
3503 * @param iDrReg The debug register being accessed.
3504 * @param iGReg The general register to/from which the DRx value is being
3505 * store/loaded.
3506 * @param cbInstr The instruction length in bytes.
3507 */
3508IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3509 uint8_t cbInstr)
3510{
3511 Assert(iDrReg <= 7);
3512 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3513 Assert(iGReg < X86_GREG_COUNT);
3514
3515 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3516 Assert(pVmcs);
3517
3518 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3519 {
3520 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3521 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3522 VMXVEXITINFO ExitInfo;
3523 RT_ZERO(ExitInfo);
3524 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3525 ExitInfo.cbInstr = cbInstr;
3526 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3527 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3528 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3529 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3530 }
3531
3532 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3533}
3534
3535
3536/**
3537 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3538 *
3539 * @returns VBox strict status code.
3540 * @param pVCpu The cross context virtual CPU structure.
3541 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3542 * VMXINSTRID_IO_OUT).
3543 * @param u16Port The I/O port being accessed.
3544 * @param fImm Whether the I/O port was encoded using an immediate operand
3545 * or the implicit DX register.
3546 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3547 * @param cbInstr The instruction length in bytes.
3548 */
3549IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3550 uint8_t cbInstr)
3551{
3552 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3553 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3554
3555 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3556 if (fIntercept)
3557 {
3558 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3559 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3560 VMXVEXITINFO ExitInfo;
3561 RT_ZERO(ExitInfo);
3562 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3563 ExitInfo.cbInstr = cbInstr;
3564 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3565 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3566 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3567 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3568 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3569 }
3570
3571 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3572}
3573
3574
3575/**
3576 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3577 *
3578 * @returns VBox strict status code.
3579 * @param pVCpu The cross context virtual CPU structure.
3580 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3581 * VMXINSTRID_IO_OUTS).
3582 * @param u16Port The I/O port being accessed.
3583 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3584 * @param fRep Whether the instruction has a REP prefix or not.
3585 * @param ExitInstrInfo The VM-exit instruction info. field.
3586 * @param cbInstr The instruction length in bytes.
3587 */
3588IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3589 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3590{
3591 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3592 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3593 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3594 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3595 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3596
3597 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3598 if (fIntercept)
3599 {
3600 /*
3601 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3602 */
3603 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3604 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3605 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3606 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3607 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3608
3609 uint32_t uDirection;
3610 uint64_t uGuestLinearAddr;
3611 if (uInstrId == VMXINSTRID_IO_INS)
3612 {
3613 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3614 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3615 }
3616 else
3617 {
3618 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3619 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3620 }
3621
3622 /*
3623 * If the segment is ununsable, the guest-linear address in undefined.
3624 * We shall clear it for consistency.
3625 *
3626 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3627 */
3628 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3629 uGuestLinearAddr = 0;
3630
3631 VMXVEXITINFO ExitInfo;
3632 RT_ZERO(ExitInfo);
3633 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3634 ExitInfo.cbInstr = cbInstr;
3635 ExitInfo.InstrInfo = ExitInstrInfo;
3636 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3637 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3638 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3639 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3640 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3641 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3642 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3643 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3644 }
3645
3646 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3647}
3648
3649
3650/**
3651 * VMX VM-exit handler for VM-exits due to MWAIT.
3652 *
3653 * @returns VBox strict status code.
3654 * @param pVCpu The cross context virtual CPU structure.
3655 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3656 * @param cbInstr The instruction length in bytes.
3657 */
3658IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3659{
3660 VMXVEXITINFO ExitInfo;
3661 RT_ZERO(ExitInfo);
3662 ExitInfo.uReason = VMX_EXIT_MWAIT;
3663 ExitInfo.cbInstr = cbInstr;
3664 ExitInfo.u64Qual = fMonitorHwArmed;
3665 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3666}
3667
3668
3669/**
3670 * VMX VM-exit handler for VM-exits due to PAUSE.
3671 *
3672 * @returns VBox strict status code.
3673 * @param pVCpu The cross context virtual CPU structure.
3674 * @param cbInstr The instruction length in bytes.
3675 */
3676IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3677{
3678 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3679 Assert(pVmcs);
3680
3681 /*
3682 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3683 * "PAUSE-loop exiting" control.
3684 *
3685 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3686 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3687 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3688 * a VM-exit.
3689 *
3690 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3691 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3692 */
3693 bool fIntercept = false;
3694 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3695 fIntercept = true;
3696 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3697 && pVCpu->iem.s.uCpl == 0)
3698 {
3699 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3700
3701 /*
3702 * A previous-PAUSE-tick value of 0 is used to identify the first time
3703 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3704 * consider this to be the first execution of PAUSE in a loop according
3705 * to the Intel.
3706 *
3707 * All subsequent records for the previous-PAUSE-tick we ensure that it
3708 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3709 */
3710 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3711 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3712 uint64_t const uTick = TMCpuTickGet(pVCpu);
3713 uint32_t const uPleGap = pVmcs->u32PleGap;
3714 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3715 if ( *puPrevPauseTick == 0
3716 || uTick - *puPrevPauseTick > uPleGap)
3717 *puFirstPauseLoopTick = uTick;
3718 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3719 fIntercept = true;
3720
3721 *puPrevPauseTick = uTick | 1;
3722 }
3723
3724 if (fIntercept)
3725 {
3726 VMXVEXITINFO ExitInfo;
3727 RT_ZERO(ExitInfo);
3728 ExitInfo.uReason = VMX_EXIT_PAUSE;
3729 ExitInfo.cbInstr = cbInstr;
3730 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3731 }
3732
3733 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3734}
3735
3736
3737/**
3738 * VMX VM-exit handler for VM-exits due to task switches.
3739 *
3740 * @returns VBox strict status code.
3741 * @param pVCpu The cross context virtual CPU structure.
3742 * @param enmTaskSwitch The cause of the task switch.
3743 * @param SelNewTss The selector of the new TSS.
3744 * @param cbInstr The instruction length in bytes.
3745 */
3746IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3747{
3748 /*
3749 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3750 *
3751 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3752 * instruction or delivery of the exception generated by one of these instructions
3753 * lead to a task switch through a task gate in the IDT, we need to provide the
3754 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3755 * leaves the VM-exit instruction length field undefined.
3756 *
3757 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3758 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3759 */
3760 Assert(cbInstr <= 15);
3761
3762 uint8_t uType;
3763 switch (enmTaskSwitch)
3764 {
3765 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3766 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3767 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3768 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3769 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3770 }
3771
3772 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3773 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3774 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3775 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3776 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3777}
3778
3779
3780/**
3781 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3782 *
3783 * @returns VBox strict status code.
3784 * @param pVCpu The cross context virtual CPU structure.
3785 */
3786IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3787{
3788 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3789 Assert(pVmcs);
3790
3791 /* Check if the guest has enabled VMX-preemption timers in the first place. */
3792 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3793 {
3794 /*
3795 * Calculate the current VMX-preemption timer value.
3796 * Only if the value has reached zero, we cause the VM-exit.
3797 */
3798 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3799 if (!uPreemptTimer)
3800 {
3801 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3802 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3803 pVmcs->u32PreemptTimer = 0;
3804
3805 /* Clear the force-flag indicating the VMX-preemption timer no longer active. */
3806 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3807
3808 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3809 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3810 }
3811 }
3812
3813 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3814}
3815
3816
3817/**
3818 * VMX VM-exit handler for VM-exits due to external interrupts.
3819 *
3820 * @returns VBox strict status code.
3821 * @param pVCpu The cross context virtual CPU structure.
3822 * @param uVector The external interrupt vector (pass 0 if the interrupt
3823 * is still pending since we typically won't know the
3824 * vector).
3825 * @param fIntPending Whether the external interrupt is pending or
3826 * acknowledged in the interrupt controller.
3827 */
3828IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3829{
3830 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3831 Assert(pVmcs);
3832 Assert(fIntPending || uVector == 0);
3833
3834 /* The VM-exit is subject to "External interrupt exiting" is being set. */
3835 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3836 {
3837 if (fIntPending)
3838 {
3839 /*
3840 * If the interrupt is pending and we don't need to acknowledge the
3841 * interrupt on VM-exit, cause the VM-exit immediately.
3842 *
3843 * See Intel spec 25.2 "Other Causes Of VM Exits".
3844 */
3845 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3846 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3847
3848 /*
3849 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3850 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3851 * acknowledged that the interrupt has been consumed.
3852 */
3853 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3854 }
3855
3856 /*
3857 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3858 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3859 * all set, we cause the VM-exit now. We need to record the external interrupt that
3860 * just occurred in the VM-exit interruption information field.
3861 *
3862 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3863 */
3864 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3865 {
3866 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3867 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3868 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3869 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3870 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3871 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3872 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3873 }
3874 }
3875
3876 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3877}
3878
3879
3880/**
3881 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3882 *
3883 * @returns VBox strict status code.
3884 * @param pVCpu The cross context virtual CPU structure.
3885 * @param uVector The SIPI vector.
3886 */
3887IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3888{
3889 iemVmxVmcsSetExitQual(pVCpu, uVector);
3890 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3891}
3892
3893
3894/**
3895 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3896 *
3897 * @returns VBox strict status code.
3898 * @param pVCpu The cross context virtual CPU structure.
3899 */
3900IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3901{
3902 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3903}
3904
3905
3906/**
3907 * VMX VM-exit handler for interrupt-window VM-exits.
3908 *
3909 * @returns VBox strict status code.
3910 * @param pVCpu The cross context virtual CPU structure.
3911 */
3912IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3913{
3914 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3915}
3916
3917
3918/**
3919 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3920 * an event.
3921 *
3922 * @returns VBox strict status code.
3923 * @param pVCpu The cross context virtual CPU structure.
3924 */
3925IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3926{
3927 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3928 Assert(pVmcs);
3929
3930 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3931 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3932 {
3933 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3934 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3935 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3936 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3937 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3938 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3939 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3940 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3941 iemVmxVmcsSetExitQual(pVCpu, 0);
3942 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3943
3944 /*
3945 * A VM-exit is not considered to occur during event delivery when the original
3946 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3947 * using the exception bitmap).
3948 *
3949 * Therefore, we must clear the original event from the IDT-vectoring fields which
3950 * would've been recorded before causing the VM-exit.
3951 *
3952 * 27.2.3 "Information for VM Exits During Event Delivery"
3953 */
3954 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3955 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3956
3957 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3958 }
3959
3960 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3961}
3962
3963
3964/**
3965 * VMX VM-exit handler for VM-exits due to delivery of an event.
3966 *
3967 * @returns VBox strict status code.
3968 * @param pVCpu The cross context virtual CPU structure.
3969 * @param uVector The interrupt / exception vector.
3970 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3971 * @param uErrCode The error code associated with the event.
3972 * @param uCr2 The CR2 value in case of a \#PF exception.
3973 * @param cbInstr The instruction length in bytes.
3974 */
3975IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3976 uint8_t cbInstr)
3977{
3978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3979 Assert(pVmcs);
3980
3981 /*
3982 * If the event is being injected as part of VM-entry, it isn't subject to event
3983 * intercepts in the nested-guest. However, secondary exceptions that occur during
3984 * injection of any event -are- subject to event interception.
3985 *
3986 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3987 */
3988 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3989 {
3990 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3991 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3992 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3993 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3994 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3995 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3996 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3997 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3998 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3999
4000 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4001 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4002 }
4003
4004 /*
4005 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4006 * If not, the caller will continue delivery of the external interrupt as it would
4007 * normally. The interrupt is no longer pending in the interrupt controller at this
4008 * point.
4009 */
4010 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4011 {
4012 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4013 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4014 }
4015
4016 /*
4017 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4018 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4019 */
4020 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4021 bool fIntercept = false;
4022 bool fIsHwXcpt = false;
4023 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4024 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4025 {
4026 fIsHwXcpt = true;
4027 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4028 if (uVector == X86_XCPT_NMI)
4029 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
4030 else
4031 {
4032 /* Page-faults are subject to masking using its error code. */
4033 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4034 if (uVector == X86_XCPT_PF)
4035 {
4036 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4037 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4038 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4039 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4040 }
4041
4042 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4043 if (fXcptBitmap & RT_BIT(uVector))
4044 fIntercept = true;
4045 }
4046 }
4047 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4048
4049 /*
4050 * Now that we've determined whether the software interrupt or hardware exception
4051 * causes a VM-exit, we need to construct the relevant VM-exit information and
4052 * cause the VM-exit.
4053 */
4054 if (fIntercept)
4055 {
4056 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4057
4058 /* Construct the rest of the event related information fields and cause the VM-exit. */
4059 uint64_t uExitQual = 0;
4060 if (fIsHwXcpt)
4061 {
4062 if (uVector == X86_XCPT_PF)
4063 {
4064 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4065 uExitQual = uCr2;
4066 }
4067 else if (uVector == X86_XCPT_DB)
4068 {
4069 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
4070 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4071 }
4072 }
4073
4074 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4075 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4076 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4077 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4078 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4079 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4080 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4081 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4082 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4083 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4084 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4085
4086 /*
4087 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4088 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4089 * length.
4090 */
4091 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4092 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4093 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4094 else
4095 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4096
4097 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4098 }
4099
4100 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4101}
4102
4103
4104/**
4105 * VMX VM-exit handler for VM-exits due to a triple fault.
4106 *
4107 * @returns VBox strict status code.
4108 * @param pVCpu The cross context virtual CPU structure.
4109 */
4110IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4111{
4112 /*
4113 * A VM-exit is not considered to occur during event delivery when the original
4114 * event results in a triple-fault.
4115 *
4116 * Therefore, we must clear the original event from the IDT-vectoring fields which
4117 * would've been recorded before causing the VM-exit.
4118 *
4119 * 27.2.3 "Information for VM Exits During Event Delivery"
4120 */
4121 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4122 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4123
4124 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4125}
4126
4127
4128/**
4129 * VMX VM-exit handler for APIC-accesses.
4130 *
4131 * @param pVCpu The cross context virtual CPU structure.
4132 * @param offAccess The offset of the register being accessed.
4133 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4134 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4135 */
4136IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4137{
4138 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4139
4140 VMXAPICACCESS enmAccess;
4141 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4142 if (fInEventDelivery)
4143 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4144 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4145 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4146 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4147 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4148 else
4149 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4150
4151 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4152 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4153 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4154 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4155}
4156
4157
4158/**
4159 * VMX VM-exit handler for APIC-write VM-exits.
4160 *
4161 * @param pVCpu The cross context virtual CPU structure.
4162 * @param offApic The write to the virtual-APIC page offset that caused this
4163 * VM-exit.
4164 */
4165IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4166{
4167 Assert(offApic < XAPIC_OFF_END + 4);
4168
4169 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4170 offApic &= UINT16_C(0xfff);
4171 iemVmxVmcsSetExitQual(pVCpu, offApic);
4172 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4173}
4174
4175
4176/**
4177 * VMX VM-exit handler for virtualized-EOIs.
4178 *
4179 * @param pVCpu The cross context virtual CPU structure.
4180 */
4181IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4182{
4183 iemVmxVmcsSetExitQual(pVCpu, uVector);
4184 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4185}
4186
4187
4188/**
4189 * Sets virtual-APIC write emulation as pending.
4190 *
4191 * @param pVCpu The cross context virtual CPU structure.
4192 * @param offApic The offset in the virtual-APIC page that was written.
4193 */
4194DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4195{
4196 Assert(offApic < XAPIC_OFF_END + 4);
4197
4198 /*
4199 * Record the currently updated APIC offset, as we need this later for figuring
4200 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4201 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4202 */
4203 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4204
4205 /*
4206 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4207 * virtualization or APIC-write emulation).
4208 */
4209 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4210 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4211}
4212
4213
4214/**
4215 * Clears any pending virtual-APIC write emulation.
4216 *
4217 * @returns The virtual-APIC offset that was written before clearing it.
4218 * @param pVCpu The cross context virtual CPU structure.
4219 */
4220DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4221{
4222 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4223 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4224 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4225 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4226 return offVirtApicWrite;
4227}
4228
4229
4230/**
4231 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4232 *
4233 * @returns The register from the virtual-APIC page.
4234 * @param pVCpu The cross context virtual CPU structure.
4235 * @param offReg The offset of the register being read.
4236 */
4237DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4238{
4239 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4240 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4241 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4242 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4243 return uReg;
4244}
4245
4246
4247/**
4248 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4249 *
4250 * @returns The register from the virtual-APIC page.
4251 * @param pVCpu The cross context virtual CPU structure.
4252 * @param offReg The offset of the register being read.
4253 */
4254DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4255{
4256 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4257 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4258 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4259 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4260 return uReg;
4261}
4262
4263
4264/**
4265 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4266 *
4267 * @param pVCpu The cross context virtual CPU structure.
4268 * @param offReg The offset of the register being written.
4269 * @param uReg The register value to write.
4270 */
4271DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4272{
4273 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4274 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4275 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4276 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4277}
4278
4279
4280/**
4281 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4282 *
4283 * @param pVCpu The cross context virtual CPU structure.
4284 * @param offReg The offset of the register being written.
4285 * @param uReg The register value to write.
4286 */
4287DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4288{
4289 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4290 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4291 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4292 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4293}
4294
4295
4296/**
4297 * Sets the vector in a virtual-APIC 256-bit sparse register.
4298 *
4299 * @param pVCpu The cross context virtual CPU structure.
4300 * @param offReg The offset of the 256-bit spare register.
4301 * @param uVector The vector to set.
4302 *
4303 * @remarks This is based on our APIC device code.
4304 */
4305DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4306{
4307 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4308 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4309 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4310 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4311 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4312}
4313
4314
4315/**
4316 * Clears the vector in a virtual-APIC 256-bit sparse register.
4317 *
4318 * @param pVCpu The cross context virtual CPU structure.
4319 * @param offReg The offset of the 256-bit spare register.
4320 * @param uVector The vector to clear.
4321 *
4322 * @remarks This is based on our APIC device code.
4323 */
4324DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4325{
4326 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4327 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4328 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4329 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4330 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4331}
4332
4333
4334/**
4335 * Checks if a memory access to the APIC-access page must causes an APIC-access
4336 * VM-exit.
4337 *
4338 * @param pVCpu The cross context virtual CPU structure.
4339 * @param offAccess The offset of the register being accessed.
4340 * @param cbAccess The size of the access in bytes.
4341 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4342 * IEM_ACCESS_TYPE_WRITE).
4343 *
4344 * @remarks This must not be used for MSR-based APIC-access page accesses!
4345 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4346 */
4347IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4348{
4349 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4350 Assert(pVmcs);
4351 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4352
4353 /*
4354 * We must cause a VM-exit if any of the following are true:
4355 * - TPR shadowing isn't active.
4356 * - The access size exceeds 32-bits.
4357 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4358 *
4359 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4360 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4361 */
4362 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4363 || cbAccess > sizeof(uint32_t)
4364 || ((offAccess + cbAccess - 1) & 0xc)
4365 || offAccess >= XAPIC_OFF_END + 4)
4366 return true;
4367
4368 /*
4369 * If the access is part of an operation where we have already
4370 * virtualized a virtual-APIC write, we must cause a VM-exit.
4371 */
4372 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4373 return true;
4374
4375 /*
4376 * Check write accesses to the APIC-access page that cause VM-exits.
4377 */
4378 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4379 {
4380 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4381 {
4382 /*
4383 * With APIC-register virtualization, a write access to any of the
4384 * following registers are virtualized. Accessing any other register
4385 * causes a VM-exit.
4386 */
4387 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4388 switch (offAlignedAccess)
4389 {
4390 case XAPIC_OFF_ID:
4391 case XAPIC_OFF_TPR:
4392 case XAPIC_OFF_EOI:
4393 case XAPIC_OFF_LDR:
4394 case XAPIC_OFF_DFR:
4395 case XAPIC_OFF_SVR:
4396 case XAPIC_OFF_ESR:
4397 case XAPIC_OFF_ICR_LO:
4398 case XAPIC_OFF_ICR_HI:
4399 case XAPIC_OFF_LVT_TIMER:
4400 case XAPIC_OFF_LVT_THERMAL:
4401 case XAPIC_OFF_LVT_PERF:
4402 case XAPIC_OFF_LVT_LINT0:
4403 case XAPIC_OFF_LVT_LINT1:
4404 case XAPIC_OFF_LVT_ERROR:
4405 case XAPIC_OFF_TIMER_ICR:
4406 case XAPIC_OFF_TIMER_DCR:
4407 break;
4408 default:
4409 return true;
4410 }
4411 }
4412 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4413 {
4414 /*
4415 * With virtual-interrupt delivery, a write access to any of the
4416 * following registers are virtualized. Accessing any other register
4417 * causes a VM-exit.
4418 *
4419 * Note! The specification does not allow writing to offsets in-between
4420 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4421 */
4422 switch (offAccess)
4423 {
4424 case XAPIC_OFF_TPR:
4425 case XAPIC_OFF_EOI:
4426 case XAPIC_OFF_ICR_LO:
4427 break;
4428 default:
4429 return true;
4430 }
4431 }
4432 else
4433 {
4434 /*
4435 * Without APIC-register virtualization or virtual-interrupt delivery,
4436 * only TPR accesses are virtualized.
4437 */
4438 if (offAccess == XAPIC_OFF_TPR)
4439 { /* likely */ }
4440 else
4441 return true;
4442 }
4443 }
4444 else
4445 {
4446 /*
4447 * Check read accesses to the APIC-access page that cause VM-exits.
4448 */
4449 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4450 {
4451 /*
4452 * With APIC-register virtualization, a read access to any of the
4453 * following registers are virtualized. Accessing any other register
4454 * causes a VM-exit.
4455 */
4456 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4457 switch (offAlignedAccess)
4458 {
4459 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4460 case XAPIC_OFF_ID:
4461 case XAPIC_OFF_VERSION:
4462 case XAPIC_OFF_TPR:
4463 case XAPIC_OFF_EOI:
4464 case XAPIC_OFF_LDR:
4465 case XAPIC_OFF_DFR:
4466 case XAPIC_OFF_SVR:
4467 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4468 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4469 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4470 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4471 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4472 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4473 case XAPIC_OFF_ESR:
4474 case XAPIC_OFF_ICR_LO:
4475 case XAPIC_OFF_ICR_HI:
4476 case XAPIC_OFF_LVT_TIMER:
4477 case XAPIC_OFF_LVT_THERMAL:
4478 case XAPIC_OFF_LVT_PERF:
4479 case XAPIC_OFF_LVT_LINT0:
4480 case XAPIC_OFF_LVT_LINT1:
4481 case XAPIC_OFF_LVT_ERROR:
4482 case XAPIC_OFF_TIMER_ICR:
4483 case XAPIC_OFF_TIMER_DCR:
4484 break;
4485 default:
4486 return true;
4487 }
4488 }
4489 else
4490 {
4491 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4492 if (offAccess == XAPIC_OFF_TPR)
4493 { /* likely */ }
4494 else
4495 return true;
4496 }
4497 }
4498
4499 /* The APIC-access is virtualized, does not cause a VM-exit. */
4500 return false;
4501}
4502
4503
4504/**
4505 * Virtualizes a memory-based APIC-access where the address is not used to access
4506 * memory.
4507 *
4508 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4509 * page-faults but do not use the address to access memory.
4510 *
4511 * @param pVCpu The cross context virtual CPU structure.
4512 * @param pGCPhysAccess Pointer to the guest-physical address used.
4513 */
4514IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4515{
4516 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4517 Assert(pVmcs);
4518 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4519 Assert(pGCPhysAccess);
4520
4521 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4522 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4523 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4524
4525 if (GCPhysAccess == GCPhysApic)
4526 {
4527 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4528 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4529 uint16_t const cbAccess = 1;
4530 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4531 if (fIntercept)
4532 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4533
4534 *pGCPhysAccess = GCPhysApic | offAccess;
4535 return VINF_VMX_MODIFIES_BEHAVIOR;
4536 }
4537
4538 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4539}
4540
4541
4542/**
4543 * Virtualizes a memory-based APIC-access.
4544 *
4545 * @returns VBox strict status code.
4546 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4547 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4548 *
4549 * @param pVCpu The cross context virtual CPU structure.
4550 * @param offAccess The offset of the register being accessed (within the
4551 * APIC-access page).
4552 * @param cbAccess The size of the access in bytes.
4553 * @param pvData Pointer to the data being written or where to store the data
4554 * being read.
4555 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4556 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4557 */
4558IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4559 uint32_t fAccess)
4560{
4561 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4562 Assert(pVmcs);
4563 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4564 Assert(pvData);
4565 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4566 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4567 || (fAccess & IEM_ACCESS_INSTRUCTION));
4568
4569 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4570 if (fIntercept)
4571 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4572
4573 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4574 {
4575 /*
4576 * A write access to the APIC-access page that is virtualized (rather than
4577 * causing a VM-exit) writes data to the virtual-APIC page.
4578 */
4579 uint32_t const u32Data = *(uint32_t *)pvData;
4580 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4581
4582 /*
4583 * Record the currently updated APIC offset, as we need this later for figuring
4584 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4585 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4586 *
4587 * After completion of the current operation, we need to perform TPR virtualization,
4588 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4589 *
4590 * The current operation may be a REP-prefixed string instruction, execution of any
4591 * other instruction, or delivery of an event through the IDT.
4592 *
4593 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4594 * performed now but later after completion of the current operation.
4595 *
4596 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4597 */
4598 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4599 }
4600 else
4601 {
4602 /*
4603 * A read access from the APIC-access page that is virtualized (rather than
4604 * causing a VM-exit) returns data from the virtual-APIC page.
4605 *
4606 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4607 */
4608 Assert(cbAccess <= 4);
4609 Assert(offAccess < XAPIC_OFF_END + 4);
4610 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4611
4612 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4613 u32Data &= s_auAccessSizeMasks[cbAccess];
4614 *(uint32_t *)pvData = u32Data;
4615 }
4616
4617 return VINF_VMX_MODIFIES_BEHAVIOR;
4618}
4619
4620
4621/**
4622 * Virtualizes an MSR-based APIC read access.
4623 *
4624 * @returns VBox strict status code.
4625 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4626 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4627 * handled by the x2APIC device.
4628 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4629 * not within the range of valid MSRs, caller must raise \#GP(0).
4630 * @param pVCpu The cross context virtual CPU structure.
4631 * @param idMsr The x2APIC MSR being read.
4632 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4633 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4634 */
4635IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4636{
4637 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4638 Assert(pVmcs);
4639 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4640 Assert(pu64Value);
4641
4642 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4643 {
4644 /*
4645 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4646 * what the end of the valid x2APIC MSR range is. Hence the use of different
4647 * macros here.
4648 *
4649 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4650 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4651 */
4652 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4653 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4654 {
4655 uint16_t const offReg = (idMsr & 0xff) << 4;
4656 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4657 *pu64Value = u64Value;
4658 return VINF_VMX_MODIFIES_BEHAVIOR;
4659 }
4660 return VERR_OUT_OF_RANGE;
4661 }
4662
4663 if (idMsr == MSR_IA32_X2APIC_TPR)
4664 {
4665 uint16_t const offReg = (idMsr & 0xff) << 4;
4666 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4667 *pu64Value = u64Value;
4668 return VINF_VMX_MODIFIES_BEHAVIOR;
4669 }
4670
4671 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4672}
4673
4674
4675/**
4676 * Virtualizes an MSR-based APIC write access.
4677 *
4678 * @returns VBox strict status code.
4679 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4680 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4681 * not within the range of valid MSRs, caller must raise \#GP(0).
4682 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4683 *
4684 * @param pVCpu The cross context virtual CPU structure.
4685 * @param idMsr The x2APIC MSR being written.
4686 * @param u64Value The value of the x2APIC MSR being written.
4687 */
4688IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4689{
4690 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4691 Assert(pVmcs);
4692
4693 /*
4694 * Check if the access is to be virtualized.
4695 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4696 */
4697 if ( idMsr == MSR_IA32_X2APIC_TPR
4698 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4699 && ( idMsr == MSR_IA32_X2APIC_EOI
4700 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4701 {
4702 /* Validate the MSR write depending on the register. */
4703 switch (idMsr)
4704 {
4705 case MSR_IA32_X2APIC_TPR:
4706 case MSR_IA32_X2APIC_SELF_IPI:
4707 {
4708 if (u64Value & UINT64_C(0xffffffffffffff00))
4709 return VERR_OUT_OF_RANGE;
4710 break;
4711 }
4712 case MSR_IA32_X2APIC_EOI:
4713 {
4714 if (u64Value != 0)
4715 return VERR_OUT_OF_RANGE;
4716 break;
4717 }
4718 }
4719
4720 /* Write the MSR to the virtual-APIC page. */
4721 uint16_t const offReg = (idMsr & 0xff) << 4;
4722 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4723
4724 /*
4725 * Record the currently updated APIC offset, as we need this later for figuring
4726 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4727 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4728 */
4729 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4730
4731 return VINF_VMX_MODIFIES_BEHAVIOR;
4732 }
4733
4734 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4735}
4736
4737
4738/**
4739 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4740 *
4741 * @returns VBox status code.
4742 * @retval VINF_SUCCES when the highest set bit is found.
4743 * @retval VERR_NOT_FOUND when no bit is set.
4744 *
4745 * @param pVCpu The cross context virtual CPU structure.
4746 * @param offReg The offset of the APIC 256-bit sparse register.
4747 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4748 * set in the register. Only valid when VINF_SUCCESS is
4749 * returned.
4750 *
4751 * @remarks The format of the 256-bit sparse register here mirrors that found in
4752 * real APIC hardware.
4753 */
4754static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4755{
4756 Assert(offReg < XAPIC_OFF_END + 4);
4757 Assert(pidxHighestBit);
4758
4759 /*
4760 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4761 * However, in each fragment only the first 4 bytes are used.
4762 */
4763 uint8_t const cFrags = 8;
4764 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4765 {
4766 uint16_t const offFrag = iFrag * 16;
4767 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4768 if (!u32Frag)
4769 continue;
4770
4771 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4772 Assert(idxHighestBit > 0);
4773 --idxHighestBit;
4774 Assert(idxHighestBit <= UINT8_MAX);
4775 *pidxHighestBit = idxHighestBit;
4776 return VINF_SUCCESS;
4777 }
4778 return VERR_NOT_FOUND;
4779}
4780
4781
4782/**
4783 * Evaluates pending virtual interrupts.
4784 *
4785 * @param pVCpu The cross context virtual CPU structure.
4786 */
4787IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4788{
4789 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4790 Assert(pVmcs);
4791 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4792
4793 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4794 {
4795 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4796 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4797
4798 if ((uRvi >> 4) > (uPpr >> 4))
4799 {
4800 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4801 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4802 }
4803 else
4804 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4805 }
4806}
4807
4808
4809/**
4810 * Performs PPR virtualization.
4811 *
4812 * @returns VBox strict status code.
4813 * @param pVCpu The cross context virtual CPU structure.
4814 */
4815IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4816{
4817 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4818 Assert(pVmcs);
4819 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4820 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4821
4822 /*
4823 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4824 * or EOI-virtualization.
4825 *
4826 * See Intel spec. 29.1.3 "PPR Virtualization".
4827 */
4828 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4829 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4830
4831 uint32_t uPpr;
4832 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4833 uPpr = uTpr & 0xff;
4834 else
4835 uPpr = uSvi & 0xf0;
4836
4837 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4838 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4839}
4840
4841
4842/**
4843 * Performs VMX TPR virtualization.
4844 *
4845 * @returns VBox strict status code.
4846 * @param pVCpu The cross context virtual CPU structure.
4847 */
4848IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4849{
4850 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4851 Assert(pVmcs);
4852 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4853
4854 /*
4855 * We should have already performed the virtual-APIC write to the TPR offset
4856 * in the virtual-APIC page. We now perform TPR virtualization.
4857 *
4858 * See Intel spec. 29.1.2 "TPR Virtualization".
4859 */
4860 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4861 {
4862 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4863 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4864
4865 /*
4866 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4867 * See Intel spec. 29.1.2 "TPR Virtualization".
4868 */
4869 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4870 {
4871 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4872 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4873 }
4874 }
4875 else
4876 {
4877 iemVmxPprVirtualization(pVCpu);
4878 iemVmxEvalPendingVirtIntrs(pVCpu);
4879 }
4880
4881 return VINF_SUCCESS;
4882}
4883
4884
4885/**
4886 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4887 * not.
4888 *
4889 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4890 * @param pVCpu The cross context virtual CPU structure.
4891 * @param uVector The interrupt that was acknowledged using an EOI.
4892 */
4893IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4894{
4895 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4896 Assert(pVmcs);
4897 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4898
4899 if (uVector < 64)
4900 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4901 if (uVector < 128)
4902 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4903 if (uVector < 192)
4904 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4905 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4906}
4907
4908
4909/**
4910 * Performs EOI virtualization.
4911 *
4912 * @returns VBox strict status code.
4913 * @param pVCpu The cross context virtual CPU structure.
4914 */
4915IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4916{
4917 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4918 Assert(pVmcs);
4919 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4920
4921 /*
4922 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4923 * and get the next guest-interrupt that's in-service (if any).
4924 *
4925 * See Intel spec. 29.1.4 "EOI Virtualization".
4926 */
4927 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4928 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4929 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4930
4931 uint8_t uVector = uSvi;
4932 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4933
4934 uVector = 0;
4935 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4936
4937 if (uVector)
4938 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4939 else
4940 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4941
4942 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4943 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4944
4945 iemVmxPprVirtualization(pVCpu);
4946 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4947 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4948 iemVmxEvalPendingVirtIntrs(pVCpu);
4949 return VINF_SUCCESS;
4950}
4951
4952
4953/**
4954 * Performs self-IPI virtualization.
4955 *
4956 * @returns VBox strict status code.
4957 * @param pVCpu The cross context virtual CPU structure.
4958 */
4959IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4960{
4961 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4962 Assert(pVmcs);
4963 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4964
4965 /*
4966 * We should have already performed the virtual-APIC write to the self-IPI offset
4967 * in the virtual-APIC page. We now perform self-IPI virtualization.
4968 *
4969 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4970 */
4971 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4972 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4973 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
4974 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4975 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4976 if (uVector > uRvi)
4977 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4978 iemVmxEvalPendingVirtIntrs(pVCpu);
4979 return VINF_SUCCESS;
4980}
4981
4982
4983/**
4984 * Performs VMX APIC-write emulation.
4985 *
4986 * @returns VBox strict status code.
4987 * @param pVCpu The cross context virtual CPU structure.
4988 */
4989IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4990{
4991 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4992 Assert(pVmcs);
4993
4994 /*
4995 * Perform APIC-write emulation based on the virtual-APIC register written.
4996 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4997 */
4998 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4999 VBOXSTRICTRC rcStrict;
5000 switch (offApicWrite)
5001 {
5002 case XAPIC_OFF_TPR:
5003 {
5004 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5005 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5006 uTpr &= UINT32_C(0x000000ff);
5007 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5008 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5009 rcStrict = iemVmxTprVirtualization(pVCpu);
5010 break;
5011 }
5012
5013 case XAPIC_OFF_EOI:
5014 {
5015 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5016 {
5017 /* Clear VEOI and perform EOI virtualization. */
5018 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5019 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5020 rcStrict = iemVmxEoiVirtualization(pVCpu);
5021 }
5022 else
5023 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5024 break;
5025 }
5026
5027 case XAPIC_OFF_ICR_LO:
5028 {
5029 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5030 {
5031 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5032 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5033 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5034 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5035 if ( !(uIcrLo & fIcrLoMb0)
5036 && (uIcrLo & fIcrLoMb1))
5037 {
5038 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5039 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5040 }
5041 else
5042 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5043 }
5044 else
5045 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5046 break;
5047 }
5048
5049 case XAPIC_OFF_ICR_HI:
5050 {
5051 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5052 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5053 uIcrHi &= UINT32_C(0xff000000);
5054 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5055 rcStrict = VINF_SUCCESS;
5056 break;
5057 }
5058
5059 default:
5060 {
5061 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5062 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5063 break;
5064 }
5065 }
5066
5067 return rcStrict;
5068}
5069
5070
5071/**
5072 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5073 *
5074 * @param pVCpu The cross context virtual CPU structure.
5075 * @param pszInstr The VMX instruction name (for logging purposes).
5076 */
5077IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5078{
5079 /*
5080 * Guest Control Registers, Debug Registers, and MSRs.
5081 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5082 */
5083 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5084 const char *const pszFailure = "VM-exit";
5085 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5086
5087 /* CR0 reserved bits. */
5088 {
5089 /* CR0 MB1 bits. */
5090 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5091 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5092 if (fUnrestrictedGuest)
5093 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5094 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5095 { /* likely */ }
5096 else
5097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5098
5099 /* CR0 MBZ bits. */
5100 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5101 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5102 { /* likely */ }
5103 else
5104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5105
5106 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5107 if ( !fUnrestrictedGuest
5108 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5109 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5111 }
5112
5113 /* CR4 reserved bits. */
5114 {
5115 /* CR4 MB1 bits. */
5116 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5117 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5118 { /* likely */ }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5121
5122 /* CR4 MBZ bits. */
5123 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5124 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5125 { /* likely */ }
5126 else
5127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5128 }
5129
5130 /* DEBUGCTL MSR. */
5131 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5132 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5133 { /* likely */ }
5134 else
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5136
5137 /* 64-bit CPU checks. */
5138 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5139 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5140 {
5141 if (fGstInLongMode)
5142 {
5143 /* PAE must be set. */
5144 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5145 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5149 }
5150 else
5151 {
5152 /* PCIDE should not be set. */
5153 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5154 { /* likely */ }
5155 else
5156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5157 }
5158
5159 /* CR3. */
5160 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5161 { /* likely */ }
5162 else
5163 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5164
5165 /* DR7. */
5166 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5167 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5171
5172 /* SYSENTER ESP and SYSENTER EIP. */
5173 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5174 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5178 }
5179
5180 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5181 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5182
5183 /* PAT MSR. */
5184 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5185 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5186 { /* likely */ }
5187 else
5188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5189
5190 /* EFER MSR. */
5191 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5192 {
5193 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5194 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5195 { /* likely */ }
5196 else
5197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5198
5199 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5200 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5201 if ( fGstLma == fGstInLongMode
5202 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5203 || fGstLma == fGstLme))
5204 { /* likely */ }
5205 else
5206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5207 }
5208
5209 /* We don't support IA32_BNDCFGS MSR yet. */
5210 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5211
5212 NOREF(pszInstr);
5213 NOREF(pszFailure);
5214 return VINF_SUCCESS;
5215}
5216
5217
5218/**
5219 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5220 *
5221 * @param pVCpu The cross context virtual CPU structure.
5222 * @param pszInstr The VMX instruction name (for logging purposes).
5223 */
5224IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5225{
5226 /*
5227 * Segment registers.
5228 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5229 */
5230 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5231 const char *const pszFailure = "VM-exit";
5232 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5233 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5234 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5235
5236 /* Selectors. */
5237 if ( !fGstInV86Mode
5238 && !fUnrestrictedGuest
5239 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5241
5242 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5243 {
5244 CPUMSELREG SelReg;
5245 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5246 if (RT_LIKELY(rc == VINF_SUCCESS))
5247 { /* likely */ }
5248 else
5249 return rc;
5250
5251 /*
5252 * Virtual-8086 mode checks.
5253 */
5254 if (fGstInV86Mode)
5255 {
5256 /* Base address. */
5257 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5258 { /* likely */ }
5259 else
5260 {
5261 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5263 }
5264
5265 /* Limit. */
5266 if (SelReg.u32Limit == 0xffff)
5267 { /* likely */ }
5268 else
5269 {
5270 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5272 }
5273
5274 /* Attribute. */
5275 if (SelReg.Attr.u == 0xf3)
5276 { /* likely */ }
5277 else
5278 {
5279 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5281 }
5282
5283 /* We're done; move to checking the next segment. */
5284 continue;
5285 }
5286
5287 /* Checks done by 64-bit CPUs. */
5288 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5289 {
5290 /* Base address. */
5291 if ( iSegReg == X86_SREG_FS
5292 || iSegReg == X86_SREG_GS)
5293 {
5294 if (X86_IS_CANONICAL(SelReg.u64Base))
5295 { /* likely */ }
5296 else
5297 {
5298 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5300 }
5301 }
5302 else if (iSegReg == X86_SREG_CS)
5303 {
5304 if (!RT_HI_U32(SelReg.u64Base))
5305 { /* likely */ }
5306 else
5307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5308 }
5309 else
5310 {
5311 if ( SelReg.Attr.n.u1Unusable
5312 || !RT_HI_U32(SelReg.u64Base))
5313 { /* likely */ }
5314 else
5315 {
5316 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5318 }
5319 }
5320 }
5321
5322 /*
5323 * Checks outside Virtual-8086 mode.
5324 */
5325 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5326 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5327 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5328 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5329 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5330 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5331 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5332 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5333
5334 /* Code or usable segment. */
5335 if ( iSegReg == X86_SREG_CS
5336 || fUsable)
5337 {
5338 /* Reserved bits (bits 31:17 and bits 11:8). */
5339 if (!(SelReg.Attr.u & 0xfffe0f00))
5340 { /* likely */ }
5341 else
5342 {
5343 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5345 }
5346
5347 /* Descriptor type. */
5348 if (fCodeDataSeg)
5349 { /* likely */ }
5350 else
5351 {
5352 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5354 }
5355
5356 /* Present. */
5357 if (fPresent)
5358 { /* likely */ }
5359 else
5360 {
5361 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5363 }
5364
5365 /* Granularity. */
5366 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5367 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5368 { /* likely */ }
5369 else
5370 {
5371 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5373 }
5374 }
5375
5376 if (iSegReg == X86_SREG_CS)
5377 {
5378 /* Segment Type and DPL. */
5379 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5380 && fUnrestrictedGuest)
5381 {
5382 if (uDpl == 0)
5383 { /* likely */ }
5384 else
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5386 }
5387 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5388 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5389 {
5390 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5391 if (uDpl == AttrSs.n.u2Dpl)
5392 { /* likely */ }
5393 else
5394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5395 }
5396 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5397 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5398 {
5399 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5400 if (uDpl <= AttrSs.n.u2Dpl)
5401 { /* likely */ }
5402 else
5403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5404 }
5405 else
5406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5407
5408 /* Def/Big. */
5409 if ( fGstInLongMode
5410 && fSegLong)
5411 {
5412 if (uDefBig == 0)
5413 { /* likely */ }
5414 else
5415 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5416 }
5417 }
5418 else if (iSegReg == X86_SREG_SS)
5419 {
5420 /* Segment Type. */
5421 if ( !fUsable
5422 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5423 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5424 { /* likely */ }
5425 else
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5427
5428 /* DPL. */
5429 if (!fUnrestrictedGuest)
5430 {
5431 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5432 { /* likely */ }
5433 else
5434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5435 }
5436 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5437 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5438 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5439 {
5440 if (uDpl == 0)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5444 }
5445 }
5446 else
5447 {
5448 /* DS, ES, FS, GS. */
5449 if (fUsable)
5450 {
5451 /* Segment type. */
5452 if (uSegType & X86_SEL_TYPE_ACCESSED)
5453 { /* likely */ }
5454 else
5455 {
5456 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5458 }
5459
5460 if ( !(uSegType & X86_SEL_TYPE_CODE)
5461 || (uSegType & X86_SEL_TYPE_READ))
5462 { /* likely */ }
5463 else
5464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5465
5466 /* DPL. */
5467 if ( !fUnrestrictedGuest
5468 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5469 {
5470 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5471 { /* likely */ }
5472 else
5473 {
5474 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5476 }
5477 }
5478 }
5479 }
5480 }
5481
5482 /*
5483 * LDTR.
5484 */
5485 {
5486 CPUMSELREG Ldtr;
5487 Ldtr.Sel = pVmcs->GuestLdtr;
5488 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5489 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5490 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5491
5492 if (!Ldtr.Attr.n.u1Unusable)
5493 {
5494 /* Selector. */
5495 if (!(Ldtr.Sel & X86_SEL_LDT))
5496 { /* likely */ }
5497 else
5498 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5499
5500 /* Base. */
5501 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5502 {
5503 if (X86_IS_CANONICAL(Ldtr.u64Base))
5504 { /* likely */ }
5505 else
5506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5507 }
5508
5509 /* Attributes. */
5510 /* Reserved bits (bits 31:17 and bits 11:8). */
5511 if (!(Ldtr.Attr.u & 0xfffe0f00))
5512 { /* likely */ }
5513 else
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5515
5516 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5517 { /* likely */ }
5518 else
5519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5520
5521 if (!Ldtr.Attr.n.u1DescType)
5522 { /* likely */ }
5523 else
5524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5525
5526 if (Ldtr.Attr.n.u1Present)
5527 { /* likely */ }
5528 else
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5530
5531 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5532 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5533 { /* likely */ }
5534 else
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5536 }
5537 }
5538
5539 /*
5540 * TR.
5541 */
5542 {
5543 CPUMSELREG Tr;
5544 Tr.Sel = pVmcs->GuestTr;
5545 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5546 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5547 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5548
5549 /* Selector. */
5550 if (!(Tr.Sel & X86_SEL_LDT))
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5554
5555 /* Base. */
5556 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5557 {
5558 if (X86_IS_CANONICAL(Tr.u64Base))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5562 }
5563
5564 /* Attributes. */
5565 /* Reserved bits (bits 31:17 and bits 11:8). */
5566 if (!(Tr.Attr.u & 0xfffe0f00))
5567 { /* likely */ }
5568 else
5569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5570
5571 if (!Tr.Attr.n.u1Unusable)
5572 { /* likely */ }
5573 else
5574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5575
5576 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5577 || ( !fGstInLongMode
5578 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5579 { /* likely */ }
5580 else
5581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5582
5583 if (!Tr.Attr.n.u1DescType)
5584 { /* likely */ }
5585 else
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5587
5588 if (Tr.Attr.n.u1Present)
5589 { /* likely */ }
5590 else
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5592
5593 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5594 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5598 }
5599
5600 NOREF(pszInstr);
5601 NOREF(pszFailure);
5602 return VINF_SUCCESS;
5603}
5604
5605
5606/**
5607 * Checks guest GDTR and IDTR as part of VM-entry.
5608 *
5609 * @param pVCpu The cross context virtual CPU structure.
5610 * @param pszInstr The VMX instruction name (for logging purposes).
5611 */
5612IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5613{
5614 /*
5615 * GDTR and IDTR.
5616 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5617 */
5618 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5619 const char *const pszFailure = "VM-exit";
5620
5621 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5622 {
5623 /* Base. */
5624 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5625 { /* likely */ }
5626 else
5627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5628
5629 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5630 { /* likely */ }
5631 else
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5633 }
5634
5635 /* Limit. */
5636 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5637 { /* likely */ }
5638 else
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5640
5641 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5642 { /* likely */ }
5643 else
5644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5645
5646 NOREF(pszInstr);
5647 NOREF(pszFailure);
5648 return VINF_SUCCESS;
5649}
5650
5651
5652/**
5653 * Checks guest RIP and RFLAGS as part of VM-entry.
5654 *
5655 * @param pVCpu The cross context virtual CPU structure.
5656 * @param pszInstr The VMX instruction name (for logging purposes).
5657 */
5658IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5659{
5660 /*
5661 * RIP and RFLAGS.
5662 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5663 */
5664 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5665 const char *const pszFailure = "VM-exit";
5666 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5667
5668 /* RIP. */
5669 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5670 {
5671 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5672 if ( !fGstInLongMode
5673 || !AttrCs.n.u1Long)
5674 {
5675 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5676 { /* likely */ }
5677 else
5678 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5679 }
5680
5681 if ( fGstInLongMode
5682 && AttrCs.n.u1Long)
5683 {
5684 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5685 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5686 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5687 { /* likely */ }
5688 else
5689 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5690 }
5691 }
5692
5693 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5694 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5695 : pVmcs->u64GuestRFlags.s.Lo;
5696 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5697 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5698 { /* likely */ }
5699 else
5700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5701
5702 if ( fGstInLongMode
5703 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5704 {
5705 if (!(uGuestRFlags & X86_EFL_VM))
5706 { /* likely */ }
5707 else
5708 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5709 }
5710
5711 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5712 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5713 {
5714 if (uGuestRFlags & X86_EFL_IF)
5715 { /* likely */ }
5716 else
5717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5718 }
5719
5720 NOREF(pszInstr);
5721 NOREF(pszFailure);
5722 return VINF_SUCCESS;
5723}
5724
5725
5726/**
5727 * Checks guest non-register state as part of VM-entry.
5728 *
5729 * @param pVCpu The cross context virtual CPU structure.
5730 * @param pszInstr The VMX instruction name (for logging purposes).
5731 */
5732IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5733{
5734 /*
5735 * Guest non-register state.
5736 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5737 */
5738 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5739 const char *const pszFailure = "VM-exit";
5740
5741 /*
5742 * Activity state.
5743 */
5744 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5745 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5746 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5747 { /* likely */ }
5748 else
5749 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5750
5751 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5752 if ( !AttrSs.n.u2Dpl
5753 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5754 { /* likely */ }
5755 else
5756 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5757
5758 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5759 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5760 {
5761 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5762 { /* likely */ }
5763 else
5764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5765 }
5766
5767 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5768 {
5769 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5770 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5771 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5772 switch (pVmcs->u32GuestActivityState)
5773 {
5774 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5775 {
5776 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5777 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5778 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5779 && ( uVector == X86_XCPT_DB
5780 || uVector == X86_XCPT_MC))
5781 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5782 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5783 { /* likely */ }
5784 else
5785 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5786 break;
5787 }
5788
5789 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5790 {
5791 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5792 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5793 && uVector == X86_XCPT_MC))
5794 { /* likely */ }
5795 else
5796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5797 break;
5798 }
5799
5800 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5801 default:
5802 break;
5803 }
5804 }
5805
5806 /*
5807 * Interruptibility state.
5808 */
5809 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5810 { /* likely */ }
5811 else
5812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5813
5814 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5815 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5816 { /* likely */ }
5817 else
5818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5819
5820 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5821 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5822 { /* likely */ }
5823 else
5824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5825
5826 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5827 {
5828 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5829 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5830 {
5831 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5835 }
5836 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5837 {
5838 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5839 { /* likely */ }
5840 else
5841 {
5842 /*
5843 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5844 * We update the VM-exit qualification only when blocking-by-STI is set
5845 * without blocking-by-MovSS being set. Although in practise it does not
5846 * make much difference since the order of checks are implementation defined.
5847 */
5848 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5849 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5851 }
5852
5853 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5854 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5855 { /* likely */ }
5856 else
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5858 }
5859 }
5860
5861 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5862 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5863 { /* likely */ }
5864 else
5865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5866
5867 /* We don't support SGX yet. So enclave-interruption must not be set. */
5868 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5872
5873 /*
5874 * Pending debug exceptions.
5875 */
5876 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5877 ? pVmcs->u64GuestPendingDbgXcpt.u
5878 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5879 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5883
5884 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5885 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5886 {
5887 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5888 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5889 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5891
5892 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5893 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5894 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5896 }
5897
5898 /* We don't support RTM (Real-time Transactional Memory) yet. */
5899 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5903
5904 /*
5905 * VMCS link pointer.
5906 */
5907 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5908 {
5909 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5910 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5911 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5912 { /* likely */ }
5913 else
5914 {
5915 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5917 }
5918
5919 /* Validate the address. */
5920 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5921 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5922 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5923 { /* likely */ }
5924 else
5925 {
5926 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5928 }
5929
5930 /* Read the VMCS-link pointer from guest memory. */
5931 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5932 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5933 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5934 if (RT_SUCCESS(rc))
5935 { /* likely */ }
5936 else
5937 {
5938 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5940 }
5941
5942 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5943 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5944 { /* likely */ }
5945 else
5946 {
5947 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5948 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5949 }
5950
5951 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5952 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5953 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5954 { /* likely */ }
5955 else
5956 {
5957 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5958 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5959 }
5960
5961 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5962 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5963 }
5964
5965 NOREF(pszInstr);
5966 NOREF(pszFailure);
5967 return VINF_SUCCESS;
5968}
5969
5970
5971/**
5972 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5973 * VM-entry.
5974 *
5975 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5976 * @param pVCpu The cross context virtual CPU structure.
5977 * @param pszInstr The VMX instruction name (for logging purposes).
5978 * @param pVmcs Pointer to the virtual VMCS.
5979 */
5980IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5981{
5982 /*
5983 * Check PDPTEs.
5984 * See Intel spec. 4.4.1 "PDPTE Registers".
5985 */
5986 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5987 const char *const pszFailure = "VM-exit";
5988
5989 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5990 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5991 if (RT_SUCCESS(rc))
5992 {
5993 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5994 {
5995 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5996 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5997 { /* likely */ }
5998 else
5999 {
6000 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6001 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6003 }
6004 }
6005 }
6006 else
6007 {
6008 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6010 }
6011
6012 NOREF(pszFailure);
6013 NOREF(pszInstr);
6014 return rc;
6015}
6016
6017
6018/**
6019 * Checks guest PDPTEs as part of VM-entry.
6020 *
6021 * @param pVCpu The cross context virtual CPU structure.
6022 * @param pszInstr The VMX instruction name (for logging purposes).
6023 */
6024IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6025{
6026 /*
6027 * Guest PDPTEs.
6028 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6029 */
6030 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6031 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6032
6033 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6034 int rc;
6035 if ( !fGstInLongMode
6036 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6037 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6038 {
6039 /*
6040 * We don't support nested-paging for nested-guests yet.
6041 *
6042 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6043 * rather we need to check the PDPTEs referenced by the guest CR3.
6044 */
6045 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6046 }
6047 else
6048 rc = VINF_SUCCESS;
6049 return rc;
6050}
6051
6052
6053/**
6054 * Checks guest-state as part of VM-entry.
6055 *
6056 * @returns VBox status code.
6057 * @param pVCpu The cross context virtual CPU structure.
6058 * @param pszInstr The VMX instruction name (for logging purposes).
6059 */
6060IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6061{
6062 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6063 if (RT_SUCCESS(rc))
6064 {
6065 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6066 if (RT_SUCCESS(rc))
6067 {
6068 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6069 if (RT_SUCCESS(rc))
6070 {
6071 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6072 if (RT_SUCCESS(rc))
6073 {
6074 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6075 if (RT_SUCCESS(rc))
6076 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6077 }
6078 }
6079 }
6080 }
6081 return rc;
6082}
6083
6084
6085/**
6086 * Checks host-state as part of VM-entry.
6087 *
6088 * @returns VBox status code.
6089 * @param pVCpu The cross context virtual CPU structure.
6090 * @param pszInstr The VMX instruction name (for logging purposes).
6091 */
6092IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6093{
6094 /*
6095 * Host Control Registers and MSRs.
6096 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6097 */
6098 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6099 const char * const pszFailure = "VMFail";
6100
6101 /* CR0 reserved bits. */
6102 {
6103 /* CR0 MB1 bits. */
6104 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6105 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6106 { /* likely */ }
6107 else
6108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6109
6110 /* CR0 MBZ bits. */
6111 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6112 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6113 { /* likely */ }
6114 else
6115 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6116 }
6117
6118 /* CR4 reserved bits. */
6119 {
6120 /* CR4 MB1 bits. */
6121 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6122 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6123 { /* likely */ }
6124 else
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6126
6127 /* CR4 MBZ bits. */
6128 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6129 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6133 }
6134
6135 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6136 {
6137 /* CR3 reserved bits. */
6138 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6142
6143 /* SYSENTER ESP and SYSENTER EIP. */
6144 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6145 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6149 }
6150
6151 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6152 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6153
6154 /* PAT MSR. */
6155 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6156 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6157 { /* likely */ }
6158 else
6159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6160
6161 /* EFER MSR. */
6162 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6163 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6164 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6165 { /* likely */ }
6166 else
6167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6168
6169 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6170 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6171 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6172 if ( fHostInLongMode == fHostLma
6173 && fHostInLongMode == fHostLme)
6174 { /* likely */ }
6175 else
6176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6177
6178 /*
6179 * Host Segment and Descriptor-Table Registers.
6180 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6181 */
6182 /* Selector RPL and TI. */
6183 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6184 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6185 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6186 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6187 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6188 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6189 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6190 { /* likely */ }
6191 else
6192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6193
6194 /* CS and TR selectors cannot be 0. */
6195 if ( pVmcs->HostCs
6196 && pVmcs->HostTr)
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6200
6201 /* SS cannot be 0 if 32-bit host. */
6202 if ( fHostInLongMode
6203 || pVmcs->HostSs)
6204 { /* likely */ }
6205 else
6206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6207
6208 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6209 {
6210 /* FS, GS, GDTR, IDTR, TR base address. */
6211 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6212 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6213 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6214 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6215 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6219 }
6220
6221 /*
6222 * Host address-space size for 64-bit CPUs.
6223 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6224 */
6225 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6226 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6227 {
6228 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6229
6230 /* Logical processor in IA-32e mode. */
6231 if (fCpuInLongMode)
6232 {
6233 if (fHostInLongMode)
6234 {
6235 /* PAE must be set. */
6236 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6237 { /* likely */ }
6238 else
6239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6240
6241 /* RIP must be canonical. */
6242 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6243 { /* likely */ }
6244 else
6245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6246 }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6249 }
6250 else
6251 {
6252 /* Logical processor is outside IA-32e mode. */
6253 if ( !fGstInLongMode
6254 && !fHostInLongMode)
6255 {
6256 /* PCIDE should not be set. */
6257 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6261
6262 /* The high 32-bits of RIP MBZ. */
6263 if (!pVmcs->u64HostRip.s.Hi)
6264 { /* likely */ }
6265 else
6266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6267 }
6268 else
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6270 }
6271 }
6272 else
6273 {
6274 /* Host address-space size for 32-bit CPUs. */
6275 if ( !fGstInLongMode
6276 && !fHostInLongMode)
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6280 }
6281
6282 NOREF(pszInstr);
6283 NOREF(pszFailure);
6284 return VINF_SUCCESS;
6285}
6286
6287
6288/**
6289 * Checks VM-entry controls fields as part of VM-entry.
6290 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6291 *
6292 * @returns VBox status code.
6293 * @param pVCpu The cross context virtual CPU structure.
6294 * @param pszInstr The VMX instruction name (for logging purposes).
6295 */
6296IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6297{
6298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6299 const char * const pszFailure = "VMFail";
6300
6301 /* VM-entry controls. */
6302 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6303 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6304 { /* likely */ }
6305 else
6306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6307
6308 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6309 { /* likely */ }
6310 else
6311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6312
6313 /* Event injection. */
6314 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6315 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6316 {
6317 /* Type and vector. */
6318 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6319 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6320 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6321 if ( !uRsvd
6322 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6323 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6324 { /* likely */ }
6325 else
6326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6327
6328 /* Exception error code. */
6329 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6330 {
6331 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6332 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6333 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6334 { /* likely */ }
6335 else
6336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6337
6338 /* Exceptions that provide an error code. */
6339 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6340 && ( uVector == X86_XCPT_DF
6341 || uVector == X86_XCPT_TS
6342 || uVector == X86_XCPT_NP
6343 || uVector == X86_XCPT_SS
6344 || uVector == X86_XCPT_GP
6345 || uVector == X86_XCPT_PF
6346 || uVector == X86_XCPT_AC))
6347 { /* likely */ }
6348 else
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6350
6351 /* Exception error-code reserved bits. */
6352 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6353 { /* likely */ }
6354 else
6355 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6356
6357 /* Injecting a software interrupt, software exception or privileged software exception. */
6358 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6359 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6360 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6361 {
6362 /* Instruction length must be in the range 0-15. */
6363 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6364 { /* likely */ }
6365 else
6366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6367
6368 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6369 if ( pVmcs->u32EntryInstrLen == 0
6370 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6372 }
6373 }
6374 }
6375
6376 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6377 if (pVmcs->u32EntryMsrLoadCount)
6378 {
6379 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6380 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6381 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6382 { /* likely */ }
6383 else
6384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6385 }
6386
6387 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6388 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6389
6390 NOREF(pszInstr);
6391 NOREF(pszFailure);
6392 return VINF_SUCCESS;
6393}
6394
6395
6396/**
6397 * Checks VM-exit controls fields as part of VM-entry.
6398 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6399 *
6400 * @returns VBox status code.
6401 * @param pVCpu The cross context virtual CPU structure.
6402 * @param pszInstr The VMX instruction name (for logging purposes).
6403 */
6404IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6405{
6406 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6407 const char * const pszFailure = "VMFail";
6408
6409 /* VM-exit controls. */
6410 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6411 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6415
6416 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6417 { /* likely */ }
6418 else
6419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6420
6421 /* Save preemption timer without activating it. */
6422 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6423 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6424 { /* likely */ }
6425 else
6426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6427
6428 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6429 if (pVmcs->u32ExitMsrStoreCount)
6430 {
6431 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6432 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6433 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6434 { /* likely */ }
6435 else
6436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6437 }
6438
6439 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6440 if (pVmcs->u32ExitMsrLoadCount)
6441 {
6442 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6443 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6444 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6445 { /* likely */ }
6446 else
6447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6448 }
6449
6450 NOREF(pszInstr);
6451 NOREF(pszFailure);
6452 return VINF_SUCCESS;
6453}
6454
6455
6456/**
6457 * Checks VM-execution controls fields as part of VM-entry.
6458 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6459 *
6460 * @returns VBox status code.
6461 * @param pVCpu The cross context virtual CPU structure.
6462 * @param pszInstr The VMX instruction name (for logging purposes).
6463 *
6464 * @remarks This may update secondary-processor based VM-execution control fields
6465 * in the current VMCS if necessary.
6466 */
6467IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6468{
6469 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6470 const char * const pszFailure = "VMFail";
6471
6472 /* Pin-based VM-execution controls. */
6473 {
6474 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6475 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6476 { /* likely */ }
6477 else
6478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6479
6480 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6481 { /* likely */ }
6482 else
6483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6484 }
6485
6486 /* Processor-based VM-execution controls. */
6487 {
6488 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6489 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6490 { /* likely */ }
6491 else
6492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6493
6494 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6495 { /* likely */ }
6496 else
6497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6498 }
6499
6500 /* Secondary processor-based VM-execution controls. */
6501 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6502 {
6503 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6504 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6505 { /* likely */ }
6506 else
6507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6508
6509 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6510 { /* likely */ }
6511 else
6512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6513 }
6514 else
6515 Assert(!pVmcs->u32ProcCtls2);
6516
6517 /* CR3-target count. */
6518 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6519 { /* likely */ }
6520 else
6521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6522
6523 /* I/O bitmaps physical addresses. */
6524 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6525 {
6526 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6527 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6528 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6529 { /* likely */ }
6530 else
6531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6532
6533 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6534 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6535 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6539 }
6540
6541 /* MSR bitmap physical address. */
6542 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6543 {
6544 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6545 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6546 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6547 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6548 { /* likely */ }
6549 else
6550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6551
6552 /* Read the MSR bitmap. */
6553 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6554 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6555 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6556 if (RT_SUCCESS(rc))
6557 { /* likely */ }
6558 else
6559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6560 }
6561
6562 /* TPR shadow related controls. */
6563 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6564 {
6565 /* Virtual-APIC page physical address. */
6566 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6567 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6568 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6569 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6570 { /* likely */ }
6571 else
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6573
6574 /* Read the Virtual-APIC page. */
6575 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6576 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6577 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6578 if (RT_SUCCESS(rc))
6579 { /* likely */ }
6580 else
6581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6582
6583 /* TPR threshold without virtual-interrupt delivery. */
6584 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6585 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6587
6588 /* TPR threshold and VTPR. */
6589 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6590 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6591 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6592 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6593 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6595 }
6596 else
6597 {
6598 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6599 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6600 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6601 { /* likely */ }
6602 else
6603 {
6604 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6606 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6608 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6610 }
6611 }
6612
6613 /* NMI exiting and virtual-NMIs. */
6614 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6615 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6619
6620 /* Virtual-NMIs and NMI-window exiting. */
6621 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6622 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6623 { /* likely */ }
6624 else
6625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6626
6627 /* Virtualize APIC accesses. */
6628 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6629 {
6630 /* APIC-access physical address. */
6631 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6632 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6633 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6634 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6635 { /* likely */ }
6636 else
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6638
6639 /*
6640 * Disallow APIC-access page and virtual-APIC page from being the same address.
6641 * Note! This is not an Intel requirement, but one imposed by our implementation.
6642 */
6643 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6644 * redirecting accesses between the APIC-access page and the virtual-APIC
6645 * page. If any nested hypervisor requires this, we can implement it later. */
6646 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6647 {
6648 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6649 if (GCPhysVirtApic != GCPhysApicAccess)
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6653 }
6654
6655 /*
6656 * Register the handler for the APIC-access page.
6657 *
6658 * We don't deregister the APIC-access page handler during the VM-exit as a different
6659 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6660 *
6661 * We leave the page registered until the first access that happens outside VMX non-root
6662 * mode. Guest software is allowed to access structures such as the APIC-access page
6663 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6664 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6665 *
6666 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6667 */
6668 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6669 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6670 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6671 if (RT_SUCCESS(rc))
6672 { /* likely */ }
6673 else
6674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6675 }
6676
6677 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6678 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6679 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6680 { /* likely */ }
6681 else
6682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6683
6684 /* Virtual-interrupt delivery requires external interrupt exiting. */
6685 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6686 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6687 { /* likely */ }
6688 else
6689 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6690
6691 /* VPID. */
6692 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6693 || pVmcs->u16Vpid != 0)
6694 { /* likely */ }
6695 else
6696 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6697
6698 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6699 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6700 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6701 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6702 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6703 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6704 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6705
6706 /* VMCS shadowing. */
6707 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6708 {
6709 /* VMREAD-bitmap physical address. */
6710 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6711 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6712 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6713 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6717
6718 /* VMWRITE-bitmap physical address. */
6719 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6720 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6721 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6722 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6723 { /* likely */ }
6724 else
6725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6726
6727 /* Read the VMREAD-bitmap. */
6728 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6729 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6730 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6731 if (RT_SUCCESS(rc))
6732 { /* likely */ }
6733 else
6734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6735
6736 /* Read the VMWRITE-bitmap. */
6737 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6738 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6739 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6740 if (RT_SUCCESS(rc))
6741 { /* likely */ }
6742 else
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6744 }
6745
6746 NOREF(pszInstr);
6747 NOREF(pszFailure);
6748 return VINF_SUCCESS;
6749}
6750
6751
6752/**
6753 * Loads the guest control registers, debug register and some MSRs as part of
6754 * VM-entry.
6755 *
6756 * @param pVCpu The cross context virtual CPU structure.
6757 */
6758IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6759{
6760 /*
6761 * Load guest control registers, debug registers and MSRs.
6762 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6763 */
6764 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6765 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6766 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6767 CPUMSetGuestCR0(pVCpu, uGstCr0);
6768 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6769 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6770
6771 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6772 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6773
6774 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6775 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6776 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6777
6778 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6779 {
6780 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6781
6782 /* EFER MSR. */
6783 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6784 {
6785 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6786 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6787 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6788 if (fGstInLongMode)
6789 {
6790 /* If the nested-guest is in long mode, LMA and LME are both set. */
6791 Assert(fGstPaging);
6792 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6793 }
6794 else
6795 {
6796 /*
6797 * If the nested-guest is outside long mode:
6798 * - With paging: LMA is cleared, LME is cleared.
6799 * - Without paging: LMA is cleared, LME is left unmodified.
6800 */
6801 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6802 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6803 }
6804 }
6805 /* else: see below. */
6806 }
6807
6808 /* PAT MSR. */
6809 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6810 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6811
6812 /* EFER MSR. */
6813 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6814 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6815
6816 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6817 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6818
6819 /* We don't support IA32_BNDCFGS MSR yet. */
6820 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6821
6822 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6823}
6824
6825
6826/**
6827 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6828 *
6829 * @param pVCpu The cross context virtual CPU structure.
6830 */
6831IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6832{
6833 /*
6834 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6835 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6836 */
6837 /* CS, SS, ES, DS, FS, GS. */
6838 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6839 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6840 {
6841 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6842 CPUMSELREG VmcsSelReg;
6843 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6844 AssertRC(rc); NOREF(rc);
6845 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6846 {
6847 pGstSelReg->Sel = VmcsSelReg.Sel;
6848 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6849 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6850 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6851 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6852 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6853 }
6854 else
6855 {
6856 pGstSelReg->Sel = VmcsSelReg.Sel;
6857 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6858 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6859 switch (iSegReg)
6860 {
6861 case X86_SREG_CS:
6862 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6863 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6864 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6865 break;
6866
6867 case X86_SREG_SS:
6868 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6869 pGstSelReg->u32Limit = 0;
6870 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6871 break;
6872
6873 case X86_SREG_ES:
6874 case X86_SREG_DS:
6875 pGstSelReg->u64Base = 0;
6876 pGstSelReg->u32Limit = 0;
6877 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6878 break;
6879
6880 case X86_SREG_FS:
6881 case X86_SREG_GS:
6882 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6883 pGstSelReg->u32Limit = 0;
6884 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6885 break;
6886 }
6887 Assert(pGstSelReg->Attr.n.u1Unusable);
6888 }
6889 }
6890
6891 /* LDTR. */
6892 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6893 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6894 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6895 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6896 {
6897 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6898 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6899 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6900 }
6901 else
6902 {
6903 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6904 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6905 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6906 }
6907
6908 /* TR. */
6909 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6910 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6911 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6912 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6913 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6914 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6915 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6916
6917 /* GDTR. */
6918 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6919 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6920
6921 /* IDTR. */
6922 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6923 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6924}
6925
6926
6927/**
6928 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6929 *
6930 * @returns VBox status code.
6931 * @param pVCpu The cross context virtual CPU structure.
6932 * @param pszInstr The VMX instruction name (for logging purposes).
6933 */
6934IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6935{
6936 /*
6937 * Load guest MSRs.
6938 * See Intel spec. 26.4 "Loading MSRs".
6939 */
6940 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6941 const char *const pszFailure = "VM-exit";
6942
6943 /*
6944 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6945 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6946 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6947 */
6948 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6949 if (!cMsrs)
6950 return VINF_SUCCESS;
6951
6952 /*
6953 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6954 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6955 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6956 */
6957 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6958 if (fIsMsrCountValid)
6959 { /* likely */ }
6960 else
6961 {
6962 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6964 }
6965
6966 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
6967 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
6968 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
6969 if (RT_SUCCESS(rc))
6970 {
6971 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
6972 Assert(pMsr);
6973 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6974 {
6975 if ( !pMsr->u32Reserved
6976 && pMsr->u32Msr != MSR_K8_FS_BASE
6977 && pMsr->u32Msr != MSR_K8_GS_BASE
6978 && pMsr->u32Msr != MSR_K6_EFER
6979 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6980 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6981 {
6982 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6983 if (rcStrict == VINF_SUCCESS)
6984 continue;
6985
6986 /*
6987 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6988 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6989 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
6990 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6991 * MSR in ring-0 if possible, or come up with a better, generic solution.
6992 */
6993 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6994 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6995 ? kVmxVDiag_Vmentry_MsrLoadRing3
6996 : kVmxVDiag_Vmentry_MsrLoad;
6997 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6998 }
6999 else
7000 {
7001 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7003 }
7004 }
7005 }
7006 else
7007 {
7008 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
7009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7010 }
7011
7012 NOREF(pszInstr);
7013 NOREF(pszFailure);
7014 return VINF_SUCCESS;
7015}
7016
7017
7018/**
7019 * Loads the guest-state non-register state as part of VM-entry.
7020 *
7021 * @returns VBox status code.
7022 * @param pVCpu The cross context virtual CPU structure.
7023 *
7024 * @remarks This must be called only after loading the nested-guest register state
7025 * (especially nested-guest RIP).
7026 */
7027IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7028{
7029 /*
7030 * Load guest non-register state.
7031 * See Intel spec. 26.6 "Special Features of VM Entry"
7032 */
7033 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7034
7035 /*
7036 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7037 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7038 *
7039 * See Intel spec. 26.6.1 "Interruptibility State".
7040 */
7041 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7042 if ( !fEntryVectoring
7043 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7044 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7045 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7046 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7047
7048 /* NMI blocking. */
7049 if ( (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7050 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7051 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7052
7053 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7054
7055 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7056 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7057
7058 /* VPID is irrelevant. We don't support VPID yet. */
7059
7060 /* Clear address-range monitoring. */
7061 EMMonitorWaitClear(pVCpu);
7062}
7063
7064
7065/**
7066 * Loads the guest-state as part of VM-entry.
7067 *
7068 * @returns VBox status code.
7069 * @param pVCpu The cross context virtual CPU structure.
7070 * @param pszInstr The VMX instruction name (for logging purposes).
7071 *
7072 * @remarks This must be done after all the necessary steps prior to loading of
7073 * guest-state (e.g. checking various VMCS state).
7074 */
7075IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7076{
7077 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7078 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7079
7080 /*
7081 * Load guest RIP, RSP and RFLAGS.
7082 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7083 */
7084 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7085 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7086 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7087 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7088
7089 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7090 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7091 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7092
7093 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7094
7095 NOREF(pszInstr);
7096 return VINF_SUCCESS;
7097}
7098
7099
7100/**
7101 * Returns whether there are is a pending debug exception on VM-entry.
7102 *
7103 * @param pVCpu The cross context virtual CPU structure.
7104 * @param pszInstr The VMX instruction name (for logging purposes).
7105 */
7106IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7107{
7108 /*
7109 * Pending debug exceptions.
7110 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7111 */
7112 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7113 Assert(pVmcs);
7114
7115 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7116 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7117 if (fPendingDbgXcpt)
7118 {
7119 uint8_t uEntryIntInfoType;
7120 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7121 if (fEntryVectoring)
7122 {
7123 switch (uEntryIntInfoType)
7124 {
7125 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7126 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7127 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7128 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7129 fPendingDbgXcpt = false;
7130 break;
7131
7132 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7133 {
7134 /*
7135 * Whether the pending debug exception for software exceptions other than
7136 * #BP and #OF is delivered after injecting the exception or is discard
7137 * is CPU implementation specific. We will discard them (easier).
7138 */
7139 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7140 if ( uVector != X86_XCPT_BP
7141 && uVector != X86_XCPT_OF)
7142 fPendingDbgXcpt = false;
7143 RT_FALL_THRU();
7144 }
7145 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7146 {
7147 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7148 fPendingDbgXcpt = false;
7149 break;
7150 }
7151 }
7152 }
7153 else
7154 {
7155 /*
7156 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7157 * pending debug exception is held pending or is discarded is CPU implementation
7158 * specific. We will discard them (easier).
7159 */
7160 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7161 fPendingDbgXcpt = false;
7162
7163 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7164 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7165 fPendingDbgXcpt = false;
7166 }
7167 }
7168
7169 NOREF(pszInstr);
7170 return fPendingDbgXcpt;
7171}
7172
7173
7174/**
7175 * Set up the monitor-trap flag (MTF).
7176 *
7177 * @param pVCpu The cross context virtual CPU structure.
7178 * @param pszInstr The VMX instruction name (for logging purposes).
7179 */
7180IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7181{
7182 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7183 Assert(pVmcs);
7184 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7185 {
7186 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7187 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7188 }
7189 else
7190 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7191 NOREF(pszInstr);
7192}
7193
7194
7195/**
7196 * Set up the VMX-preemption timer.
7197 *
7198 * @param pVCpu The cross context virtual CPU structure.
7199 * @param pszInstr The VMX instruction name (for logging purposes).
7200 */
7201IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7202{
7203 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7204 Assert(pVmcs);
7205 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7206 {
7207 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7208 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7209 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7210
7211 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7212 }
7213 else
7214 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7215
7216 NOREF(pszInstr);
7217}
7218
7219
7220/**
7221 * Injects an event using TRPM given a VM-entry interruption info. and related
7222 * fields.
7223 *
7224 * @returns VBox status code.
7225 * @param pVCpu The cross context virtual CPU structure.
7226 * @param uEntryIntInfo The VM-entry interruption info.
7227 * @param uErrCode The error code associated with the event if any.
7228 * @param cbInstr The VM-entry instruction length (for software
7229 * interrupts and software exceptions). Pass 0
7230 * otherwise.
7231 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7232 */
7233IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7234 RTGCUINTPTR GCPtrFaultAddress)
7235{
7236 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7237
7238 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7239 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7240 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7241
7242 TRPMEVENT enmTrapType;
7243 switch (uType)
7244 {
7245 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7246 enmTrapType = TRPM_HARDWARE_INT;
7247 break;
7248
7249 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7250 enmTrapType = TRPM_SOFTWARE_INT;
7251 break;
7252
7253 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7254 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
7255 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7256 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7257 enmTrapType = TRPM_TRAP;
7258 break;
7259
7260 default:
7261 /* Shouldn't really happen. */
7262 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7263 break;
7264 }
7265
7266 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7267 AssertRCReturn(rc, rc);
7268
7269 if (fErrCodeValid)
7270 TRPMSetErrorCode(pVCpu, uErrCode);
7271
7272 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7273 && uVector == X86_XCPT_PF)
7274 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7275 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7276 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7277 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7278 {
7279 AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7280 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7281 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
7282 TRPMSetInstrLength(pVCpu, cbInstr);
7283 }
7284
7285 return VINF_SUCCESS;
7286}
7287
7288
7289/**
7290 * Performs event injection (if any) as part of VM-entry.
7291 *
7292 * @param pVCpu The cross context virtual CPU structure.
7293 * @param pszInstr The VMX instruction name (for logging purposes).
7294 */
7295IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7296{
7297 /*
7298 * Inject events.
7299 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7300 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7301 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7302 * the actually delivery of this event.
7303 *
7304 * See Intel spec. 26.5 "Event Injection".
7305 */
7306 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7307 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7308 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7309
7310 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7311 if (fEntryIntInfoValid)
7312 {
7313 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7314 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7315 {
7316 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7317 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7318 return VINF_SUCCESS;
7319 }
7320
7321 return iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7322 pVCpu->cpum.GstCtx.cr2);
7323 }
7324
7325 /*
7326 * Inject any pending guest debug exception.
7327 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7328 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7329 */
7330 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7331 if (fPendingDbgXcpt)
7332 {
7333 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7334 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7335 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7336 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7337 0 /* GCPtrFaultAddress */);
7338 }
7339
7340 NOREF(pszInstr);
7341 return VINF_SUCCESS;
7342}
7343
7344
7345/**
7346 * Initializes all read-only VMCS fields as part of VM-entry.
7347 *
7348 * @param pVCpu The cross context virtual CPU structure.
7349 */
7350IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7351{
7352 /*
7353 * Any VMCS field which we do not establish on every VM-exit but may potentially
7354 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7355 * specified to be undefined needs to be initialized here.
7356 *
7357 * Thus, it is especially important to clear the VM-exit qualification field
7358 * since it must be zero for VM-exits where it is not used. Similarly, the
7359 * VM-exit interruption information field's valid bit needs to be cleared for
7360 * the same reasons.
7361 */
7362 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7363 Assert(pVmcs);
7364
7365 /* 16-bit (none currently). */
7366 /* 32-bit. */
7367 pVmcs->u32RoVmInstrError = 0;
7368 pVmcs->u32RoExitReason = 0;
7369 pVmcs->u32RoExitIntInfo = 0;
7370 pVmcs->u32RoExitIntErrCode = 0;
7371 pVmcs->u32RoIdtVectoringInfo = 0;
7372 pVmcs->u32RoIdtVectoringErrCode = 0;
7373 pVmcs->u32RoExitInstrLen = 0;
7374 pVmcs->u32RoExitInstrInfo = 0;
7375
7376 /* 64-bit. */
7377 pVmcs->u64RoGuestPhysAddr.u = 0;
7378
7379 /* Natural-width. */
7380 pVmcs->u64RoExitQual.u = 0;
7381 pVmcs->u64RoIoRcx.u = 0;
7382 pVmcs->u64RoIoRsi.u = 0;
7383 pVmcs->u64RoIoRdi.u = 0;
7384 pVmcs->u64RoIoRip.u = 0;
7385 pVmcs->u64RoGuestLinearAddr.u = 0;
7386}
7387
7388
7389/**
7390 * VMLAUNCH/VMRESUME instruction execution worker.
7391 *
7392 * @returns Strict VBox status code.
7393 * @param pVCpu The cross context virtual CPU structure.
7394 * @param cbInstr The instruction length in bytes.
7395 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7396 * VMXINSTRID_VMRESUME).
7397 *
7398 * @remarks Common VMX instruction checks are already expected to by the caller,
7399 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7400 */
7401IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7402{
7403# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7404 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7405 return VINF_EM_RAW_EMULATE_INSTR;
7406# else
7407 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7408 || uInstrId == VMXINSTRID_VMRESUME);
7409 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7410
7411 /* Nested-guest intercept. */
7412 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7413 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7414
7415 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7416
7417 /*
7418 * Basic VM-entry checks.
7419 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7420 * The checks following that do not have to follow a specific order.
7421 *
7422 * See Intel spec. 26.1 "Basic VM-entry Checks".
7423 */
7424
7425 /* CPL. */
7426 if (pVCpu->iem.s.uCpl == 0)
7427 { /* likely */ }
7428 else
7429 {
7430 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7431 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7432 return iemRaiseGeneralProtectionFault0(pVCpu);
7433 }
7434
7435 /* Current VMCS valid. */
7436 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7437 { /* likely */ }
7438 else
7439 {
7440 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7441 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7442 iemVmxVmFailInvalid(pVCpu);
7443 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7444 return VINF_SUCCESS;
7445 }
7446
7447 /* Current VMCS is not a shadow VMCS. */
7448 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7449 { /* likely */ }
7450 else
7451 {
7452 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7454 iemVmxVmFailInvalid(pVCpu);
7455 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7456 return VINF_SUCCESS;
7457 }
7458
7459 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7460 * use block-by-STI here which is not quite correct. */
7461 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7462 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7463 { /* likely */ }
7464 else
7465 {
7466 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7467 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7468 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7469 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7470 return VINF_SUCCESS;
7471 }
7472
7473 if (uInstrId == VMXINSTRID_VMLAUNCH)
7474 {
7475 /* VMLAUNCH with non-clear VMCS. */
7476 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
7477 { /* likely */ }
7478 else
7479 {
7480 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7481 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7482 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7483 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7484 return VINF_SUCCESS;
7485 }
7486 }
7487 else
7488 {
7489 /* VMRESUME with non-launched VMCS. */
7490 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
7491 { /* likely */ }
7492 else
7493 {
7494 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7496 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7498 return VINF_SUCCESS;
7499 }
7500 }
7501
7502 /*
7503 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7504 * while entering VMX non-root mode. We do some of this while checking VM-execution
7505 * controls. The guest hypervisor should not make assumptions and cannot expect
7506 * predictable behavior if changes to these structures are made in guest memory while
7507 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7508 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7509 *
7510 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7511 */
7512 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7513 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7514 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7515 if (RT_SUCCESS(rc))
7516 {
7517 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7518 if (RT_SUCCESS(rc))
7519 {
7520 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7521 if (RT_SUCCESS(rc))
7522 {
7523 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7524 if (RT_SUCCESS(rc))
7525 {
7526 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7527 iemVmxVmentryInitReadOnlyFields(pVCpu);
7528
7529 /*
7530 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7531 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7532 * VM-exit when required.
7533 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7534 */
7535 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7536
7537 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7538 if (RT_SUCCESS(rc))
7539 {
7540 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7541 if (RT_SUCCESS(rc))
7542 {
7543 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7544 if (RT_SUCCESS(rc))
7545 {
7546 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7547
7548 /* VMLAUNCH instruction must update the VMCS launch state. */
7549 if (uInstrId == VMXINSTRID_VMLAUNCH)
7550 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
7551
7552 /* Perform the VMX transition (PGM updates). */
7553 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7554 if (rcStrict == VINF_SUCCESS)
7555 { /* likely */ }
7556 else if (RT_SUCCESS(rcStrict))
7557 {
7558 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7559 VBOXSTRICTRC_VAL(rcStrict)));
7560 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7561 }
7562 else
7563 {
7564 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7565 return rcStrict;
7566 }
7567
7568 /* We've now entered nested-guest execution. */
7569 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7570
7571 /*
7572 * The priority of potential VM-exits during VM-entry is important.
7573 * The priorities of VM-exits and events are listed from highest
7574 * to lowest as follows:
7575 *
7576 * 1. Event injection.
7577 * 2. Trap on task-switch (T flag set in TSS).
7578 * 3. TPR below threshold / APIC-write.
7579 * 4. SMI, INIT.
7580 * 5. MTF exit.
7581 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7582 * 7. VMX-preemption timer.
7583 * 9. NMI-window exit.
7584 * 10. NMI injection.
7585 * 11. Interrupt-window exit.
7586 * 12. Virtual-interrupt injection.
7587 * 13. Interrupt injection.
7588 * 14. Process next instruction (fetch, decode, execute).
7589 */
7590
7591 /* Setup the VMX-preemption timer. */
7592 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7593
7594 /* Setup monitor-trap flag. */
7595 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7596
7597 /* Now that we've switched page tables, we can go ahead and inject any event. */
7598 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7599 if (RT_SUCCESS(rcStrict))
7600 {
7601 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7602 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr, VINF_SUCCESS);
7603 }
7604
7605 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7606 return rcStrict;
7607 }
7608 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7609 }
7610 }
7611 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7612 }
7613
7614 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7615 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7616 return VINF_SUCCESS;
7617 }
7618 }
7619 }
7620
7621 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7622 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7623 return VINF_SUCCESS;
7624# endif
7625}
7626
7627
7628/**
7629 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7630 * (causes a VM-exit) or not.
7631 *
7632 * @returns @c true if the instruction is intercepted, @c false otherwise.
7633 * @param pVCpu The cross context virtual CPU structure.
7634 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7635 * VMX_EXIT_WRMSR).
7636 * @param idMsr The MSR.
7637 */
7638IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7639{
7640 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7641 Assert( uExitReason == VMX_EXIT_RDMSR
7642 || uExitReason == VMX_EXIT_WRMSR);
7643
7644 /* Consult the MSR bitmap if the feature is supported. */
7645 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7646 Assert(pVmcs);
7647 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7648 {
7649 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7650 if (uExitReason == VMX_EXIT_RDMSR)
7651 {
7652 VMXMSREXITREAD enmRead;
7653 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7654 NULL /* penmWrite */);
7655 AssertRC(rc);
7656 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7657 return true;
7658 }
7659 else
7660 {
7661 VMXMSREXITWRITE enmWrite;
7662 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7663 &enmWrite);
7664 AssertRC(rc);
7665 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7666 return true;
7667 }
7668 return false;
7669 }
7670
7671 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7672 return true;
7673}
7674
7675
7676/**
7677 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7678 * intercepted (causes a VM-exit) or not.
7679 *
7680 * @returns @c true if the instruction is intercepted, @c false otherwise.
7681 * @param pVCpu The cross context virtual CPU structure.
7682 * @param u64FieldEnc The VMCS field encoding.
7683 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7684 * VMX_EXIT_VMREAD).
7685 */
7686IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7687{
7688 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7689 Assert( uExitReason == VMX_EXIT_VMREAD
7690 || uExitReason == VMX_EXIT_VMWRITE);
7691
7692 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7693 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7694 return true;
7695
7696 /*
7697 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7698 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7699 */
7700 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7701 return true;
7702
7703 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7704 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7705 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7706 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7707 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7708 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7709 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7710 pbBitmap += (u32FieldEnc >> 3);
7711 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7712 return true;
7713
7714 return false;
7715}
7716
7717
7718/**
7719 * VMREAD common (memory/register) instruction execution worker
7720 *
7721 * @returns Strict VBox status code.
7722 * @param pVCpu The cross context virtual CPU structure.
7723 * @param cbInstr The instruction length in bytes.
7724 * @param pu64Dst Where to write the VMCS value (only updated when
7725 * VINF_SUCCESS is returned).
7726 * @param u64FieldEnc The VMCS field encoding.
7727 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7728 * be NULL.
7729 */
7730IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7731 PCVMXVEXITINFO pExitInfo)
7732{
7733 /* Nested-guest intercept. */
7734 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7735 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7736 {
7737 if (pExitInfo)
7738 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7739 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7740 }
7741
7742 /* CPL. */
7743 if (pVCpu->iem.s.uCpl == 0)
7744 { /* likely */ }
7745 else
7746 {
7747 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7748 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7749 return iemRaiseGeneralProtectionFault0(pVCpu);
7750 }
7751
7752 /* VMCS pointer in root mode. */
7753 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7754 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7755 { /* likely */ }
7756 else
7757 {
7758 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7759 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7760 iemVmxVmFailInvalid(pVCpu);
7761 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7762 return VINF_SUCCESS;
7763 }
7764
7765 /* VMCS-link pointer in non-root mode. */
7766 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7767 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7768 { /* likely */ }
7769 else
7770 {
7771 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7773 iemVmxVmFailInvalid(pVCpu);
7774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7775 return VINF_SUCCESS;
7776 }
7777
7778 /* Supported VMCS field. */
7779 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7780 { /* likely */ }
7781 else
7782 {
7783 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7784 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7785 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7786 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7787 return VINF_SUCCESS;
7788 }
7789
7790 /*
7791 * Setup reading from the current or shadow VMCS.
7792 */
7793 uint8_t *pbVmcs;
7794 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7795 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7796 else
7797 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7798 Assert(pbVmcs);
7799
7800 VMXVMCSFIELDENC FieldEnc;
7801 FieldEnc.u = u64FieldEnc;
7802 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7803 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7804 uint8_t const uWidthType = (uWidth << 2) | uType;
7805 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7806 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7807 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7808 Assert(offField < VMX_V_VMCS_SIZE);
7809
7810 /*
7811 * Read the VMCS component based on the field's effective width.
7812 *
7813 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7814 * indicates high bits (little endian).
7815 *
7816 * Note! The caller is responsible to trim the result and update registers
7817 * or memory locations are required. Here we just zero-extend to the largest
7818 * type (i.e. 64-bits).
7819 */
7820 uint8_t *pbField = pbVmcs + offField;
7821 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7822 switch (uEffWidth)
7823 {
7824 case VMX_VMCS_ENC_WIDTH_64BIT:
7825 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7826 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7827 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7828 }
7829 return VINF_SUCCESS;
7830}
7831
7832
7833/**
7834 * VMREAD (64-bit register) instruction execution worker.
7835 *
7836 * @returns Strict VBox status code.
7837 * @param pVCpu The cross context virtual CPU structure.
7838 * @param cbInstr The instruction length in bytes.
7839 * @param pu64Dst Where to store the VMCS field's value.
7840 * @param u64FieldEnc The VMCS field encoding.
7841 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7842 * be NULL.
7843 */
7844IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7845 PCVMXVEXITINFO pExitInfo)
7846{
7847 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7848 if (rcStrict == VINF_SUCCESS)
7849 {
7850 iemVmxVmreadSuccess(pVCpu, cbInstr);
7851 return VINF_SUCCESS;
7852 }
7853
7854 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7855 return rcStrict;
7856}
7857
7858
7859/**
7860 * VMREAD (32-bit register) instruction execution worker.
7861 *
7862 * @returns Strict VBox status code.
7863 * @param pVCpu The cross context virtual CPU structure.
7864 * @param cbInstr The instruction length in bytes.
7865 * @param pu32Dst Where to store the VMCS field's value.
7866 * @param u32FieldEnc The VMCS field encoding.
7867 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7868 * be NULL.
7869 */
7870IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7871 PCVMXVEXITINFO pExitInfo)
7872{
7873 uint64_t u64Dst;
7874 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7875 if (rcStrict == VINF_SUCCESS)
7876 {
7877 *pu32Dst = u64Dst;
7878 iemVmxVmreadSuccess(pVCpu, cbInstr);
7879 return VINF_SUCCESS;
7880 }
7881
7882 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7883 return rcStrict;
7884}
7885
7886
7887/**
7888 * VMREAD (memory) instruction execution worker.
7889 *
7890 * @returns Strict VBox status code.
7891 * @param pVCpu The cross context virtual CPU structure.
7892 * @param cbInstr The instruction length in bytes.
7893 * @param iEffSeg The effective segment register to use with @a u64Val.
7894 * Pass UINT8_MAX if it is a register access.
7895 * @param enmEffAddrMode The effective addressing mode (only used with memory
7896 * operand).
7897 * @param GCPtrDst The guest linear address to store the VMCS field's
7898 * value.
7899 * @param u64FieldEnc The VMCS field encoding.
7900 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7901 * be NULL.
7902 */
7903IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7904 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7905{
7906 uint64_t u64Dst;
7907 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7908 if (rcStrict == VINF_SUCCESS)
7909 {
7910 /*
7911 * Write the VMCS field's value to the location specified in guest-memory.
7912 *
7913 * The pointer size depends on the address size (address-size prefix allowed).
7914 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7915 */
7916 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7917 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7918 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7919
7920 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7921 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7922 else
7923 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7924 if (rcStrict == VINF_SUCCESS)
7925 {
7926 iemVmxVmreadSuccess(pVCpu, cbInstr);
7927 return VINF_SUCCESS;
7928 }
7929
7930 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7931 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7932 return rcStrict;
7933 }
7934
7935 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7936 return rcStrict;
7937}
7938
7939
7940/**
7941 * VMWRITE instruction execution worker.
7942 *
7943 * @returns Strict VBox status code.
7944 * @param pVCpu The cross context virtual CPU structure.
7945 * @param cbInstr The instruction length in bytes.
7946 * @param iEffSeg The effective segment register to use with @a u64Val.
7947 * Pass UINT8_MAX if it is a register access.
7948 * @param enmEffAddrMode The effective addressing mode (only used with memory
7949 * operand).
7950 * @param u64Val The value to write (or guest linear address to the
7951 * value), @a iEffSeg will indicate if it's a memory
7952 * operand.
7953 * @param u64FieldEnc The VMCS field encoding.
7954 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7955 * be NULL.
7956 */
7957IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7958 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7959{
7960 /* Nested-guest intercept. */
7961 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7962 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7963 {
7964 if (pExitInfo)
7965 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7966 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7967 }
7968
7969 /* CPL. */
7970 if (pVCpu->iem.s.uCpl == 0)
7971 { /* likely */ }
7972 else
7973 {
7974 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7975 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7976 return iemRaiseGeneralProtectionFault0(pVCpu);
7977 }
7978
7979 /* VMCS pointer in root mode. */
7980 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7981 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7982 { /* likely */ }
7983 else
7984 {
7985 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7986 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7987 iemVmxVmFailInvalid(pVCpu);
7988 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7989 return VINF_SUCCESS;
7990 }
7991
7992 /* VMCS-link pointer in non-root mode. */
7993 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7994 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7995 { /* likely */ }
7996 else
7997 {
7998 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7999 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8000 iemVmxVmFailInvalid(pVCpu);
8001 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8002 return VINF_SUCCESS;
8003 }
8004
8005 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8006 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8007 if (!fIsRegOperand)
8008 {
8009 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8010 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8011 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8012
8013 /* Read the value from the specified guest memory location. */
8014 VBOXSTRICTRC rcStrict;
8015 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8016 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8017 else
8018 {
8019 uint32_t u32Val;
8020 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8021 u64Val = u32Val;
8022 }
8023 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8024 {
8025 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8026 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8027 return rcStrict;
8028 }
8029 }
8030 else
8031 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8032
8033 /* Supported VMCS field. */
8034 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8035 { /* likely */ }
8036 else
8037 {
8038 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8039 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8040 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8041 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8042 return VINF_SUCCESS;
8043 }
8044
8045 /* Read-only VMCS field. */
8046 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8047 if ( !fIsFieldReadOnly
8048 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8049 { /* likely */ }
8050 else
8051 {
8052 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8053 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8054 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8055 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8056 return VINF_SUCCESS;
8057 }
8058
8059 /*
8060 * Setup writing to the current or shadow VMCS.
8061 */
8062 uint8_t *pbVmcs;
8063 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8064 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8065 else
8066 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8067 Assert(pbVmcs);
8068
8069 VMXVMCSFIELDENC FieldEnc;
8070 FieldEnc.u = u64FieldEnc;
8071 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8072 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8073 uint8_t const uWidthType = (uWidth << 2) | uType;
8074 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8075 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8076 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8077 Assert(offField < VMX_V_VMCS_SIZE);
8078
8079 /*
8080 * Write the VMCS component based on the field's effective width.
8081 *
8082 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8083 * indicates high bits (little endian).
8084 */
8085 uint8_t *pbField = pbVmcs + offField;
8086 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8087 switch (uEffWidth)
8088 {
8089 case VMX_VMCS_ENC_WIDTH_64BIT:
8090 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8091 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8092 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8093 }
8094
8095 iemVmxVmSucceed(pVCpu);
8096 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8097 return VINF_SUCCESS;
8098}
8099
8100
8101/**
8102 * VMCLEAR instruction execution worker.
8103 *
8104 * @returns Strict VBox status code.
8105 * @param pVCpu The cross context virtual CPU structure.
8106 * @param cbInstr The instruction length in bytes.
8107 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8108 * @param GCPtrVmcs The linear address of the VMCS pointer.
8109 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8110 * be NULL.
8111 *
8112 * @remarks Common VMX instruction checks are already expected to by the caller,
8113 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8114 */
8115IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8116 PCVMXVEXITINFO pExitInfo)
8117{
8118 /* Nested-guest intercept. */
8119 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8120 {
8121 if (pExitInfo)
8122 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8123 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8124 }
8125
8126 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8127
8128 /* CPL. */
8129 if (pVCpu->iem.s.uCpl == 0)
8130 { /* likely */ }
8131 else
8132 {
8133 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8134 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8135 return iemRaiseGeneralProtectionFault0(pVCpu);
8136 }
8137
8138 /* Get the VMCS pointer from the location specified by the source memory operand. */
8139 RTGCPHYS GCPhysVmcs;
8140 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8141 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8142 { /* likely */ }
8143 else
8144 {
8145 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8146 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8147 return rcStrict;
8148 }
8149
8150 /* VMCS pointer alignment. */
8151 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8152 { /* likely */ }
8153 else
8154 {
8155 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8157 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8158 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8159 return VINF_SUCCESS;
8160 }
8161
8162 /* VMCS physical-address width limits. */
8163 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8164 { /* likely */ }
8165 else
8166 {
8167 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8168 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8169 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8170 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8171 return VINF_SUCCESS;
8172 }
8173
8174 /* VMCS is not the VMXON region. */
8175 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8176 { /* likely */ }
8177 else
8178 {
8179 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8180 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8181 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8182 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8183 return VINF_SUCCESS;
8184 }
8185
8186 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8187 restriction imposed by our implementation. */
8188 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8189 { /* likely */ }
8190 else
8191 {
8192 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8193 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8194 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8195 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8196 return VINF_SUCCESS;
8197 }
8198
8199 /*
8200 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8201 *
8202 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8203 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8204 * to 'clear'.
8205 */
8206 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
8207 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8208 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8209 {
8210 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8211 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8212 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
8213 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8214 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8215 }
8216 else
8217 {
8218 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsStateClear));
8219 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8220 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
8221 if (RT_FAILURE(rcStrict))
8222 return rcStrict;
8223 }
8224
8225 iemVmxVmSucceed(pVCpu);
8226 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8227 return VINF_SUCCESS;
8228}
8229
8230
8231/**
8232 * VMPTRST instruction execution worker.
8233 *
8234 * @returns Strict VBox status code.
8235 * @param pVCpu The cross context virtual CPU structure.
8236 * @param cbInstr The instruction length in bytes.
8237 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8238 * @param GCPtrVmcs The linear address of where to store the current VMCS
8239 * pointer.
8240 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8241 * be NULL.
8242 *
8243 * @remarks Common VMX instruction checks are already expected to by the caller,
8244 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8245 */
8246IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8247 PCVMXVEXITINFO pExitInfo)
8248{
8249 /* Nested-guest intercept. */
8250 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8251 {
8252 if (pExitInfo)
8253 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8254 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8255 }
8256
8257 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8258
8259 /* CPL. */
8260 if (pVCpu->iem.s.uCpl == 0)
8261 { /* likely */ }
8262 else
8263 {
8264 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8265 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8266 return iemRaiseGeneralProtectionFault0(pVCpu);
8267 }
8268
8269 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8270 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8271 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8272 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8273 {
8274 iemVmxVmSucceed(pVCpu);
8275 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8276 return rcStrict;
8277 }
8278
8279 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8280 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8281 return rcStrict;
8282}
8283
8284
8285/**
8286 * VMPTRLD instruction execution worker.
8287 *
8288 * @returns Strict VBox status code.
8289 * @param pVCpu The cross context virtual CPU structure.
8290 * @param cbInstr The instruction length in bytes.
8291 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8292 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8293 * be NULL.
8294 *
8295 * @remarks Common VMX instruction checks are already expected to by the caller,
8296 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8297 */
8298IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8299 PCVMXVEXITINFO pExitInfo)
8300{
8301 /* Nested-guest intercept. */
8302 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8303 {
8304 if (pExitInfo)
8305 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8306 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8307 }
8308
8309 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8310
8311 /* CPL. */
8312 if (pVCpu->iem.s.uCpl == 0)
8313 { /* likely */ }
8314 else
8315 {
8316 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8317 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8318 return iemRaiseGeneralProtectionFault0(pVCpu);
8319 }
8320
8321 /* Get the VMCS pointer from the location specified by the source memory operand. */
8322 RTGCPHYS GCPhysVmcs;
8323 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8324 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8325 { /* likely */ }
8326 else
8327 {
8328 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8329 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8330 return rcStrict;
8331 }
8332
8333 /* VMCS pointer alignment. */
8334 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8335 { /* likely */ }
8336 else
8337 {
8338 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8339 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8340 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8341 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8342 return VINF_SUCCESS;
8343 }
8344
8345 /* VMCS physical-address width limits. */
8346 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8347 { /* likely */ }
8348 else
8349 {
8350 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8351 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8352 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8353 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8354 return VINF_SUCCESS;
8355 }
8356
8357 /* VMCS is not the VMXON region. */
8358 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8359 { /* likely */ }
8360 else
8361 {
8362 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8363 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8364 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8365 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8366 return VINF_SUCCESS;
8367 }
8368
8369 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8370 restriction imposed by our implementation. */
8371 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8372 { /* likely */ }
8373 else
8374 {
8375 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8377 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8378 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8379 return VINF_SUCCESS;
8380 }
8381
8382 /* Read just the VMCS revision from the VMCS. */
8383 VMXVMCSREVID VmcsRevId;
8384 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8385 if (RT_SUCCESS(rc))
8386 { /* likely */ }
8387 else
8388 {
8389 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8390 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8391 return rc;
8392 }
8393
8394 /*
8395 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8396 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8397 */
8398 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8399 && ( !VmcsRevId.n.fIsShadowVmcs
8400 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8401 { /* likely */ }
8402 else
8403 {
8404 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8405 {
8406 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8407 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8408 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8409 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8410 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8411 return VINF_SUCCESS;
8412 }
8413
8414 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8416 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8417 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8418 return VINF_SUCCESS;
8419 }
8420
8421 /*
8422 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8423 * the cache of an existing, current VMCS back to guest memory before loading a new,
8424 * different current VMCS.
8425 */
8426 bool fLoadVmcsFromMem;
8427 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8428 {
8429 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8430 {
8431 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8432 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8433 fLoadVmcsFromMem = true;
8434 }
8435 else
8436 fLoadVmcsFromMem = false;
8437 }
8438 else
8439 fLoadVmcsFromMem = true;
8440
8441 if (fLoadVmcsFromMem)
8442 {
8443 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8444 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8445 sizeof(VMXVVMCS));
8446 if (RT_SUCCESS(rc))
8447 { /* likely */ }
8448 else
8449 {
8450 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8451 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8452 return rc;
8453 }
8454 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8455 }
8456
8457 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8458 iemVmxVmSucceed(pVCpu);
8459 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8460 return VINF_SUCCESS;
8461}
8462
8463
8464/**
8465 * VMXON instruction execution worker.
8466 *
8467 * @returns Strict VBox status code.
8468 * @param pVCpu The cross context virtual CPU structure.
8469 * @param cbInstr The instruction length in bytes.
8470 * @param iEffSeg The effective segment register to use with @a
8471 * GCPtrVmxon.
8472 * @param GCPtrVmxon The linear address of the VMXON pointer.
8473 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8474 * Optional, can be NULL.
8475 *
8476 * @remarks Common VMX instruction checks are already expected to by the caller,
8477 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8478 */
8479IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8480 PCVMXVEXITINFO pExitInfo)
8481{
8482 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8483 {
8484 /* CPL. */
8485 if (pVCpu->iem.s.uCpl == 0)
8486 { /* likely */ }
8487 else
8488 {
8489 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8490 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8491 return iemRaiseGeneralProtectionFault0(pVCpu);
8492 }
8493
8494 /* A20M (A20 Masked) mode. */
8495 if (PGMPhysIsA20Enabled(pVCpu))
8496 { /* likely */ }
8497 else
8498 {
8499 Log(("vmxon: A20M mode -> #GP(0)\n"));
8500 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8501 return iemRaiseGeneralProtectionFault0(pVCpu);
8502 }
8503
8504 /* CR0. */
8505 {
8506 /* CR0 MB1 bits. */
8507 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8508 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8509 { /* likely */ }
8510 else
8511 {
8512 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8513 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8514 return iemRaiseGeneralProtectionFault0(pVCpu);
8515 }
8516
8517 /* CR0 MBZ bits. */
8518 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8519 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8520 { /* likely */ }
8521 else
8522 {
8523 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8525 return iemRaiseGeneralProtectionFault0(pVCpu);
8526 }
8527 }
8528
8529 /* CR4. */
8530 {
8531 /* CR4 MB1 bits. */
8532 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8533 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8534 { /* likely */ }
8535 else
8536 {
8537 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8538 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8539 return iemRaiseGeneralProtectionFault0(pVCpu);
8540 }
8541
8542 /* CR4 MBZ bits. */
8543 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8544 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8545 { /* likely */ }
8546 else
8547 {
8548 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8550 return iemRaiseGeneralProtectionFault0(pVCpu);
8551 }
8552 }
8553
8554 /* Feature control MSR's LOCK and VMXON bits. */
8555 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8556 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8557 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8558 { /* likely */ }
8559 else
8560 {
8561 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8563 return iemRaiseGeneralProtectionFault0(pVCpu);
8564 }
8565
8566 /* Get the VMXON pointer from the location specified by the source memory operand. */
8567 RTGCPHYS GCPhysVmxon;
8568 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8569 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8570 { /* likely */ }
8571 else
8572 {
8573 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8574 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8575 return rcStrict;
8576 }
8577
8578 /* VMXON region pointer alignment. */
8579 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8580 { /* likely */ }
8581 else
8582 {
8583 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8584 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8585 iemVmxVmFailInvalid(pVCpu);
8586 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8587 return VINF_SUCCESS;
8588 }
8589
8590 /* VMXON physical-address width limits. */
8591 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8592 { /* likely */ }
8593 else
8594 {
8595 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8596 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8597 iemVmxVmFailInvalid(pVCpu);
8598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8599 return VINF_SUCCESS;
8600 }
8601
8602 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8603 restriction imposed by our implementation. */
8604 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8605 { /* likely */ }
8606 else
8607 {
8608 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8609 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8610 iemVmxVmFailInvalid(pVCpu);
8611 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8612 return VINF_SUCCESS;
8613 }
8614
8615 /* Read the VMCS revision ID from the VMXON region. */
8616 VMXVMCSREVID VmcsRevId;
8617 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8618 if (RT_SUCCESS(rc))
8619 { /* likely */ }
8620 else
8621 {
8622 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8623 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8624 return rc;
8625 }
8626
8627 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8628 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8629 { /* likely */ }
8630 else
8631 {
8632 /* Revision ID mismatch. */
8633 if (!VmcsRevId.n.fIsShadowVmcs)
8634 {
8635 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8636 VmcsRevId.n.u31RevisionId));
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8638 iemVmxVmFailInvalid(pVCpu);
8639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8640 return VINF_SUCCESS;
8641 }
8642
8643 /* Shadow VMCS disallowed. */
8644 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8645 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8646 iemVmxVmFailInvalid(pVCpu);
8647 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8648 return VINF_SUCCESS;
8649 }
8650
8651 /*
8652 * Record that we're in VMX operation, block INIT, block and disable A20M.
8653 */
8654 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8655 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8657
8658 /* Clear address-range monitoring. */
8659 EMMonitorWaitClear(pVCpu);
8660 /** @todo NSTVMX: Intel PT. */
8661
8662 iemVmxVmSucceed(pVCpu);
8663 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8664 return VINF_SUCCESS;
8665 }
8666 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8667 {
8668 /* Nested-guest intercept. */
8669 if (pExitInfo)
8670 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8671 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8672 }
8673
8674 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8675
8676 /* CPL. */
8677 if (pVCpu->iem.s.uCpl > 0)
8678 {
8679 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8681 return iemRaiseGeneralProtectionFault0(pVCpu);
8682 }
8683
8684 /* VMXON when already in VMX root mode. */
8685 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8686 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8688 return VINF_SUCCESS;
8689}
8690
8691
8692/**
8693 * Implements 'VMXOFF'.
8694 *
8695 * @remarks Common VMX instruction checks are already expected to by the caller,
8696 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8697 */
8698IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8699{
8700 /* Nested-guest intercept. */
8701 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8702 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8703
8704 /* CPL. */
8705 if (pVCpu->iem.s.uCpl == 0)
8706 { /* likely */ }
8707 else
8708 {
8709 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8710 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8711 return iemRaiseGeneralProtectionFault0(pVCpu);
8712 }
8713
8714 /* Dual monitor treatment of SMIs and SMM. */
8715 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8716 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8717 { /* likely */ }
8718 else
8719 {
8720 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8721 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8722 return VINF_SUCCESS;
8723 }
8724
8725 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8726 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8727 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8728
8729 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8730 { /** @todo NSTVMX: Unblock SMI. */ }
8731
8732 EMMonitorWaitClear(pVCpu);
8733 /** @todo NSTVMX: Unblock and enable A20M. */
8734
8735 iemVmxVmSucceed(pVCpu);
8736 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8737 return VINF_SUCCESS;
8738}
8739
8740
8741/**
8742 * Implements 'VMXON'.
8743 */
8744IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8745{
8746 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8747}
8748
8749
8750/**
8751 * Implements 'VMLAUNCH'.
8752 */
8753IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8754{
8755 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8756}
8757
8758
8759/**
8760 * Implements 'VMRESUME'.
8761 */
8762IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8763{
8764 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8765}
8766
8767
8768/**
8769 * Implements 'VMPTRLD'.
8770 */
8771IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8772{
8773 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8774}
8775
8776
8777/**
8778 * Implements 'VMPTRST'.
8779 */
8780IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8781{
8782 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8783}
8784
8785
8786/**
8787 * Implements 'VMCLEAR'.
8788 */
8789IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8790{
8791 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8792}
8793
8794
8795/**
8796 * Implements 'VMWRITE' register.
8797 */
8798IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8799{
8800 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8801 NULL /* pExitInfo */);
8802}
8803
8804
8805/**
8806 * Implements 'VMWRITE' memory.
8807 */
8808IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8809{
8810 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8811}
8812
8813
8814/**
8815 * Implements 'VMREAD' register (64-bit).
8816 */
8817IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8818{
8819 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8820}
8821
8822
8823/**
8824 * Implements 'VMREAD' register (32-bit).
8825 */
8826IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8827{
8828 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8829}
8830
8831
8832/**
8833 * Implements 'VMREAD' memory, 64-bit register.
8834 */
8835IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8836{
8837 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8838}
8839
8840
8841/**
8842 * Implements 'VMREAD' memory, 32-bit register.
8843 */
8844IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8845{
8846 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8847}
8848
8849
8850/**
8851 * Implements VMX's implementation of PAUSE.
8852 */
8853IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8854{
8855 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8856 {
8857 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8858 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8859 return rcStrict;
8860 }
8861
8862 /*
8863 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8864 * a VM-exit, the instruction operates normally.
8865 */
8866 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8867 return VINF_SUCCESS;
8868}
8869
8870#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8871
8872
8873/**
8874 * Implements 'VMCALL'.
8875 */
8876IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8877{
8878#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8879 /* Nested-guest intercept. */
8880 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8881 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8882#endif
8883
8884 /* Join forces with vmmcall. */
8885 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8886}
8887
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette