VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78003

Last change on this file since 78003 was 77899, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Build fix.
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File size: 354.3 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 77899 2019-03-27 06:43:09Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 if (rcSched != VINF_SUCCESS) \
172 iemSetPassUpStatus(pVCpu, rcSched); \
173 return (a_rcStrictRet); \
174 } while (0)
175
176# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
177 do { \
178 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
179 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
180 if (rcSched != VINF_SUCCESS) \
181 iemSetPassUpStatus(pVCpu, rcSched); \
182 return (a_rcStrictRet); \
183 } while (0)
184# else
185# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
186# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
187# endif
188
189
190/*********************************************************************************************************************************
191* Global Variables *
192*********************************************************************************************************************************/
193/** @todo NSTVMX: The following VM-exit intercepts are pending:
194 * VMX_EXIT_IO_SMI
195 * VMX_EXIT_SMI
196 * VMX_EXIT_INT_WINDOW
197 * VMX_EXIT_NMI_WINDOW
198 * VMX_EXIT_GETSEC
199 * VMX_EXIT_RSM
200 * VMX_EXIT_MTF
201 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
202 * VMX_EXIT_ERR_MACHINE_CHECK
203 * VMX_EXIT_TPR_BELOW_THRESHOLD
204 * VMX_EXIT_APIC_ACCESS
205 * VMX_EXIT_VIRTUALIZED_EOI
206 * VMX_EXIT_EPT_VIOLATION
207 * VMX_EXIT_EPT_MISCONFIG
208 * VMX_EXIT_INVEPT
209 * VMX_EXIT_PREEMPT_TIMER
210 * VMX_EXIT_INVVPID
211 * VMX_EXIT_APIC_WRITE
212 * VMX_EXIT_RDRAND
213 * VMX_EXIT_VMFUNC
214 * VMX_EXIT_ENCLS
215 * VMX_EXIT_RDSEED
216 * VMX_EXIT_PML_FULL
217 * VMX_EXIT_XSAVES
218 * VMX_EXIT_XRSTORS
219 */
220/**
221 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
222 *
223 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
224 * second dimension is the Index, see VMXVMCSFIELDENC.
225 */
226uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
227{
228 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
233 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
236 },
237 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
238 {
239 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 24-25 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
253 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
254 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
255 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
256 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
258 },
259 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
268 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
270 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
271 },
272 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
275 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
276 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
277 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
278 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
279 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
280 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
281 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
282 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
283 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
284 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
285 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
286 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
287 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
288 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
289 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
290 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
291 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
292 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
293 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
294 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
295 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
296 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
297 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
298 /* 24 */ UINT16_MAX,
299 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
300 },
301 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
304 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 25 */ UINT16_MAX
308 },
309 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
329 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
330 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
331 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
332 },
333 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
334 {
335 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
336 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
337 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
338 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
339 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
340 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
341 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
342 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
343 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
344 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
345 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
346 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
347 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
348 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
349 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
350 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
351 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
352 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
353 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
354 },
355 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
356 {
357 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
358 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
359 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
360 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
361 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
362 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
363 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
364 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
365 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
366 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
367 /* 24-25 */ UINT16_MAX, UINT16_MAX
368 },
369 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
370 {
371 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
372 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
373 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
374 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
375 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
376 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
377 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
378 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
379 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
380 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
381 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
382 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
383 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
384 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
385 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
386 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
387 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
388 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
389 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
390 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
391 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
392 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
393 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
394 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
395 },
396 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
397 {
398 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
399 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
401 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
402 /* 25 */ UINT16_MAX
403 },
404 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
405 {
406 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
407 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
408 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
409 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
410 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
411 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
412 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
413 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
414 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
415 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
416 /* 24-25 */ UINT16_MAX, UINT16_MAX
417 },
418 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
419 {
420 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
421 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
422 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
423 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
424 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
425 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
426 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
429 },
430 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
431 {
432 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
433 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
434 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
435 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
436 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
437 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
438 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
439 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
440 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
441 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
442 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
443 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
444 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
445 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
446 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
447 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
448 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
449 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
450 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
451 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
452 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 },
454 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
455 {
456 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
457 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
458 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
459 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
460 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
461 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
462 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
463 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
464 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
465 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
466 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
467 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
468 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
469 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
470 }
471};
472
473
474/**
475 * Returns whether the given VMCS field is valid and supported by our emulation.
476 *
477 * @param pVCpu The cross context virtual CPU structure.
478 * @param u64FieldEnc The VMCS field encoding.
479 *
480 * @remarks This takes into account the CPU features exposed to the guest.
481 */
482IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
483{
484 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
485 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
486 if (!uFieldEncHi)
487 { /* likely */ }
488 else
489 return false;
490
491 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
492 switch (uFieldEncLo)
493 {
494 /*
495 * 16-bit fields.
496 */
497 /* Control fields. */
498 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
499 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
500 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
501
502 /* Guest-state fields. */
503 case VMX_VMCS16_GUEST_ES_SEL:
504 case VMX_VMCS16_GUEST_CS_SEL:
505 case VMX_VMCS16_GUEST_SS_SEL:
506 case VMX_VMCS16_GUEST_DS_SEL:
507 case VMX_VMCS16_GUEST_FS_SEL:
508 case VMX_VMCS16_GUEST_GS_SEL:
509 case VMX_VMCS16_GUEST_LDTR_SEL:
510 case VMX_VMCS16_GUEST_TR_SEL: return true;
511 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
512 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
513
514 /* Host-state fields. */
515 case VMX_VMCS16_HOST_ES_SEL:
516 case VMX_VMCS16_HOST_CS_SEL:
517 case VMX_VMCS16_HOST_SS_SEL:
518 case VMX_VMCS16_HOST_DS_SEL:
519 case VMX_VMCS16_HOST_FS_SEL:
520 case VMX_VMCS16_HOST_GS_SEL:
521 case VMX_VMCS16_HOST_TR_SEL: return true;
522
523 /*
524 * 64-bit fields.
525 */
526 /* Control fields. */
527 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
528 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
529 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
530 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
531 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
532 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
533 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
534 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
535 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
536 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
537 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
538 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
539 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
540 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
541 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
542 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
543 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
544 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
545 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
546 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
547 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
548 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
549 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
550 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
551 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
552 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
553 case VMX_VMCS64_CTRL_EPTP_FULL:
554 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
555 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
557 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
558 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
559 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
560 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
561 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
562 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
563 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
564 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
565 {
566 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
567 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
568 }
569 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
571 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
573 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
574 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
575 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
576 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
577 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
578 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
579 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
580 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
581
582 /* Read-only data fields. */
583 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
584 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
585
586 /* Guest-state fields. */
587 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
588 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
589 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
590 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
591 case VMX_VMCS64_GUEST_PAT_FULL:
592 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
593 case VMX_VMCS64_GUEST_EFER_FULL:
594 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
595 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
596 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
597 case VMX_VMCS64_GUEST_PDPTE0_FULL:
598 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
599 case VMX_VMCS64_GUEST_PDPTE1_FULL:
600 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
601 case VMX_VMCS64_GUEST_PDPTE2_FULL:
602 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
603 case VMX_VMCS64_GUEST_PDPTE3_FULL:
604 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
605 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
606 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
607
608 /* Host-state fields. */
609 case VMX_VMCS64_HOST_PAT_FULL:
610 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
611 case VMX_VMCS64_HOST_EFER_FULL:
612 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
613 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
614 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
615
616 /*
617 * 32-bit fields.
618 */
619 /* Control fields. */
620 case VMX_VMCS32_CTRL_PIN_EXEC:
621 case VMX_VMCS32_CTRL_PROC_EXEC:
622 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
623 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
624 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
625 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
626 case VMX_VMCS32_CTRL_EXIT:
627 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
628 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
629 case VMX_VMCS32_CTRL_ENTRY:
630 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
631 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
632 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
633 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
634 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
635 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
636 case VMX_VMCS32_CTRL_PLE_GAP:
637 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
638
639 /* Read-only data fields. */
640 case VMX_VMCS32_RO_VM_INSTR_ERROR:
641 case VMX_VMCS32_RO_EXIT_REASON:
642 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
643 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
644 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
645 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
646 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
647 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
648
649 /* Guest-state fields. */
650 case VMX_VMCS32_GUEST_ES_LIMIT:
651 case VMX_VMCS32_GUEST_CS_LIMIT:
652 case VMX_VMCS32_GUEST_SS_LIMIT:
653 case VMX_VMCS32_GUEST_DS_LIMIT:
654 case VMX_VMCS32_GUEST_FS_LIMIT:
655 case VMX_VMCS32_GUEST_GS_LIMIT:
656 case VMX_VMCS32_GUEST_LDTR_LIMIT:
657 case VMX_VMCS32_GUEST_TR_LIMIT:
658 case VMX_VMCS32_GUEST_GDTR_LIMIT:
659 case VMX_VMCS32_GUEST_IDTR_LIMIT:
660 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
663 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
664 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
665 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
666 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
667 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
668 case VMX_VMCS32_GUEST_INT_STATE:
669 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
670 case VMX_VMCS32_GUEST_SMBASE:
671 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
672 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
673
674 /* Host-state fields. */
675 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
676
677 /*
678 * Natural-width fields.
679 */
680 /* Control fields. */
681 case VMX_VMCS_CTRL_CR0_MASK:
682 case VMX_VMCS_CTRL_CR4_MASK:
683 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
684 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
685 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
686 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
687 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
688 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
689
690 /* Read-only data fields. */
691 case VMX_VMCS_RO_EXIT_QUALIFICATION:
692 case VMX_VMCS_RO_IO_RCX:
693 case VMX_VMCS_RO_IO_RSX:
694 case VMX_VMCS_RO_IO_RDI:
695 case VMX_VMCS_RO_IO_RIP:
696 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
697
698 /* Guest-state fields. */
699 case VMX_VMCS_GUEST_CR0:
700 case VMX_VMCS_GUEST_CR3:
701 case VMX_VMCS_GUEST_CR4:
702 case VMX_VMCS_GUEST_ES_BASE:
703 case VMX_VMCS_GUEST_CS_BASE:
704 case VMX_VMCS_GUEST_SS_BASE:
705 case VMX_VMCS_GUEST_DS_BASE:
706 case VMX_VMCS_GUEST_FS_BASE:
707 case VMX_VMCS_GUEST_GS_BASE:
708 case VMX_VMCS_GUEST_LDTR_BASE:
709 case VMX_VMCS_GUEST_TR_BASE:
710 case VMX_VMCS_GUEST_GDTR_BASE:
711 case VMX_VMCS_GUEST_IDTR_BASE:
712 case VMX_VMCS_GUEST_DR7:
713 case VMX_VMCS_GUEST_RSP:
714 case VMX_VMCS_GUEST_RIP:
715 case VMX_VMCS_GUEST_RFLAGS:
716 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
717 case VMX_VMCS_GUEST_SYSENTER_ESP:
718 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
719
720 /* Host-state fields. */
721 case VMX_VMCS_HOST_CR0:
722 case VMX_VMCS_HOST_CR3:
723 case VMX_VMCS_HOST_CR4:
724 case VMX_VMCS_HOST_FS_BASE:
725 case VMX_VMCS_HOST_GS_BASE:
726 case VMX_VMCS_HOST_TR_BASE:
727 case VMX_VMCS_HOST_GDTR_BASE:
728 case VMX_VMCS_HOST_IDTR_BASE:
729 case VMX_VMCS_HOST_SYSENTER_ESP:
730 case VMX_VMCS_HOST_SYSENTER_EIP:
731 case VMX_VMCS_HOST_RSP:
732 case VMX_VMCS_HOST_RIP: return true;
733 }
734
735 return false;
736}
737
738
739/**
740 * Gets a host selector from the VMCS.
741 *
742 * @param pVmcs Pointer to the virtual VMCS.
743 * @param iSelReg The index of the segment register (X86_SREG_XXX).
744 */
745DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
746{
747 Assert(iSegReg < X86_SREG_COUNT);
748 RTSEL HostSel;
749 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
750 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
751 uint8_t const uWidthType = (uWidth << 2) | uType;
752 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
753 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
754 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
755 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
756 uint8_t const *pbField = pbVmcs + offField;
757 HostSel = *(uint16_t *)pbField;
758 return HostSel;
759}
760
761
762/**
763 * Sets a guest segment register in the VMCS.
764 *
765 * @param pVmcs Pointer to the virtual VMCS.
766 * @param iSegReg The index of the segment register (X86_SREG_XXX).
767 * @param pSelReg Pointer to the segment register.
768 */
769IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
770{
771 Assert(pSelReg);
772 Assert(iSegReg < X86_SREG_COUNT);
773
774 /* Selector. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t *pbField = pbVmcs + offField;
784 *(uint16_t *)pbField = pSelReg->Sel;
785 }
786
787 /* Limit. */
788 {
789 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
790 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
791 uint8_t const uWidthType = (uWidth << 2) | uType;
792 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
793 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
794 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
795 uint8_t *pbVmcs = (uint8_t *)pVmcs;
796 uint8_t *pbField = pbVmcs + offField;
797 *(uint32_t *)pbField = pSelReg->u32Limit;
798 }
799
800 /* Base. */
801 {
802 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
803 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
804 uint8_t const uWidthType = (uWidth << 2) | uType;
805 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
806 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
807 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
808 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
809 uint8_t const *pbField = pbVmcs + offField;
810 *(uint64_t *)pbField = pSelReg->u64Base;
811 }
812
813 /* Attributes. */
814 {
815 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
816 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
817 | X86DESCATTR_UNUSABLE;
818 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
819 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
820 uint8_t const uWidthType = (uWidth << 2) | uType;
821 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
822 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
823 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
824 uint8_t *pbVmcs = (uint8_t *)pVmcs;
825 uint8_t *pbField = pbVmcs + offField;
826 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
827 }
828}
829
830
831/**
832 * Gets a guest segment register from the VMCS.
833 *
834 * @returns VBox status code.
835 * @param pVmcs Pointer to the virtual VMCS.
836 * @param iSegReg The index of the segment register (X86_SREG_XXX).
837 * @param pSelReg Where to store the segment register (only updated when
838 * VINF_SUCCESS is returned).
839 *
840 * @remarks Warning! This does not validate the contents of the retrieved segment
841 * register.
842 */
843IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
844{
845 Assert(pSelReg);
846 Assert(iSegReg < X86_SREG_COUNT);
847
848 /* Selector. */
849 uint16_t u16Sel;
850 {
851 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
852 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
853 uint8_t const uWidthType = (uWidth << 2) | uType;
854 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
855 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
856 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
857 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
858 uint8_t const *pbField = pbVmcs + offField;
859 u16Sel = *(uint16_t *)pbField;
860 }
861
862 /* Limit. */
863 uint32_t u32Limit;
864 {
865 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
866 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
867 uint8_t const uWidthType = (uWidth << 2) | uType;
868 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
869 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
870 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
871 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
872 uint8_t const *pbField = pbVmcs + offField;
873 u32Limit = *(uint32_t *)pbField;
874 }
875
876 /* Base. */
877 uint64_t u64Base;
878 {
879 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
880 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
881 uint8_t const uWidthType = (uWidth << 2) | uType;
882 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
883 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
884 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
885 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
886 uint8_t const *pbField = pbVmcs + offField;
887 u64Base = *(uint64_t *)pbField;
888 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
889 }
890
891 /* Attributes. */
892 uint32_t u32Attr;
893 {
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
898 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 u32Attr = *(uint32_t *)pbField;
903 }
904
905 pSelReg->Sel = u16Sel;
906 pSelReg->ValidSel = u16Sel;
907 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
908 pSelReg->u32Limit = u32Limit;
909 pSelReg->u64Base = u64Base;
910 pSelReg->Attr.u = u32Attr;
911 return VINF_SUCCESS;
912}
913
914
915/**
916 * Gets a CR3 target value from the VMCS.
917 *
918 * @returns VBox status code.
919 * @param pVmcs Pointer to the virtual VMCS.
920 * @param idxCr3Target The index of the CR3-target value to retrieve.
921 * @param puValue Where to store the CR3-target value.
922 */
923IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
924{
925 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
926 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
927 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
928 uint8_t const uWidthType = (uWidth << 2) | uType;
929 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
930 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
931 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
932 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
933 uint8_t const *pbField = pbVmcs + offField;
934 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
935 return uCr3TargetValue;
936}
937
938
939/**
940 * Converts an IEM exception event type to a VMX event type.
941 *
942 * @returns The VMX event type.
943 * @param uVector The interrupt / exception vector.
944 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
945 */
946DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
947{
948 /* Paranoia (callers may use these interchangeably). */
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
956 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
957 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
958 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
959 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
960 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
961
962 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
963 {
964 if (uVector == X86_XCPT_NMI)
965 return VMX_EXIT_INT_INFO_TYPE_NMI;
966 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
967 }
968
969 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
970 {
971 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
972 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
973 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
974 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
975 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
976 }
977
978 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
979 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
980}
981
982
983/**
984 * Sets the VM-exit qualification VMCS field.
985 *
986 * @param pVCpu The cross context virtual CPU structure.
987 * @param uExitQual The VM-exit qualification.
988 */
989DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
990{
991 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
992 pVmcs->u64RoExitQual.u = uExitQual;
993}
994
995
996/**
997 * Sets the VM-exit interruption information field.
998 *
999 * @param pVCpu The cross context virtual CPU structure.
1000 * @param uExitQual The VM-exit interruption information.
1001 */
1002DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1003{
1004 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1005 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1006}
1007
1008
1009/**
1010 * Sets the VM-exit interruption error code.
1011 *
1012 * @param pVCpu The cross context virtual CPU structure.
1013 * @param uErrCode The error code.
1014 */
1015DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1016{
1017 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1018 pVmcs->u32RoExitIntErrCode = uErrCode;
1019}
1020
1021
1022/**
1023 * Sets the IDT-vectoring information field.
1024 *
1025 * @param pVCpu The cross context virtual CPU structure.
1026 * @param uIdtVectorInfo The IDT-vectoring information.
1027 */
1028DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1029{
1030 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1031 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1032}
1033
1034
1035/**
1036 * Sets the IDT-vectoring error code field.
1037 *
1038 * @param pVCpu The cross context virtual CPU structure.
1039 * @param uErrCode The error code.
1040 */
1041DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1042{
1043 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1044 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1045}
1046
1047
1048/**
1049 * Sets the VM-exit guest-linear address VMCS field.
1050 *
1051 * @param pVCpu The cross context virtual CPU structure.
1052 * @param uGuestLinearAddr The VM-exit guest-linear address.
1053 */
1054DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1055{
1056 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1057 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1058}
1059
1060
1061/**
1062 * Sets the VM-exit guest-physical address VMCS field.
1063 *
1064 * @param pVCpu The cross context virtual CPU structure.
1065 * @param uGuestPhysAddr The VM-exit guest-physical address.
1066 */
1067DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1068{
1069 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1070 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1071}
1072
1073
1074/**
1075 * Sets the VM-exit instruction length VMCS field.
1076 *
1077 * @param pVCpu The cross context virtual CPU structure.
1078 * @param cbInstr The VM-exit instruction length in bytes.
1079 *
1080 * @remarks Callers may clear this field to 0. Hence, this function does not check
1081 * the validity of the instruction length.
1082 */
1083DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1084{
1085 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1086 pVmcs->u32RoExitInstrLen = cbInstr;
1087}
1088
1089
1090/**
1091 * Sets the VM-exit instruction info. VMCS field.
1092 *
1093 * @param pVCpu The cross context virtual CPU structure.
1094 * @param uExitInstrInfo The VM-exit instruction information.
1095 */
1096DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1097{
1098 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1099 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1100}
1101
1102
1103/**
1104 * Implements VMSucceed for VMX instruction success.
1105 *
1106 * @param pVCpu The cross context virtual CPU structure.
1107 */
1108DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1109{
1110 return CPUMSetGuestVmxVmSucceed(IEM_GET_CTX(pVCpu));
1111}
1112
1113
1114/**
1115 * Implements VMFailInvalid for VMX instruction failure.
1116 *
1117 * @param pVCpu The cross context virtual CPU structure.
1118 */
1119DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1120{
1121 return CPUMSetGuestVmxVmFailInvalid(IEM_GET_CTX(pVCpu));
1122}
1123
1124
1125/**
1126 * Implements VMFailValid for VMX instruction failure.
1127 *
1128 * @param pVCpu The cross context virtual CPU structure.
1129 * @param enmInsErr The VM instruction error.
1130 */
1131DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1132{
1133 return CPUMSetGuestVmxVmFailValid(IEM_GET_CTX(pVCpu), enmInsErr);
1134}
1135
1136
1137/**
1138 * Implements VMFail for VMX instruction failure.
1139 *
1140 * @param pVCpu The cross context virtual CPU structure.
1141 * @param enmInsErr The VM instruction error.
1142 */
1143DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1144{
1145 return CPUMSetGuestVmxVmFail(IEM_GET_CTX(pVCpu), enmInsErr);
1146}
1147
1148
1149/**
1150 * Checks if the given auto-load/store MSR area count is valid for the
1151 * implementation.
1152 *
1153 * @returns @c true if it's within the valid limit, @c false otherwise.
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param uMsrCount The MSR area count to check.
1156 */
1157DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1158{
1159 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1160 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1161 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1162 if (uMsrCount <= cMaxSupportedMsrs)
1163 return true;
1164 return false;
1165}
1166
1167
1168/**
1169 * Flushes the current VMCS contents back to guest memory.
1170 *
1171 * @returns VBox status code.
1172 * @param pVCpu The cross context virtual CPU structure.
1173 */
1174DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1175{
1176 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1177 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1178 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1179 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1180 return rc;
1181}
1182
1183
1184/**
1185 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1186 *
1187 * @param pVCpu The cross context virtual CPU structure.
1188 */
1189DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1190{
1191 iemVmxVmSucceed(pVCpu);
1192 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1193}
1194
1195
1196/**
1197 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1198 * nested-guest.
1199 *
1200 * @param iSegReg The segment index (X86_SREG_XXX).
1201 */
1202IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1203{
1204 switch (iSegReg)
1205 {
1206 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1207 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1208 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1209 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1210 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1211 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1212 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1213 }
1214}
1215
1216
1217/**
1218 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1219 * nested-guest that is in Virtual-8086 mode.
1220 *
1221 * @param iSegReg The segment index (X86_SREG_XXX).
1222 */
1223IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1224{
1225 switch (iSegReg)
1226 {
1227 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1228 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1229 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1230 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1231 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1232 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1233 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1234 }
1235}
1236
1237
1238/**
1239 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1240 * nested-guest that is in Virtual-8086 mode.
1241 *
1242 * @param iSegReg The segment index (X86_SREG_XXX).
1243 */
1244IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1245{
1246 switch (iSegReg)
1247 {
1248 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1249 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1250 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1251 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1252 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1253 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1254 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1255 }
1256}
1257
1258
1259/**
1260 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1261 * nested-guest that is in Virtual-8086 mode.
1262 *
1263 * @param iSegReg The segment index (X86_SREG_XXX).
1264 */
1265IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1266{
1267 switch (iSegReg)
1268 {
1269 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1270 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1271 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1272 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1273 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1274 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1275 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1276 }
1277}
1278
1279
1280/**
1281 * Gets the instruction diagnostic for segment attributes reserved bits failure
1282 * during VM-entry of a nested-guest.
1283 *
1284 * @param iSegReg The segment index (X86_SREG_XXX).
1285 */
1286IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1287{
1288 switch (iSegReg)
1289 {
1290 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1291 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1292 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1293 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1294 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1295 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1296 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1297 }
1298}
1299
1300
1301/**
1302 * Gets the instruction diagnostic for segment attributes descriptor-type
1303 * (code/segment or system) failure during VM-entry of a nested-guest.
1304 *
1305 * @param iSegReg The segment index (X86_SREG_XXX).
1306 */
1307IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1308{
1309 switch (iSegReg)
1310 {
1311 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1312 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1313 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1314 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1315 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1316 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1317 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1318 }
1319}
1320
1321
1322/**
1323 * Gets the instruction diagnostic for segment attributes descriptor-type
1324 * (code/segment or system) failure during VM-entry of a nested-guest.
1325 *
1326 * @param iSegReg The segment index (X86_SREG_XXX).
1327 */
1328IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1329{
1330 switch (iSegReg)
1331 {
1332 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1333 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1334 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1335 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1336 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1337 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1338 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1339 }
1340}
1341
1342
1343/**
1344 * Gets the instruction diagnostic for segment attribute granularity failure during
1345 * VM-entry of a nested-guest.
1346 *
1347 * @param iSegReg The segment index (X86_SREG_XXX).
1348 */
1349IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1350{
1351 switch (iSegReg)
1352 {
1353 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1354 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1355 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1356 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1357 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1358 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1359 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1360 }
1361}
1362
1363/**
1364 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1365 * VM-entry of a nested-guest.
1366 *
1367 * @param iSegReg The segment index (X86_SREG_XXX).
1368 */
1369IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1370{
1371 switch (iSegReg)
1372 {
1373 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1374 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1375 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1376 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1377 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1378 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1379 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1380 }
1381}
1382
1383
1384/**
1385 * Gets the instruction diagnostic for segment attribute type accessed failure
1386 * during VM-entry of a nested-guest.
1387 *
1388 * @param iSegReg The segment index (X86_SREG_XXX).
1389 */
1390IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1391{
1392 switch (iSegReg)
1393 {
1394 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1395 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1396 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1397 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1398 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1399 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1400 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1401 }
1402}
1403
1404
1405/**
1406 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1407 * failure during VM-entry of a nested-guest.
1408 *
1409 * @param iSegReg The PDPTE entry index.
1410 */
1411IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1412{
1413 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1414 switch (iPdpte)
1415 {
1416 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1417 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1418 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1419 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1420 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1421 }
1422}
1423
1424
1425/**
1426 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1427 * failure during VM-exit of a nested-guest.
1428 *
1429 * @param iSegReg The PDPTE entry index.
1430 */
1431IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1432{
1433 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1434 switch (iPdpte)
1435 {
1436 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1437 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1438 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1439 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1440 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1441 }
1442}
1443
1444
1445/**
1446 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1447 * mask and the read-shadow (CR0/CR4 read).
1448 *
1449 * @returns The masked CR0/CR4.
1450 * @param pVCpu The cross context virtual CPU structure.
1451 * @param iCrReg The control register (either CR0 or CR4).
1452 * @param uGuestCrX The current guest CR0 or guest CR4.
1453 */
1454IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1455{
1456 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1457 Assert(iCrReg == 0 || iCrReg == 4);
1458
1459 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1460 Assert(pVmcs);
1461
1462 /*
1463 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1464 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1465 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1466 *
1467 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1468 */
1469 uint64_t fGstHostMask;
1470 uint64_t fReadShadow;
1471 if (iCrReg == 0)
1472 {
1473 fGstHostMask = pVmcs->u64Cr0Mask.u;
1474 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1475 }
1476 else
1477 {
1478 fGstHostMask = pVmcs->u64Cr4Mask.u;
1479 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1480 }
1481
1482 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1483 return fMaskedCrX;
1484}
1485
1486
1487/**
1488 * Saves the guest control registers, debug registers and some MSRs are part of
1489 * VM-exit.
1490 *
1491 * @param pVCpu The cross context virtual CPU structure.
1492 */
1493IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1494{
1495 /*
1496 * Saves the guest control registers, debug registers and some MSRs.
1497 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1498 */
1499 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1500
1501 /* Save control registers. */
1502 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1503 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1504 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1505
1506 /* Save SYSENTER CS, ESP, EIP. */
1507 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1508 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1509 {
1510 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1511 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1512 }
1513 else
1514 {
1515 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1516 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1517 }
1518
1519 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1520 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1521 {
1522 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1523 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1524 }
1525
1526 /* Save PAT MSR. */
1527 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1528 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1529
1530 /* Save EFER MSR. */
1531 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1532 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1533
1534 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1535 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1536
1537 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1538}
1539
1540
1541/**
1542 * Saves the guest force-flags in preparation of entering the nested-guest.
1543 *
1544 * @param pVCpu The cross context virtual CPU structure.
1545 */
1546IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1547{
1548 /* We shouldn't be called multiple times during VM-entry. */
1549 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1550
1551 /* MTF should not be set outside VMX non-root mode. */
1552 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1553
1554 /*
1555 * Preserve the required force-flags.
1556 *
1557 * We cache and clear force-flags that would affect the execution of the
1558 * nested-guest. Cached flags are then restored while returning to the guest
1559 * if necessary.
1560 *
1561 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1562 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1563 * instruction. Interrupt inhibition for any nested-guest instruction
1564 * is supplied by the guest-interruptibility state VMCS field and will
1565 * be set up as part of loading the guest state.
1566 *
1567 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1568 * successful VM-entry (due to invalid guest-state) need to continue
1569 * blocking NMIs if it was in effect before VM-entry.
1570 *
1571 * - MTF need not be preserved as it's used only in VMX non-root mode and
1572 * is supplied through the VM-execution controls.
1573 *
1574 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1575 * we will be able to generate interrupts that may cause VM-exits for
1576 * the nested-guest.
1577 */
1578 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1579}
1580
1581
1582/**
1583 * Restores the guest force-flags in preparation of exiting the nested-guest.
1584 *
1585 * @param pVCpu The cross context virtual CPU structure.
1586 */
1587IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1588{
1589 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1590 {
1591 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1592 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1593 }
1594}
1595
1596
1597/**
1598 * Perform a VMX transition updated PGM, IEM and CPUM.
1599 *
1600 * @param pVCpu The cross context virtual CPU structure.
1601 */
1602IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1603{
1604 /*
1605 * Inform PGM about paging mode changes.
1606 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1607 * see comment in iemMemPageTranslateAndCheckAccess().
1608 */
1609 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1610# ifdef IN_RING3
1611 Assert(rc != VINF_PGM_CHANGE_MODE);
1612# endif
1613 AssertRCReturn(rc, rc);
1614
1615 /* Inform CPUM (recompiler), can later be removed. */
1616 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1617
1618 /*
1619 * Flush the TLB with new CR3. This is required in case the PGM mode change
1620 * above doesn't actually change anything.
1621 */
1622 if (rc == VINF_SUCCESS)
1623 {
1624 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1625 AssertRCReturn(rc, rc);
1626 }
1627
1628 /* Re-initialize IEM cache/state after the drastic mode switch. */
1629 iemReInitExec(pVCpu);
1630 return rc;
1631}
1632
1633
1634/**
1635 * Calculates the current VMX-preemption timer value.
1636 *
1637 * @param pVCpu The cross context virtual CPU structure.
1638 */
1639IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1640{
1641 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1642 Assert(pVmcs);
1643
1644 /*
1645 * Assume the following:
1646 * PreemptTimerShift = 5
1647 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1648 * VmentryTick = 50000 (TSC at time of VM-entry)
1649 *
1650 * CurTick Delta PreemptTimerVal
1651 * ----------------------------------
1652 * 60000 10000 2
1653 * 80000 30000 1
1654 * 90000 40000 0 -> VM-exit.
1655 *
1656 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1657 * The saved VMX-preemption timer value is calculated as follows:
1658 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1659 * E.g.:
1660 * Delta = 10000
1661 * Tmp = 10000 / (2 * 10000) = 0.5
1662 * NewPt = 2 - 0.5 = 2
1663 * Delta = 30000
1664 * Tmp = 30000 / (2 * 10000) = 1.5
1665 * NewPt = 2 - 1.5 = 1
1666 * Delta = 40000
1667 * Tmp = 40000 / 20000 = 2
1668 * NewPt = 2 - 2 = 0
1669 */
1670 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1671 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1672 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1673 uint64_t const uDelta = uCurTick - uVmentryTick;
1674 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1675 uint32_t const uPreemptTimer = uVmcsPreemptVal
1676 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1677 return uPreemptTimer;
1678}
1679
1680
1681/**
1682 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1683 *
1684 * @param pVCpu The cross context virtual CPU structure.
1685 */
1686IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1687{
1688 /*
1689 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1690 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1691 */
1692 /* CS, SS, ES, DS, FS, GS. */
1693 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1694 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1695 {
1696 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1697 if (!pSelReg->Attr.n.u1Unusable)
1698 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1699 else
1700 {
1701 /*
1702 * For unusable segments the attributes are undefined except for CS and SS.
1703 * For the rest we don't bother preserving anything but the unusable bit.
1704 */
1705 switch (iSegReg)
1706 {
1707 case X86_SREG_CS:
1708 pVmcs->GuestCs = pSelReg->Sel;
1709 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1710 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1711 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1712 | X86DESCATTR_UNUSABLE);
1713 break;
1714
1715 case X86_SREG_SS:
1716 pVmcs->GuestSs = pSelReg->Sel;
1717 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1718 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1719 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1720 break;
1721
1722 case X86_SREG_DS:
1723 pVmcs->GuestDs = pSelReg->Sel;
1724 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1725 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1726 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1727 break;
1728
1729 case X86_SREG_ES:
1730 pVmcs->GuestEs = pSelReg->Sel;
1731 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1732 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1733 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1734 break;
1735
1736 case X86_SREG_FS:
1737 pVmcs->GuestFs = pSelReg->Sel;
1738 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1739 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1740 break;
1741
1742 case X86_SREG_GS:
1743 pVmcs->GuestGs = pSelReg->Sel;
1744 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1745 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1746 break;
1747 }
1748 }
1749 }
1750
1751 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1752 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1753 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1754 | X86DESCATTR_UNUSABLE;
1755 /* LDTR. */
1756 {
1757 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1758 pVmcs->GuestLdtr = pSelReg->Sel;
1759 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1760 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1761 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1762 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1763 }
1764
1765 /* TR. */
1766 {
1767 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1768 pVmcs->GuestTr = pSelReg->Sel;
1769 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1770 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1771 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1772 }
1773
1774 /* GDTR. */
1775 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1776 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1777
1778 /* IDTR. */
1779 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1780 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1781}
1782
1783
1784/**
1785 * Saves guest non-register state as part of VM-exit.
1786 *
1787 * @param pVCpu The cross context virtual CPU structure.
1788 * @param uExitReason The VM-exit reason.
1789 */
1790IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1791{
1792 /*
1793 * Save guest non-register state.
1794 * See Intel spec. 27.3.4 "Saving Non-Register State".
1795 */
1796 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1797
1798 /*
1799 * Activity state.
1800 * Most VM-exits will occur in the active state. However, if the first instruction
1801 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1802 * the VM-exit will be from the HLT activity state.
1803 *
1804 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1805 */
1806 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1807 * not? */
1808 EMSTATE const enmActivityState = EMGetState(pVCpu);
1809 switch (enmActivityState)
1810 {
1811 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1812 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1813 }
1814
1815 /*
1816 * Interruptibility-state.
1817 */
1818 /* NMI. */
1819 pVmcs->u32GuestIntrState = 0;
1820 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1821 {
1822 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1823 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1824 }
1825 else
1826 {
1827 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1828 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1829 }
1830
1831 /* Blocking-by-STI. */
1832 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1833 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1834 {
1835 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1836 * currently. */
1837 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1838 }
1839 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1840
1841 /*
1842 * Pending debug exceptions.
1843 */
1844 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1845 && uExitReason != VMX_EXIT_SMI
1846 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1847 && !HMVmxIsVmexitTrapLike(uExitReason))
1848 {
1849 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1850 * block-by-MovSS is in effect. */
1851 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1852 }
1853 else
1854 {
1855 /*
1856 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1857 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1858 *
1859 * See Intel spec. 24.4.2 "Guest Non-Register State".
1860 */
1861 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1862 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1863 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1864 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1865 if (fPendingDbgMask & fBpHitMask)
1866 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1867 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1868 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1869 }
1870
1871 /*
1872 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1873 *
1874 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1875 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1876 */
1877 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1878 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1879 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1880
1881 /* PDPTEs. */
1882 /* We don't support EPT yet. */
1883 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1884 pVmcs->u64GuestPdpte0.u = 0;
1885 pVmcs->u64GuestPdpte1.u = 0;
1886 pVmcs->u64GuestPdpte2.u = 0;
1887 pVmcs->u64GuestPdpte3.u = 0;
1888}
1889
1890
1891/**
1892 * Saves the guest-state as part of VM-exit.
1893 *
1894 * @returns VBox status code.
1895 * @param pVCpu The cross context virtual CPU structure.
1896 * @param uExitReason The VM-exit reason.
1897 */
1898IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1899{
1900 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1901 Assert(pVmcs);
1902
1903 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1904 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1905
1906 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1907 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1908 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1909
1910 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1911}
1912
1913
1914/**
1915 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1916 *
1917 * @returns VBox status code.
1918 * @param pVCpu The cross context virtual CPU structure.
1919 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1920 */
1921IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1922{
1923 /*
1924 * Save guest MSRs.
1925 * See Intel spec. 27.4 "Saving MSRs".
1926 */
1927 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1928 const char *const pszFailure = "VMX-abort";
1929
1930 /*
1931 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1932 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1933 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1934 */
1935 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1936 if (!cMsrs)
1937 return VINF_SUCCESS;
1938
1939 /*
1940 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1941 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1942 * implementation causes a VMX-abort followed by a triple-fault.
1943 */
1944 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1945 if (fIsMsrCountValid)
1946 { /* likely */ }
1947 else
1948 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1949
1950 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1951 Assert(pMsr);
1952 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1953 {
1954 if ( !pMsr->u32Reserved
1955 && pMsr->u32Msr != MSR_IA32_SMBASE
1956 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1957 {
1958 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1959 if (rcStrict == VINF_SUCCESS)
1960 continue;
1961
1962 /*
1963 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1964 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1965 * recording the MSR index in the auxiliary info. field and indicated further by our
1966 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1967 * if possible, or come up with a better, generic solution.
1968 */
1969 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1970 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1971 ? kVmxVDiag_Vmexit_MsrStoreRing3
1972 : kVmxVDiag_Vmexit_MsrStore;
1973 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1974 }
1975 else
1976 {
1977 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1978 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1979 }
1980 }
1981
1982 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
1983 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
1984 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
1985 if (RT_SUCCESS(rc))
1986 { /* likely */ }
1987 else
1988 {
1989 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
1990 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1991 }
1992
1993 NOREF(uExitReason);
1994 NOREF(pszFailure);
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/**
2000 * Performs a VMX abort (due to an fatal error during VM-exit).
2001 *
2002 * @returns Strict VBox status code.
2003 * @param pVCpu The cross context virtual CPU structure.
2004 * @param enmAbort The VMX abort reason.
2005 */
2006IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
2007{
2008 /*
2009 * Perform the VMX abort.
2010 * See Intel spec. 27.7 "VMX Aborts".
2011 */
2012 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
2013
2014 /* We don't support SMX yet. */
2015 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2016 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2017 {
2018 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2019 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2020 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2021 }
2022
2023 return VINF_EM_TRIPLE_FAULT;
2024}
2025
2026
2027/**
2028 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2029 *
2030 * @param pVCpu The cross context virtual CPU structure.
2031 */
2032IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2033{
2034 /*
2035 * Load host control registers, debug registers and MSRs.
2036 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2037 */
2038 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2039 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2040
2041 /* CR0. */
2042 {
2043 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2044 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2045 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2046 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2047 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2048 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2049 CPUMSetGuestCR0(pVCpu, uValidCr0);
2050 }
2051
2052 /* CR4. */
2053 {
2054 /* CR4 MB1 bits are not modified. */
2055 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2056 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2057 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2058 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2059 if (fHostInLongMode)
2060 uValidCr4 |= X86_CR4_PAE;
2061 else
2062 uValidCr4 &= ~X86_CR4_PCIDE;
2063 CPUMSetGuestCR4(pVCpu, uValidCr4);
2064 }
2065
2066 /* CR3 (host value validated while checking host-state during VM-entry). */
2067 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2068
2069 /* DR7. */
2070 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2071
2072 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2073
2074 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2075 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2076 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2077 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2078
2079 /* FS, GS bases are loaded later while we load host segment registers. */
2080
2081 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2082 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2083 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2084 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2085 {
2086 if (fHostInLongMode)
2087 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2088 else
2089 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2090 }
2091
2092 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2093
2094 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2095 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2096 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2097
2098 /* We don't support IA32_BNDCFGS MSR yet. */
2099}
2100
2101
2102/**
2103 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2104 *
2105 * @param pVCpu The cross context virtual CPU structure.
2106 */
2107IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2108{
2109 /*
2110 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2111 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2112 *
2113 * Warning! Be careful to not touch fields that are reserved by VT-x,
2114 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2115 */
2116 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2117 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2118
2119 /* CS, SS, ES, DS, FS, GS. */
2120 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2121 {
2122 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2123 bool const fUnusable = RT_BOOL(HostSel == 0);
2124 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2125
2126 /* Selector. */
2127 pSelReg->Sel = HostSel;
2128 pSelReg->ValidSel = HostSel;
2129 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2130
2131 /* Limit. */
2132 pSelReg->u32Limit = 0xffffffff;
2133
2134 /* Base. */
2135 pSelReg->u64Base = 0;
2136
2137 /* Attributes. */
2138 if (iSegReg == X86_SREG_CS)
2139 {
2140 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2141 pSelReg->Attr.n.u1DescType = 1;
2142 pSelReg->Attr.n.u2Dpl = 0;
2143 pSelReg->Attr.n.u1Present = 1;
2144 pSelReg->Attr.n.u1Long = fHostInLongMode;
2145 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2146 pSelReg->Attr.n.u1Granularity = 1;
2147 Assert(!pSelReg->Attr.n.u1Unusable);
2148 Assert(!fUnusable);
2149 }
2150 else
2151 {
2152 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2153 pSelReg->Attr.n.u1DescType = 1;
2154 pSelReg->Attr.n.u2Dpl = 0;
2155 pSelReg->Attr.n.u1Present = 1;
2156 pSelReg->Attr.n.u1DefBig = 1;
2157 pSelReg->Attr.n.u1Granularity = 1;
2158 pSelReg->Attr.n.u1Unusable = fUnusable;
2159 }
2160 }
2161
2162 /* FS base. */
2163 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2164 || fHostInLongMode)
2165 {
2166 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2167 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2168 }
2169
2170 /* GS base. */
2171 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2172 || fHostInLongMode)
2173 {
2174 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2175 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2176 }
2177
2178 /* TR. */
2179 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2180 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2181 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2182 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2183 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2184 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2185 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2186 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2187 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2188 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2189 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2190 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2191 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2192
2193 /* LDTR (Warning! do not touch the base and limits here). */
2194 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2195 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2196 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2197 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2198
2199 /* GDTR. */
2200 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2201 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2202 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2203
2204 /* IDTR.*/
2205 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2206 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2207 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2208}
2209
2210
2211/**
2212 * Checks host PDPTes as part of VM-exit.
2213 *
2214 * @param pVCpu The cross context virtual CPU structure.
2215 * @param uExitReason The VM-exit reason (for logging purposes).
2216 */
2217IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2218{
2219 /*
2220 * Check host PDPTEs.
2221 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2222 */
2223 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2224 const char *const pszFailure = "VMX-abort";
2225 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2226
2227 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2228 && !fHostInLongMode)
2229 {
2230 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2231 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2232 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2233 if (RT_SUCCESS(rc))
2234 {
2235 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2236 {
2237 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2238 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2239 { /* likely */ }
2240 else
2241 {
2242 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2243 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2244 }
2245 }
2246 }
2247 else
2248 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2249 }
2250
2251 NOREF(pszFailure);
2252 NOREF(uExitReason);
2253 return VINF_SUCCESS;
2254}
2255
2256
2257/**
2258 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2259 *
2260 * @returns VBox status code.
2261 * @param pVCpu The cross context virtual CPU structure.
2262 * @param pszInstr The VMX instruction name (for logging purposes).
2263 */
2264IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2265{
2266 /*
2267 * Load host MSRs.
2268 * See Intel spec. 27.6 "Loading MSRs".
2269 */
2270 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2271 const char *const pszFailure = "VMX-abort";
2272
2273 /*
2274 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2275 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2276 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2277 */
2278 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2279 if (!cMsrs)
2280 return VINF_SUCCESS;
2281
2282 /*
2283 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2284 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2285 * implementation causes a VMX-abort followed by a triple-fault.
2286 */
2287 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2288 if (fIsMsrCountValid)
2289 { /* likely */ }
2290 else
2291 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2292
2293 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2294 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2295 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2296 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2297 if (RT_SUCCESS(rc))
2298 {
2299 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2300 Assert(pMsr);
2301 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2302 {
2303 if ( !pMsr->u32Reserved
2304 && pMsr->u32Msr != MSR_K8_FS_BASE
2305 && pMsr->u32Msr != MSR_K8_GS_BASE
2306 && pMsr->u32Msr != MSR_K6_EFER
2307 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2308 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2309 {
2310 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2311 if (rcStrict == VINF_SUCCESS)
2312 continue;
2313
2314 /*
2315 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2316 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2317 * recording the MSR index in the auxiliary info. field and indicated further by our
2318 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2319 * if possible, or come up with a better, generic solution.
2320 */
2321 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2322 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2323 ? kVmxVDiag_Vmexit_MsrLoadRing3
2324 : kVmxVDiag_Vmexit_MsrLoad;
2325 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2326 }
2327 else
2328 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2329 }
2330 }
2331 else
2332 {
2333 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2334 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2335 }
2336
2337 NOREF(uExitReason);
2338 NOREF(pszFailure);
2339 return VINF_SUCCESS;
2340}
2341
2342
2343/**
2344 * Loads the host state as part of VM-exit.
2345 *
2346 * @returns Strict VBox status code.
2347 * @param pVCpu The cross context virtual CPU structure.
2348 * @param uExitReason The VM-exit reason (for logging purposes).
2349 */
2350IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2351{
2352 /*
2353 * Load host state.
2354 * See Intel spec. 27.5 "Loading Host State".
2355 */
2356 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2357 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2358
2359 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2360 if ( CPUMIsGuestInLongMode(pVCpu)
2361 && !fHostInLongMode)
2362 {
2363 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2364 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2365 }
2366
2367 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2368 iemVmxVmexitLoadHostSegRegs(pVCpu);
2369
2370 /*
2371 * Load host RIP, RSP and RFLAGS.
2372 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2373 */
2374 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2375 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2376 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2377
2378 /* Clear address range monitoring. */
2379 EMMonitorWaitClear(pVCpu);
2380
2381 /* Perform the VMX transition (PGM updates). */
2382 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2383 if (rcStrict == VINF_SUCCESS)
2384 {
2385 /* Check host PDPTEs (only when we've fully switched page tables_. */
2386 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2387 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2388 if (RT_FAILURE(rc))
2389 {
2390 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2391 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2392 }
2393 }
2394 else if (RT_SUCCESS(rcStrict))
2395 {
2396 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2397 uExitReason));
2398 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2399 }
2400 else
2401 {
2402 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2403 return VBOXSTRICTRC_VAL(rcStrict);
2404 }
2405
2406 Assert(rcStrict == VINF_SUCCESS);
2407
2408 /* Load MSRs from the VM-exit auto-load MSR area. */
2409 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2410 if (RT_FAILURE(rc))
2411 {
2412 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2413 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2414 }
2415 return VINF_SUCCESS;
2416}
2417
2418
2419/**
2420 * Gets VM-exit instruction information along with any displacement for an
2421 * instruction VM-exit.
2422 *
2423 * @returns The VM-exit instruction information.
2424 * @param pVCpu The cross context virtual CPU structure.
2425 * @param uExitReason The VM-exit reason.
2426 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2427 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2428 * NULL.
2429 */
2430IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2431{
2432 RTGCPTR GCPtrDisp;
2433 VMXEXITINSTRINFO ExitInstrInfo;
2434 ExitInstrInfo.u = 0;
2435
2436 /*
2437 * Get and parse the ModR/M byte from our decoded opcodes.
2438 */
2439 uint8_t bRm;
2440 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2441 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2442 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2443 {
2444 /*
2445 * ModR/M indicates register addressing.
2446 *
2447 * The primary/secondary register operands are reported in the iReg1 or iReg2
2448 * fields depending on whether it is a read/write form.
2449 */
2450 uint8_t idxReg1;
2451 uint8_t idxReg2;
2452 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2453 {
2454 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2455 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2456 }
2457 else
2458 {
2459 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2460 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2461 }
2462 ExitInstrInfo.All.u2Scaling = 0;
2463 ExitInstrInfo.All.iReg1 = idxReg1;
2464 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2465 ExitInstrInfo.All.fIsRegOperand = 1;
2466 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2467 ExitInstrInfo.All.iSegReg = 0;
2468 ExitInstrInfo.All.iIdxReg = 0;
2469 ExitInstrInfo.All.fIdxRegInvalid = 1;
2470 ExitInstrInfo.All.iBaseReg = 0;
2471 ExitInstrInfo.All.fBaseRegInvalid = 1;
2472 ExitInstrInfo.All.iReg2 = idxReg2;
2473
2474 /* Displacement not applicable for register addressing. */
2475 GCPtrDisp = 0;
2476 }
2477 else
2478 {
2479 /*
2480 * ModR/M indicates memory addressing.
2481 */
2482 uint8_t uScale = 0;
2483 bool fBaseRegValid = false;
2484 bool fIdxRegValid = false;
2485 uint8_t iBaseReg = 0;
2486 uint8_t iIdxReg = 0;
2487 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2488 {
2489 /*
2490 * Parse the ModR/M, displacement for 16-bit addressing mode.
2491 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2492 */
2493 uint16_t u16Disp = 0;
2494 uint8_t const offDisp = offModRm + sizeof(bRm);
2495 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2496 {
2497 /* Displacement without any registers. */
2498 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2499 }
2500 else
2501 {
2502 /* Register (index and base). */
2503 switch (bRm & X86_MODRM_RM_MASK)
2504 {
2505 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2506 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2507 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2508 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2509 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2510 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2511 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2512 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2513 }
2514
2515 /* Register + displacement. */
2516 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2517 {
2518 case 0: break;
2519 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2520 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2521 default:
2522 {
2523 /* Register addressing, handled at the beginning. */
2524 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2525 break;
2526 }
2527 }
2528 }
2529
2530 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2531 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2532 }
2533 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2534 {
2535 /*
2536 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2537 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2538 */
2539 uint32_t u32Disp = 0;
2540 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2541 {
2542 /* Displacement without any registers. */
2543 uint8_t const offDisp = offModRm + sizeof(bRm);
2544 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2545 }
2546 else
2547 {
2548 /* Register (and perhaps scale, index and base). */
2549 uint8_t offDisp = offModRm + sizeof(bRm);
2550 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2551 if (iBaseReg == 4)
2552 {
2553 /* An SIB byte follows the ModR/M byte, parse it. */
2554 uint8_t bSib;
2555 uint8_t const offSib = offModRm + sizeof(bRm);
2556 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2557
2558 /* A displacement may follow SIB, update its offset. */
2559 offDisp += sizeof(bSib);
2560
2561 /* Get the scale. */
2562 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2563
2564 /* Get the index register. */
2565 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2566 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2567
2568 /* Get the base register. */
2569 iBaseReg = bSib & X86_SIB_BASE_MASK;
2570 fBaseRegValid = true;
2571 if (iBaseReg == 5)
2572 {
2573 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2574 {
2575 /* Mod is 0 implies a 32-bit displacement with no base. */
2576 fBaseRegValid = false;
2577 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2578 }
2579 else
2580 {
2581 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2582 iBaseReg = X86_GREG_xBP;
2583 }
2584 }
2585 }
2586
2587 /* Register + displacement. */
2588 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2589 {
2590 case 0: /* Handled above */ break;
2591 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2592 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2593 default:
2594 {
2595 /* Register addressing, handled at the beginning. */
2596 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2597 break;
2598 }
2599 }
2600 }
2601
2602 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2603 }
2604 else
2605 {
2606 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2607
2608 /*
2609 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2610 * See Intel instruction spec. 2.2 "IA-32e Mode".
2611 */
2612 uint64_t u64Disp = 0;
2613 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2614 if (fRipRelativeAddr)
2615 {
2616 /*
2617 * RIP-relative addressing mode.
2618 *
2619 * The displacement is 32-bit signed implying an offset range of +/-2G.
2620 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2621 */
2622 uint8_t const offDisp = offModRm + sizeof(bRm);
2623 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2624 }
2625 else
2626 {
2627 uint8_t offDisp = offModRm + sizeof(bRm);
2628
2629 /*
2630 * Register (and perhaps scale, index and base).
2631 *
2632 * REX.B extends the most-significant bit of the base register. However, REX.B
2633 * is ignored while determining whether an SIB follows the opcode. Hence, we
2634 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2635 *
2636 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2637 */
2638 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2639 if (iBaseReg == 4)
2640 {
2641 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2642 uint8_t bSib;
2643 uint8_t const offSib = offModRm + sizeof(bRm);
2644 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2645
2646 /* Displacement may follow SIB, update its offset. */
2647 offDisp += sizeof(bSib);
2648
2649 /* Get the scale. */
2650 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2651
2652 /* Get the index. */
2653 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2654 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2655
2656 /* Get the base. */
2657 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2658 fBaseRegValid = true;
2659 if (iBaseReg == 5)
2660 {
2661 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2662 {
2663 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2664 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2665 }
2666 else
2667 {
2668 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2669 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2670 }
2671 }
2672 }
2673 iBaseReg |= pVCpu->iem.s.uRexB;
2674
2675 /* Register + displacement. */
2676 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2677 {
2678 case 0: /* Handled above */ break;
2679 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2680 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2681 default:
2682 {
2683 /* Register addressing, handled at the beginning. */
2684 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2685 break;
2686 }
2687 }
2688 }
2689
2690 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2691 }
2692
2693 /*
2694 * The primary or secondary register operand is reported in iReg2 depending
2695 * on whether the primary operand is in read/write form.
2696 */
2697 uint8_t idxReg2;
2698 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2699 {
2700 idxReg2 = bRm & X86_MODRM_RM_MASK;
2701 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2702 idxReg2 |= pVCpu->iem.s.uRexB;
2703 }
2704 else
2705 {
2706 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2707 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2708 idxReg2 |= pVCpu->iem.s.uRexReg;
2709 }
2710 ExitInstrInfo.All.u2Scaling = uScale;
2711 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2712 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2713 ExitInstrInfo.All.fIsRegOperand = 0;
2714 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2715 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2716 ExitInstrInfo.All.iIdxReg = iIdxReg;
2717 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2718 ExitInstrInfo.All.iBaseReg = iBaseReg;
2719 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2720 ExitInstrInfo.All.iReg2 = idxReg2;
2721 }
2722
2723 /*
2724 * Handle exceptions to the norm for certain instructions.
2725 * (e.g. some instructions convey an instruction identity in place of iReg2).
2726 */
2727 switch (uExitReason)
2728 {
2729 case VMX_EXIT_GDTR_IDTR_ACCESS:
2730 {
2731 Assert(VMXINSTRID_IS_VALID(uInstrId));
2732 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2733 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2734 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2735 break;
2736 }
2737
2738 case VMX_EXIT_LDTR_TR_ACCESS:
2739 {
2740 Assert(VMXINSTRID_IS_VALID(uInstrId));
2741 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2742 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2743 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2744 break;
2745 }
2746
2747 case VMX_EXIT_RDRAND:
2748 case VMX_EXIT_RDSEED:
2749 {
2750 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2751 break;
2752 }
2753 }
2754
2755 /* Update displacement and return the constructed VM-exit instruction information field. */
2756 if (pGCPtrDisp)
2757 *pGCPtrDisp = GCPtrDisp;
2758
2759 return ExitInstrInfo.u;
2760}
2761
2762
2763/**
2764 * VMX VM-exit handler.
2765 *
2766 * @returns Strict VBox status code.
2767 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2768 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2769 * triple-fault.
2770 *
2771 * @param pVCpu The cross context virtual CPU structure.
2772 * @param uExitReason The VM-exit reason.
2773 *
2774 * @remarks Make sure VM-exit qualification is updated before calling this
2775 * function!
2776 */
2777IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2778{
2779# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2780 RT_NOREF2(pVCpu, uExitReason);
2781 return VINF_EM_RAW_EMULATE_INSTR;
2782# else
2783 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2784 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2785 | CPUMCTX_EXTRN_EFER /* MSRs */
2786 | CPUMCTX_EXTRN_SYSENTER_MSRS
2787 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2788 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2789 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2790 | CPUMCTX_EXTRN_TR /* Task register */
2791 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2792 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2793
2794 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2795 Assert(pVmcs);
2796
2797 /* Ensure VM-entry interruption information valid bit isn't set. */
2798 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2799
2800 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2801 pVmcs->u32RoExitReason = uExitReason;
2802 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2803 IEM_GET_CTX(pVCpu)->cs.Sel, IEM_GET_CTX(pVCpu)->rip));
2804
2805 /*
2806 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2807 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2808 */
2809 {
2810 uint8_t uVector;
2811 uint32_t fFlags;
2812 uint32_t uErrCode;
2813 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2814 if (!fInEventDelivery)
2815 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2816 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2817 }
2818
2819 /*
2820 * Save the guest state back into the VMCS.
2821 * We only need to save the state when the VM-entry was successful.
2822 */
2823 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2824 if (!fVmentryFailed)
2825 {
2826 /*
2827 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2828 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2829 *
2830 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2831 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2832 * as guest-CPU state would not been modified. Hence for now, we do this only when
2833 * the VM-entry succeeded.
2834 */
2835 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2836 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2837 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2838 {
2839 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2840 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2841 else
2842 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2843 }
2844
2845 /*
2846 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2847 * occurs in enclave mode/SMM which we don't support yet.
2848 *
2849 * If we ever add support for it, we can pass just the lower bits to the functions
2850 * below, till then an assert should suffice.
2851 */
2852 Assert(!RT_HI_U16(uExitReason));
2853
2854 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2855 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2856 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2857 if (RT_SUCCESS(rc))
2858 { /* likely */ }
2859 else
2860 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2861
2862 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2863 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2864 }
2865 else
2866 {
2867 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2868 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2869 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2870 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2871 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2872 }
2873
2874 /*
2875 * Clear any pending VMX nested-guest force-flags.
2876 * These force-flags have no effect on guest execution and will
2877 * be re-evaluated and setup on the next nested-guest VM-entry.
2878 */
2879 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2880 | VMCPU_FF_VMX_MTF
2881 | VMCPU_FF_VMX_APIC_WRITE
2882 | VMCPU_FF_VMX_INT_WINDOW
2883 | VMCPU_FF_VMX_NMI_WINDOW);
2884
2885 /* Restore the host (outer guest) state. */
2886 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2887 if (RT_SUCCESS(rcStrict))
2888 {
2889 Assert(rcStrict == VINF_SUCCESS);
2890 rcStrict = VINF_VMX_VMEXIT;
2891 }
2892 else
2893 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2894
2895 /* We're no longer in nested-guest execution mode. */
2896 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2897
2898 /* Revert any IEM-only nested-guest execution policy if it was set earlier, otherwise return rcStrict. */
2899 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(pVCpu, "VM-exit", rcStrict);
2900# endif
2901}
2902
2903
2904/**
2905 * VMX VM-exit handler for VM-exits due to instruction execution.
2906 *
2907 * This is intended for instructions where the caller provides all the relevant
2908 * VM-exit information.
2909 *
2910 * @returns Strict VBox status code.
2911 * @param pVCpu The cross context virtual CPU structure.
2912 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2913 */
2914DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2915{
2916 /*
2917 * For instructions where any of the following fields are not applicable:
2918 * - VM-exit instruction info. is undefined.
2919 * - VM-exit qualification must be cleared.
2920 * - VM-exit guest-linear address is undefined.
2921 * - VM-exit guest-physical address is undefined.
2922 *
2923 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2924 * instruction execution. For VM-exits that are not due to instruction execution this
2925 * field is undefined.
2926 *
2927 * In our implementation in IEM, all undefined fields are generally cleared. However,
2928 * if the caller supplies information (from say the physical CPU directly) it is
2929 * then possible that the undefined fields are not cleared.
2930 *
2931 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2932 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2933 */
2934 Assert(pExitInfo);
2935 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2936 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2937 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2938
2939 /* Update all the relevant fields from the VM-exit instruction information struct. */
2940 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2941 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2942 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2943 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2944 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2945
2946 /* Perform the VM-exit. */
2947 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2948}
2949
2950
2951/**
2952 * VMX VM-exit handler for VM-exits due to instruction execution.
2953 *
2954 * This is intended for instructions that only provide the VM-exit instruction
2955 * length.
2956 *
2957 * @param pVCpu The cross context virtual CPU structure.
2958 * @param uExitReason The VM-exit reason.
2959 * @param cbInstr The instruction length in bytes.
2960 */
2961IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2962{
2963 VMXVEXITINFO ExitInfo;
2964 RT_ZERO(ExitInfo);
2965 ExitInfo.uReason = uExitReason;
2966 ExitInfo.cbInstr = cbInstr;
2967
2968#ifdef VBOX_STRICT
2969 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2970 switch (uExitReason)
2971 {
2972 case VMX_EXIT_INVEPT:
2973 case VMX_EXIT_INVPCID:
2974 case VMX_EXIT_LDTR_TR_ACCESS:
2975 case VMX_EXIT_GDTR_IDTR_ACCESS:
2976 case VMX_EXIT_VMCLEAR:
2977 case VMX_EXIT_VMPTRLD:
2978 case VMX_EXIT_VMPTRST:
2979 case VMX_EXIT_VMREAD:
2980 case VMX_EXIT_VMWRITE:
2981 case VMX_EXIT_VMXON:
2982 case VMX_EXIT_XRSTORS:
2983 case VMX_EXIT_XSAVES:
2984 case VMX_EXIT_RDRAND:
2985 case VMX_EXIT_RDSEED:
2986 case VMX_EXIT_IO_INSTR:
2987 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2988 break;
2989 }
2990#endif
2991
2992 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2993}
2994
2995
2996/**
2997 * VMX VM-exit handler for VM-exits due to instruction execution.
2998 *
2999 * This is intended for instructions that have a ModR/M byte and update the VM-exit
3000 * instruction information and VM-exit qualification fields.
3001 *
3002 * @param pVCpu The cross context virtual CPU structure.
3003 * @param uExitReason The VM-exit reason.
3004 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
3005 * @param cbInstr The instruction length in bytes.
3006 *
3007 * @remarks Do not use this for INS/OUTS instruction.
3008 */
3009IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
3010{
3011 VMXVEXITINFO ExitInfo;
3012 RT_ZERO(ExitInfo);
3013 ExitInfo.uReason = uExitReason;
3014 ExitInfo.cbInstr = cbInstr;
3015
3016 /*
3017 * Update the VM-exit qualification field with displacement bytes.
3018 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3019 */
3020 switch (uExitReason)
3021 {
3022 case VMX_EXIT_INVEPT:
3023 case VMX_EXIT_INVPCID:
3024 case VMX_EXIT_LDTR_TR_ACCESS:
3025 case VMX_EXIT_GDTR_IDTR_ACCESS:
3026 case VMX_EXIT_VMCLEAR:
3027 case VMX_EXIT_VMPTRLD:
3028 case VMX_EXIT_VMPTRST:
3029 case VMX_EXIT_VMREAD:
3030 case VMX_EXIT_VMWRITE:
3031 case VMX_EXIT_VMXON:
3032 case VMX_EXIT_XRSTORS:
3033 case VMX_EXIT_XSAVES:
3034 case VMX_EXIT_RDRAND:
3035 case VMX_EXIT_RDSEED:
3036 {
3037 /* Construct the VM-exit instruction information. */
3038 RTGCPTR GCPtrDisp;
3039 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3040
3041 /* Update the VM-exit instruction information. */
3042 ExitInfo.InstrInfo.u = uInstrInfo;
3043
3044 /* Update the VM-exit qualification. */
3045 ExitInfo.u64Qual = GCPtrDisp;
3046 break;
3047 }
3048
3049 default:
3050 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3051 break;
3052 }
3053
3054 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3055}
3056
3057
3058/**
3059 * Checks whether an I/O instruction for the given port is intercepted (causes a
3060 * VM-exit) or not.
3061 *
3062 * @returns @c true if the instruction is intercepted, @c false otherwise.
3063 * @param pVCpu The cross context virtual CPU structure.
3064 * @param u16Port The I/O port being accessed by the instruction.
3065 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3066 */
3067IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3068{
3069 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3070 Assert(pVmcs);
3071
3072 /*
3073 * Check whether the I/O instruction must cause a VM-exit or not.
3074 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3075 */
3076 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3077 return true;
3078
3079 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3080 {
3081 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3082 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3083 Assert(pbIoBitmapA);
3084 Assert(pbIoBitmapB);
3085 return HMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3086 }
3087
3088 return false;
3089}
3090
3091
3092/**
3093 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3094 *
3095 * @returns Strict VBox status code.
3096 * @param pVCpu The cross context virtual CPU structure.
3097 */
3098IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3099{
3100 /*
3101 * The MTF VM-exit can occur even when the MTF VM-execution control is
3102 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3103 * check for the intercept here.
3104 */
3105 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3106}
3107
3108
3109/**
3110 * VMX VM-exit handler for VM-exits due to INVLPG.
3111 *
3112 * @returns Strict VBox status code.
3113 * @param pVCpu The cross context virtual CPU structure.
3114 * @param GCPtrPage The guest-linear address of the page being invalidated.
3115 * @param cbInstr The instruction length in bytes.
3116 */
3117IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3118{
3119 VMXVEXITINFO ExitInfo;
3120 RT_ZERO(ExitInfo);
3121 ExitInfo.uReason = VMX_EXIT_INVLPG;
3122 ExitInfo.cbInstr = cbInstr;
3123 ExitInfo.u64Qual = GCPtrPage;
3124 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3125
3126 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3127}
3128
3129
3130/**
3131 * VMX VM-exit handler for VM-exits due to LMSW.
3132 *
3133 * @returns Strict VBox status code.
3134 * @param pVCpu The cross context virtual CPU structure.
3135 * @param uGuestCr0 The current guest CR0.
3136 * @param pu16NewMsw The machine-status word specified in LMSW's source
3137 * operand. This will be updated depending on the VMX
3138 * guest/host CR0 mask if LMSW is not intercepted.
3139 * @param GCPtrEffDst The guest-linear address of the source operand in case
3140 * of a memory operand. For register operand, pass
3141 * NIL_RTGCPTR.
3142 * @param cbInstr The instruction length in bytes.
3143 */
3144IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3145 uint8_t cbInstr)
3146{
3147 /*
3148 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3149 *
3150 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3151 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3152 */
3153 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3154 Assert(pVmcs);
3155 Assert(pu16NewMsw);
3156
3157 bool fIntercept = false;
3158 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3159 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3160
3161 /*
3162 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3163 * CR0.PE case first, before the rest of the bits in the MSW.
3164 *
3165 * If CR0.PE is owned by the host and CR0.PE differs between the
3166 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3167 */
3168 if ( (fGstHostMask & X86_CR0_PE)
3169 && (*pu16NewMsw & X86_CR0_PE)
3170 && !(fReadShadow & X86_CR0_PE))
3171 fIntercept = true;
3172
3173 /*
3174 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3175 * bits differ between the MSW (source operand) and the read-shadow, we must
3176 * cause a VM-exit.
3177 */
3178 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3179 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3180 fIntercept = true;
3181
3182 if (fIntercept)
3183 {
3184 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3185
3186 VMXVEXITINFO ExitInfo;
3187 RT_ZERO(ExitInfo);
3188 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3189 ExitInfo.cbInstr = cbInstr;
3190
3191 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3192 if (fMemOperand)
3193 {
3194 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3195 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3196 }
3197
3198 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3201 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3202
3203 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3204 }
3205
3206 /*
3207 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3208 * CR0 guest/host mask must be left unmodified.
3209 *
3210 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3211 */
3212 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3213 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3214
3215 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3216}
3217
3218
3219/**
3220 * VMX VM-exit handler for VM-exits due to CLTS.
3221 *
3222 * @returns Strict VBox status code.
3223 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3224 * VM-exit but must not modify the guest CR0.TS bit.
3225 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3226 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3227 * CR0 fixed bits in VMX operation).
3228 * @param pVCpu The cross context virtual CPU structure.
3229 * @param cbInstr The instruction length in bytes.
3230 */
3231IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3232{
3233 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3234 Assert(pVmcs);
3235
3236 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3237 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3238
3239 /*
3240 * If CR0.TS is owned by the host:
3241 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3242 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3243 * CLTS instruction completes without clearing CR0.TS.
3244 *
3245 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3246 */
3247 if (fGstHostMask & X86_CR0_TS)
3248 {
3249 if (fReadShadow & X86_CR0_TS)
3250 {
3251 Log2(("clts: Guest intercept -> VM-exit\n"));
3252
3253 VMXVEXITINFO ExitInfo;
3254 RT_ZERO(ExitInfo);
3255 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3256 ExitInfo.cbInstr = cbInstr;
3257 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3258 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3259 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3260 }
3261
3262 return VINF_VMX_MODIFIES_BEHAVIOR;
3263 }
3264
3265 /*
3266 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3267 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3268 */
3269 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3270}
3271
3272
3273/**
3274 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3275 * (CR0/CR4 write).
3276 *
3277 * @returns Strict VBox status code.
3278 * @param pVCpu The cross context virtual CPU structure.
3279 * @param iCrReg The control register (either CR0 or CR4).
3280 * @param uGuestCrX The current guest CR0/CR4.
3281 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3282 * if no VM-exit is caused.
3283 * @param iGReg The general register from which the CR0/CR4 value is
3284 * being loaded.
3285 * @param cbInstr The instruction length in bytes.
3286 */
3287IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3288 uint8_t cbInstr)
3289{
3290 Assert(puNewCrX);
3291 Assert(iCrReg == 0 || iCrReg == 4);
3292 Assert(iGReg < X86_GREG_COUNT);
3293
3294 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3295 Assert(pVmcs);
3296
3297 uint64_t uGuestCrX;
3298 uint64_t fGstHostMask;
3299 uint64_t fReadShadow;
3300 if (iCrReg == 0)
3301 {
3302 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3303 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3304 fGstHostMask = pVmcs->u64Cr0Mask.u;
3305 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3306 }
3307 else
3308 {
3309 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3310 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3311 fGstHostMask = pVmcs->u64Cr4Mask.u;
3312 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3313 }
3314
3315 /*
3316 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3317 * corresponding bits differ between the source operand and the read-shadow,
3318 * we must cause a VM-exit.
3319 *
3320 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3321 */
3322 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3323 {
3324 Assert(fGstHostMask != 0);
3325 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3326
3327 VMXVEXITINFO ExitInfo;
3328 RT_ZERO(ExitInfo);
3329 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3330 ExitInfo.cbInstr = cbInstr;
3331 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3332 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3333 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3334 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3335 }
3336
3337 /*
3338 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3339 * must not be modified the instruction.
3340 *
3341 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3342 */
3343 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3344
3345 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3346}
3347
3348
3349/**
3350 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3351 *
3352 * @returns VBox strict status code.
3353 * @param pVCpu The cross context virtual CPU structure.
3354 * @param iGReg The general register to which the CR3 value is being stored.
3355 * @param cbInstr The instruction length in bytes.
3356 */
3357IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3358{
3359 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3360 Assert(pVmcs);
3361 Assert(iGReg < X86_GREG_COUNT);
3362 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3363
3364 /*
3365 * If the CR3-store exiting control is set, we must cause a VM-exit.
3366 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3367 */
3368 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3369 {
3370 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3371
3372 VMXVEXITINFO ExitInfo;
3373 RT_ZERO(ExitInfo);
3374 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3375 ExitInfo.cbInstr = cbInstr;
3376 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3377 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3378 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3379 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3380 }
3381
3382 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3383}
3384
3385
3386/**
3387 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3388 *
3389 * @returns VBox strict status code.
3390 * @param pVCpu The cross context virtual CPU structure.
3391 * @param uNewCr3 The new CR3 value.
3392 * @param iGReg The general register from which the CR3 value is being
3393 * loaded.
3394 * @param cbInstr The instruction length in bytes.
3395 */
3396IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3397{
3398 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3399 Assert(pVmcs);
3400 Assert(iGReg < X86_GREG_COUNT);
3401
3402 /*
3403 * If the CR3-load exiting control is set and the new CR3 value does not
3404 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3405 *
3406 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3407 */
3408 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3409 {
3410 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3411 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3412
3413 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3414 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3415 if (!fIntercept)
3416 {
3417 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3418 {
3419 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3420 if (uNewCr3 != uCr3TargetValue)
3421 {
3422 fIntercept = true;
3423 break;
3424 }
3425 }
3426 }
3427
3428 if (fIntercept)
3429 {
3430 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3431
3432 VMXVEXITINFO ExitInfo;
3433 RT_ZERO(ExitInfo);
3434 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3435 ExitInfo.cbInstr = cbInstr;
3436 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3437 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3438 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3439 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3440 }
3441 }
3442
3443 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3444}
3445
3446
3447/**
3448 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3449 *
3450 * @returns VBox strict status code.
3451 * @param pVCpu The cross context virtual CPU structure.
3452 * @param iGReg The general register to which the CR8 value is being stored.
3453 * @param cbInstr The instruction length in bytes.
3454 */
3455IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3456{
3457 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3458 Assert(pVmcs);
3459 Assert(iGReg < X86_GREG_COUNT);
3460
3461 /*
3462 * If the CR8-store exiting control is set, we must cause a VM-exit.
3463 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3464 */
3465 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3466 {
3467 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3468
3469 VMXVEXITINFO ExitInfo;
3470 RT_ZERO(ExitInfo);
3471 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3472 ExitInfo.cbInstr = cbInstr;
3473 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3474 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3476 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3477 }
3478
3479 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480}
3481
3482
3483/**
3484 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3485 *
3486 * @returns VBox strict status code.
3487 * @param pVCpu The cross context virtual CPU structure.
3488 * @param iGReg The general register from which the CR8 value is being
3489 * loaded.
3490 * @param cbInstr The instruction length in bytes.
3491 */
3492IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3493{
3494 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3495 Assert(pVmcs);
3496 Assert(iGReg < X86_GREG_COUNT);
3497
3498 /*
3499 * If the CR8-load exiting control is set, we must cause a VM-exit.
3500 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3501 */
3502 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3503 {
3504 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3505
3506 VMXVEXITINFO ExitInfo;
3507 RT_ZERO(ExitInfo);
3508 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3509 ExitInfo.cbInstr = cbInstr;
3510 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3511 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3512 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3513 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3514 }
3515
3516 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3517}
3518
3519
3520/**
3521 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3522 * GReg,DRx' (DRx read).
3523 *
3524 * @returns VBox strict status code.
3525 * @param pVCpu The cross context virtual CPU structure.
3526 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3527 * VMXINSTRID_MOV_FROM_DRX).
3528 * @param iDrReg The debug register being accessed.
3529 * @param iGReg The general register to/from which the DRx value is being
3530 * store/loaded.
3531 * @param cbInstr The instruction length in bytes.
3532 */
3533IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3534 uint8_t cbInstr)
3535{
3536 Assert(iDrReg <= 7);
3537 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3538 Assert(iGReg < X86_GREG_COUNT);
3539
3540 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3541 Assert(pVmcs);
3542
3543 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3544 {
3545 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3546 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3547 VMXVEXITINFO ExitInfo;
3548 RT_ZERO(ExitInfo);
3549 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3550 ExitInfo.cbInstr = cbInstr;
3551 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3552 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3553 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3554 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3555 }
3556
3557 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3558}
3559
3560
3561/**
3562 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3563 *
3564 * @returns VBox strict status code.
3565 * @param pVCpu The cross context virtual CPU structure.
3566 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3567 * VMXINSTRID_IO_OUT).
3568 * @param u16Port The I/O port being accessed.
3569 * @param fImm Whether the I/O port was encoded using an immediate operand
3570 * or the implicit DX register.
3571 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3572 * @param cbInstr The instruction length in bytes.
3573 */
3574IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3575 uint8_t cbInstr)
3576{
3577 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3578 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3579
3580 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3581 if (fIntercept)
3582 {
3583 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3584 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3585 VMXVEXITINFO ExitInfo;
3586 RT_ZERO(ExitInfo);
3587 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3588 ExitInfo.cbInstr = cbInstr;
3589 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3590 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3591 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3592 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3593 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3594 }
3595
3596 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3597}
3598
3599
3600/**
3601 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3602 *
3603 * @returns VBox strict status code.
3604 * @param pVCpu The cross context virtual CPU structure.
3605 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3606 * VMXINSTRID_IO_OUTS).
3607 * @param u16Port The I/O port being accessed.
3608 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3609 * @param fRep Whether the instruction has a REP prefix or not.
3610 * @param ExitInstrInfo The VM-exit instruction info. field.
3611 * @param cbInstr The instruction length in bytes.
3612 */
3613IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3614 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3615{
3616 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3617 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3618 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3619 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3620 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3621
3622 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3623 if (fIntercept)
3624 {
3625 /*
3626 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3627 */
3628 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3629 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3630 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3631 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3632 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3633
3634 uint32_t uDirection;
3635 uint64_t uGuestLinearAddr;
3636 if (uInstrId == VMXINSTRID_IO_INS)
3637 {
3638 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3639 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3640 }
3641 else
3642 {
3643 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3644 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3645 }
3646
3647 /*
3648 * If the segment is ununsable, the guest-linear address in undefined.
3649 * We shall clear it for consistency.
3650 *
3651 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3652 */
3653 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3654 uGuestLinearAddr = 0;
3655
3656 VMXVEXITINFO ExitInfo;
3657 RT_ZERO(ExitInfo);
3658 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3659 ExitInfo.cbInstr = cbInstr;
3660 ExitInfo.InstrInfo = ExitInstrInfo;
3661 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3662 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3663 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3664 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3665 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3666 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3667 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3668 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3669 }
3670
3671 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3672}
3673
3674
3675/**
3676 * VMX VM-exit handler for VM-exits due to MWAIT.
3677 *
3678 * @returns VBox strict status code.
3679 * @param pVCpu The cross context virtual CPU structure.
3680 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3681 * @param cbInstr The instruction length in bytes.
3682 */
3683IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3684{
3685 VMXVEXITINFO ExitInfo;
3686 RT_ZERO(ExitInfo);
3687 ExitInfo.uReason = VMX_EXIT_MWAIT;
3688 ExitInfo.cbInstr = cbInstr;
3689 ExitInfo.u64Qual = fMonitorHwArmed;
3690 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3691}
3692
3693
3694/**
3695 * VMX VM-exit handler for VM-exits due to PAUSE.
3696 *
3697 * @returns VBox strict status code.
3698 * @param pVCpu The cross context virtual CPU structure.
3699 * @param cbInstr The instruction length in bytes.
3700 */
3701IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3702{
3703 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3704 Assert(pVmcs);
3705
3706 /*
3707 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3708 * "PAUSE-loop exiting" control.
3709 *
3710 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3711 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3712 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3713 * a VM-exit.
3714 *
3715 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3716 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3717 */
3718 bool fIntercept = false;
3719 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3720 fIntercept = true;
3721 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3722 && pVCpu->iem.s.uCpl == 0)
3723 {
3724 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3725
3726 /*
3727 * A previous-PAUSE-tick value of 0 is used to identify the first time
3728 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3729 * consider this to be the first execution of PAUSE in a loop according
3730 * to the Intel.
3731 *
3732 * All subsequent records for the previous-PAUSE-tick we ensure that it
3733 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3734 */
3735 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3736 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3737 uint64_t const uTick = TMCpuTickGet(pVCpu);
3738 uint32_t const uPleGap = pVmcs->u32PleGap;
3739 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3740 if ( *puPrevPauseTick == 0
3741 || uTick - *puPrevPauseTick > uPleGap)
3742 *puFirstPauseLoopTick = uTick;
3743 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3744 fIntercept = true;
3745
3746 *puPrevPauseTick = uTick | 1;
3747 }
3748
3749 if (fIntercept)
3750 {
3751 VMXVEXITINFO ExitInfo;
3752 RT_ZERO(ExitInfo);
3753 ExitInfo.uReason = VMX_EXIT_PAUSE;
3754 ExitInfo.cbInstr = cbInstr;
3755 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3756 }
3757
3758 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3759}
3760
3761
3762/**
3763 * VMX VM-exit handler for VM-exits due to task switches.
3764 *
3765 * @returns VBox strict status code.
3766 * @param pVCpu The cross context virtual CPU structure.
3767 * @param enmTaskSwitch The cause of the task switch.
3768 * @param SelNewTss The selector of the new TSS.
3769 * @param cbInstr The instruction length in bytes.
3770 */
3771IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3772{
3773 /*
3774 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3775 *
3776 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3777 * instruction or delivery of the exception generated by one of these instructions
3778 * lead to a task switch through a task gate in the IDT, we need to provide the
3779 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3780 * leaves the VM-exit instruction length field undefined.
3781 *
3782 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3783 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3784 */
3785 Assert(cbInstr <= 15);
3786
3787 uint8_t uType;
3788 switch (enmTaskSwitch)
3789 {
3790 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3791 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3792 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3793 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3794 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3795 }
3796
3797 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3798 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3799 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3800 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3801 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3802}
3803
3804
3805/**
3806 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3807 *
3808 * @returns VBox strict status code.
3809 * @param pVCpu The cross context virtual CPU structure.
3810 */
3811IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3812{
3813 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3814 Assert(pVmcs);
3815
3816 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3817 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3818 {
3819 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3820 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3821
3822 /*
3823 * Calculate the current VMX-preemption timer value.
3824 * Only if the value has reached zero, we cause the VM-exit.
3825 */
3826 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3827 if (!uPreemptTimer)
3828 {
3829 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3830 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3831 pVmcs->u32PreemptTimer = 0;
3832
3833 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3834 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3835 }
3836 }
3837
3838 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3839}
3840
3841
3842/**
3843 * VMX VM-exit handler for VM-exits due to external interrupts.
3844 *
3845 * @returns VBox strict status code.
3846 * @param pVCpu The cross context virtual CPU structure.
3847 * @param uVector The external interrupt vector (pass 0 if the interrupt
3848 * is still pending since we typically won't know the
3849 * vector).
3850 * @param fIntPending Whether the external interrupt is pending or
3851 * acknowledged in the interrupt controller.
3852 */
3853IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3854{
3855 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3856 Assert(pVmcs);
3857 Assert(fIntPending || uVector == 0);
3858
3859 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3860 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3861 * functions require prior checking of a blanket intercept and which don't.
3862 * It is better for the caller to check a blanket intercept performance wise
3863 * than making a function call. Leaving this as a todo because it is more
3864 * a performance issue. */
3865
3866 /* The VM-exit is subject to "External interrupt exiting" being set. */
3867 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3868 {
3869 if (fIntPending)
3870 {
3871 /*
3872 * If the interrupt is pending and we don't need to acknowledge the
3873 * interrupt on VM-exit, cause the VM-exit immediately.
3874 *
3875 * See Intel spec 25.2 "Other Causes Of VM Exits".
3876 */
3877 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3878 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3879
3880 /*
3881 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3882 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3883 * acknowledged that the interrupt has been consumed.
3884 */
3885 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3886 }
3887
3888 /*
3889 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3890 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3891 * all set, we cause the VM-exit now. We need to record the external interrupt that
3892 * just occurred in the VM-exit interruption information field.
3893 *
3894 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3895 */
3896 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3897 {
3898 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3899 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3900 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3901 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3902 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3903 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3904 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3905 }
3906 }
3907
3908 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3909}
3910
3911
3912/**
3913 * VMX VM-exit handler for VM-exits due to NMIs.
3914 *
3915 * @returns VBox strict status code.
3916 * @param pVCpu The cross context virtual CPU structure.
3917 *
3918 * @remarks This function might import externally kept DR6 if necessary.
3919 */
3920IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3921{
3922 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3923 Assert(pVmcs);
3924 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3925 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3926 NOREF(pVmcs);
3927 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3928}
3929
3930
3931/**
3932 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3933 *
3934 * @returns VBox strict status code.
3935 * @param pVCpu The cross context virtual CPU structure.
3936 * @param uVector The SIPI vector.
3937 */
3938IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3939{
3940 iemVmxVmcsSetExitQual(pVCpu, uVector);
3941 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3942}
3943
3944
3945/**
3946 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3947 *
3948 * @returns VBox strict status code.
3949 * @param pVCpu The cross context virtual CPU structure.
3950 */
3951IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3952{
3953 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3954}
3955
3956
3957/**
3958 * VMX VM-exit handler for interrupt-window VM-exits.
3959 *
3960 * @returns VBox strict status code.
3961 * @param pVCpu The cross context virtual CPU structure.
3962 */
3963IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3964{
3965 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3966}
3967
3968
3969/**
3970 * VMX VM-exit handler for NMI-window VM-exits.
3971 *
3972 * @returns VBox strict status code.
3973 * @param pVCpu The cross context virtual CPU structure.
3974 */
3975IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmiWindow(PVMCPU pVCpu)
3976{
3977 return iemVmxVmexit(pVCpu, VMX_EXIT_NMI_WINDOW);
3978}
3979
3980
3981/**
3982 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3983 * an event.
3984 *
3985 * @returns VBox strict status code.
3986 * @param pVCpu The cross context virtual CPU structure.
3987 */
3988IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3989{
3990 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3991 Assert(pVmcs);
3992
3993 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3994 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3995 {
3996 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3997 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3998 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3999 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
4000 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4001 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4002 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4003 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4004 iemVmxVmcsSetExitQual(pVCpu, 0);
4005 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4006
4007 /*
4008 * A VM-exit is not considered to occur during event delivery when the original
4009 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
4010 * using the exception bitmap).
4011 *
4012 * Therefore, we must clear the original event from the IDT-vectoring fields which
4013 * would've been recorded before causing the VM-exit.
4014 *
4015 * 27.2.3 "Information for VM Exits During Event Delivery"
4016 */
4017 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4018 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4019
4020 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4021 }
4022
4023 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4024}
4025
4026
4027/**
4028 * VMX VM-exit handler for VM-exits due to delivery of an event.
4029 *
4030 * @returns VBox strict status code.
4031 * @param pVCpu The cross context virtual CPU structure.
4032 * @param uVector The interrupt / exception vector.
4033 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
4034 * @param uErrCode The error code associated with the event.
4035 * @param uCr2 The CR2 value in case of a \#PF exception.
4036 * @param cbInstr The instruction length in bytes.
4037 */
4038IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
4039 uint8_t cbInstr)
4040{
4041 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4042 Assert(pVmcs);
4043
4044 /*
4045 * If the event is being injected as part of VM-entry, it isn't subject to event
4046 * intercepts in the nested-guest. However, secondary exceptions that occur during
4047 * injection of any event -are- subject to event interception.
4048 *
4049 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
4050 */
4051 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
4052 {
4053 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
4054 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
4055 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4056 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
4057 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
4058 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
4059 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
4060 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
4061 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
4062
4063 /*
4064 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
4065 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
4066 *
4067 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
4068 */
4069 if ( uVector == X86_XCPT_NMI
4070 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
4071 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
4072 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
4073 else
4074 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
4075
4076 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4077 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4078 }
4079
4080 /*
4081 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4082 * If not, the caller will continue delivery of the external interrupt as it would
4083 * normally. The interrupt is no longer pending in the interrupt controller at this
4084 * point.
4085 */
4086 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4087 {
4088 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4089 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4090 }
4091
4092 /*
4093 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4094 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4095 */
4096 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4097 bool fIntercept = false;
4098 bool fIsHwXcpt = false;
4099 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4100 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4101 {
4102 fIsHwXcpt = true;
4103 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4104 if (uVector == X86_XCPT_NMI)
4105 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
4106 else
4107 {
4108 /* Page-faults are subject to masking using its error code. */
4109 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4110 if (uVector == X86_XCPT_PF)
4111 {
4112 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4113 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4114 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4115 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4116 }
4117
4118 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4119 if (fXcptBitmap & RT_BIT(uVector))
4120 fIntercept = true;
4121 }
4122 }
4123 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4124
4125 /*
4126 * Now that we've determined whether the software interrupt or hardware exception
4127 * causes a VM-exit, we need to construct the relevant VM-exit information and
4128 * cause the VM-exit.
4129 */
4130 if (fIntercept)
4131 {
4132 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4133
4134 /* Construct the rest of the event related information fields and cause the VM-exit. */
4135 uint64_t uExitQual = 0;
4136 if (fIsHwXcpt)
4137 {
4138 if (uVector == X86_XCPT_PF)
4139 {
4140 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4141 uExitQual = uCr2;
4142 }
4143 else if (uVector == X86_XCPT_DB)
4144 {
4145 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4146 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4147 }
4148 }
4149
4150 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4151 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4152 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4153 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4154 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4155 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4156 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4157 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4158 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4159 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4160 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4161
4162 /*
4163 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4164 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4165 * length.
4166 */
4167 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4168 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4169 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4170 else
4171 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4172
4173 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4174 }
4175
4176 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4177}
4178
4179
4180/**
4181 * VMX VM-exit handler for VM-exits due to a triple fault.
4182 *
4183 * @returns VBox strict status code.
4184 * @param pVCpu The cross context virtual CPU structure.
4185 */
4186IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4187{
4188 /*
4189 * A VM-exit is not considered to occur during event delivery when the original
4190 * event results in a triple-fault.
4191 *
4192 * Therefore, we must clear the original event from the IDT-vectoring fields which
4193 * would've been recorded before causing the VM-exit.
4194 *
4195 * 27.2.3 "Information for VM Exits During Event Delivery"
4196 */
4197 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4198 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4199
4200 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4201}
4202
4203
4204/**
4205 * VMX VM-exit handler for APIC-accesses.
4206 *
4207 * @param pVCpu The cross context virtual CPU structure.
4208 * @param offAccess The offset of the register being accessed.
4209 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4210 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4211 */
4212IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4213{
4214 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4215
4216 VMXAPICACCESS enmAccess;
4217 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4218 if (fInEventDelivery)
4219 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4220 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4221 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4222 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4223 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4224 else
4225 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4226
4227 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4228 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4229 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4230 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4231}
4232
4233
4234/**
4235 * VMX VM-exit handler for APIC-write VM-exits.
4236 *
4237 * @param pVCpu The cross context virtual CPU structure.
4238 * @param offApic The write to the virtual-APIC page offset that caused this
4239 * VM-exit.
4240 */
4241IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4242{
4243 Assert(offApic < XAPIC_OFF_END + 4);
4244
4245 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4246 offApic &= UINT16_C(0xfff);
4247 iemVmxVmcsSetExitQual(pVCpu, offApic);
4248 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4249}
4250
4251
4252/**
4253 * VMX VM-exit handler for virtualized-EOIs.
4254 *
4255 * @param pVCpu The cross context virtual CPU structure.
4256 */
4257IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4258{
4259 iemVmxVmcsSetExitQual(pVCpu, uVector);
4260 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4261}
4262
4263
4264/**
4265 * Sets virtual-APIC write emulation as pending.
4266 *
4267 * @param pVCpu The cross context virtual CPU structure.
4268 * @param offApic The offset in the virtual-APIC page that was written.
4269 */
4270DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4271{
4272 Assert(offApic < XAPIC_OFF_END + 4);
4273
4274 /*
4275 * Record the currently updated APIC offset, as we need this later for figuring
4276 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4277 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4278 */
4279 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4280
4281 /*
4282 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4283 * virtualization or APIC-write emulation).
4284 */
4285 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4286 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4287}
4288
4289
4290/**
4291 * Clears any pending virtual-APIC write emulation.
4292 *
4293 * @returns The virtual-APIC offset that was written before clearing it.
4294 * @param pVCpu The cross context virtual CPU structure.
4295 */
4296DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4297{
4298 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4299 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4300 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4301 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4302 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4303 return offVirtApicWrite;
4304}
4305
4306
4307/**
4308 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4309 *
4310 * @returns The register from the virtual-APIC page.
4311 * @param pVCpu The cross context virtual CPU structure.
4312 * @param offReg The offset of the register being read.
4313 */
4314DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4315{
4316 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4317 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4318 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4319 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4320 return uReg;
4321}
4322
4323
4324/**
4325 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4326 *
4327 * @returns The register from the virtual-APIC page.
4328 * @param pVCpu The cross context virtual CPU structure.
4329 * @param offReg The offset of the register being read.
4330 */
4331DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4332{
4333 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4334 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4335 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4336 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4337 return uReg;
4338}
4339
4340
4341/**
4342 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4343 *
4344 * @param pVCpu The cross context virtual CPU structure.
4345 * @param offReg The offset of the register being written.
4346 * @param uReg The register value to write.
4347 */
4348DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4349{
4350 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4351 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4352 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4353 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4354}
4355
4356
4357/**
4358 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4359 *
4360 * @param pVCpu The cross context virtual CPU structure.
4361 * @param offReg The offset of the register being written.
4362 * @param uReg The register value to write.
4363 */
4364DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4365{
4366 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4367 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4368 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4369 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4370}
4371
4372
4373/**
4374 * Sets the vector in a virtual-APIC 256-bit sparse register.
4375 *
4376 * @param pVCpu The cross context virtual CPU structure.
4377 * @param offReg The offset of the 256-bit spare register.
4378 * @param uVector The vector to set.
4379 *
4380 * @remarks This is based on our APIC device code.
4381 */
4382DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4383{
4384 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4385 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4386 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4387 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4388 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4389}
4390
4391
4392/**
4393 * Clears the vector in a virtual-APIC 256-bit sparse register.
4394 *
4395 * @param pVCpu The cross context virtual CPU structure.
4396 * @param offReg The offset of the 256-bit spare register.
4397 * @param uVector The vector to clear.
4398 *
4399 * @remarks This is based on our APIC device code.
4400 */
4401DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4402{
4403 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4404 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4405 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4406 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4407 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4408}
4409
4410
4411/**
4412 * Checks if a memory access to the APIC-access page must causes an APIC-access
4413 * VM-exit.
4414 *
4415 * @param pVCpu The cross context virtual CPU structure.
4416 * @param offAccess The offset of the register being accessed.
4417 * @param cbAccess The size of the access in bytes.
4418 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4419 * IEM_ACCESS_TYPE_WRITE).
4420 *
4421 * @remarks This must not be used for MSR-based APIC-access page accesses!
4422 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4423 */
4424IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4425{
4426 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4427 Assert(pVmcs);
4428 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4429
4430 /*
4431 * We must cause a VM-exit if any of the following are true:
4432 * - TPR shadowing isn't active.
4433 * - The access size exceeds 32-bits.
4434 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4435 *
4436 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4437 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4438 */
4439 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4440 || cbAccess > sizeof(uint32_t)
4441 || ((offAccess + cbAccess - 1) & 0xc)
4442 || offAccess >= XAPIC_OFF_END + 4)
4443 return true;
4444
4445 /*
4446 * If the access is part of an operation where we have already
4447 * virtualized a virtual-APIC write, we must cause a VM-exit.
4448 */
4449 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4450 return true;
4451
4452 /*
4453 * Check write accesses to the APIC-access page that cause VM-exits.
4454 */
4455 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4456 {
4457 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4458 {
4459 /*
4460 * With APIC-register virtualization, a write access to any of the
4461 * following registers are virtualized. Accessing any other register
4462 * causes a VM-exit.
4463 */
4464 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4465 switch (offAlignedAccess)
4466 {
4467 case XAPIC_OFF_ID:
4468 case XAPIC_OFF_TPR:
4469 case XAPIC_OFF_EOI:
4470 case XAPIC_OFF_LDR:
4471 case XAPIC_OFF_DFR:
4472 case XAPIC_OFF_SVR:
4473 case XAPIC_OFF_ESR:
4474 case XAPIC_OFF_ICR_LO:
4475 case XAPIC_OFF_ICR_HI:
4476 case XAPIC_OFF_LVT_TIMER:
4477 case XAPIC_OFF_LVT_THERMAL:
4478 case XAPIC_OFF_LVT_PERF:
4479 case XAPIC_OFF_LVT_LINT0:
4480 case XAPIC_OFF_LVT_LINT1:
4481 case XAPIC_OFF_LVT_ERROR:
4482 case XAPIC_OFF_TIMER_ICR:
4483 case XAPIC_OFF_TIMER_DCR:
4484 break;
4485 default:
4486 return true;
4487 }
4488 }
4489 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4490 {
4491 /*
4492 * With virtual-interrupt delivery, a write access to any of the
4493 * following registers are virtualized. Accessing any other register
4494 * causes a VM-exit.
4495 *
4496 * Note! The specification does not allow writing to offsets in-between
4497 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4498 */
4499 switch (offAccess)
4500 {
4501 case XAPIC_OFF_TPR:
4502 case XAPIC_OFF_EOI:
4503 case XAPIC_OFF_ICR_LO:
4504 break;
4505 default:
4506 return true;
4507 }
4508 }
4509 else
4510 {
4511 /*
4512 * Without APIC-register virtualization or virtual-interrupt delivery,
4513 * only TPR accesses are virtualized.
4514 */
4515 if (offAccess == XAPIC_OFF_TPR)
4516 { /* likely */ }
4517 else
4518 return true;
4519 }
4520 }
4521 else
4522 {
4523 /*
4524 * Check read accesses to the APIC-access page that cause VM-exits.
4525 */
4526 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4527 {
4528 /*
4529 * With APIC-register virtualization, a read access to any of the
4530 * following registers are virtualized. Accessing any other register
4531 * causes a VM-exit.
4532 */
4533 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4534 switch (offAlignedAccess)
4535 {
4536 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4537 case XAPIC_OFF_ID:
4538 case XAPIC_OFF_VERSION:
4539 case XAPIC_OFF_TPR:
4540 case XAPIC_OFF_EOI:
4541 case XAPIC_OFF_LDR:
4542 case XAPIC_OFF_DFR:
4543 case XAPIC_OFF_SVR:
4544 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4545 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4546 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4547 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4548 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4549 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4550 case XAPIC_OFF_ESR:
4551 case XAPIC_OFF_ICR_LO:
4552 case XAPIC_OFF_ICR_HI:
4553 case XAPIC_OFF_LVT_TIMER:
4554 case XAPIC_OFF_LVT_THERMAL:
4555 case XAPIC_OFF_LVT_PERF:
4556 case XAPIC_OFF_LVT_LINT0:
4557 case XAPIC_OFF_LVT_LINT1:
4558 case XAPIC_OFF_LVT_ERROR:
4559 case XAPIC_OFF_TIMER_ICR:
4560 case XAPIC_OFF_TIMER_DCR:
4561 break;
4562 default:
4563 return true;
4564 }
4565 }
4566 else
4567 {
4568 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4569 if (offAccess == XAPIC_OFF_TPR)
4570 { /* likely */ }
4571 else
4572 return true;
4573 }
4574 }
4575
4576 /* The APIC-access is virtualized, does not cause a VM-exit. */
4577 return false;
4578}
4579
4580
4581/**
4582 * Virtualizes a memory-based APIC-access where the address is not used to access
4583 * memory.
4584 *
4585 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4586 * page-faults but do not use the address to access memory.
4587 *
4588 * @param pVCpu The cross context virtual CPU structure.
4589 * @param pGCPhysAccess Pointer to the guest-physical address used.
4590 */
4591IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4592{
4593 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4594 Assert(pVmcs);
4595 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4596 Assert(pGCPhysAccess);
4597
4598 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4599 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4600 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4601
4602 if (GCPhysAccess == GCPhysApic)
4603 {
4604 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4605 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4606 uint16_t const cbAccess = 1;
4607 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4608 if (fIntercept)
4609 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4610
4611 *pGCPhysAccess = GCPhysApic | offAccess;
4612 return VINF_VMX_MODIFIES_BEHAVIOR;
4613 }
4614
4615 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4616}
4617
4618
4619/**
4620 * Virtualizes a memory-based APIC-access.
4621 *
4622 * @returns VBox strict status code.
4623 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4624 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4625 *
4626 * @param pVCpu The cross context virtual CPU structure.
4627 * @param offAccess The offset of the register being accessed (within the
4628 * APIC-access page).
4629 * @param cbAccess The size of the access in bytes.
4630 * @param pvData Pointer to the data being written or where to store the data
4631 * being read.
4632 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4633 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4634 */
4635IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4636 uint32_t fAccess)
4637{
4638 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4639 Assert(pVmcs);
4640 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4641 Assert(pvData);
4642 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4643 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4644 || (fAccess & IEM_ACCESS_INSTRUCTION));
4645
4646 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4647 if (fIntercept)
4648 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4649
4650 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4651 {
4652 /*
4653 * A write access to the APIC-access page that is virtualized (rather than
4654 * causing a VM-exit) writes data to the virtual-APIC page.
4655 */
4656 uint32_t const u32Data = *(uint32_t *)pvData;
4657 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4658
4659 /*
4660 * Record the currently updated APIC offset, as we need this later for figuring
4661 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4662 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4663 *
4664 * After completion of the current operation, we need to perform TPR virtualization,
4665 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4666 *
4667 * The current operation may be a REP-prefixed string instruction, execution of any
4668 * other instruction, or delivery of an event through the IDT.
4669 *
4670 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4671 * performed now but later after completion of the current operation.
4672 *
4673 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4674 */
4675 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4676 }
4677 else
4678 {
4679 /*
4680 * A read access from the APIC-access page that is virtualized (rather than
4681 * causing a VM-exit) returns data from the virtual-APIC page.
4682 *
4683 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4684 */
4685 Assert(cbAccess <= 4);
4686 Assert(offAccess < XAPIC_OFF_END + 4);
4687 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4688
4689 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4690 u32Data &= s_auAccessSizeMasks[cbAccess];
4691 *(uint32_t *)pvData = u32Data;
4692 }
4693
4694 return VINF_VMX_MODIFIES_BEHAVIOR;
4695}
4696
4697
4698/**
4699 * Virtualizes an MSR-based APIC read access.
4700 *
4701 * @returns VBox strict status code.
4702 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4703 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4704 * handled by the x2APIC device.
4705 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4706 * not within the range of valid MSRs, caller must raise \#GP(0).
4707 * @param pVCpu The cross context virtual CPU structure.
4708 * @param idMsr The x2APIC MSR being read.
4709 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4710 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4711 */
4712IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4713{
4714 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4715 Assert(pVmcs);
4716 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4717 Assert(pu64Value);
4718
4719 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4720 {
4721 /*
4722 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4723 * what the end of the valid x2APIC MSR range is. Hence the use of different
4724 * macros here.
4725 *
4726 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4727 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4728 */
4729 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4730 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4731 {
4732 uint16_t const offReg = (idMsr & 0xff) << 4;
4733 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4734 *pu64Value = u64Value;
4735 return VINF_VMX_MODIFIES_BEHAVIOR;
4736 }
4737 return VERR_OUT_OF_RANGE;
4738 }
4739
4740 if (idMsr == MSR_IA32_X2APIC_TPR)
4741 {
4742 uint16_t const offReg = (idMsr & 0xff) << 4;
4743 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4744 *pu64Value = u64Value;
4745 return VINF_VMX_MODIFIES_BEHAVIOR;
4746 }
4747
4748 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4749}
4750
4751
4752/**
4753 * Virtualizes an MSR-based APIC write access.
4754 *
4755 * @returns VBox strict status code.
4756 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4757 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4758 * not within the range of valid MSRs, caller must raise \#GP(0).
4759 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4760 *
4761 * @param pVCpu The cross context virtual CPU structure.
4762 * @param idMsr The x2APIC MSR being written.
4763 * @param u64Value The value of the x2APIC MSR being written.
4764 */
4765IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4766{
4767 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4768 Assert(pVmcs);
4769
4770 /*
4771 * Check if the access is to be virtualized.
4772 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4773 */
4774 if ( idMsr == MSR_IA32_X2APIC_TPR
4775 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4776 && ( idMsr == MSR_IA32_X2APIC_EOI
4777 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4778 {
4779 /* Validate the MSR write depending on the register. */
4780 switch (idMsr)
4781 {
4782 case MSR_IA32_X2APIC_TPR:
4783 case MSR_IA32_X2APIC_SELF_IPI:
4784 {
4785 if (u64Value & UINT64_C(0xffffffffffffff00))
4786 return VERR_OUT_OF_RANGE;
4787 break;
4788 }
4789 case MSR_IA32_X2APIC_EOI:
4790 {
4791 if (u64Value != 0)
4792 return VERR_OUT_OF_RANGE;
4793 break;
4794 }
4795 }
4796
4797 /* Write the MSR to the virtual-APIC page. */
4798 uint16_t const offReg = (idMsr & 0xff) << 4;
4799 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4800
4801 /*
4802 * Record the currently updated APIC offset, as we need this later for figuring
4803 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4804 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4805 */
4806 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4807
4808 return VINF_VMX_MODIFIES_BEHAVIOR;
4809 }
4810
4811 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4812}
4813
4814
4815/**
4816 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4817 *
4818 * @returns VBox status code.
4819 * @retval VINF_SUCCES when the highest set bit is found.
4820 * @retval VERR_NOT_FOUND when no bit is set.
4821 *
4822 * @param pVCpu The cross context virtual CPU structure.
4823 * @param offReg The offset of the APIC 256-bit sparse register.
4824 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4825 * set in the register. Only valid when VINF_SUCCESS is
4826 * returned.
4827 *
4828 * @remarks The format of the 256-bit sparse register here mirrors that found in
4829 * real APIC hardware.
4830 */
4831static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4832{
4833 Assert(offReg < XAPIC_OFF_END + 4);
4834 Assert(pidxHighestBit);
4835
4836 /*
4837 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4838 * However, in each fragment only the first 4 bytes are used.
4839 */
4840 uint8_t const cFrags = 8;
4841 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4842 {
4843 uint16_t const offFrag = iFrag * 16;
4844 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4845 if (!u32Frag)
4846 continue;
4847
4848 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4849 Assert(idxHighestBit > 0);
4850 --idxHighestBit;
4851 Assert(idxHighestBit <= UINT8_MAX);
4852 *pidxHighestBit = idxHighestBit;
4853 return VINF_SUCCESS;
4854 }
4855 return VERR_NOT_FOUND;
4856}
4857
4858
4859/**
4860 * Evaluates pending virtual interrupts.
4861 *
4862 * @param pVCpu The cross context virtual CPU structure.
4863 */
4864IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4865{
4866 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4867 Assert(pVmcs);
4868 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4869
4870 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4871 {
4872 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4873 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4874
4875 if ((uRvi >> 4) > (uPpr >> 4))
4876 {
4877 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4878 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4879 }
4880 else
4881 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4882 }
4883}
4884
4885
4886/**
4887 * Performs PPR virtualization.
4888 *
4889 * @returns VBox strict status code.
4890 * @param pVCpu The cross context virtual CPU structure.
4891 */
4892IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4893{
4894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4895 Assert(pVmcs);
4896 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4897 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4898
4899 /*
4900 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4901 * or EOI-virtualization.
4902 *
4903 * See Intel spec. 29.1.3 "PPR Virtualization".
4904 */
4905 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4906 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4907
4908 uint32_t uPpr;
4909 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4910 uPpr = uTpr & 0xff;
4911 else
4912 uPpr = uSvi & 0xf0;
4913
4914 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4915 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4916}
4917
4918
4919/**
4920 * Performs VMX TPR virtualization.
4921 *
4922 * @returns VBox strict status code.
4923 * @param pVCpu The cross context virtual CPU structure.
4924 */
4925IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4926{
4927 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4928 Assert(pVmcs);
4929 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4930
4931 /*
4932 * We should have already performed the virtual-APIC write to the TPR offset
4933 * in the virtual-APIC page. We now perform TPR virtualization.
4934 *
4935 * See Intel spec. 29.1.2 "TPR Virtualization".
4936 */
4937 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4938 {
4939 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4940 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4941
4942 /*
4943 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4944 * See Intel spec. 29.1.2 "TPR Virtualization".
4945 */
4946 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4947 {
4948 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4949 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4950 }
4951 }
4952 else
4953 {
4954 iemVmxPprVirtualization(pVCpu);
4955 iemVmxEvalPendingVirtIntrs(pVCpu);
4956 }
4957
4958 return VINF_SUCCESS;
4959}
4960
4961
4962/**
4963 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4964 * not.
4965 *
4966 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4967 * @param pVCpu The cross context virtual CPU structure.
4968 * @param uVector The interrupt that was acknowledged using an EOI.
4969 */
4970IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4971{
4972 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4973 Assert(pVmcs);
4974 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4975
4976 if (uVector < 64)
4977 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4978 if (uVector < 128)
4979 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4980 if (uVector < 192)
4981 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4982 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4983}
4984
4985
4986/**
4987 * Performs EOI virtualization.
4988 *
4989 * @returns VBox strict status code.
4990 * @param pVCpu The cross context virtual CPU structure.
4991 */
4992IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4993{
4994 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4995 Assert(pVmcs);
4996 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4997
4998 /*
4999 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
5000 * and get the next guest-interrupt that's in-service (if any).
5001 *
5002 * See Intel spec. 29.1.4 "EOI Virtualization".
5003 */
5004 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5005 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5006 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5007
5008 uint8_t uVector = uSvi;
5009 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
5010
5011 uVector = 0;
5012 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5013
5014 if (uVector)
5015 Log2(("eoi_virt: next interrupt %#x\n", uVector));
5016 else
5017 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5018
5019 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5020 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5021
5022 iemVmxPprVirtualization(pVCpu);
5023 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5024 return iemVmxVmexitVirtEoi(pVCpu, uVector);
5025 iemVmxEvalPendingVirtIntrs(pVCpu);
5026 return VINF_SUCCESS;
5027}
5028
5029
5030/**
5031 * Performs self-IPI virtualization.
5032 *
5033 * @returns VBox strict status code.
5034 * @param pVCpu The cross context virtual CPU structure.
5035 */
5036IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5037{
5038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5039 Assert(pVmcs);
5040 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5041
5042 /*
5043 * We should have already performed the virtual-APIC write to the self-IPI offset
5044 * in the virtual-APIC page. We now perform self-IPI virtualization.
5045 *
5046 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5047 */
5048 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5049 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5050 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
5051 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5052 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5053 if (uVector > uRvi)
5054 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5055 iemVmxEvalPendingVirtIntrs(pVCpu);
5056 return VINF_SUCCESS;
5057}
5058
5059
5060/**
5061 * Performs VMX APIC-write emulation.
5062 *
5063 * @returns VBox strict status code.
5064 * @param pVCpu The cross context virtual CPU structure.
5065 */
5066IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5067{
5068 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5069 Assert(pVmcs);
5070
5071 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5072 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5073
5074 /*
5075 * Perform APIC-write emulation based on the virtual-APIC register written.
5076 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5077 */
5078 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5079 VBOXSTRICTRC rcStrict;
5080 switch (offApicWrite)
5081 {
5082 case XAPIC_OFF_TPR:
5083 {
5084 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5085 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5086 uTpr &= UINT32_C(0x000000ff);
5087 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5088 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5089 rcStrict = iemVmxTprVirtualization(pVCpu);
5090 break;
5091 }
5092
5093 case XAPIC_OFF_EOI:
5094 {
5095 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5096 {
5097 /* Clear VEOI and perform EOI virtualization. */
5098 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5099 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5100 rcStrict = iemVmxEoiVirtualization(pVCpu);
5101 }
5102 else
5103 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5104 break;
5105 }
5106
5107 case XAPIC_OFF_ICR_LO:
5108 {
5109 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5110 {
5111 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5112 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5113 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5114 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5115 if ( !(uIcrLo & fIcrLoMb0)
5116 && (uIcrLo & fIcrLoMb1))
5117 {
5118 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5119 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5120 }
5121 else
5122 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5123 }
5124 else
5125 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5126 break;
5127 }
5128
5129 case XAPIC_OFF_ICR_HI:
5130 {
5131 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5132 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5133 uIcrHi &= UINT32_C(0xff000000);
5134 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5135 rcStrict = VINF_SUCCESS;
5136 break;
5137 }
5138
5139 default:
5140 {
5141 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5142 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5143 break;
5144 }
5145 }
5146
5147 return rcStrict;
5148}
5149
5150
5151/**
5152 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5153 *
5154 * @param pVCpu The cross context virtual CPU structure.
5155 * @param pszInstr The VMX instruction name (for logging purposes).
5156 */
5157IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5158{
5159 /*
5160 * Guest Control Registers, Debug Registers, and MSRs.
5161 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5162 */
5163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5164 const char *const pszFailure = "VM-exit";
5165 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5166
5167 /* CR0 reserved bits. */
5168 {
5169 /* CR0 MB1 bits. */
5170 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5171 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5172 if (fUnrestrictedGuest)
5173 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5174 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5178
5179 /* CR0 MBZ bits. */
5180 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5181 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5182 { /* likely */ }
5183 else
5184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5185
5186 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5187 if ( !fUnrestrictedGuest
5188 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5189 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5191 }
5192
5193 /* CR4 reserved bits. */
5194 {
5195 /* CR4 MB1 bits. */
5196 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5197 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5201
5202 /* CR4 MBZ bits. */
5203 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5204 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5208 }
5209
5210 /* DEBUGCTL MSR. */
5211 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5212 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5216
5217 /* 64-bit CPU checks. */
5218 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5219 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5220 {
5221 if (fGstInLongMode)
5222 {
5223 /* PAE must be set. */
5224 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5225 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5229 }
5230 else
5231 {
5232 /* PCIDE should not be set. */
5233 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5237 }
5238
5239 /* CR3. */
5240 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5241 { /* likely */ }
5242 else
5243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5244
5245 /* DR7. */
5246 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5247 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5251
5252 /* SYSENTER ESP and SYSENTER EIP. */
5253 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5254 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5258 }
5259
5260 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5261 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5262
5263 /* PAT MSR. */
5264 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5265 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5266 { /* likely */ }
5267 else
5268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5269
5270 /* EFER MSR. */
5271 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5272 {
5273 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5274 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5275 { /* likely */ }
5276 else
5277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5278
5279 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5280 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5281 if ( fGstLma == fGstInLongMode
5282 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5283 || fGstLma == fGstLme))
5284 { /* likely */ }
5285 else
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5287 }
5288
5289 /* We don't support IA32_BNDCFGS MSR yet. */
5290 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5291
5292 NOREF(pszInstr);
5293 NOREF(pszFailure);
5294 return VINF_SUCCESS;
5295}
5296
5297
5298/**
5299 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5300 *
5301 * @param pVCpu The cross context virtual CPU structure.
5302 * @param pszInstr The VMX instruction name (for logging purposes).
5303 */
5304IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5305{
5306 /*
5307 * Segment registers.
5308 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5309 */
5310 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5311 const char *const pszFailure = "VM-exit";
5312 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5313 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5314 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5315
5316 /* Selectors. */
5317 if ( !fGstInV86Mode
5318 && !fUnrestrictedGuest
5319 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5321
5322 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5323 {
5324 CPUMSELREG SelReg;
5325 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5326 if (RT_LIKELY(rc == VINF_SUCCESS))
5327 { /* likely */ }
5328 else
5329 return rc;
5330
5331 /*
5332 * Virtual-8086 mode checks.
5333 */
5334 if (fGstInV86Mode)
5335 {
5336 /* Base address. */
5337 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5338 { /* likely */ }
5339 else
5340 {
5341 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5343 }
5344
5345 /* Limit. */
5346 if (SelReg.u32Limit == 0xffff)
5347 { /* likely */ }
5348 else
5349 {
5350 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5352 }
5353
5354 /* Attribute. */
5355 if (SelReg.Attr.u == 0xf3)
5356 { /* likely */ }
5357 else
5358 {
5359 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5361 }
5362
5363 /* We're done; move to checking the next segment. */
5364 continue;
5365 }
5366
5367 /* Checks done by 64-bit CPUs. */
5368 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5369 {
5370 /* Base address. */
5371 if ( iSegReg == X86_SREG_FS
5372 || iSegReg == X86_SREG_GS)
5373 {
5374 if (X86_IS_CANONICAL(SelReg.u64Base))
5375 { /* likely */ }
5376 else
5377 {
5378 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5380 }
5381 }
5382 else if (iSegReg == X86_SREG_CS)
5383 {
5384 if (!RT_HI_U32(SelReg.u64Base))
5385 { /* likely */ }
5386 else
5387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5388 }
5389 else
5390 {
5391 if ( SelReg.Attr.n.u1Unusable
5392 || !RT_HI_U32(SelReg.u64Base))
5393 { /* likely */ }
5394 else
5395 {
5396 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5397 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5398 }
5399 }
5400 }
5401
5402 /*
5403 * Checks outside Virtual-8086 mode.
5404 */
5405 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5406 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5407 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5408 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5409 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5410 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5411 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5412 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5413
5414 /* Code or usable segment. */
5415 if ( iSegReg == X86_SREG_CS
5416 || fUsable)
5417 {
5418 /* Reserved bits (bits 31:17 and bits 11:8). */
5419 if (!(SelReg.Attr.u & 0xfffe0f00))
5420 { /* likely */ }
5421 else
5422 {
5423 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5424 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5425 }
5426
5427 /* Descriptor type. */
5428 if (fCodeDataSeg)
5429 { /* likely */ }
5430 else
5431 {
5432 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5434 }
5435
5436 /* Present. */
5437 if (fPresent)
5438 { /* likely */ }
5439 else
5440 {
5441 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5443 }
5444
5445 /* Granularity. */
5446 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5447 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5448 { /* likely */ }
5449 else
5450 {
5451 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5453 }
5454 }
5455
5456 if (iSegReg == X86_SREG_CS)
5457 {
5458 /* Segment Type and DPL. */
5459 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5460 && fUnrestrictedGuest)
5461 {
5462 if (uDpl == 0)
5463 { /* likely */ }
5464 else
5465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5466 }
5467 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5468 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5469 {
5470 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5471 if (uDpl == AttrSs.n.u2Dpl)
5472 { /* likely */ }
5473 else
5474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5475 }
5476 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5477 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5478 {
5479 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5480 if (uDpl <= AttrSs.n.u2Dpl)
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5484 }
5485 else
5486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5487
5488 /* Def/Big. */
5489 if ( fGstInLongMode
5490 && fSegLong)
5491 {
5492 if (uDefBig == 0)
5493 { /* likely */ }
5494 else
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5496 }
5497 }
5498 else if (iSegReg == X86_SREG_SS)
5499 {
5500 /* Segment Type. */
5501 if ( !fUsable
5502 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5503 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5504 { /* likely */ }
5505 else
5506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5507
5508 /* DPL. */
5509 if (!fUnrestrictedGuest)
5510 {
5511 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5512 { /* likely */ }
5513 else
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5515 }
5516 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5517 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5518 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5519 {
5520 if (uDpl == 0)
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5524 }
5525 }
5526 else
5527 {
5528 /* DS, ES, FS, GS. */
5529 if (fUsable)
5530 {
5531 /* Segment type. */
5532 if (uSegType & X86_SEL_TYPE_ACCESSED)
5533 { /* likely */ }
5534 else
5535 {
5536 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5538 }
5539
5540 if ( !(uSegType & X86_SEL_TYPE_CODE)
5541 || (uSegType & X86_SEL_TYPE_READ))
5542 { /* likely */ }
5543 else
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5545
5546 /* DPL. */
5547 if ( !fUnrestrictedGuest
5548 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5549 {
5550 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5551 { /* likely */ }
5552 else
5553 {
5554 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5556 }
5557 }
5558 }
5559 }
5560 }
5561
5562 /*
5563 * LDTR.
5564 */
5565 {
5566 CPUMSELREG Ldtr;
5567 Ldtr.Sel = pVmcs->GuestLdtr;
5568 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5569 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5570 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5571
5572 if (!Ldtr.Attr.n.u1Unusable)
5573 {
5574 /* Selector. */
5575 if (!(Ldtr.Sel & X86_SEL_LDT))
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5579
5580 /* Base. */
5581 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5582 {
5583 if (X86_IS_CANONICAL(Ldtr.u64Base))
5584 { /* likely */ }
5585 else
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5587 }
5588
5589 /* Attributes. */
5590 /* Reserved bits (bits 31:17 and bits 11:8). */
5591 if (!(Ldtr.Attr.u & 0xfffe0f00))
5592 { /* likely */ }
5593 else
5594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5595
5596 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5597 { /* likely */ }
5598 else
5599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5600
5601 if (!Ldtr.Attr.n.u1DescType)
5602 { /* likely */ }
5603 else
5604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5605
5606 if (Ldtr.Attr.n.u1Present)
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5610
5611 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5612 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5613 { /* likely */ }
5614 else
5615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5616 }
5617 }
5618
5619 /*
5620 * TR.
5621 */
5622 {
5623 CPUMSELREG Tr;
5624 Tr.Sel = pVmcs->GuestTr;
5625 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5626 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5627 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5628
5629 /* Selector. */
5630 if (!(Tr.Sel & X86_SEL_LDT))
5631 { /* likely */ }
5632 else
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5634
5635 /* Base. */
5636 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5637 {
5638 if (X86_IS_CANONICAL(Tr.u64Base))
5639 { /* likely */ }
5640 else
5641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5642 }
5643
5644 /* Attributes. */
5645 /* Reserved bits (bits 31:17 and bits 11:8). */
5646 if (!(Tr.Attr.u & 0xfffe0f00))
5647 { /* likely */ }
5648 else
5649 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5650
5651 if (!Tr.Attr.n.u1Unusable)
5652 { /* likely */ }
5653 else
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5655
5656 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5657 || ( !fGstInLongMode
5658 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5659 { /* likely */ }
5660 else
5661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5662
5663 if (!Tr.Attr.n.u1DescType)
5664 { /* likely */ }
5665 else
5666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5667
5668 if (Tr.Attr.n.u1Present)
5669 { /* likely */ }
5670 else
5671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5672
5673 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5674 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5675 { /* likely */ }
5676 else
5677 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5678 }
5679
5680 NOREF(pszInstr);
5681 NOREF(pszFailure);
5682 return VINF_SUCCESS;
5683}
5684
5685
5686/**
5687 * Checks guest GDTR and IDTR as part of VM-entry.
5688 *
5689 * @param pVCpu The cross context virtual CPU structure.
5690 * @param pszInstr The VMX instruction name (for logging purposes).
5691 */
5692IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5693{
5694 /*
5695 * GDTR and IDTR.
5696 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5697 */
5698 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5699 const char *const pszFailure = "VM-exit";
5700
5701 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5702 {
5703 /* Base. */
5704 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5705 { /* likely */ }
5706 else
5707 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5708
5709 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5713 }
5714
5715 /* Limit. */
5716 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5717 { /* likely */ }
5718 else
5719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5720
5721 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5722 { /* likely */ }
5723 else
5724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5725
5726 NOREF(pszInstr);
5727 NOREF(pszFailure);
5728 return VINF_SUCCESS;
5729}
5730
5731
5732/**
5733 * Checks guest RIP and RFLAGS as part of VM-entry.
5734 *
5735 * @param pVCpu The cross context virtual CPU structure.
5736 * @param pszInstr The VMX instruction name (for logging purposes).
5737 */
5738IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5739{
5740 /*
5741 * RIP and RFLAGS.
5742 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5743 */
5744 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5745 const char *const pszFailure = "VM-exit";
5746 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5747
5748 /* RIP. */
5749 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5750 {
5751 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5752 if ( !fGstInLongMode
5753 || !AttrCs.n.u1Long)
5754 {
5755 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5756 { /* likely */ }
5757 else
5758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5759 }
5760
5761 if ( fGstInLongMode
5762 && AttrCs.n.u1Long)
5763 {
5764 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5765 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5766 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5767 { /* likely */ }
5768 else
5769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5770 }
5771 }
5772
5773 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5774 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5775 : pVmcs->u64GuestRFlags.s.Lo;
5776 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5777 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5778 { /* likely */ }
5779 else
5780 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5781
5782 if ( fGstInLongMode
5783 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5784 {
5785 if (!(uGuestRFlags & X86_EFL_VM))
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5789 }
5790
5791 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5792 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5793 {
5794 if (uGuestRFlags & X86_EFL_IF)
5795 { /* likely */ }
5796 else
5797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5798 }
5799
5800 NOREF(pszInstr);
5801 NOREF(pszFailure);
5802 return VINF_SUCCESS;
5803}
5804
5805
5806/**
5807 * Checks guest non-register state as part of VM-entry.
5808 *
5809 * @param pVCpu The cross context virtual CPU structure.
5810 * @param pszInstr The VMX instruction name (for logging purposes).
5811 */
5812IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5813{
5814 /*
5815 * Guest non-register state.
5816 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5817 */
5818 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5819 const char *const pszFailure = "VM-exit";
5820
5821 /*
5822 * Activity state.
5823 */
5824 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5825 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5826 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5830
5831 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5832 if ( !AttrSs.n.u2Dpl
5833 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5834 { /* likely */ }
5835 else
5836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5837
5838 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5839 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5840 {
5841 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5845 }
5846
5847 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5848 {
5849 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5850 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5851 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5852 switch (pVmcs->u32GuestActivityState)
5853 {
5854 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5855 {
5856 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5857 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5858 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5859 && ( uVector == X86_XCPT_DB
5860 || uVector == X86_XCPT_MC))
5861 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5862 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5863 { /* likely */ }
5864 else
5865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5866 break;
5867 }
5868
5869 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5870 {
5871 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5872 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5873 && uVector == X86_XCPT_MC))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5877 break;
5878 }
5879
5880 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5881 default:
5882 break;
5883 }
5884 }
5885
5886 /*
5887 * Interruptibility state.
5888 */
5889 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5890 { /* likely */ }
5891 else
5892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5893
5894 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5895 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5896 { /* likely */ }
5897 else
5898 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5899
5900 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5901 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5902 { /* likely */ }
5903 else
5904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5905
5906 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5907 {
5908 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5909 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5910 {
5911 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5912 { /* likely */ }
5913 else
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5915 }
5916 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5917 {
5918 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5919 { /* likely */ }
5920 else
5921 {
5922 /*
5923 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5924 * We update the VM-exit qualification only when blocking-by-STI is set
5925 * without blocking-by-MovSS being set. Although in practise it does not
5926 * make much difference since the order of checks are implementation defined.
5927 */
5928 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5929 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5931 }
5932
5933 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5934 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5935 { /* likely */ }
5936 else
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5938 }
5939 }
5940
5941 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5942 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5943 { /* likely */ }
5944 else
5945 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5946
5947 /* We don't support SGX yet. So enclave-interruption must not be set. */
5948 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5949 { /* likely */ }
5950 else
5951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5952
5953 /*
5954 * Pending debug exceptions.
5955 */
5956 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5957 ? pVmcs->u64GuestPendingDbgXcpt.u
5958 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5959 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5963
5964 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5965 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5966 {
5967 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5968 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5969 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5971
5972 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5973 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5974 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5976 }
5977
5978 /* We don't support RTM (Real-time Transactional Memory) yet. */
5979 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5980 { /* likely */ }
5981 else
5982 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5983
5984 /*
5985 * VMCS link pointer.
5986 */
5987 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5988 {
5989 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5990 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5991 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5992 { /* likely */ }
5993 else
5994 {
5995 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5997 }
5998
5999 /* Validate the address. */
6000 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
6001 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6002 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
6003 { /* likely */ }
6004 else
6005 {
6006 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6008 }
6009
6010 /* Read the VMCS-link pointer from guest memory. */
6011 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6012 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6013 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
6014 if (RT_SUCCESS(rc))
6015 { /* likely */ }
6016 else
6017 {
6018 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6019 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6020 }
6021
6022 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6023 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6024 { /* likely */ }
6025 else
6026 {
6027 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6029 }
6030
6031 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6032 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6033 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6034 { /* likely */ }
6035 else
6036 {
6037 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6039 }
6040
6041 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6042 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6043 }
6044
6045 NOREF(pszInstr);
6046 NOREF(pszFailure);
6047 return VINF_SUCCESS;
6048}
6049
6050
6051/**
6052 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6053 * VM-entry.
6054 *
6055 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6056 * @param pVCpu The cross context virtual CPU structure.
6057 * @param pszInstr The VMX instruction name (for logging purposes).
6058 * @param pVmcs Pointer to the virtual VMCS.
6059 */
6060IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6061{
6062 /*
6063 * Check PDPTEs.
6064 * See Intel spec. 4.4.1 "PDPTE Registers".
6065 */
6066 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6067 const char *const pszFailure = "VM-exit";
6068
6069 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6070 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6071 if (RT_SUCCESS(rc))
6072 {
6073 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6074 {
6075 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6076 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6077 { /* likely */ }
6078 else
6079 {
6080 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6081 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6083 }
6084 }
6085 }
6086 else
6087 {
6088 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6090 }
6091
6092 NOREF(pszFailure);
6093 NOREF(pszInstr);
6094 return rc;
6095}
6096
6097
6098/**
6099 * Checks guest PDPTEs as part of VM-entry.
6100 *
6101 * @param pVCpu The cross context virtual CPU structure.
6102 * @param pszInstr The VMX instruction name (for logging purposes).
6103 */
6104IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6105{
6106 /*
6107 * Guest PDPTEs.
6108 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6109 */
6110 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6111 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6112
6113 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6114 int rc;
6115 if ( !fGstInLongMode
6116 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6117 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6118 {
6119 /*
6120 * We don't support nested-paging for nested-guests yet.
6121 *
6122 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6123 * rather we need to check the PDPTEs referenced by the guest CR3.
6124 */
6125 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6126 }
6127 else
6128 rc = VINF_SUCCESS;
6129 return rc;
6130}
6131
6132
6133/**
6134 * Checks guest-state as part of VM-entry.
6135 *
6136 * @returns VBox status code.
6137 * @param pVCpu The cross context virtual CPU structure.
6138 * @param pszInstr The VMX instruction name (for logging purposes).
6139 */
6140IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6141{
6142 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6143 if (RT_SUCCESS(rc))
6144 {
6145 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6146 if (RT_SUCCESS(rc))
6147 {
6148 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6149 if (RT_SUCCESS(rc))
6150 {
6151 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6152 if (RT_SUCCESS(rc))
6153 {
6154 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6155 if (RT_SUCCESS(rc))
6156 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6157 }
6158 }
6159 }
6160 }
6161 return rc;
6162}
6163
6164
6165/**
6166 * Checks host-state as part of VM-entry.
6167 *
6168 * @returns VBox status code.
6169 * @param pVCpu The cross context virtual CPU structure.
6170 * @param pszInstr The VMX instruction name (for logging purposes).
6171 */
6172IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6173{
6174 /*
6175 * Host Control Registers and MSRs.
6176 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6177 */
6178 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6179 const char * const pszFailure = "VMFail";
6180
6181 /* CR0 reserved bits. */
6182 {
6183 /* CR0 MB1 bits. */
6184 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6185 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6186 { /* likely */ }
6187 else
6188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6189
6190 /* CR0 MBZ bits. */
6191 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6192 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6193 { /* likely */ }
6194 else
6195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6196 }
6197
6198 /* CR4 reserved bits. */
6199 {
6200 /* CR4 MB1 bits. */
6201 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6202 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6203 { /* likely */ }
6204 else
6205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6206
6207 /* CR4 MBZ bits. */
6208 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6209 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6210 { /* likely */ }
6211 else
6212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6213 }
6214
6215 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6216 {
6217 /* CR3 reserved bits. */
6218 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6222
6223 /* SYSENTER ESP and SYSENTER EIP. */
6224 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6225 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6226 { /* likely */ }
6227 else
6228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6229 }
6230
6231 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6232 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6233
6234 /* PAT MSR. */
6235 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6236 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6237 { /* likely */ }
6238 else
6239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6240
6241 /* EFER MSR. */
6242 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6243 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6244 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6245 { /* likely */ }
6246 else
6247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6248
6249 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6250 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6251 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6252 if ( fHostInLongMode == fHostLma
6253 && fHostInLongMode == fHostLme)
6254 { /* likely */ }
6255 else
6256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6257
6258 /*
6259 * Host Segment and Descriptor-Table Registers.
6260 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6261 */
6262 /* Selector RPL and TI. */
6263 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6264 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6265 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6266 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6267 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6268 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6269 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6273
6274 /* CS and TR selectors cannot be 0. */
6275 if ( pVmcs->HostCs
6276 && pVmcs->HostTr)
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6280
6281 /* SS cannot be 0 if 32-bit host. */
6282 if ( fHostInLongMode
6283 || pVmcs->HostSs)
6284 { /* likely */ }
6285 else
6286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6287
6288 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6289 {
6290 /* FS, GS, GDTR, IDTR, TR base address. */
6291 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6292 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6293 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6294 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6295 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6296 { /* likely */ }
6297 else
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6299 }
6300
6301 /*
6302 * Host address-space size for 64-bit CPUs.
6303 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6304 */
6305 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6306 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6307 {
6308 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6309
6310 /* Logical processor in IA-32e mode. */
6311 if (fCpuInLongMode)
6312 {
6313 if (fHostInLongMode)
6314 {
6315 /* PAE must be set. */
6316 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6317 { /* likely */ }
6318 else
6319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6320
6321 /* RIP must be canonical. */
6322 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6326 }
6327 else
6328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6329 }
6330 else
6331 {
6332 /* Logical processor is outside IA-32e mode. */
6333 if ( !fGstInLongMode
6334 && !fHostInLongMode)
6335 {
6336 /* PCIDE should not be set. */
6337 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6338 { /* likely */ }
6339 else
6340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6341
6342 /* The high 32-bits of RIP MBZ. */
6343 if (!pVmcs->u64HostRip.s.Hi)
6344 { /* likely */ }
6345 else
6346 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6347 }
6348 else
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6350 }
6351 }
6352 else
6353 {
6354 /* Host address-space size for 32-bit CPUs. */
6355 if ( !fGstInLongMode
6356 && !fHostInLongMode)
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6360 }
6361
6362 NOREF(pszInstr);
6363 NOREF(pszFailure);
6364 return VINF_SUCCESS;
6365}
6366
6367
6368/**
6369 * Checks VM-entry controls fields as part of VM-entry.
6370 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6371 *
6372 * @returns VBox status code.
6373 * @param pVCpu The cross context virtual CPU structure.
6374 * @param pszInstr The VMX instruction name (for logging purposes).
6375 */
6376IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6377{
6378 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6379 const char * const pszFailure = "VMFail";
6380
6381 /* VM-entry controls. */
6382 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6383 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6384 { /* likely */ }
6385 else
6386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6387
6388 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6389 { /* likely */ }
6390 else
6391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6392
6393 /* Event injection. */
6394 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6395 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6396 {
6397 /* Type and vector. */
6398 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6399 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6400 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6401 if ( !uRsvd
6402 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6403 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6404 { /* likely */ }
6405 else
6406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6407
6408 /* Exception error code. */
6409 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6410 {
6411 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6412 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6413 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6414 { /* likely */ }
6415 else
6416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6417
6418 /* Exceptions that provide an error code. */
6419 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6420 && ( uVector == X86_XCPT_DF
6421 || uVector == X86_XCPT_TS
6422 || uVector == X86_XCPT_NP
6423 || uVector == X86_XCPT_SS
6424 || uVector == X86_XCPT_GP
6425 || uVector == X86_XCPT_PF
6426 || uVector == X86_XCPT_AC))
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6430
6431 /* Exception error-code reserved bits. */
6432 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6433 { /* likely */ }
6434 else
6435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6436
6437 /* Injecting a software interrupt, software exception or privileged software exception. */
6438 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6439 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6440 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6441 {
6442 /* Instruction length must be in the range 0-15. */
6443 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6444 { /* likely */ }
6445 else
6446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6447
6448 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6449 if ( pVmcs->u32EntryInstrLen == 0
6450 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6452 }
6453 }
6454 }
6455
6456 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6457 if (pVmcs->u32EntryMsrLoadCount)
6458 {
6459 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6460 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6461 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6462 { /* likely */ }
6463 else
6464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6465 }
6466
6467 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6468 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6469
6470 NOREF(pszInstr);
6471 NOREF(pszFailure);
6472 return VINF_SUCCESS;
6473}
6474
6475
6476/**
6477 * Checks VM-exit controls fields as part of VM-entry.
6478 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6479 *
6480 * @returns VBox status code.
6481 * @param pVCpu The cross context virtual CPU structure.
6482 * @param pszInstr The VMX instruction name (for logging purposes).
6483 */
6484IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6485{
6486 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6487 const char * const pszFailure = "VMFail";
6488
6489 /* VM-exit controls. */
6490 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6491 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6492 { /* likely */ }
6493 else
6494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6495
6496 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6497 { /* likely */ }
6498 else
6499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6500
6501 /* Save preemption timer without activating it. */
6502 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6503 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6507
6508 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6509 if (pVmcs->u32ExitMsrStoreCount)
6510 {
6511 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6512 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6513 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6514 { /* likely */ }
6515 else
6516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6517 }
6518
6519 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6520 if (pVmcs->u32ExitMsrLoadCount)
6521 {
6522 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6523 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6524 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6525 { /* likely */ }
6526 else
6527 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6528 }
6529
6530 NOREF(pszInstr);
6531 NOREF(pszFailure);
6532 return VINF_SUCCESS;
6533}
6534
6535
6536/**
6537 * Checks VM-execution controls fields as part of VM-entry.
6538 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6539 *
6540 * @returns VBox status code.
6541 * @param pVCpu The cross context virtual CPU structure.
6542 * @param pszInstr The VMX instruction name (for logging purposes).
6543 *
6544 * @remarks This may update secondary-processor based VM-execution control fields
6545 * in the current VMCS if necessary.
6546 */
6547IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6548{
6549 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6550 const char * const pszFailure = "VMFail";
6551
6552 /* Pin-based VM-execution controls. */
6553 {
6554 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6555 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6556 { /* likely */ }
6557 else
6558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6559
6560 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6561 { /* likely */ }
6562 else
6563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6564 }
6565
6566 /* Processor-based VM-execution controls. */
6567 {
6568 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6569 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6570 { /* likely */ }
6571 else
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6573
6574 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6575 { /* likely */ }
6576 else
6577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6578 }
6579
6580 /* Secondary processor-based VM-execution controls. */
6581 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6582 {
6583 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6584 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6585 { /* likely */ }
6586 else
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6588
6589 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6590 { /* likely */ }
6591 else
6592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6593 }
6594 else
6595 Assert(!pVmcs->u32ProcCtls2);
6596
6597 /* CR3-target count. */
6598 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6599 { /* likely */ }
6600 else
6601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6602
6603 /* I/O bitmaps physical addresses. */
6604 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6605 {
6606 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6607 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6608 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6609 { /* likely */ }
6610 else
6611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6612
6613 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6614 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6615 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6619 }
6620
6621 /* MSR bitmap physical address. */
6622 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6623 {
6624 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6625 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6626 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6627 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6628 { /* likely */ }
6629 else
6630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6631
6632 /* Read the MSR bitmap. */
6633 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6634 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6635 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6636 if (RT_SUCCESS(rc))
6637 { /* likely */ }
6638 else
6639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6640 }
6641
6642 /* TPR shadow related controls. */
6643 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6644 {
6645 /* Virtual-APIC page physical address. */
6646 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6647 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6648 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6649 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6653
6654 /* Read the Virtual-APIC page. */
6655 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6656 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6657 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6658 if (RT_SUCCESS(rc))
6659 { /* likely */ }
6660 else
6661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6662
6663 /* TPR threshold without virtual-interrupt delivery. */
6664 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6665 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6667
6668 /* TPR threshold and VTPR. */
6669 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6670 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6671 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6672 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6673 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6675 }
6676 else
6677 {
6678 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6679 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6680 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6681 { /* likely */ }
6682 else
6683 {
6684 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6686 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6687 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6688 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6689 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6690 }
6691 }
6692
6693 /* NMI exiting and virtual-NMIs. */
6694 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6695 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6696 { /* likely */ }
6697 else
6698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6699
6700 /* Virtual-NMIs and NMI-window exiting. */
6701 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6702 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6703 { /* likely */ }
6704 else
6705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6706
6707 /* Virtualize APIC accesses. */
6708 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6709 {
6710 /* APIC-access physical address. */
6711 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6712 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6713 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6714 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6715 { /* likely */ }
6716 else
6717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6718
6719 /*
6720 * Disallow APIC-access page and virtual-APIC page from being the same address.
6721 * Note! This is not an Intel requirement, but one imposed by our implementation.
6722 */
6723 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6724 * redirecting accesses between the APIC-access page and the virtual-APIC
6725 * page. If any nested hypervisor requires this, we can implement it later. */
6726 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6727 {
6728 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6729 if (GCPhysVirtApic != GCPhysApicAccess)
6730 { /* likely */ }
6731 else
6732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6733 }
6734
6735 /*
6736 * Register the handler for the APIC-access page.
6737 *
6738 * We don't deregister the APIC-access page handler during the VM-exit as a different
6739 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6740 *
6741 * We leave the page registered until the first access that happens outside VMX non-root
6742 * mode. Guest software is allowed to access structures such as the APIC-access page
6743 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6744 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6745 *
6746 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6747 */
6748 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6749 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6750 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6751 if (RT_SUCCESS(rc))
6752 { /* likely */ }
6753 else
6754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6755 }
6756
6757 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6758 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6759 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6760 { /* likely */ }
6761 else
6762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6763
6764 /* Virtual-interrupt delivery requires external interrupt exiting. */
6765 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6766 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6767 { /* likely */ }
6768 else
6769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6770
6771 /* VPID. */
6772 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6773 || pVmcs->u16Vpid != 0)
6774 { /* likely */ }
6775 else
6776 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6777
6778 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6779 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6780 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6781 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6782 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6783 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6784 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6785
6786 /* VMCS shadowing. */
6787 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6788 {
6789 /* VMREAD-bitmap physical address. */
6790 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6791 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6792 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6793 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6794 { /* likely */ }
6795 else
6796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6797
6798 /* VMWRITE-bitmap physical address. */
6799 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6800 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6801 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6802 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6803 { /* likely */ }
6804 else
6805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6806
6807 /* Read the VMREAD-bitmap. */
6808 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6809 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6810 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6811 if (RT_SUCCESS(rc))
6812 { /* likely */ }
6813 else
6814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6815
6816 /* Read the VMWRITE-bitmap. */
6817 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6818 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6819 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6820 if (RT_SUCCESS(rc))
6821 { /* likely */ }
6822 else
6823 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6824 }
6825
6826 NOREF(pszInstr);
6827 NOREF(pszFailure);
6828 return VINF_SUCCESS;
6829}
6830
6831
6832/**
6833 * Loads the guest control registers, debug register and some MSRs as part of
6834 * VM-entry.
6835 *
6836 * @param pVCpu The cross context virtual CPU structure.
6837 */
6838IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6839{
6840 /*
6841 * Load guest control registers, debug registers and MSRs.
6842 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6843 */
6844 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6845
6846 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6847 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6848 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6849 CPUMSetGuestCR0(pVCpu, uGstCr0);
6850 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6851 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6852
6853 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6854 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6855
6856 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6857 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6858 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6859
6860 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6861 {
6862 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6863
6864 /* EFER MSR. */
6865 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6866 {
6867 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6868 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6869 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6870 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6871 if (fGstInLongMode)
6872 {
6873 /* If the nested-guest is in long mode, LMA and LME are both set. */
6874 Assert(fGstPaging);
6875 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6876 }
6877 else
6878 {
6879 /*
6880 * If the nested-guest is outside long mode:
6881 * - With paging: LMA is cleared, LME is cleared.
6882 * - Without paging: LMA is cleared, LME is left unmodified.
6883 */
6884 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6885 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6886 }
6887 }
6888 /* else: see below. */
6889 }
6890
6891 /* PAT MSR. */
6892 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6893 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6894
6895 /* EFER MSR. */
6896 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6897 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6898
6899 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6900 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6901
6902 /* We don't support IA32_BNDCFGS MSR yet. */
6903 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6904
6905 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6906}
6907
6908
6909/**
6910 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6911 *
6912 * @param pVCpu The cross context virtual CPU structure.
6913 */
6914IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6915{
6916 /*
6917 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6918 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6919 */
6920 /* CS, SS, ES, DS, FS, GS. */
6921 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6922 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6923 {
6924 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6925 CPUMSELREG VmcsSelReg;
6926 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6927 AssertRC(rc); NOREF(rc);
6928 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6929 {
6930 pGstSelReg->Sel = VmcsSelReg.Sel;
6931 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6932 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6933 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6934 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6935 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6936 }
6937 else
6938 {
6939 pGstSelReg->Sel = VmcsSelReg.Sel;
6940 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6941 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6942 switch (iSegReg)
6943 {
6944 case X86_SREG_CS:
6945 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6946 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6947 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6948 break;
6949
6950 case X86_SREG_SS:
6951 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6952 pGstSelReg->u32Limit = 0;
6953 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6954 break;
6955
6956 case X86_SREG_ES:
6957 case X86_SREG_DS:
6958 pGstSelReg->u64Base = 0;
6959 pGstSelReg->u32Limit = 0;
6960 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6961 break;
6962
6963 case X86_SREG_FS:
6964 case X86_SREG_GS:
6965 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6966 pGstSelReg->u32Limit = 0;
6967 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6968 break;
6969 }
6970 Assert(pGstSelReg->Attr.n.u1Unusable);
6971 }
6972 }
6973
6974 /* LDTR. */
6975 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6976 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6977 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6978 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6979 {
6980 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6981 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6982 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6983 }
6984 else
6985 {
6986 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6987 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6988 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6989 }
6990
6991 /* TR. */
6992 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6993 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6994 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6995 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6996 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6997 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6998 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6999
7000 /* GDTR. */
7001 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
7002 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
7003
7004 /* IDTR. */
7005 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
7006 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
7007}
7008
7009
7010/**
7011 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
7012 *
7013 * @returns VBox status code.
7014 * @param pVCpu The cross context virtual CPU structure.
7015 * @param pszInstr The VMX instruction name (for logging purposes).
7016 */
7017IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
7018{
7019 /*
7020 * Load guest MSRs.
7021 * See Intel spec. 26.4 "Loading MSRs".
7022 */
7023 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7024 const char *const pszFailure = "VM-exit";
7025
7026 /*
7027 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7028 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7029 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7030 */
7031 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7032 if (!cMsrs)
7033 return VINF_SUCCESS;
7034
7035 /*
7036 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7037 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7038 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7039 */
7040 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7041 if (fIsMsrCountValid)
7042 { /* likely */ }
7043 else
7044 {
7045 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7047 }
7048
7049 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
7050 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
7051 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
7052 if (RT_SUCCESS(rc))
7053 {
7054 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
7055 Assert(pMsr);
7056 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7057 {
7058 if ( !pMsr->u32Reserved
7059 && pMsr->u32Msr != MSR_K8_FS_BASE
7060 && pMsr->u32Msr != MSR_K8_GS_BASE
7061 && pMsr->u32Msr != MSR_K6_EFER
7062 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7063 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7064 {
7065 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7066 if (rcStrict == VINF_SUCCESS)
7067 continue;
7068
7069 /*
7070 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7071 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7072 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7073 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7074 * MSR in ring-0 if possible, or come up with a better, generic solution.
7075 */
7076 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7077 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7078 ? kVmxVDiag_Vmentry_MsrLoadRing3
7079 : kVmxVDiag_Vmentry_MsrLoad;
7080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7081 }
7082 else
7083 {
7084 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7086 }
7087 }
7088 }
7089 else
7090 {
7091 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
7092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7093 }
7094
7095 NOREF(pszInstr);
7096 NOREF(pszFailure);
7097 return VINF_SUCCESS;
7098}
7099
7100
7101/**
7102 * Loads the guest-state non-register state as part of VM-entry.
7103 *
7104 * @returns VBox status code.
7105 * @param pVCpu The cross context virtual CPU structure.
7106 *
7107 * @remarks This must be called only after loading the nested-guest register state
7108 * (especially nested-guest RIP).
7109 */
7110IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7111{
7112 /*
7113 * Load guest non-register state.
7114 * See Intel spec. 26.6 "Special Features of VM Entry"
7115 */
7116 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7117
7118 /*
7119 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7120 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7121 *
7122 * See Intel spec. 26.6.1 "Interruptibility State".
7123 */
7124 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7125 if ( !fEntryVectoring
7126 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7127 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7128 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7129 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7130
7131 /* NMI blocking. */
7132 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7133 {
7134 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7135 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7136 else
7137 {
7138 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7139 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7140 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7141 }
7142 }
7143 else
7144 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7145
7146 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7147
7148 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7149 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7150
7151 /* VPID is irrelevant. We don't support VPID yet. */
7152
7153 /* Clear address-range monitoring. */
7154 EMMonitorWaitClear(pVCpu);
7155}
7156
7157
7158/**
7159 * Loads the guest-state as part of VM-entry.
7160 *
7161 * @returns VBox status code.
7162 * @param pVCpu The cross context virtual CPU structure.
7163 * @param pszInstr The VMX instruction name (for logging purposes).
7164 *
7165 * @remarks This must be done after all the necessary steps prior to loading of
7166 * guest-state (e.g. checking various VMCS state).
7167 */
7168IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7169{
7170 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7171 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7172
7173 /*
7174 * Load guest RIP, RSP and RFLAGS.
7175 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7176 */
7177 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7178 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7179 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7180 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7181
7182 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7183 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7184 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7185
7186 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7187
7188 NOREF(pszInstr);
7189 return VINF_SUCCESS;
7190}
7191
7192
7193/**
7194 * Returns whether there are is a pending debug exception on VM-entry.
7195 *
7196 * @param pVCpu The cross context virtual CPU structure.
7197 * @param pszInstr The VMX instruction name (for logging purposes).
7198 */
7199IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7200{
7201 /*
7202 * Pending debug exceptions.
7203 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7204 */
7205 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7206 Assert(pVmcs);
7207
7208 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7209 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7210 if (fPendingDbgXcpt)
7211 {
7212 uint8_t uEntryIntInfoType;
7213 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7214 if (fEntryVectoring)
7215 {
7216 switch (uEntryIntInfoType)
7217 {
7218 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7219 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7220 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7221 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7222 fPendingDbgXcpt = false;
7223 break;
7224
7225 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7226 {
7227 /*
7228 * Whether the pending debug exception for software exceptions other than
7229 * #BP and #OF is delivered after injecting the exception or is discard
7230 * is CPU implementation specific. We will discard them (easier).
7231 */
7232 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7233 if ( uVector != X86_XCPT_BP
7234 && uVector != X86_XCPT_OF)
7235 fPendingDbgXcpt = false;
7236 RT_FALL_THRU();
7237 }
7238 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7239 {
7240 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7241 fPendingDbgXcpt = false;
7242 break;
7243 }
7244 }
7245 }
7246 else
7247 {
7248 /*
7249 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7250 * pending debug exception is held pending or is discarded is CPU implementation
7251 * specific. We will discard them (easier).
7252 */
7253 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7254 fPendingDbgXcpt = false;
7255
7256 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7257 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7258 fPendingDbgXcpt = false;
7259 }
7260 }
7261
7262 NOREF(pszInstr);
7263 return fPendingDbgXcpt;
7264}
7265
7266
7267/**
7268 * Set up the monitor-trap flag (MTF).
7269 *
7270 * @param pVCpu The cross context virtual CPU structure.
7271 * @param pszInstr The VMX instruction name (for logging purposes).
7272 */
7273IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7274{
7275 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7276 Assert(pVmcs);
7277 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7278 {
7279 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7280 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7281 }
7282 else
7283 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7284 NOREF(pszInstr);
7285}
7286
7287
7288/**
7289 * Set up the VMX-preemption timer.
7290 *
7291 * @param pVCpu The cross context virtual CPU structure.
7292 * @param pszInstr The VMX instruction name (for logging purposes).
7293 */
7294IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7295{
7296 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7297 Assert(pVmcs);
7298 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7299 {
7300 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7301 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7302 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7303
7304 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7305 }
7306 else
7307 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7308
7309 NOREF(pszInstr);
7310}
7311
7312
7313/**
7314 * Injects an event using TRPM given a VM-entry interruption info. and related
7315 * fields.
7316 *
7317 * @returns VBox status code.
7318 * @param pVCpu The cross context virtual CPU structure.
7319 * @param uEntryIntInfo The VM-entry interruption info.
7320 * @param uErrCode The error code associated with the event if any.
7321 * @param cbInstr The VM-entry instruction length (for software
7322 * interrupts and software exceptions). Pass 0
7323 * otherwise.
7324 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7325 */
7326IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7327 RTGCUINTPTR GCPtrFaultAddress)
7328{
7329 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7330
7331 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7332 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7333 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7334
7335 TRPMEVENT enmTrapType;
7336 switch (uType)
7337 {
7338 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7339 enmTrapType = TRPM_HARDWARE_INT;
7340 break;
7341
7342 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7343 enmTrapType = TRPM_SOFTWARE_INT;
7344 break;
7345
7346 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7347 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
7348 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7349 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7350 enmTrapType = TRPM_TRAP;
7351 break;
7352
7353 default:
7354 /* Shouldn't really happen. */
7355 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7356 break;
7357 }
7358
7359 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7360 AssertRCReturn(rc, rc);
7361
7362 if (fErrCodeValid)
7363 TRPMSetErrorCode(pVCpu, uErrCode);
7364
7365 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7366 && uVector == X86_XCPT_PF)
7367 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7368 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7369 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7370 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7371 {
7372 AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7373 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7374 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
7375 TRPMSetInstrLength(pVCpu, cbInstr);
7376 }
7377
7378 return VINF_SUCCESS;
7379}
7380
7381
7382/**
7383 * Performs event injection (if any) as part of VM-entry.
7384 *
7385 * @param pVCpu The cross context virtual CPU structure.
7386 * @param pszInstr The VMX instruction name (for logging purposes).
7387 */
7388IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7389{
7390 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7391
7392 /*
7393 * Inject events.
7394 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7395 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7396 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7397 * the actually delivery of this event.
7398 *
7399 * See Intel spec. 26.5 "Event Injection".
7400 */
7401 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7402 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7403
7404 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7405 if (fEntryIntInfoValid)
7406 {
7407 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7408 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7409 {
7410 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7411 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7412 return VINF_SUCCESS;
7413 }
7414
7415 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7416 pVCpu->cpum.GstCtx.cr2);
7417 if (RT_SUCCESS(rc))
7418 {
7419 /*
7420 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7421 *
7422 * However, we do it here on VM-entry because while it continues to not be visible to
7423 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7424 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7425 * information field.
7426 *
7427 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7428 */
7429 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7430 }
7431 return rc;
7432 }
7433
7434 /*
7435 * Inject any pending guest debug exception.
7436 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7437 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7438 */
7439 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7440 if (fPendingDbgXcpt)
7441 {
7442 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7443 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7444 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7445 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7446 0 /* GCPtrFaultAddress */);
7447 }
7448
7449 NOREF(pszInstr);
7450 return VINF_SUCCESS;
7451}
7452
7453
7454/**
7455 * Initializes all read-only VMCS fields as part of VM-entry.
7456 *
7457 * @param pVCpu The cross context virtual CPU structure.
7458 */
7459IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7460{
7461 /*
7462 * Any VMCS field which we do not establish on every VM-exit but may potentially
7463 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7464 * specified to be undefined needs to be initialized here.
7465 *
7466 * Thus, it is especially important to clear the VM-exit qualification field
7467 * since it must be zero for VM-exits where it is not used. Similarly, the
7468 * VM-exit interruption information field's valid bit needs to be cleared for
7469 * the same reasons.
7470 */
7471 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7472 Assert(pVmcs);
7473
7474 /* 16-bit (none currently). */
7475 /* 32-bit. */
7476 pVmcs->u32RoVmInstrError = 0;
7477 pVmcs->u32RoExitReason = 0;
7478 pVmcs->u32RoExitIntInfo = 0;
7479 pVmcs->u32RoExitIntErrCode = 0;
7480 pVmcs->u32RoIdtVectoringInfo = 0;
7481 pVmcs->u32RoIdtVectoringErrCode = 0;
7482 pVmcs->u32RoExitInstrLen = 0;
7483 pVmcs->u32RoExitInstrInfo = 0;
7484
7485 /* 64-bit. */
7486 pVmcs->u64RoGuestPhysAddr.u = 0;
7487
7488 /* Natural-width. */
7489 pVmcs->u64RoExitQual.u = 0;
7490 pVmcs->u64RoIoRcx.u = 0;
7491 pVmcs->u64RoIoRsi.u = 0;
7492 pVmcs->u64RoIoRdi.u = 0;
7493 pVmcs->u64RoIoRip.u = 0;
7494 pVmcs->u64RoGuestLinearAddr.u = 0;
7495}
7496
7497
7498/**
7499 * VMLAUNCH/VMRESUME instruction execution worker.
7500 *
7501 * @returns Strict VBox status code.
7502 * @param pVCpu The cross context virtual CPU structure.
7503 * @param cbInstr The instruction length in bytes.
7504 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7505 * VMXINSTRID_VMRESUME).
7506 *
7507 * @remarks Common VMX instruction checks are already expected to by the caller,
7508 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7509 */
7510IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7511{
7512# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7513 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7514 return VINF_EM_RAW_EMULATE_INSTR;
7515# else
7516 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7517 || uInstrId == VMXINSTRID_VMRESUME);
7518 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7519
7520 /* Nested-guest intercept. */
7521 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7522 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7523
7524 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7525
7526 /*
7527 * Basic VM-entry checks.
7528 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7529 * The checks following that do not have to follow a specific order.
7530 *
7531 * See Intel spec. 26.1 "Basic VM-entry Checks".
7532 */
7533
7534 /* CPL. */
7535 if (pVCpu->iem.s.uCpl == 0)
7536 { /* likely */ }
7537 else
7538 {
7539 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7540 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7541 return iemRaiseGeneralProtectionFault0(pVCpu);
7542 }
7543
7544 /* Current VMCS valid. */
7545 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7546 { /* likely */ }
7547 else
7548 {
7549 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7550 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7551 iemVmxVmFailInvalid(pVCpu);
7552 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7553 return VINF_SUCCESS;
7554 }
7555
7556 /* Current VMCS is not a shadow VMCS. */
7557 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7558 { /* likely */ }
7559 else
7560 {
7561 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7563 iemVmxVmFailInvalid(pVCpu);
7564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7565 return VINF_SUCCESS;
7566 }
7567
7568 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7569 * use block-by-STI here which is not quite correct. */
7570 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7571 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7572 { /* likely */ }
7573 else
7574 {
7575 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7576 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7577 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7578 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7579 return VINF_SUCCESS;
7580 }
7581
7582 if (uInstrId == VMXINSTRID_VMLAUNCH)
7583 {
7584 /* VMLAUNCH with non-clear VMCS. */
7585 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7586 { /* likely */ }
7587 else
7588 {
7589 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7591 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7592 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7593 return VINF_SUCCESS;
7594 }
7595 }
7596 else
7597 {
7598 /* VMRESUME with non-launched VMCS. */
7599 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7600 { /* likely */ }
7601 else
7602 {
7603 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7605 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7606 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7607 return VINF_SUCCESS;
7608 }
7609 }
7610
7611 /*
7612 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7613 * while entering VMX non-root mode. We do some of this while checking VM-execution
7614 * controls. The guest hypervisor should not make assumptions and cannot expect
7615 * predictable behavior if changes to these structures are made in guest memory while
7616 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7617 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7618 *
7619 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7620 */
7621 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7622 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7623 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7624 if (RT_SUCCESS(rc))
7625 {
7626 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7627 if (RT_SUCCESS(rc))
7628 {
7629 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7630 if (RT_SUCCESS(rc))
7631 {
7632 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7633 if (RT_SUCCESS(rc))
7634 {
7635 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7636 iemVmxVmentryInitReadOnlyFields(pVCpu);
7637
7638 /*
7639 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7640 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7641 * VM-exit when required.
7642 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7643 */
7644 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7645
7646 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7647 if (RT_SUCCESS(rc))
7648 {
7649 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7650 if (RT_SUCCESS(rc))
7651 {
7652 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7653 if (RT_SUCCESS(rc))
7654 {
7655 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7656
7657 /* VMLAUNCH instruction must update the VMCS launch state. */
7658 if (uInstrId == VMXINSTRID_VMLAUNCH)
7659 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7660
7661 /* Perform the VMX transition (PGM updates). */
7662 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7663 if (rcStrict == VINF_SUCCESS)
7664 { /* likely */ }
7665 else if (RT_SUCCESS(rcStrict))
7666 {
7667 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7668 VBOXSTRICTRC_VAL(rcStrict)));
7669 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7670 }
7671 else
7672 {
7673 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7674 return rcStrict;
7675 }
7676
7677 /* We've now entered nested-guest execution. */
7678 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7679
7680 /*
7681 * The priority of potential VM-exits during VM-entry is important.
7682 * The priorities of VM-exits and events are listed from highest
7683 * to lowest as follows:
7684 *
7685 * 1. Event injection.
7686 * 2. Trap on task-switch (T flag set in TSS).
7687 * 3. TPR below threshold / APIC-write.
7688 * 4. SMI, INIT.
7689 * 5. MTF exit.
7690 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7691 * 7. VMX-preemption timer.
7692 * 9. NMI-window exit.
7693 * 10. NMI injection.
7694 * 11. Interrupt-window exit.
7695 * 12. Virtual-interrupt injection.
7696 * 13. Interrupt injection.
7697 * 14. Process next instruction (fetch, decode, execute).
7698 */
7699
7700 /* Setup the VMX-preemption timer. */
7701 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7702
7703 /* Setup monitor-trap flag. */
7704 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7705
7706 /* Now that we've switched page tables, we can go ahead and inject any event. */
7707 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7708 if (RT_SUCCESS(rcStrict))
7709 {
7710 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7711 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr, VINF_SUCCESS);
7712 }
7713
7714 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7715 return rcStrict;
7716 }
7717 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7718 }
7719 }
7720 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7721 }
7722
7723 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7724 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7725 return VINF_SUCCESS;
7726 }
7727 }
7728 }
7729
7730 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7732 return VINF_SUCCESS;
7733# endif
7734}
7735
7736
7737/**
7738 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7739 * (causes a VM-exit) or not.
7740 *
7741 * @returns @c true if the instruction is intercepted, @c false otherwise.
7742 * @param pVCpu The cross context virtual CPU structure.
7743 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7744 * VMX_EXIT_WRMSR).
7745 * @param idMsr The MSR.
7746 */
7747IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7748{
7749 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7750 Assert( uExitReason == VMX_EXIT_RDMSR
7751 || uExitReason == VMX_EXIT_WRMSR);
7752
7753 /* Consult the MSR bitmap if the feature is supported. */
7754 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7755 Assert(pVmcs);
7756 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7757 {
7758 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7759 if (uExitReason == VMX_EXIT_RDMSR)
7760 {
7761 VMXMSREXITREAD enmRead;
7762 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7763 NULL /* penmWrite */);
7764 AssertRC(rc);
7765 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7766 return true;
7767 }
7768 else
7769 {
7770 VMXMSREXITWRITE enmWrite;
7771 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7772 &enmWrite);
7773 AssertRC(rc);
7774 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7775 return true;
7776 }
7777 return false;
7778 }
7779
7780 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7781 return true;
7782}
7783
7784
7785/**
7786 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7787 * intercepted (causes a VM-exit) or not.
7788 *
7789 * @returns @c true if the instruction is intercepted, @c false otherwise.
7790 * @param pVCpu The cross context virtual CPU structure.
7791 * @param u64FieldEnc The VMCS field encoding.
7792 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7793 * VMX_EXIT_VMREAD).
7794 */
7795IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7796{
7797 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7798 Assert( uExitReason == VMX_EXIT_VMREAD
7799 || uExitReason == VMX_EXIT_VMWRITE);
7800
7801 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7802 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7803 return true;
7804
7805 /*
7806 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7807 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7808 */
7809 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7810 return true;
7811
7812 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7813 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7814 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7815 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7816 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7817 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7818 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7819 pbBitmap += (u32FieldEnc >> 3);
7820 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7821 return true;
7822
7823 return false;
7824}
7825
7826
7827/**
7828 * VMREAD common (memory/register) instruction execution worker
7829 *
7830 * @returns Strict VBox status code.
7831 * @param pVCpu The cross context virtual CPU structure.
7832 * @param cbInstr The instruction length in bytes.
7833 * @param pu64Dst Where to write the VMCS value (only updated when
7834 * VINF_SUCCESS is returned).
7835 * @param u64FieldEnc The VMCS field encoding.
7836 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7837 * be NULL.
7838 */
7839IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7840 PCVMXVEXITINFO pExitInfo)
7841{
7842 /* Nested-guest intercept. */
7843 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7844 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7845 {
7846 if (pExitInfo)
7847 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7848 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7849 }
7850
7851 /* CPL. */
7852 if (pVCpu->iem.s.uCpl == 0)
7853 { /* likely */ }
7854 else
7855 {
7856 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7857 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7858 return iemRaiseGeneralProtectionFault0(pVCpu);
7859 }
7860
7861 /* VMCS pointer in root mode. */
7862 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7863 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7864 { /* likely */ }
7865 else
7866 {
7867 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7869 iemVmxVmFailInvalid(pVCpu);
7870 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7871 return VINF_SUCCESS;
7872 }
7873
7874 /* VMCS-link pointer in non-root mode. */
7875 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7876 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7877 { /* likely */ }
7878 else
7879 {
7880 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7881 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7882 iemVmxVmFailInvalid(pVCpu);
7883 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7884 return VINF_SUCCESS;
7885 }
7886
7887 /* Supported VMCS field. */
7888 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7889 { /* likely */ }
7890 else
7891 {
7892 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7893 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7894 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7895 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7896 return VINF_SUCCESS;
7897 }
7898
7899 /*
7900 * Setup reading from the current or shadow VMCS.
7901 */
7902 uint8_t *pbVmcs;
7903 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7904 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7905 else
7906 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7907 Assert(pbVmcs);
7908
7909 VMXVMCSFIELDENC FieldEnc;
7910 FieldEnc.u = u64FieldEnc;
7911 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7912 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7913 uint8_t const uWidthType = (uWidth << 2) | uType;
7914 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7915 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7916 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7917 Assert(offField < VMX_V_VMCS_SIZE);
7918
7919 /*
7920 * Read the VMCS component based on the field's effective width.
7921 *
7922 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7923 * indicates high bits (little endian).
7924 *
7925 * Note! The caller is responsible to trim the result and update registers
7926 * or memory locations are required. Here we just zero-extend to the largest
7927 * type (i.e. 64-bits).
7928 */
7929 uint8_t *pbField = pbVmcs + offField;
7930 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7931 switch (uEffWidth)
7932 {
7933 case VMX_VMCS_ENC_WIDTH_64BIT:
7934 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7935 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7936 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7937 }
7938 return VINF_SUCCESS;
7939}
7940
7941
7942/**
7943 * VMREAD (64-bit register) instruction execution worker.
7944 *
7945 * @returns Strict VBox status code.
7946 * @param pVCpu The cross context virtual CPU structure.
7947 * @param cbInstr The instruction length in bytes.
7948 * @param pu64Dst Where to store the VMCS field's value.
7949 * @param u64FieldEnc The VMCS field encoding.
7950 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7951 * be NULL.
7952 */
7953IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7954 PCVMXVEXITINFO pExitInfo)
7955{
7956 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7957 if (rcStrict == VINF_SUCCESS)
7958 {
7959 iemVmxVmreadSuccess(pVCpu, cbInstr);
7960 return VINF_SUCCESS;
7961 }
7962
7963 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7964 return rcStrict;
7965}
7966
7967
7968/**
7969 * VMREAD (32-bit register) instruction execution worker.
7970 *
7971 * @returns Strict VBox status code.
7972 * @param pVCpu The cross context virtual CPU structure.
7973 * @param cbInstr The instruction length in bytes.
7974 * @param pu32Dst Where to store the VMCS field's value.
7975 * @param u32FieldEnc The VMCS field encoding.
7976 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7977 * be NULL.
7978 */
7979IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7980 PCVMXVEXITINFO pExitInfo)
7981{
7982 uint64_t u64Dst;
7983 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7984 if (rcStrict == VINF_SUCCESS)
7985 {
7986 *pu32Dst = u64Dst;
7987 iemVmxVmreadSuccess(pVCpu, cbInstr);
7988 return VINF_SUCCESS;
7989 }
7990
7991 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7992 return rcStrict;
7993}
7994
7995
7996/**
7997 * VMREAD (memory) instruction execution worker.
7998 *
7999 * @returns Strict VBox status code.
8000 * @param pVCpu The cross context virtual CPU structure.
8001 * @param cbInstr The instruction length in bytes.
8002 * @param iEffSeg The effective segment register to use with @a u64Val.
8003 * Pass UINT8_MAX if it is a register access.
8004 * @param enmEffAddrMode The effective addressing mode (only used with memory
8005 * operand).
8006 * @param GCPtrDst The guest linear address to store the VMCS field's
8007 * value.
8008 * @param u64FieldEnc The VMCS field encoding.
8009 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8010 * be NULL.
8011 */
8012IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
8013 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
8014{
8015 uint64_t u64Dst;
8016 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
8017 if (rcStrict == VINF_SUCCESS)
8018 {
8019 /*
8020 * Write the VMCS field's value to the location specified in guest-memory.
8021 *
8022 * The pointer size depends on the address size (address-size prefix allowed).
8023 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
8024 */
8025 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8026 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8027 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
8028
8029 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8030 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8031 else
8032 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8033 if (rcStrict == VINF_SUCCESS)
8034 {
8035 iemVmxVmreadSuccess(pVCpu, cbInstr);
8036 return VINF_SUCCESS;
8037 }
8038
8039 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8040 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8041 return rcStrict;
8042 }
8043
8044 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8045 return rcStrict;
8046}
8047
8048
8049/**
8050 * VMWRITE instruction execution worker.
8051 *
8052 * @returns Strict VBox status code.
8053 * @param pVCpu The cross context virtual CPU structure.
8054 * @param cbInstr The instruction length in bytes.
8055 * @param iEffSeg The effective segment register to use with @a u64Val.
8056 * Pass UINT8_MAX if it is a register access.
8057 * @param enmEffAddrMode The effective addressing mode (only used with memory
8058 * operand).
8059 * @param u64Val The value to write (or guest linear address to the
8060 * value), @a iEffSeg will indicate if it's a memory
8061 * operand.
8062 * @param u64FieldEnc The VMCS field encoding.
8063 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8064 * be NULL.
8065 */
8066IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
8067 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
8068{
8069 /* Nested-guest intercept. */
8070 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8071 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8072 {
8073 if (pExitInfo)
8074 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8075 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8076 }
8077
8078 /* CPL. */
8079 if (pVCpu->iem.s.uCpl == 0)
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8085 return iemRaiseGeneralProtectionFault0(pVCpu);
8086 }
8087
8088 /* VMCS pointer in root mode. */
8089 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8090 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8091 { /* likely */ }
8092 else
8093 {
8094 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8096 iemVmxVmFailInvalid(pVCpu);
8097 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8098 return VINF_SUCCESS;
8099 }
8100
8101 /* VMCS-link pointer in non-root mode. */
8102 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8103 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8104 { /* likely */ }
8105 else
8106 {
8107 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8109 iemVmxVmFailInvalid(pVCpu);
8110 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8111 return VINF_SUCCESS;
8112 }
8113
8114 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8115 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8116 if (!fIsRegOperand)
8117 {
8118 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8119 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8120 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8121
8122 /* Read the value from the specified guest memory location. */
8123 VBOXSTRICTRC rcStrict;
8124 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8125 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8126 else
8127 {
8128 uint32_t u32Val;
8129 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8130 u64Val = u32Val;
8131 }
8132 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8133 {
8134 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8135 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8136 return rcStrict;
8137 }
8138 }
8139 else
8140 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8141
8142 /* Supported VMCS field. */
8143 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8144 { /* likely */ }
8145 else
8146 {
8147 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8148 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8149 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8150 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8151 return VINF_SUCCESS;
8152 }
8153
8154 /* Read-only VMCS field. */
8155 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8156 if ( !fIsFieldReadOnly
8157 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8158 { /* likely */ }
8159 else
8160 {
8161 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8163 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8164 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8165 return VINF_SUCCESS;
8166 }
8167
8168 /*
8169 * Setup writing to the current or shadow VMCS.
8170 */
8171 uint8_t *pbVmcs;
8172 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8173 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8174 else
8175 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8176 Assert(pbVmcs);
8177
8178 VMXVMCSFIELDENC FieldEnc;
8179 FieldEnc.u = u64FieldEnc;
8180 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8181 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8182 uint8_t const uWidthType = (uWidth << 2) | uType;
8183 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8184 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8185 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8186 Assert(offField < VMX_V_VMCS_SIZE);
8187
8188 /*
8189 * Write the VMCS component based on the field's effective width.
8190 *
8191 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8192 * indicates high bits (little endian).
8193 */
8194 uint8_t *pbField = pbVmcs + offField;
8195 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8196 switch (uEffWidth)
8197 {
8198 case VMX_VMCS_ENC_WIDTH_64BIT:
8199 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8200 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8201 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8202 }
8203
8204 iemVmxVmSucceed(pVCpu);
8205 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8206 return VINF_SUCCESS;
8207}
8208
8209
8210/**
8211 * VMCLEAR instruction execution worker.
8212 *
8213 * @returns Strict VBox status code.
8214 * @param pVCpu The cross context virtual CPU structure.
8215 * @param cbInstr The instruction length in bytes.
8216 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8217 * @param GCPtrVmcs The linear address of the VMCS pointer.
8218 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8219 * be NULL.
8220 *
8221 * @remarks Common VMX instruction checks are already expected to by the caller,
8222 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8223 */
8224IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8225 PCVMXVEXITINFO pExitInfo)
8226{
8227 /* Nested-guest intercept. */
8228 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8229 {
8230 if (pExitInfo)
8231 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8232 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8233 }
8234
8235 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8236
8237 /* CPL. */
8238 if (pVCpu->iem.s.uCpl == 0)
8239 { /* likely */ }
8240 else
8241 {
8242 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8243 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8244 return iemRaiseGeneralProtectionFault0(pVCpu);
8245 }
8246
8247 /* Get the VMCS pointer from the location specified by the source memory operand. */
8248 RTGCPHYS GCPhysVmcs;
8249 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8250 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8251 { /* likely */ }
8252 else
8253 {
8254 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8256 return rcStrict;
8257 }
8258
8259 /* VMCS pointer alignment. */
8260 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8261 { /* likely */ }
8262 else
8263 {
8264 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8265 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8266 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8267 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8268 return VINF_SUCCESS;
8269 }
8270
8271 /* VMCS physical-address width limits. */
8272 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8273 { /* likely */ }
8274 else
8275 {
8276 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8277 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8278 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8279 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8280 return VINF_SUCCESS;
8281 }
8282
8283 /* VMCS is not the VMXON region. */
8284 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8285 { /* likely */ }
8286 else
8287 {
8288 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8289 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8290 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8291 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8292 return VINF_SUCCESS;
8293 }
8294
8295 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8296 restriction imposed by our implementation. */
8297 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8298 { /* likely */ }
8299 else
8300 {
8301 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8302 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8303 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8304 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8305 return VINF_SUCCESS;
8306 }
8307
8308 /*
8309 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8310 *
8311 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8312 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8313 * to 'clear'.
8314 */
8315 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8316 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8317 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8318 {
8319 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8320 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8321 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8322 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8323 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8324 }
8325 else
8326 {
8327 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8328 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8329 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8330 if (RT_FAILURE(rcStrict))
8331 return rcStrict;
8332 }
8333
8334 iemVmxVmSucceed(pVCpu);
8335 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8336 return VINF_SUCCESS;
8337}
8338
8339
8340/**
8341 * VMPTRST instruction execution worker.
8342 *
8343 * @returns Strict VBox status code.
8344 * @param pVCpu The cross context virtual CPU structure.
8345 * @param cbInstr The instruction length in bytes.
8346 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8347 * @param GCPtrVmcs The linear address of where to store the current VMCS
8348 * pointer.
8349 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8350 * be NULL.
8351 *
8352 * @remarks Common VMX instruction checks are already expected to by the caller,
8353 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8354 */
8355IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8356 PCVMXVEXITINFO pExitInfo)
8357{
8358 /* Nested-guest intercept. */
8359 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8360 {
8361 if (pExitInfo)
8362 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8363 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8364 }
8365
8366 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8367
8368 /* CPL. */
8369 if (pVCpu->iem.s.uCpl == 0)
8370 { /* likely */ }
8371 else
8372 {
8373 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8374 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8375 return iemRaiseGeneralProtectionFault0(pVCpu);
8376 }
8377
8378 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8379 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8380 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8381 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8382 {
8383 iemVmxVmSucceed(pVCpu);
8384 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8385 return rcStrict;
8386 }
8387
8388 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8389 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8390 return rcStrict;
8391}
8392
8393
8394/**
8395 * VMPTRLD instruction execution worker.
8396 *
8397 * @returns Strict VBox status code.
8398 * @param pVCpu The cross context virtual CPU structure.
8399 * @param cbInstr The instruction length in bytes.
8400 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8401 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8402 * be NULL.
8403 *
8404 * @remarks Common VMX instruction checks are already expected to by the caller,
8405 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8406 */
8407IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8408 PCVMXVEXITINFO pExitInfo)
8409{
8410 /* Nested-guest intercept. */
8411 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8412 {
8413 if (pExitInfo)
8414 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8415 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8416 }
8417
8418 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8419
8420 /* CPL. */
8421 if (pVCpu->iem.s.uCpl == 0)
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8427 return iemRaiseGeneralProtectionFault0(pVCpu);
8428 }
8429
8430 /* Get the VMCS pointer from the location specified by the source memory operand. */
8431 RTGCPHYS GCPhysVmcs;
8432 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8433 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8434 { /* likely */ }
8435 else
8436 {
8437 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8438 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8439 return rcStrict;
8440 }
8441
8442 /* VMCS pointer alignment. */
8443 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8444 { /* likely */ }
8445 else
8446 {
8447 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8448 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8449 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8450 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8451 return VINF_SUCCESS;
8452 }
8453
8454 /* VMCS physical-address width limits. */
8455 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8456 { /* likely */ }
8457 else
8458 {
8459 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8461 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8462 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8463 return VINF_SUCCESS;
8464 }
8465
8466 /* VMCS is not the VMXON region. */
8467 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8468 { /* likely */ }
8469 else
8470 {
8471 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8473 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8474 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8475 return VINF_SUCCESS;
8476 }
8477
8478 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8479 restriction imposed by our implementation. */
8480 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8481 { /* likely */ }
8482 else
8483 {
8484 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8485 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8486 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8487 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8488 return VINF_SUCCESS;
8489 }
8490
8491 /* Read just the VMCS revision from the VMCS. */
8492 VMXVMCSREVID VmcsRevId;
8493 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8494 if (RT_SUCCESS(rc))
8495 { /* likely */ }
8496 else
8497 {
8498 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8499 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8500 return rc;
8501 }
8502
8503 /*
8504 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8505 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8506 */
8507 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8508 && ( !VmcsRevId.n.fIsShadowVmcs
8509 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8510 { /* likely */ }
8511 else
8512 {
8513 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8514 {
8515 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8516 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8518 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8519 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8520 return VINF_SUCCESS;
8521 }
8522
8523 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8525 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8526 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8527 return VINF_SUCCESS;
8528 }
8529
8530 /*
8531 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8532 * the cache of an existing, current VMCS back to guest memory before loading a new,
8533 * different current VMCS.
8534 */
8535 bool fLoadVmcsFromMem;
8536 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8537 {
8538 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8539 {
8540 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8541 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8542 fLoadVmcsFromMem = true;
8543 }
8544 else
8545 fLoadVmcsFromMem = false;
8546 }
8547 else
8548 fLoadVmcsFromMem = true;
8549
8550 if (fLoadVmcsFromMem)
8551 {
8552 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8553 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8554 sizeof(VMXVVMCS));
8555 if (RT_SUCCESS(rc))
8556 { /* likely */ }
8557 else
8558 {
8559 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8560 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8561 return rc;
8562 }
8563 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8564 }
8565
8566 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8567 iemVmxVmSucceed(pVCpu);
8568 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8569 return VINF_SUCCESS;
8570}
8571
8572
8573/**
8574 * VMXON instruction execution worker.
8575 *
8576 * @returns Strict VBox status code.
8577 * @param pVCpu The cross context virtual CPU structure.
8578 * @param cbInstr The instruction length in bytes.
8579 * @param iEffSeg The effective segment register to use with @a
8580 * GCPtrVmxon.
8581 * @param GCPtrVmxon The linear address of the VMXON pointer.
8582 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8583 * Optional, can be NULL.
8584 *
8585 * @remarks Common VMX instruction checks are already expected to by the caller,
8586 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8587 */
8588IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8589 PCVMXVEXITINFO pExitInfo)
8590{
8591 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8592 {
8593 /* CPL. */
8594 if (pVCpu->iem.s.uCpl == 0)
8595 { /* likely */ }
8596 else
8597 {
8598 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8599 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8600 return iemRaiseGeneralProtectionFault0(pVCpu);
8601 }
8602
8603 /* A20M (A20 Masked) mode. */
8604 if (PGMPhysIsA20Enabled(pVCpu))
8605 { /* likely */ }
8606 else
8607 {
8608 Log(("vmxon: A20M mode -> #GP(0)\n"));
8609 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8610 return iemRaiseGeneralProtectionFault0(pVCpu);
8611 }
8612
8613 /* CR0. */
8614 {
8615 /* CR0 MB1 bits. */
8616 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8617 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8618 { /* likely */ }
8619 else
8620 {
8621 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8622 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8623 return iemRaiseGeneralProtectionFault0(pVCpu);
8624 }
8625
8626 /* CR0 MBZ bits. */
8627 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8628 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8629 { /* likely */ }
8630 else
8631 {
8632 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8634 return iemRaiseGeneralProtectionFault0(pVCpu);
8635 }
8636 }
8637
8638 /* CR4. */
8639 {
8640 /* CR4 MB1 bits. */
8641 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8642 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8643 { /* likely */ }
8644 else
8645 {
8646 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8647 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8648 return iemRaiseGeneralProtectionFault0(pVCpu);
8649 }
8650
8651 /* CR4 MBZ bits. */
8652 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8653 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8654 { /* likely */ }
8655 else
8656 {
8657 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8658 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8659 return iemRaiseGeneralProtectionFault0(pVCpu);
8660 }
8661 }
8662
8663 /* Feature control MSR's LOCK and VMXON bits. */
8664 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8665 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8666 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8667 { /* likely */ }
8668 else
8669 {
8670 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8671 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8672 return iemRaiseGeneralProtectionFault0(pVCpu);
8673 }
8674
8675 /* Get the VMXON pointer from the location specified by the source memory operand. */
8676 RTGCPHYS GCPhysVmxon;
8677 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8678 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8679 { /* likely */ }
8680 else
8681 {
8682 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8684 return rcStrict;
8685 }
8686
8687 /* VMXON region pointer alignment. */
8688 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8689 { /* likely */ }
8690 else
8691 {
8692 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8694 iemVmxVmFailInvalid(pVCpu);
8695 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8696 return VINF_SUCCESS;
8697 }
8698
8699 /* VMXON physical-address width limits. */
8700 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8701 { /* likely */ }
8702 else
8703 {
8704 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8706 iemVmxVmFailInvalid(pVCpu);
8707 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8708 return VINF_SUCCESS;
8709 }
8710
8711 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8712 restriction imposed by our implementation. */
8713 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8714 { /* likely */ }
8715 else
8716 {
8717 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8718 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8719 iemVmxVmFailInvalid(pVCpu);
8720 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8721 return VINF_SUCCESS;
8722 }
8723
8724 /* Read the VMCS revision ID from the VMXON region. */
8725 VMXVMCSREVID VmcsRevId;
8726 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8727 if (RT_SUCCESS(rc))
8728 { /* likely */ }
8729 else
8730 {
8731 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8732 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8733 return rc;
8734 }
8735
8736 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8737 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8738 { /* likely */ }
8739 else
8740 {
8741 /* Revision ID mismatch. */
8742 if (!VmcsRevId.n.fIsShadowVmcs)
8743 {
8744 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8745 VmcsRevId.n.u31RevisionId));
8746 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8747 iemVmxVmFailInvalid(pVCpu);
8748 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8749 return VINF_SUCCESS;
8750 }
8751
8752 /* Shadow VMCS disallowed. */
8753 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8755 iemVmxVmFailInvalid(pVCpu);
8756 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8757 return VINF_SUCCESS;
8758 }
8759
8760 /*
8761 * Record that we're in VMX operation, block INIT, block and disable A20M.
8762 */
8763 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8764 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8765 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8766
8767 /* Clear address-range monitoring. */
8768 EMMonitorWaitClear(pVCpu);
8769 /** @todo NSTVMX: Intel PT. */
8770
8771 iemVmxVmSucceed(pVCpu);
8772 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8773 return VINF_SUCCESS;
8774 }
8775 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8776 {
8777 /* Nested-guest intercept. */
8778 if (pExitInfo)
8779 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8780 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8781 }
8782
8783 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8784
8785 /* CPL. */
8786 if (pVCpu->iem.s.uCpl > 0)
8787 {
8788 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8789 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8790 return iemRaiseGeneralProtectionFault0(pVCpu);
8791 }
8792
8793 /* VMXON when already in VMX root mode. */
8794 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8795 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8796 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8797 return VINF_SUCCESS;
8798}
8799
8800
8801/**
8802 * Implements 'VMXOFF'.
8803 *
8804 * @remarks Common VMX instruction checks are already expected to by the caller,
8805 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8806 */
8807IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8808{
8809 /* Nested-guest intercept. */
8810 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8811 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8812
8813 /* CPL. */
8814 if (pVCpu->iem.s.uCpl == 0)
8815 { /* likely */ }
8816 else
8817 {
8818 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8819 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8820 return iemRaiseGeneralProtectionFault0(pVCpu);
8821 }
8822
8823 /* Dual monitor treatment of SMIs and SMM. */
8824 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8825 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8826 { /* likely */ }
8827 else
8828 {
8829 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8830 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8831 return VINF_SUCCESS;
8832 }
8833
8834 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8835 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8836 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8837
8838 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8839 { /** @todo NSTVMX: Unblock SMI. */ }
8840
8841 EMMonitorWaitClear(pVCpu);
8842 /** @todo NSTVMX: Unblock and enable A20M. */
8843
8844 iemVmxVmSucceed(pVCpu);
8845 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8846 return VINF_SUCCESS;
8847}
8848
8849
8850/**
8851 * Implements 'VMXON'.
8852 */
8853IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8854{
8855 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8856}
8857
8858
8859/**
8860 * Implements 'VMLAUNCH'.
8861 */
8862IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8863{
8864 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8865}
8866
8867
8868/**
8869 * Implements 'VMRESUME'.
8870 */
8871IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8872{
8873 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8874}
8875
8876
8877/**
8878 * Implements 'VMPTRLD'.
8879 */
8880IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8881{
8882 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8883}
8884
8885
8886/**
8887 * Implements 'VMPTRST'.
8888 */
8889IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8890{
8891 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8892}
8893
8894
8895/**
8896 * Implements 'VMCLEAR'.
8897 */
8898IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8899{
8900 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8901}
8902
8903
8904/**
8905 * Implements 'VMWRITE' register.
8906 */
8907IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8908{
8909 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8910 NULL /* pExitInfo */);
8911}
8912
8913
8914/**
8915 * Implements 'VMWRITE' memory.
8916 */
8917IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8918{
8919 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8920}
8921
8922
8923/**
8924 * Implements 'VMREAD' register (64-bit).
8925 */
8926IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8927{
8928 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8929}
8930
8931
8932/**
8933 * Implements 'VMREAD' register (32-bit).
8934 */
8935IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8936{
8937 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8938}
8939
8940
8941/**
8942 * Implements 'VMREAD' memory, 64-bit register.
8943 */
8944IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8945{
8946 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8947}
8948
8949
8950/**
8951 * Implements 'VMREAD' memory, 32-bit register.
8952 */
8953IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8954{
8955 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8956}
8957
8958
8959/**
8960 * Implements VMX's implementation of PAUSE.
8961 */
8962IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8963{
8964 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8965 {
8966 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8967 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8968 return rcStrict;
8969 }
8970
8971 /*
8972 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8973 * a VM-exit, the instruction operates normally.
8974 */
8975 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8976 return VINF_SUCCESS;
8977}
8978
8979#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8980
8981
8982/**
8983 * Implements 'VMCALL'.
8984 */
8985IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8986{
8987#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8988 /* Nested-guest intercept. */
8989 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8990 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8991#endif
8992
8993 /* Join forces with vmmcall. */
8994 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8995}
8996
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