VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78425

Last change on this file since 78425 was 78371, checked in by vboxsync, 6 years ago

VMM: Move VT-x/AMD-V helpers that are based on CPU specs to CPUM in preparation of upcoming changes. It is better placed in CPUM if say NEM in future needs to implement nested VT-x/AMD-V.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 354.0 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78371 2019-05-03 08:21:44Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_INT_WINDOW
173 * VMX_EXIT_NMI_WINDOW
174 * VMX_EXIT_GETSEC
175 * VMX_EXIT_RSM
176 * VMX_EXIT_MTF
177 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
178 * VMX_EXIT_ERR_MACHINE_CHECK
179 * VMX_EXIT_TPR_BELOW_THRESHOLD
180 * VMX_EXIT_APIC_ACCESS
181 * VMX_EXIT_VIRTUALIZED_EOI
182 * VMX_EXIT_EPT_VIOLATION
183 * VMX_EXIT_EPT_MISCONFIG
184 * VMX_EXIT_INVEPT
185 * VMX_EXIT_PREEMPT_TIMER
186 * VMX_EXIT_INVVPID
187 * VMX_EXIT_APIC_WRITE
188 * VMX_EXIT_RDRAND
189 * VMX_EXIT_VMFUNC
190 * VMX_EXIT_ENCLS
191 * VMX_EXIT_RDSEED
192 * VMX_EXIT_PML_FULL
193 * VMX_EXIT_XSAVES
194 * VMX_EXIT_XRSTORS
195 */
196/**
197 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
198 *
199 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
200 * second dimension is the Index, see VMXVMCSFIELDENC.
201 */
202uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
203{
204 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
205 {
206 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
207 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
208 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
209 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
211 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
212 },
213 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
214 {
215 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
216 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
218 /* 24-25 */ UINT16_MAX, UINT16_MAX
219 },
220 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
221 {
222 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
223 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
224 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
225 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
226 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
227 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
228 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
229 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
230 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
231 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
232 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
234 },
235 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
244 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
247 },
248 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
257 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
258 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
259 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
260 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
261 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
262 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
263 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
264 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
265 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
266 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
267 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
268 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
269 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
270 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
271 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
272 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
273 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
274 /* 24 */ UINT16_MAX,
275 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
280 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
281 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
282 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 25 */ UINT16_MAX
284 },
285 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
297 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
298 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
299 },
300 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
303 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
304 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
305 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
322 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
324 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
325 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
326 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
327 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
328 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
329 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-25 */ UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
370 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
371 },
372 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
373 {
374 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
375 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 25 */ UINT16_MAX
379 },
380 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
381 {
382 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
383 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
384 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
385 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
386 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
387 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
388 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
389 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
390 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
391 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 24-25 */ UINT16_MAX, UINT16_MAX
393 },
394 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
395 {
396 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
397 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
398 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
399 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
400 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
401 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
402 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
403 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
405 },
406 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
407 {
408 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
409 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
410 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
411 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
412 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
413 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
414 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
415 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
416 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
417 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
418 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
419 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
420 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
421 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
422 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
423 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
424 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
425 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
426 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
427 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
428 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
429 },
430 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
431 {
432 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
433 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
434 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
435 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
436 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
437 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
438 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
439 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
440 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
441 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
442 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
443 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
444 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
445 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
446 }
447};
448
449
450/**
451 * Returns whether the given VMCS field is valid and supported by our emulation.
452 *
453 * @param pVCpu The cross context virtual CPU structure.
454 * @param u64FieldEnc The VMCS field encoding.
455 *
456 * @remarks This takes into account the CPU features exposed to the guest.
457 */
458IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
459{
460 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
461 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
462 if (!uFieldEncHi)
463 { /* likely */ }
464 else
465 return false;
466
467 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
468 switch (uFieldEncLo)
469 {
470 /*
471 * 16-bit fields.
472 */
473 /* Control fields. */
474 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
475 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
476 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
477
478 /* Guest-state fields. */
479 case VMX_VMCS16_GUEST_ES_SEL:
480 case VMX_VMCS16_GUEST_CS_SEL:
481 case VMX_VMCS16_GUEST_SS_SEL:
482 case VMX_VMCS16_GUEST_DS_SEL:
483 case VMX_VMCS16_GUEST_FS_SEL:
484 case VMX_VMCS16_GUEST_GS_SEL:
485 case VMX_VMCS16_GUEST_LDTR_SEL:
486 case VMX_VMCS16_GUEST_TR_SEL: return true;
487 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
488 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
489
490 /* Host-state fields. */
491 case VMX_VMCS16_HOST_ES_SEL:
492 case VMX_VMCS16_HOST_CS_SEL:
493 case VMX_VMCS16_HOST_SS_SEL:
494 case VMX_VMCS16_HOST_DS_SEL:
495 case VMX_VMCS16_HOST_FS_SEL:
496 case VMX_VMCS16_HOST_GS_SEL:
497 case VMX_VMCS16_HOST_TR_SEL: return true;
498
499 /*
500 * 64-bit fields.
501 */
502 /* Control fields. */
503 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
504 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
505 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
506 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
507 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
508 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
509 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
510 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
511 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
512 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
513 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
514 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
515 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
516 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
517 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
518 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
519 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
520 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
521 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
522 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
523 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
524 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
525 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
526 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
527 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
528 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
529 case VMX_VMCS64_CTRL_EPTP_FULL:
530 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
531 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
532 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
533 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
534 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
535 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
536 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
537 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
538 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
539 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
540 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
541 {
542 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
543 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
544 }
545 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
547 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
548 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
549 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
550 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
551 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
552 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
553 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
554 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
555 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
556 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
557
558 /* Read-only data fields. */
559 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
560 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
561
562 /* Guest-state fields. */
563 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
564 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
565 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
566 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
567 case VMX_VMCS64_GUEST_PAT_FULL:
568 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
569 case VMX_VMCS64_GUEST_EFER_FULL:
570 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
571 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
572 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
573 case VMX_VMCS64_GUEST_PDPTE0_FULL:
574 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
575 case VMX_VMCS64_GUEST_PDPTE1_FULL:
576 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
577 case VMX_VMCS64_GUEST_PDPTE2_FULL:
578 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
579 case VMX_VMCS64_GUEST_PDPTE3_FULL:
580 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
581 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
582 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
583
584 /* Host-state fields. */
585 case VMX_VMCS64_HOST_PAT_FULL:
586 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
587 case VMX_VMCS64_HOST_EFER_FULL:
588 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
589 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
590 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
591
592 /*
593 * 32-bit fields.
594 */
595 /* Control fields. */
596 case VMX_VMCS32_CTRL_PIN_EXEC:
597 case VMX_VMCS32_CTRL_PROC_EXEC:
598 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
599 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
600 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
601 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
602 case VMX_VMCS32_CTRL_EXIT:
603 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
604 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
605 case VMX_VMCS32_CTRL_ENTRY:
606 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
607 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
608 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
609 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
610 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
611 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
612 case VMX_VMCS32_CTRL_PLE_GAP:
613 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
614
615 /* Read-only data fields. */
616 case VMX_VMCS32_RO_VM_INSTR_ERROR:
617 case VMX_VMCS32_RO_EXIT_REASON:
618 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
619 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
620 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
621 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
622 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
623 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
624
625 /* Guest-state fields. */
626 case VMX_VMCS32_GUEST_ES_LIMIT:
627 case VMX_VMCS32_GUEST_CS_LIMIT:
628 case VMX_VMCS32_GUEST_SS_LIMIT:
629 case VMX_VMCS32_GUEST_DS_LIMIT:
630 case VMX_VMCS32_GUEST_FS_LIMIT:
631 case VMX_VMCS32_GUEST_GS_LIMIT:
632 case VMX_VMCS32_GUEST_LDTR_LIMIT:
633 case VMX_VMCS32_GUEST_TR_LIMIT:
634 case VMX_VMCS32_GUEST_GDTR_LIMIT:
635 case VMX_VMCS32_GUEST_IDTR_LIMIT:
636 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
638 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
639 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
640 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
641 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
642 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
643 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
644 case VMX_VMCS32_GUEST_INT_STATE:
645 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
646 case VMX_VMCS32_GUEST_SMBASE:
647 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
648 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
649
650 /* Host-state fields. */
651 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
652
653 /*
654 * Natural-width fields.
655 */
656 /* Control fields. */
657 case VMX_VMCS_CTRL_CR0_MASK:
658 case VMX_VMCS_CTRL_CR4_MASK:
659 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
660 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
661 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
662 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
663 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
664 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
665
666 /* Read-only data fields. */
667 case VMX_VMCS_RO_EXIT_QUALIFICATION:
668 case VMX_VMCS_RO_IO_RCX:
669 case VMX_VMCS_RO_IO_RSX:
670 case VMX_VMCS_RO_IO_RDI:
671 case VMX_VMCS_RO_IO_RIP:
672 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
673
674 /* Guest-state fields. */
675 case VMX_VMCS_GUEST_CR0:
676 case VMX_VMCS_GUEST_CR3:
677 case VMX_VMCS_GUEST_CR4:
678 case VMX_VMCS_GUEST_ES_BASE:
679 case VMX_VMCS_GUEST_CS_BASE:
680 case VMX_VMCS_GUEST_SS_BASE:
681 case VMX_VMCS_GUEST_DS_BASE:
682 case VMX_VMCS_GUEST_FS_BASE:
683 case VMX_VMCS_GUEST_GS_BASE:
684 case VMX_VMCS_GUEST_LDTR_BASE:
685 case VMX_VMCS_GUEST_TR_BASE:
686 case VMX_VMCS_GUEST_GDTR_BASE:
687 case VMX_VMCS_GUEST_IDTR_BASE:
688 case VMX_VMCS_GUEST_DR7:
689 case VMX_VMCS_GUEST_RSP:
690 case VMX_VMCS_GUEST_RIP:
691 case VMX_VMCS_GUEST_RFLAGS:
692 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
693 case VMX_VMCS_GUEST_SYSENTER_ESP:
694 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
695
696 /* Host-state fields. */
697 case VMX_VMCS_HOST_CR0:
698 case VMX_VMCS_HOST_CR3:
699 case VMX_VMCS_HOST_CR4:
700 case VMX_VMCS_HOST_FS_BASE:
701 case VMX_VMCS_HOST_GS_BASE:
702 case VMX_VMCS_HOST_TR_BASE:
703 case VMX_VMCS_HOST_GDTR_BASE:
704 case VMX_VMCS_HOST_IDTR_BASE:
705 case VMX_VMCS_HOST_SYSENTER_ESP:
706 case VMX_VMCS_HOST_SYSENTER_EIP:
707 case VMX_VMCS_HOST_RSP:
708 case VMX_VMCS_HOST_RIP: return true;
709 }
710
711 return false;
712}
713
714
715/**
716 * Gets a host selector from the VMCS.
717 *
718 * @param pVmcs Pointer to the virtual VMCS.
719 * @param iSelReg The index of the segment register (X86_SREG_XXX).
720 */
721DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
722{
723 Assert(iSegReg < X86_SREG_COUNT);
724 RTSEL HostSel;
725 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
726 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
727 uint8_t const uWidthType = (uWidth << 2) | uType;
728 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
729 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
730 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
731 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
732 uint8_t const *pbField = pbVmcs + offField;
733 HostSel = *(uint16_t *)pbField;
734 return HostSel;
735}
736
737
738/**
739 * Sets a guest segment register in the VMCS.
740 *
741 * @param pVmcs Pointer to the virtual VMCS.
742 * @param iSegReg The index of the segment register (X86_SREG_XXX).
743 * @param pSelReg Pointer to the segment register.
744 */
745IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
746{
747 Assert(pSelReg);
748 Assert(iSegReg < X86_SREG_COUNT);
749
750 /* Selector. */
751 {
752 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
753 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
754 uint8_t const uWidthType = (uWidth << 2) | uType;
755 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
756 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
757 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
758 uint8_t *pbVmcs = (uint8_t *)pVmcs;
759 uint8_t *pbField = pbVmcs + offField;
760 *(uint16_t *)pbField = pSelReg->Sel;
761 }
762
763 /* Limit. */
764 {
765 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
766 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
767 uint8_t const uWidthType = (uWidth << 2) | uType;
768 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
769 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
770 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
771 uint8_t *pbVmcs = (uint8_t *)pVmcs;
772 uint8_t *pbField = pbVmcs + offField;
773 *(uint32_t *)pbField = pSelReg->u32Limit;
774 }
775
776 /* Base. */
777 {
778 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
779 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
780 uint8_t const uWidthType = (uWidth << 2) | uType;
781 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
782 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
783 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
784 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
785 uint8_t const *pbField = pbVmcs + offField;
786 *(uint64_t *)pbField = pSelReg->u64Base;
787 }
788
789 /* Attributes. */
790 {
791 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
792 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
793 | X86DESCATTR_UNUSABLE;
794 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
795 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
796 uint8_t const uWidthType = (uWidth << 2) | uType;
797 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
798 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
799 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
800 uint8_t *pbVmcs = (uint8_t *)pVmcs;
801 uint8_t *pbField = pbVmcs + offField;
802 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
803 }
804}
805
806
807/**
808 * Gets a guest segment register from the VMCS.
809 *
810 * @returns VBox status code.
811 * @param pVmcs Pointer to the virtual VMCS.
812 * @param iSegReg The index of the segment register (X86_SREG_XXX).
813 * @param pSelReg Where to store the segment register (only updated when
814 * VINF_SUCCESS is returned).
815 *
816 * @remarks Warning! This does not validate the contents of the retrieved segment
817 * register.
818 */
819IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
820{
821 Assert(pSelReg);
822 Assert(iSegReg < X86_SREG_COUNT);
823
824 /* Selector. */
825 uint16_t u16Sel;
826 {
827 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
828 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
829 uint8_t const uWidthType = (uWidth << 2) | uType;
830 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
831 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
832 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
833 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
834 uint8_t const *pbField = pbVmcs + offField;
835 u16Sel = *(uint16_t *)pbField;
836 }
837
838 /* Limit. */
839 uint32_t u32Limit;
840 {
841 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
842 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
843 uint8_t const uWidthType = (uWidth << 2) | uType;
844 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
845 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
846 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
847 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
848 uint8_t const *pbField = pbVmcs + offField;
849 u32Limit = *(uint32_t *)pbField;
850 }
851
852 /* Base. */
853 uint64_t u64Base;
854 {
855 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
856 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
857 uint8_t const uWidthType = (uWidth << 2) | uType;
858 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
859 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
860 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
861 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
862 uint8_t const *pbField = pbVmcs + offField;
863 u64Base = *(uint64_t *)pbField;
864 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
865 }
866
867 /* Attributes. */
868 uint32_t u32Attr;
869 {
870 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
871 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
872 uint8_t const uWidthType = (uWidth << 2) | uType;
873 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
874 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
875 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
876 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
877 uint8_t const *pbField = pbVmcs + offField;
878 u32Attr = *(uint32_t *)pbField;
879 }
880
881 pSelReg->Sel = u16Sel;
882 pSelReg->ValidSel = u16Sel;
883 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
884 pSelReg->u32Limit = u32Limit;
885 pSelReg->u64Base = u64Base;
886 pSelReg->Attr.u = u32Attr;
887 return VINF_SUCCESS;
888}
889
890
891/**
892 * Gets a CR3 target value from the VMCS.
893 *
894 * @returns VBox status code.
895 * @param pVmcs Pointer to the virtual VMCS.
896 * @param idxCr3Target The index of the CR3-target value to retrieve.
897 * @param puValue Where to store the CR3-target value.
898 */
899IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
900{
901 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
902 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
903 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
904 uint8_t const uWidthType = (uWidth << 2) | uType;
905 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
906 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
907 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
908 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
909 uint8_t const *pbField = pbVmcs + offField;
910 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
911 return uCr3TargetValue;
912}
913
914
915/**
916 * Converts an IEM exception event type to a VMX event type.
917 *
918 * @returns The VMX event type.
919 * @param uVector The interrupt / exception vector.
920 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
921 */
922DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
923{
924 /* Paranoia (callers may use these interchangeably). */
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
930 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
931 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
932 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
933 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
934 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
935 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
936 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
937
938 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
939 {
940 if (uVector == X86_XCPT_NMI)
941 return VMX_EXIT_INT_INFO_TYPE_NMI;
942 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
943 }
944
945 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
946 {
947 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
948 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
949 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
950 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
951 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
952 }
953
954 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
955 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
956}
957
958
959/**
960 * Sets the VM-exit qualification VMCS field.
961 *
962 * @param pVCpu The cross context virtual CPU structure.
963 * @param uExitQual The VM-exit qualification.
964 */
965DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
966{
967 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
968 pVmcs->u64RoExitQual.u = uExitQual;
969}
970
971
972/**
973 * Sets the VM-exit interruption information field.
974 *
975 * @param pVCpu The cross context virtual CPU structure.
976 * @param uExitQual The VM-exit interruption information.
977 */
978DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
979{
980 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
981 pVmcs->u32RoExitIntInfo = uExitIntInfo;
982}
983
984
985/**
986 * Sets the VM-exit interruption error code.
987 *
988 * @param pVCpu The cross context virtual CPU structure.
989 * @param uErrCode The error code.
990 */
991DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
992{
993 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
994 pVmcs->u32RoExitIntErrCode = uErrCode;
995}
996
997
998/**
999 * Sets the IDT-vectoring information field.
1000 *
1001 * @param pVCpu The cross context virtual CPU structure.
1002 * @param uIdtVectorInfo The IDT-vectoring information.
1003 */
1004DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1005{
1006 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1007 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1008}
1009
1010
1011/**
1012 * Sets the IDT-vectoring error code field.
1013 *
1014 * @param pVCpu The cross context virtual CPU structure.
1015 * @param uErrCode The error code.
1016 */
1017DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1018{
1019 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1020 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1021}
1022
1023
1024/**
1025 * Sets the VM-exit guest-linear address VMCS field.
1026 *
1027 * @param pVCpu The cross context virtual CPU structure.
1028 * @param uGuestLinearAddr The VM-exit guest-linear address.
1029 */
1030DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1031{
1032 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1033 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1034}
1035
1036
1037/**
1038 * Sets the VM-exit guest-physical address VMCS field.
1039 *
1040 * @param pVCpu The cross context virtual CPU structure.
1041 * @param uGuestPhysAddr The VM-exit guest-physical address.
1042 */
1043DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1044{
1045 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1046 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1047}
1048
1049
1050/**
1051 * Sets the VM-exit instruction length VMCS field.
1052 *
1053 * @param pVCpu The cross context virtual CPU structure.
1054 * @param cbInstr The VM-exit instruction length in bytes.
1055 *
1056 * @remarks Callers may clear this field to 0. Hence, this function does not check
1057 * the validity of the instruction length.
1058 */
1059DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1060{
1061 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1062 pVmcs->u32RoExitInstrLen = cbInstr;
1063}
1064
1065
1066/**
1067 * Sets the VM-exit instruction info. VMCS field.
1068 *
1069 * @param pVCpu The cross context virtual CPU structure.
1070 * @param uExitInstrInfo The VM-exit instruction information.
1071 */
1072DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1073{
1074 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1075 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1076}
1077
1078
1079/**
1080 * Implements VMSucceed for VMX instruction success.
1081 *
1082 * @param pVCpu The cross context virtual CPU structure.
1083 */
1084DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1085{
1086 return CPUMSetGuestVmxVmSucceed(IEM_GET_CTX(pVCpu));
1087}
1088
1089
1090/**
1091 * Implements VMFailInvalid for VMX instruction failure.
1092 *
1093 * @param pVCpu The cross context virtual CPU structure.
1094 */
1095DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1096{
1097 return CPUMSetGuestVmxVmFailInvalid(IEM_GET_CTX(pVCpu));
1098}
1099
1100
1101/**
1102 * Implements VMFailValid for VMX instruction failure.
1103 *
1104 * @param pVCpu The cross context virtual CPU structure.
1105 * @param enmInsErr The VM instruction error.
1106 */
1107DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1108{
1109 return CPUMSetGuestVmxVmFailValid(IEM_GET_CTX(pVCpu), enmInsErr);
1110}
1111
1112
1113/**
1114 * Implements VMFail for VMX instruction failure.
1115 *
1116 * @param pVCpu The cross context virtual CPU structure.
1117 * @param enmInsErr The VM instruction error.
1118 */
1119DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1120{
1121 return CPUMSetGuestVmxVmFail(IEM_GET_CTX(pVCpu), enmInsErr);
1122}
1123
1124
1125/**
1126 * Checks if the given auto-load/store MSR area count is valid for the
1127 * implementation.
1128 *
1129 * @returns @c true if it's within the valid limit, @c false otherwise.
1130 * @param pVCpu The cross context virtual CPU structure.
1131 * @param uMsrCount The MSR area count to check.
1132 */
1133DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1134{
1135 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1136 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1137 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1138 if (uMsrCount <= cMaxSupportedMsrs)
1139 return true;
1140 return false;
1141}
1142
1143
1144/**
1145 * Flushes the current VMCS contents back to guest memory.
1146 *
1147 * @returns VBox status code.
1148 * @param pVCpu The cross context virtual CPU structure.
1149 */
1150DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1151{
1152 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1153 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1154 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1155 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1156 return rc;
1157}
1158
1159
1160/**
1161 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1162 *
1163 * @param pVCpu The cross context virtual CPU structure.
1164 */
1165DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1166{
1167 iemVmxVmSucceed(pVCpu);
1168 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1169}
1170
1171
1172/**
1173 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1174 * nested-guest.
1175 *
1176 * @param iSegReg The segment index (X86_SREG_XXX).
1177 */
1178IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1179{
1180 switch (iSegReg)
1181 {
1182 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1183 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1184 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1185 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1186 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1187 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1188 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1189 }
1190}
1191
1192
1193/**
1194 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1195 * nested-guest that is in Virtual-8086 mode.
1196 *
1197 * @param iSegReg The segment index (X86_SREG_XXX).
1198 */
1199IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1200{
1201 switch (iSegReg)
1202 {
1203 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1204 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1205 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1206 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1207 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1208 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1209 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1210 }
1211}
1212
1213
1214/**
1215 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1216 * nested-guest that is in Virtual-8086 mode.
1217 *
1218 * @param iSegReg The segment index (X86_SREG_XXX).
1219 */
1220IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1221{
1222 switch (iSegReg)
1223 {
1224 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1225 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1226 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1227 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1228 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1229 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1230 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1231 }
1232}
1233
1234
1235/**
1236 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1237 * nested-guest that is in Virtual-8086 mode.
1238 *
1239 * @param iSegReg The segment index (X86_SREG_XXX).
1240 */
1241IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1242{
1243 switch (iSegReg)
1244 {
1245 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1246 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1247 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1248 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1249 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1250 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1251 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1252 }
1253}
1254
1255
1256/**
1257 * Gets the instruction diagnostic for segment attributes reserved bits failure
1258 * during VM-entry of a nested-guest.
1259 *
1260 * @param iSegReg The segment index (X86_SREG_XXX).
1261 */
1262IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1263{
1264 switch (iSegReg)
1265 {
1266 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1267 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1268 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1269 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1270 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1271 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1272 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1273 }
1274}
1275
1276
1277/**
1278 * Gets the instruction diagnostic for segment attributes descriptor-type
1279 * (code/segment or system) failure during VM-entry of a nested-guest.
1280 *
1281 * @param iSegReg The segment index (X86_SREG_XXX).
1282 */
1283IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1284{
1285 switch (iSegReg)
1286 {
1287 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1288 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1289 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1290 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1291 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1292 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1293 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1294 }
1295}
1296
1297
1298/**
1299 * Gets the instruction diagnostic for segment attributes descriptor-type
1300 * (code/segment or system) failure during VM-entry of a nested-guest.
1301 *
1302 * @param iSegReg The segment index (X86_SREG_XXX).
1303 */
1304IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1305{
1306 switch (iSegReg)
1307 {
1308 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1309 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1310 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1311 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1312 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1313 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1314 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1315 }
1316}
1317
1318
1319/**
1320 * Gets the instruction diagnostic for segment attribute granularity failure during
1321 * VM-entry of a nested-guest.
1322 *
1323 * @param iSegReg The segment index (X86_SREG_XXX).
1324 */
1325IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1326{
1327 switch (iSegReg)
1328 {
1329 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1330 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1331 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1332 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1333 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1334 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1335 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1336 }
1337}
1338
1339/**
1340 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1341 * VM-entry of a nested-guest.
1342 *
1343 * @param iSegReg The segment index (X86_SREG_XXX).
1344 */
1345IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1346{
1347 switch (iSegReg)
1348 {
1349 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1350 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1351 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1352 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1353 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1354 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1355 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1356 }
1357}
1358
1359
1360/**
1361 * Gets the instruction diagnostic for segment attribute type accessed failure
1362 * during VM-entry of a nested-guest.
1363 *
1364 * @param iSegReg The segment index (X86_SREG_XXX).
1365 */
1366IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1367{
1368 switch (iSegReg)
1369 {
1370 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1371 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1372 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1373 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1374 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1375 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1376 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1377 }
1378}
1379
1380
1381/**
1382 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1383 * failure during VM-entry of a nested-guest.
1384 *
1385 * @param iSegReg The PDPTE entry index.
1386 */
1387IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1388{
1389 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1390 switch (iPdpte)
1391 {
1392 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1393 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1394 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1395 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1396 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1397 }
1398}
1399
1400
1401/**
1402 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1403 * failure during VM-exit of a nested-guest.
1404 *
1405 * @param iSegReg The PDPTE entry index.
1406 */
1407IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1408{
1409 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1410 switch (iPdpte)
1411 {
1412 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1413 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1414 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1415 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1416 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1417 }
1418}
1419
1420
1421/**
1422 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1423 * mask and the read-shadow (CR0/CR4 read).
1424 *
1425 * @returns The masked CR0/CR4.
1426 * @param pVCpu The cross context virtual CPU structure.
1427 * @param iCrReg The control register (either CR0 or CR4).
1428 * @param uGuestCrX The current guest CR0 or guest CR4.
1429 */
1430IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1431{
1432 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1433 Assert(iCrReg == 0 || iCrReg == 4);
1434
1435 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1436 Assert(pVmcs);
1437
1438 /*
1439 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1440 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1441 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1442 *
1443 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1444 */
1445 uint64_t fGstHostMask;
1446 uint64_t fReadShadow;
1447 if (iCrReg == 0)
1448 {
1449 fGstHostMask = pVmcs->u64Cr0Mask.u;
1450 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1451 }
1452 else
1453 {
1454 fGstHostMask = pVmcs->u64Cr4Mask.u;
1455 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1456 }
1457
1458 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1459 return fMaskedCrX;
1460}
1461
1462
1463/**
1464 * Saves the guest control registers, debug registers and some MSRs are part of
1465 * VM-exit.
1466 *
1467 * @param pVCpu The cross context virtual CPU structure.
1468 */
1469IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1470{
1471 /*
1472 * Saves the guest control registers, debug registers and some MSRs.
1473 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1474 */
1475 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1476
1477 /* Save control registers. */
1478 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1479 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1480 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1481
1482 /* Save SYSENTER CS, ESP, EIP. */
1483 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1484 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1485 {
1486 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1487 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1488 }
1489 else
1490 {
1491 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1492 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1493 }
1494
1495 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1496 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1497 {
1498 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1499 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1500 }
1501
1502 /* Save PAT MSR. */
1503 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1504 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1505
1506 /* Save EFER MSR. */
1507 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1508 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1509
1510 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1511 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1512
1513 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1514}
1515
1516
1517/**
1518 * Saves the guest force-flags in preparation of entering the nested-guest.
1519 *
1520 * @param pVCpu The cross context virtual CPU structure.
1521 */
1522IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1523{
1524 /* We shouldn't be called multiple times during VM-entry. */
1525 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1526
1527 /* MTF should not be set outside VMX non-root mode. */
1528 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1529
1530 /*
1531 * Preserve the required force-flags.
1532 *
1533 * We cache and clear force-flags that would affect the execution of the
1534 * nested-guest. Cached flags are then restored while returning to the guest
1535 * if necessary.
1536 *
1537 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1538 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1539 * instruction. Interrupt inhibition for any nested-guest instruction
1540 * is supplied by the guest-interruptibility state VMCS field and will
1541 * be set up as part of loading the guest state.
1542 *
1543 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1544 * successful VM-entry (due to invalid guest-state) need to continue
1545 * blocking NMIs if it was in effect before VM-entry.
1546 *
1547 * - MTF need not be preserved as it's used only in VMX non-root mode and
1548 * is supplied through the VM-execution controls.
1549 *
1550 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1551 * we will be able to generate interrupts that may cause VM-exits for
1552 * the nested-guest.
1553 */
1554 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1555}
1556
1557
1558/**
1559 * Restores the guest force-flags in preparation of exiting the nested-guest.
1560 *
1561 * @param pVCpu The cross context virtual CPU structure.
1562 */
1563IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1564{
1565 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1566 {
1567 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1568 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1569 }
1570}
1571
1572
1573/**
1574 * Perform a VMX transition updated PGM, IEM and CPUM.
1575 *
1576 * @param pVCpu The cross context virtual CPU structure.
1577 */
1578IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1579{
1580 /*
1581 * Inform PGM about paging mode changes.
1582 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1583 * see comment in iemMemPageTranslateAndCheckAccess().
1584 */
1585 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1586# ifdef IN_RING3
1587 Assert(rc != VINF_PGM_CHANGE_MODE);
1588# endif
1589 AssertRCReturn(rc, rc);
1590
1591 /* Inform CPUM (recompiler), can later be removed. */
1592 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1593
1594 /*
1595 * Flush the TLB with new CR3. This is required in case the PGM mode change
1596 * above doesn't actually change anything.
1597 */
1598 if (rc == VINF_SUCCESS)
1599 {
1600 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1601 AssertRCReturn(rc, rc);
1602 }
1603
1604 /* Re-initialize IEM cache/state after the drastic mode switch. */
1605 iemReInitExec(pVCpu);
1606 return rc;
1607}
1608
1609
1610/**
1611 * Calculates the current VMX-preemption timer value.
1612 *
1613 * @param pVCpu The cross context virtual CPU structure.
1614 */
1615IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1616{
1617 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1618 Assert(pVmcs);
1619
1620 /*
1621 * Assume the following:
1622 * PreemptTimerShift = 5
1623 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1624 * EntryTick = 50000 (TSC at time of VM-entry)
1625 *
1626 * CurTick Delta PreemptTimerVal
1627 * ----------------------------------
1628 * 60000 10000 2
1629 * 80000 30000 1
1630 * 90000 40000 0 -> VM-exit.
1631 *
1632 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1633 * The saved VMX-preemption timer value is calculated as follows:
1634 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1635 * E.g.:
1636 * Delta = 10000
1637 * Tmp = 10000 / (2 * 10000) = 0.5
1638 * NewPt = 2 - 0.5 = 2
1639 * Delta = 30000
1640 * Tmp = 30000 / (2 * 10000) = 1.5
1641 * NewPt = 2 - 1.5 = 1
1642 * Delta = 40000
1643 * Tmp = 40000 / 20000 = 2
1644 * NewPt = 2 - 2 = 0
1645 */
1646 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1647 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1648 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1649 uint64_t const uDelta = uCurTick - uEntryTick;
1650 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1651 uint32_t const uPreemptTimer = uVmcsPreemptVal
1652 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1653 return uPreemptTimer;
1654}
1655
1656
1657/**
1658 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1659 *
1660 * @param pVCpu The cross context virtual CPU structure.
1661 */
1662IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1663{
1664 /*
1665 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1666 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1667 */
1668 /* CS, SS, ES, DS, FS, GS. */
1669 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1670 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1673 if (!pSelReg->Attr.n.u1Unusable)
1674 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1675 else
1676 {
1677 /*
1678 * For unusable segments the attributes are undefined except for CS and SS.
1679 * For the rest we don't bother preserving anything but the unusable bit.
1680 */
1681 switch (iSegReg)
1682 {
1683 case X86_SREG_CS:
1684 pVmcs->GuestCs = pSelReg->Sel;
1685 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1686 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1687 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1688 | X86DESCATTR_UNUSABLE);
1689 break;
1690
1691 case X86_SREG_SS:
1692 pVmcs->GuestSs = pSelReg->Sel;
1693 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1694 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1695 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1696 break;
1697
1698 case X86_SREG_DS:
1699 pVmcs->GuestDs = pSelReg->Sel;
1700 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1701 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1702 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1703 break;
1704
1705 case X86_SREG_ES:
1706 pVmcs->GuestEs = pSelReg->Sel;
1707 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1708 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1709 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1710 break;
1711
1712 case X86_SREG_FS:
1713 pVmcs->GuestFs = pSelReg->Sel;
1714 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1715 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1716 break;
1717
1718 case X86_SREG_GS:
1719 pVmcs->GuestGs = pSelReg->Sel;
1720 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1721 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1722 break;
1723 }
1724 }
1725 }
1726
1727 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1728 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1729 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1730 | X86DESCATTR_UNUSABLE;
1731 /* LDTR. */
1732 {
1733 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1734 pVmcs->GuestLdtr = pSelReg->Sel;
1735 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1736 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1737 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1738 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1739 }
1740
1741 /* TR. */
1742 {
1743 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1744 pVmcs->GuestTr = pSelReg->Sel;
1745 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1746 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1747 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1748 }
1749
1750 /* GDTR. */
1751 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1752 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1753
1754 /* IDTR. */
1755 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1756 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1757}
1758
1759
1760/**
1761 * Saves guest non-register state as part of VM-exit.
1762 *
1763 * @param pVCpu The cross context virtual CPU structure.
1764 * @param uExitReason The VM-exit reason.
1765 */
1766IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1767{
1768 /*
1769 * Save guest non-register state.
1770 * See Intel spec. 27.3.4 "Saving Non-Register State".
1771 */
1772 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1773
1774 /*
1775 * Activity state.
1776 * Most VM-exits will occur in the active state. However, if the first instruction
1777 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1778 * the VM-exit will be from the HLT activity state.
1779 *
1780 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1781 */
1782 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1783 * not? */
1784 EMSTATE const enmActivityState = EMGetState(pVCpu);
1785 switch (enmActivityState)
1786 {
1787 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1788 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1789 }
1790
1791 /*
1792 * Interruptibility-state.
1793 */
1794 /* NMI. */
1795 pVmcs->u32GuestIntrState = 0;
1796 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1797 {
1798 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1799 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1800 }
1801 else
1802 {
1803 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1804 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1805 }
1806
1807 /* Blocking-by-STI. */
1808 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1809 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1810 {
1811 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1812 * currently. */
1813 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1814 }
1815 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1816
1817 /*
1818 * Pending debug exceptions.
1819 */
1820 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1821 && uExitReason != VMX_EXIT_SMI
1822 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1823 && !HMVmxIsVmexitTrapLike(uExitReason))
1824 {
1825 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1826 * block-by-MovSS is in effect. */
1827 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1828 }
1829 else
1830 {
1831 /*
1832 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1833 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1834 *
1835 * See Intel spec. 24.4.2 "Guest Non-Register State".
1836 */
1837 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1838 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1839 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1840 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1841 if (fPendingDbgMask & fBpHitMask)
1842 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1843 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1844 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1845 }
1846
1847 /*
1848 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1849 *
1850 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1851 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1852 */
1853 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1854 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1855 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1856
1857 /* PDPTEs. */
1858 /* We don't support EPT yet. */
1859 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1860 pVmcs->u64GuestPdpte0.u = 0;
1861 pVmcs->u64GuestPdpte1.u = 0;
1862 pVmcs->u64GuestPdpte2.u = 0;
1863 pVmcs->u64GuestPdpte3.u = 0;
1864}
1865
1866
1867/**
1868 * Saves the guest-state as part of VM-exit.
1869 *
1870 * @returns VBox status code.
1871 * @param pVCpu The cross context virtual CPU structure.
1872 * @param uExitReason The VM-exit reason.
1873 */
1874IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1875{
1876 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1877 Assert(pVmcs);
1878
1879 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1880 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1881
1882 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1883 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1884 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1885
1886 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1887}
1888
1889
1890/**
1891 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1892 *
1893 * @returns VBox status code.
1894 * @param pVCpu The cross context virtual CPU structure.
1895 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1896 */
1897IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1898{
1899 /*
1900 * Save guest MSRs.
1901 * See Intel spec. 27.4 "Saving MSRs".
1902 */
1903 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1904 const char *const pszFailure = "VMX-abort";
1905
1906 /*
1907 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1908 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1909 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1910 */
1911 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1912 if (!cMsrs)
1913 return VINF_SUCCESS;
1914
1915 /*
1916 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1917 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1918 * implementation causes a VMX-abort followed by a triple-fault.
1919 */
1920 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1921 if (fIsMsrCountValid)
1922 { /* likely */ }
1923 else
1924 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1925
1926 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1927 Assert(pMsr);
1928 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1929 {
1930 if ( !pMsr->u32Reserved
1931 && pMsr->u32Msr != MSR_IA32_SMBASE
1932 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1933 {
1934 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1935 if (rcStrict == VINF_SUCCESS)
1936 continue;
1937
1938 /*
1939 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1940 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1941 * recording the MSR index in the auxiliary info. field and indicated further by our
1942 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1943 * if possible, or come up with a better, generic solution.
1944 */
1945 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1946 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1947 ? kVmxVDiag_Vmexit_MsrStoreRing3
1948 : kVmxVDiag_Vmexit_MsrStore;
1949 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1950 }
1951 else
1952 {
1953 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1955 }
1956 }
1957
1958 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1959 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea,
1960 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), cMsrs * sizeof(VMXAUTOMSR));
1961 if (RT_SUCCESS(rc))
1962 { /* likely */ }
1963 else
1964 {
1965 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1966 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1967 }
1968
1969 NOREF(uExitReason);
1970 NOREF(pszFailure);
1971 return VINF_SUCCESS;
1972}
1973
1974
1975/**
1976 * Performs a VMX abort (due to an fatal error during VM-exit).
1977 *
1978 * @returns Strict VBox status code.
1979 * @param pVCpu The cross context virtual CPU structure.
1980 * @param enmAbort The VMX abort reason.
1981 */
1982IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1983{
1984 /*
1985 * Perform the VMX abort.
1986 * See Intel spec. 27.7 "VMX Aborts".
1987 */
1988 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1989
1990 /* We don't support SMX yet. */
1991 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1992 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1993 {
1994 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1995 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1996 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1997 }
1998
1999 return VINF_EM_TRIPLE_FAULT;
2000}
2001
2002
2003/**
2004 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2005 *
2006 * @param pVCpu The cross context virtual CPU structure.
2007 */
2008IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2009{
2010 /*
2011 * Load host control registers, debug registers and MSRs.
2012 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2013 */
2014 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2015 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2016
2017 /* CR0. */
2018 {
2019 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2020 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2021 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2022 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2023 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2024 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2025 CPUMSetGuestCR0(pVCpu, uValidCr0);
2026 }
2027
2028 /* CR4. */
2029 {
2030 /* CR4 MB1 bits are not modified. */
2031 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2032 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2033 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2034 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2035 if (fHostInLongMode)
2036 uValidCr4 |= X86_CR4_PAE;
2037 else
2038 uValidCr4 &= ~X86_CR4_PCIDE;
2039 CPUMSetGuestCR4(pVCpu, uValidCr4);
2040 }
2041
2042 /* CR3 (host value validated while checking host-state during VM-entry). */
2043 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2044
2045 /* DR7. */
2046 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2047
2048 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2049
2050 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2051 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2052 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2053 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2054
2055 /* FS, GS bases are loaded later while we load host segment registers. */
2056
2057 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2058 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2059 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2060 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2061 {
2062 if (fHostInLongMode)
2063 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2064 else
2065 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2066 }
2067
2068 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2069
2070 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2071 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2072 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2073
2074 /* We don't support IA32_BNDCFGS MSR yet. */
2075}
2076
2077
2078/**
2079 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2080 *
2081 * @param pVCpu The cross context virtual CPU structure.
2082 */
2083IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2084{
2085 /*
2086 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2087 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2088 *
2089 * Warning! Be careful to not touch fields that are reserved by VT-x,
2090 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2091 */
2092 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2093 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2094
2095 /* CS, SS, ES, DS, FS, GS. */
2096 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2097 {
2098 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2099 bool const fUnusable = RT_BOOL(HostSel == 0);
2100 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2101
2102 /* Selector. */
2103 pSelReg->Sel = HostSel;
2104 pSelReg->ValidSel = HostSel;
2105 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2106
2107 /* Limit. */
2108 pSelReg->u32Limit = 0xffffffff;
2109
2110 /* Base. */
2111 pSelReg->u64Base = 0;
2112
2113 /* Attributes. */
2114 if (iSegReg == X86_SREG_CS)
2115 {
2116 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2117 pSelReg->Attr.n.u1DescType = 1;
2118 pSelReg->Attr.n.u2Dpl = 0;
2119 pSelReg->Attr.n.u1Present = 1;
2120 pSelReg->Attr.n.u1Long = fHostInLongMode;
2121 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2122 pSelReg->Attr.n.u1Granularity = 1;
2123 Assert(!pSelReg->Attr.n.u1Unusable);
2124 Assert(!fUnusable);
2125 }
2126 else
2127 {
2128 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2129 pSelReg->Attr.n.u1DescType = 1;
2130 pSelReg->Attr.n.u2Dpl = 0;
2131 pSelReg->Attr.n.u1Present = 1;
2132 pSelReg->Attr.n.u1DefBig = 1;
2133 pSelReg->Attr.n.u1Granularity = 1;
2134 pSelReg->Attr.n.u1Unusable = fUnusable;
2135 }
2136 }
2137
2138 /* FS base. */
2139 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2140 || fHostInLongMode)
2141 {
2142 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2143 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2144 }
2145
2146 /* GS base. */
2147 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2148 || fHostInLongMode)
2149 {
2150 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2151 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2152 }
2153
2154 /* TR. */
2155 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2156 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2157 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2158 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2159 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2160 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2161 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2162 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2163 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2164 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2165 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2166 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2167 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2168
2169 /* LDTR (Warning! do not touch the base and limits here). */
2170 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2171 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2172 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2173 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2174
2175 /* GDTR. */
2176 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2177 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2178 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2179
2180 /* IDTR.*/
2181 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2182 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2183 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2184}
2185
2186
2187/**
2188 * Checks host PDPTes as part of VM-exit.
2189 *
2190 * @param pVCpu The cross context virtual CPU structure.
2191 * @param uExitReason The VM-exit reason (for logging purposes).
2192 */
2193IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2194{
2195 /*
2196 * Check host PDPTEs.
2197 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2198 */
2199 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2200 const char *const pszFailure = "VMX-abort";
2201 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2202
2203 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2204 && !fHostInLongMode)
2205 {
2206 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2207 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2208 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2209 if (RT_SUCCESS(rc))
2210 {
2211 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2212 {
2213 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2214 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2215 { /* likely */ }
2216 else
2217 {
2218 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2219 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2220 }
2221 }
2222 }
2223 else
2224 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2225 }
2226
2227 NOREF(pszFailure);
2228 NOREF(uExitReason);
2229 return VINF_SUCCESS;
2230}
2231
2232
2233/**
2234 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2235 *
2236 * @returns VBox status code.
2237 * @param pVCpu The cross context virtual CPU structure.
2238 * @param pszInstr The VMX instruction name (for logging purposes).
2239 */
2240IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2241{
2242 /*
2243 * Load host MSRs.
2244 * See Intel spec. 27.6 "Loading MSRs".
2245 */
2246 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2247 const char *const pszFailure = "VMX-abort";
2248
2249 /*
2250 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2251 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2252 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2253 */
2254 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2255 if (!cMsrs)
2256 return VINF_SUCCESS;
2257
2258 /*
2259 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2260 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2261 * implementation causes a VMX-abort followed by a triple-fault.
2262 */
2263 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2264 if (fIsMsrCountValid)
2265 { /* likely */ }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2268
2269 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2270 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2271 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2272 if (RT_SUCCESS(rc))
2273 {
2274 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2275 Assert(pMsr);
2276 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2277 {
2278 if ( !pMsr->u32Reserved
2279 && pMsr->u32Msr != MSR_K8_FS_BASE
2280 && pMsr->u32Msr != MSR_K8_GS_BASE
2281 && pMsr->u32Msr != MSR_K6_EFER
2282 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2283 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2284 {
2285 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2286 if (rcStrict == VINF_SUCCESS)
2287 continue;
2288
2289 /*
2290 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2291 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2292 * recording the MSR index in the auxiliary info. field and indicated further by our
2293 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2294 * if possible, or come up with a better, generic solution.
2295 */
2296 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2297 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2298 ? kVmxVDiag_Vmexit_MsrLoadRing3
2299 : kVmxVDiag_Vmexit_MsrLoad;
2300 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2301 }
2302 else
2303 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2304 }
2305 }
2306 else
2307 {
2308 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2309 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2310 }
2311
2312 NOREF(uExitReason);
2313 NOREF(pszFailure);
2314 return VINF_SUCCESS;
2315}
2316
2317
2318/**
2319 * Loads the host state as part of VM-exit.
2320 *
2321 * @returns Strict VBox status code.
2322 * @param pVCpu The cross context virtual CPU structure.
2323 * @param uExitReason The VM-exit reason (for logging purposes).
2324 */
2325IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2326{
2327 /*
2328 * Load host state.
2329 * See Intel spec. 27.5 "Loading Host State".
2330 */
2331 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2332 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2333
2334 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2335 if ( CPUMIsGuestInLongMode(pVCpu)
2336 && !fHostInLongMode)
2337 {
2338 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2339 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2340 }
2341
2342 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2343 iemVmxVmexitLoadHostSegRegs(pVCpu);
2344
2345 /*
2346 * Load host RIP, RSP and RFLAGS.
2347 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2348 */
2349 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2350 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2351 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2352
2353 /* Clear address range monitoring. */
2354 EMMonitorWaitClear(pVCpu);
2355
2356 /* Perform the VMX transition (PGM updates). */
2357 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2358 if (rcStrict == VINF_SUCCESS)
2359 {
2360 /* Check host PDPTEs (only when we've fully switched page tables_. */
2361 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2362 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2363 if (RT_FAILURE(rc))
2364 {
2365 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2366 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2367 }
2368 }
2369 else if (RT_SUCCESS(rcStrict))
2370 {
2371 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2372 uExitReason));
2373 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2374 }
2375 else
2376 {
2377 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2378 return VBOXSTRICTRC_VAL(rcStrict);
2379 }
2380
2381 Assert(rcStrict == VINF_SUCCESS);
2382
2383 /* Load MSRs from the VM-exit auto-load MSR area. */
2384 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2385 if (RT_FAILURE(rc))
2386 {
2387 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2388 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2389 }
2390 return VINF_SUCCESS;
2391}
2392
2393
2394/**
2395 * Gets VM-exit instruction information along with any displacement for an
2396 * instruction VM-exit.
2397 *
2398 * @returns The VM-exit instruction information.
2399 * @param pVCpu The cross context virtual CPU structure.
2400 * @param uExitReason The VM-exit reason.
2401 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2402 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2403 * NULL.
2404 */
2405IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2406{
2407 RTGCPTR GCPtrDisp;
2408 VMXEXITINSTRINFO ExitInstrInfo;
2409 ExitInstrInfo.u = 0;
2410
2411 /*
2412 * Get and parse the ModR/M byte from our decoded opcodes.
2413 */
2414 uint8_t bRm;
2415 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2416 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2417 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2418 {
2419 /*
2420 * ModR/M indicates register addressing.
2421 *
2422 * The primary/secondary register operands are reported in the iReg1 or iReg2
2423 * fields depending on whether it is a read/write form.
2424 */
2425 uint8_t idxReg1;
2426 uint8_t idxReg2;
2427 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2428 {
2429 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2430 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2431 }
2432 else
2433 {
2434 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2435 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2436 }
2437 ExitInstrInfo.All.u2Scaling = 0;
2438 ExitInstrInfo.All.iReg1 = idxReg1;
2439 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2440 ExitInstrInfo.All.fIsRegOperand = 1;
2441 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2442 ExitInstrInfo.All.iSegReg = 0;
2443 ExitInstrInfo.All.iIdxReg = 0;
2444 ExitInstrInfo.All.fIdxRegInvalid = 1;
2445 ExitInstrInfo.All.iBaseReg = 0;
2446 ExitInstrInfo.All.fBaseRegInvalid = 1;
2447 ExitInstrInfo.All.iReg2 = idxReg2;
2448
2449 /* Displacement not applicable for register addressing. */
2450 GCPtrDisp = 0;
2451 }
2452 else
2453 {
2454 /*
2455 * ModR/M indicates memory addressing.
2456 */
2457 uint8_t uScale = 0;
2458 bool fBaseRegValid = false;
2459 bool fIdxRegValid = false;
2460 uint8_t iBaseReg = 0;
2461 uint8_t iIdxReg = 0;
2462 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2463 {
2464 /*
2465 * Parse the ModR/M, displacement for 16-bit addressing mode.
2466 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2467 */
2468 uint16_t u16Disp = 0;
2469 uint8_t const offDisp = offModRm + sizeof(bRm);
2470 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2471 {
2472 /* Displacement without any registers. */
2473 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2474 }
2475 else
2476 {
2477 /* Register (index and base). */
2478 switch (bRm & X86_MODRM_RM_MASK)
2479 {
2480 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2481 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2482 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2483 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2484 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2485 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2486 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2487 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2488 }
2489
2490 /* Register + displacement. */
2491 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2492 {
2493 case 0: break;
2494 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2495 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2496 default:
2497 {
2498 /* Register addressing, handled at the beginning. */
2499 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2500 break;
2501 }
2502 }
2503 }
2504
2505 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2506 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2507 }
2508 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2509 {
2510 /*
2511 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2512 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2513 */
2514 uint32_t u32Disp = 0;
2515 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2516 {
2517 /* Displacement without any registers. */
2518 uint8_t const offDisp = offModRm + sizeof(bRm);
2519 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2520 }
2521 else
2522 {
2523 /* Register (and perhaps scale, index and base). */
2524 uint8_t offDisp = offModRm + sizeof(bRm);
2525 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2526 if (iBaseReg == 4)
2527 {
2528 /* An SIB byte follows the ModR/M byte, parse it. */
2529 uint8_t bSib;
2530 uint8_t const offSib = offModRm + sizeof(bRm);
2531 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2532
2533 /* A displacement may follow SIB, update its offset. */
2534 offDisp += sizeof(bSib);
2535
2536 /* Get the scale. */
2537 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2538
2539 /* Get the index register. */
2540 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2541 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2542
2543 /* Get the base register. */
2544 iBaseReg = bSib & X86_SIB_BASE_MASK;
2545 fBaseRegValid = true;
2546 if (iBaseReg == 5)
2547 {
2548 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2549 {
2550 /* Mod is 0 implies a 32-bit displacement with no base. */
2551 fBaseRegValid = false;
2552 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2553 }
2554 else
2555 {
2556 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2557 iBaseReg = X86_GREG_xBP;
2558 }
2559 }
2560 }
2561
2562 /* Register + displacement. */
2563 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2564 {
2565 case 0: /* Handled above */ break;
2566 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2567 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2568 default:
2569 {
2570 /* Register addressing, handled at the beginning. */
2571 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2572 break;
2573 }
2574 }
2575 }
2576
2577 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2578 }
2579 else
2580 {
2581 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2582
2583 /*
2584 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2585 * See Intel instruction spec. 2.2 "IA-32e Mode".
2586 */
2587 uint64_t u64Disp = 0;
2588 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2589 if (fRipRelativeAddr)
2590 {
2591 /*
2592 * RIP-relative addressing mode.
2593 *
2594 * The displacement is 32-bit signed implying an offset range of +/-2G.
2595 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2596 */
2597 uint8_t const offDisp = offModRm + sizeof(bRm);
2598 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2599 }
2600 else
2601 {
2602 uint8_t offDisp = offModRm + sizeof(bRm);
2603
2604 /*
2605 * Register (and perhaps scale, index and base).
2606 *
2607 * REX.B extends the most-significant bit of the base register. However, REX.B
2608 * is ignored while determining whether an SIB follows the opcode. Hence, we
2609 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2610 *
2611 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2612 */
2613 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2614 if (iBaseReg == 4)
2615 {
2616 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2617 uint8_t bSib;
2618 uint8_t const offSib = offModRm + sizeof(bRm);
2619 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2620
2621 /* Displacement may follow SIB, update its offset. */
2622 offDisp += sizeof(bSib);
2623
2624 /* Get the scale. */
2625 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2626
2627 /* Get the index. */
2628 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2629 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2630
2631 /* Get the base. */
2632 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2633 fBaseRegValid = true;
2634 if (iBaseReg == 5)
2635 {
2636 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2637 {
2638 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2639 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2640 }
2641 else
2642 {
2643 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2644 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2645 }
2646 }
2647 }
2648 iBaseReg |= pVCpu->iem.s.uRexB;
2649
2650 /* Register + displacement. */
2651 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2652 {
2653 case 0: /* Handled above */ break;
2654 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2655 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2656 default:
2657 {
2658 /* Register addressing, handled at the beginning. */
2659 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2660 break;
2661 }
2662 }
2663 }
2664
2665 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2666 }
2667
2668 /*
2669 * The primary or secondary register operand is reported in iReg2 depending
2670 * on whether the primary operand is in read/write form.
2671 */
2672 uint8_t idxReg2;
2673 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2674 {
2675 idxReg2 = bRm & X86_MODRM_RM_MASK;
2676 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2677 idxReg2 |= pVCpu->iem.s.uRexB;
2678 }
2679 else
2680 {
2681 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2682 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2683 idxReg2 |= pVCpu->iem.s.uRexReg;
2684 }
2685 ExitInstrInfo.All.u2Scaling = uScale;
2686 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2687 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2688 ExitInstrInfo.All.fIsRegOperand = 0;
2689 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2690 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2691 ExitInstrInfo.All.iIdxReg = iIdxReg;
2692 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2693 ExitInstrInfo.All.iBaseReg = iBaseReg;
2694 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2695 ExitInstrInfo.All.iReg2 = idxReg2;
2696 }
2697
2698 /*
2699 * Handle exceptions to the norm for certain instructions.
2700 * (e.g. some instructions convey an instruction identity in place of iReg2).
2701 */
2702 switch (uExitReason)
2703 {
2704 case VMX_EXIT_GDTR_IDTR_ACCESS:
2705 {
2706 Assert(VMXINSTRID_IS_VALID(uInstrId));
2707 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2708 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2709 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2710 break;
2711 }
2712
2713 case VMX_EXIT_LDTR_TR_ACCESS:
2714 {
2715 Assert(VMXINSTRID_IS_VALID(uInstrId));
2716 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2717 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2718 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2719 break;
2720 }
2721
2722 case VMX_EXIT_RDRAND:
2723 case VMX_EXIT_RDSEED:
2724 {
2725 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2726 break;
2727 }
2728 }
2729
2730 /* Update displacement and return the constructed VM-exit instruction information field. */
2731 if (pGCPtrDisp)
2732 *pGCPtrDisp = GCPtrDisp;
2733
2734 return ExitInstrInfo.u;
2735}
2736
2737
2738/**
2739 * VMX VM-exit handler.
2740 *
2741 * @returns Strict VBox status code.
2742 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2743 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2744 * triple-fault.
2745 *
2746 * @param pVCpu The cross context virtual CPU structure.
2747 * @param uExitReason The VM-exit reason.
2748 *
2749 * @remarks Make sure VM-exit qualification is updated before calling this
2750 * function!
2751 */
2752IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2753{
2754# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2755 RT_NOREF2(pVCpu, uExitReason);
2756 return VINF_EM_RAW_EMULATE_INSTR;
2757# else
2758 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2759 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2760 | CPUMCTX_EXTRN_EFER /* MSRs */
2761 | CPUMCTX_EXTRN_SYSENTER_MSRS
2762 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2763 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2764 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2765 | CPUMCTX_EXTRN_TR /* Task register */
2766 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2767 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2768
2769 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2770 Assert(pVmcs);
2771
2772 /* Ensure VM-entry interruption information valid bit isn't set. */
2773 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2774
2775 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2776 pVmcs->u32RoExitReason = uExitReason;
2777 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2778 IEM_GET_CTX(pVCpu)->cs.Sel, IEM_GET_CTX(pVCpu)->rip));
2779
2780 /*
2781 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2782 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2783 */
2784 {
2785 uint8_t uVector;
2786 uint32_t fFlags;
2787 uint32_t uErrCode;
2788 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2789 if (!fInEventDelivery)
2790 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2791 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2792 }
2793
2794 /*
2795 * Save the guest state back into the VMCS.
2796 * We only need to save the state when the VM-entry was successful.
2797 */
2798 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2799 if (!fVmentryFailed)
2800 {
2801 /*
2802 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2803 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2804 *
2805 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2806 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2807 * as guest-CPU state would not been modified. Hence for now, we do this only when
2808 * the VM-entry succeeded.
2809 */
2810 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2811 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2812 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2813 {
2814 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2815 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2816 else
2817 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2818 }
2819
2820 /*
2821 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2822 * occurs in enclave mode/SMM which we don't support yet.
2823 *
2824 * If we ever add support for it, we can pass just the lower bits to the functions
2825 * below, till then an assert should suffice.
2826 */
2827 Assert(!RT_HI_U16(uExitReason));
2828
2829 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2830 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2831 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2832 if (RT_SUCCESS(rc))
2833 { /* likely */ }
2834 else
2835 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2836
2837 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2838 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2839 }
2840 else
2841 {
2842 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2843 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2844 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2845 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2846 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2847 }
2848
2849 /*
2850 * Clear any pending VMX nested-guest force-flags.
2851 * These force-flags have no effect on guest execution and will
2852 * be re-evaluated and setup on the next nested-guest VM-entry.
2853 */
2854 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2855 | VMCPU_FF_VMX_MTF
2856 | VMCPU_FF_VMX_APIC_WRITE
2857 | VMCPU_FF_VMX_INT_WINDOW
2858 | VMCPU_FF_VMX_NMI_WINDOW);
2859
2860 /* Restore the host (outer guest) state. */
2861 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2862 if (RT_SUCCESS(rcStrict))
2863 {
2864 Assert(rcStrict == VINF_SUCCESS);
2865 rcStrict = VINF_VMX_VMEXIT;
2866 }
2867 else
2868 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2869
2870 /* We're no longer in nested-guest execution mode. */
2871 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2872
2873# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2874 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2875 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2876 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2877 if (rcSched != VINF_SUCCESS)
2878 iemSetPassUpStatus(pVCpu, rcSched);
2879# endif
2880 return VINF_SUCCESS;
2881# endif
2882}
2883
2884
2885/**
2886 * VMX VM-exit handler for VM-exits due to instruction execution.
2887 *
2888 * This is intended for instructions where the caller provides all the relevant
2889 * VM-exit information.
2890 *
2891 * @returns Strict VBox status code.
2892 * @param pVCpu The cross context virtual CPU structure.
2893 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2894 */
2895DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2896{
2897 /*
2898 * For instructions where any of the following fields are not applicable:
2899 * - VM-exit instruction info. is undefined.
2900 * - VM-exit qualification must be cleared.
2901 * - VM-exit guest-linear address is undefined.
2902 * - VM-exit guest-physical address is undefined.
2903 *
2904 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2905 * instruction execution. For VM-exits that are not due to instruction execution this
2906 * field is undefined.
2907 *
2908 * In our implementation in IEM, all undefined fields are generally cleared. However,
2909 * if the caller supplies information (from say the physical CPU directly) it is
2910 * then possible that the undefined fields are not cleared.
2911 *
2912 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2913 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2914 */
2915 Assert(pExitInfo);
2916 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2917 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2918 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2919
2920 /* Update all the relevant fields from the VM-exit instruction information struct. */
2921 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2922 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2923 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2924 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2925 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2926
2927 /* Perform the VM-exit. */
2928 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2929}
2930
2931
2932/**
2933 * VMX VM-exit handler for VM-exits due to instruction execution.
2934 *
2935 * This is intended for instructions that only provide the VM-exit instruction
2936 * length.
2937 *
2938 * @param pVCpu The cross context virtual CPU structure.
2939 * @param uExitReason The VM-exit reason.
2940 * @param cbInstr The instruction length in bytes.
2941 */
2942IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2943{
2944 VMXVEXITINFO ExitInfo;
2945 RT_ZERO(ExitInfo);
2946 ExitInfo.uReason = uExitReason;
2947 ExitInfo.cbInstr = cbInstr;
2948
2949#ifdef VBOX_STRICT
2950 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2951 switch (uExitReason)
2952 {
2953 case VMX_EXIT_INVEPT:
2954 case VMX_EXIT_INVPCID:
2955 case VMX_EXIT_LDTR_TR_ACCESS:
2956 case VMX_EXIT_GDTR_IDTR_ACCESS:
2957 case VMX_EXIT_VMCLEAR:
2958 case VMX_EXIT_VMPTRLD:
2959 case VMX_EXIT_VMPTRST:
2960 case VMX_EXIT_VMREAD:
2961 case VMX_EXIT_VMWRITE:
2962 case VMX_EXIT_VMXON:
2963 case VMX_EXIT_XRSTORS:
2964 case VMX_EXIT_XSAVES:
2965 case VMX_EXIT_RDRAND:
2966 case VMX_EXIT_RDSEED:
2967 case VMX_EXIT_IO_INSTR:
2968 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2969 break;
2970 }
2971#endif
2972
2973 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2974}
2975
2976
2977/**
2978 * VMX VM-exit handler for VM-exits due to instruction execution.
2979 *
2980 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2981 * instruction information and VM-exit qualification fields.
2982 *
2983 * @param pVCpu The cross context virtual CPU structure.
2984 * @param uExitReason The VM-exit reason.
2985 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2986 * @param cbInstr The instruction length in bytes.
2987 *
2988 * @remarks Do not use this for INS/OUTS instruction.
2989 */
2990IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2991{
2992 VMXVEXITINFO ExitInfo;
2993 RT_ZERO(ExitInfo);
2994 ExitInfo.uReason = uExitReason;
2995 ExitInfo.cbInstr = cbInstr;
2996
2997 /*
2998 * Update the VM-exit qualification field with displacement bytes.
2999 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3000 */
3001 switch (uExitReason)
3002 {
3003 case VMX_EXIT_INVEPT:
3004 case VMX_EXIT_INVPCID:
3005 case VMX_EXIT_LDTR_TR_ACCESS:
3006 case VMX_EXIT_GDTR_IDTR_ACCESS:
3007 case VMX_EXIT_VMCLEAR:
3008 case VMX_EXIT_VMPTRLD:
3009 case VMX_EXIT_VMPTRST:
3010 case VMX_EXIT_VMREAD:
3011 case VMX_EXIT_VMWRITE:
3012 case VMX_EXIT_VMXON:
3013 case VMX_EXIT_XRSTORS:
3014 case VMX_EXIT_XSAVES:
3015 case VMX_EXIT_RDRAND:
3016 case VMX_EXIT_RDSEED:
3017 {
3018 /* Construct the VM-exit instruction information. */
3019 RTGCPTR GCPtrDisp;
3020 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3021
3022 /* Update the VM-exit instruction information. */
3023 ExitInfo.InstrInfo.u = uInstrInfo;
3024
3025 /* Update the VM-exit qualification. */
3026 ExitInfo.u64Qual = GCPtrDisp;
3027 break;
3028 }
3029
3030 default:
3031 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3032 break;
3033 }
3034
3035 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3036}
3037
3038
3039/**
3040 * Checks whether an I/O instruction for the given port is intercepted (causes a
3041 * VM-exit) or not.
3042 *
3043 * @returns @c true if the instruction is intercepted, @c false otherwise.
3044 * @param pVCpu The cross context virtual CPU structure.
3045 * @param u16Port The I/O port being accessed by the instruction.
3046 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3047 */
3048IEM_STATIC bool iemVmxIsIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3049{
3050 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3051 Assert(pVmcs);
3052
3053 /*
3054 * Check whether the I/O instruction must cause a VM-exit or not.
3055 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3056 */
3057 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3058 return true;
3059
3060 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3061 {
3062 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3063 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3064 Assert(pbIoBitmapA);
3065 Assert(pbIoBitmapB);
3066 return CPUMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3067 }
3068
3069 return false;
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to INVLPG.
3075 *
3076 * @returns Strict VBox status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 * @param GCPtrPage The guest-linear address of the page being invalidated.
3079 * @param cbInstr The instruction length in bytes.
3080 */
3081IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3082{
3083 VMXVEXITINFO ExitInfo;
3084 RT_ZERO(ExitInfo);
3085 ExitInfo.uReason = VMX_EXIT_INVLPG;
3086 ExitInfo.cbInstr = cbInstr;
3087 ExitInfo.u64Qual = GCPtrPage;
3088 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3089
3090 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3091}
3092
3093
3094/**
3095 * VMX VM-exit handler for VM-exits due to LMSW.
3096 *
3097 * @returns Strict VBox status code.
3098 * @param pVCpu The cross context virtual CPU structure.
3099 * @param uGuestCr0 The current guest CR0.
3100 * @param pu16NewMsw The machine-status word specified in LMSW's source
3101 * operand. This will be updated depending on the VMX
3102 * guest/host CR0 mask if LMSW is not intercepted.
3103 * @param GCPtrEffDst The guest-linear address of the source operand in case
3104 * of a memory operand. For register operand, pass
3105 * NIL_RTGCPTR.
3106 * @param cbInstr The instruction length in bytes.
3107 */
3108IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3109 uint8_t cbInstr)
3110{
3111 /*
3112 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3113 *
3114 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3115 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3116 */
3117 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3118 Assert(pVmcs);
3119 Assert(pu16NewMsw);
3120
3121 bool fIntercept = false;
3122 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3123 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3124
3125 /*
3126 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3127 * CR0.PE case first, before the rest of the bits in the MSW.
3128 *
3129 * If CR0.PE is owned by the host and CR0.PE differs between the
3130 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3131 */
3132 if ( (fGstHostMask & X86_CR0_PE)
3133 && (*pu16NewMsw & X86_CR0_PE)
3134 && !(fReadShadow & X86_CR0_PE))
3135 fIntercept = true;
3136
3137 /*
3138 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3139 * bits differ between the MSW (source operand) and the read-shadow, we must
3140 * cause a VM-exit.
3141 */
3142 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3143 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3144 fIntercept = true;
3145
3146 if (fIntercept)
3147 {
3148 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3149
3150 VMXVEXITINFO ExitInfo;
3151 RT_ZERO(ExitInfo);
3152 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3153 ExitInfo.cbInstr = cbInstr;
3154
3155 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3156 if (fMemOperand)
3157 {
3158 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3159 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3160 }
3161
3162 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3163 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3164 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3165 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3166
3167 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3168 }
3169
3170 /*
3171 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3172 * CR0 guest/host mask must be left unmodified.
3173 *
3174 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3175 */
3176 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3177 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3178
3179 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3180}
3181
3182
3183/**
3184 * VMX VM-exit handler for VM-exits due to CLTS.
3185 *
3186 * @returns Strict VBox status code.
3187 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3188 * VM-exit but must not modify the guest CR0.TS bit.
3189 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3190 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3191 * CR0 fixed bits in VMX operation).
3192 * @param pVCpu The cross context virtual CPU structure.
3193 * @param cbInstr The instruction length in bytes.
3194 */
3195IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3196{
3197 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3198 Assert(pVmcs);
3199
3200 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3201 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3202
3203 /*
3204 * If CR0.TS is owned by the host:
3205 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3206 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3207 * CLTS instruction completes without clearing CR0.TS.
3208 *
3209 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3210 */
3211 if (fGstHostMask & X86_CR0_TS)
3212 {
3213 if (fReadShadow & X86_CR0_TS)
3214 {
3215 Log2(("clts: Guest intercept -> VM-exit\n"));
3216
3217 VMXVEXITINFO ExitInfo;
3218 RT_ZERO(ExitInfo);
3219 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3220 ExitInfo.cbInstr = cbInstr;
3221 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3222 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3223 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3224 }
3225
3226 return VINF_VMX_MODIFIES_BEHAVIOR;
3227 }
3228
3229 /*
3230 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3231 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3232 */
3233 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3234}
3235
3236
3237/**
3238 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3239 * (CR0/CR4 write).
3240 *
3241 * @returns Strict VBox status code.
3242 * @param pVCpu The cross context virtual CPU structure.
3243 * @param iCrReg The control register (either CR0 or CR4).
3244 * @param uGuestCrX The current guest CR0/CR4.
3245 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3246 * if no VM-exit is caused.
3247 * @param iGReg The general register from which the CR0/CR4 value is
3248 * being loaded.
3249 * @param cbInstr The instruction length in bytes.
3250 */
3251IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3252 uint8_t cbInstr)
3253{
3254 Assert(puNewCrX);
3255 Assert(iCrReg == 0 || iCrReg == 4);
3256 Assert(iGReg < X86_GREG_COUNT);
3257
3258 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3259 Assert(pVmcs);
3260
3261 uint64_t uGuestCrX;
3262 uint64_t fGstHostMask;
3263 uint64_t fReadShadow;
3264 if (iCrReg == 0)
3265 {
3266 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3267 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3268 fGstHostMask = pVmcs->u64Cr0Mask.u;
3269 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3270 }
3271 else
3272 {
3273 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3274 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3275 fGstHostMask = pVmcs->u64Cr4Mask.u;
3276 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3277 }
3278
3279 /*
3280 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3281 * corresponding bits differ between the source operand and the read-shadow,
3282 * we must cause a VM-exit.
3283 *
3284 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3285 */
3286 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3287 {
3288 Assert(fGstHostMask != 0);
3289 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3290
3291 VMXVEXITINFO ExitInfo;
3292 RT_ZERO(ExitInfo);
3293 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3294 ExitInfo.cbInstr = cbInstr;
3295 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3296 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3297 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3298 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3299 }
3300
3301 /*
3302 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3303 * must not be modified the instruction.
3304 *
3305 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3306 */
3307 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3308
3309 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3310}
3311
3312
3313/**
3314 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3315 *
3316 * @returns VBox strict status code.
3317 * @param pVCpu The cross context virtual CPU structure.
3318 * @param iGReg The general register to which the CR3 value is being stored.
3319 * @param cbInstr The instruction length in bytes.
3320 */
3321IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3322{
3323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3324 Assert(pVmcs);
3325 Assert(iGReg < X86_GREG_COUNT);
3326 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3327
3328 /*
3329 * If the CR3-store exiting control is set, we must cause a VM-exit.
3330 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3331 */
3332 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3333 {
3334 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3335
3336 VMXVEXITINFO ExitInfo;
3337 RT_ZERO(ExitInfo);
3338 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3339 ExitInfo.cbInstr = cbInstr;
3340 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3341 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3342 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3343 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3344 }
3345
3346 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3347}
3348
3349
3350/**
3351 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3352 *
3353 * @returns VBox strict status code.
3354 * @param pVCpu The cross context virtual CPU structure.
3355 * @param uNewCr3 The new CR3 value.
3356 * @param iGReg The general register from which the CR3 value is being
3357 * loaded.
3358 * @param cbInstr The instruction length in bytes.
3359 */
3360IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3361{
3362 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3363 Assert(pVmcs);
3364 Assert(iGReg < X86_GREG_COUNT);
3365
3366 /*
3367 * If the CR3-load exiting control is set and the new CR3 value does not
3368 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3369 *
3370 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3371 */
3372 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3373 {
3374 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3375 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3376
3377 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3378 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3379 if (!fIntercept)
3380 {
3381 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3382 {
3383 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3384 if (uNewCr3 != uCr3TargetValue)
3385 {
3386 fIntercept = true;
3387 break;
3388 }
3389 }
3390 }
3391
3392 if (fIntercept)
3393 {
3394 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3395
3396 VMXVEXITINFO ExitInfo;
3397 RT_ZERO(ExitInfo);
3398 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3399 ExitInfo.cbInstr = cbInstr;
3400 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3401 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3402 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3403 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3404 }
3405 }
3406
3407 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3408}
3409
3410
3411/**
3412 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3413 *
3414 * @returns VBox strict status code.
3415 * @param pVCpu The cross context virtual CPU structure.
3416 * @param iGReg The general register to which the CR8 value is being stored.
3417 * @param cbInstr The instruction length in bytes.
3418 */
3419IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3420{
3421 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3422 Assert(pVmcs);
3423 Assert(iGReg < X86_GREG_COUNT);
3424
3425 /*
3426 * If the CR8-store exiting control is set, we must cause a VM-exit.
3427 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3428 */
3429 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3430 {
3431 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3432
3433 VMXVEXITINFO ExitInfo;
3434 RT_ZERO(ExitInfo);
3435 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3436 ExitInfo.cbInstr = cbInstr;
3437 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3438 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3439 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3440 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3441 }
3442
3443 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3444}
3445
3446
3447/**
3448 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3449 *
3450 * @returns VBox strict status code.
3451 * @param pVCpu The cross context virtual CPU structure.
3452 * @param iGReg The general register from which the CR8 value is being
3453 * loaded.
3454 * @param cbInstr The instruction length in bytes.
3455 */
3456IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3457{
3458 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3459 Assert(pVmcs);
3460 Assert(iGReg < X86_GREG_COUNT);
3461
3462 /*
3463 * If the CR8-load exiting control is set, we must cause a VM-exit.
3464 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3465 */
3466 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3467 {
3468 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3469
3470 VMXVEXITINFO ExitInfo;
3471 RT_ZERO(ExitInfo);
3472 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3473 ExitInfo.cbInstr = cbInstr;
3474 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3476 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3477 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3478 }
3479
3480 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3481}
3482
3483
3484/**
3485 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3486 * GReg,DRx' (DRx read).
3487 *
3488 * @returns VBox strict status code.
3489 * @param pVCpu The cross context virtual CPU structure.
3490 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3491 * VMXINSTRID_MOV_FROM_DRX).
3492 * @param iDrReg The debug register being accessed.
3493 * @param iGReg The general register to/from which the DRx value is being
3494 * store/loaded.
3495 * @param cbInstr The instruction length in bytes.
3496 */
3497IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3498 uint8_t cbInstr)
3499{
3500 Assert(iDrReg <= 7);
3501 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3502 Assert(iGReg < X86_GREG_COUNT);
3503
3504 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3505 Assert(pVmcs);
3506
3507 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3508 {
3509 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3510 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3511 VMXVEXITINFO ExitInfo;
3512 RT_ZERO(ExitInfo);
3513 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3514 ExitInfo.cbInstr = cbInstr;
3515 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3516 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3517 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3518 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3519 }
3520
3521 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3522}
3523
3524
3525/**
3526 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3527 *
3528 * @returns VBox strict status code.
3529 * @param pVCpu The cross context virtual CPU structure.
3530 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3531 * VMXINSTRID_IO_OUT).
3532 * @param u16Port The I/O port being accessed.
3533 * @param fImm Whether the I/O port was encoded using an immediate operand
3534 * or the implicit DX register.
3535 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3536 * @param cbInstr The instruction length in bytes.
3537 */
3538IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3539 uint8_t cbInstr)
3540{
3541 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3542 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3543
3544 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3545 if (fIntercept)
3546 {
3547 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3548 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3549 VMXVEXITINFO ExitInfo;
3550 RT_ZERO(ExitInfo);
3551 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3552 ExitInfo.cbInstr = cbInstr;
3553 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3554 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3555 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3556 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3557 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3558 }
3559
3560 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3561}
3562
3563
3564/**
3565 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3566 *
3567 * @returns VBox strict status code.
3568 * @param pVCpu The cross context virtual CPU structure.
3569 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3570 * VMXINSTRID_IO_OUTS).
3571 * @param u16Port The I/O port being accessed.
3572 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3573 * @param fRep Whether the instruction has a REP prefix or not.
3574 * @param ExitInstrInfo The VM-exit instruction info. field.
3575 * @param cbInstr The instruction length in bytes.
3576 */
3577IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3578 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3579{
3580 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3581 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3582 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3583 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3584 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3585
3586 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3587 if (fIntercept)
3588 {
3589 /*
3590 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3591 */
3592 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3593 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3594 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3595 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3596 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3597
3598 uint32_t uDirection;
3599 uint64_t uGuestLinearAddr;
3600 if (uInstrId == VMXINSTRID_IO_INS)
3601 {
3602 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3603 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3604 }
3605 else
3606 {
3607 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3608 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3609 }
3610
3611 /*
3612 * If the segment is ununsable, the guest-linear address in undefined.
3613 * We shall clear it for consistency.
3614 *
3615 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3616 */
3617 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3618 uGuestLinearAddr = 0;
3619
3620 VMXVEXITINFO ExitInfo;
3621 RT_ZERO(ExitInfo);
3622 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3623 ExitInfo.cbInstr = cbInstr;
3624 ExitInfo.InstrInfo = ExitInstrInfo;
3625 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3626 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3627 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3628 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3629 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3630 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3631 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3632 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3633 }
3634
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636}
3637
3638
3639/**
3640 * VMX VM-exit handler for VM-exits due to MWAIT.
3641 *
3642 * @returns VBox strict status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3645 * @param cbInstr The instruction length in bytes.
3646 */
3647IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3648{
3649 VMXVEXITINFO ExitInfo;
3650 RT_ZERO(ExitInfo);
3651 ExitInfo.uReason = VMX_EXIT_MWAIT;
3652 ExitInfo.cbInstr = cbInstr;
3653 ExitInfo.u64Qual = fMonitorHwArmed;
3654 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3655}
3656
3657
3658/**
3659 * VMX VM-exit handler for VM-exits due to PAUSE.
3660 *
3661 * @returns VBox strict status code.
3662 * @param pVCpu The cross context virtual CPU structure.
3663 * @param cbInstr The instruction length in bytes.
3664 */
3665IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3666{
3667 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3668 Assert(pVmcs);
3669
3670 /*
3671 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3672 * "PAUSE-loop exiting" control.
3673 *
3674 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3675 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3676 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3677 * a VM-exit.
3678 *
3679 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3680 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3681 */
3682 bool fIntercept = false;
3683 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3684 fIntercept = true;
3685 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3686 && pVCpu->iem.s.uCpl == 0)
3687 {
3688 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3689
3690 /*
3691 * A previous-PAUSE-tick value of 0 is used to identify the first time
3692 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3693 * consider this to be the first execution of PAUSE in a loop according
3694 * to the Intel.
3695 *
3696 * All subsequent records for the previous-PAUSE-tick we ensure that it
3697 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3698 */
3699 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3700 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3701 uint64_t const uTick = TMCpuTickGet(pVCpu);
3702 uint32_t const uPleGap = pVmcs->u32PleGap;
3703 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3704 if ( *puPrevPauseTick == 0
3705 || uTick - *puPrevPauseTick > uPleGap)
3706 *puFirstPauseLoopTick = uTick;
3707 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3708 fIntercept = true;
3709
3710 *puPrevPauseTick = uTick | 1;
3711 }
3712
3713 if (fIntercept)
3714 {
3715 VMXVEXITINFO ExitInfo;
3716 RT_ZERO(ExitInfo);
3717 ExitInfo.uReason = VMX_EXIT_PAUSE;
3718 ExitInfo.cbInstr = cbInstr;
3719 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3720 }
3721
3722 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3723}
3724
3725
3726/**
3727 * VMX VM-exit handler for VM-exits due to task switches.
3728 *
3729 * @returns VBox strict status code.
3730 * @param pVCpu The cross context virtual CPU structure.
3731 * @param enmTaskSwitch The cause of the task switch.
3732 * @param SelNewTss The selector of the new TSS.
3733 * @param cbInstr The instruction length in bytes.
3734 */
3735IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3736{
3737 /*
3738 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3739 *
3740 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3741 * instruction or delivery of the exception generated by one of these instructions
3742 * lead to a task switch through a task gate in the IDT, we need to provide the
3743 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3744 * leaves the VM-exit instruction length field undefined.
3745 *
3746 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3747 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3748 */
3749 Assert(cbInstr <= 15);
3750
3751 uint8_t uType;
3752 switch (enmTaskSwitch)
3753 {
3754 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3755 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3756 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3757 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3758 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3759 }
3760
3761 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3762 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3763 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3764 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3765 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3766}
3767
3768
3769/**
3770 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3771 *
3772 * @returns VBox strict status code.
3773 * @param pVCpu The cross context virtual CPU structure.
3774 */
3775IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3776{
3777 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3778 Assert(pVmcs);
3779
3780 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3781 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3782 {
3783 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3784 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3785
3786 /*
3787 * Calculate the current VMX-preemption timer value.
3788 * Only if the value has reached zero, we cause the VM-exit.
3789 */
3790 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3791 if (!uPreemptTimer)
3792 {
3793 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3794 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3795 pVmcs->u32PreemptTimer = 0;
3796
3797 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3798 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3799 }
3800 }
3801
3802 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3803}
3804
3805
3806/**
3807 * VMX VM-exit handler for VM-exits due to external interrupts.
3808 *
3809 * @returns VBox strict status code.
3810 * @param pVCpu The cross context virtual CPU structure.
3811 * @param uVector The external interrupt vector (pass 0 if the interrupt
3812 * is still pending since we typically won't know the
3813 * vector).
3814 * @param fIntPending Whether the external interrupt is pending or
3815 * acknowledged in the interrupt controller.
3816 */
3817IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3818{
3819 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3820 Assert(pVmcs);
3821 Assert(fIntPending || uVector == 0);
3822
3823 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3824 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3825 * functions require prior checking of a blanket intercept and which don't.
3826 * It is better for the caller to check a blanket intercept performance wise
3827 * than making a function call. Leaving this as a todo because it is more
3828 * a performance issue. */
3829
3830 /* The VM-exit is subject to "External interrupt exiting" being set. */
3831 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3832 {
3833 if (fIntPending)
3834 {
3835 /*
3836 * If the interrupt is pending and we don't need to acknowledge the
3837 * interrupt on VM-exit, cause the VM-exit immediately.
3838 *
3839 * See Intel spec 25.2 "Other Causes Of VM Exits".
3840 */
3841 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3842 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3843
3844 /*
3845 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3846 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3847 * acknowledged that the interrupt has been consumed.
3848 */
3849 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3850 }
3851
3852 /*
3853 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3854 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3855 * all set, we cause the VM-exit now. We need to record the external interrupt that
3856 * just occurred in the VM-exit interruption information field.
3857 *
3858 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3859 */
3860 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3861 {
3862 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3863 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3864 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3865 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3866 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3867 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3868 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3869 }
3870 }
3871
3872 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3873}
3874
3875
3876/**
3877 * VMX VM-exit handler for VM-exits due to NMIs.
3878 *
3879 * @returns VBox strict status code.
3880 * @param pVCpu The cross context virtual CPU structure.
3881 *
3882 * @remarks This function might import externally kept DR6 if necessary.
3883 */
3884IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3885{
3886 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3887 Assert(pVmcs);
3888 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3889 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3890 NOREF(pVmcs);
3891 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3892}
3893
3894
3895/**
3896 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3897 *
3898 * @returns VBox strict status code.
3899 * @param pVCpu The cross context virtual CPU structure.
3900 * @param uVector The SIPI vector.
3901 */
3902IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3903{
3904 iemVmxVmcsSetExitQual(pVCpu, uVector);
3905 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3906}
3907
3908
3909/**
3910 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3911 * an event.
3912 *
3913 * @returns VBox strict status code.
3914 * @param pVCpu The cross context virtual CPU structure.
3915 */
3916IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3917{
3918 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3919 Assert(pVmcs);
3920
3921 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3922 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3923 {
3924 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3925 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3926 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3927 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3928 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3929 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3930 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3931 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3932 iemVmxVmcsSetExitQual(pVCpu, 0);
3933 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3934
3935 /*
3936 * A VM-exit is not considered to occur during event delivery when the original
3937 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3938 * using the exception bitmap).
3939 *
3940 * Therefore, we must clear the original event from the IDT-vectoring fields which
3941 * would've been recorded before causing the VM-exit.
3942 *
3943 * 27.2.3 "Information for VM Exits During Event Delivery"
3944 */
3945 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3946 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3947
3948 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3949 }
3950
3951 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3952}
3953
3954
3955/**
3956 * VMX VM-exit handler for VM-exits due to delivery of an event.
3957 *
3958 * @returns VBox strict status code.
3959 * @param pVCpu The cross context virtual CPU structure.
3960 * @param uVector The interrupt / exception vector.
3961 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3962 * @param uErrCode The error code associated with the event.
3963 * @param uCr2 The CR2 value in case of a \#PF exception.
3964 * @param cbInstr The instruction length in bytes.
3965 */
3966IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3967 uint8_t cbInstr)
3968{
3969 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3970 Assert(pVmcs);
3971
3972 /*
3973 * If the event is being injected as part of VM-entry, it isn't subject to event
3974 * intercepts in the nested-guest. However, secondary exceptions that occur during
3975 * injection of any event -are- subject to event interception.
3976 *
3977 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3978 */
3979 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3980 {
3981 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3982 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3983 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3984 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3985 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3986 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3987 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3988 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3989 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3990
3991 /*
3992 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3993 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3994 *
3995 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3996 */
3997 if ( uVector == X86_XCPT_NMI
3998 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3999 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
4000 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
4001 else
4002 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
4003
4004 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4005 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4006 }
4007
4008 /*
4009 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4010 * If not, the caller will continue delivery of the external interrupt as it would
4011 * normally. The interrupt is no longer pending in the interrupt controller at this
4012 * point.
4013 */
4014 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4015 {
4016 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4017 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4018 }
4019
4020 /*
4021 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4022 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4023 */
4024 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4025 bool fIntercept = false;
4026 bool fIsHwXcpt = false;
4027 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4028 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4029 {
4030 fIsHwXcpt = true;
4031 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4032 if (uVector == X86_XCPT_NMI)
4033 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
4034 else
4035 {
4036 /* Page-faults are subject to masking using its error code. */
4037 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4038 if (uVector == X86_XCPT_PF)
4039 {
4040 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4041 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4042 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4043 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4044 }
4045
4046 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4047 if (fXcptBitmap & RT_BIT(uVector))
4048 fIntercept = true;
4049 }
4050 }
4051 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4052
4053 /*
4054 * Now that we've determined whether the software interrupt or hardware exception
4055 * causes a VM-exit, we need to construct the relevant VM-exit information and
4056 * cause the VM-exit.
4057 */
4058 if (fIntercept)
4059 {
4060 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4061
4062 /* Construct the rest of the event related information fields and cause the VM-exit. */
4063 uint64_t uExitQual = 0;
4064 if (fIsHwXcpt)
4065 {
4066 if (uVector == X86_XCPT_PF)
4067 {
4068 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4069 uExitQual = uCr2;
4070 }
4071 else if (uVector == X86_XCPT_DB)
4072 {
4073 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4074 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4075 }
4076 }
4077
4078 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4079 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4080 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4081 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4082 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4083 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4084 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4085 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4086 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4087 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4088 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4089
4090 /*
4091 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4092 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4093 * length.
4094 */
4095 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4096 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4097 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4098 else
4099 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4100
4101 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4102 }
4103
4104 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4105}
4106
4107
4108/**
4109 * VMX VM-exit handler for VM-exits due to a triple fault.
4110 *
4111 * @returns VBox strict status code.
4112 * @param pVCpu The cross context virtual CPU structure.
4113 */
4114IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4115{
4116 /*
4117 * A VM-exit is not considered to occur during event delivery when the original
4118 * event results in a triple-fault.
4119 *
4120 * Therefore, we must clear the original event from the IDT-vectoring fields which
4121 * would've been recorded before causing the VM-exit.
4122 *
4123 * 27.2.3 "Information for VM Exits During Event Delivery"
4124 */
4125 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4126 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4127
4128 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4129}
4130
4131
4132/**
4133 * VMX VM-exit handler for APIC-accesses.
4134 *
4135 * @param pVCpu The cross context virtual CPU structure.
4136 * @param offAccess The offset of the register being accessed.
4137 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4138 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4139 */
4140IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4141{
4142 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4143
4144 VMXAPICACCESS enmAccess;
4145 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4146 if (fInEventDelivery)
4147 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4148 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4149 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4150 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4151 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4152 else
4153 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4154
4155 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4156 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4157 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4158 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4159}
4160
4161
4162/**
4163 * VMX VM-exit handler for APIC-write VM-exits.
4164 *
4165 * @param pVCpu The cross context virtual CPU structure.
4166 * @param offApic The write to the virtual-APIC page offset that caused this
4167 * VM-exit.
4168 */
4169IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4170{
4171 Assert(offApic < XAPIC_OFF_END + 4);
4172
4173 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4174 offApic &= UINT16_C(0xfff);
4175 iemVmxVmcsSetExitQual(pVCpu, offApic);
4176 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4177}
4178
4179
4180/**
4181 * VMX VM-exit handler for virtualized-EOIs.
4182 *
4183 * @param pVCpu The cross context virtual CPU structure.
4184 */
4185IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4186{
4187 iemVmxVmcsSetExitQual(pVCpu, uVector);
4188 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4189}
4190
4191
4192/**
4193 * Sets virtual-APIC write emulation as pending.
4194 *
4195 * @param pVCpu The cross context virtual CPU structure.
4196 * @param offApic The offset in the virtual-APIC page that was written.
4197 */
4198DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4199{
4200 Assert(offApic < XAPIC_OFF_END + 4);
4201
4202 /*
4203 * Record the currently updated APIC offset, as we need this later for figuring
4204 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4205 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4206 */
4207 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4208
4209 /*
4210 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4211 * virtualization or APIC-write emulation).
4212 */
4213 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4214 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4215}
4216
4217
4218/**
4219 * Clears any pending virtual-APIC write emulation.
4220 *
4221 * @returns The virtual-APIC offset that was written before clearing it.
4222 * @param pVCpu The cross context virtual CPU structure.
4223 */
4224DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4225{
4226 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4227 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4228 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4229 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4230 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4231 return offVirtApicWrite;
4232}
4233
4234
4235/**
4236 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4237 *
4238 * @returns The register from the virtual-APIC page.
4239 * @param pVCpu The cross context virtual CPU structure.
4240 * @param offReg The offset of the register being read.
4241 */
4242IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4243{
4244 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4245 Assert(pVmcs);
4246
4247 uint32_t uReg;
4248 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4249 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4250 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4251 if (RT_FAILURE(rc))
4252 {
4253 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4254 GCPhysVirtApic));
4255 uReg = 0;
4256 }
4257 return uReg;
4258}
4259
4260
4261/**
4262 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4263 *
4264 * @returns The register from the virtual-APIC page.
4265 * @param pVCpu The cross context virtual CPU structure.
4266 * @param offReg The offset of the register being read.
4267 */
4268IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4269{
4270 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4271 Assert(pVmcs);
4272
4273 uint64_t uReg;
4274 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4275 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4276 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4277 if (RT_FAILURE(rc))
4278 {
4279 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4280 GCPhysVirtApic));
4281 uReg = 0;
4282 }
4283 return uReg;
4284}
4285
4286
4287/**
4288 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4289 *
4290 * @param pVCpu The cross context virtual CPU structure.
4291 * @param offReg The offset of the register being written.
4292 * @param uReg The register value to write.
4293 */
4294IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4295{
4296 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4297 Assert(pVmcs);
4298 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4299 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4300 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4301 if (RT_FAILURE(rc))
4302 {
4303 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4304 GCPhysVirtApic));
4305 }
4306}
4307
4308
4309/**
4310 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4311 *
4312 * @param pVCpu The cross context virtual CPU structure.
4313 * @param offReg The offset of the register being written.
4314 * @param uReg The register value to write.
4315 */
4316IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4317{
4318 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4319 Assert(pVmcs);
4320 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4321 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4322 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4323 if (RT_FAILURE(rc))
4324 {
4325 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4326 GCPhysVirtApic));
4327 }
4328}
4329
4330
4331/**
4332 * Sets the vector in a virtual-APIC 256-bit sparse register.
4333 *
4334 * @param pVCpu The cross context virtual CPU structure.
4335 * @param offReg The offset of the 256-bit spare register.
4336 * @param uVector The vector to set.
4337 *
4338 * @remarks This is based on our APIC device code.
4339 */
4340IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4341{
4342 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4343 Assert(pVmcs);
4344 uint32_t uReg;
4345 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4346 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4347 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4348 if (RT_SUCCESS(rc))
4349 {
4350 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4351 uReg |= RT_BIT(idxVectorBit);
4352 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4353 if (RT_FAILURE(rc))
4354 {
4355 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4356 uVector, offReg, GCPhysVirtApic));
4357 }
4358 }
4359 else
4360 {
4361 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4362 uVector, offReg, GCPhysVirtApic));
4363 }
4364}
4365
4366
4367/**
4368 * Clears the vector in a virtual-APIC 256-bit sparse register.
4369 *
4370 * @param pVCpu The cross context virtual CPU structure.
4371 * @param offReg The offset of the 256-bit spare register.
4372 * @param uVector The vector to clear.
4373 *
4374 * @remarks This is based on our APIC device code.
4375 */
4376IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4377{
4378 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4379 Assert(pVmcs);
4380 uint32_t uReg;
4381 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4382 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4383 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4384 if (RT_SUCCESS(rc))
4385 {
4386 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4387 uReg &= ~RT_BIT(idxVectorBit);
4388 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4389 if (RT_FAILURE(rc))
4390 {
4391 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4392 uVector, offReg, GCPhysVirtApic));
4393 }
4394 }
4395 else
4396 {
4397 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4398 uVector, offReg, GCPhysVirtApic));
4399 }
4400}
4401
4402
4403/**
4404 * Checks if a memory access to the APIC-access page must causes an APIC-access
4405 * VM-exit.
4406 *
4407 * @param pVCpu The cross context virtual CPU structure.
4408 * @param offAccess The offset of the register being accessed.
4409 * @param cbAccess The size of the access in bytes.
4410 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4411 * IEM_ACCESS_TYPE_WRITE).
4412 *
4413 * @remarks This must not be used for MSR-based APIC-access page accesses!
4414 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4415 */
4416IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4417{
4418 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4419 Assert(pVmcs);
4420 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4421
4422 /*
4423 * We must cause a VM-exit if any of the following are true:
4424 * - TPR shadowing isn't active.
4425 * - The access size exceeds 32-bits.
4426 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4427 *
4428 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4429 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4430 */
4431 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4432 || cbAccess > sizeof(uint32_t)
4433 || ((offAccess + cbAccess - 1) & 0xc)
4434 || offAccess >= XAPIC_OFF_END + 4)
4435 return true;
4436
4437 /*
4438 * If the access is part of an operation where we have already
4439 * virtualized a virtual-APIC write, we must cause a VM-exit.
4440 */
4441 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4442 return true;
4443
4444 /*
4445 * Check write accesses to the APIC-access page that cause VM-exits.
4446 */
4447 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4448 {
4449 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4450 {
4451 /*
4452 * With APIC-register virtualization, a write access to any of the
4453 * following registers are virtualized. Accessing any other register
4454 * causes a VM-exit.
4455 */
4456 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4457 switch (offAlignedAccess)
4458 {
4459 case XAPIC_OFF_ID:
4460 case XAPIC_OFF_TPR:
4461 case XAPIC_OFF_EOI:
4462 case XAPIC_OFF_LDR:
4463 case XAPIC_OFF_DFR:
4464 case XAPIC_OFF_SVR:
4465 case XAPIC_OFF_ESR:
4466 case XAPIC_OFF_ICR_LO:
4467 case XAPIC_OFF_ICR_HI:
4468 case XAPIC_OFF_LVT_TIMER:
4469 case XAPIC_OFF_LVT_THERMAL:
4470 case XAPIC_OFF_LVT_PERF:
4471 case XAPIC_OFF_LVT_LINT0:
4472 case XAPIC_OFF_LVT_LINT1:
4473 case XAPIC_OFF_LVT_ERROR:
4474 case XAPIC_OFF_TIMER_ICR:
4475 case XAPIC_OFF_TIMER_DCR:
4476 break;
4477 default:
4478 return true;
4479 }
4480 }
4481 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4482 {
4483 /*
4484 * With virtual-interrupt delivery, a write access to any of the
4485 * following registers are virtualized. Accessing any other register
4486 * causes a VM-exit.
4487 *
4488 * Note! The specification does not allow writing to offsets in-between
4489 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4490 */
4491 switch (offAccess)
4492 {
4493 case XAPIC_OFF_TPR:
4494 case XAPIC_OFF_EOI:
4495 case XAPIC_OFF_ICR_LO:
4496 break;
4497 default:
4498 return true;
4499 }
4500 }
4501 else
4502 {
4503 /*
4504 * Without APIC-register virtualization or virtual-interrupt delivery,
4505 * only TPR accesses are virtualized.
4506 */
4507 if (offAccess == XAPIC_OFF_TPR)
4508 { /* likely */ }
4509 else
4510 return true;
4511 }
4512 }
4513 else
4514 {
4515 /*
4516 * Check read accesses to the APIC-access page that cause VM-exits.
4517 */
4518 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4519 {
4520 /*
4521 * With APIC-register virtualization, a read access to any of the
4522 * following registers are virtualized. Accessing any other register
4523 * causes a VM-exit.
4524 */
4525 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4526 switch (offAlignedAccess)
4527 {
4528 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4529 case XAPIC_OFF_ID:
4530 case XAPIC_OFF_VERSION:
4531 case XAPIC_OFF_TPR:
4532 case XAPIC_OFF_EOI:
4533 case XAPIC_OFF_LDR:
4534 case XAPIC_OFF_DFR:
4535 case XAPIC_OFF_SVR:
4536 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4537 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4538 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4539 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4540 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4541 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4542 case XAPIC_OFF_ESR:
4543 case XAPIC_OFF_ICR_LO:
4544 case XAPIC_OFF_ICR_HI:
4545 case XAPIC_OFF_LVT_TIMER:
4546 case XAPIC_OFF_LVT_THERMAL:
4547 case XAPIC_OFF_LVT_PERF:
4548 case XAPIC_OFF_LVT_LINT0:
4549 case XAPIC_OFF_LVT_LINT1:
4550 case XAPIC_OFF_LVT_ERROR:
4551 case XAPIC_OFF_TIMER_ICR:
4552 case XAPIC_OFF_TIMER_DCR:
4553 break;
4554 default:
4555 return true;
4556 }
4557 }
4558 else
4559 {
4560 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4561 if (offAccess == XAPIC_OFF_TPR)
4562 { /* likely */ }
4563 else
4564 return true;
4565 }
4566 }
4567
4568 /* The APIC-access is virtualized, does not cause a VM-exit. */
4569 return false;
4570}
4571
4572
4573/**
4574 * Virtualizes a memory-based APIC-access where the address is not used to access
4575 * memory.
4576 *
4577 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4578 * page-faults but do not use the address to access memory.
4579 *
4580 * @param pVCpu The cross context virtual CPU structure.
4581 * @param pGCPhysAccess Pointer to the guest-physical address used.
4582 */
4583IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4584{
4585 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4586 Assert(pVmcs);
4587 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4588 Assert(pGCPhysAccess);
4589
4590 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4591 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4592 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4593
4594 if (GCPhysAccess == GCPhysApic)
4595 {
4596 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4597 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4598 uint16_t const cbAccess = 1;
4599 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4600 if (fIntercept)
4601 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4602
4603 *pGCPhysAccess = GCPhysApic | offAccess;
4604 return VINF_VMX_MODIFIES_BEHAVIOR;
4605 }
4606
4607 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4608}
4609
4610
4611/**
4612 * Virtualizes a memory-based APIC-access.
4613 *
4614 * @returns VBox strict status code.
4615 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4616 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4617 *
4618 * @param pVCpu The cross context virtual CPU structure.
4619 * @param offAccess The offset of the register being accessed (within the
4620 * APIC-access page).
4621 * @param cbAccess The size of the access in bytes.
4622 * @param pvData Pointer to the data being written or where to store the data
4623 * being read.
4624 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4625 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4626 */
4627IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4628 uint32_t fAccess)
4629{
4630 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4631 Assert(pVmcs);
4632 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4633 Assert(pvData);
4634 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4635 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4636 || (fAccess & IEM_ACCESS_INSTRUCTION));
4637
4638 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4639 if (fIntercept)
4640 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4641
4642 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4643 {
4644 /*
4645 * A write access to the APIC-access page that is virtualized (rather than
4646 * causing a VM-exit) writes data to the virtual-APIC page.
4647 */
4648 uint32_t const u32Data = *(uint32_t *)pvData;
4649 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4650
4651 /*
4652 * Record the currently updated APIC offset, as we need this later for figuring
4653 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4654 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4655 *
4656 * After completion of the current operation, we need to perform TPR virtualization,
4657 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4658 *
4659 * The current operation may be a REP-prefixed string instruction, execution of any
4660 * other instruction, or delivery of an event through the IDT.
4661 *
4662 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4663 * performed now but later after completion of the current operation.
4664 *
4665 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4666 */
4667 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4668 }
4669 else
4670 {
4671 /*
4672 * A read access from the APIC-access page that is virtualized (rather than
4673 * causing a VM-exit) returns data from the virtual-APIC page.
4674 *
4675 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4676 */
4677 Assert(cbAccess <= 4);
4678 Assert(offAccess < XAPIC_OFF_END + 4);
4679 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4680
4681 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4682 u32Data &= s_auAccessSizeMasks[cbAccess];
4683 *(uint32_t *)pvData = u32Data;
4684 }
4685
4686 return VINF_VMX_MODIFIES_BEHAVIOR;
4687}
4688
4689
4690/**
4691 * Virtualizes an MSR-based APIC read access.
4692 *
4693 * @returns VBox strict status code.
4694 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4695 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4696 * handled by the x2APIC device.
4697 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4698 * not within the range of valid MSRs, caller must raise \#GP(0).
4699 * @param pVCpu The cross context virtual CPU structure.
4700 * @param idMsr The x2APIC MSR being read.
4701 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4702 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4703 */
4704IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4705{
4706 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4707 Assert(pVmcs);
4708 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4709 Assert(pu64Value);
4710
4711 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4712 {
4713 /*
4714 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4715 * what the end of the valid x2APIC MSR range is. Hence the use of different
4716 * macros here.
4717 *
4718 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4719 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4720 */
4721 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4722 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4723 {
4724 uint16_t const offReg = (idMsr & 0xff) << 4;
4725 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4726 *pu64Value = u64Value;
4727 return VINF_VMX_MODIFIES_BEHAVIOR;
4728 }
4729 return VERR_OUT_OF_RANGE;
4730 }
4731
4732 if (idMsr == MSR_IA32_X2APIC_TPR)
4733 {
4734 uint16_t const offReg = (idMsr & 0xff) << 4;
4735 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4736 *pu64Value = u64Value;
4737 return VINF_VMX_MODIFIES_BEHAVIOR;
4738 }
4739
4740 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4741}
4742
4743
4744/**
4745 * Virtualizes an MSR-based APIC write access.
4746 *
4747 * @returns VBox strict status code.
4748 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4749 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4750 * not within the range of valid MSRs, caller must raise \#GP(0).
4751 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4752 *
4753 * @param pVCpu The cross context virtual CPU structure.
4754 * @param idMsr The x2APIC MSR being written.
4755 * @param u64Value The value of the x2APIC MSR being written.
4756 */
4757IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4758{
4759 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4760 Assert(pVmcs);
4761
4762 /*
4763 * Check if the access is to be virtualized.
4764 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4765 */
4766 if ( idMsr == MSR_IA32_X2APIC_TPR
4767 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4768 && ( idMsr == MSR_IA32_X2APIC_EOI
4769 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4770 {
4771 /* Validate the MSR write depending on the register. */
4772 switch (idMsr)
4773 {
4774 case MSR_IA32_X2APIC_TPR:
4775 case MSR_IA32_X2APIC_SELF_IPI:
4776 {
4777 if (u64Value & UINT64_C(0xffffffffffffff00))
4778 return VERR_OUT_OF_RANGE;
4779 break;
4780 }
4781 case MSR_IA32_X2APIC_EOI:
4782 {
4783 if (u64Value != 0)
4784 return VERR_OUT_OF_RANGE;
4785 break;
4786 }
4787 }
4788
4789 /* Write the MSR to the virtual-APIC page. */
4790 uint16_t const offReg = (idMsr & 0xff) << 4;
4791 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4792
4793 /*
4794 * Record the currently updated APIC offset, as we need this later for figuring
4795 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4796 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4797 */
4798 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4799
4800 return VINF_VMX_MODIFIES_BEHAVIOR;
4801 }
4802
4803 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4804}
4805
4806
4807/**
4808 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4809 *
4810 * @returns VBox status code.
4811 * @retval VINF_SUCCES when the highest set bit is found.
4812 * @retval VERR_NOT_FOUND when no bit is set.
4813 *
4814 * @param pVCpu The cross context virtual CPU structure.
4815 * @param offReg The offset of the APIC 256-bit sparse register.
4816 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4817 * set in the register. Only valid when VINF_SUCCESS is
4818 * returned.
4819 *
4820 * @remarks The format of the 256-bit sparse register here mirrors that found in
4821 * real APIC hardware.
4822 */
4823static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4824{
4825 Assert(offReg < XAPIC_OFF_END + 4);
4826 Assert(pidxHighestBit);
4827 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4828
4829 /*
4830 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4831 * However, in each fragment only the first 4 bytes are used.
4832 */
4833 uint8_t const cFrags = 8;
4834 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4835 {
4836 uint16_t const offFrag = iFrag * 16;
4837 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4838 if (!u32Frag)
4839 continue;
4840
4841 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4842 Assert(idxHighestBit > 0);
4843 --idxHighestBit;
4844 Assert(idxHighestBit <= UINT8_MAX);
4845 *pidxHighestBit = idxHighestBit;
4846 return VINF_SUCCESS;
4847 }
4848 return VERR_NOT_FOUND;
4849}
4850
4851
4852/**
4853 * Evaluates pending virtual interrupts.
4854 *
4855 * @param pVCpu The cross context virtual CPU structure.
4856 */
4857IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4858{
4859 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4860 Assert(pVmcs);
4861 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4862
4863 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4864 {
4865 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4866 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4867
4868 if ((uRvi >> 4) > (uPpr >> 4))
4869 {
4870 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4871 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4872 }
4873 else
4874 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4875 }
4876}
4877
4878
4879/**
4880 * Performs PPR virtualization.
4881 *
4882 * @returns VBox strict status code.
4883 * @param pVCpu The cross context virtual CPU structure.
4884 */
4885IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4886{
4887 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4888 Assert(pVmcs);
4889 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4890 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4891
4892 /*
4893 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4894 * or EOI-virtualization.
4895 *
4896 * See Intel spec. 29.1.3 "PPR Virtualization".
4897 */
4898 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4899 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4900
4901 uint32_t uPpr;
4902 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4903 uPpr = uTpr & 0xff;
4904 else
4905 uPpr = uSvi & 0xf0;
4906
4907 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4908 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4909}
4910
4911
4912/**
4913 * Performs VMX TPR virtualization.
4914 *
4915 * @returns VBox strict status code.
4916 * @param pVCpu The cross context virtual CPU structure.
4917 */
4918IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4919{
4920 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4921 Assert(pVmcs);
4922 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4923
4924 /*
4925 * We should have already performed the virtual-APIC write to the TPR offset
4926 * in the virtual-APIC page. We now perform TPR virtualization.
4927 *
4928 * See Intel spec. 29.1.2 "TPR Virtualization".
4929 */
4930 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4931 {
4932 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4933 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4934
4935 /*
4936 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4937 * See Intel spec. 29.1.2 "TPR Virtualization".
4938 */
4939 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4940 {
4941 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4942 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4943 }
4944 }
4945 else
4946 {
4947 iemVmxPprVirtualization(pVCpu);
4948 iemVmxEvalPendingVirtIntrs(pVCpu);
4949 }
4950
4951 return VINF_SUCCESS;
4952}
4953
4954
4955/**
4956 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4957 * not.
4958 *
4959 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4960 * @param pVCpu The cross context virtual CPU structure.
4961 * @param uVector The interrupt that was acknowledged using an EOI.
4962 */
4963IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4964{
4965 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4966 Assert(pVmcs);
4967 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4968
4969 if (uVector < 64)
4970 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4971 if (uVector < 128)
4972 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4973 if (uVector < 192)
4974 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4975 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4976}
4977
4978
4979/**
4980 * Performs EOI virtualization.
4981 *
4982 * @returns VBox strict status code.
4983 * @param pVCpu The cross context virtual CPU structure.
4984 */
4985IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4986{
4987 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4988 Assert(pVmcs);
4989 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4990
4991 /*
4992 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4993 * and get the next guest-interrupt that's in-service (if any).
4994 *
4995 * See Intel spec. 29.1.4 "EOI Virtualization".
4996 */
4997 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4998 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4999 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5000
5001 uint8_t uVector = uSvi;
5002 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
5003
5004 uVector = 0;
5005 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5006
5007 if (uVector)
5008 Log2(("eoi_virt: next interrupt %#x\n", uVector));
5009 else
5010 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5011
5012 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5013 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5014
5015 iemVmxPprVirtualization(pVCpu);
5016 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5017 return iemVmxVmexitVirtEoi(pVCpu, uVector);
5018 iemVmxEvalPendingVirtIntrs(pVCpu);
5019 return VINF_SUCCESS;
5020}
5021
5022
5023/**
5024 * Performs self-IPI virtualization.
5025 *
5026 * @returns VBox strict status code.
5027 * @param pVCpu The cross context virtual CPU structure.
5028 */
5029IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5030{
5031 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5032 Assert(pVmcs);
5033 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5034
5035 /*
5036 * We should have already performed the virtual-APIC write to the self-IPI offset
5037 * in the virtual-APIC page. We now perform self-IPI virtualization.
5038 *
5039 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5040 */
5041 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5042 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5043 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5044 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5045 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5046 if (uVector > uRvi)
5047 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5048 iemVmxEvalPendingVirtIntrs(pVCpu);
5049 return VINF_SUCCESS;
5050}
5051
5052
5053/**
5054 * Performs VMX APIC-write emulation.
5055 *
5056 * @returns VBox strict status code.
5057 * @param pVCpu The cross context virtual CPU structure.
5058 */
5059IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5060{
5061 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5062 Assert(pVmcs);
5063
5064 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5065 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5066
5067 /*
5068 * Perform APIC-write emulation based on the virtual-APIC register written.
5069 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5070 */
5071 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5072 VBOXSTRICTRC rcStrict;
5073 switch (offApicWrite)
5074 {
5075 case XAPIC_OFF_TPR:
5076 {
5077 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5078 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5079 uTpr &= UINT32_C(0x000000ff);
5080 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5081 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5082 rcStrict = iemVmxTprVirtualization(pVCpu);
5083 break;
5084 }
5085
5086 case XAPIC_OFF_EOI:
5087 {
5088 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5089 {
5090 /* Clear VEOI and perform EOI virtualization. */
5091 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5092 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5093 rcStrict = iemVmxEoiVirtualization(pVCpu);
5094 }
5095 else
5096 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5097 break;
5098 }
5099
5100 case XAPIC_OFF_ICR_LO:
5101 {
5102 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5103 {
5104 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5105 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5106 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5107 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5108 if ( !(uIcrLo & fIcrLoMb0)
5109 && (uIcrLo & fIcrLoMb1))
5110 {
5111 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5112 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5113 }
5114 else
5115 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5116 }
5117 else
5118 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5119 break;
5120 }
5121
5122 case XAPIC_OFF_ICR_HI:
5123 {
5124 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5125 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5126 uIcrHi &= UINT32_C(0xff000000);
5127 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5128 rcStrict = VINF_SUCCESS;
5129 break;
5130 }
5131
5132 default:
5133 {
5134 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5135 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5136 break;
5137 }
5138 }
5139
5140 return rcStrict;
5141}
5142
5143
5144/**
5145 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5146 *
5147 * @param pVCpu The cross context virtual CPU structure.
5148 * @param pszInstr The VMX instruction name (for logging purposes).
5149 */
5150IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5151{
5152 /*
5153 * Guest Control Registers, Debug Registers, and MSRs.
5154 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5155 */
5156 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5157 const char *const pszFailure = "VM-exit";
5158 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5159
5160 /* CR0 reserved bits. */
5161 {
5162 /* CR0 MB1 bits. */
5163 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5164 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5165 if (fUnrestrictedGuest)
5166 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5167 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5171
5172 /* CR0 MBZ bits. */
5173 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5174 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5178
5179 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5180 if ( !fUnrestrictedGuest
5181 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5182 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5184 }
5185
5186 /* CR4 reserved bits. */
5187 {
5188 /* CR4 MB1 bits. */
5189 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5190 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5194
5195 /* CR4 MBZ bits. */
5196 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5197 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5201 }
5202
5203 /* DEBUGCTL MSR. */
5204 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5205 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5206 { /* likely */ }
5207 else
5208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5209
5210 /* 64-bit CPU checks. */
5211 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5212 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5213 {
5214 if (fGstInLongMode)
5215 {
5216 /* PAE must be set. */
5217 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5218 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5222 }
5223 else
5224 {
5225 /* PCIDE should not be set. */
5226 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5230 }
5231
5232 /* CR3. */
5233 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5237
5238 /* DR7. */
5239 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5240 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5241 { /* likely */ }
5242 else
5243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5244
5245 /* SYSENTER ESP and SYSENTER EIP. */
5246 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5247 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5251 }
5252
5253 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5254 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5255
5256 /* PAT MSR. */
5257 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5258 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5262
5263 /* EFER MSR. */
5264 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5265 {
5266 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5267 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5268 { /* likely */ }
5269 else
5270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5271
5272 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5273 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5274 if ( fGstLma == fGstInLongMode
5275 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5276 || fGstLma == fGstLme))
5277 { /* likely */ }
5278 else
5279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5280 }
5281
5282 /* We don't support IA32_BNDCFGS MSR yet. */
5283 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5284
5285 NOREF(pszInstr);
5286 NOREF(pszFailure);
5287 return VINF_SUCCESS;
5288}
5289
5290
5291/**
5292 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5293 *
5294 * @param pVCpu The cross context virtual CPU structure.
5295 * @param pszInstr The VMX instruction name (for logging purposes).
5296 */
5297IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5298{
5299 /*
5300 * Segment registers.
5301 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5302 */
5303 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5304 const char *const pszFailure = "VM-exit";
5305 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5306 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5307 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5308
5309 /* Selectors. */
5310 if ( !fGstInV86Mode
5311 && !fUnrestrictedGuest
5312 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5314
5315 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5316 {
5317 CPUMSELREG SelReg;
5318 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5319 if (RT_LIKELY(rc == VINF_SUCCESS))
5320 { /* likely */ }
5321 else
5322 return rc;
5323
5324 /*
5325 * Virtual-8086 mode checks.
5326 */
5327 if (fGstInV86Mode)
5328 {
5329 /* Base address. */
5330 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5331 { /* likely */ }
5332 else
5333 {
5334 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5336 }
5337
5338 /* Limit. */
5339 if (SelReg.u32Limit == 0xffff)
5340 { /* likely */ }
5341 else
5342 {
5343 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5345 }
5346
5347 /* Attribute. */
5348 if (SelReg.Attr.u == 0xf3)
5349 { /* likely */ }
5350 else
5351 {
5352 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5354 }
5355
5356 /* We're done; move to checking the next segment. */
5357 continue;
5358 }
5359
5360 /* Checks done by 64-bit CPUs. */
5361 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5362 {
5363 /* Base address. */
5364 if ( iSegReg == X86_SREG_FS
5365 || iSegReg == X86_SREG_GS)
5366 {
5367 if (X86_IS_CANONICAL(SelReg.u64Base))
5368 { /* likely */ }
5369 else
5370 {
5371 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5373 }
5374 }
5375 else if (iSegReg == X86_SREG_CS)
5376 {
5377 if (!RT_HI_U32(SelReg.u64Base))
5378 { /* likely */ }
5379 else
5380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5381 }
5382 else
5383 {
5384 if ( SelReg.Attr.n.u1Unusable
5385 || !RT_HI_U32(SelReg.u64Base))
5386 { /* likely */ }
5387 else
5388 {
5389 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5391 }
5392 }
5393 }
5394
5395 /*
5396 * Checks outside Virtual-8086 mode.
5397 */
5398 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5399 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5400 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5401 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5402 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5403 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5404 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5405 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5406
5407 /* Code or usable segment. */
5408 if ( iSegReg == X86_SREG_CS
5409 || fUsable)
5410 {
5411 /* Reserved bits (bits 31:17 and bits 11:8). */
5412 if (!(SelReg.Attr.u & 0xfffe0f00))
5413 { /* likely */ }
5414 else
5415 {
5416 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5418 }
5419
5420 /* Descriptor type. */
5421 if (fCodeDataSeg)
5422 { /* likely */ }
5423 else
5424 {
5425 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5427 }
5428
5429 /* Present. */
5430 if (fPresent)
5431 { /* likely */ }
5432 else
5433 {
5434 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5436 }
5437
5438 /* Granularity. */
5439 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5440 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5441 { /* likely */ }
5442 else
5443 {
5444 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5446 }
5447 }
5448
5449 if (iSegReg == X86_SREG_CS)
5450 {
5451 /* Segment Type and DPL. */
5452 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5453 && fUnrestrictedGuest)
5454 {
5455 if (uDpl == 0)
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5459 }
5460 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5461 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5462 {
5463 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5464 if (uDpl == AttrSs.n.u2Dpl)
5465 { /* likely */ }
5466 else
5467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5468 }
5469 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5470 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5471 {
5472 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5473 if (uDpl <= AttrSs.n.u2Dpl)
5474 { /* likely */ }
5475 else
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5477 }
5478 else
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5480
5481 /* Def/Big. */
5482 if ( fGstInLongMode
5483 && fSegLong)
5484 {
5485 if (uDefBig == 0)
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5489 }
5490 }
5491 else if (iSegReg == X86_SREG_SS)
5492 {
5493 /* Segment Type. */
5494 if ( !fUsable
5495 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5496 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5497 { /* likely */ }
5498 else
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5500
5501 /* DPL. */
5502 if (!fUnrestrictedGuest)
5503 {
5504 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5505 { /* likely */ }
5506 else
5507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5508 }
5509 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5510 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5511 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5512 {
5513 if (uDpl == 0)
5514 { /* likely */ }
5515 else
5516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5517 }
5518 }
5519 else
5520 {
5521 /* DS, ES, FS, GS. */
5522 if (fUsable)
5523 {
5524 /* Segment type. */
5525 if (uSegType & X86_SEL_TYPE_ACCESSED)
5526 { /* likely */ }
5527 else
5528 {
5529 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5531 }
5532
5533 if ( !(uSegType & X86_SEL_TYPE_CODE)
5534 || (uSegType & X86_SEL_TYPE_READ))
5535 { /* likely */ }
5536 else
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5538
5539 /* DPL. */
5540 if ( !fUnrestrictedGuest
5541 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5542 {
5543 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5544 { /* likely */ }
5545 else
5546 {
5547 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5549 }
5550 }
5551 }
5552 }
5553 }
5554
5555 /*
5556 * LDTR.
5557 */
5558 {
5559 CPUMSELREG Ldtr;
5560 Ldtr.Sel = pVmcs->GuestLdtr;
5561 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5562 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5563 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5564
5565 if (!Ldtr.Attr.n.u1Unusable)
5566 {
5567 /* Selector. */
5568 if (!(Ldtr.Sel & X86_SEL_LDT))
5569 { /* likely */ }
5570 else
5571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5572
5573 /* Base. */
5574 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5575 {
5576 if (X86_IS_CANONICAL(Ldtr.u64Base))
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5580 }
5581
5582 /* Attributes. */
5583 /* Reserved bits (bits 31:17 and bits 11:8). */
5584 if (!(Ldtr.Attr.u & 0xfffe0f00))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5588
5589 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5590 { /* likely */ }
5591 else
5592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5593
5594 if (!Ldtr.Attr.n.u1DescType)
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5598
5599 if (Ldtr.Attr.n.u1Present)
5600 { /* likely */ }
5601 else
5602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5603
5604 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5605 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5606 { /* likely */ }
5607 else
5608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5609 }
5610 }
5611
5612 /*
5613 * TR.
5614 */
5615 {
5616 CPUMSELREG Tr;
5617 Tr.Sel = pVmcs->GuestTr;
5618 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5619 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5620 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5621
5622 /* Selector. */
5623 if (!(Tr.Sel & X86_SEL_LDT))
5624 { /* likely */ }
5625 else
5626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5627
5628 /* Base. */
5629 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5630 {
5631 if (X86_IS_CANONICAL(Tr.u64Base))
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5635 }
5636
5637 /* Attributes. */
5638 /* Reserved bits (bits 31:17 and bits 11:8). */
5639 if (!(Tr.Attr.u & 0xfffe0f00))
5640 { /* likely */ }
5641 else
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5643
5644 if (!Tr.Attr.n.u1Unusable)
5645 { /* likely */ }
5646 else
5647 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5648
5649 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5650 || ( !fGstInLongMode
5651 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5652 { /* likely */ }
5653 else
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5655
5656 if (!Tr.Attr.n.u1DescType)
5657 { /* likely */ }
5658 else
5659 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5660
5661 if (Tr.Attr.n.u1Present)
5662 { /* likely */ }
5663 else
5664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5665
5666 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5667 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5668 { /* likely */ }
5669 else
5670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5671 }
5672
5673 NOREF(pszInstr);
5674 NOREF(pszFailure);
5675 return VINF_SUCCESS;
5676}
5677
5678
5679/**
5680 * Checks guest GDTR and IDTR as part of VM-entry.
5681 *
5682 * @param pVCpu The cross context virtual CPU structure.
5683 * @param pszInstr The VMX instruction name (for logging purposes).
5684 */
5685IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5686{
5687 /*
5688 * GDTR and IDTR.
5689 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5690 */
5691 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5692 const char *const pszFailure = "VM-exit";
5693
5694 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5695 {
5696 /* Base. */
5697 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5698 { /* likely */ }
5699 else
5700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5701
5702 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5703 { /* likely */ }
5704 else
5705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5706 }
5707
5708 /* Limit. */
5709 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5713
5714 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5715 { /* likely */ }
5716 else
5717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5718
5719 NOREF(pszInstr);
5720 NOREF(pszFailure);
5721 return VINF_SUCCESS;
5722}
5723
5724
5725/**
5726 * Checks guest RIP and RFLAGS as part of VM-entry.
5727 *
5728 * @param pVCpu The cross context virtual CPU structure.
5729 * @param pszInstr The VMX instruction name (for logging purposes).
5730 */
5731IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5732{
5733 /*
5734 * RIP and RFLAGS.
5735 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5736 */
5737 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5738 const char *const pszFailure = "VM-exit";
5739 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5740
5741 /* RIP. */
5742 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5743 {
5744 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5745 if ( !fGstInLongMode
5746 || !AttrCs.n.u1Long)
5747 {
5748 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5749 { /* likely */ }
5750 else
5751 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5752 }
5753
5754 if ( fGstInLongMode
5755 && AttrCs.n.u1Long)
5756 {
5757 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5758 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5759 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5763 }
5764 }
5765
5766 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5767 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5768 : pVmcs->u64GuestRFlags.s.Lo;
5769 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5770 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5771 { /* likely */ }
5772 else
5773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5774
5775 if ( fGstInLongMode
5776 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5777 {
5778 if (!(uGuestRFlags & X86_EFL_VM))
5779 { /* likely */ }
5780 else
5781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5782 }
5783
5784 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5785 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5786 {
5787 if (uGuestRFlags & X86_EFL_IF)
5788 { /* likely */ }
5789 else
5790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5791 }
5792
5793 NOREF(pszInstr);
5794 NOREF(pszFailure);
5795 return VINF_SUCCESS;
5796}
5797
5798
5799/**
5800 * Checks guest non-register state as part of VM-entry.
5801 *
5802 * @param pVCpu The cross context virtual CPU structure.
5803 * @param pszInstr The VMX instruction name (for logging purposes).
5804 */
5805IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5806{
5807 /*
5808 * Guest non-register state.
5809 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5810 */
5811 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5812 const char *const pszFailure = "VM-exit";
5813
5814 /*
5815 * Activity state.
5816 */
5817 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5818 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5819 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5820 { /* likely */ }
5821 else
5822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5823
5824 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5825 if ( !AttrSs.n.u2Dpl
5826 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5830
5831 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5832 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5833 {
5834 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5838 }
5839
5840 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5841 {
5842 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5843 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5844 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5845 switch (pVmcs->u32GuestActivityState)
5846 {
5847 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5848 {
5849 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5850 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5851 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5852 && ( uVector == X86_XCPT_DB
5853 || uVector == X86_XCPT_MC))
5854 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5855 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5856 { /* likely */ }
5857 else
5858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5859 break;
5860 }
5861
5862 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5863 {
5864 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5865 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5866 && uVector == X86_XCPT_MC))
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5870 break;
5871 }
5872
5873 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5874 default:
5875 break;
5876 }
5877 }
5878
5879 /*
5880 * Interruptibility state.
5881 */
5882 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5886
5887 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5888 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5889 { /* likely */ }
5890 else
5891 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5892
5893 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5894 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5895 { /* likely */ }
5896 else
5897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5898
5899 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5900 {
5901 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5902 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5903 {
5904 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5905 { /* likely */ }
5906 else
5907 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5908 }
5909 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5910 {
5911 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5912 { /* likely */ }
5913 else
5914 {
5915 /*
5916 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5917 * We update the VM-exit qualification only when blocking-by-STI is set
5918 * without blocking-by-MovSS being set. Although in practise it does not
5919 * make much difference since the order of checks are implementation defined.
5920 */
5921 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5922 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5924 }
5925
5926 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5927 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5931 }
5932 }
5933
5934 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5935 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5936 { /* likely */ }
5937 else
5938 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5939
5940 /* We don't support SGX yet. So enclave-interruption must not be set. */
5941 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5942 { /* likely */ }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5945
5946 /*
5947 * Pending debug exceptions.
5948 */
5949 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5950 ? pVmcs->u64GuestPendingDbgXcpt.u
5951 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5952 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5956
5957 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5958 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5959 {
5960 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5961 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5962 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5964
5965 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5966 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5967 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5969 }
5970
5971 /* We don't support RTM (Real-time Transactional Memory) yet. */
5972 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5976
5977 /*
5978 * VMCS link pointer.
5979 */
5980 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5981 {
5982 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5983 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5984 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5985 { /* likely */ }
5986 else
5987 {
5988 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5990 }
5991
5992 /* Validate the address. */
5993 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5994 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5995 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5996 { /* likely */ }
5997 else
5998 {
5999 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6001 }
6002
6003 /* Read the VMCS-link pointer from guest memory. */
6004 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6005 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6006 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
6007 if (RT_SUCCESS(rc))
6008 { /* likely */ }
6009 else
6010 {
6011 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6013 }
6014
6015 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6016 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6017 { /* likely */ }
6018 else
6019 {
6020 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6021 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6022 }
6023
6024 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6025 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6026 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6027 { /* likely */ }
6028 else
6029 {
6030 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6032 }
6033
6034 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6035 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6036 }
6037
6038 NOREF(pszInstr);
6039 NOREF(pszFailure);
6040 return VINF_SUCCESS;
6041}
6042
6043
6044/**
6045 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6046 * VM-entry.
6047 *
6048 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6049 * @param pVCpu The cross context virtual CPU structure.
6050 * @param pszInstr The VMX instruction name (for logging purposes).
6051 * @param pVmcs Pointer to the virtual VMCS.
6052 */
6053IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6054{
6055 /*
6056 * Check PDPTEs.
6057 * See Intel spec. 4.4.1 "PDPTE Registers".
6058 */
6059 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6060 const char *const pszFailure = "VM-exit";
6061
6062 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6063 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6064 if (RT_SUCCESS(rc))
6065 {
6066 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6067 {
6068 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6069 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6070 { /* likely */ }
6071 else
6072 {
6073 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6074 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6076 }
6077 }
6078 }
6079 else
6080 {
6081 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6083 }
6084
6085 NOREF(pszFailure);
6086 NOREF(pszInstr);
6087 return rc;
6088}
6089
6090
6091/**
6092 * Checks guest PDPTEs as part of VM-entry.
6093 *
6094 * @param pVCpu The cross context virtual CPU structure.
6095 * @param pszInstr The VMX instruction name (for logging purposes).
6096 */
6097IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6098{
6099 /*
6100 * Guest PDPTEs.
6101 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6102 */
6103 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6104 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6105
6106 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6107 int rc;
6108 if ( !fGstInLongMode
6109 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6110 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6111 {
6112 /*
6113 * We don't support nested-paging for nested-guests yet.
6114 *
6115 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6116 * rather we need to check the PDPTEs referenced by the guest CR3.
6117 */
6118 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6119 }
6120 else
6121 rc = VINF_SUCCESS;
6122 return rc;
6123}
6124
6125
6126/**
6127 * Checks guest-state as part of VM-entry.
6128 *
6129 * @returns VBox status code.
6130 * @param pVCpu The cross context virtual CPU structure.
6131 * @param pszInstr The VMX instruction name (for logging purposes).
6132 */
6133IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6134{
6135 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6136 if (RT_SUCCESS(rc))
6137 {
6138 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6139 if (RT_SUCCESS(rc))
6140 {
6141 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6142 if (RT_SUCCESS(rc))
6143 {
6144 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6145 if (RT_SUCCESS(rc))
6146 {
6147 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6148 if (RT_SUCCESS(rc))
6149 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6150 }
6151 }
6152 }
6153 }
6154 return rc;
6155}
6156
6157
6158/**
6159 * Checks host-state as part of VM-entry.
6160 *
6161 * @returns VBox status code.
6162 * @param pVCpu The cross context virtual CPU structure.
6163 * @param pszInstr The VMX instruction name (for logging purposes).
6164 */
6165IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6166{
6167 /*
6168 * Host Control Registers and MSRs.
6169 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6170 */
6171 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6172 const char * const pszFailure = "VMFail";
6173
6174 /* CR0 reserved bits. */
6175 {
6176 /* CR0 MB1 bits. */
6177 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6178 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6179 { /* likely */ }
6180 else
6181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6182
6183 /* CR0 MBZ bits. */
6184 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6185 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6186 { /* likely */ }
6187 else
6188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6189 }
6190
6191 /* CR4 reserved bits. */
6192 {
6193 /* CR4 MB1 bits. */
6194 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6195 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6196 { /* likely */ }
6197 else
6198 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6199
6200 /* CR4 MBZ bits. */
6201 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6202 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6203 { /* likely */ }
6204 else
6205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6206 }
6207
6208 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6209 {
6210 /* CR3 reserved bits. */
6211 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6215
6216 /* SYSENTER ESP and SYSENTER EIP. */
6217 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6218 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6222 }
6223
6224 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6225 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6226
6227 /* PAT MSR. */
6228 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6229 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6233
6234 /* EFER MSR. */
6235 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6236 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6237 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6241
6242 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6243 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6244 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6245 if ( fHostInLongMode == fHostLma
6246 && fHostInLongMode == fHostLme)
6247 { /* likely */ }
6248 else
6249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6250
6251 /*
6252 * Host Segment and Descriptor-Table Registers.
6253 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6254 */
6255 /* Selector RPL and TI. */
6256 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6257 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6258 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6259 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6260 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6261 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6262 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6266
6267 /* CS and TR selectors cannot be 0. */
6268 if ( pVmcs->HostCs
6269 && pVmcs->HostTr)
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6273
6274 /* SS cannot be 0 if 32-bit host. */
6275 if ( fHostInLongMode
6276 || pVmcs->HostSs)
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6280
6281 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6282 {
6283 /* FS, GS, GDTR, IDTR, TR base address. */
6284 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6285 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6286 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6287 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6288 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6289 { /* likely */ }
6290 else
6291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6292 }
6293
6294 /*
6295 * Host address-space size for 64-bit CPUs.
6296 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6297 */
6298 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6299 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6300 {
6301 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6302
6303 /* Logical processor in IA-32e mode. */
6304 if (fCpuInLongMode)
6305 {
6306 if (fHostInLongMode)
6307 {
6308 /* PAE must be set. */
6309 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6310 { /* likely */ }
6311 else
6312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6313
6314 /* RIP must be canonical. */
6315 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6316 { /* likely */ }
6317 else
6318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6319 }
6320 else
6321 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6322 }
6323 else
6324 {
6325 /* Logical processor is outside IA-32e mode. */
6326 if ( !fGstInLongMode
6327 && !fHostInLongMode)
6328 {
6329 /* PCIDE should not be set. */
6330 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6331 { /* likely */ }
6332 else
6333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6334
6335 /* The high 32-bits of RIP MBZ. */
6336 if (!pVmcs->u64HostRip.s.Hi)
6337 { /* likely */ }
6338 else
6339 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6340 }
6341 else
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6343 }
6344 }
6345 else
6346 {
6347 /* Host address-space size for 32-bit CPUs. */
6348 if ( !fGstInLongMode
6349 && !fHostInLongMode)
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6353 }
6354
6355 NOREF(pszInstr);
6356 NOREF(pszFailure);
6357 return VINF_SUCCESS;
6358}
6359
6360
6361/**
6362 * Checks VM-entry controls fields as part of VM-entry.
6363 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6364 *
6365 * @returns VBox status code.
6366 * @param pVCpu The cross context virtual CPU structure.
6367 * @param pszInstr The VMX instruction name (for logging purposes).
6368 */
6369IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6370{
6371 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6372 const char * const pszFailure = "VMFail";
6373
6374 /* VM-entry controls. */
6375 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6376 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6377 { /* likely */ }
6378 else
6379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6380
6381 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6382 { /* likely */ }
6383 else
6384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6385
6386 /* Event injection. */
6387 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6388 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6389 {
6390 /* Type and vector. */
6391 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6392 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6393 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6394 if ( !uRsvd
6395 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6396 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6397 { /* likely */ }
6398 else
6399 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6400
6401 /* Exception error code. */
6402 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6403 {
6404 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6405 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6406 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6410
6411 /* Exceptions that provide an error code. */
6412 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6413 && ( uVector == X86_XCPT_DF
6414 || uVector == X86_XCPT_TS
6415 || uVector == X86_XCPT_NP
6416 || uVector == X86_XCPT_SS
6417 || uVector == X86_XCPT_GP
6418 || uVector == X86_XCPT_PF
6419 || uVector == X86_XCPT_AC))
6420 { /* likely */ }
6421 else
6422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6423
6424 /* Exception error-code reserved bits. */
6425 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6426 { /* likely */ }
6427 else
6428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6429
6430 /* Injecting a software interrupt, software exception or privileged software exception. */
6431 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6432 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6433 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6434 {
6435 /* Instruction length must be in the range 0-15. */
6436 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6437 { /* likely */ }
6438 else
6439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6440
6441 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6442 if ( pVmcs->u32EntryInstrLen == 0
6443 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6445 }
6446 }
6447 }
6448
6449 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6450 if (pVmcs->u32EntryMsrLoadCount)
6451 {
6452 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6453 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6454 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6455 { /* likely */ }
6456 else
6457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6458 }
6459
6460 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6461 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6462
6463 NOREF(pszInstr);
6464 NOREF(pszFailure);
6465 return VINF_SUCCESS;
6466}
6467
6468
6469/**
6470 * Checks VM-exit controls fields as part of VM-entry.
6471 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6472 *
6473 * @returns VBox status code.
6474 * @param pVCpu The cross context virtual CPU structure.
6475 * @param pszInstr The VMX instruction name (for logging purposes).
6476 */
6477IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6478{
6479 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6480 const char * const pszFailure = "VMFail";
6481
6482 /* VM-exit controls. */
6483 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6484 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6485 { /* likely */ }
6486 else
6487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6488
6489 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6490 { /* likely */ }
6491 else
6492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6493
6494 /* Save preemption timer without activating it. */
6495 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6496 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6497 { /* likely */ }
6498 else
6499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6500
6501 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6502 if (pVmcs->u32ExitMsrStoreCount)
6503 {
6504 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6505 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6506 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6507 { /* likely */ }
6508 else
6509 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6510 }
6511
6512 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6513 if (pVmcs->u32ExitMsrLoadCount)
6514 {
6515 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6516 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6517 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6518 { /* likely */ }
6519 else
6520 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6521 }
6522
6523 NOREF(pszInstr);
6524 NOREF(pszFailure);
6525 return VINF_SUCCESS;
6526}
6527
6528
6529/**
6530 * Checks VM-execution controls fields as part of VM-entry.
6531 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6532 *
6533 * @returns VBox status code.
6534 * @param pVCpu The cross context virtual CPU structure.
6535 * @param pszInstr The VMX instruction name (for logging purposes).
6536 *
6537 * @remarks This may update secondary-processor based VM-execution control fields
6538 * in the current VMCS if necessary.
6539 */
6540IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6541{
6542 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6543 const char * const pszFailure = "VMFail";
6544
6545 /* Pin-based VM-execution controls. */
6546 {
6547 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6548 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6549 { /* likely */ }
6550 else
6551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6552
6553 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6557 }
6558
6559 /* Processor-based VM-execution controls. */
6560 {
6561 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6562 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6563 { /* likely */ }
6564 else
6565 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6566
6567 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6568 { /* likely */ }
6569 else
6570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6571 }
6572
6573 /* Secondary processor-based VM-execution controls. */
6574 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6575 {
6576 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6577 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6578 { /* likely */ }
6579 else
6580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6581
6582 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6583 { /* likely */ }
6584 else
6585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6586 }
6587 else
6588 Assert(!pVmcs->u32ProcCtls2);
6589
6590 /* CR3-target count. */
6591 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6592 { /* likely */ }
6593 else
6594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6595
6596 /* I/O bitmaps physical addresses. */
6597 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6598 {
6599 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6600 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6601 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6602 { /* likely */ }
6603 else
6604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6605
6606 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6607 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6608 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6609 { /* likely */ }
6610 else
6611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6612 }
6613
6614 /* MSR bitmap physical address. */
6615 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6616 {
6617 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6618 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6619 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6620 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6621 { /* likely */ }
6622 else
6623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6624
6625 /* Read the MSR bitmap. */
6626 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6627 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6628 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6629 if (RT_SUCCESS(rc))
6630 { /* likely */ }
6631 else
6632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6633 }
6634
6635 /* TPR shadow related controls. */
6636 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6637 {
6638 /* Virtual-APIC page physical address. */
6639 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6640 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6641 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6642 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6643 { /* likely */ }
6644 else
6645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6646
6647 /* TPR threshold without virtual-interrupt delivery. */
6648 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6649 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6651
6652 /* TPR threshold and VTPR. */
6653 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6654 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6655 {
6656 /* Read the VTPR from the virtual-APIC page. */
6657 uint8_t u8VTpr;
6658 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6659 if (RT_SUCCESS(rc))
6660 { /* likely */ }
6661 else
6662 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6663
6664 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6665 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6666 { /* likely */ }
6667 else
6668 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6669 }
6670 }
6671 else
6672 {
6673 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6674 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6675 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6676 { /* likely */ }
6677 else
6678 {
6679 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6681 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6683 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6685 }
6686 }
6687
6688 /* NMI exiting and virtual-NMIs. */
6689 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6690 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6691 { /* likely */ }
6692 else
6693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6694
6695 /* Virtual-NMIs and NMI-window exiting. */
6696 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6697 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6698 { /* likely */ }
6699 else
6700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6701
6702 /* Virtualize APIC accesses. */
6703 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6704 {
6705 /* APIC-access physical address. */
6706 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6707 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6708 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6709 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6710 { /* likely */ }
6711 else
6712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6713
6714 /*
6715 * Disallow APIC-access page and virtual-APIC page from being the same address.
6716 * Note! This is not an Intel requirement, but one imposed by our implementation.
6717 */
6718 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6719 * redirecting accesses between the APIC-access page and the virtual-APIC
6720 * page. If any nested hypervisor requires this, we can implement it later. */
6721 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6722 {
6723 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6724 if (GCPhysVirtApic != GCPhysApicAccess)
6725 { /* likely */ }
6726 else
6727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6728 }
6729
6730 /*
6731 * Register the handler for the APIC-access page.
6732 *
6733 * We don't deregister the APIC-access page handler during the VM-exit as a different
6734 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6735 *
6736 * We leave the page registered until the first access that happens outside VMX non-root
6737 * mode. Guest software is allowed to access structures such as the APIC-access page
6738 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6739 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6740 *
6741 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6742 */
6743 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6744 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6745 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6746 if (RT_SUCCESS(rc))
6747 { /* likely */ }
6748 else
6749 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6750 }
6751
6752 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6753 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6754 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6755 { /* likely */ }
6756 else
6757 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6758
6759 /* Virtual-interrupt delivery requires external interrupt exiting. */
6760 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6761 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6762 { /* likely */ }
6763 else
6764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6765
6766 /* VPID. */
6767 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6768 || pVmcs->u16Vpid != 0)
6769 { /* likely */ }
6770 else
6771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6772
6773 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6774 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6775 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6776 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6777 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6778 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6779 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6780
6781 /* VMCS shadowing. */
6782 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6783 {
6784 /* VMREAD-bitmap physical address. */
6785 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6786 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6787 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6788 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6789 { /* likely */ }
6790 else
6791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6792
6793 /* VMWRITE-bitmap physical address. */
6794 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6795 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6796 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6797 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6798 { /* likely */ }
6799 else
6800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6801
6802 /* Read the VMREAD-bitmap. */
6803 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6804 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6805 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6806 if (RT_SUCCESS(rc))
6807 { /* likely */ }
6808 else
6809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6810
6811 /* Read the VMWRITE-bitmap. */
6812 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6813 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6814 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6815 if (RT_SUCCESS(rc))
6816 { /* likely */ }
6817 else
6818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6819 }
6820
6821 NOREF(pszInstr);
6822 NOREF(pszFailure);
6823 return VINF_SUCCESS;
6824}
6825
6826
6827/**
6828 * Loads the guest control registers, debug register and some MSRs as part of
6829 * VM-entry.
6830 *
6831 * @param pVCpu The cross context virtual CPU structure.
6832 */
6833IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6834{
6835 /*
6836 * Load guest control registers, debug registers and MSRs.
6837 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6838 */
6839 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6840
6841 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6842 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6843 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6844 CPUMSetGuestCR0(pVCpu, uGstCr0);
6845 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6846 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6847
6848 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6849 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6850
6851 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6852 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6853 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6854
6855 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6856 {
6857 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6858
6859 /* EFER MSR. */
6860 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6861 {
6862 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6863 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6864 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6865 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6866 if (fGstInLongMode)
6867 {
6868 /* If the nested-guest is in long mode, LMA and LME are both set. */
6869 Assert(fGstPaging);
6870 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6871 }
6872 else
6873 {
6874 /*
6875 * If the nested-guest is outside long mode:
6876 * - With paging: LMA is cleared, LME is cleared.
6877 * - Without paging: LMA is cleared, LME is left unmodified.
6878 */
6879 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6880 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6881 }
6882 }
6883 /* else: see below. */
6884 }
6885
6886 /* PAT MSR. */
6887 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6888 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6889
6890 /* EFER MSR. */
6891 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6892 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6893
6894 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6895 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6896
6897 /* We don't support IA32_BNDCFGS MSR yet. */
6898 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6899
6900 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6901}
6902
6903
6904/**
6905 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6906 *
6907 * @param pVCpu The cross context virtual CPU structure.
6908 */
6909IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6910{
6911 /*
6912 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6913 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6914 */
6915 /* CS, SS, ES, DS, FS, GS. */
6916 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6917 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6918 {
6919 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6920 CPUMSELREG VmcsSelReg;
6921 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6922 AssertRC(rc); NOREF(rc);
6923 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6924 {
6925 pGstSelReg->Sel = VmcsSelReg.Sel;
6926 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6927 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6928 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6929 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6930 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6931 }
6932 else
6933 {
6934 pGstSelReg->Sel = VmcsSelReg.Sel;
6935 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6936 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6937 switch (iSegReg)
6938 {
6939 case X86_SREG_CS:
6940 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6941 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6942 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6943 break;
6944
6945 case X86_SREG_SS:
6946 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6947 pGstSelReg->u32Limit = 0;
6948 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6949 break;
6950
6951 case X86_SREG_ES:
6952 case X86_SREG_DS:
6953 pGstSelReg->u64Base = 0;
6954 pGstSelReg->u32Limit = 0;
6955 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6956 break;
6957
6958 case X86_SREG_FS:
6959 case X86_SREG_GS:
6960 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6961 pGstSelReg->u32Limit = 0;
6962 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6963 break;
6964 }
6965 Assert(pGstSelReg->Attr.n.u1Unusable);
6966 }
6967 }
6968
6969 /* LDTR. */
6970 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6971 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6972 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6973 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6974 {
6975 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6976 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6977 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6978 }
6979 else
6980 {
6981 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6982 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6983 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6984 }
6985
6986 /* TR. */
6987 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6988 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6989 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6990 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6991 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6992 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6993 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6994
6995 /* GDTR. */
6996 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6997 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6998
6999 /* IDTR. */
7000 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
7001 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
7002}
7003
7004
7005/**
7006 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
7007 *
7008 * @returns VBox status code.
7009 * @param pVCpu The cross context virtual CPU structure.
7010 * @param pszInstr The VMX instruction name (for logging purposes).
7011 */
7012IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
7013{
7014 /*
7015 * Load guest MSRs.
7016 * See Intel spec. 26.4 "Loading MSRs".
7017 */
7018 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7019 const char *const pszFailure = "VM-exit";
7020
7021 /*
7022 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7023 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7024 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7025 */
7026 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7027 if (!cMsrs)
7028 return VINF_SUCCESS;
7029
7030 /*
7031 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7032 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7033 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7034 */
7035 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7036 if (fIsMsrCountValid)
7037 { /* likely */ }
7038 else
7039 {
7040 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7042 }
7043
7044 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7045 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7046 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7047 if (RT_SUCCESS(rc))
7048 {
7049 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7050 Assert(pMsr);
7051 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7052 {
7053 if ( !pMsr->u32Reserved
7054 && pMsr->u32Msr != MSR_K8_FS_BASE
7055 && pMsr->u32Msr != MSR_K8_GS_BASE
7056 && pMsr->u32Msr != MSR_K6_EFER
7057 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7058 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7059 {
7060 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7061 if (rcStrict == VINF_SUCCESS)
7062 continue;
7063
7064 /*
7065 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7066 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7067 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7068 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7069 * MSR in ring-0 if possible, or come up with a better, generic solution.
7070 */
7071 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7072 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7073 ? kVmxVDiag_Vmentry_MsrLoadRing3
7074 : kVmxVDiag_Vmentry_MsrLoad;
7075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7076 }
7077 else
7078 {
7079 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7081 }
7082 }
7083 }
7084 else
7085 {
7086 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7087 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7088 }
7089
7090 NOREF(pszInstr);
7091 NOREF(pszFailure);
7092 return VINF_SUCCESS;
7093}
7094
7095
7096/**
7097 * Loads the guest-state non-register state as part of VM-entry.
7098 *
7099 * @returns VBox status code.
7100 * @param pVCpu The cross context virtual CPU structure.
7101 *
7102 * @remarks This must be called only after loading the nested-guest register state
7103 * (especially nested-guest RIP).
7104 */
7105IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7106{
7107 /*
7108 * Load guest non-register state.
7109 * See Intel spec. 26.6 "Special Features of VM Entry"
7110 */
7111 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7112
7113 /*
7114 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7115 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7116 *
7117 * See Intel spec. 26.6.1 "Interruptibility State".
7118 */
7119 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7120 if ( !fEntryVectoring
7121 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7122 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7123 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7124 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7125
7126 /* NMI blocking. */
7127 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7128 {
7129 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7130 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7131 else
7132 {
7133 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7134 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7135 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7136 }
7137 }
7138 else
7139 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7140
7141 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7142
7143 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7144 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7145
7146 /* VPID is irrelevant. We don't support VPID yet. */
7147
7148 /* Clear address-range monitoring. */
7149 EMMonitorWaitClear(pVCpu);
7150}
7151
7152
7153/**
7154 * Loads the guest-state as part of VM-entry.
7155 *
7156 * @returns VBox status code.
7157 * @param pVCpu The cross context virtual CPU structure.
7158 * @param pszInstr The VMX instruction name (for logging purposes).
7159 *
7160 * @remarks This must be done after all the necessary steps prior to loading of
7161 * guest-state (e.g. checking various VMCS state).
7162 */
7163IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7164{
7165 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7166 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7167
7168 /*
7169 * Load guest RIP, RSP and RFLAGS.
7170 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7171 */
7172 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7173 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7174 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7175 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7176
7177 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7178 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7179 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7180
7181 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7182
7183 NOREF(pszInstr);
7184 return VINF_SUCCESS;
7185}
7186
7187
7188/**
7189 * Returns whether there are is a pending debug exception on VM-entry.
7190 *
7191 * @param pVCpu The cross context virtual CPU structure.
7192 * @param pszInstr The VMX instruction name (for logging purposes).
7193 */
7194IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7195{
7196 /*
7197 * Pending debug exceptions.
7198 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7199 */
7200 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7201 Assert(pVmcs);
7202
7203 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7204 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7205 if (fPendingDbgXcpt)
7206 {
7207 uint8_t uEntryIntInfoType;
7208 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7209 if (fEntryVectoring)
7210 {
7211 switch (uEntryIntInfoType)
7212 {
7213 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7214 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7215 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7216 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7217 fPendingDbgXcpt = false;
7218 break;
7219
7220 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7221 {
7222 /*
7223 * Whether the pending debug exception for software exceptions other than
7224 * #BP and #OF is delivered after injecting the exception or is discard
7225 * is CPU implementation specific. We will discard them (easier).
7226 */
7227 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7228 if ( uVector != X86_XCPT_BP
7229 && uVector != X86_XCPT_OF)
7230 fPendingDbgXcpt = false;
7231 RT_FALL_THRU();
7232 }
7233 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7234 {
7235 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7236 fPendingDbgXcpt = false;
7237 break;
7238 }
7239 }
7240 }
7241 else
7242 {
7243 /*
7244 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7245 * pending debug exception is held pending or is discarded is CPU implementation
7246 * specific. We will discard them (easier).
7247 */
7248 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7249 fPendingDbgXcpt = false;
7250
7251 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7252 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7253 fPendingDbgXcpt = false;
7254 }
7255 }
7256
7257 NOREF(pszInstr);
7258 return fPendingDbgXcpt;
7259}
7260
7261
7262/**
7263 * Set up the monitor-trap flag (MTF).
7264 *
7265 * @param pVCpu The cross context virtual CPU structure.
7266 * @param pszInstr The VMX instruction name (for logging purposes).
7267 */
7268IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7269{
7270 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7271 Assert(pVmcs);
7272 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7273 {
7274 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7275 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7276 }
7277 else
7278 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7279 NOREF(pszInstr);
7280}
7281
7282
7283/**
7284 * Set up the VMX-preemption timer.
7285 *
7286 * @param pVCpu The cross context virtual CPU structure.
7287 * @param pszInstr The VMX instruction name (for logging purposes).
7288 */
7289IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7290{
7291 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7292 Assert(pVmcs);
7293 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7294 {
7295 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7296 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7297 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7298
7299 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7300 }
7301 else
7302 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7303
7304 NOREF(pszInstr);
7305}
7306
7307
7308/**
7309 * Injects an event using TRPM given a VM-entry interruption info. and related
7310 * fields.
7311 *
7312 * @returns VBox status code.
7313 * @param pVCpu The cross context virtual CPU structure.
7314 * @param uEntryIntInfo The VM-entry interruption info.
7315 * @param uErrCode The error code associated with the event if any.
7316 * @param cbInstr The VM-entry instruction length (for software
7317 * interrupts and software exceptions). Pass 0
7318 * otherwise.
7319 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7320 */
7321IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7322 RTGCUINTPTR GCPtrFaultAddress)
7323{
7324 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7325
7326 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7327 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7328 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7329
7330 TRPMEVENT enmTrapType;
7331 switch (uType)
7332 {
7333 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7334 enmTrapType = TRPM_HARDWARE_INT;
7335 break;
7336
7337 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7338 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7339 enmTrapType = TRPM_TRAP;
7340 break;
7341
7342 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7343 enmTrapType = TRPM_SOFTWARE_INT;
7344 break;
7345
7346 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7347 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7348 enmTrapType = TRPM_SOFTWARE_INT;
7349 break;
7350
7351 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7352 Assert(uVector == X86_XCPT_DB);
7353 enmTrapType = TRPM_SOFTWARE_INT;
7354 break;
7355
7356 default:
7357 /* Shouldn't really happen. */
7358 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7359 break;
7360 }
7361
7362 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7363 AssertRCReturn(rc, rc);
7364
7365 if (fErrCodeValid)
7366 TRPMSetErrorCode(pVCpu, uErrCode);
7367
7368 if ( enmTrapType == TRPM_TRAP
7369 && uVector == X86_XCPT_PF)
7370 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7371 else if (enmTrapType == TRPM_SOFTWARE_INT)
7372 TRPMSetInstrLength(pVCpu, cbInstr);
7373
7374 return VINF_SUCCESS;
7375}
7376
7377
7378/**
7379 * Performs event injection (if any) as part of VM-entry.
7380 *
7381 * @param pVCpu The cross context virtual CPU structure.
7382 * @param pszInstr The VMX instruction name (for logging purposes).
7383 */
7384IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7385{
7386 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7387
7388 /*
7389 * Inject events.
7390 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7391 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7392 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7393 * the actually delivery of this event.
7394 *
7395 * See Intel spec. 26.5 "Event Injection".
7396 */
7397 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7398 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7399
7400 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7401 if (fEntryIntInfoValid)
7402 {
7403 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7404 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7405 {
7406 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7407 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7408 return VINF_SUCCESS;
7409 }
7410
7411 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7412 pVCpu->cpum.GstCtx.cr2);
7413 if (RT_SUCCESS(rc))
7414 {
7415 /*
7416 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7417 *
7418 * However, we do it here on VM-entry because while it continues to not be visible to
7419 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7420 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7421 * information field.
7422 *
7423 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7424 */
7425 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7426 }
7427 return rc;
7428 }
7429
7430 /*
7431 * Inject any pending guest debug exception.
7432 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7433 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7434 */
7435 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7436 if (fPendingDbgXcpt)
7437 {
7438 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7439 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7440 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7441 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7442 0 /* GCPtrFaultAddress */);
7443 }
7444
7445 NOREF(pszInstr);
7446 return VINF_SUCCESS;
7447}
7448
7449
7450/**
7451 * Initializes all read-only VMCS fields as part of VM-entry.
7452 *
7453 * @param pVCpu The cross context virtual CPU structure.
7454 */
7455IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7456{
7457 /*
7458 * Any VMCS field which we do not establish on every VM-exit but may potentially
7459 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7460 * specified to be undefined needs to be initialized here.
7461 *
7462 * Thus, it is especially important to clear the VM-exit qualification field
7463 * since it must be zero for VM-exits where it is not used. Similarly, the
7464 * VM-exit interruption information field's valid bit needs to be cleared for
7465 * the same reasons.
7466 */
7467 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7468 Assert(pVmcs);
7469
7470 /* 16-bit (none currently). */
7471 /* 32-bit. */
7472 pVmcs->u32RoVmInstrError = 0;
7473 pVmcs->u32RoExitReason = 0;
7474 pVmcs->u32RoExitIntInfo = 0;
7475 pVmcs->u32RoExitIntErrCode = 0;
7476 pVmcs->u32RoIdtVectoringInfo = 0;
7477 pVmcs->u32RoIdtVectoringErrCode = 0;
7478 pVmcs->u32RoExitInstrLen = 0;
7479 pVmcs->u32RoExitInstrInfo = 0;
7480
7481 /* 64-bit. */
7482 pVmcs->u64RoGuestPhysAddr.u = 0;
7483
7484 /* Natural-width. */
7485 pVmcs->u64RoExitQual.u = 0;
7486 pVmcs->u64RoIoRcx.u = 0;
7487 pVmcs->u64RoIoRsi.u = 0;
7488 pVmcs->u64RoIoRdi.u = 0;
7489 pVmcs->u64RoIoRip.u = 0;
7490 pVmcs->u64RoGuestLinearAddr.u = 0;
7491}
7492
7493
7494/**
7495 * VMLAUNCH/VMRESUME instruction execution worker.
7496 *
7497 * @returns Strict VBox status code.
7498 * @param pVCpu The cross context virtual CPU structure.
7499 * @param cbInstr The instruction length in bytes.
7500 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7501 * VMXINSTRID_VMRESUME).
7502 *
7503 * @remarks Common VMX instruction checks are already expected to by the caller,
7504 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7505 */
7506IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7507{
7508# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7509 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7510 return VINF_EM_RAW_EMULATE_INSTR;
7511# else
7512 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7513 || uInstrId == VMXINSTRID_VMRESUME);
7514 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7515
7516 /* Nested-guest intercept. */
7517 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7518 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7519
7520 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7521
7522 /*
7523 * Basic VM-entry checks.
7524 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7525 * The checks following that do not have to follow a specific order.
7526 *
7527 * See Intel spec. 26.1 "Basic VM-entry Checks".
7528 */
7529
7530 /* CPL. */
7531 if (pVCpu->iem.s.uCpl == 0)
7532 { /* likely */ }
7533 else
7534 {
7535 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7536 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7537 return iemRaiseGeneralProtectionFault0(pVCpu);
7538 }
7539
7540 /* Current VMCS valid. */
7541 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7542 { /* likely */ }
7543 else
7544 {
7545 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7547 iemVmxVmFailInvalid(pVCpu);
7548 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7549 return VINF_SUCCESS;
7550 }
7551
7552 /* Current VMCS is not a shadow VMCS. */
7553 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7554 { /* likely */ }
7555 else
7556 {
7557 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7559 iemVmxVmFailInvalid(pVCpu);
7560 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7561 return VINF_SUCCESS;
7562 }
7563
7564 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7565 * use block-by-STI here which is not quite correct. */
7566 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7567 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7568 { /* likely */ }
7569 else
7570 {
7571 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7572 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7573 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7574 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7575 return VINF_SUCCESS;
7576 }
7577
7578 if (uInstrId == VMXINSTRID_VMLAUNCH)
7579 {
7580 /* VMLAUNCH with non-clear VMCS. */
7581 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7582 { /* likely */ }
7583 else
7584 {
7585 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7587 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7588 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7589 return VINF_SUCCESS;
7590 }
7591 }
7592 else
7593 {
7594 /* VMRESUME with non-launched VMCS. */
7595 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7596 { /* likely */ }
7597 else
7598 {
7599 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7600 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7601 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7602 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7603 return VINF_SUCCESS;
7604 }
7605 }
7606
7607 /*
7608 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7609 * while entering VMX non-root mode. We do some of this while checking VM-execution
7610 * controls. The guest hypervisor should not make assumptions and cannot expect
7611 * predictable behavior if changes to these structures are made in guest memory while
7612 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7613 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7614 *
7615 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7616 */
7617 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7618 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7619 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7620 if (RT_SUCCESS(rc))
7621 {
7622 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7623 if (RT_SUCCESS(rc))
7624 {
7625 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7626 if (RT_SUCCESS(rc))
7627 {
7628 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7629 if (RT_SUCCESS(rc))
7630 {
7631 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7632 iemVmxVmentryInitReadOnlyFields(pVCpu);
7633
7634 /*
7635 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7636 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7637 * VM-exit when required.
7638 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7639 */
7640 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7641
7642 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7643 if (RT_SUCCESS(rc))
7644 {
7645 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7646 if (RT_SUCCESS(rc))
7647 {
7648 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7649 if (RT_SUCCESS(rc))
7650 {
7651 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7652
7653 /* VMLAUNCH instruction must update the VMCS launch state. */
7654 if (uInstrId == VMXINSTRID_VMLAUNCH)
7655 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7656
7657 /* Perform the VMX transition (PGM updates). */
7658 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7659 if (rcStrict == VINF_SUCCESS)
7660 { /* likely */ }
7661 else if (RT_SUCCESS(rcStrict))
7662 {
7663 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7664 VBOXSTRICTRC_VAL(rcStrict)));
7665 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7666 }
7667 else
7668 {
7669 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7670 return rcStrict;
7671 }
7672
7673 /* We've now entered nested-guest execution. */
7674 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7675
7676 /*
7677 * The priority of potential VM-exits during VM-entry is important.
7678 * The priorities of VM-exits and events are listed from highest
7679 * to lowest as follows:
7680 *
7681 * 1. Event injection.
7682 * 2. Trap on task-switch (T flag set in TSS).
7683 * 3. TPR below threshold / APIC-write.
7684 * 4. SMI, INIT.
7685 * 5. MTF exit.
7686 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7687 * 7. VMX-preemption timer.
7688 * 9. NMI-window exit.
7689 * 10. NMI injection.
7690 * 11. Interrupt-window exit.
7691 * 12. Virtual-interrupt injection.
7692 * 13. Interrupt injection.
7693 * 14. Process next instruction (fetch, decode, execute).
7694 */
7695
7696 /* Setup the VMX-preemption timer. */
7697 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7698
7699 /* Setup monitor-trap flag. */
7700 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7701
7702 /* Now that we've switched page tables, we can go ahead and inject any event. */
7703 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7704 if (RT_SUCCESS(rcStrict))
7705 {
7706 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7707# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7708 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7709 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7710 if (rcSched != VINF_SUCCESS)
7711 iemSetPassUpStatus(pVCpu, rcSched);
7712# endif
7713 return VINF_SUCCESS;
7714 }
7715
7716 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7717 return rcStrict;
7718 }
7719 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7720 }
7721 }
7722 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7723 }
7724
7725 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7726 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7727 return VINF_SUCCESS;
7728 }
7729 }
7730 }
7731
7732 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7733 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7734 return VINF_SUCCESS;
7735# endif
7736}
7737
7738
7739/**
7740 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7741 * (causes a VM-exit) or not.
7742 *
7743 * @returns @c true if the instruction is intercepted, @c false otherwise.
7744 * @param pVCpu The cross context virtual CPU structure.
7745 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7746 * VMX_EXIT_WRMSR).
7747 * @param idMsr The MSR.
7748 */
7749IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7750{
7751 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7752 Assert( uExitReason == VMX_EXIT_RDMSR
7753 || uExitReason == VMX_EXIT_WRMSR);
7754
7755 /* Consult the MSR bitmap if the feature is supported. */
7756 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7757 Assert(pVmcs);
7758 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7759 {
7760 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7761 uint32_t fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7762 if (uExitReason == VMX_EXIT_RDMSR)
7763 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7764 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7765 }
7766
7767 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7768 return true;
7769}
7770
7771
7772/**
7773 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7774 * intercepted (causes a VM-exit) or not.
7775 *
7776 * @returns @c true if the instruction is intercepted, @c false otherwise.
7777 * @param pVCpu The cross context virtual CPU structure.
7778 * @param u64FieldEnc The VMCS field encoding.
7779 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7780 * VMX_EXIT_VMREAD).
7781 */
7782IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7783{
7784 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7785 Assert( uExitReason == VMX_EXIT_VMREAD
7786 || uExitReason == VMX_EXIT_VMWRITE);
7787
7788 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7789 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7790 return true;
7791
7792 /*
7793 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7794 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7795 */
7796 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7797 return true;
7798
7799 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7800 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7801 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7802 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7803 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7804 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7805 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7806 pbBitmap += (u32FieldEnc >> 3);
7807 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7808 return true;
7809
7810 return false;
7811}
7812
7813
7814/**
7815 * VMREAD common (memory/register) instruction execution worker
7816 *
7817 * @returns Strict VBox status code.
7818 * @param pVCpu The cross context virtual CPU structure.
7819 * @param cbInstr The instruction length in bytes.
7820 * @param pu64Dst Where to write the VMCS value (only updated when
7821 * VINF_SUCCESS is returned).
7822 * @param u64FieldEnc The VMCS field encoding.
7823 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7824 * be NULL.
7825 */
7826IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7827 PCVMXVEXITINFO pExitInfo)
7828{
7829 /* Nested-guest intercept. */
7830 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7831 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7832 {
7833 if (pExitInfo)
7834 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7835 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7836 }
7837
7838 /* CPL. */
7839 if (pVCpu->iem.s.uCpl == 0)
7840 { /* likely */ }
7841 else
7842 {
7843 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7845 return iemRaiseGeneralProtectionFault0(pVCpu);
7846 }
7847
7848 /* VMCS pointer in root mode. */
7849 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7850 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7851 { /* likely */ }
7852 else
7853 {
7854 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7855 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7856 iemVmxVmFailInvalid(pVCpu);
7857 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7858 return VINF_SUCCESS;
7859 }
7860
7861 /* VMCS-link pointer in non-root mode. */
7862 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7863 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7864 { /* likely */ }
7865 else
7866 {
7867 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7869 iemVmxVmFailInvalid(pVCpu);
7870 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7871 return VINF_SUCCESS;
7872 }
7873
7874 /* Supported VMCS field. */
7875 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7876 { /* likely */ }
7877 else
7878 {
7879 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7880 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7881 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7882 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7883 return VINF_SUCCESS;
7884 }
7885
7886 /*
7887 * Setup reading from the current or shadow VMCS.
7888 */
7889 uint8_t *pbVmcs;
7890 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7891 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7892 else
7893 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7894 Assert(pbVmcs);
7895
7896 VMXVMCSFIELDENC FieldEnc;
7897 FieldEnc.u = u64FieldEnc;
7898 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7899 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7900 uint8_t const uWidthType = (uWidth << 2) | uType;
7901 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7902 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7903 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7904 Assert(offField < VMX_V_VMCS_SIZE);
7905
7906 /*
7907 * Read the VMCS component based on the field's effective width.
7908 *
7909 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7910 * indicates high bits (little endian).
7911 *
7912 * Note! The caller is responsible to trim the result and update registers
7913 * or memory locations are required. Here we just zero-extend to the largest
7914 * type (i.e. 64-bits).
7915 */
7916 uint8_t *pbField = pbVmcs + offField;
7917 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7918 switch (uEffWidth)
7919 {
7920 case VMX_VMCS_ENC_WIDTH_64BIT:
7921 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7922 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7923 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7924 }
7925 return VINF_SUCCESS;
7926}
7927
7928
7929/**
7930 * VMREAD (64-bit register) instruction execution worker.
7931 *
7932 * @returns Strict VBox status code.
7933 * @param pVCpu The cross context virtual CPU structure.
7934 * @param cbInstr The instruction length in bytes.
7935 * @param pu64Dst Where to store the VMCS field's value.
7936 * @param u64FieldEnc The VMCS field encoding.
7937 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7938 * be NULL.
7939 */
7940IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7941 PCVMXVEXITINFO pExitInfo)
7942{
7943 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7944 if (rcStrict == VINF_SUCCESS)
7945 {
7946 iemVmxVmreadSuccess(pVCpu, cbInstr);
7947 return VINF_SUCCESS;
7948 }
7949
7950 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7951 return rcStrict;
7952}
7953
7954
7955/**
7956 * VMREAD (32-bit register) instruction execution worker.
7957 *
7958 * @returns Strict VBox status code.
7959 * @param pVCpu The cross context virtual CPU structure.
7960 * @param cbInstr The instruction length in bytes.
7961 * @param pu32Dst Where to store the VMCS field's value.
7962 * @param u32FieldEnc The VMCS field encoding.
7963 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7964 * be NULL.
7965 */
7966IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7967 PCVMXVEXITINFO pExitInfo)
7968{
7969 uint64_t u64Dst;
7970 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7971 if (rcStrict == VINF_SUCCESS)
7972 {
7973 *pu32Dst = u64Dst;
7974 iemVmxVmreadSuccess(pVCpu, cbInstr);
7975 return VINF_SUCCESS;
7976 }
7977
7978 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7979 return rcStrict;
7980}
7981
7982
7983/**
7984 * VMREAD (memory) instruction execution worker.
7985 *
7986 * @returns Strict VBox status code.
7987 * @param pVCpu The cross context virtual CPU structure.
7988 * @param cbInstr The instruction length in bytes.
7989 * @param iEffSeg The effective segment register to use with @a u64Val.
7990 * Pass UINT8_MAX if it is a register access.
7991 * @param enmEffAddrMode The effective addressing mode (only used with memory
7992 * operand).
7993 * @param GCPtrDst The guest linear address to store the VMCS field's
7994 * value.
7995 * @param u64FieldEnc The VMCS field encoding.
7996 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7997 * be NULL.
7998 */
7999IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
8000 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
8001{
8002 uint64_t u64Dst;
8003 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
8004 if (rcStrict == VINF_SUCCESS)
8005 {
8006 /*
8007 * Write the VMCS field's value to the location specified in guest-memory.
8008 *
8009 * The pointer size depends on the address size (address-size prefix allowed).
8010 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
8011 */
8012 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8013 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8014 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
8015
8016 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8017 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8018 else
8019 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8020 if (rcStrict == VINF_SUCCESS)
8021 {
8022 iemVmxVmreadSuccess(pVCpu, cbInstr);
8023 return VINF_SUCCESS;
8024 }
8025
8026 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8028 return rcStrict;
8029 }
8030
8031 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8032 return rcStrict;
8033}
8034
8035
8036/**
8037 * VMWRITE instruction execution worker.
8038 *
8039 * @returns Strict VBox status code.
8040 * @param pVCpu The cross context virtual CPU structure.
8041 * @param cbInstr The instruction length in bytes.
8042 * @param iEffSeg The effective segment register to use with @a u64Val.
8043 * Pass UINT8_MAX if it is a register access.
8044 * @param enmEffAddrMode The effective addressing mode (only used with memory
8045 * operand).
8046 * @param u64Val The value to write (or guest linear address to the
8047 * value), @a iEffSeg will indicate if it's a memory
8048 * operand.
8049 * @param u64FieldEnc The VMCS field encoding.
8050 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8051 * be NULL.
8052 */
8053IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
8054 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
8055{
8056 /* Nested-guest intercept. */
8057 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8058 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8059 {
8060 if (pExitInfo)
8061 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8062 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8063 }
8064
8065 /* CPL. */
8066 if (pVCpu->iem.s.uCpl == 0)
8067 { /* likely */ }
8068 else
8069 {
8070 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8071 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8072 return iemRaiseGeneralProtectionFault0(pVCpu);
8073 }
8074
8075 /* VMCS pointer in root mode. */
8076 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8077 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8078 { /* likely */ }
8079 else
8080 {
8081 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8082 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8083 iemVmxVmFailInvalid(pVCpu);
8084 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8085 return VINF_SUCCESS;
8086 }
8087
8088 /* VMCS-link pointer in non-root mode. */
8089 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8090 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8091 { /* likely */ }
8092 else
8093 {
8094 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8096 iemVmxVmFailInvalid(pVCpu);
8097 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8098 return VINF_SUCCESS;
8099 }
8100
8101 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8102 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8103 if (!fIsRegOperand)
8104 {
8105 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8106 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8107 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8108
8109 /* Read the value from the specified guest memory location. */
8110 VBOXSTRICTRC rcStrict;
8111 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8112 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8113 else
8114 {
8115 uint32_t u32Val;
8116 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8117 u64Val = u32Val;
8118 }
8119 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8120 {
8121 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8122 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8123 return rcStrict;
8124 }
8125 }
8126 else
8127 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8128
8129 /* Supported VMCS field. */
8130 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8131 { /* likely */ }
8132 else
8133 {
8134 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8135 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8136 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8137 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8138 return VINF_SUCCESS;
8139 }
8140
8141 /* Read-only VMCS field. */
8142 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8143 if ( !fIsFieldReadOnly
8144 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8145 { /* likely */ }
8146 else
8147 {
8148 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8149 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8150 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8151 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8152 return VINF_SUCCESS;
8153 }
8154
8155 /*
8156 * Setup writing to the current or shadow VMCS.
8157 */
8158 uint8_t *pbVmcs;
8159 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8160 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8161 else
8162 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8163 Assert(pbVmcs);
8164
8165 VMXVMCSFIELDENC FieldEnc;
8166 FieldEnc.u = u64FieldEnc;
8167 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8168 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8169 uint8_t const uWidthType = (uWidth << 2) | uType;
8170 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8171 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8172 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8173 Assert(offField < VMX_V_VMCS_SIZE);
8174
8175 /*
8176 * Write the VMCS component based on the field's effective width.
8177 *
8178 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8179 * indicates high bits (little endian).
8180 */
8181 uint8_t *pbField = pbVmcs + offField;
8182 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8183 switch (uEffWidth)
8184 {
8185 case VMX_VMCS_ENC_WIDTH_64BIT:
8186 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8187 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8188 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8189 }
8190
8191 iemVmxVmSucceed(pVCpu);
8192 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8193 return VINF_SUCCESS;
8194}
8195
8196
8197/**
8198 * VMCLEAR instruction execution worker.
8199 *
8200 * @returns Strict VBox status code.
8201 * @param pVCpu The cross context virtual CPU structure.
8202 * @param cbInstr The instruction length in bytes.
8203 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8204 * @param GCPtrVmcs The linear address of the VMCS pointer.
8205 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8206 * be NULL.
8207 *
8208 * @remarks Common VMX instruction checks are already expected to by the caller,
8209 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8210 */
8211IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8212 PCVMXVEXITINFO pExitInfo)
8213{
8214 /* Nested-guest intercept. */
8215 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8216 {
8217 if (pExitInfo)
8218 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8219 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8220 }
8221
8222 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8223
8224 /* CPL. */
8225 if (pVCpu->iem.s.uCpl == 0)
8226 { /* likely */ }
8227 else
8228 {
8229 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8230 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8231 return iemRaiseGeneralProtectionFault0(pVCpu);
8232 }
8233
8234 /* Get the VMCS pointer from the location specified by the source memory operand. */
8235 RTGCPHYS GCPhysVmcs;
8236 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8237 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8238 { /* likely */ }
8239 else
8240 {
8241 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8242 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8243 return rcStrict;
8244 }
8245
8246 /* VMCS pointer alignment. */
8247 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8248 { /* likely */ }
8249 else
8250 {
8251 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8252 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8253 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8255 return VINF_SUCCESS;
8256 }
8257
8258 /* VMCS physical-address width limits. */
8259 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8260 { /* likely */ }
8261 else
8262 {
8263 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8264 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8265 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8266 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8267 return VINF_SUCCESS;
8268 }
8269
8270 /* VMCS is not the VMXON region. */
8271 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8272 { /* likely */ }
8273 else
8274 {
8275 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8276 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8277 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8278 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8279 return VINF_SUCCESS;
8280 }
8281
8282 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8283 restriction imposed by our implementation. */
8284 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8285 { /* likely */ }
8286 else
8287 {
8288 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8289 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8290 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8291 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8292 return VINF_SUCCESS;
8293 }
8294
8295 /*
8296 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8297 *
8298 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8299 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8300 * to 'clear'.
8301 */
8302 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8303 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8304 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8305 {
8306 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8307 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8309 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8310 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8311 }
8312 else
8313 {
8314 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8315 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8316 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8317 if (RT_FAILURE(rcStrict))
8318 return rcStrict;
8319 }
8320
8321 iemVmxVmSucceed(pVCpu);
8322 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8323 return VINF_SUCCESS;
8324}
8325
8326
8327/**
8328 * VMPTRST instruction execution worker.
8329 *
8330 * @returns Strict VBox status code.
8331 * @param pVCpu The cross context virtual CPU structure.
8332 * @param cbInstr The instruction length in bytes.
8333 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8334 * @param GCPtrVmcs The linear address of where to store the current VMCS
8335 * pointer.
8336 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8337 * be NULL.
8338 *
8339 * @remarks Common VMX instruction checks are already expected to by the caller,
8340 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8341 */
8342IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8343 PCVMXVEXITINFO pExitInfo)
8344{
8345 /* Nested-guest intercept. */
8346 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8347 {
8348 if (pExitInfo)
8349 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8350 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8351 }
8352
8353 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8354
8355 /* CPL. */
8356 if (pVCpu->iem.s.uCpl == 0)
8357 { /* likely */ }
8358 else
8359 {
8360 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8361 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8362 return iemRaiseGeneralProtectionFault0(pVCpu);
8363 }
8364
8365 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8366 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8367 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8368 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8369 {
8370 iemVmxVmSucceed(pVCpu);
8371 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8372 return rcStrict;
8373 }
8374
8375 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8377 return rcStrict;
8378}
8379
8380
8381/**
8382 * VMPTRLD instruction execution worker.
8383 *
8384 * @returns Strict VBox status code.
8385 * @param pVCpu The cross context virtual CPU structure.
8386 * @param cbInstr The instruction length in bytes.
8387 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8388 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8389 * be NULL.
8390 *
8391 * @remarks Common VMX instruction checks are already expected to by the caller,
8392 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8393 */
8394IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8395 PCVMXVEXITINFO pExitInfo)
8396{
8397 /* Nested-guest intercept. */
8398 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8399 {
8400 if (pExitInfo)
8401 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8402 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8403 }
8404
8405 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8406
8407 /* CPL. */
8408 if (pVCpu->iem.s.uCpl == 0)
8409 { /* likely */ }
8410 else
8411 {
8412 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8414 return iemRaiseGeneralProtectionFault0(pVCpu);
8415 }
8416
8417 /* Get the VMCS pointer from the location specified by the source memory operand. */
8418 RTGCPHYS GCPhysVmcs;
8419 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8420 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8421 { /* likely */ }
8422 else
8423 {
8424 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8425 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8426 return rcStrict;
8427 }
8428
8429 /* VMCS pointer alignment. */
8430 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8431 { /* likely */ }
8432 else
8433 {
8434 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8436 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8437 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8438 return VINF_SUCCESS;
8439 }
8440
8441 /* VMCS physical-address width limits. */
8442 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8443 { /* likely */ }
8444 else
8445 {
8446 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8447 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8448 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8449 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8450 return VINF_SUCCESS;
8451 }
8452
8453 /* VMCS is not the VMXON region. */
8454 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8455 { /* likely */ }
8456 else
8457 {
8458 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8460 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8461 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8462 return VINF_SUCCESS;
8463 }
8464
8465 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8466 restriction imposed by our implementation. */
8467 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8468 { /* likely */ }
8469 else
8470 {
8471 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8473 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8474 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8475 return VINF_SUCCESS;
8476 }
8477
8478 /* Read just the VMCS revision from the VMCS. */
8479 VMXVMCSREVID VmcsRevId;
8480 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8481 if (RT_SUCCESS(rc))
8482 { /* likely */ }
8483 else
8484 {
8485 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8486 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8487 return rc;
8488 }
8489
8490 /*
8491 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8492 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8493 */
8494 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8495 && ( !VmcsRevId.n.fIsShadowVmcs
8496 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8497 { /* likely */ }
8498 else
8499 {
8500 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8501 {
8502 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8503 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8505 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8506 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8507 return VINF_SUCCESS;
8508 }
8509
8510 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8511 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8512 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8513 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8514 return VINF_SUCCESS;
8515 }
8516
8517 /*
8518 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8519 * the cache of an existing, current VMCS back to guest memory before loading a new,
8520 * different current VMCS.
8521 */
8522 bool fLoadVmcsFromMem;
8523 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8524 {
8525 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8526 {
8527 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8528 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8529 fLoadVmcsFromMem = true;
8530 }
8531 else
8532 fLoadVmcsFromMem = false;
8533 }
8534 else
8535 fLoadVmcsFromMem = true;
8536
8537 if (fLoadVmcsFromMem)
8538 {
8539 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8540 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8541 sizeof(VMXVVMCS));
8542 if (RT_SUCCESS(rc))
8543 { /* likely */ }
8544 else
8545 {
8546 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8547 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8548 return rc;
8549 }
8550 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8551 }
8552
8553 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8554 iemVmxVmSucceed(pVCpu);
8555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8556 return VINF_SUCCESS;
8557}
8558
8559
8560/**
8561 * VMXON instruction execution worker.
8562 *
8563 * @returns Strict VBox status code.
8564 * @param pVCpu The cross context virtual CPU structure.
8565 * @param cbInstr The instruction length in bytes.
8566 * @param iEffSeg The effective segment register to use with @a
8567 * GCPtrVmxon.
8568 * @param GCPtrVmxon The linear address of the VMXON pointer.
8569 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8570 * Optional, can be NULL.
8571 *
8572 * @remarks Common VMX instruction checks are already expected to by the caller,
8573 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8574 */
8575IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8576 PCVMXVEXITINFO pExitInfo)
8577{
8578 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8579 {
8580 /* CPL. */
8581 if (pVCpu->iem.s.uCpl == 0)
8582 { /* likely */ }
8583 else
8584 {
8585 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8587 return iemRaiseGeneralProtectionFault0(pVCpu);
8588 }
8589
8590 /* A20M (A20 Masked) mode. */
8591 if (PGMPhysIsA20Enabled(pVCpu))
8592 { /* likely */ }
8593 else
8594 {
8595 Log(("vmxon: A20M mode -> #GP(0)\n"));
8596 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8597 return iemRaiseGeneralProtectionFault0(pVCpu);
8598 }
8599
8600 /* CR0. */
8601 {
8602 /* CR0 MB1 bits. */
8603 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8604 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8605 { /* likely */ }
8606 else
8607 {
8608 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8609 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8610 return iemRaiseGeneralProtectionFault0(pVCpu);
8611 }
8612
8613 /* CR0 MBZ bits. */
8614 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8615 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8616 { /* likely */ }
8617 else
8618 {
8619 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8621 return iemRaiseGeneralProtectionFault0(pVCpu);
8622 }
8623 }
8624
8625 /* CR4. */
8626 {
8627 /* CR4 MB1 bits. */
8628 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8629 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8630 { /* likely */ }
8631 else
8632 {
8633 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8634 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8635 return iemRaiseGeneralProtectionFault0(pVCpu);
8636 }
8637
8638 /* CR4 MBZ bits. */
8639 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8640 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8641 { /* likely */ }
8642 else
8643 {
8644 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8645 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8646 return iemRaiseGeneralProtectionFault0(pVCpu);
8647 }
8648 }
8649
8650 /* Feature control MSR's LOCK and VMXON bits. */
8651 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8652 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8653 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8654 { /* likely */ }
8655 else
8656 {
8657 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8658 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8659 return iemRaiseGeneralProtectionFault0(pVCpu);
8660 }
8661
8662 /* Get the VMXON pointer from the location specified by the source memory operand. */
8663 RTGCPHYS GCPhysVmxon;
8664 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8665 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8666 { /* likely */ }
8667 else
8668 {
8669 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8670 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8671 return rcStrict;
8672 }
8673
8674 /* VMXON region pointer alignment. */
8675 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8676 { /* likely */ }
8677 else
8678 {
8679 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8681 iemVmxVmFailInvalid(pVCpu);
8682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8683 return VINF_SUCCESS;
8684 }
8685
8686 /* VMXON physical-address width limits. */
8687 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8688 { /* likely */ }
8689 else
8690 {
8691 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8693 iemVmxVmFailInvalid(pVCpu);
8694 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8695 return VINF_SUCCESS;
8696 }
8697
8698 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8699 restriction imposed by our implementation. */
8700 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8701 { /* likely */ }
8702 else
8703 {
8704 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8706 iemVmxVmFailInvalid(pVCpu);
8707 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8708 return VINF_SUCCESS;
8709 }
8710
8711 /* Read the VMCS revision ID from the VMXON region. */
8712 VMXVMCSREVID VmcsRevId;
8713 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8714 if (RT_SUCCESS(rc))
8715 { /* likely */ }
8716 else
8717 {
8718 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8719 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8720 return rc;
8721 }
8722
8723 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8724 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8725 { /* likely */ }
8726 else
8727 {
8728 /* Revision ID mismatch. */
8729 if (!VmcsRevId.n.fIsShadowVmcs)
8730 {
8731 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8732 VmcsRevId.n.u31RevisionId));
8733 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8734 iemVmxVmFailInvalid(pVCpu);
8735 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8736 return VINF_SUCCESS;
8737 }
8738
8739 /* Shadow VMCS disallowed. */
8740 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8741 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8742 iemVmxVmFailInvalid(pVCpu);
8743 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8744 return VINF_SUCCESS;
8745 }
8746
8747 /*
8748 * Record that we're in VMX operation, block INIT, block and disable A20M.
8749 */
8750 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8751 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8752 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8753
8754 /* Clear address-range monitoring. */
8755 EMMonitorWaitClear(pVCpu);
8756 /** @todo NSTVMX: Intel PT. */
8757
8758 iemVmxVmSucceed(pVCpu);
8759 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8760 return VINF_SUCCESS;
8761 }
8762 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8763 {
8764 /* Nested-guest intercept. */
8765 if (pExitInfo)
8766 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8767 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8768 }
8769
8770 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8771
8772 /* CPL. */
8773 if (pVCpu->iem.s.uCpl > 0)
8774 {
8775 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8776 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8777 return iemRaiseGeneralProtectionFault0(pVCpu);
8778 }
8779
8780 /* VMXON when already in VMX root mode. */
8781 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8783 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8784 return VINF_SUCCESS;
8785}
8786
8787
8788/**
8789 * Implements 'VMXOFF'.
8790 *
8791 * @remarks Common VMX instruction checks are already expected to by the caller,
8792 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8793 */
8794IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8795{
8796 /* Nested-guest intercept. */
8797 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8798 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8799
8800 /* CPL. */
8801 if (pVCpu->iem.s.uCpl == 0)
8802 { /* likely */ }
8803 else
8804 {
8805 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8806 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8807 return iemRaiseGeneralProtectionFault0(pVCpu);
8808 }
8809
8810 /* Dual monitor treatment of SMIs and SMM. */
8811 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8812 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8813 { /* likely */ }
8814 else
8815 {
8816 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8817 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8818 return VINF_SUCCESS;
8819 }
8820
8821 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8822 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8823 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8824
8825 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8826 { /** @todo NSTVMX: Unblock SMI. */ }
8827
8828 EMMonitorWaitClear(pVCpu);
8829 /** @todo NSTVMX: Unblock and enable A20M. */
8830
8831 iemVmxVmSucceed(pVCpu);
8832 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8833 return VINF_SUCCESS;
8834}
8835
8836
8837/**
8838 * Implements 'VMXON'.
8839 */
8840IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8841{
8842 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8843}
8844
8845
8846/**
8847 * Implements 'VMLAUNCH'.
8848 */
8849IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8850{
8851 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8852}
8853
8854
8855/**
8856 * Implements 'VMRESUME'.
8857 */
8858IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8859{
8860 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8861}
8862
8863
8864/**
8865 * Implements 'VMPTRLD'.
8866 */
8867IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8868{
8869 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8870}
8871
8872
8873/**
8874 * Implements 'VMPTRST'.
8875 */
8876IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8877{
8878 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8879}
8880
8881
8882/**
8883 * Implements 'VMCLEAR'.
8884 */
8885IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8886{
8887 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8888}
8889
8890
8891/**
8892 * Implements 'VMWRITE' register.
8893 */
8894IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8895{
8896 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8897 NULL /* pExitInfo */);
8898}
8899
8900
8901/**
8902 * Implements 'VMWRITE' memory.
8903 */
8904IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8905{
8906 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8907}
8908
8909
8910/**
8911 * Implements 'VMREAD' register (64-bit).
8912 */
8913IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8914{
8915 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8916}
8917
8918
8919/**
8920 * Implements 'VMREAD' register (32-bit).
8921 */
8922IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8923{
8924 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8925}
8926
8927
8928/**
8929 * Implements 'VMREAD' memory, 64-bit register.
8930 */
8931IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8932{
8933 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8934}
8935
8936
8937/**
8938 * Implements 'VMREAD' memory, 32-bit register.
8939 */
8940IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8941{
8942 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8943}
8944
8945
8946/**
8947 * Implements VMX's implementation of PAUSE.
8948 */
8949IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8950{
8951 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8952 {
8953 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8954 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8955 return rcStrict;
8956 }
8957
8958 /*
8959 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8960 * a VM-exit, the instruction operates normally.
8961 */
8962 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8963 return VINF_SUCCESS;
8964}
8965
8966#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8967
8968
8969/**
8970 * Implements 'VMCALL'.
8971 */
8972IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8973{
8974#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8975 /* Nested-guest intercept. */
8976 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8977 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8978#endif
8979
8980 /* Join forces with vmmcall. */
8981 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8982}
8983
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