VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78455

Last change on this file since 78455 was 78455, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Use the CPUM function for determining VMX I/O intercepts.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78455 2019-05-09 08:36:06Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_INVVPID
181 * VMX_EXIT_RDRAND
182 * VMX_EXIT_VMFUNC
183 * VMX_EXIT_ENCLS
184 * VMX_EXIT_RDSEED
185 * VMX_EXIT_PML_FULL
186 * VMX_EXIT_XSAVES
187 * VMX_EXIT_XRSTORS
188 */
189/**
190 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
191 *
192 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
193 * second dimension is the Index, see VMXVMCSFIELDENC.
194 */
195uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
196{
197 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
198 {
199 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
200 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
201 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
202 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
204 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
205 },
206 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
207 {
208 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
211 /* 24-25 */ UINT16_MAX, UINT16_MAX
212 },
213 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
214 {
215 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
216 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
217 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
218 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
219 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
220 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
221 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
222 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
223 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
224 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
225 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
267 /* 24 */ UINT16_MAX,
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
269 },
270 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
271 {
272 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
273 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 25 */ UINT16_MAX
277 },
278 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
279 {
280 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
281 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
282 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
283 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
284 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
285 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
286 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
287 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
288 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
289 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
290 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64FieldEnc The VMCS field encoding.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSX:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the VM-exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param uExitQual The VM-exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = uExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitQual The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFailValid for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFailValid(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Implements VMFail for VMX instruction failure.
1108 *
1109 * @param pVCpu The cross context virtual CPU structure.
1110 * @param enmInsErr The VM instruction error.
1111 */
1112DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1113{
1114 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1115}
1116
1117
1118/**
1119 * Checks if the given auto-load/store MSR area count is valid for the
1120 * implementation.
1121 *
1122 * @returns @c true if it's within the valid limit, @c false otherwise.
1123 * @param pVCpu The cross context virtual CPU structure.
1124 * @param uMsrCount The MSR area count to check.
1125 */
1126DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1127{
1128 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1129 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1130 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1131 if (uMsrCount <= cMaxSupportedMsrs)
1132 return true;
1133 return false;
1134}
1135
1136
1137/**
1138 * Flushes the current VMCS contents back to guest memory.
1139 *
1140 * @returns VBox status code.
1141 * @param pVCpu The cross context virtual CPU structure.
1142 */
1143DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1144{
1145 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1146 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1147 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1148 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1149 return rc;
1150}
1151
1152
1153/**
1154 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1155 *
1156 * @param pVCpu The cross context virtual CPU structure.
1157 */
1158DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1159{
1160 iemVmxVmSucceed(pVCpu);
1161 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1162}
1163
1164
1165/**
1166 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1167 * nested-guest.
1168 *
1169 * @param iSegReg The segment index (X86_SREG_XXX).
1170 */
1171IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1172{
1173 switch (iSegReg)
1174 {
1175 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1176 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1177 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1178 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1179 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1180 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1181 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1182 }
1183}
1184
1185
1186/**
1187 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1188 * nested-guest that is in Virtual-8086 mode.
1189 *
1190 * @param iSegReg The segment index (X86_SREG_XXX).
1191 */
1192IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1193{
1194 switch (iSegReg)
1195 {
1196 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1197 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1198 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1199 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1200 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1201 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1202 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1203 }
1204}
1205
1206
1207/**
1208 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1209 * nested-guest that is in Virtual-8086 mode.
1210 *
1211 * @param iSegReg The segment index (X86_SREG_XXX).
1212 */
1213IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1214{
1215 switch (iSegReg)
1216 {
1217 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1218 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1219 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1220 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1221 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1222 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1223 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1224 }
1225}
1226
1227
1228/**
1229 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1230 * nested-guest that is in Virtual-8086 mode.
1231 *
1232 * @param iSegReg The segment index (X86_SREG_XXX).
1233 */
1234IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1235{
1236 switch (iSegReg)
1237 {
1238 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1239 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1240 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1241 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1242 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1243 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1244 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1245 }
1246}
1247
1248
1249/**
1250 * Gets the instruction diagnostic for segment attributes reserved bits failure
1251 * during VM-entry of a nested-guest.
1252 *
1253 * @param iSegReg The segment index (X86_SREG_XXX).
1254 */
1255IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1256{
1257 switch (iSegReg)
1258 {
1259 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1260 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1261 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1262 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1263 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1264 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1265 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1266 }
1267}
1268
1269
1270/**
1271 * Gets the instruction diagnostic for segment attributes descriptor-type
1272 * (code/segment or system) failure during VM-entry of a nested-guest.
1273 *
1274 * @param iSegReg The segment index (X86_SREG_XXX).
1275 */
1276IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1277{
1278 switch (iSegReg)
1279 {
1280 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1281 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1282 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1283 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1284 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1285 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1286 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1287 }
1288}
1289
1290
1291/**
1292 * Gets the instruction diagnostic for segment attributes descriptor-type
1293 * (code/segment or system) failure during VM-entry of a nested-guest.
1294 *
1295 * @param iSegReg The segment index (X86_SREG_XXX).
1296 */
1297IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1298{
1299 switch (iSegReg)
1300 {
1301 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1302 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1303 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1304 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1305 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1306 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1307 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1308 }
1309}
1310
1311
1312/**
1313 * Gets the instruction diagnostic for segment attribute granularity failure during
1314 * VM-entry of a nested-guest.
1315 *
1316 * @param iSegReg The segment index (X86_SREG_XXX).
1317 */
1318IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1319{
1320 switch (iSegReg)
1321 {
1322 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1323 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1324 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1325 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1326 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1327 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1328 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1329 }
1330}
1331
1332/**
1333 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1334 * VM-entry of a nested-guest.
1335 *
1336 * @param iSegReg The segment index (X86_SREG_XXX).
1337 */
1338IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1339{
1340 switch (iSegReg)
1341 {
1342 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1343 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1344 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1345 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1346 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1347 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1348 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1349 }
1350}
1351
1352
1353/**
1354 * Gets the instruction diagnostic for segment attribute type accessed failure
1355 * during VM-entry of a nested-guest.
1356 *
1357 * @param iSegReg The segment index (X86_SREG_XXX).
1358 */
1359IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1360{
1361 switch (iSegReg)
1362 {
1363 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1364 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1365 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1366 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1367 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1368 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1369 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1370 }
1371}
1372
1373
1374/**
1375 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1376 * failure during VM-entry of a nested-guest.
1377 *
1378 * @param iSegReg The PDPTE entry index.
1379 */
1380IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1381{
1382 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1383 switch (iPdpte)
1384 {
1385 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1386 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1387 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1388 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1389 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1390 }
1391}
1392
1393
1394/**
1395 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1396 * failure during VM-exit of a nested-guest.
1397 *
1398 * @param iSegReg The PDPTE entry index.
1399 */
1400IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1401{
1402 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1403 switch (iPdpte)
1404 {
1405 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1406 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1407 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1408 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1409 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1410 }
1411}
1412
1413
1414/**
1415 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1416 * mask and the read-shadow (CR0/CR4 read).
1417 *
1418 * @returns The masked CR0/CR4.
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param iCrReg The control register (either CR0 or CR4).
1421 * @param uGuestCrX The current guest CR0 or guest CR4.
1422 */
1423IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1424{
1425 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1426 Assert(iCrReg == 0 || iCrReg == 4);
1427
1428 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1429 Assert(pVmcs);
1430
1431 /*
1432 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1433 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1434 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1435 *
1436 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1437 */
1438 uint64_t fGstHostMask;
1439 uint64_t fReadShadow;
1440 if (iCrReg == 0)
1441 {
1442 fGstHostMask = pVmcs->u64Cr0Mask.u;
1443 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1444 }
1445 else
1446 {
1447 fGstHostMask = pVmcs->u64Cr4Mask.u;
1448 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1449 }
1450
1451 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1452 return fMaskedCrX;
1453}
1454
1455
1456/**
1457 * Saves the guest control registers, debug registers and some MSRs are part of
1458 * VM-exit.
1459 *
1460 * @param pVCpu The cross context virtual CPU structure.
1461 */
1462IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1463{
1464 /*
1465 * Saves the guest control registers, debug registers and some MSRs.
1466 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1467 */
1468 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1469
1470 /* Save control registers. */
1471 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1472 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1473 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1474
1475 /* Save SYSENTER CS, ESP, EIP. */
1476 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1477 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1478 {
1479 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1480 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1481 }
1482 else
1483 {
1484 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1485 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1486 }
1487
1488 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1489 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1490 {
1491 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1492 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1493 }
1494
1495 /* Save PAT MSR. */
1496 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1497 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1498
1499 /* Save EFER MSR. */
1500 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1501 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1502
1503 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1504 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1505
1506 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1507}
1508
1509
1510/**
1511 * Saves the guest force-flags in preparation of entering the nested-guest.
1512 *
1513 * @param pVCpu The cross context virtual CPU structure.
1514 */
1515IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1516{
1517 /* We shouldn't be called multiple times during VM-entry. */
1518 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1519
1520 /* MTF should not be set outside VMX non-root mode. */
1521 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1522
1523 /*
1524 * Preserve the required force-flags.
1525 *
1526 * We cache and clear force-flags that would affect the execution of the
1527 * nested-guest. Cached flags are then restored while returning to the guest
1528 * if necessary.
1529 *
1530 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1531 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1532 * instruction. Interrupt inhibition for any nested-guest instruction
1533 * is supplied by the guest-interruptibility state VMCS field and will
1534 * be set up as part of loading the guest state.
1535 *
1536 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1537 * successful VM-entry (due to invalid guest-state) need to continue
1538 * blocking NMIs if it was in effect before VM-entry.
1539 *
1540 * - MTF need not be preserved as it's used only in VMX non-root mode and
1541 * is supplied through the VM-execution controls.
1542 *
1543 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1544 * we will be able to generate interrupts that may cause VM-exits for
1545 * the nested-guest.
1546 */
1547 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1548}
1549
1550
1551/**
1552 * Restores the guest force-flags in preparation of exiting the nested-guest.
1553 *
1554 * @param pVCpu The cross context virtual CPU structure.
1555 */
1556IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1557{
1558 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1559 {
1560 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1561 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1562 }
1563}
1564
1565
1566/**
1567 * Perform a VMX transition updated PGM, IEM and CPUM.
1568 *
1569 * @param pVCpu The cross context virtual CPU structure.
1570 */
1571IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1572{
1573 /*
1574 * Inform PGM about paging mode changes.
1575 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1576 * see comment in iemMemPageTranslateAndCheckAccess().
1577 */
1578 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1579# ifdef IN_RING3
1580 Assert(rc != VINF_PGM_CHANGE_MODE);
1581# endif
1582 AssertRCReturn(rc, rc);
1583
1584 /* Inform CPUM (recompiler), can later be removed. */
1585 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1586
1587 /*
1588 * Flush the TLB with new CR3. This is required in case the PGM mode change
1589 * above doesn't actually change anything.
1590 */
1591 if (rc == VINF_SUCCESS)
1592 {
1593 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1594 AssertRCReturn(rc, rc);
1595 }
1596
1597 /* Re-initialize IEM cache/state after the drastic mode switch. */
1598 iemReInitExec(pVCpu);
1599 return rc;
1600}
1601
1602
1603/**
1604 * Calculates the current VMX-preemption timer value.
1605 *
1606 * @param pVCpu The cross context virtual CPU structure.
1607 */
1608IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1609{
1610 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1611 Assert(pVmcs);
1612
1613 /*
1614 * Assume the following:
1615 * PreemptTimerShift = 5
1616 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1617 * EntryTick = 50000 (TSC at time of VM-entry)
1618 *
1619 * CurTick Delta PreemptTimerVal
1620 * ----------------------------------
1621 * 60000 10000 2
1622 * 80000 30000 1
1623 * 90000 40000 0 -> VM-exit.
1624 *
1625 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1626 * The saved VMX-preemption timer value is calculated as follows:
1627 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1628 * E.g.:
1629 * Delta = 10000
1630 * Tmp = 10000 / (2 * 10000) = 0.5
1631 * NewPt = 2 - 0.5 = 2
1632 * Delta = 30000
1633 * Tmp = 30000 / (2 * 10000) = 1.5
1634 * NewPt = 2 - 1.5 = 1
1635 * Delta = 40000
1636 * Tmp = 40000 / 20000 = 2
1637 * NewPt = 2 - 2 = 0
1638 */
1639 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1640 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1641 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1642 uint64_t const uDelta = uCurTick - uEntryTick;
1643 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1644 uint32_t const uPreemptTimer = uVmcsPreemptVal
1645 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1646 return uPreemptTimer;
1647}
1648
1649
1650/**
1651 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1652 *
1653 * @param pVCpu The cross context virtual CPU structure.
1654 */
1655IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1656{
1657 /*
1658 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1659 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1660 */
1661 /* CS, SS, ES, DS, FS, GS. */
1662 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1663 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1664 {
1665 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1666 if (!pSelReg->Attr.n.u1Unusable)
1667 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1668 else
1669 {
1670 /*
1671 * For unusable segments the attributes are undefined except for CS and SS.
1672 * For the rest we don't bother preserving anything but the unusable bit.
1673 */
1674 switch (iSegReg)
1675 {
1676 case X86_SREG_CS:
1677 pVmcs->GuestCs = pSelReg->Sel;
1678 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1679 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1680 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1681 | X86DESCATTR_UNUSABLE);
1682 break;
1683
1684 case X86_SREG_SS:
1685 pVmcs->GuestSs = pSelReg->Sel;
1686 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1687 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1688 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1689 break;
1690
1691 case X86_SREG_DS:
1692 pVmcs->GuestDs = pSelReg->Sel;
1693 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1694 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1695 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1696 break;
1697
1698 case X86_SREG_ES:
1699 pVmcs->GuestEs = pSelReg->Sel;
1700 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1701 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1702 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1703 break;
1704
1705 case X86_SREG_FS:
1706 pVmcs->GuestFs = pSelReg->Sel;
1707 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1708 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1709 break;
1710
1711 case X86_SREG_GS:
1712 pVmcs->GuestGs = pSelReg->Sel;
1713 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1714 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1715 break;
1716 }
1717 }
1718 }
1719
1720 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1721 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1722 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1723 | X86DESCATTR_UNUSABLE;
1724 /* LDTR. */
1725 {
1726 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1727 pVmcs->GuestLdtr = pSelReg->Sel;
1728 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1729 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1730 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1731 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1732 }
1733
1734 /* TR. */
1735 {
1736 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1737 pVmcs->GuestTr = pSelReg->Sel;
1738 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1739 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1740 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1741 }
1742
1743 /* GDTR. */
1744 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1745 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1746
1747 /* IDTR. */
1748 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1749 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1750}
1751
1752
1753/**
1754 * Saves guest non-register state as part of VM-exit.
1755 *
1756 * @param pVCpu The cross context virtual CPU structure.
1757 * @param uExitReason The VM-exit reason.
1758 */
1759IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1760{
1761 /*
1762 * Save guest non-register state.
1763 * See Intel spec. 27.3.4 "Saving Non-Register State".
1764 */
1765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1766
1767 /*
1768 * Activity state.
1769 * Most VM-exits will occur in the active state. However, if the first instruction
1770 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1771 * the VM-exit will be from the HLT activity state.
1772 *
1773 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1774 */
1775 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1776 * not? */
1777 EMSTATE const enmActivityState = EMGetState(pVCpu);
1778 switch (enmActivityState)
1779 {
1780 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1781 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1782 }
1783
1784 /*
1785 * Interruptibility-state.
1786 */
1787 /* NMI. */
1788 pVmcs->u32GuestIntrState = 0;
1789 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1790 {
1791 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1792 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1793 }
1794 else
1795 {
1796 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1797 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1798 }
1799
1800 /* Blocking-by-STI. */
1801 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1802 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1803 {
1804 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1805 * currently. */
1806 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1807 }
1808 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1809
1810 /*
1811 * Pending debug exceptions.
1812 */
1813 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1814 && uExitReason != VMX_EXIT_SMI
1815 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1816 && !HMVmxIsVmexitTrapLike(uExitReason))
1817 {
1818 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1819 * block-by-MovSS is in effect. */
1820 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1821 }
1822 else
1823 {
1824 /*
1825 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1826 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1827 *
1828 * See Intel spec. 24.4.2 "Guest Non-Register State".
1829 */
1830 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1831 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1832 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1833 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1834 if (fPendingDbgMask & fBpHitMask)
1835 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1836 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1837 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1838 }
1839
1840 /*
1841 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1842 *
1843 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1844 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1845 */
1846 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1847 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1848 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1849
1850 /* PDPTEs. */
1851 /* We don't support EPT yet. */
1852 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1853 pVmcs->u64GuestPdpte0.u = 0;
1854 pVmcs->u64GuestPdpte1.u = 0;
1855 pVmcs->u64GuestPdpte2.u = 0;
1856 pVmcs->u64GuestPdpte3.u = 0;
1857}
1858
1859
1860/**
1861 * Saves the guest-state as part of VM-exit.
1862 *
1863 * @returns VBox status code.
1864 * @param pVCpu The cross context virtual CPU structure.
1865 * @param uExitReason The VM-exit reason.
1866 */
1867IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1868{
1869 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1870 Assert(pVmcs);
1871
1872 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1873 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1874
1875 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1876 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1877 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1878
1879 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1880}
1881
1882
1883/**
1884 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1885 *
1886 * @returns VBox status code.
1887 * @param pVCpu The cross context virtual CPU structure.
1888 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1889 */
1890IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1891{
1892 /*
1893 * Save guest MSRs.
1894 * See Intel spec. 27.4 "Saving MSRs".
1895 */
1896 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1897 const char *const pszFailure = "VMX-abort";
1898
1899 /*
1900 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1901 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1902 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1903 */
1904 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1905 if (!cMsrs)
1906 return VINF_SUCCESS;
1907
1908 /*
1909 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1910 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1911 * implementation causes a VMX-abort followed by a triple-fault.
1912 */
1913 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1914 if (fIsMsrCountValid)
1915 { /* likely */ }
1916 else
1917 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1918
1919 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1920 Assert(pMsr);
1921 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1922 {
1923 if ( !pMsr->u32Reserved
1924 && pMsr->u32Msr != MSR_IA32_SMBASE
1925 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1926 {
1927 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1928 if (rcStrict == VINF_SUCCESS)
1929 continue;
1930
1931 /*
1932 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1933 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1934 * recording the MSR index in the auxiliary info. field and indicated further by our
1935 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1936 * if possible, or come up with a better, generic solution.
1937 */
1938 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1939 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1940 ? kVmxVDiag_Vmexit_MsrStoreRing3
1941 : kVmxVDiag_Vmexit_MsrStore;
1942 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1943 }
1944 else
1945 {
1946 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1947 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1948 }
1949 }
1950
1951 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1952 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea,
1953 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), cMsrs * sizeof(VMXAUTOMSR));
1954 if (RT_SUCCESS(rc))
1955 { /* likely */ }
1956 else
1957 {
1958 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1959 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1960 }
1961
1962 NOREF(uExitReason);
1963 NOREF(pszFailure);
1964 return VINF_SUCCESS;
1965}
1966
1967
1968/**
1969 * Performs a VMX abort (due to an fatal error during VM-exit).
1970 *
1971 * @returns Strict VBox status code.
1972 * @param pVCpu The cross context virtual CPU structure.
1973 * @param enmAbort The VMX abort reason.
1974 */
1975IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1976{
1977 /*
1978 * Perform the VMX abort.
1979 * See Intel spec. 27.7 "VMX Aborts".
1980 */
1981 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1982
1983 /* We don't support SMX yet. */
1984 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1985 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1986 {
1987 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1988 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1989 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1990 }
1991
1992 return VINF_EM_TRIPLE_FAULT;
1993}
1994
1995
1996/**
1997 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1998 *
1999 * @param pVCpu The cross context virtual CPU structure.
2000 */
2001IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2002{
2003 /*
2004 * Load host control registers, debug registers and MSRs.
2005 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2006 */
2007 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2008 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2009
2010 /* CR0. */
2011 {
2012 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2013 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2014 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2015 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2016 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2017 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2018 CPUMSetGuestCR0(pVCpu, uValidCr0);
2019 }
2020
2021 /* CR4. */
2022 {
2023 /* CR4 MB1 bits are not modified. */
2024 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2025 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2026 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2027 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2028 if (fHostInLongMode)
2029 uValidCr4 |= X86_CR4_PAE;
2030 else
2031 uValidCr4 &= ~X86_CR4_PCIDE;
2032 CPUMSetGuestCR4(pVCpu, uValidCr4);
2033 }
2034
2035 /* CR3 (host value validated while checking host-state during VM-entry). */
2036 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2037
2038 /* DR7. */
2039 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2040
2041 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2042
2043 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2044 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2045 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2046 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2047
2048 /* FS, GS bases are loaded later while we load host segment registers. */
2049
2050 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2051 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2052 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2053 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2054 {
2055 if (fHostInLongMode)
2056 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2057 else
2058 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2059 }
2060
2061 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2062
2063 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2064 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2065 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2066
2067 /* We don't support IA32_BNDCFGS MSR yet. */
2068}
2069
2070
2071/**
2072 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2073 *
2074 * @param pVCpu The cross context virtual CPU structure.
2075 */
2076IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2077{
2078 /*
2079 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2080 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2081 *
2082 * Warning! Be careful to not touch fields that are reserved by VT-x,
2083 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2084 */
2085 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2086 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2087
2088 /* CS, SS, ES, DS, FS, GS. */
2089 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2090 {
2091 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2092 bool const fUnusable = RT_BOOL(HostSel == 0);
2093 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2094
2095 /* Selector. */
2096 pSelReg->Sel = HostSel;
2097 pSelReg->ValidSel = HostSel;
2098 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2099
2100 /* Limit. */
2101 pSelReg->u32Limit = 0xffffffff;
2102
2103 /* Base. */
2104 pSelReg->u64Base = 0;
2105
2106 /* Attributes. */
2107 if (iSegReg == X86_SREG_CS)
2108 {
2109 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2110 pSelReg->Attr.n.u1DescType = 1;
2111 pSelReg->Attr.n.u2Dpl = 0;
2112 pSelReg->Attr.n.u1Present = 1;
2113 pSelReg->Attr.n.u1Long = fHostInLongMode;
2114 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2115 pSelReg->Attr.n.u1Granularity = 1;
2116 Assert(!pSelReg->Attr.n.u1Unusable);
2117 Assert(!fUnusable);
2118 }
2119 else
2120 {
2121 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2122 pSelReg->Attr.n.u1DescType = 1;
2123 pSelReg->Attr.n.u2Dpl = 0;
2124 pSelReg->Attr.n.u1Present = 1;
2125 pSelReg->Attr.n.u1DefBig = 1;
2126 pSelReg->Attr.n.u1Granularity = 1;
2127 pSelReg->Attr.n.u1Unusable = fUnusable;
2128 }
2129 }
2130
2131 /* FS base. */
2132 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2133 || fHostInLongMode)
2134 {
2135 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2136 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2137 }
2138
2139 /* GS base. */
2140 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2141 || fHostInLongMode)
2142 {
2143 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2144 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2145 }
2146
2147 /* TR. */
2148 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2149 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2150 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2151 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2152 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2153 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2154 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2155 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2156 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2157 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2158 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2159 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2160 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2161
2162 /* LDTR (Warning! do not touch the base and limits here). */
2163 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2164 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2165 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2166 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2167
2168 /* GDTR. */
2169 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2170 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2171 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2172
2173 /* IDTR.*/
2174 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2175 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2176 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2177}
2178
2179
2180/**
2181 * Checks host PDPTes as part of VM-exit.
2182 *
2183 * @param pVCpu The cross context virtual CPU structure.
2184 * @param uExitReason The VM-exit reason (for logging purposes).
2185 */
2186IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2187{
2188 /*
2189 * Check host PDPTEs.
2190 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2191 */
2192 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2193 const char *const pszFailure = "VMX-abort";
2194 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2195
2196 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2197 && !fHostInLongMode)
2198 {
2199 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2200 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2201 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2202 if (RT_SUCCESS(rc))
2203 {
2204 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2205 {
2206 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2207 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2208 { /* likely */ }
2209 else
2210 {
2211 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2212 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2213 }
2214 }
2215 }
2216 else
2217 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2218 }
2219
2220 NOREF(pszFailure);
2221 NOREF(uExitReason);
2222 return VINF_SUCCESS;
2223}
2224
2225
2226/**
2227 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2228 *
2229 * @returns VBox status code.
2230 * @param pVCpu The cross context virtual CPU structure.
2231 * @param pszInstr The VMX instruction name (for logging purposes).
2232 */
2233IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2234{
2235 /*
2236 * Load host MSRs.
2237 * See Intel spec. 27.6 "Loading MSRs".
2238 */
2239 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2240 const char *const pszFailure = "VMX-abort";
2241
2242 /*
2243 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2244 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2245 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2246 */
2247 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2248 if (!cMsrs)
2249 return VINF_SUCCESS;
2250
2251 /*
2252 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2253 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2254 * implementation causes a VMX-abort followed by a triple-fault.
2255 */
2256 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2257 if (fIsMsrCountValid)
2258 { /* likely */ }
2259 else
2260 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2261
2262 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2263 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2264 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2265 if (RT_SUCCESS(rc))
2266 {
2267 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2268 Assert(pMsr);
2269 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2270 {
2271 if ( !pMsr->u32Reserved
2272 && pMsr->u32Msr != MSR_K8_FS_BASE
2273 && pMsr->u32Msr != MSR_K8_GS_BASE
2274 && pMsr->u32Msr != MSR_K6_EFER
2275 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2276 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2277 {
2278 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2279 if (rcStrict == VINF_SUCCESS)
2280 continue;
2281
2282 /*
2283 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2284 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2285 * recording the MSR index in the auxiliary info. field and indicated further by our
2286 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2287 * if possible, or come up with a better, generic solution.
2288 */
2289 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2290 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2291 ? kVmxVDiag_Vmexit_MsrLoadRing3
2292 : kVmxVDiag_Vmexit_MsrLoad;
2293 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2294 }
2295 else
2296 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2297 }
2298 }
2299 else
2300 {
2301 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2302 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2303 }
2304
2305 NOREF(uExitReason);
2306 NOREF(pszFailure);
2307 return VINF_SUCCESS;
2308}
2309
2310
2311/**
2312 * Loads the host state as part of VM-exit.
2313 *
2314 * @returns Strict VBox status code.
2315 * @param pVCpu The cross context virtual CPU structure.
2316 * @param uExitReason The VM-exit reason (for logging purposes).
2317 */
2318IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2319{
2320 /*
2321 * Load host state.
2322 * See Intel spec. 27.5 "Loading Host State".
2323 */
2324 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2325 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2326
2327 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2328 if ( CPUMIsGuestInLongMode(pVCpu)
2329 && !fHostInLongMode)
2330 {
2331 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2332 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2333 }
2334
2335 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2336 iemVmxVmexitLoadHostSegRegs(pVCpu);
2337
2338 /*
2339 * Load host RIP, RSP and RFLAGS.
2340 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2341 */
2342 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2343 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2344 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2345
2346 /* Clear address range monitoring. */
2347 EMMonitorWaitClear(pVCpu);
2348
2349 /* Perform the VMX transition (PGM updates). */
2350 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2351 if (rcStrict == VINF_SUCCESS)
2352 {
2353 /* Check host PDPTEs (only when we've fully switched page tables_. */
2354 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2355 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2356 if (RT_FAILURE(rc))
2357 {
2358 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2359 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2360 }
2361 }
2362 else if (RT_SUCCESS(rcStrict))
2363 {
2364 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2365 uExitReason));
2366 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2367 }
2368 else
2369 {
2370 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2371 return VBOXSTRICTRC_VAL(rcStrict);
2372 }
2373
2374 Assert(rcStrict == VINF_SUCCESS);
2375
2376 /* Load MSRs from the VM-exit auto-load MSR area. */
2377 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2378 if (RT_FAILURE(rc))
2379 {
2380 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2381 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2382 }
2383 return VINF_SUCCESS;
2384}
2385
2386
2387/**
2388 * Gets VM-exit instruction information along with any displacement for an
2389 * instruction VM-exit.
2390 *
2391 * @returns The VM-exit instruction information.
2392 * @param pVCpu The cross context virtual CPU structure.
2393 * @param uExitReason The VM-exit reason.
2394 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2395 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2396 * NULL.
2397 */
2398IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2399{
2400 RTGCPTR GCPtrDisp;
2401 VMXEXITINSTRINFO ExitInstrInfo;
2402 ExitInstrInfo.u = 0;
2403
2404 /*
2405 * Get and parse the ModR/M byte from our decoded opcodes.
2406 */
2407 uint8_t bRm;
2408 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2409 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2410 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2411 {
2412 /*
2413 * ModR/M indicates register addressing.
2414 *
2415 * The primary/secondary register operands are reported in the iReg1 or iReg2
2416 * fields depending on whether it is a read/write form.
2417 */
2418 uint8_t idxReg1;
2419 uint8_t idxReg2;
2420 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2421 {
2422 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2423 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2424 }
2425 else
2426 {
2427 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2428 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2429 }
2430 ExitInstrInfo.All.u2Scaling = 0;
2431 ExitInstrInfo.All.iReg1 = idxReg1;
2432 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2433 ExitInstrInfo.All.fIsRegOperand = 1;
2434 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2435 ExitInstrInfo.All.iSegReg = 0;
2436 ExitInstrInfo.All.iIdxReg = 0;
2437 ExitInstrInfo.All.fIdxRegInvalid = 1;
2438 ExitInstrInfo.All.iBaseReg = 0;
2439 ExitInstrInfo.All.fBaseRegInvalid = 1;
2440 ExitInstrInfo.All.iReg2 = idxReg2;
2441
2442 /* Displacement not applicable for register addressing. */
2443 GCPtrDisp = 0;
2444 }
2445 else
2446 {
2447 /*
2448 * ModR/M indicates memory addressing.
2449 */
2450 uint8_t uScale = 0;
2451 bool fBaseRegValid = false;
2452 bool fIdxRegValid = false;
2453 uint8_t iBaseReg = 0;
2454 uint8_t iIdxReg = 0;
2455 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2456 {
2457 /*
2458 * Parse the ModR/M, displacement for 16-bit addressing mode.
2459 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2460 */
2461 uint16_t u16Disp = 0;
2462 uint8_t const offDisp = offModRm + sizeof(bRm);
2463 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2464 {
2465 /* Displacement without any registers. */
2466 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2467 }
2468 else
2469 {
2470 /* Register (index and base). */
2471 switch (bRm & X86_MODRM_RM_MASK)
2472 {
2473 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2474 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2475 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2476 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2477 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2478 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2479 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2480 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2481 }
2482
2483 /* Register + displacement. */
2484 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2485 {
2486 case 0: break;
2487 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2488 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2489 default:
2490 {
2491 /* Register addressing, handled at the beginning. */
2492 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2493 break;
2494 }
2495 }
2496 }
2497
2498 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2499 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2500 }
2501 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2502 {
2503 /*
2504 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2505 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2506 */
2507 uint32_t u32Disp = 0;
2508 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2509 {
2510 /* Displacement without any registers. */
2511 uint8_t const offDisp = offModRm + sizeof(bRm);
2512 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2513 }
2514 else
2515 {
2516 /* Register (and perhaps scale, index and base). */
2517 uint8_t offDisp = offModRm + sizeof(bRm);
2518 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2519 if (iBaseReg == 4)
2520 {
2521 /* An SIB byte follows the ModR/M byte, parse it. */
2522 uint8_t bSib;
2523 uint8_t const offSib = offModRm + sizeof(bRm);
2524 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2525
2526 /* A displacement may follow SIB, update its offset. */
2527 offDisp += sizeof(bSib);
2528
2529 /* Get the scale. */
2530 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2531
2532 /* Get the index register. */
2533 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2534 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2535
2536 /* Get the base register. */
2537 iBaseReg = bSib & X86_SIB_BASE_MASK;
2538 fBaseRegValid = true;
2539 if (iBaseReg == 5)
2540 {
2541 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2542 {
2543 /* Mod is 0 implies a 32-bit displacement with no base. */
2544 fBaseRegValid = false;
2545 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2546 }
2547 else
2548 {
2549 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2550 iBaseReg = X86_GREG_xBP;
2551 }
2552 }
2553 }
2554
2555 /* Register + displacement. */
2556 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2557 {
2558 case 0: /* Handled above */ break;
2559 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2560 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2561 default:
2562 {
2563 /* Register addressing, handled at the beginning. */
2564 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2565 break;
2566 }
2567 }
2568 }
2569
2570 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2571 }
2572 else
2573 {
2574 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2575
2576 /*
2577 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2578 * See Intel instruction spec. 2.2 "IA-32e Mode".
2579 */
2580 uint64_t u64Disp = 0;
2581 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2582 if (fRipRelativeAddr)
2583 {
2584 /*
2585 * RIP-relative addressing mode.
2586 *
2587 * The displacement is 32-bit signed implying an offset range of +/-2G.
2588 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2589 */
2590 uint8_t const offDisp = offModRm + sizeof(bRm);
2591 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2592 }
2593 else
2594 {
2595 uint8_t offDisp = offModRm + sizeof(bRm);
2596
2597 /*
2598 * Register (and perhaps scale, index and base).
2599 *
2600 * REX.B extends the most-significant bit of the base register. However, REX.B
2601 * is ignored while determining whether an SIB follows the opcode. Hence, we
2602 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2603 *
2604 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2605 */
2606 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2607 if (iBaseReg == 4)
2608 {
2609 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2610 uint8_t bSib;
2611 uint8_t const offSib = offModRm + sizeof(bRm);
2612 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2613
2614 /* Displacement may follow SIB, update its offset. */
2615 offDisp += sizeof(bSib);
2616
2617 /* Get the scale. */
2618 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2619
2620 /* Get the index. */
2621 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2622 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2623
2624 /* Get the base. */
2625 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2626 fBaseRegValid = true;
2627 if (iBaseReg == 5)
2628 {
2629 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2630 {
2631 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2632 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2633 }
2634 else
2635 {
2636 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2637 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2638 }
2639 }
2640 }
2641 iBaseReg |= pVCpu->iem.s.uRexB;
2642
2643 /* Register + displacement. */
2644 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2645 {
2646 case 0: /* Handled above */ break;
2647 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2648 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2649 default:
2650 {
2651 /* Register addressing, handled at the beginning. */
2652 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2653 break;
2654 }
2655 }
2656 }
2657
2658 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2659 }
2660
2661 /*
2662 * The primary or secondary register operand is reported in iReg2 depending
2663 * on whether the primary operand is in read/write form.
2664 */
2665 uint8_t idxReg2;
2666 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2667 {
2668 idxReg2 = bRm & X86_MODRM_RM_MASK;
2669 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2670 idxReg2 |= pVCpu->iem.s.uRexB;
2671 }
2672 else
2673 {
2674 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2675 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2676 idxReg2 |= pVCpu->iem.s.uRexReg;
2677 }
2678 ExitInstrInfo.All.u2Scaling = uScale;
2679 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2680 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2681 ExitInstrInfo.All.fIsRegOperand = 0;
2682 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2683 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2684 ExitInstrInfo.All.iIdxReg = iIdxReg;
2685 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2686 ExitInstrInfo.All.iBaseReg = iBaseReg;
2687 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2688 ExitInstrInfo.All.iReg2 = idxReg2;
2689 }
2690
2691 /*
2692 * Handle exceptions to the norm for certain instructions.
2693 * (e.g. some instructions convey an instruction identity in place of iReg2).
2694 */
2695 switch (uExitReason)
2696 {
2697 case VMX_EXIT_GDTR_IDTR_ACCESS:
2698 {
2699 Assert(VMXINSTRID_IS_VALID(uInstrId));
2700 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2701 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2702 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2703 break;
2704 }
2705
2706 case VMX_EXIT_LDTR_TR_ACCESS:
2707 {
2708 Assert(VMXINSTRID_IS_VALID(uInstrId));
2709 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2710 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2711 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2712 break;
2713 }
2714
2715 case VMX_EXIT_RDRAND:
2716 case VMX_EXIT_RDSEED:
2717 {
2718 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2719 break;
2720 }
2721 }
2722
2723 /* Update displacement and return the constructed VM-exit instruction information field. */
2724 if (pGCPtrDisp)
2725 *pGCPtrDisp = GCPtrDisp;
2726
2727 return ExitInstrInfo.u;
2728}
2729
2730
2731/**
2732 * VMX VM-exit handler.
2733 *
2734 * @returns Strict VBox status code.
2735 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2736 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2737 * triple-fault.
2738 *
2739 * @param pVCpu The cross context virtual CPU structure.
2740 * @param uExitReason The VM-exit reason.
2741 *
2742 * @remarks Make sure VM-exit qualification is updated before calling this
2743 * function!
2744 */
2745IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2746{
2747# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2748 RT_NOREF2(pVCpu, uExitReason);
2749 return VINF_EM_RAW_EMULATE_INSTR;
2750# else
2751 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2752 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2753 | CPUMCTX_EXTRN_EFER /* MSRs */
2754 | CPUMCTX_EXTRN_SYSENTER_MSRS
2755 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2756 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2757 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2758 | CPUMCTX_EXTRN_TR /* Task register */
2759 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2760 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2761
2762 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2763 Assert(pVmcs);
2764
2765 /* Ensure VM-entry interruption information valid bit isn't set. */
2766 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2767
2768 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2769 pVmcs->u32RoExitReason = uExitReason;
2770 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2771 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2772
2773 /*
2774 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2775 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2776 */
2777 {
2778 uint8_t uVector;
2779 uint32_t fFlags;
2780 uint32_t uErrCode;
2781 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2782 if (!fInEventDelivery)
2783 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2784 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2785 }
2786
2787 /*
2788 * Save the guest state back into the VMCS.
2789 * We only need to save the state when the VM-entry was successful.
2790 */
2791 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2792 if (!fVmentryFailed)
2793 {
2794 /*
2795 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2796 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2797 *
2798 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2799 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2800 * as guest-CPU state would not been modified. Hence for now, we do this only when
2801 * the VM-entry succeeded.
2802 */
2803 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2804 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2805 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2806 {
2807 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2808 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2809 else
2810 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2811 }
2812
2813 /*
2814 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2815 * occurs in enclave mode/SMM which we don't support yet.
2816 *
2817 * If we ever add support for it, we can pass just the lower bits to the functions
2818 * below, till then an assert should suffice.
2819 */
2820 Assert(!RT_HI_U16(uExitReason));
2821
2822 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2823 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2824 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2825 if (RT_SUCCESS(rc))
2826 { /* likely */ }
2827 else
2828 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2829
2830 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2831 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2832 }
2833 else
2834 {
2835 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2836 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2837 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2838 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2839 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2840 }
2841
2842 /*
2843 * Clear any pending VMX nested-guest force-flags.
2844 * These force-flags have no effect on guest execution and will
2845 * be re-evaluated and setup on the next nested-guest VM-entry.
2846 */
2847 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2848 | VMCPU_FF_VMX_MTF
2849 | VMCPU_FF_VMX_APIC_WRITE
2850 | VMCPU_FF_VMX_INT_WINDOW
2851 | VMCPU_FF_VMX_NMI_WINDOW);
2852
2853 /* Restore the host (outer guest) state. */
2854 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2855 if (RT_SUCCESS(rcStrict))
2856 {
2857 Assert(rcStrict == VINF_SUCCESS);
2858 rcStrict = VINF_VMX_VMEXIT;
2859 }
2860 else
2861 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2862
2863 /* We're no longer in nested-guest execution mode. */
2864 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2865
2866# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2867 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2868 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2869 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2870 if (rcSched != VINF_SUCCESS)
2871 iemSetPassUpStatus(pVCpu, rcSched);
2872# endif
2873 return VINF_SUCCESS;
2874# endif
2875}
2876
2877
2878/**
2879 * VMX VM-exit handler for VM-exits due to instruction execution.
2880 *
2881 * This is intended for instructions where the caller provides all the relevant
2882 * VM-exit information.
2883 *
2884 * @returns Strict VBox status code.
2885 * @param pVCpu The cross context virtual CPU structure.
2886 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2887 */
2888DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2889{
2890 /*
2891 * For instructions where any of the following fields are not applicable:
2892 * - VM-exit instruction info. is undefined.
2893 * - VM-exit qualification must be cleared.
2894 * - VM-exit guest-linear address is undefined.
2895 * - VM-exit guest-physical address is undefined.
2896 *
2897 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2898 * instruction execution. For VM-exits that are not due to instruction execution this
2899 * field is undefined.
2900 *
2901 * In our implementation in IEM, all undefined fields are generally cleared. However,
2902 * if the caller supplies information (from say the physical CPU directly) it is
2903 * then possible that the undefined fields are not cleared.
2904 *
2905 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2906 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2907 */
2908 Assert(pExitInfo);
2909 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2910 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2911 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2912
2913 /* Update all the relevant fields from the VM-exit instruction information struct. */
2914 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2915 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2916 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2917 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2918 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2919
2920 /* Perform the VM-exit. */
2921 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2922}
2923
2924
2925/**
2926 * VMX VM-exit handler for VM-exits due to instruction execution.
2927 *
2928 * This is intended for instructions that only provide the VM-exit instruction
2929 * length.
2930 *
2931 * @param pVCpu The cross context virtual CPU structure.
2932 * @param uExitReason The VM-exit reason.
2933 * @param cbInstr The instruction length in bytes.
2934 */
2935IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2936{
2937 VMXVEXITINFO ExitInfo;
2938 RT_ZERO(ExitInfo);
2939 ExitInfo.uReason = uExitReason;
2940 ExitInfo.cbInstr = cbInstr;
2941
2942#ifdef VBOX_STRICT
2943 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2944 switch (uExitReason)
2945 {
2946 case VMX_EXIT_INVEPT:
2947 case VMX_EXIT_INVPCID:
2948 case VMX_EXIT_LDTR_TR_ACCESS:
2949 case VMX_EXIT_GDTR_IDTR_ACCESS:
2950 case VMX_EXIT_VMCLEAR:
2951 case VMX_EXIT_VMPTRLD:
2952 case VMX_EXIT_VMPTRST:
2953 case VMX_EXIT_VMREAD:
2954 case VMX_EXIT_VMWRITE:
2955 case VMX_EXIT_VMXON:
2956 case VMX_EXIT_XRSTORS:
2957 case VMX_EXIT_XSAVES:
2958 case VMX_EXIT_RDRAND:
2959 case VMX_EXIT_RDSEED:
2960 case VMX_EXIT_IO_INSTR:
2961 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2962 break;
2963 }
2964#endif
2965
2966 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2967}
2968
2969
2970/**
2971 * VMX VM-exit handler for VM-exits due to instruction execution.
2972 *
2973 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2974 * instruction information and VM-exit qualification fields.
2975 *
2976 * @param pVCpu The cross context virtual CPU structure.
2977 * @param uExitReason The VM-exit reason.
2978 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2979 * @param cbInstr The instruction length in bytes.
2980 *
2981 * @remarks Do not use this for INS/OUTS instruction.
2982 */
2983IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2984{
2985 VMXVEXITINFO ExitInfo;
2986 RT_ZERO(ExitInfo);
2987 ExitInfo.uReason = uExitReason;
2988 ExitInfo.cbInstr = cbInstr;
2989
2990 /*
2991 * Update the VM-exit qualification field with displacement bytes.
2992 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2993 */
2994 switch (uExitReason)
2995 {
2996 case VMX_EXIT_INVEPT:
2997 case VMX_EXIT_INVPCID:
2998 case VMX_EXIT_LDTR_TR_ACCESS:
2999 case VMX_EXIT_GDTR_IDTR_ACCESS:
3000 case VMX_EXIT_VMCLEAR:
3001 case VMX_EXIT_VMPTRLD:
3002 case VMX_EXIT_VMPTRST:
3003 case VMX_EXIT_VMREAD:
3004 case VMX_EXIT_VMWRITE:
3005 case VMX_EXIT_VMXON:
3006 case VMX_EXIT_XRSTORS:
3007 case VMX_EXIT_XSAVES:
3008 case VMX_EXIT_RDRAND:
3009 case VMX_EXIT_RDSEED:
3010 {
3011 /* Construct the VM-exit instruction information. */
3012 RTGCPTR GCPtrDisp;
3013 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3014
3015 /* Update the VM-exit instruction information. */
3016 ExitInfo.InstrInfo.u = uInstrInfo;
3017
3018 /* Update the VM-exit qualification. */
3019 ExitInfo.u64Qual = GCPtrDisp;
3020 break;
3021 }
3022
3023 default:
3024 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3025 break;
3026 }
3027
3028 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3029}
3030
3031
3032/**
3033 * VMX VM-exit handler for VM-exits due to INVLPG.
3034 *
3035 * @returns Strict VBox status code.
3036 * @param pVCpu The cross context virtual CPU structure.
3037 * @param GCPtrPage The guest-linear address of the page being invalidated.
3038 * @param cbInstr The instruction length in bytes.
3039 */
3040IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3041{
3042 VMXVEXITINFO ExitInfo;
3043 RT_ZERO(ExitInfo);
3044 ExitInfo.uReason = VMX_EXIT_INVLPG;
3045 ExitInfo.cbInstr = cbInstr;
3046 ExitInfo.u64Qual = GCPtrPage;
3047 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3048
3049 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3050}
3051
3052
3053/**
3054 * VMX VM-exit handler for VM-exits due to LMSW.
3055 *
3056 * @returns Strict VBox status code.
3057 * @param pVCpu The cross context virtual CPU structure.
3058 * @param uGuestCr0 The current guest CR0.
3059 * @param pu16NewMsw The machine-status word specified in LMSW's source
3060 * operand. This will be updated depending on the VMX
3061 * guest/host CR0 mask if LMSW is not intercepted.
3062 * @param GCPtrEffDst The guest-linear address of the source operand in case
3063 * of a memory operand. For register operand, pass
3064 * NIL_RTGCPTR.
3065 * @param cbInstr The instruction length in bytes.
3066 */
3067IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3068 uint8_t cbInstr)
3069{
3070 /*
3071 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3072 *
3073 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3074 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3075 */
3076 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3077 Assert(pVmcs);
3078 Assert(pu16NewMsw);
3079
3080 bool fIntercept = false;
3081 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3082 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3083
3084 /*
3085 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3086 * CR0.PE case first, before the rest of the bits in the MSW.
3087 *
3088 * If CR0.PE is owned by the host and CR0.PE differs between the
3089 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3090 */
3091 if ( (fGstHostMask & X86_CR0_PE)
3092 && (*pu16NewMsw & X86_CR0_PE)
3093 && !(fReadShadow & X86_CR0_PE))
3094 fIntercept = true;
3095
3096 /*
3097 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3098 * bits differ between the MSW (source operand) and the read-shadow, we must
3099 * cause a VM-exit.
3100 */
3101 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3102 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3103 fIntercept = true;
3104
3105 if (fIntercept)
3106 {
3107 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3108
3109 VMXVEXITINFO ExitInfo;
3110 RT_ZERO(ExitInfo);
3111 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3112 ExitInfo.cbInstr = cbInstr;
3113
3114 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3115 if (fMemOperand)
3116 {
3117 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3118 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3119 }
3120
3121 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3122 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3123 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3124 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3125
3126 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3127 }
3128
3129 /*
3130 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3131 * CR0 guest/host mask must be left unmodified.
3132 *
3133 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3134 */
3135 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3136 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3137
3138 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3139}
3140
3141
3142/**
3143 * VMX VM-exit handler for VM-exits due to CLTS.
3144 *
3145 * @returns Strict VBox status code.
3146 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3147 * VM-exit but must not modify the guest CR0.TS bit.
3148 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3149 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3150 * CR0 fixed bits in VMX operation).
3151 * @param pVCpu The cross context virtual CPU structure.
3152 * @param cbInstr The instruction length in bytes.
3153 */
3154IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3155{
3156 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3157 Assert(pVmcs);
3158
3159 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3160 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3161
3162 /*
3163 * If CR0.TS is owned by the host:
3164 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3165 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3166 * CLTS instruction completes without clearing CR0.TS.
3167 *
3168 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3169 */
3170 if (fGstHostMask & X86_CR0_TS)
3171 {
3172 if (fReadShadow & X86_CR0_TS)
3173 {
3174 Log2(("clts: Guest intercept -> VM-exit\n"));
3175
3176 VMXVEXITINFO ExitInfo;
3177 RT_ZERO(ExitInfo);
3178 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3179 ExitInfo.cbInstr = cbInstr;
3180 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3181 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3182 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3183 }
3184
3185 return VINF_VMX_MODIFIES_BEHAVIOR;
3186 }
3187
3188 /*
3189 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3190 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3191 */
3192 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3193}
3194
3195
3196/**
3197 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3198 * (CR0/CR4 write).
3199 *
3200 * @returns Strict VBox status code.
3201 * @param pVCpu The cross context virtual CPU structure.
3202 * @param iCrReg The control register (either CR0 or CR4).
3203 * @param uGuestCrX The current guest CR0/CR4.
3204 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3205 * if no VM-exit is caused.
3206 * @param iGReg The general register from which the CR0/CR4 value is
3207 * being loaded.
3208 * @param cbInstr The instruction length in bytes.
3209 */
3210IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3211 uint8_t cbInstr)
3212{
3213 Assert(puNewCrX);
3214 Assert(iCrReg == 0 || iCrReg == 4);
3215 Assert(iGReg < X86_GREG_COUNT);
3216
3217 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3218 Assert(pVmcs);
3219
3220 uint64_t uGuestCrX;
3221 uint64_t fGstHostMask;
3222 uint64_t fReadShadow;
3223 if (iCrReg == 0)
3224 {
3225 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3226 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3227 fGstHostMask = pVmcs->u64Cr0Mask.u;
3228 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3229 }
3230 else
3231 {
3232 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3233 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3234 fGstHostMask = pVmcs->u64Cr4Mask.u;
3235 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3236 }
3237
3238 /*
3239 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3240 * corresponding bits differ between the source operand and the read-shadow,
3241 * we must cause a VM-exit.
3242 *
3243 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3244 */
3245 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3246 {
3247 Assert(fGstHostMask != 0);
3248 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3249
3250 VMXVEXITINFO ExitInfo;
3251 RT_ZERO(ExitInfo);
3252 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3253 ExitInfo.cbInstr = cbInstr;
3254 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3255 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3256 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3257 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3258 }
3259
3260 /*
3261 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3262 * must not be modified the instruction.
3263 *
3264 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3265 */
3266 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3267
3268 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3269}
3270
3271
3272/**
3273 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3274 *
3275 * @returns VBox strict status code.
3276 * @param pVCpu The cross context virtual CPU structure.
3277 * @param iGReg The general register to which the CR3 value is being stored.
3278 * @param cbInstr The instruction length in bytes.
3279 */
3280IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3281{
3282 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3283 Assert(pVmcs);
3284 Assert(iGReg < X86_GREG_COUNT);
3285 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3286
3287 /*
3288 * If the CR3-store exiting control is set, we must cause a VM-exit.
3289 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3290 */
3291 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3292 {
3293 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3294
3295 VMXVEXITINFO ExitInfo;
3296 RT_ZERO(ExitInfo);
3297 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3298 ExitInfo.cbInstr = cbInstr;
3299 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3300 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3301 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3302 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3303 }
3304
3305 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3306}
3307
3308
3309/**
3310 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3311 *
3312 * @returns VBox strict status code.
3313 * @param pVCpu The cross context virtual CPU structure.
3314 * @param uNewCr3 The new CR3 value.
3315 * @param iGReg The general register from which the CR3 value is being
3316 * loaded.
3317 * @param cbInstr The instruction length in bytes.
3318 */
3319IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3320{
3321 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3322 Assert(pVmcs);
3323 Assert(iGReg < X86_GREG_COUNT);
3324
3325 /*
3326 * If the CR3-load exiting control is set and the new CR3 value does not
3327 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3328 *
3329 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3330 */
3331 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3332 {
3333 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3334 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3335
3336 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3337 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3338 if (!fIntercept)
3339 {
3340 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3341 {
3342 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3343 if (uNewCr3 != uCr3TargetValue)
3344 {
3345 fIntercept = true;
3346 break;
3347 }
3348 }
3349 }
3350
3351 if (fIntercept)
3352 {
3353 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3354
3355 VMXVEXITINFO ExitInfo;
3356 RT_ZERO(ExitInfo);
3357 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3358 ExitInfo.cbInstr = cbInstr;
3359 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3360 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3361 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3362 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3363 }
3364 }
3365
3366 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3367}
3368
3369
3370/**
3371 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3372 *
3373 * @returns VBox strict status code.
3374 * @param pVCpu The cross context virtual CPU structure.
3375 * @param iGReg The general register to which the CR8 value is being stored.
3376 * @param cbInstr The instruction length in bytes.
3377 */
3378IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3379{
3380 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3381 Assert(pVmcs);
3382 Assert(iGReg < X86_GREG_COUNT);
3383
3384 /*
3385 * If the CR8-store exiting control is set, we must cause a VM-exit.
3386 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3387 */
3388 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3389 {
3390 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3391
3392 VMXVEXITINFO ExitInfo;
3393 RT_ZERO(ExitInfo);
3394 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3395 ExitInfo.cbInstr = cbInstr;
3396 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3397 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3398 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3399 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3400 }
3401
3402 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3403}
3404
3405
3406/**
3407 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3408 *
3409 * @returns VBox strict status code.
3410 * @param pVCpu The cross context virtual CPU structure.
3411 * @param iGReg The general register from which the CR8 value is being
3412 * loaded.
3413 * @param cbInstr The instruction length in bytes.
3414 */
3415IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3416{
3417 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3418 Assert(pVmcs);
3419 Assert(iGReg < X86_GREG_COUNT);
3420
3421 /*
3422 * If the CR8-load exiting control is set, we must cause a VM-exit.
3423 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3424 */
3425 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3426 {
3427 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3428
3429 VMXVEXITINFO ExitInfo;
3430 RT_ZERO(ExitInfo);
3431 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3432 ExitInfo.cbInstr = cbInstr;
3433 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3434 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3435 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3436 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3437 }
3438
3439 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3440}
3441
3442
3443/**
3444 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3445 * GReg,DRx' (DRx read).
3446 *
3447 * @returns VBox strict status code.
3448 * @param pVCpu The cross context virtual CPU structure.
3449 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3450 * VMXINSTRID_MOV_FROM_DRX).
3451 * @param iDrReg The debug register being accessed.
3452 * @param iGReg The general register to/from which the DRx value is being
3453 * store/loaded.
3454 * @param cbInstr The instruction length in bytes.
3455 */
3456IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3457 uint8_t cbInstr)
3458{
3459 Assert(iDrReg <= 7);
3460 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3461 Assert(iGReg < X86_GREG_COUNT);
3462
3463 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3464 Assert(pVmcs);
3465
3466 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3467 {
3468 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3469 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3470 VMXVEXITINFO ExitInfo;
3471 RT_ZERO(ExitInfo);
3472 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3473 ExitInfo.cbInstr = cbInstr;
3474 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3476 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3477 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3478 }
3479
3480 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3481}
3482
3483
3484/**
3485 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3486 *
3487 * @returns VBox strict status code.
3488 * @param pVCpu The cross context virtual CPU structure.
3489 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3490 * VMXINSTRID_IO_OUT).
3491 * @param u16Port The I/O port being accessed.
3492 * @param fImm Whether the I/O port was encoded using an immediate operand
3493 * or the implicit DX register.
3494 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3495 * @param cbInstr The instruction length in bytes.
3496 */
3497IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3498 uint8_t cbInstr)
3499{
3500 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3501 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3502
3503 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3504 if (fIntercept)
3505 {
3506 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3507 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3508 VMXVEXITINFO ExitInfo;
3509 RT_ZERO(ExitInfo);
3510 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3511 ExitInfo.cbInstr = cbInstr;
3512 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3513 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3514 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3515 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3516 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3517 }
3518
3519 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3520}
3521
3522
3523/**
3524 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3525 *
3526 * @returns VBox strict status code.
3527 * @param pVCpu The cross context virtual CPU structure.
3528 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3529 * VMXINSTRID_IO_OUTS).
3530 * @param u16Port The I/O port being accessed.
3531 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3532 * @param fRep Whether the instruction has a REP prefix or not.
3533 * @param ExitInstrInfo The VM-exit instruction info. field.
3534 * @param cbInstr The instruction length in bytes.
3535 */
3536IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3537 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3538{
3539 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3540 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3541 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3542 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3543 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3544
3545 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3546 if (fIntercept)
3547 {
3548 /*
3549 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3550 */
3551 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3552 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3553 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3554 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3555 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3556
3557 uint32_t uDirection;
3558 uint64_t uGuestLinearAddr;
3559 if (uInstrId == VMXINSTRID_IO_INS)
3560 {
3561 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3562 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3563 }
3564 else
3565 {
3566 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3567 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3568 }
3569
3570 /*
3571 * If the segment is ununsable, the guest-linear address in undefined.
3572 * We shall clear it for consistency.
3573 *
3574 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3575 */
3576 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3577 uGuestLinearAddr = 0;
3578
3579 VMXVEXITINFO ExitInfo;
3580 RT_ZERO(ExitInfo);
3581 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3582 ExitInfo.cbInstr = cbInstr;
3583 ExitInfo.InstrInfo = ExitInstrInfo;
3584 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3585 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3586 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3587 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3588 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3589 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3590 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3591 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3592 }
3593
3594 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3595}
3596
3597
3598/**
3599 * VMX VM-exit handler for VM-exits due to MWAIT.
3600 *
3601 * @returns VBox strict status code.
3602 * @param pVCpu The cross context virtual CPU structure.
3603 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3604 * @param cbInstr The instruction length in bytes.
3605 */
3606IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3607{
3608 VMXVEXITINFO ExitInfo;
3609 RT_ZERO(ExitInfo);
3610 ExitInfo.uReason = VMX_EXIT_MWAIT;
3611 ExitInfo.cbInstr = cbInstr;
3612 ExitInfo.u64Qual = fMonitorHwArmed;
3613 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3614}
3615
3616
3617/**
3618 * VMX VM-exit handler for VM-exits due to PAUSE.
3619 *
3620 * @returns VBox strict status code.
3621 * @param pVCpu The cross context virtual CPU structure.
3622 * @param cbInstr The instruction length in bytes.
3623 */
3624IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3625{
3626 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3627 Assert(pVmcs);
3628
3629 /*
3630 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3631 * "PAUSE-loop exiting" control.
3632 *
3633 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3634 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3635 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3636 * a VM-exit.
3637 *
3638 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3639 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3640 */
3641 bool fIntercept = false;
3642 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3643 fIntercept = true;
3644 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3645 && pVCpu->iem.s.uCpl == 0)
3646 {
3647 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3648
3649 /*
3650 * A previous-PAUSE-tick value of 0 is used to identify the first time
3651 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3652 * consider this to be the first execution of PAUSE in a loop according
3653 * to the Intel.
3654 *
3655 * All subsequent records for the previous-PAUSE-tick we ensure that it
3656 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3657 */
3658 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3659 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3660 uint64_t const uTick = TMCpuTickGet(pVCpu);
3661 uint32_t const uPleGap = pVmcs->u32PleGap;
3662 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3663 if ( *puPrevPauseTick == 0
3664 || uTick - *puPrevPauseTick > uPleGap)
3665 *puFirstPauseLoopTick = uTick;
3666 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3667 fIntercept = true;
3668
3669 *puPrevPauseTick = uTick | 1;
3670 }
3671
3672 if (fIntercept)
3673 {
3674 VMXVEXITINFO ExitInfo;
3675 RT_ZERO(ExitInfo);
3676 ExitInfo.uReason = VMX_EXIT_PAUSE;
3677 ExitInfo.cbInstr = cbInstr;
3678 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3679 }
3680
3681 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3682}
3683
3684
3685/**
3686 * VMX VM-exit handler for VM-exits due to task switches.
3687 *
3688 * @returns VBox strict status code.
3689 * @param pVCpu The cross context virtual CPU structure.
3690 * @param enmTaskSwitch The cause of the task switch.
3691 * @param SelNewTss The selector of the new TSS.
3692 * @param cbInstr The instruction length in bytes.
3693 */
3694IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3695{
3696 /*
3697 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3698 *
3699 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3700 * instruction or delivery of the exception generated by one of these instructions
3701 * lead to a task switch through a task gate in the IDT, we need to provide the
3702 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3703 * leaves the VM-exit instruction length field undefined.
3704 *
3705 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3706 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3707 */
3708 Assert(cbInstr <= 15);
3709
3710 uint8_t uType;
3711 switch (enmTaskSwitch)
3712 {
3713 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3714 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3715 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3716 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3717 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3718 }
3719
3720 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3721 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3722 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3723 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3724 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3725}
3726
3727
3728/**
3729 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3730 *
3731 * @returns VBox strict status code.
3732 * @param pVCpu The cross context virtual CPU structure.
3733 */
3734IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3735{
3736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3737 Assert(pVmcs);
3738
3739 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3740 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3741 {
3742 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3743 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3744
3745 /*
3746 * Calculate the current VMX-preemption timer value.
3747 * Only if the value has reached zero, we cause the VM-exit.
3748 */
3749 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3750 if (!uPreemptTimer)
3751 {
3752 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3753 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3754 pVmcs->u32PreemptTimer = 0;
3755
3756 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3757 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3758 }
3759 }
3760
3761 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3762}
3763
3764
3765/**
3766 * VMX VM-exit handler for VM-exits due to external interrupts.
3767 *
3768 * @returns VBox strict status code.
3769 * @param pVCpu The cross context virtual CPU structure.
3770 * @param uVector The external interrupt vector (pass 0 if the interrupt
3771 * is still pending since we typically won't know the
3772 * vector).
3773 * @param fIntPending Whether the external interrupt is pending or
3774 * acknowledged in the interrupt controller.
3775 */
3776IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3777{
3778 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3779 Assert(pVmcs);
3780 Assert(fIntPending || uVector == 0);
3781
3782 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3783 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3784 * functions require prior checking of a blanket intercept and which don't.
3785 * It is better for the caller to check a blanket intercept performance wise
3786 * than making a function call. Leaving this as a todo because it is more
3787 * a performance issue. */
3788
3789 /* The VM-exit is subject to "External interrupt exiting" being set. */
3790 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3791 {
3792 if (fIntPending)
3793 {
3794 /*
3795 * If the interrupt is pending and we don't need to acknowledge the
3796 * interrupt on VM-exit, cause the VM-exit immediately.
3797 *
3798 * See Intel spec 25.2 "Other Causes Of VM Exits".
3799 */
3800 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3801 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3802
3803 /*
3804 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3805 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3806 * acknowledged that the interrupt has been consumed.
3807 */
3808 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3809 }
3810
3811 /*
3812 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3813 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3814 * all set, we cause the VM-exit now. We need to record the external interrupt that
3815 * just occurred in the VM-exit interruption information field.
3816 *
3817 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3818 */
3819 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3820 {
3821 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3822 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3823 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3824 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3825 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3826 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3827 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3828 }
3829 }
3830
3831 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3832}
3833
3834
3835/**
3836 * VMX VM-exit handler for VM-exits due to NMIs.
3837 *
3838 * @returns VBox strict status code.
3839 * @param pVCpu The cross context virtual CPU structure.
3840 *
3841 * @remarks This function might import externally kept DR6 if necessary.
3842 */
3843IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3844{
3845 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3846 Assert(pVmcs);
3847 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3848 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3849 NOREF(pVmcs);
3850 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3851}
3852
3853
3854/**
3855 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3856 *
3857 * @returns VBox strict status code.
3858 * @param pVCpu The cross context virtual CPU structure.
3859 * @param uVector The SIPI vector.
3860 */
3861IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3862{
3863 iemVmxVmcsSetExitQual(pVCpu, uVector);
3864 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3865}
3866
3867
3868/**
3869 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3870 * an event.
3871 *
3872 * @returns VBox strict status code.
3873 * @param pVCpu The cross context virtual CPU structure.
3874 */
3875IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3876{
3877 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3878 Assert(pVmcs);
3879
3880 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3881 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3882 {
3883 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3884 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3885 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3886 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3887 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3888 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3889 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3890 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3891 iemVmxVmcsSetExitQual(pVCpu, 0);
3892 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3893
3894 /*
3895 * A VM-exit is not considered to occur during event delivery when the original
3896 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3897 * using the exception bitmap).
3898 *
3899 * Therefore, we must clear the original event from the IDT-vectoring fields which
3900 * would've been recorded before causing the VM-exit.
3901 *
3902 * 27.2.3 "Information for VM Exits During Event Delivery"
3903 */
3904 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3905 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3906
3907 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3908 }
3909
3910 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3911}
3912
3913
3914/**
3915 * VMX VM-exit handler for VM-exits due to delivery of an event.
3916 *
3917 * @returns VBox strict status code.
3918 * @param pVCpu The cross context virtual CPU structure.
3919 * @param uVector The interrupt / exception vector.
3920 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3921 * @param uErrCode The error code associated with the event.
3922 * @param uCr2 The CR2 value in case of a \#PF exception.
3923 * @param cbInstr The instruction length in bytes.
3924 */
3925IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3926 uint8_t cbInstr)
3927{
3928 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3929 Assert(pVmcs);
3930
3931 /*
3932 * If the event is being injected as part of VM-entry, it isn't subject to event
3933 * intercepts in the nested-guest. However, secondary exceptions that occur during
3934 * injection of any event -are- subject to event interception.
3935 *
3936 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3937 */
3938 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3939 {
3940 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3941 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3942 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3943 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3944 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3945 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3946 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3947 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3948 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3949
3950 /*
3951 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3952 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3953 *
3954 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3955 */
3956 if ( uVector == X86_XCPT_NMI
3957 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3958 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3959 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3960 else
3961 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3962
3963 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3964 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3965 }
3966
3967 /*
3968 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3969 * If not, the caller will continue delivery of the external interrupt as it would
3970 * normally. The interrupt is no longer pending in the interrupt controller at this
3971 * point.
3972 */
3973 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3974 {
3975 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3976 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3977 }
3978
3979 /*
3980 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3981 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3982 */
3983 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3984 bool fIntercept = false;
3985 bool fIsHwXcpt = false;
3986 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3987 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3988 {
3989 fIsHwXcpt = true;
3990 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
3991 if (uVector == X86_XCPT_NMI)
3992 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3993 else
3994 {
3995 /* Page-faults are subject to masking using its error code. */
3996 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
3997 if (uVector == X86_XCPT_PF)
3998 {
3999 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4000 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4001 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4002 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4003 }
4004
4005 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4006 if (fXcptBitmap & RT_BIT(uVector))
4007 fIntercept = true;
4008 }
4009 }
4010 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4011
4012 /*
4013 * Now that we've determined whether the software interrupt or hardware exception
4014 * causes a VM-exit, we need to construct the relevant VM-exit information and
4015 * cause the VM-exit.
4016 */
4017 if (fIntercept)
4018 {
4019 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4020
4021 /* Construct the rest of the event related information fields and cause the VM-exit. */
4022 uint64_t uExitQual = 0;
4023 if (fIsHwXcpt)
4024 {
4025 if (uVector == X86_XCPT_PF)
4026 {
4027 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4028 uExitQual = uCr2;
4029 }
4030 else if (uVector == X86_XCPT_DB)
4031 {
4032 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4033 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4034 }
4035 }
4036
4037 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4038 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4039 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4040 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4041 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4042 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4043 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4044 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4045 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4046 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4047 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4048
4049 /*
4050 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4051 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4052 * length.
4053 */
4054 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4055 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4056 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4057 else
4058 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4059
4060 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4061 }
4062
4063 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4064}
4065
4066
4067/**
4068 * VMX VM-exit handler for VM-exits due to a triple fault.
4069 *
4070 * @returns VBox strict status code.
4071 * @param pVCpu The cross context virtual CPU structure.
4072 */
4073IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4074{
4075 /*
4076 * A VM-exit is not considered to occur during event delivery when the original
4077 * event results in a triple-fault.
4078 *
4079 * Therefore, we must clear the original event from the IDT-vectoring fields which
4080 * would've been recorded before causing the VM-exit.
4081 *
4082 * 27.2.3 "Information for VM Exits During Event Delivery"
4083 */
4084 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4085 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4086
4087 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4088}
4089
4090
4091/**
4092 * VMX VM-exit handler for APIC-accesses.
4093 *
4094 * @param pVCpu The cross context virtual CPU structure.
4095 * @param offAccess The offset of the register being accessed.
4096 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4097 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4098 */
4099IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4100{
4101 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4102
4103 VMXAPICACCESS enmAccess;
4104 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4105 if (fInEventDelivery)
4106 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4107 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4108 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4109 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4110 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4111 else
4112 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4113
4114 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4115 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4116 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4117 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4118}
4119
4120
4121/**
4122 * VMX VM-exit handler for APIC-write VM-exits.
4123 *
4124 * @param pVCpu The cross context virtual CPU structure.
4125 * @param offApic The write to the virtual-APIC page offset that caused this
4126 * VM-exit.
4127 */
4128IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4129{
4130 Assert(offApic < XAPIC_OFF_END + 4);
4131
4132 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4133 offApic &= UINT16_C(0xfff);
4134 iemVmxVmcsSetExitQual(pVCpu, offApic);
4135 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4136}
4137
4138
4139/**
4140 * VMX VM-exit handler for virtualized-EOIs.
4141 *
4142 * @param pVCpu The cross context virtual CPU structure.
4143 */
4144IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4145{
4146 iemVmxVmcsSetExitQual(pVCpu, uVector);
4147 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4148}
4149
4150
4151/**
4152 * Sets virtual-APIC write emulation as pending.
4153 *
4154 * @param pVCpu The cross context virtual CPU structure.
4155 * @param offApic The offset in the virtual-APIC page that was written.
4156 */
4157DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4158{
4159 Assert(offApic < XAPIC_OFF_END + 4);
4160
4161 /*
4162 * Record the currently updated APIC offset, as we need this later for figuring
4163 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4164 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4165 */
4166 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4167
4168 /*
4169 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4170 * virtualization or APIC-write emulation).
4171 */
4172 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4173 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4174}
4175
4176
4177/**
4178 * Clears any pending virtual-APIC write emulation.
4179 *
4180 * @returns The virtual-APIC offset that was written before clearing it.
4181 * @param pVCpu The cross context virtual CPU structure.
4182 */
4183DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4184{
4185 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4186 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4187 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4188 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4189 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4190 return offVirtApicWrite;
4191}
4192
4193
4194/**
4195 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4196 *
4197 * @returns The register from the virtual-APIC page.
4198 * @param pVCpu The cross context virtual CPU structure.
4199 * @param offReg The offset of the register being read.
4200 */
4201IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4202{
4203 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4204 Assert(pVmcs);
4205
4206 uint32_t uReg;
4207 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4208 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4209 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4210 if (RT_FAILURE(rc))
4211 {
4212 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4213 GCPhysVirtApic));
4214 uReg = 0;
4215 }
4216 return uReg;
4217}
4218
4219
4220/**
4221 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4222 *
4223 * @returns The register from the virtual-APIC page.
4224 * @param pVCpu The cross context virtual CPU structure.
4225 * @param offReg The offset of the register being read.
4226 */
4227IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4228{
4229 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4230 Assert(pVmcs);
4231
4232 uint64_t uReg;
4233 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4234 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4235 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4236 if (RT_FAILURE(rc))
4237 {
4238 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4239 GCPhysVirtApic));
4240 uReg = 0;
4241 }
4242 return uReg;
4243}
4244
4245
4246/**
4247 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4248 *
4249 * @param pVCpu The cross context virtual CPU structure.
4250 * @param offReg The offset of the register being written.
4251 * @param uReg The register value to write.
4252 */
4253IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4254{
4255 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4256 Assert(pVmcs);
4257 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4258 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4259 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4260 if (RT_FAILURE(rc))
4261 {
4262 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4263 GCPhysVirtApic));
4264 }
4265}
4266
4267
4268/**
4269 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4270 *
4271 * @param pVCpu The cross context virtual CPU structure.
4272 * @param offReg The offset of the register being written.
4273 * @param uReg The register value to write.
4274 */
4275IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4276{
4277 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4278 Assert(pVmcs);
4279 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4280 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4281 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4282 if (RT_FAILURE(rc))
4283 {
4284 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4285 GCPhysVirtApic));
4286 }
4287}
4288
4289
4290/**
4291 * Sets the vector in a virtual-APIC 256-bit sparse register.
4292 *
4293 * @param pVCpu The cross context virtual CPU structure.
4294 * @param offReg The offset of the 256-bit spare register.
4295 * @param uVector The vector to set.
4296 *
4297 * @remarks This is based on our APIC device code.
4298 */
4299IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4300{
4301 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4302 Assert(pVmcs);
4303 uint32_t uReg;
4304 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4305 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4306 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4307 if (RT_SUCCESS(rc))
4308 {
4309 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4310 uReg |= RT_BIT(idxVectorBit);
4311 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4312 if (RT_FAILURE(rc))
4313 {
4314 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4315 uVector, offReg, GCPhysVirtApic));
4316 }
4317 }
4318 else
4319 {
4320 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4321 uVector, offReg, GCPhysVirtApic));
4322 }
4323}
4324
4325
4326/**
4327 * Clears the vector in a virtual-APIC 256-bit sparse register.
4328 *
4329 * @param pVCpu The cross context virtual CPU structure.
4330 * @param offReg The offset of the 256-bit spare register.
4331 * @param uVector The vector to clear.
4332 *
4333 * @remarks This is based on our APIC device code.
4334 */
4335IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4336{
4337 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4338 Assert(pVmcs);
4339 uint32_t uReg;
4340 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4341 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4342 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4343 if (RT_SUCCESS(rc))
4344 {
4345 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4346 uReg &= ~RT_BIT(idxVectorBit);
4347 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4348 if (RT_FAILURE(rc))
4349 {
4350 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4351 uVector, offReg, GCPhysVirtApic));
4352 }
4353 }
4354 else
4355 {
4356 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4357 uVector, offReg, GCPhysVirtApic));
4358 }
4359}
4360
4361
4362/**
4363 * Checks if a memory access to the APIC-access page must causes an APIC-access
4364 * VM-exit.
4365 *
4366 * @param pVCpu The cross context virtual CPU structure.
4367 * @param offAccess The offset of the register being accessed.
4368 * @param cbAccess The size of the access in bytes.
4369 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4370 * IEM_ACCESS_TYPE_WRITE).
4371 *
4372 * @remarks This must not be used for MSR-based APIC-access page accesses!
4373 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4374 */
4375IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4376{
4377 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4378 Assert(pVmcs);
4379 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4380
4381 /*
4382 * We must cause a VM-exit if any of the following are true:
4383 * - TPR shadowing isn't active.
4384 * - The access size exceeds 32-bits.
4385 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4386 *
4387 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4388 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4389 */
4390 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4391 || cbAccess > sizeof(uint32_t)
4392 || ((offAccess + cbAccess - 1) & 0xc)
4393 || offAccess >= XAPIC_OFF_END + 4)
4394 return true;
4395
4396 /*
4397 * If the access is part of an operation where we have already
4398 * virtualized a virtual-APIC write, we must cause a VM-exit.
4399 */
4400 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4401 return true;
4402
4403 /*
4404 * Check write accesses to the APIC-access page that cause VM-exits.
4405 */
4406 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4407 {
4408 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4409 {
4410 /*
4411 * With APIC-register virtualization, a write access to any of the
4412 * following registers are virtualized. Accessing any other register
4413 * causes a VM-exit.
4414 */
4415 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4416 switch (offAlignedAccess)
4417 {
4418 case XAPIC_OFF_ID:
4419 case XAPIC_OFF_TPR:
4420 case XAPIC_OFF_EOI:
4421 case XAPIC_OFF_LDR:
4422 case XAPIC_OFF_DFR:
4423 case XAPIC_OFF_SVR:
4424 case XAPIC_OFF_ESR:
4425 case XAPIC_OFF_ICR_LO:
4426 case XAPIC_OFF_ICR_HI:
4427 case XAPIC_OFF_LVT_TIMER:
4428 case XAPIC_OFF_LVT_THERMAL:
4429 case XAPIC_OFF_LVT_PERF:
4430 case XAPIC_OFF_LVT_LINT0:
4431 case XAPIC_OFF_LVT_LINT1:
4432 case XAPIC_OFF_LVT_ERROR:
4433 case XAPIC_OFF_TIMER_ICR:
4434 case XAPIC_OFF_TIMER_DCR:
4435 break;
4436 default:
4437 return true;
4438 }
4439 }
4440 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4441 {
4442 /*
4443 * With virtual-interrupt delivery, a write access to any of the
4444 * following registers are virtualized. Accessing any other register
4445 * causes a VM-exit.
4446 *
4447 * Note! The specification does not allow writing to offsets in-between
4448 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4449 */
4450 switch (offAccess)
4451 {
4452 case XAPIC_OFF_TPR:
4453 case XAPIC_OFF_EOI:
4454 case XAPIC_OFF_ICR_LO:
4455 break;
4456 default:
4457 return true;
4458 }
4459 }
4460 else
4461 {
4462 /*
4463 * Without APIC-register virtualization or virtual-interrupt delivery,
4464 * only TPR accesses are virtualized.
4465 */
4466 if (offAccess == XAPIC_OFF_TPR)
4467 { /* likely */ }
4468 else
4469 return true;
4470 }
4471 }
4472 else
4473 {
4474 /*
4475 * Check read accesses to the APIC-access page that cause VM-exits.
4476 */
4477 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4478 {
4479 /*
4480 * With APIC-register virtualization, a read access to any of the
4481 * following registers are virtualized. Accessing any other register
4482 * causes a VM-exit.
4483 */
4484 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4485 switch (offAlignedAccess)
4486 {
4487 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4488 case XAPIC_OFF_ID:
4489 case XAPIC_OFF_VERSION:
4490 case XAPIC_OFF_TPR:
4491 case XAPIC_OFF_EOI:
4492 case XAPIC_OFF_LDR:
4493 case XAPIC_OFF_DFR:
4494 case XAPIC_OFF_SVR:
4495 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4496 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4497 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4498 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4499 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4500 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4501 case XAPIC_OFF_ESR:
4502 case XAPIC_OFF_ICR_LO:
4503 case XAPIC_OFF_ICR_HI:
4504 case XAPIC_OFF_LVT_TIMER:
4505 case XAPIC_OFF_LVT_THERMAL:
4506 case XAPIC_OFF_LVT_PERF:
4507 case XAPIC_OFF_LVT_LINT0:
4508 case XAPIC_OFF_LVT_LINT1:
4509 case XAPIC_OFF_LVT_ERROR:
4510 case XAPIC_OFF_TIMER_ICR:
4511 case XAPIC_OFF_TIMER_DCR:
4512 break;
4513 default:
4514 return true;
4515 }
4516 }
4517 else
4518 {
4519 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4520 if (offAccess == XAPIC_OFF_TPR)
4521 { /* likely */ }
4522 else
4523 return true;
4524 }
4525 }
4526
4527 /* The APIC-access is virtualized, does not cause a VM-exit. */
4528 return false;
4529}
4530
4531
4532/**
4533 * Virtualizes a memory-based APIC-access where the address is not used to access
4534 * memory.
4535 *
4536 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4537 * page-faults but do not use the address to access memory.
4538 *
4539 * @param pVCpu The cross context virtual CPU structure.
4540 * @param pGCPhysAccess Pointer to the guest-physical address used.
4541 */
4542IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4543{
4544 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4545 Assert(pVmcs);
4546 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4547 Assert(pGCPhysAccess);
4548
4549 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4550 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4551 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4552
4553 if (GCPhysAccess == GCPhysApic)
4554 {
4555 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4556 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4557 uint16_t const cbAccess = 1;
4558 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4559 if (fIntercept)
4560 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4561
4562 *pGCPhysAccess = GCPhysApic | offAccess;
4563 return VINF_VMX_MODIFIES_BEHAVIOR;
4564 }
4565
4566 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4567}
4568
4569
4570/**
4571 * Virtualizes a memory-based APIC-access.
4572 *
4573 * @returns VBox strict status code.
4574 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4575 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4576 *
4577 * @param pVCpu The cross context virtual CPU structure.
4578 * @param offAccess The offset of the register being accessed (within the
4579 * APIC-access page).
4580 * @param cbAccess The size of the access in bytes.
4581 * @param pvData Pointer to the data being written or where to store the data
4582 * being read.
4583 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4584 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4585 */
4586IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4587 uint32_t fAccess)
4588{
4589 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4590 Assert(pVmcs);
4591 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4592 Assert(pvData);
4593 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4594 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4595 || (fAccess & IEM_ACCESS_INSTRUCTION));
4596
4597 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4598 if (fIntercept)
4599 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4600
4601 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4602 {
4603 /*
4604 * A write access to the APIC-access page that is virtualized (rather than
4605 * causing a VM-exit) writes data to the virtual-APIC page.
4606 */
4607 uint32_t const u32Data = *(uint32_t *)pvData;
4608 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4609
4610 /*
4611 * Record the currently updated APIC offset, as we need this later for figuring
4612 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4613 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4614 *
4615 * After completion of the current operation, we need to perform TPR virtualization,
4616 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4617 *
4618 * The current operation may be a REP-prefixed string instruction, execution of any
4619 * other instruction, or delivery of an event through the IDT.
4620 *
4621 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4622 * performed now but later after completion of the current operation.
4623 *
4624 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4625 */
4626 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4627 }
4628 else
4629 {
4630 /*
4631 * A read access from the APIC-access page that is virtualized (rather than
4632 * causing a VM-exit) returns data from the virtual-APIC page.
4633 *
4634 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4635 */
4636 Assert(cbAccess <= 4);
4637 Assert(offAccess < XAPIC_OFF_END + 4);
4638 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4639
4640 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4641 u32Data &= s_auAccessSizeMasks[cbAccess];
4642 *(uint32_t *)pvData = u32Data;
4643 }
4644
4645 return VINF_VMX_MODIFIES_BEHAVIOR;
4646}
4647
4648
4649/**
4650 * Virtualizes an MSR-based APIC read access.
4651 *
4652 * @returns VBox strict status code.
4653 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4654 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4655 * handled by the x2APIC device.
4656 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4657 * not within the range of valid MSRs, caller must raise \#GP(0).
4658 * @param pVCpu The cross context virtual CPU structure.
4659 * @param idMsr The x2APIC MSR being read.
4660 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4661 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4662 */
4663IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4664{
4665 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4666 Assert(pVmcs);
4667 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4668 Assert(pu64Value);
4669
4670 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4671 {
4672 /*
4673 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4674 * what the end of the valid x2APIC MSR range is. Hence the use of different
4675 * macros here.
4676 *
4677 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4678 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4679 */
4680 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4681 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4682 {
4683 uint16_t const offReg = (idMsr & 0xff) << 4;
4684 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4685 *pu64Value = u64Value;
4686 return VINF_VMX_MODIFIES_BEHAVIOR;
4687 }
4688 return VERR_OUT_OF_RANGE;
4689 }
4690
4691 if (idMsr == MSR_IA32_X2APIC_TPR)
4692 {
4693 uint16_t const offReg = (idMsr & 0xff) << 4;
4694 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4695 *pu64Value = u64Value;
4696 return VINF_VMX_MODIFIES_BEHAVIOR;
4697 }
4698
4699 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4700}
4701
4702
4703/**
4704 * Virtualizes an MSR-based APIC write access.
4705 *
4706 * @returns VBox strict status code.
4707 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4708 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4709 * not within the range of valid MSRs, caller must raise \#GP(0).
4710 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4711 *
4712 * @param pVCpu The cross context virtual CPU structure.
4713 * @param idMsr The x2APIC MSR being written.
4714 * @param u64Value The value of the x2APIC MSR being written.
4715 */
4716IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4717{
4718 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4719 Assert(pVmcs);
4720
4721 /*
4722 * Check if the access is to be virtualized.
4723 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4724 */
4725 if ( idMsr == MSR_IA32_X2APIC_TPR
4726 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4727 && ( idMsr == MSR_IA32_X2APIC_EOI
4728 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4729 {
4730 /* Validate the MSR write depending on the register. */
4731 switch (idMsr)
4732 {
4733 case MSR_IA32_X2APIC_TPR:
4734 case MSR_IA32_X2APIC_SELF_IPI:
4735 {
4736 if (u64Value & UINT64_C(0xffffffffffffff00))
4737 return VERR_OUT_OF_RANGE;
4738 break;
4739 }
4740 case MSR_IA32_X2APIC_EOI:
4741 {
4742 if (u64Value != 0)
4743 return VERR_OUT_OF_RANGE;
4744 break;
4745 }
4746 }
4747
4748 /* Write the MSR to the virtual-APIC page. */
4749 uint16_t const offReg = (idMsr & 0xff) << 4;
4750 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4751
4752 /*
4753 * Record the currently updated APIC offset, as we need this later for figuring
4754 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4755 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4756 */
4757 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4758
4759 return VINF_VMX_MODIFIES_BEHAVIOR;
4760 }
4761
4762 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4763}
4764
4765
4766/**
4767 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4768 *
4769 * @returns VBox status code.
4770 * @retval VINF_SUCCES when the highest set bit is found.
4771 * @retval VERR_NOT_FOUND when no bit is set.
4772 *
4773 * @param pVCpu The cross context virtual CPU structure.
4774 * @param offReg The offset of the APIC 256-bit sparse register.
4775 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4776 * set in the register. Only valid when VINF_SUCCESS is
4777 * returned.
4778 *
4779 * @remarks The format of the 256-bit sparse register here mirrors that found in
4780 * real APIC hardware.
4781 */
4782static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4783{
4784 Assert(offReg < XAPIC_OFF_END + 4);
4785 Assert(pidxHighestBit);
4786 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4787
4788 /*
4789 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4790 * However, in each fragment only the first 4 bytes are used.
4791 */
4792 uint8_t const cFrags = 8;
4793 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4794 {
4795 uint16_t const offFrag = iFrag * 16;
4796 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4797 if (!u32Frag)
4798 continue;
4799
4800 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4801 Assert(idxHighestBit > 0);
4802 --idxHighestBit;
4803 Assert(idxHighestBit <= UINT8_MAX);
4804 *pidxHighestBit = idxHighestBit;
4805 return VINF_SUCCESS;
4806 }
4807 return VERR_NOT_FOUND;
4808}
4809
4810
4811/**
4812 * Evaluates pending virtual interrupts.
4813 *
4814 * @param pVCpu The cross context virtual CPU structure.
4815 */
4816IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4817{
4818 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4819 Assert(pVmcs);
4820 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4821
4822 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4823 {
4824 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4825 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4826
4827 if ((uRvi >> 4) > (uPpr >> 4))
4828 {
4829 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4830 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4831 }
4832 else
4833 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4834 }
4835}
4836
4837
4838/**
4839 * Performs PPR virtualization.
4840 *
4841 * @returns VBox strict status code.
4842 * @param pVCpu The cross context virtual CPU structure.
4843 */
4844IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4845{
4846 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4847 Assert(pVmcs);
4848 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4849 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4850
4851 /*
4852 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4853 * or EOI-virtualization.
4854 *
4855 * See Intel spec. 29.1.3 "PPR Virtualization".
4856 */
4857 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4858 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4859
4860 uint32_t uPpr;
4861 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4862 uPpr = uTpr & 0xff;
4863 else
4864 uPpr = uSvi & 0xf0;
4865
4866 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4867 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4868}
4869
4870
4871/**
4872 * Performs VMX TPR virtualization.
4873 *
4874 * @returns VBox strict status code.
4875 * @param pVCpu The cross context virtual CPU structure.
4876 */
4877IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4878{
4879 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4880 Assert(pVmcs);
4881 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4882
4883 /*
4884 * We should have already performed the virtual-APIC write to the TPR offset
4885 * in the virtual-APIC page. We now perform TPR virtualization.
4886 *
4887 * See Intel spec. 29.1.2 "TPR Virtualization".
4888 */
4889 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4890 {
4891 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4892 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4893
4894 /*
4895 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4896 * See Intel spec. 29.1.2 "TPR Virtualization".
4897 */
4898 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4899 {
4900 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4901 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4902 }
4903 }
4904 else
4905 {
4906 iemVmxPprVirtualization(pVCpu);
4907 iemVmxEvalPendingVirtIntrs(pVCpu);
4908 }
4909
4910 return VINF_SUCCESS;
4911}
4912
4913
4914/**
4915 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4916 * not.
4917 *
4918 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4919 * @param pVCpu The cross context virtual CPU structure.
4920 * @param uVector The interrupt that was acknowledged using an EOI.
4921 */
4922IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4923{
4924 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4925 Assert(pVmcs);
4926 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4927
4928 if (uVector < 64)
4929 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4930 if (uVector < 128)
4931 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4932 if (uVector < 192)
4933 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4934 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4935}
4936
4937
4938/**
4939 * Performs EOI virtualization.
4940 *
4941 * @returns VBox strict status code.
4942 * @param pVCpu The cross context virtual CPU structure.
4943 */
4944IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4945{
4946 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4947 Assert(pVmcs);
4948 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4949
4950 /*
4951 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4952 * and get the next guest-interrupt that's in-service (if any).
4953 *
4954 * See Intel spec. 29.1.4 "EOI Virtualization".
4955 */
4956 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4957 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4958 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4959
4960 uint8_t uVector = uSvi;
4961 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4962
4963 uVector = 0;
4964 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4965
4966 if (uVector)
4967 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4968 else
4969 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4970
4971 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4972 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4973
4974 iemVmxPprVirtualization(pVCpu);
4975 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4976 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4977 iemVmxEvalPendingVirtIntrs(pVCpu);
4978 return VINF_SUCCESS;
4979}
4980
4981
4982/**
4983 * Performs self-IPI virtualization.
4984 *
4985 * @returns VBox strict status code.
4986 * @param pVCpu The cross context virtual CPU structure.
4987 */
4988IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4989{
4990 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4991 Assert(pVmcs);
4992 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4993
4994 /*
4995 * We should have already performed the virtual-APIC write to the self-IPI offset
4996 * in the virtual-APIC page. We now perform self-IPI virtualization.
4997 *
4998 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4999 */
5000 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5001 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5002 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5003 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5004 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5005 if (uVector > uRvi)
5006 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5007 iemVmxEvalPendingVirtIntrs(pVCpu);
5008 return VINF_SUCCESS;
5009}
5010
5011
5012/**
5013 * Performs VMX APIC-write emulation.
5014 *
5015 * @returns VBox strict status code.
5016 * @param pVCpu The cross context virtual CPU structure.
5017 */
5018IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5019{
5020 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5021 Assert(pVmcs);
5022
5023 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5024 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5025
5026 /*
5027 * Perform APIC-write emulation based on the virtual-APIC register written.
5028 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5029 */
5030 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5031 VBOXSTRICTRC rcStrict;
5032 switch (offApicWrite)
5033 {
5034 case XAPIC_OFF_TPR:
5035 {
5036 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5037 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5038 uTpr &= UINT32_C(0x000000ff);
5039 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5040 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5041 rcStrict = iemVmxTprVirtualization(pVCpu);
5042 break;
5043 }
5044
5045 case XAPIC_OFF_EOI:
5046 {
5047 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5048 {
5049 /* Clear VEOI and perform EOI virtualization. */
5050 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5051 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5052 rcStrict = iemVmxEoiVirtualization(pVCpu);
5053 }
5054 else
5055 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5056 break;
5057 }
5058
5059 case XAPIC_OFF_ICR_LO:
5060 {
5061 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5062 {
5063 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5064 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5065 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5066 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5067 if ( !(uIcrLo & fIcrLoMb0)
5068 && (uIcrLo & fIcrLoMb1))
5069 {
5070 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5071 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5072 }
5073 else
5074 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5075 }
5076 else
5077 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5078 break;
5079 }
5080
5081 case XAPIC_OFF_ICR_HI:
5082 {
5083 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5084 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5085 uIcrHi &= UINT32_C(0xff000000);
5086 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5087 rcStrict = VINF_SUCCESS;
5088 break;
5089 }
5090
5091 default:
5092 {
5093 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5094 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5095 break;
5096 }
5097 }
5098
5099 return rcStrict;
5100}
5101
5102
5103/**
5104 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5105 *
5106 * @param pVCpu The cross context virtual CPU structure.
5107 * @param pszInstr The VMX instruction name (for logging purposes).
5108 */
5109IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5110{
5111 /*
5112 * Guest Control Registers, Debug Registers, and MSRs.
5113 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5114 */
5115 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5116 const char *const pszFailure = "VM-exit";
5117 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5118
5119 /* CR0 reserved bits. */
5120 {
5121 /* CR0 MB1 bits. */
5122 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5123 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5124 if (fUnrestrictedGuest)
5125 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5126 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5127 { /* likely */ }
5128 else
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5130
5131 /* CR0 MBZ bits. */
5132 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5133 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5134 { /* likely */ }
5135 else
5136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5137
5138 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5139 if ( !fUnrestrictedGuest
5140 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5141 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5143 }
5144
5145 /* CR4 reserved bits. */
5146 {
5147 /* CR4 MB1 bits. */
5148 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5149 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5153
5154 /* CR4 MBZ bits. */
5155 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5156 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5157 { /* likely */ }
5158 else
5159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5160 }
5161
5162 /* DEBUGCTL MSR. */
5163 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5164 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5165 { /* likely */ }
5166 else
5167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5168
5169 /* 64-bit CPU checks. */
5170 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5171 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5172 {
5173 if (fGstInLongMode)
5174 {
5175 /* PAE must be set. */
5176 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5177 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5178 { /* likely */ }
5179 else
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5181 }
5182 else
5183 {
5184 /* PCIDE should not be set. */
5185 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5186 { /* likely */ }
5187 else
5188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5189 }
5190
5191 /* CR3. */
5192 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5196
5197 /* DR7. */
5198 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5199 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5203
5204 /* SYSENTER ESP and SYSENTER EIP. */
5205 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5206 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5207 { /* likely */ }
5208 else
5209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5210 }
5211
5212 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5213 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5214
5215 /* PAT MSR. */
5216 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5217 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5218 { /* likely */ }
5219 else
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5221
5222 /* EFER MSR. */
5223 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5224 {
5225 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5226 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5230
5231 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5232 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5233 if ( fGstLma == fGstInLongMode
5234 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5235 || fGstLma == fGstLme))
5236 { /* likely */ }
5237 else
5238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5239 }
5240
5241 /* We don't support IA32_BNDCFGS MSR yet. */
5242 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5243
5244 NOREF(pszInstr);
5245 NOREF(pszFailure);
5246 return VINF_SUCCESS;
5247}
5248
5249
5250/**
5251 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5252 *
5253 * @param pVCpu The cross context virtual CPU structure.
5254 * @param pszInstr The VMX instruction name (for logging purposes).
5255 */
5256IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5257{
5258 /*
5259 * Segment registers.
5260 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5261 */
5262 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5263 const char *const pszFailure = "VM-exit";
5264 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5265 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5266 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5267
5268 /* Selectors. */
5269 if ( !fGstInV86Mode
5270 && !fUnrestrictedGuest
5271 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5273
5274 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5275 {
5276 CPUMSELREG SelReg;
5277 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5278 if (RT_LIKELY(rc == VINF_SUCCESS))
5279 { /* likely */ }
5280 else
5281 return rc;
5282
5283 /*
5284 * Virtual-8086 mode checks.
5285 */
5286 if (fGstInV86Mode)
5287 {
5288 /* Base address. */
5289 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5290 { /* likely */ }
5291 else
5292 {
5293 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5295 }
5296
5297 /* Limit. */
5298 if (SelReg.u32Limit == 0xffff)
5299 { /* likely */ }
5300 else
5301 {
5302 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5304 }
5305
5306 /* Attribute. */
5307 if (SelReg.Attr.u == 0xf3)
5308 { /* likely */ }
5309 else
5310 {
5311 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5313 }
5314
5315 /* We're done; move to checking the next segment. */
5316 continue;
5317 }
5318
5319 /* Checks done by 64-bit CPUs. */
5320 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5321 {
5322 /* Base address. */
5323 if ( iSegReg == X86_SREG_FS
5324 || iSegReg == X86_SREG_GS)
5325 {
5326 if (X86_IS_CANONICAL(SelReg.u64Base))
5327 { /* likely */ }
5328 else
5329 {
5330 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5332 }
5333 }
5334 else if (iSegReg == X86_SREG_CS)
5335 {
5336 if (!RT_HI_U32(SelReg.u64Base))
5337 { /* likely */ }
5338 else
5339 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5340 }
5341 else
5342 {
5343 if ( SelReg.Attr.n.u1Unusable
5344 || !RT_HI_U32(SelReg.u64Base))
5345 { /* likely */ }
5346 else
5347 {
5348 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5350 }
5351 }
5352 }
5353
5354 /*
5355 * Checks outside Virtual-8086 mode.
5356 */
5357 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5358 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5359 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5360 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5361 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5362 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5363 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5364 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5365
5366 /* Code or usable segment. */
5367 if ( iSegReg == X86_SREG_CS
5368 || fUsable)
5369 {
5370 /* Reserved bits (bits 31:17 and bits 11:8). */
5371 if (!(SelReg.Attr.u & 0xfffe0f00))
5372 { /* likely */ }
5373 else
5374 {
5375 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5377 }
5378
5379 /* Descriptor type. */
5380 if (fCodeDataSeg)
5381 { /* likely */ }
5382 else
5383 {
5384 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5386 }
5387
5388 /* Present. */
5389 if (fPresent)
5390 { /* likely */ }
5391 else
5392 {
5393 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5395 }
5396
5397 /* Granularity. */
5398 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5399 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5400 { /* likely */ }
5401 else
5402 {
5403 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5405 }
5406 }
5407
5408 if (iSegReg == X86_SREG_CS)
5409 {
5410 /* Segment Type and DPL. */
5411 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5412 && fUnrestrictedGuest)
5413 {
5414 if (uDpl == 0)
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5418 }
5419 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5420 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5421 {
5422 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5423 if (uDpl == AttrSs.n.u2Dpl)
5424 { /* likely */ }
5425 else
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5427 }
5428 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5429 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5430 {
5431 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5432 if (uDpl <= AttrSs.n.u2Dpl)
5433 { /* likely */ }
5434 else
5435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5436 }
5437 else
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5439
5440 /* Def/Big. */
5441 if ( fGstInLongMode
5442 && fSegLong)
5443 {
5444 if (uDefBig == 0)
5445 { /* likely */ }
5446 else
5447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5448 }
5449 }
5450 else if (iSegReg == X86_SREG_SS)
5451 {
5452 /* Segment Type. */
5453 if ( !fUsable
5454 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5455 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5459
5460 /* DPL. */
5461 if (!fUnrestrictedGuest)
5462 {
5463 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5464 { /* likely */ }
5465 else
5466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5467 }
5468 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5469 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5470 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5471 {
5472 if (uDpl == 0)
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5476 }
5477 }
5478 else
5479 {
5480 /* DS, ES, FS, GS. */
5481 if (fUsable)
5482 {
5483 /* Segment type. */
5484 if (uSegType & X86_SEL_TYPE_ACCESSED)
5485 { /* likely */ }
5486 else
5487 {
5488 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5489 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5490 }
5491
5492 if ( !(uSegType & X86_SEL_TYPE_CODE)
5493 || (uSegType & X86_SEL_TYPE_READ))
5494 { /* likely */ }
5495 else
5496 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5497
5498 /* DPL. */
5499 if ( !fUnrestrictedGuest
5500 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5501 {
5502 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5503 { /* likely */ }
5504 else
5505 {
5506 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5508 }
5509 }
5510 }
5511 }
5512 }
5513
5514 /*
5515 * LDTR.
5516 */
5517 {
5518 CPUMSELREG Ldtr;
5519 Ldtr.Sel = pVmcs->GuestLdtr;
5520 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5521 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5522 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5523
5524 if (!Ldtr.Attr.n.u1Unusable)
5525 {
5526 /* Selector. */
5527 if (!(Ldtr.Sel & X86_SEL_LDT))
5528 { /* likely */ }
5529 else
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5531
5532 /* Base. */
5533 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5534 {
5535 if (X86_IS_CANONICAL(Ldtr.u64Base))
5536 { /* likely */ }
5537 else
5538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5539 }
5540
5541 /* Attributes. */
5542 /* Reserved bits (bits 31:17 and bits 11:8). */
5543 if (!(Ldtr.Attr.u & 0xfffe0f00))
5544 { /* likely */ }
5545 else
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5547
5548 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5549 { /* likely */ }
5550 else
5551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5552
5553 if (!Ldtr.Attr.n.u1DescType)
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5557
5558 if (Ldtr.Attr.n.u1Present)
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5562
5563 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5564 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5565 { /* likely */ }
5566 else
5567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5568 }
5569 }
5570
5571 /*
5572 * TR.
5573 */
5574 {
5575 CPUMSELREG Tr;
5576 Tr.Sel = pVmcs->GuestTr;
5577 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5578 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5579 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5580
5581 /* Selector. */
5582 if (!(Tr.Sel & X86_SEL_LDT))
5583 { /* likely */ }
5584 else
5585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5586
5587 /* Base. */
5588 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5589 {
5590 if (X86_IS_CANONICAL(Tr.u64Base))
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5594 }
5595
5596 /* Attributes. */
5597 /* Reserved bits (bits 31:17 and bits 11:8). */
5598 if (!(Tr.Attr.u & 0xfffe0f00))
5599 { /* likely */ }
5600 else
5601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5602
5603 if (!Tr.Attr.n.u1Unusable)
5604 { /* likely */ }
5605 else
5606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5607
5608 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5609 || ( !fGstInLongMode
5610 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5611 { /* likely */ }
5612 else
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5614
5615 if (!Tr.Attr.n.u1DescType)
5616 { /* likely */ }
5617 else
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5619
5620 if (Tr.Attr.n.u1Present)
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5624
5625 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5626 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5627 { /* likely */ }
5628 else
5629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5630 }
5631
5632 NOREF(pszInstr);
5633 NOREF(pszFailure);
5634 return VINF_SUCCESS;
5635}
5636
5637
5638/**
5639 * Checks guest GDTR and IDTR as part of VM-entry.
5640 *
5641 * @param pVCpu The cross context virtual CPU structure.
5642 * @param pszInstr The VMX instruction name (for logging purposes).
5643 */
5644IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5645{
5646 /*
5647 * GDTR and IDTR.
5648 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5649 */
5650 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5651 const char *const pszFailure = "VM-exit";
5652
5653 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5654 {
5655 /* Base. */
5656 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5657 { /* likely */ }
5658 else
5659 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5660
5661 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5662 { /* likely */ }
5663 else
5664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5665 }
5666
5667 /* Limit. */
5668 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5669 { /* likely */ }
5670 else
5671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5672
5673 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5674 { /* likely */ }
5675 else
5676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5677
5678 NOREF(pszInstr);
5679 NOREF(pszFailure);
5680 return VINF_SUCCESS;
5681}
5682
5683
5684/**
5685 * Checks guest RIP and RFLAGS as part of VM-entry.
5686 *
5687 * @param pVCpu The cross context virtual CPU structure.
5688 * @param pszInstr The VMX instruction name (for logging purposes).
5689 */
5690IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5691{
5692 /*
5693 * RIP and RFLAGS.
5694 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5695 */
5696 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5697 const char *const pszFailure = "VM-exit";
5698 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5699
5700 /* RIP. */
5701 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5702 {
5703 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5704 if ( !fGstInLongMode
5705 || !AttrCs.n.u1Long)
5706 {
5707 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5708 { /* likely */ }
5709 else
5710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5711 }
5712
5713 if ( fGstInLongMode
5714 && AttrCs.n.u1Long)
5715 {
5716 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5717 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5718 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5719 { /* likely */ }
5720 else
5721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5722 }
5723 }
5724
5725 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5726 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5727 : pVmcs->u64GuestRFlags.s.Lo;
5728 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5729 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5730 { /* likely */ }
5731 else
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5733
5734 if ( fGstInLongMode
5735 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5736 {
5737 if (!(uGuestRFlags & X86_EFL_VM))
5738 { /* likely */ }
5739 else
5740 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5741 }
5742
5743 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5744 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5745 {
5746 if (uGuestRFlags & X86_EFL_IF)
5747 { /* likely */ }
5748 else
5749 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5750 }
5751
5752 NOREF(pszInstr);
5753 NOREF(pszFailure);
5754 return VINF_SUCCESS;
5755}
5756
5757
5758/**
5759 * Checks guest non-register state as part of VM-entry.
5760 *
5761 * @param pVCpu The cross context virtual CPU structure.
5762 * @param pszInstr The VMX instruction name (for logging purposes).
5763 */
5764IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5765{
5766 /*
5767 * Guest non-register state.
5768 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5769 */
5770 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5771 const char *const pszFailure = "VM-exit";
5772
5773 /*
5774 * Activity state.
5775 */
5776 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5777 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5778 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5779 { /* likely */ }
5780 else
5781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5782
5783 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5784 if ( !AttrSs.n.u2Dpl
5785 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5789
5790 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5791 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5792 {
5793 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5794 { /* likely */ }
5795 else
5796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5797 }
5798
5799 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5800 {
5801 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5802 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5803 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5804 switch (pVmcs->u32GuestActivityState)
5805 {
5806 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5807 {
5808 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5809 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5810 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5811 && ( uVector == X86_XCPT_DB
5812 || uVector == X86_XCPT_MC))
5813 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5814 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5815 { /* likely */ }
5816 else
5817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5818 break;
5819 }
5820
5821 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5822 {
5823 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5824 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5825 && uVector == X86_XCPT_MC))
5826 { /* likely */ }
5827 else
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5829 break;
5830 }
5831
5832 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5833 default:
5834 break;
5835 }
5836 }
5837
5838 /*
5839 * Interruptibility state.
5840 */
5841 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5845
5846 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5847 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5851
5852 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5853 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5854 { /* likely */ }
5855 else
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5857
5858 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5859 {
5860 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5861 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5862 {
5863 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5867 }
5868 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5869 {
5870 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5871 { /* likely */ }
5872 else
5873 {
5874 /*
5875 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5876 * We update the VM-exit qualification only when blocking-by-STI is set
5877 * without blocking-by-MovSS being set. Although in practise it does not
5878 * make much difference since the order of checks are implementation defined.
5879 */
5880 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5881 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5883 }
5884
5885 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5886 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5887 { /* likely */ }
5888 else
5889 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5890 }
5891 }
5892
5893 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5894 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5895 { /* likely */ }
5896 else
5897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5898
5899 /* We don't support SGX yet. So enclave-interruption must not be set. */
5900 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5904
5905 /*
5906 * Pending debug exceptions.
5907 */
5908 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5909 ? pVmcs->u64GuestPendingDbgXcpt.u
5910 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5911 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5912 { /* likely */ }
5913 else
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5915
5916 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5917 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5918 {
5919 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5920 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5921 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5923
5924 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5925 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5926 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5928 }
5929
5930 /* We don't support RTM (Real-time Transactional Memory) yet. */
5931 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5932 { /* likely */ }
5933 else
5934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5935
5936 /*
5937 * VMCS link pointer.
5938 */
5939 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5940 {
5941 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5942 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5943 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5944 { /* likely */ }
5945 else
5946 {
5947 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5948 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5949 }
5950
5951 /* Validate the address. */
5952 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5953 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5954 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5955 { /* likely */ }
5956 else
5957 {
5958 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5959 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5960 }
5961
5962 /* Read the VMCS-link pointer from guest memory. */
5963 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5964 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5965 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5966 if (RT_SUCCESS(rc))
5967 { /* likely */ }
5968 else
5969 {
5970 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5972 }
5973
5974 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5975 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5976 { /* likely */ }
5977 else
5978 {
5979 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5980 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5981 }
5982
5983 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5984 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5985 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5986 { /* likely */ }
5987 else
5988 {
5989 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5990 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5991 }
5992
5993 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5994 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5995 }
5996
5997 NOREF(pszInstr);
5998 NOREF(pszFailure);
5999 return VINF_SUCCESS;
6000}
6001
6002
6003/**
6004 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6005 * VM-entry.
6006 *
6007 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6008 * @param pVCpu The cross context virtual CPU structure.
6009 * @param pszInstr The VMX instruction name (for logging purposes).
6010 * @param pVmcs Pointer to the virtual VMCS.
6011 */
6012IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6013{
6014 /*
6015 * Check PDPTEs.
6016 * See Intel spec. 4.4.1 "PDPTE Registers".
6017 */
6018 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6019 const char *const pszFailure = "VM-exit";
6020
6021 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6022 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6023 if (RT_SUCCESS(rc))
6024 {
6025 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6026 {
6027 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6028 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6029 { /* likely */ }
6030 else
6031 {
6032 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6033 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6035 }
6036 }
6037 }
6038 else
6039 {
6040 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6042 }
6043
6044 NOREF(pszFailure);
6045 NOREF(pszInstr);
6046 return rc;
6047}
6048
6049
6050/**
6051 * Checks guest PDPTEs as part of VM-entry.
6052 *
6053 * @param pVCpu The cross context virtual CPU structure.
6054 * @param pszInstr The VMX instruction name (for logging purposes).
6055 */
6056IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6057{
6058 /*
6059 * Guest PDPTEs.
6060 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6061 */
6062 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6063 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6064
6065 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6066 int rc;
6067 if ( !fGstInLongMode
6068 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6069 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6070 {
6071 /*
6072 * We don't support nested-paging for nested-guests yet.
6073 *
6074 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6075 * rather we need to check the PDPTEs referenced by the guest CR3.
6076 */
6077 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6078 }
6079 else
6080 rc = VINF_SUCCESS;
6081 return rc;
6082}
6083
6084
6085/**
6086 * Checks guest-state as part of VM-entry.
6087 *
6088 * @returns VBox status code.
6089 * @param pVCpu The cross context virtual CPU structure.
6090 * @param pszInstr The VMX instruction name (for logging purposes).
6091 */
6092IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6093{
6094 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6095 if (RT_SUCCESS(rc))
6096 {
6097 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6098 if (RT_SUCCESS(rc))
6099 {
6100 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6101 if (RT_SUCCESS(rc))
6102 {
6103 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6104 if (RT_SUCCESS(rc))
6105 {
6106 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6107 if (RT_SUCCESS(rc))
6108 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6109 }
6110 }
6111 }
6112 }
6113 return rc;
6114}
6115
6116
6117/**
6118 * Checks host-state as part of VM-entry.
6119 *
6120 * @returns VBox status code.
6121 * @param pVCpu The cross context virtual CPU structure.
6122 * @param pszInstr The VMX instruction name (for logging purposes).
6123 */
6124IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6125{
6126 /*
6127 * Host Control Registers and MSRs.
6128 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6129 */
6130 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6131 const char * const pszFailure = "VMFail";
6132
6133 /* CR0 reserved bits. */
6134 {
6135 /* CR0 MB1 bits. */
6136 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6137 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6138 { /* likely */ }
6139 else
6140 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6141
6142 /* CR0 MBZ bits. */
6143 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6144 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6148 }
6149
6150 /* CR4 reserved bits. */
6151 {
6152 /* CR4 MB1 bits. */
6153 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6154 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6158
6159 /* CR4 MBZ bits. */
6160 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6161 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6165 }
6166
6167 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6168 {
6169 /* CR3 reserved bits. */
6170 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6171 { /* likely */ }
6172 else
6173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6174
6175 /* SYSENTER ESP and SYSENTER EIP. */
6176 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6177 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6181 }
6182
6183 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6184 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6185
6186 /* PAT MSR. */
6187 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6188 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6189 { /* likely */ }
6190 else
6191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6192
6193 /* EFER MSR. */
6194 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6195 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6196 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6200
6201 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6202 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6203 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6204 if ( fHostInLongMode == fHostLma
6205 && fHostInLongMode == fHostLme)
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6209
6210 /*
6211 * Host Segment and Descriptor-Table Registers.
6212 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6213 */
6214 /* Selector RPL and TI. */
6215 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6216 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6217 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6218 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6219 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6220 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6221 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6225
6226 /* CS and TR selectors cannot be 0. */
6227 if ( pVmcs->HostCs
6228 && pVmcs->HostTr)
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6232
6233 /* SS cannot be 0 if 32-bit host. */
6234 if ( fHostInLongMode
6235 || pVmcs->HostSs)
6236 { /* likely */ }
6237 else
6238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6239
6240 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6241 {
6242 /* FS, GS, GDTR, IDTR, TR base address. */
6243 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6244 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6245 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6246 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6247 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6251 }
6252
6253 /*
6254 * Host address-space size for 64-bit CPUs.
6255 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6256 */
6257 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6258 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6259 {
6260 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6261
6262 /* Logical processor in IA-32e mode. */
6263 if (fCpuInLongMode)
6264 {
6265 if (fHostInLongMode)
6266 {
6267 /* PAE must be set. */
6268 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6269 { /* likely */ }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6272
6273 /* RIP must be canonical. */
6274 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6275 { /* likely */ }
6276 else
6277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6278 }
6279 else
6280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6281 }
6282 else
6283 {
6284 /* Logical processor is outside IA-32e mode. */
6285 if ( !fGstInLongMode
6286 && !fHostInLongMode)
6287 {
6288 /* PCIDE should not be set. */
6289 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6293
6294 /* The high 32-bits of RIP MBZ. */
6295 if (!pVmcs->u64HostRip.s.Hi)
6296 { /* likely */ }
6297 else
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6299 }
6300 else
6301 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6302 }
6303 }
6304 else
6305 {
6306 /* Host address-space size for 32-bit CPUs. */
6307 if ( !fGstInLongMode
6308 && !fHostInLongMode)
6309 { /* likely */ }
6310 else
6311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6312 }
6313
6314 NOREF(pszInstr);
6315 NOREF(pszFailure);
6316 return VINF_SUCCESS;
6317}
6318
6319
6320/**
6321 * Checks VM-entry controls fields as part of VM-entry.
6322 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6323 *
6324 * @returns VBox status code.
6325 * @param pVCpu The cross context virtual CPU structure.
6326 * @param pszInstr The VMX instruction name (for logging purposes).
6327 */
6328IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6329{
6330 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6331 const char * const pszFailure = "VMFail";
6332
6333 /* VM-entry controls. */
6334 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6335 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6336 { /* likely */ }
6337 else
6338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6339
6340 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6341 { /* likely */ }
6342 else
6343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6344
6345 /* Event injection. */
6346 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6347 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6348 {
6349 /* Type and vector. */
6350 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6351 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6352 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6353 if ( !uRsvd
6354 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6355 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6356 { /* likely */ }
6357 else
6358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6359
6360 /* Exception error code. */
6361 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6362 {
6363 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6364 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6365 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6366 { /* likely */ }
6367 else
6368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6369
6370 /* Exceptions that provide an error code. */
6371 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6372 && ( uVector == X86_XCPT_DF
6373 || uVector == X86_XCPT_TS
6374 || uVector == X86_XCPT_NP
6375 || uVector == X86_XCPT_SS
6376 || uVector == X86_XCPT_GP
6377 || uVector == X86_XCPT_PF
6378 || uVector == X86_XCPT_AC))
6379 { /* likely */ }
6380 else
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6382
6383 /* Exception error-code reserved bits. */
6384 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6385 { /* likely */ }
6386 else
6387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6388
6389 /* Injecting a software interrupt, software exception or privileged software exception. */
6390 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6391 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6392 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6393 {
6394 /* Instruction length must be in the range 0-15. */
6395 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6396 { /* likely */ }
6397 else
6398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6399
6400 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6401 if ( pVmcs->u32EntryInstrLen == 0
6402 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6404 }
6405 }
6406 }
6407
6408 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6409 if (pVmcs->u32EntryMsrLoadCount)
6410 {
6411 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6412 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6413 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6414 { /* likely */ }
6415 else
6416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6417 }
6418
6419 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6420 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6421
6422 NOREF(pszInstr);
6423 NOREF(pszFailure);
6424 return VINF_SUCCESS;
6425}
6426
6427
6428/**
6429 * Checks VM-exit controls fields as part of VM-entry.
6430 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6431 *
6432 * @returns VBox status code.
6433 * @param pVCpu The cross context virtual CPU structure.
6434 * @param pszInstr The VMX instruction name (for logging purposes).
6435 */
6436IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6437{
6438 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6439 const char * const pszFailure = "VMFail";
6440
6441 /* VM-exit controls. */
6442 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6443 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6444 { /* likely */ }
6445 else
6446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6447
6448 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6449 { /* likely */ }
6450 else
6451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6452
6453 /* Save preemption timer without activating it. */
6454 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6455 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6456 { /* likely */ }
6457 else
6458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6459
6460 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6461 if (pVmcs->u32ExitMsrStoreCount)
6462 {
6463 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6464 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6465 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6466 { /* likely */ }
6467 else
6468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6469 }
6470
6471 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6472 if (pVmcs->u32ExitMsrLoadCount)
6473 {
6474 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6475 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6476 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6477 { /* likely */ }
6478 else
6479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6480 }
6481
6482 NOREF(pszInstr);
6483 NOREF(pszFailure);
6484 return VINF_SUCCESS;
6485}
6486
6487
6488/**
6489 * Checks VM-execution controls fields as part of VM-entry.
6490 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6491 *
6492 * @returns VBox status code.
6493 * @param pVCpu The cross context virtual CPU structure.
6494 * @param pszInstr The VMX instruction name (for logging purposes).
6495 *
6496 * @remarks This may update secondary-processor based VM-execution control fields
6497 * in the current VMCS if necessary.
6498 */
6499IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6500{
6501 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6502 const char * const pszFailure = "VMFail";
6503
6504 /* Pin-based VM-execution controls. */
6505 {
6506 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6507 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6508 { /* likely */ }
6509 else
6510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6511
6512 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6513 { /* likely */ }
6514 else
6515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6516 }
6517
6518 /* Processor-based VM-execution controls. */
6519 {
6520 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6521 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6522 { /* likely */ }
6523 else
6524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6525
6526 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6527 { /* likely */ }
6528 else
6529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6530 }
6531
6532 /* Secondary processor-based VM-execution controls. */
6533 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6534 {
6535 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6536 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6537 { /* likely */ }
6538 else
6539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6540
6541 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6542 { /* likely */ }
6543 else
6544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6545 }
6546 else
6547 Assert(!pVmcs->u32ProcCtls2);
6548
6549 /* CR3-target count. */
6550 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6551 { /* likely */ }
6552 else
6553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6554
6555 /* I/O bitmaps physical addresses. */
6556 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6557 {
6558 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6559 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6560 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6561 { /* likely */ }
6562 else
6563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6564
6565 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6566 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6567 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6568 { /* likely */ }
6569 else
6570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6571 }
6572
6573 /* MSR bitmap physical address. */
6574 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6575 {
6576 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6577 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6578 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6579 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6580 { /* likely */ }
6581 else
6582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6583
6584 /* Read the MSR bitmap. */
6585 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6586 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6587 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6588 if (RT_SUCCESS(rc))
6589 { /* likely */ }
6590 else
6591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6592 }
6593
6594 /* TPR shadow related controls. */
6595 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6596 {
6597 /* Virtual-APIC page physical address. */
6598 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6599 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6600 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6601 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6602 { /* likely */ }
6603 else
6604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6605
6606 /* TPR threshold without virtual-interrupt delivery. */
6607 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6608 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6610
6611 /* TPR threshold and VTPR. */
6612 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6613 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6614 {
6615 /* Read the VTPR from the virtual-APIC page. */
6616 uint8_t u8VTpr;
6617 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6618 if (RT_SUCCESS(rc))
6619 { /* likely */ }
6620 else
6621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6622
6623 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6624 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6625 { /* likely */ }
6626 else
6627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6628 }
6629 }
6630 else
6631 {
6632 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6633 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6634 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6635 { /* likely */ }
6636 else
6637 {
6638 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6640 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6641 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6642 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6644 }
6645 }
6646
6647 /* NMI exiting and virtual-NMIs. */
6648 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6649 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6653
6654 /* Virtual-NMIs and NMI-window exiting. */
6655 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6656 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6657 { /* likely */ }
6658 else
6659 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6660
6661 /* Virtualize APIC accesses. */
6662 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6663 {
6664 /* APIC-access physical address. */
6665 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6666 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6667 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6668 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6669 { /* likely */ }
6670 else
6671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6672
6673 /*
6674 * Disallow APIC-access page and virtual-APIC page from being the same address.
6675 * Note! This is not an Intel requirement, but one imposed by our implementation.
6676 */
6677 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6678 * redirecting accesses between the APIC-access page and the virtual-APIC
6679 * page. If any nested hypervisor requires this, we can implement it later. */
6680 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6681 {
6682 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6683 if (GCPhysVirtApic != GCPhysApicAccess)
6684 { /* likely */ }
6685 else
6686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6687 }
6688
6689 /*
6690 * Register the handler for the APIC-access page.
6691 *
6692 * We don't deregister the APIC-access page handler during the VM-exit as a different
6693 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6694 *
6695 * We leave the page registered until the first access that happens outside VMX non-root
6696 * mode. Guest software is allowed to access structures such as the APIC-access page
6697 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6698 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6699 *
6700 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6701 */
6702 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6703 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6704 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6705 if (RT_SUCCESS(rc))
6706 { /* likely */ }
6707 else
6708 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6709 }
6710
6711 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6712 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6713 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6717
6718 /* Virtual-interrupt delivery requires external interrupt exiting. */
6719 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6720 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6721 { /* likely */ }
6722 else
6723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6724
6725 /* VPID. */
6726 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6727 || pVmcs->u16Vpid != 0)
6728 { /* likely */ }
6729 else
6730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6731
6732 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6733 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6734 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6735 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6736 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6737 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6738 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6739
6740 /* VMCS shadowing. */
6741 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6742 {
6743 /* VMREAD-bitmap physical address. */
6744 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6745 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6746 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6747 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6751
6752 /* VMWRITE-bitmap physical address. */
6753 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6754 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6755 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6756 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6757 { /* likely */ }
6758 else
6759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6760
6761 /* Read the VMREAD-bitmap. */
6762 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6763 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6764 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6765 if (RT_SUCCESS(rc))
6766 { /* likely */ }
6767 else
6768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6769
6770 /* Read the VMWRITE-bitmap. */
6771 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6772 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6773 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6774 if (RT_SUCCESS(rc))
6775 { /* likely */ }
6776 else
6777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6778 }
6779
6780 NOREF(pszInstr);
6781 NOREF(pszFailure);
6782 return VINF_SUCCESS;
6783}
6784
6785
6786/**
6787 * Loads the guest control registers, debug register and some MSRs as part of
6788 * VM-entry.
6789 *
6790 * @param pVCpu The cross context virtual CPU structure.
6791 */
6792IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6793{
6794 /*
6795 * Load guest control registers, debug registers and MSRs.
6796 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6797 */
6798 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6799
6800 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6801 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6802 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6803 CPUMSetGuestCR0(pVCpu, uGstCr0);
6804 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6805 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6806
6807 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6808 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6809
6810 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6811 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6812 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6813
6814 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6815 {
6816 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6817
6818 /* EFER MSR. */
6819 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6820 {
6821 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6822 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6823 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6824 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6825 if (fGstInLongMode)
6826 {
6827 /* If the nested-guest is in long mode, LMA and LME are both set. */
6828 Assert(fGstPaging);
6829 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6830 }
6831 else
6832 {
6833 /*
6834 * If the nested-guest is outside long mode:
6835 * - With paging: LMA is cleared, LME is cleared.
6836 * - Without paging: LMA is cleared, LME is left unmodified.
6837 */
6838 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6839 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6840 }
6841 }
6842 /* else: see below. */
6843 }
6844
6845 /* PAT MSR. */
6846 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6847 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6848
6849 /* EFER MSR. */
6850 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6851 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6852
6853 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6854 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6855
6856 /* We don't support IA32_BNDCFGS MSR yet. */
6857 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6858
6859 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6860}
6861
6862
6863/**
6864 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6865 *
6866 * @param pVCpu The cross context virtual CPU structure.
6867 */
6868IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6869{
6870 /*
6871 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6872 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6873 */
6874 /* CS, SS, ES, DS, FS, GS. */
6875 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6876 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6877 {
6878 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6879 CPUMSELREG VmcsSelReg;
6880 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6881 AssertRC(rc); NOREF(rc);
6882 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6883 {
6884 pGstSelReg->Sel = VmcsSelReg.Sel;
6885 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6886 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6887 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6888 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6889 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6890 }
6891 else
6892 {
6893 pGstSelReg->Sel = VmcsSelReg.Sel;
6894 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6895 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6896 switch (iSegReg)
6897 {
6898 case X86_SREG_CS:
6899 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6900 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6901 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6902 break;
6903
6904 case X86_SREG_SS:
6905 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6906 pGstSelReg->u32Limit = 0;
6907 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6908 break;
6909
6910 case X86_SREG_ES:
6911 case X86_SREG_DS:
6912 pGstSelReg->u64Base = 0;
6913 pGstSelReg->u32Limit = 0;
6914 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6915 break;
6916
6917 case X86_SREG_FS:
6918 case X86_SREG_GS:
6919 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6920 pGstSelReg->u32Limit = 0;
6921 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6922 break;
6923 }
6924 Assert(pGstSelReg->Attr.n.u1Unusable);
6925 }
6926 }
6927
6928 /* LDTR. */
6929 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6930 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6931 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6932 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6933 {
6934 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6935 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6936 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6937 }
6938 else
6939 {
6940 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6941 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6942 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6943 }
6944
6945 /* TR. */
6946 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6947 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6948 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6949 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6950 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6951 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6952 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6953
6954 /* GDTR. */
6955 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6956 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6957
6958 /* IDTR. */
6959 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6960 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6961}
6962
6963
6964/**
6965 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6966 *
6967 * @returns VBox status code.
6968 * @param pVCpu The cross context virtual CPU structure.
6969 * @param pszInstr The VMX instruction name (for logging purposes).
6970 */
6971IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6972{
6973 /*
6974 * Load guest MSRs.
6975 * See Intel spec. 26.4 "Loading MSRs".
6976 */
6977 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6978 const char *const pszFailure = "VM-exit";
6979
6980 /*
6981 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6982 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6983 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6984 */
6985 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6986 if (!cMsrs)
6987 return VINF_SUCCESS;
6988
6989 /*
6990 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6991 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6992 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6993 */
6994 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6995 if (fIsMsrCountValid)
6996 { /* likely */ }
6997 else
6998 {
6999 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7001 }
7002
7003 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7004 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7005 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7006 if (RT_SUCCESS(rc))
7007 {
7008 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7009 Assert(pMsr);
7010 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7011 {
7012 if ( !pMsr->u32Reserved
7013 && pMsr->u32Msr != MSR_K8_FS_BASE
7014 && pMsr->u32Msr != MSR_K8_GS_BASE
7015 && pMsr->u32Msr != MSR_K6_EFER
7016 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7017 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7018 {
7019 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7020 if (rcStrict == VINF_SUCCESS)
7021 continue;
7022
7023 /*
7024 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7025 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7026 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7027 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7028 * MSR in ring-0 if possible, or come up with a better, generic solution.
7029 */
7030 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7031 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7032 ? kVmxVDiag_Vmentry_MsrLoadRing3
7033 : kVmxVDiag_Vmentry_MsrLoad;
7034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7035 }
7036 else
7037 {
7038 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7040 }
7041 }
7042 }
7043 else
7044 {
7045 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7047 }
7048
7049 NOREF(pszInstr);
7050 NOREF(pszFailure);
7051 return VINF_SUCCESS;
7052}
7053
7054
7055/**
7056 * Loads the guest-state non-register state as part of VM-entry.
7057 *
7058 * @returns VBox status code.
7059 * @param pVCpu The cross context virtual CPU structure.
7060 *
7061 * @remarks This must be called only after loading the nested-guest register state
7062 * (especially nested-guest RIP).
7063 */
7064IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7065{
7066 /*
7067 * Load guest non-register state.
7068 * See Intel spec. 26.6 "Special Features of VM Entry"
7069 */
7070 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7071
7072 /*
7073 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7074 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7075 *
7076 * See Intel spec. 26.6.1 "Interruptibility State".
7077 */
7078 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7079 if ( !fEntryVectoring
7080 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7081 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7082 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7083 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7084
7085 /* NMI blocking. */
7086 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7087 {
7088 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7089 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7090 else
7091 {
7092 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7093 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7094 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7095 }
7096 }
7097 else
7098 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7099
7100 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7101
7102 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7103 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7104
7105 /* VPID is irrelevant. We don't support VPID yet. */
7106
7107 /* Clear address-range monitoring. */
7108 EMMonitorWaitClear(pVCpu);
7109}
7110
7111
7112/**
7113 * Loads the guest-state as part of VM-entry.
7114 *
7115 * @returns VBox status code.
7116 * @param pVCpu The cross context virtual CPU structure.
7117 * @param pszInstr The VMX instruction name (for logging purposes).
7118 *
7119 * @remarks This must be done after all the necessary steps prior to loading of
7120 * guest-state (e.g. checking various VMCS state).
7121 */
7122IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7123{
7124 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7125 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7126
7127 /*
7128 * Load guest RIP, RSP and RFLAGS.
7129 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7130 */
7131 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7132 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7133 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7134 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7135
7136 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7137 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7138 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7139
7140 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7141
7142 NOREF(pszInstr);
7143 return VINF_SUCCESS;
7144}
7145
7146
7147/**
7148 * Returns whether there are is a pending debug exception on VM-entry.
7149 *
7150 * @param pVCpu The cross context virtual CPU structure.
7151 * @param pszInstr The VMX instruction name (for logging purposes).
7152 */
7153IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7154{
7155 /*
7156 * Pending debug exceptions.
7157 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7158 */
7159 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7160 Assert(pVmcs);
7161
7162 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7163 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7164 if (fPendingDbgXcpt)
7165 {
7166 uint8_t uEntryIntInfoType;
7167 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7168 if (fEntryVectoring)
7169 {
7170 switch (uEntryIntInfoType)
7171 {
7172 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7173 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7174 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7175 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7176 fPendingDbgXcpt = false;
7177 break;
7178
7179 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7180 {
7181 /*
7182 * Whether the pending debug exception for software exceptions other than
7183 * #BP and #OF is delivered after injecting the exception or is discard
7184 * is CPU implementation specific. We will discard them (easier).
7185 */
7186 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7187 if ( uVector != X86_XCPT_BP
7188 && uVector != X86_XCPT_OF)
7189 fPendingDbgXcpt = false;
7190 RT_FALL_THRU();
7191 }
7192 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7193 {
7194 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7195 fPendingDbgXcpt = false;
7196 break;
7197 }
7198 }
7199 }
7200 else
7201 {
7202 /*
7203 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7204 * pending debug exception is held pending or is discarded is CPU implementation
7205 * specific. We will discard them (easier).
7206 */
7207 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7208 fPendingDbgXcpt = false;
7209
7210 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7211 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7212 fPendingDbgXcpt = false;
7213 }
7214 }
7215
7216 NOREF(pszInstr);
7217 return fPendingDbgXcpt;
7218}
7219
7220
7221/**
7222 * Set up the monitor-trap flag (MTF).
7223 *
7224 * @param pVCpu The cross context virtual CPU structure.
7225 * @param pszInstr The VMX instruction name (for logging purposes).
7226 */
7227IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7228{
7229 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7230 Assert(pVmcs);
7231 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7232 {
7233 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7234 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7235 }
7236 else
7237 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7238 NOREF(pszInstr);
7239}
7240
7241
7242/**
7243 * Set up the VMX-preemption timer.
7244 *
7245 * @param pVCpu The cross context virtual CPU structure.
7246 * @param pszInstr The VMX instruction name (for logging purposes).
7247 */
7248IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7249{
7250 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7251 Assert(pVmcs);
7252 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7253 {
7254 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7255 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7256 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7257
7258 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7259 }
7260 else
7261 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7262
7263 NOREF(pszInstr);
7264}
7265
7266
7267/**
7268 * Injects an event using TRPM given a VM-entry interruption info. and related
7269 * fields.
7270 *
7271 * @returns VBox status code.
7272 * @param pVCpu The cross context virtual CPU structure.
7273 * @param uEntryIntInfo The VM-entry interruption info.
7274 * @param uErrCode The error code associated with the event if any.
7275 * @param cbInstr The VM-entry instruction length (for software
7276 * interrupts and software exceptions). Pass 0
7277 * otherwise.
7278 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7279 */
7280IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7281 RTGCUINTPTR GCPtrFaultAddress)
7282{
7283 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7284
7285 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7286 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7287 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7288
7289 TRPMEVENT enmTrapType;
7290 switch (uType)
7291 {
7292 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7293 enmTrapType = TRPM_HARDWARE_INT;
7294 break;
7295
7296 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7297 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7298 enmTrapType = TRPM_TRAP;
7299 break;
7300
7301 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7302 enmTrapType = TRPM_SOFTWARE_INT;
7303 break;
7304
7305 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7306 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7307 enmTrapType = TRPM_SOFTWARE_INT;
7308 break;
7309
7310 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7311 Assert(uVector == X86_XCPT_DB);
7312 enmTrapType = TRPM_SOFTWARE_INT;
7313 break;
7314
7315 default:
7316 /* Shouldn't really happen. */
7317 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7318 break;
7319 }
7320
7321 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7322 AssertRCReturn(rc, rc);
7323
7324 if (fErrCodeValid)
7325 TRPMSetErrorCode(pVCpu, uErrCode);
7326
7327 if ( enmTrapType == TRPM_TRAP
7328 && uVector == X86_XCPT_PF)
7329 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7330 else if (enmTrapType == TRPM_SOFTWARE_INT)
7331 TRPMSetInstrLength(pVCpu, cbInstr);
7332
7333 return VINF_SUCCESS;
7334}
7335
7336
7337/**
7338 * Performs event injection (if any) as part of VM-entry.
7339 *
7340 * @param pVCpu The cross context virtual CPU structure.
7341 * @param pszInstr The VMX instruction name (for logging purposes).
7342 */
7343IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7344{
7345 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7346
7347 /*
7348 * Inject events.
7349 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7350 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7351 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7352 * the actually delivery of this event.
7353 *
7354 * See Intel spec. 26.5 "Event Injection".
7355 */
7356 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7357 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7358
7359 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7360 if (fEntryIntInfoValid)
7361 {
7362 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7363 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7364 {
7365 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7366 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7367 return VINF_SUCCESS;
7368 }
7369
7370 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7371 pVCpu->cpum.GstCtx.cr2);
7372 if (RT_SUCCESS(rc))
7373 {
7374 /*
7375 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7376 *
7377 * However, we do it here on VM-entry because while it continues to not be visible to
7378 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7379 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7380 * information field.
7381 *
7382 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7383 */
7384 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7385 }
7386 return rc;
7387 }
7388
7389 /*
7390 * Inject any pending guest debug exception.
7391 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7392 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7393 */
7394 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7395 if (fPendingDbgXcpt)
7396 {
7397 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7398 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7399 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7400 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7401 0 /* GCPtrFaultAddress */);
7402 }
7403
7404 NOREF(pszInstr);
7405 return VINF_SUCCESS;
7406}
7407
7408
7409/**
7410 * Initializes all read-only VMCS fields as part of VM-entry.
7411 *
7412 * @param pVCpu The cross context virtual CPU structure.
7413 */
7414IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7415{
7416 /*
7417 * Any VMCS field which we do not establish on every VM-exit but may potentially
7418 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7419 * specified to be undefined needs to be initialized here.
7420 *
7421 * Thus, it is especially important to clear the VM-exit qualification field
7422 * since it must be zero for VM-exits where it is not used. Similarly, the
7423 * VM-exit interruption information field's valid bit needs to be cleared for
7424 * the same reasons.
7425 */
7426 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7427 Assert(pVmcs);
7428
7429 /* 16-bit (none currently). */
7430 /* 32-bit. */
7431 pVmcs->u32RoVmInstrError = 0;
7432 pVmcs->u32RoExitReason = 0;
7433 pVmcs->u32RoExitIntInfo = 0;
7434 pVmcs->u32RoExitIntErrCode = 0;
7435 pVmcs->u32RoIdtVectoringInfo = 0;
7436 pVmcs->u32RoIdtVectoringErrCode = 0;
7437 pVmcs->u32RoExitInstrLen = 0;
7438 pVmcs->u32RoExitInstrInfo = 0;
7439
7440 /* 64-bit. */
7441 pVmcs->u64RoGuestPhysAddr.u = 0;
7442
7443 /* Natural-width. */
7444 pVmcs->u64RoExitQual.u = 0;
7445 pVmcs->u64RoIoRcx.u = 0;
7446 pVmcs->u64RoIoRsi.u = 0;
7447 pVmcs->u64RoIoRdi.u = 0;
7448 pVmcs->u64RoIoRip.u = 0;
7449 pVmcs->u64RoGuestLinearAddr.u = 0;
7450}
7451
7452
7453/**
7454 * VMLAUNCH/VMRESUME instruction execution worker.
7455 *
7456 * @returns Strict VBox status code.
7457 * @param pVCpu The cross context virtual CPU structure.
7458 * @param cbInstr The instruction length in bytes.
7459 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7460 * VMXINSTRID_VMRESUME).
7461 *
7462 * @remarks Common VMX instruction checks are already expected to by the caller,
7463 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7464 */
7465IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7466{
7467# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7468 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7469 return VINF_EM_RAW_EMULATE_INSTR;
7470# else
7471 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7472 || uInstrId == VMXINSTRID_VMRESUME);
7473 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7474
7475 /* Nested-guest intercept. */
7476 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7477 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7478
7479 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7480
7481 /*
7482 * Basic VM-entry checks.
7483 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7484 * The checks following that do not have to follow a specific order.
7485 *
7486 * See Intel spec. 26.1 "Basic VM-entry Checks".
7487 */
7488
7489 /* CPL. */
7490 if (pVCpu->iem.s.uCpl == 0)
7491 { /* likely */ }
7492 else
7493 {
7494 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7496 return iemRaiseGeneralProtectionFault0(pVCpu);
7497 }
7498
7499 /* Current VMCS valid. */
7500 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7501 { /* likely */ }
7502 else
7503 {
7504 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7505 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7506 iemVmxVmFailInvalid(pVCpu);
7507 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7508 return VINF_SUCCESS;
7509 }
7510
7511 /* Current VMCS is not a shadow VMCS. */
7512 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7513 { /* likely */ }
7514 else
7515 {
7516 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7518 iemVmxVmFailInvalid(pVCpu);
7519 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7520 return VINF_SUCCESS;
7521 }
7522
7523 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7524 * use block-by-STI here which is not quite correct. */
7525 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7526 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7527 { /* likely */ }
7528 else
7529 {
7530 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7531 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7532 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7533 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7534 return VINF_SUCCESS;
7535 }
7536
7537 if (uInstrId == VMXINSTRID_VMLAUNCH)
7538 {
7539 /* VMLAUNCH with non-clear VMCS. */
7540 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7541 { /* likely */ }
7542 else
7543 {
7544 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7545 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7546 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7547 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7548 return VINF_SUCCESS;
7549 }
7550 }
7551 else
7552 {
7553 /* VMRESUME with non-launched VMCS. */
7554 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7555 { /* likely */ }
7556 else
7557 {
7558 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7559 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7560 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7561 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7562 return VINF_SUCCESS;
7563 }
7564 }
7565
7566 /*
7567 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7568 * while entering VMX non-root mode. We do some of this while checking VM-execution
7569 * controls. The guest hypervisor should not make assumptions and cannot expect
7570 * predictable behavior if changes to these structures are made in guest memory while
7571 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7572 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7573 *
7574 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7575 */
7576 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7577 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7578 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7579 if (RT_SUCCESS(rc))
7580 {
7581 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7582 if (RT_SUCCESS(rc))
7583 {
7584 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7585 if (RT_SUCCESS(rc))
7586 {
7587 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7588 if (RT_SUCCESS(rc))
7589 {
7590 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7591 iemVmxVmentryInitReadOnlyFields(pVCpu);
7592
7593 /*
7594 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7595 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7596 * VM-exit when required.
7597 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7598 */
7599 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7600
7601 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7602 if (RT_SUCCESS(rc))
7603 {
7604 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7605 if (RT_SUCCESS(rc))
7606 {
7607 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7608 if (RT_SUCCESS(rc))
7609 {
7610 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7611
7612 /* VMLAUNCH instruction must update the VMCS launch state. */
7613 if (uInstrId == VMXINSTRID_VMLAUNCH)
7614 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7615
7616 /* Perform the VMX transition (PGM updates). */
7617 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7618 if (rcStrict == VINF_SUCCESS)
7619 { /* likely */ }
7620 else if (RT_SUCCESS(rcStrict))
7621 {
7622 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7623 VBOXSTRICTRC_VAL(rcStrict)));
7624 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7625 }
7626 else
7627 {
7628 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7629 return rcStrict;
7630 }
7631
7632 /* We've now entered nested-guest execution. */
7633 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7634
7635 /*
7636 * The priority of potential VM-exits during VM-entry is important.
7637 * The priorities of VM-exits and events are listed from highest
7638 * to lowest as follows:
7639 *
7640 * 1. Event injection.
7641 * 2. Trap on task-switch (T flag set in TSS).
7642 * 3. TPR below threshold / APIC-write.
7643 * 4. SMI, INIT.
7644 * 5. MTF exit.
7645 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7646 * 7. VMX-preemption timer.
7647 * 9. NMI-window exit.
7648 * 10. NMI injection.
7649 * 11. Interrupt-window exit.
7650 * 12. Virtual-interrupt injection.
7651 * 13. Interrupt injection.
7652 * 14. Process next instruction (fetch, decode, execute).
7653 */
7654
7655 /* Setup the VMX-preemption timer. */
7656 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7657
7658 /* Setup monitor-trap flag. */
7659 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7660
7661 /* Now that we've switched page tables, we can go ahead and inject any event. */
7662 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7663 if (RT_SUCCESS(rcStrict))
7664 {
7665 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7666# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7667 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7668 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7669 if (rcSched != VINF_SUCCESS)
7670 iemSetPassUpStatus(pVCpu, rcSched);
7671# endif
7672 return VINF_SUCCESS;
7673 }
7674
7675 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7676 return rcStrict;
7677 }
7678 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7679 }
7680 }
7681 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7682 }
7683
7684 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7685 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7686 return VINF_SUCCESS;
7687 }
7688 }
7689 }
7690
7691 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7692 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7693 return VINF_SUCCESS;
7694# endif
7695}
7696
7697
7698/**
7699 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7700 * (causes a VM-exit) or not.
7701 *
7702 * @returns @c true if the instruction is intercepted, @c false otherwise.
7703 * @param pVCpu The cross context virtual CPU structure.
7704 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7705 * VMX_EXIT_WRMSR).
7706 * @param idMsr The MSR.
7707 */
7708IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7709{
7710 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7711 Assert( uExitReason == VMX_EXIT_RDMSR
7712 || uExitReason == VMX_EXIT_WRMSR);
7713
7714 /* Consult the MSR bitmap if the feature is supported. */
7715 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7716 Assert(pVmcs);
7717 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7718 {
7719 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7720 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7721 if (uExitReason == VMX_EXIT_RDMSR)
7722 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7723 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7724 }
7725
7726 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7727 return true;
7728}
7729
7730
7731/**
7732 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7733 * intercepted (causes a VM-exit) or not.
7734 *
7735 * @returns @c true if the instruction is intercepted, @c false otherwise.
7736 * @param pVCpu The cross context virtual CPU structure.
7737 * @param u64FieldEnc The VMCS field encoding.
7738 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7739 * VMX_EXIT_VMREAD).
7740 */
7741IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7742{
7743 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7744 Assert( uExitReason == VMX_EXIT_VMREAD
7745 || uExitReason == VMX_EXIT_VMWRITE);
7746
7747 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7748 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7749 return true;
7750
7751 /*
7752 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7753 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7754 */
7755 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7756 return true;
7757
7758 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7759 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7760 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7761 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7762 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7763 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7764 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7765 pbBitmap += (u32FieldEnc >> 3);
7766 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7767 return true;
7768
7769 return false;
7770}
7771
7772
7773/**
7774 * VMREAD common (memory/register) instruction execution worker
7775 *
7776 * @returns Strict VBox status code.
7777 * @param pVCpu The cross context virtual CPU structure.
7778 * @param cbInstr The instruction length in bytes.
7779 * @param pu64Dst Where to write the VMCS value (only updated when
7780 * VINF_SUCCESS is returned).
7781 * @param u64FieldEnc The VMCS field encoding.
7782 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7783 * be NULL.
7784 */
7785IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7786 PCVMXVEXITINFO pExitInfo)
7787{
7788 /* Nested-guest intercept. */
7789 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7790 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7791 {
7792 if (pExitInfo)
7793 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7794 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7795 }
7796
7797 /* CPL. */
7798 if (pVCpu->iem.s.uCpl == 0)
7799 { /* likely */ }
7800 else
7801 {
7802 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7803 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7804 return iemRaiseGeneralProtectionFault0(pVCpu);
7805 }
7806
7807 /* VMCS pointer in root mode. */
7808 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7809 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7810 { /* likely */ }
7811 else
7812 {
7813 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7814 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7815 iemVmxVmFailInvalid(pVCpu);
7816 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7817 return VINF_SUCCESS;
7818 }
7819
7820 /* VMCS-link pointer in non-root mode. */
7821 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7822 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7823 { /* likely */ }
7824 else
7825 {
7826 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7828 iemVmxVmFailInvalid(pVCpu);
7829 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7830 return VINF_SUCCESS;
7831 }
7832
7833 /* Supported VMCS field. */
7834 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7835 { /* likely */ }
7836 else
7837 {
7838 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7839 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7840 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7841 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7842 return VINF_SUCCESS;
7843 }
7844
7845 /*
7846 * Setup reading from the current or shadow VMCS.
7847 */
7848 uint8_t *pbVmcs;
7849 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7850 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7851 else
7852 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7853 Assert(pbVmcs);
7854
7855 VMXVMCSFIELDENC FieldEnc;
7856 FieldEnc.u = u64FieldEnc;
7857 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7858 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7859 uint8_t const uWidthType = (uWidth << 2) | uType;
7860 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7861 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7862 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7863 Assert(offField < VMX_V_VMCS_SIZE);
7864
7865 /*
7866 * Read the VMCS component based on the field's effective width.
7867 *
7868 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7869 * indicates high bits (little endian).
7870 *
7871 * Note! The caller is responsible to trim the result and update registers
7872 * or memory locations are required. Here we just zero-extend to the largest
7873 * type (i.e. 64-bits).
7874 */
7875 uint8_t *pbField = pbVmcs + offField;
7876 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7877 switch (uEffWidth)
7878 {
7879 case VMX_VMCS_ENC_WIDTH_64BIT:
7880 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7881 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7882 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7883 }
7884 return VINF_SUCCESS;
7885}
7886
7887
7888/**
7889 * VMREAD (64-bit register) instruction execution worker.
7890 *
7891 * @returns Strict VBox status code.
7892 * @param pVCpu The cross context virtual CPU structure.
7893 * @param cbInstr The instruction length in bytes.
7894 * @param pu64Dst Where to store the VMCS field's value.
7895 * @param u64FieldEnc The VMCS field encoding.
7896 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7897 * be NULL.
7898 */
7899IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7900 PCVMXVEXITINFO pExitInfo)
7901{
7902 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7903 if (rcStrict == VINF_SUCCESS)
7904 {
7905 iemVmxVmreadSuccess(pVCpu, cbInstr);
7906 return VINF_SUCCESS;
7907 }
7908
7909 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7910 return rcStrict;
7911}
7912
7913
7914/**
7915 * VMREAD (32-bit register) instruction execution worker.
7916 *
7917 * @returns Strict VBox status code.
7918 * @param pVCpu The cross context virtual CPU structure.
7919 * @param cbInstr The instruction length in bytes.
7920 * @param pu32Dst Where to store the VMCS field's value.
7921 * @param u32FieldEnc The VMCS field encoding.
7922 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7923 * be NULL.
7924 */
7925IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7926 PCVMXVEXITINFO pExitInfo)
7927{
7928 uint64_t u64Dst;
7929 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7930 if (rcStrict == VINF_SUCCESS)
7931 {
7932 *pu32Dst = u64Dst;
7933 iemVmxVmreadSuccess(pVCpu, cbInstr);
7934 return VINF_SUCCESS;
7935 }
7936
7937 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7938 return rcStrict;
7939}
7940
7941
7942/**
7943 * VMREAD (memory) instruction execution worker.
7944 *
7945 * @returns Strict VBox status code.
7946 * @param pVCpu The cross context virtual CPU structure.
7947 * @param cbInstr The instruction length in bytes.
7948 * @param iEffSeg The effective segment register to use with @a u64Val.
7949 * Pass UINT8_MAX if it is a register access.
7950 * @param enmEffAddrMode The effective addressing mode (only used with memory
7951 * operand).
7952 * @param GCPtrDst The guest linear address to store the VMCS field's
7953 * value.
7954 * @param u64FieldEnc The VMCS field encoding.
7955 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7956 * be NULL.
7957 */
7958IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7959 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7960{
7961 uint64_t u64Dst;
7962 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7963 if (rcStrict == VINF_SUCCESS)
7964 {
7965 /*
7966 * Write the VMCS field's value to the location specified in guest-memory.
7967 *
7968 * The pointer size depends on the address size (address-size prefix allowed).
7969 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7970 */
7971 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7972 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7973 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7974
7975 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7976 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7977 else
7978 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7979 if (rcStrict == VINF_SUCCESS)
7980 {
7981 iemVmxVmreadSuccess(pVCpu, cbInstr);
7982 return VINF_SUCCESS;
7983 }
7984
7985 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7986 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7987 return rcStrict;
7988 }
7989
7990 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7991 return rcStrict;
7992}
7993
7994
7995/**
7996 * VMWRITE instruction execution worker.
7997 *
7998 * @returns Strict VBox status code.
7999 * @param pVCpu The cross context virtual CPU structure.
8000 * @param cbInstr The instruction length in bytes.
8001 * @param iEffSeg The effective segment register to use with @a u64Val.
8002 * Pass UINT8_MAX if it is a register access.
8003 * @param enmEffAddrMode The effective addressing mode (only used with memory
8004 * operand).
8005 * @param u64Val The value to write (or guest linear address to the
8006 * value), @a iEffSeg will indicate if it's a memory
8007 * operand.
8008 * @param u64FieldEnc The VMCS field encoding.
8009 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8010 * be NULL.
8011 */
8012IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
8013 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
8014{
8015 /* Nested-guest intercept. */
8016 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8017 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8018 {
8019 if (pExitInfo)
8020 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8021 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8022 }
8023
8024 /* CPL. */
8025 if (pVCpu->iem.s.uCpl == 0)
8026 { /* likely */ }
8027 else
8028 {
8029 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8030 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8031 return iemRaiseGeneralProtectionFault0(pVCpu);
8032 }
8033
8034 /* VMCS pointer in root mode. */
8035 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8036 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8037 { /* likely */ }
8038 else
8039 {
8040 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8041 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8042 iemVmxVmFailInvalid(pVCpu);
8043 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8044 return VINF_SUCCESS;
8045 }
8046
8047 /* VMCS-link pointer in non-root mode. */
8048 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8049 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8050 { /* likely */ }
8051 else
8052 {
8053 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8054 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8055 iemVmxVmFailInvalid(pVCpu);
8056 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8057 return VINF_SUCCESS;
8058 }
8059
8060 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8061 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8062 if (!fIsRegOperand)
8063 {
8064 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8065 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8066 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8067
8068 /* Read the value from the specified guest memory location. */
8069 VBOXSTRICTRC rcStrict;
8070 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8071 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8072 else
8073 {
8074 uint32_t u32Val;
8075 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8076 u64Val = u32Val;
8077 }
8078 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8079 {
8080 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8081 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8082 return rcStrict;
8083 }
8084 }
8085 else
8086 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8087
8088 /* Supported VMCS field. */
8089 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8090 { /* likely */ }
8091 else
8092 {
8093 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8094 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8095 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8096 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8097 return VINF_SUCCESS;
8098 }
8099
8100 /* Read-only VMCS field. */
8101 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8102 if ( !fIsFieldReadOnly
8103 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8104 { /* likely */ }
8105 else
8106 {
8107 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8109 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8110 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8111 return VINF_SUCCESS;
8112 }
8113
8114 /*
8115 * Setup writing to the current or shadow VMCS.
8116 */
8117 uint8_t *pbVmcs;
8118 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8119 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8120 else
8121 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8122 Assert(pbVmcs);
8123
8124 VMXVMCSFIELDENC FieldEnc;
8125 FieldEnc.u = u64FieldEnc;
8126 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8127 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8128 uint8_t const uWidthType = (uWidth << 2) | uType;
8129 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8130 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8131 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8132 Assert(offField < VMX_V_VMCS_SIZE);
8133
8134 /*
8135 * Write the VMCS component based on the field's effective width.
8136 *
8137 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8138 * indicates high bits (little endian).
8139 */
8140 uint8_t *pbField = pbVmcs + offField;
8141 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8142 switch (uEffWidth)
8143 {
8144 case VMX_VMCS_ENC_WIDTH_64BIT:
8145 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8146 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8147 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8148 }
8149
8150 iemVmxVmSucceed(pVCpu);
8151 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8152 return VINF_SUCCESS;
8153}
8154
8155
8156/**
8157 * VMCLEAR instruction execution worker.
8158 *
8159 * @returns Strict VBox status code.
8160 * @param pVCpu The cross context virtual CPU structure.
8161 * @param cbInstr The instruction length in bytes.
8162 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8163 * @param GCPtrVmcs The linear address of the VMCS pointer.
8164 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8165 * be NULL.
8166 *
8167 * @remarks Common VMX instruction checks are already expected to by the caller,
8168 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8169 */
8170IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8171 PCVMXVEXITINFO pExitInfo)
8172{
8173 /* Nested-guest intercept. */
8174 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8175 {
8176 if (pExitInfo)
8177 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8178 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8179 }
8180
8181 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8182
8183 /* CPL. */
8184 if (pVCpu->iem.s.uCpl == 0)
8185 { /* likely */ }
8186 else
8187 {
8188 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8189 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8190 return iemRaiseGeneralProtectionFault0(pVCpu);
8191 }
8192
8193 /* Get the VMCS pointer from the location specified by the source memory operand. */
8194 RTGCPHYS GCPhysVmcs;
8195 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8196 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8197 { /* likely */ }
8198 else
8199 {
8200 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8201 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8202 return rcStrict;
8203 }
8204
8205 /* VMCS pointer alignment. */
8206 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8207 { /* likely */ }
8208 else
8209 {
8210 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8211 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8212 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8213 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8214 return VINF_SUCCESS;
8215 }
8216
8217 /* VMCS physical-address width limits. */
8218 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8219 { /* likely */ }
8220 else
8221 {
8222 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8223 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8224 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8225 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8226 return VINF_SUCCESS;
8227 }
8228
8229 /* VMCS is not the VMXON region. */
8230 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8231 { /* likely */ }
8232 else
8233 {
8234 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8235 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8236 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8237 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8238 return VINF_SUCCESS;
8239 }
8240
8241 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8242 restriction imposed by our implementation. */
8243 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8244 { /* likely */ }
8245 else
8246 {
8247 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8248 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8249 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8250 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8251 return VINF_SUCCESS;
8252 }
8253
8254 /*
8255 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8256 *
8257 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8258 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8259 * to 'clear'.
8260 */
8261 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8262 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8263 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8264 {
8265 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8266 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8267 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8268 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8269 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8270 }
8271 else
8272 {
8273 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8274 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8275 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8276 if (RT_FAILURE(rcStrict))
8277 return rcStrict;
8278 }
8279
8280 iemVmxVmSucceed(pVCpu);
8281 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8282 return VINF_SUCCESS;
8283}
8284
8285
8286/**
8287 * VMPTRST instruction execution worker.
8288 *
8289 * @returns Strict VBox status code.
8290 * @param pVCpu The cross context virtual CPU structure.
8291 * @param cbInstr The instruction length in bytes.
8292 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8293 * @param GCPtrVmcs The linear address of where to store the current VMCS
8294 * pointer.
8295 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8296 * be NULL.
8297 *
8298 * @remarks Common VMX instruction checks are already expected to by the caller,
8299 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8300 */
8301IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8302 PCVMXVEXITINFO pExitInfo)
8303{
8304 /* Nested-guest intercept. */
8305 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8306 {
8307 if (pExitInfo)
8308 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8309 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8310 }
8311
8312 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8313
8314 /* CPL. */
8315 if (pVCpu->iem.s.uCpl == 0)
8316 { /* likely */ }
8317 else
8318 {
8319 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8320 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8321 return iemRaiseGeneralProtectionFault0(pVCpu);
8322 }
8323
8324 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8325 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8326 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8327 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8328 {
8329 iemVmxVmSucceed(pVCpu);
8330 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8331 return rcStrict;
8332 }
8333
8334 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8335 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8336 return rcStrict;
8337}
8338
8339
8340/**
8341 * VMPTRLD instruction execution worker.
8342 *
8343 * @returns Strict VBox status code.
8344 * @param pVCpu The cross context virtual CPU structure.
8345 * @param cbInstr The instruction length in bytes.
8346 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8347 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8348 * be NULL.
8349 *
8350 * @remarks Common VMX instruction checks are already expected to by the caller,
8351 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8352 */
8353IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8354 PCVMXVEXITINFO pExitInfo)
8355{
8356 /* Nested-guest intercept. */
8357 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8358 {
8359 if (pExitInfo)
8360 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8361 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8362 }
8363
8364 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8365
8366 /* CPL. */
8367 if (pVCpu->iem.s.uCpl == 0)
8368 { /* likely */ }
8369 else
8370 {
8371 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8372 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8373 return iemRaiseGeneralProtectionFault0(pVCpu);
8374 }
8375
8376 /* Get the VMCS pointer from the location specified by the source memory operand. */
8377 RTGCPHYS GCPhysVmcs;
8378 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8379 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8380 { /* likely */ }
8381 else
8382 {
8383 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8384 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8385 return rcStrict;
8386 }
8387
8388 /* VMCS pointer alignment. */
8389 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8390 { /* likely */ }
8391 else
8392 {
8393 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8394 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8395 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8396 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8397 return VINF_SUCCESS;
8398 }
8399
8400 /* VMCS physical-address width limits. */
8401 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8402 { /* likely */ }
8403 else
8404 {
8405 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8406 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8407 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8408 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8409 return VINF_SUCCESS;
8410 }
8411
8412 /* VMCS is not the VMXON region. */
8413 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8414 { /* likely */ }
8415 else
8416 {
8417 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8419 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8420 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8421 return VINF_SUCCESS;
8422 }
8423
8424 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8425 restriction imposed by our implementation. */
8426 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8427 { /* likely */ }
8428 else
8429 {
8430 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8431 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8432 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8433 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8434 return VINF_SUCCESS;
8435 }
8436
8437 /* Read just the VMCS revision from the VMCS. */
8438 VMXVMCSREVID VmcsRevId;
8439 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8440 if (RT_SUCCESS(rc))
8441 { /* likely */ }
8442 else
8443 {
8444 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8445 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8446 return rc;
8447 }
8448
8449 /*
8450 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8451 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8452 */
8453 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8454 && ( !VmcsRevId.n.fIsShadowVmcs
8455 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8456 { /* likely */ }
8457 else
8458 {
8459 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8460 {
8461 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8462 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8464 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8465 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8466 return VINF_SUCCESS;
8467 }
8468
8469 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8470 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8471 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8472 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8473 return VINF_SUCCESS;
8474 }
8475
8476 /*
8477 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8478 * the cache of an existing, current VMCS back to guest memory before loading a new,
8479 * different current VMCS.
8480 */
8481 bool fLoadVmcsFromMem;
8482 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8483 {
8484 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8485 {
8486 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8487 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8488 fLoadVmcsFromMem = true;
8489 }
8490 else
8491 fLoadVmcsFromMem = false;
8492 }
8493 else
8494 fLoadVmcsFromMem = true;
8495
8496 if (fLoadVmcsFromMem)
8497 {
8498 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8499 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8500 sizeof(VMXVVMCS));
8501 if (RT_SUCCESS(rc))
8502 { /* likely */ }
8503 else
8504 {
8505 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8507 return rc;
8508 }
8509 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8510 }
8511
8512 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8513 iemVmxVmSucceed(pVCpu);
8514 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8515 return VINF_SUCCESS;
8516}
8517
8518
8519/**
8520 * VMXON instruction execution worker.
8521 *
8522 * @returns Strict VBox status code.
8523 * @param pVCpu The cross context virtual CPU structure.
8524 * @param cbInstr The instruction length in bytes.
8525 * @param iEffSeg The effective segment register to use with @a
8526 * GCPtrVmxon.
8527 * @param GCPtrVmxon The linear address of the VMXON pointer.
8528 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8529 * Optional, can be NULL.
8530 *
8531 * @remarks Common VMX instruction checks are already expected to by the caller,
8532 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8533 */
8534IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8535 PCVMXVEXITINFO pExitInfo)
8536{
8537 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8538 {
8539 /* CPL. */
8540 if (pVCpu->iem.s.uCpl == 0)
8541 { /* likely */ }
8542 else
8543 {
8544 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8545 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8546 return iemRaiseGeneralProtectionFault0(pVCpu);
8547 }
8548
8549 /* A20M (A20 Masked) mode. */
8550 if (PGMPhysIsA20Enabled(pVCpu))
8551 { /* likely */ }
8552 else
8553 {
8554 Log(("vmxon: A20M mode -> #GP(0)\n"));
8555 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8556 return iemRaiseGeneralProtectionFault0(pVCpu);
8557 }
8558
8559 /* CR0. */
8560 {
8561 /* CR0 MB1 bits. */
8562 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8563 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8564 { /* likely */ }
8565 else
8566 {
8567 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8569 return iemRaiseGeneralProtectionFault0(pVCpu);
8570 }
8571
8572 /* CR0 MBZ bits. */
8573 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8574 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8575 { /* likely */ }
8576 else
8577 {
8578 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8580 return iemRaiseGeneralProtectionFault0(pVCpu);
8581 }
8582 }
8583
8584 /* CR4. */
8585 {
8586 /* CR4 MB1 bits. */
8587 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8588 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8589 { /* likely */ }
8590 else
8591 {
8592 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8593 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8594 return iemRaiseGeneralProtectionFault0(pVCpu);
8595 }
8596
8597 /* CR4 MBZ bits. */
8598 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8599 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8600 { /* likely */ }
8601 else
8602 {
8603 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8605 return iemRaiseGeneralProtectionFault0(pVCpu);
8606 }
8607 }
8608
8609 /* Feature control MSR's LOCK and VMXON bits. */
8610 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8611 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8612 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8613 { /* likely */ }
8614 else
8615 {
8616 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8618 return iemRaiseGeneralProtectionFault0(pVCpu);
8619 }
8620
8621 /* Get the VMXON pointer from the location specified by the source memory operand. */
8622 RTGCPHYS GCPhysVmxon;
8623 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8624 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8625 { /* likely */ }
8626 else
8627 {
8628 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8629 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8630 return rcStrict;
8631 }
8632
8633 /* VMXON region pointer alignment. */
8634 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8635 { /* likely */ }
8636 else
8637 {
8638 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8640 iemVmxVmFailInvalid(pVCpu);
8641 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8642 return VINF_SUCCESS;
8643 }
8644
8645 /* VMXON physical-address width limits. */
8646 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8647 { /* likely */ }
8648 else
8649 {
8650 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8652 iemVmxVmFailInvalid(pVCpu);
8653 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8654 return VINF_SUCCESS;
8655 }
8656
8657 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8658 restriction imposed by our implementation. */
8659 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8660 { /* likely */ }
8661 else
8662 {
8663 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8664 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8665 iemVmxVmFailInvalid(pVCpu);
8666 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8667 return VINF_SUCCESS;
8668 }
8669
8670 /* Read the VMCS revision ID from the VMXON region. */
8671 VMXVMCSREVID VmcsRevId;
8672 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8673 if (RT_SUCCESS(rc))
8674 { /* likely */ }
8675 else
8676 {
8677 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8678 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8679 return rc;
8680 }
8681
8682 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8683 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8684 { /* likely */ }
8685 else
8686 {
8687 /* Revision ID mismatch. */
8688 if (!VmcsRevId.n.fIsShadowVmcs)
8689 {
8690 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8691 VmcsRevId.n.u31RevisionId));
8692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8693 iemVmxVmFailInvalid(pVCpu);
8694 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8695 return VINF_SUCCESS;
8696 }
8697
8698 /* Shadow VMCS disallowed. */
8699 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8700 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8701 iemVmxVmFailInvalid(pVCpu);
8702 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8703 return VINF_SUCCESS;
8704 }
8705
8706 /*
8707 * Record that we're in VMX operation, block INIT, block and disable A20M.
8708 */
8709 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8710 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8711 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8712
8713 /* Clear address-range monitoring. */
8714 EMMonitorWaitClear(pVCpu);
8715 /** @todo NSTVMX: Intel PT. */
8716
8717 iemVmxVmSucceed(pVCpu);
8718 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8719 return VINF_SUCCESS;
8720 }
8721 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8722 {
8723 /* Nested-guest intercept. */
8724 if (pExitInfo)
8725 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8726 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8727 }
8728
8729 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8730
8731 /* CPL. */
8732 if (pVCpu->iem.s.uCpl > 0)
8733 {
8734 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8735 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8736 return iemRaiseGeneralProtectionFault0(pVCpu);
8737 }
8738
8739 /* VMXON when already in VMX root mode. */
8740 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8741 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8742 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8743 return VINF_SUCCESS;
8744}
8745
8746
8747/**
8748 * Implements 'VMXOFF'.
8749 *
8750 * @remarks Common VMX instruction checks are already expected to by the caller,
8751 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8752 */
8753IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8754{
8755 /* Nested-guest intercept. */
8756 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8757 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8758
8759 /* CPL. */
8760 if (pVCpu->iem.s.uCpl == 0)
8761 { /* likely */ }
8762 else
8763 {
8764 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8766 return iemRaiseGeneralProtectionFault0(pVCpu);
8767 }
8768
8769 /* Dual monitor treatment of SMIs and SMM. */
8770 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8771 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8772 { /* likely */ }
8773 else
8774 {
8775 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8776 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8777 return VINF_SUCCESS;
8778 }
8779
8780 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8781 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8782 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8783
8784 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8785 { /** @todo NSTVMX: Unblock SMI. */ }
8786
8787 EMMonitorWaitClear(pVCpu);
8788 /** @todo NSTVMX: Unblock and enable A20M. */
8789
8790 iemVmxVmSucceed(pVCpu);
8791 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8792 return VINF_SUCCESS;
8793}
8794
8795
8796/**
8797 * Implements 'VMXON'.
8798 */
8799IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8800{
8801 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8802}
8803
8804
8805/**
8806 * Implements 'VMLAUNCH'.
8807 */
8808IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8809{
8810 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8811}
8812
8813
8814/**
8815 * Implements 'VMRESUME'.
8816 */
8817IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8818{
8819 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8820}
8821
8822
8823/**
8824 * Implements 'VMPTRLD'.
8825 */
8826IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8827{
8828 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8829}
8830
8831
8832/**
8833 * Implements 'VMPTRST'.
8834 */
8835IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8836{
8837 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8838}
8839
8840
8841/**
8842 * Implements 'VMCLEAR'.
8843 */
8844IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8845{
8846 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8847}
8848
8849
8850/**
8851 * Implements 'VMWRITE' register.
8852 */
8853IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8854{
8855 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8856 NULL /* pExitInfo */);
8857}
8858
8859
8860/**
8861 * Implements 'VMWRITE' memory.
8862 */
8863IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8864{
8865 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8866}
8867
8868
8869/**
8870 * Implements 'VMREAD' register (64-bit).
8871 */
8872IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8873{
8874 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8875}
8876
8877
8878/**
8879 * Implements 'VMREAD' register (32-bit).
8880 */
8881IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8882{
8883 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8884}
8885
8886
8887/**
8888 * Implements 'VMREAD' memory, 64-bit register.
8889 */
8890IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8891{
8892 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8893}
8894
8895
8896/**
8897 * Implements 'VMREAD' memory, 32-bit register.
8898 */
8899IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8900{
8901 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8902}
8903
8904
8905/**
8906 * Implements VMX's implementation of PAUSE.
8907 */
8908IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8909{
8910 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8911 {
8912 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8913 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8914 return rcStrict;
8915 }
8916
8917 /*
8918 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8919 * a VM-exit, the instruction operates normally.
8920 */
8921 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8922 return VINF_SUCCESS;
8923}
8924
8925#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8926
8927
8928/**
8929 * Implements 'VMCALL'.
8930 */
8931IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8932{
8933#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8934 /* Nested-guest intercept. */
8935 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8936 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8937#endif
8938
8939 /* Join forces with vmmcall. */
8940 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8941}
8942
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