VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78592

Last change on this file since 78592 was 78592, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Fixed vmread/vmwrite instruction execution workers to not need enmAddrMode anymore (callers do the work). Fixed exit code for iemVmxVmexit(). Fixed updating VM-exit MSR store area on VM-exit. Fixed minor code issues, style and assertions.
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File size: 360.1 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78592 2019-05-20 10:07:18Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
266 /* 24 */ UINT16_MAX,
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
290 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
291 },
292 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
293 {
294 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
295 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
296 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
297 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
298 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
300 },
301 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
304 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
305 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
306 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
307 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
308 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
309 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
310 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
311 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
312 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
313 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
314 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
315 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
316 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
317 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
318 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
319 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
320 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
321 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
322 },
323 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
324 {
325 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
326 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
327 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
328 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
329 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
330 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
331 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
332 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
333 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 24-25 */ UINT16_MAX, UINT16_MAX
336 },
337 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
338 {
339 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
340 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
341 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
342 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
343 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
344 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
345 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
346 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
347 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
348 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
349 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
350 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
351 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
352 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
353 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
354 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
355 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
356 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
357 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
358 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
359 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
360 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
361 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
362 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
363 },
364 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
365 {
366 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
367 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
368 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 25 */ UINT16_MAX
371 },
372 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
373 {
374 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
375 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
376 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
377 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
378 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
379 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
380 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
381 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
382 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 24-25 */ UINT16_MAX, UINT16_MAX
385 },
386 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
387 {
388 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
389 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
390 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
391 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
392 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
393 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
394 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
397 },
398 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
399 {
400 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
401 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
402 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
403 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
404 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
405 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
406 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
407 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
408 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
409 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
410 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
411 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
412 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
413 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
414 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
415 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
416 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
417 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
418 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
419 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
420 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
421 },
422 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
423 {
424 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
425 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
426 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
427 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
428 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
429 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
430 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
431 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
432 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
433 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
434 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
435 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
436 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
437 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
438 }
439};
440
441
442/**
443 * Returns whether the given VMCS field is valid and supported by our emulation.
444 *
445 * @param pVCpu The cross context virtual CPU structure.
446 * @param u64FieldEnc The VMCS field encoding.
447 *
448 * @remarks This takes into account the CPU features exposed to the guest.
449 */
450IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
451{
452 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
453 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
454 if (!uFieldEncHi)
455 { /* likely */ }
456 else
457 return false;
458
459 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
460 switch (uFieldEncLo)
461 {
462 /*
463 * 16-bit fields.
464 */
465 /* Control fields. */
466 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
467 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
468 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
469
470 /* Guest-state fields. */
471 case VMX_VMCS16_GUEST_ES_SEL:
472 case VMX_VMCS16_GUEST_CS_SEL:
473 case VMX_VMCS16_GUEST_SS_SEL:
474 case VMX_VMCS16_GUEST_DS_SEL:
475 case VMX_VMCS16_GUEST_FS_SEL:
476 case VMX_VMCS16_GUEST_GS_SEL:
477 case VMX_VMCS16_GUEST_LDTR_SEL:
478 case VMX_VMCS16_GUEST_TR_SEL: return true;
479 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
480 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
481
482 /* Host-state fields. */
483 case VMX_VMCS16_HOST_ES_SEL:
484 case VMX_VMCS16_HOST_CS_SEL:
485 case VMX_VMCS16_HOST_SS_SEL:
486 case VMX_VMCS16_HOST_DS_SEL:
487 case VMX_VMCS16_HOST_FS_SEL:
488 case VMX_VMCS16_HOST_GS_SEL:
489 case VMX_VMCS16_HOST_TR_SEL: return true;
490
491 /*
492 * 64-bit fields.
493 */
494 /* Control fields. */
495 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
497 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
499 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
500 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
501 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
503 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
505 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
507 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
509 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
511 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
512 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
513 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
515 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
517 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
519 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
521 case VMX_VMCS64_CTRL_EPTP_FULL:
522 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
523 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
531 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
532 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
533 {
534 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
535 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
536 }
537 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
539 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
541 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
543 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
545 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
547 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
549
550 /* Read-only data fields. */
551 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
553
554 /* Guest-state fields. */
555 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
557 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
558 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
559 case VMX_VMCS64_GUEST_PAT_FULL:
560 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
561 case VMX_VMCS64_GUEST_EFER_FULL:
562 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
563 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
565 case VMX_VMCS64_GUEST_PDPTE0_FULL:
566 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
567 case VMX_VMCS64_GUEST_PDPTE1_FULL:
568 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
569 case VMX_VMCS64_GUEST_PDPTE2_FULL:
570 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
571 case VMX_VMCS64_GUEST_PDPTE3_FULL:
572 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
573 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
574 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
575
576 /* Host-state fields. */
577 case VMX_VMCS64_HOST_PAT_FULL:
578 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
579 case VMX_VMCS64_HOST_EFER_FULL:
580 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
581 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
583
584 /*
585 * 32-bit fields.
586 */
587 /* Control fields. */
588 case VMX_VMCS32_CTRL_PIN_EXEC:
589 case VMX_VMCS32_CTRL_PROC_EXEC:
590 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
591 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
593 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
594 case VMX_VMCS32_CTRL_EXIT:
595 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
597 case VMX_VMCS32_CTRL_ENTRY:
598 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
599 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
600 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
601 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
602 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
603 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
604 case VMX_VMCS32_CTRL_PLE_GAP:
605 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
606
607 /* Read-only data fields. */
608 case VMX_VMCS32_RO_VM_INSTR_ERROR:
609 case VMX_VMCS32_RO_EXIT_REASON:
610 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
612 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
613 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
614 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
615 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
616
617 /* Guest-state fields. */
618 case VMX_VMCS32_GUEST_ES_LIMIT:
619 case VMX_VMCS32_GUEST_CS_LIMIT:
620 case VMX_VMCS32_GUEST_SS_LIMIT:
621 case VMX_VMCS32_GUEST_DS_LIMIT:
622 case VMX_VMCS32_GUEST_FS_LIMIT:
623 case VMX_VMCS32_GUEST_GS_LIMIT:
624 case VMX_VMCS32_GUEST_LDTR_LIMIT:
625 case VMX_VMCS32_GUEST_TR_LIMIT:
626 case VMX_VMCS32_GUEST_GDTR_LIMIT:
627 case VMX_VMCS32_GUEST_IDTR_LIMIT:
628 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
629 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_INT_STATE:
637 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
638 case VMX_VMCS32_GUEST_SMBASE:
639 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
640 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
641
642 /* Host-state fields. */
643 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
644
645 /*
646 * Natural-width fields.
647 */
648 /* Control fields. */
649 case VMX_VMCS_CTRL_CR0_MASK:
650 case VMX_VMCS_CTRL_CR4_MASK:
651 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
652 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
657
658 /* Read-only data fields. */
659 case VMX_VMCS_RO_EXIT_QUALIFICATION:
660 case VMX_VMCS_RO_IO_RCX:
661 case VMX_VMCS_RO_IO_RSI:
662 case VMX_VMCS_RO_IO_RDI:
663 case VMX_VMCS_RO_IO_RIP:
664 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
665
666 /* Guest-state fields. */
667 case VMX_VMCS_GUEST_CR0:
668 case VMX_VMCS_GUEST_CR3:
669 case VMX_VMCS_GUEST_CR4:
670 case VMX_VMCS_GUEST_ES_BASE:
671 case VMX_VMCS_GUEST_CS_BASE:
672 case VMX_VMCS_GUEST_SS_BASE:
673 case VMX_VMCS_GUEST_DS_BASE:
674 case VMX_VMCS_GUEST_FS_BASE:
675 case VMX_VMCS_GUEST_GS_BASE:
676 case VMX_VMCS_GUEST_LDTR_BASE:
677 case VMX_VMCS_GUEST_TR_BASE:
678 case VMX_VMCS_GUEST_GDTR_BASE:
679 case VMX_VMCS_GUEST_IDTR_BASE:
680 case VMX_VMCS_GUEST_DR7:
681 case VMX_VMCS_GUEST_RSP:
682 case VMX_VMCS_GUEST_RIP:
683 case VMX_VMCS_GUEST_RFLAGS:
684 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
685 case VMX_VMCS_GUEST_SYSENTER_ESP:
686 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
687
688 /* Host-state fields. */
689 case VMX_VMCS_HOST_CR0:
690 case VMX_VMCS_HOST_CR3:
691 case VMX_VMCS_HOST_CR4:
692 case VMX_VMCS_HOST_FS_BASE:
693 case VMX_VMCS_HOST_GS_BASE:
694 case VMX_VMCS_HOST_TR_BASE:
695 case VMX_VMCS_HOST_GDTR_BASE:
696 case VMX_VMCS_HOST_IDTR_BASE:
697 case VMX_VMCS_HOST_SYSENTER_ESP:
698 case VMX_VMCS_HOST_SYSENTER_EIP:
699 case VMX_VMCS_HOST_RSP:
700 case VMX_VMCS_HOST_RIP: return true;
701 }
702
703 return false;
704}
705
706
707/**
708 * Gets a host selector from the VMCS.
709 *
710 * @param pVmcs Pointer to the virtual VMCS.
711 * @param iSelReg The index of the segment register (X86_SREG_XXX).
712 */
713DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
714{
715 Assert(iSegReg < X86_SREG_COUNT);
716 RTSEL HostSel;
717 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
718 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
719 uint8_t const uWidthType = (uWidth << 2) | uType;
720 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
721 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
722 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
723 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
724 uint8_t const *pbField = pbVmcs + offField;
725 HostSel = *(uint16_t *)pbField;
726 return HostSel;
727}
728
729
730/**
731 * Sets a guest segment register in the VMCS.
732 *
733 * @param pVmcs Pointer to the virtual VMCS.
734 * @param iSegReg The index of the segment register (X86_SREG_XXX).
735 * @param pSelReg Pointer to the segment register.
736 */
737IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
738{
739 Assert(pSelReg);
740 Assert(iSegReg < X86_SREG_COUNT);
741
742 /* Selector. */
743 {
744 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
745 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
746 uint8_t const uWidthType = (uWidth << 2) | uType;
747 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
748 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
749 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
750 uint8_t *pbVmcs = (uint8_t *)pVmcs;
751 uint8_t *pbField = pbVmcs + offField;
752 *(uint16_t *)pbField = pSelReg->Sel;
753 }
754
755 /* Limit. */
756 {
757 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
758 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
759 uint8_t const uWidthType = (uWidth << 2) | uType;
760 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
761 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
762 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
763 uint8_t *pbVmcs = (uint8_t *)pVmcs;
764 uint8_t *pbField = pbVmcs + offField;
765 *(uint32_t *)pbField = pSelReg->u32Limit;
766 }
767
768 /* Base. */
769 {
770 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
771 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
772 uint8_t const uWidthType = (uWidth << 2) | uType;
773 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
774 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
775 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
776 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
777 uint8_t const *pbField = pbVmcs + offField;
778 *(uint64_t *)pbField = pSelReg->u64Base;
779 }
780
781 /* Attributes. */
782 {
783 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
784 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
785 | X86DESCATTR_UNUSABLE;
786 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
787 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
788 uint8_t const uWidthType = (uWidth << 2) | uType;
789 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
790 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
791 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
792 uint8_t *pbVmcs = (uint8_t *)pVmcs;
793 uint8_t *pbField = pbVmcs + offField;
794 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
795 }
796}
797
798
799/**
800 * Gets a guest segment register from the VMCS.
801 *
802 * @returns VBox status code.
803 * @param pVmcs Pointer to the virtual VMCS.
804 * @param iSegReg The index of the segment register (X86_SREG_XXX).
805 * @param pSelReg Where to store the segment register (only updated when
806 * VINF_SUCCESS is returned).
807 *
808 * @remarks Warning! This does not validate the contents of the retrieved segment
809 * register.
810 */
811IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
812{
813 Assert(pSelReg);
814 Assert(iSegReg < X86_SREG_COUNT);
815
816 /* Selector. */
817 uint16_t u16Sel;
818 {
819 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
820 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
821 uint8_t const uWidthType = (uWidth << 2) | uType;
822 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
823 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
824 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
825 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
826 uint8_t const *pbField = pbVmcs + offField;
827 u16Sel = *(uint16_t *)pbField;
828 }
829
830 /* Limit. */
831 uint32_t u32Limit;
832 {
833 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
834 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
835 uint8_t const uWidthType = (uWidth << 2) | uType;
836 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
837 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
838 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
839 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
840 uint8_t const *pbField = pbVmcs + offField;
841 u32Limit = *(uint32_t *)pbField;
842 }
843
844 /* Base. */
845 uint64_t u64Base;
846 {
847 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
848 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
849 uint8_t const uWidthType = (uWidth << 2) | uType;
850 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
851 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
852 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
853 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
854 uint8_t const *pbField = pbVmcs + offField;
855 u64Base = *(uint64_t *)pbField;
856 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
857 }
858
859 /* Attributes. */
860 uint32_t u32Attr;
861 {
862 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
863 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
864 uint8_t const uWidthType = (uWidth << 2) | uType;
865 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
866 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
867 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
868 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
869 uint8_t const *pbField = pbVmcs + offField;
870 u32Attr = *(uint32_t *)pbField;
871 }
872
873 pSelReg->Sel = u16Sel;
874 pSelReg->ValidSel = u16Sel;
875 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
876 pSelReg->u32Limit = u32Limit;
877 pSelReg->u64Base = u64Base;
878 pSelReg->Attr.u = u32Attr;
879 return VINF_SUCCESS;
880}
881
882
883/**
884 * Gets a CR3 target value from the VMCS.
885 *
886 * @returns VBox status code.
887 * @param pVmcs Pointer to the virtual VMCS.
888 * @param idxCr3Target The index of the CR3-target value to retrieve.
889 * @param puValue Where to store the CR3-target value.
890 */
891IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
892{
893 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
898 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
903 return uCr3TargetValue;
904}
905
906
907/**
908 * Converts an IEM exception event type to a VMX event type.
909 *
910 * @returns The VMX event type.
911 * @param uVector The interrupt / exception vector.
912 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
913 */
914DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
915{
916 /* Paranoia (callers may use these interchangeably). */
917 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
929
930 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
931 {
932 if (uVector == X86_XCPT_NMI)
933 return VMX_EXIT_INT_INFO_TYPE_NMI;
934 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
935 }
936
937 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
938 {
939 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
940 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
941 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
942 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
943 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
944 }
945
946 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
947 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
948}
949
950
951/**
952 * Sets the VM-exit qualification VMCS field.
953 *
954 * @param pVCpu The cross context virtual CPU structure.
955 * @param uExitQual The VM-exit qualification.
956 */
957DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
958{
959 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
960 pVmcs->u64RoExitQual.u = uExitQual;
961}
962
963
964/**
965 * Sets the VM-exit interruption information field.
966 *
967 * @param pVCpu The cross context virtual CPU structure.
968 * @param uExitQual The VM-exit interruption information.
969 */
970DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
971{
972 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
973 pVmcs->u32RoExitIntInfo = uExitIntInfo;
974}
975
976
977/**
978 * Sets the VM-exit interruption error code.
979 *
980 * @param pVCpu The cross context virtual CPU structure.
981 * @param uErrCode The error code.
982 */
983DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
984{
985 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
986 pVmcs->u32RoExitIntErrCode = uErrCode;
987}
988
989
990/**
991 * Sets the IDT-vectoring information field.
992 *
993 * @param pVCpu The cross context virtual CPU structure.
994 * @param uIdtVectorInfo The IDT-vectoring information.
995 */
996DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
997{
998 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
999 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1000}
1001
1002
1003/**
1004 * Sets the IDT-vectoring error code field.
1005 *
1006 * @param pVCpu The cross context virtual CPU structure.
1007 * @param uErrCode The error code.
1008 */
1009DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1010{
1011 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1012 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1013}
1014
1015
1016/**
1017 * Sets the VM-exit guest-linear address VMCS field.
1018 *
1019 * @param pVCpu The cross context virtual CPU structure.
1020 * @param uGuestLinearAddr The VM-exit guest-linear address.
1021 */
1022DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1023{
1024 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1025 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1026}
1027
1028
1029/**
1030 * Sets the VM-exit guest-physical address VMCS field.
1031 *
1032 * @param pVCpu The cross context virtual CPU structure.
1033 * @param uGuestPhysAddr The VM-exit guest-physical address.
1034 */
1035DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1036{
1037 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1038 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1039}
1040
1041
1042/**
1043 * Sets the VM-exit instruction length VMCS field.
1044 *
1045 * @param pVCpu The cross context virtual CPU structure.
1046 * @param cbInstr The VM-exit instruction length in bytes.
1047 *
1048 * @remarks Callers may clear this field to 0. Hence, this function does not check
1049 * the validity of the instruction length.
1050 */
1051DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1052{
1053 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1054 pVmcs->u32RoExitInstrLen = cbInstr;
1055}
1056
1057
1058/**
1059 * Sets the VM-exit instruction info. VMCS field.
1060 *
1061 * @param pVCpu The cross context virtual CPU structure.
1062 * @param uExitInstrInfo The VM-exit instruction information.
1063 */
1064DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1065{
1066 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1067 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1068}
1069
1070
1071/**
1072 * Implements VMSucceed for VMX instruction success.
1073 *
1074 * @param pVCpu The cross context virtual CPU structure.
1075 */
1076DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1077{
1078 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1079}
1080
1081
1082/**
1083 * Implements VMFailInvalid for VMX instruction failure.
1084 *
1085 * @param pVCpu The cross context virtual CPU structure.
1086 */
1087DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1088{
1089 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1090}
1091
1092
1093/**
1094 * Implements VMFail for VMX instruction failure.
1095 *
1096 * @param pVCpu The cross context virtual CPU structure.
1097 * @param enmInsErr The VM instruction error.
1098 */
1099DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1100{
1101 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1102}
1103
1104
1105/**
1106 * Checks if the given auto-load/store MSR area count is valid for the
1107 * implementation.
1108 *
1109 * @returns @c true if it's within the valid limit, @c false otherwise.
1110 * @param pVCpu The cross context virtual CPU structure.
1111 * @param uMsrCount The MSR area count to check.
1112 */
1113DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1114{
1115 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1116 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1117 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1118 if (uMsrCount <= cMaxSupportedMsrs)
1119 return true;
1120 return false;
1121}
1122
1123
1124/**
1125 * Flushes the current VMCS contents back to guest memory.
1126 *
1127 * @returns VBox status code.
1128 * @param pVCpu The cross context virtual CPU structure.
1129 */
1130DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1131{
1132 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1133 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1134 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1135 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1136 return rc;
1137}
1138
1139
1140/**
1141 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1142 *
1143 * @param pVCpu The cross context virtual CPU structure.
1144 */
1145DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1146{
1147 iemVmxVmSucceed(pVCpu);
1148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1149}
1150
1151
1152/**
1153 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1154 * nested-guest.
1155 *
1156 * @param iSegReg The segment index (X86_SREG_XXX).
1157 */
1158IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1159{
1160 switch (iSegReg)
1161 {
1162 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1163 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1164 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1165 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1166 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1167 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1168 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1169 }
1170}
1171
1172
1173/**
1174 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1175 * nested-guest that is in Virtual-8086 mode.
1176 *
1177 * @param iSegReg The segment index (X86_SREG_XXX).
1178 */
1179IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1180{
1181 switch (iSegReg)
1182 {
1183 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1184 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1185 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1186 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1187 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1188 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1189 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1190 }
1191}
1192
1193
1194/**
1195 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1196 * nested-guest that is in Virtual-8086 mode.
1197 *
1198 * @param iSegReg The segment index (X86_SREG_XXX).
1199 */
1200IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1201{
1202 switch (iSegReg)
1203 {
1204 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1205 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1206 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1207 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1208 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1209 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1210 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1211 }
1212}
1213
1214
1215/**
1216 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1217 * nested-guest that is in Virtual-8086 mode.
1218 *
1219 * @param iSegReg The segment index (X86_SREG_XXX).
1220 */
1221IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1222{
1223 switch (iSegReg)
1224 {
1225 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1226 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1227 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1228 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1229 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1230 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1231 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1232 }
1233}
1234
1235
1236/**
1237 * Gets the instruction diagnostic for segment attributes reserved bits failure
1238 * during VM-entry of a nested-guest.
1239 *
1240 * @param iSegReg The segment index (X86_SREG_XXX).
1241 */
1242IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1243{
1244 switch (iSegReg)
1245 {
1246 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1247 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1248 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1249 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1250 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1251 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1252 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1253 }
1254}
1255
1256
1257/**
1258 * Gets the instruction diagnostic for segment attributes descriptor-type
1259 * (code/segment or system) failure during VM-entry of a nested-guest.
1260 *
1261 * @param iSegReg The segment index (X86_SREG_XXX).
1262 */
1263IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1264{
1265 switch (iSegReg)
1266 {
1267 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1268 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1269 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1270 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1271 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1272 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1273 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1274 }
1275}
1276
1277
1278/**
1279 * Gets the instruction diagnostic for segment attributes descriptor-type
1280 * (code/segment or system) failure during VM-entry of a nested-guest.
1281 *
1282 * @param iSegReg The segment index (X86_SREG_XXX).
1283 */
1284IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1285{
1286 switch (iSegReg)
1287 {
1288 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1289 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1290 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1291 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1292 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1293 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1294 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1295 }
1296}
1297
1298
1299/**
1300 * Gets the instruction diagnostic for segment attribute granularity failure during
1301 * VM-entry of a nested-guest.
1302 *
1303 * @param iSegReg The segment index (X86_SREG_XXX).
1304 */
1305IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1306{
1307 switch (iSegReg)
1308 {
1309 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1310 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1311 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1312 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1313 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1314 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1315 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1316 }
1317}
1318
1319/**
1320 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1321 * VM-entry of a nested-guest.
1322 *
1323 * @param iSegReg The segment index (X86_SREG_XXX).
1324 */
1325IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1326{
1327 switch (iSegReg)
1328 {
1329 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1330 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1331 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1332 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1333 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1334 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1335 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1336 }
1337}
1338
1339
1340/**
1341 * Gets the instruction diagnostic for segment attribute type accessed failure
1342 * during VM-entry of a nested-guest.
1343 *
1344 * @param iSegReg The segment index (X86_SREG_XXX).
1345 */
1346IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1347{
1348 switch (iSegReg)
1349 {
1350 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1351 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1352 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1353 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1354 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1355 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1356 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1357 }
1358}
1359
1360
1361/**
1362 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1363 * failure during VM-entry of a nested-guest.
1364 *
1365 * @param iSegReg The PDPTE entry index.
1366 */
1367IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1368{
1369 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1370 switch (iPdpte)
1371 {
1372 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1373 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1374 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1375 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1376 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1377 }
1378}
1379
1380
1381/**
1382 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1383 * failure during VM-exit of a nested-guest.
1384 *
1385 * @param iSegReg The PDPTE entry index.
1386 */
1387IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1388{
1389 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1390 switch (iPdpte)
1391 {
1392 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1393 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1394 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1395 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1396 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1397 }
1398}
1399
1400
1401/**
1402 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1403 * mask and the read-shadow (CR0/CR4 read).
1404 *
1405 * @returns The masked CR0/CR4.
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param iCrReg The control register (either CR0 or CR4).
1408 * @param uGuestCrX The current guest CR0 or guest CR4.
1409 */
1410IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1411{
1412 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1413 Assert(iCrReg == 0 || iCrReg == 4);
1414
1415 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1416 Assert(pVmcs);
1417
1418 /*
1419 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1420 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1421 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1422 *
1423 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1424 */
1425 uint64_t fGstHostMask;
1426 uint64_t fReadShadow;
1427 if (iCrReg == 0)
1428 {
1429 fGstHostMask = pVmcs->u64Cr0Mask.u;
1430 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1431 }
1432 else
1433 {
1434 fGstHostMask = pVmcs->u64Cr4Mask.u;
1435 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1436 }
1437
1438 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1439 return fMaskedCrX;
1440}
1441
1442
1443/**
1444 * Saves the guest control registers, debug registers and some MSRs are part of
1445 * VM-exit.
1446 *
1447 * @param pVCpu The cross context virtual CPU structure.
1448 */
1449IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1450{
1451 /*
1452 * Saves the guest control registers, debug registers and some MSRs.
1453 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1454 */
1455 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1456
1457 /* Save control registers. */
1458 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1459 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1460 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1461
1462 /* Save SYSENTER CS, ESP, EIP. */
1463 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1464 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1465 {
1466 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1467 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1468 }
1469 else
1470 {
1471 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1472 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1473 }
1474
1475 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1476 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1477 {
1478 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1479 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1480 }
1481
1482 /* Save PAT MSR. */
1483 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1484 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1485
1486 /* Save EFER MSR. */
1487 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1488 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1489
1490 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1491 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1492
1493 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1494}
1495
1496
1497/**
1498 * Saves the guest force-flags in preparation of entering the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 /* We shouldn't be called multiple times during VM-entry. */
1505 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1506
1507 /* MTF should not be set outside VMX non-root mode. */
1508 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1509
1510 /*
1511 * Preserve the required force-flags.
1512 *
1513 * We cache and clear force-flags that would affect the execution of the
1514 * nested-guest. Cached flags are then restored while returning to the guest
1515 * if necessary.
1516 *
1517 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1518 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1519 * instruction. Interrupt inhibition for any nested-guest instruction
1520 * is supplied by the guest-interruptibility state VMCS field and will
1521 * be set up as part of loading the guest state.
1522 *
1523 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1524 * successful VM-entry (due to invalid guest-state) need to continue
1525 * blocking NMIs if it was in effect before VM-entry.
1526 *
1527 * - MTF need not be preserved as it's used only in VMX non-root mode and
1528 * is supplied through the VM-execution controls.
1529 *
1530 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1531 * we will be able to generate interrupts that may cause VM-exits for
1532 * the nested-guest.
1533 */
1534 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1535}
1536
1537
1538/**
1539 * Restores the guest force-flags in preparation of exiting the nested-guest.
1540 *
1541 * @param pVCpu The cross context virtual CPU structure.
1542 */
1543IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1544{
1545 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1546 {
1547 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1548 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1549 }
1550}
1551
1552
1553/**
1554 * Perform a VMX transition updated PGM, IEM and CPUM.
1555 *
1556 * @param pVCpu The cross context virtual CPU structure.
1557 */
1558IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1559{
1560 /*
1561 * Inform PGM about paging mode changes.
1562 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1563 * see comment in iemMemPageTranslateAndCheckAccess().
1564 */
1565 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1566# ifdef IN_RING3
1567 Assert(rc != VINF_PGM_CHANGE_MODE);
1568# endif
1569 AssertRCReturn(rc, rc);
1570
1571 /* Inform CPUM (recompiler), can later be removed. */
1572 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1573
1574 /*
1575 * Flush the TLB with new CR3. This is required in case the PGM mode change
1576 * above doesn't actually change anything.
1577 */
1578 if (rc == VINF_SUCCESS)
1579 {
1580 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1581 AssertRCReturn(rc, rc);
1582 }
1583
1584 /* Re-initialize IEM cache/state after the drastic mode switch. */
1585 iemReInitExec(pVCpu);
1586 return rc;
1587}
1588
1589
1590/**
1591 * Calculates the current VMX-preemption timer value.
1592 *
1593 * @param pVCpu The cross context virtual CPU structure.
1594 */
1595IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1596{
1597 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1598 Assert(pVmcs);
1599
1600 /*
1601 * Assume the following:
1602 * PreemptTimerShift = 5
1603 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1604 * EntryTick = 50000 (TSC at time of VM-entry)
1605 *
1606 * CurTick Delta PreemptTimerVal
1607 * ----------------------------------
1608 * 60000 10000 2
1609 * 80000 30000 1
1610 * 90000 40000 0 -> VM-exit.
1611 *
1612 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1613 * The saved VMX-preemption timer value is calculated as follows:
1614 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1615 * E.g.:
1616 * Delta = 10000
1617 * Tmp = 10000 / (2 * 10000) = 0.5
1618 * NewPt = 2 - 0.5 = 2
1619 * Delta = 30000
1620 * Tmp = 30000 / (2 * 10000) = 1.5
1621 * NewPt = 2 - 1.5 = 1
1622 * Delta = 40000
1623 * Tmp = 40000 / 20000 = 2
1624 * NewPt = 2 - 2 = 0
1625 */
1626 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1627 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1628 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1629 uint64_t const uDelta = uCurTick - uEntryTick;
1630 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1631 uint32_t const uPreemptTimer = uVmcsPreemptVal
1632 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1633 return uPreemptTimer;
1634}
1635
1636
1637/**
1638 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1639 *
1640 * @param pVCpu The cross context virtual CPU structure.
1641 */
1642IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1643{
1644 /*
1645 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1646 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1647 */
1648 /* CS, SS, ES, DS, FS, GS. */
1649 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1650 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1651 {
1652 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1653 if (!pSelReg->Attr.n.u1Unusable)
1654 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1655 else
1656 {
1657 /*
1658 * For unusable segments the attributes are undefined except for CS and SS.
1659 * For the rest we don't bother preserving anything but the unusable bit.
1660 */
1661 switch (iSegReg)
1662 {
1663 case X86_SREG_CS:
1664 pVmcs->GuestCs = pSelReg->Sel;
1665 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1666 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1667 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1668 | X86DESCATTR_UNUSABLE);
1669 break;
1670
1671 case X86_SREG_SS:
1672 pVmcs->GuestSs = pSelReg->Sel;
1673 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1674 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1675 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1676 break;
1677
1678 case X86_SREG_DS:
1679 pVmcs->GuestDs = pSelReg->Sel;
1680 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1681 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1682 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1683 break;
1684
1685 case X86_SREG_ES:
1686 pVmcs->GuestEs = pSelReg->Sel;
1687 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1688 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1689 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1690 break;
1691
1692 case X86_SREG_FS:
1693 pVmcs->GuestFs = pSelReg->Sel;
1694 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1695 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1696 break;
1697
1698 case X86_SREG_GS:
1699 pVmcs->GuestGs = pSelReg->Sel;
1700 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1701 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1702 break;
1703 }
1704 }
1705 }
1706
1707 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1708 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1709 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1710 | X86DESCATTR_UNUSABLE;
1711 /* LDTR. */
1712 {
1713 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1714 pVmcs->GuestLdtr = pSelReg->Sel;
1715 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1716 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1717 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1718 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1719 }
1720
1721 /* TR. */
1722 {
1723 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1724 pVmcs->GuestTr = pSelReg->Sel;
1725 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1726 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1727 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1728 }
1729
1730 /* GDTR. */
1731 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1732 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1733
1734 /* IDTR. */
1735 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1736 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1737}
1738
1739
1740/**
1741 * Saves guest non-register state as part of VM-exit.
1742 *
1743 * @param pVCpu The cross context virtual CPU structure.
1744 * @param uExitReason The VM-exit reason.
1745 */
1746IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1747{
1748 /*
1749 * Save guest non-register state.
1750 * See Intel spec. 27.3.4 "Saving Non-Register State".
1751 */
1752 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1753
1754 /*
1755 * Activity state.
1756 * Most VM-exits will occur in the active state. However, if the first instruction
1757 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1758 * the VM-exit will be from the HLT activity state.
1759 *
1760 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1761 */
1762 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1763 * not? */
1764 EMSTATE const enmActivityState = EMGetState(pVCpu);
1765 switch (enmActivityState)
1766 {
1767 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1768 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1769 }
1770
1771 /*
1772 * Interruptibility-state.
1773 */
1774 /* NMI. */
1775 pVmcs->u32GuestIntrState = 0;
1776 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1777 {
1778 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1779 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1780 }
1781 else
1782 {
1783 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1784 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1785 }
1786
1787 /* Blocking-by-STI. */
1788 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1789 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1790 {
1791 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1792 * currently. */
1793 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1794 }
1795 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1796
1797 /*
1798 * Pending debug exceptions.
1799 */
1800 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1801 && uExitReason != VMX_EXIT_SMI
1802 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1803 && !HMVmxIsVmexitTrapLike(uExitReason))
1804 {
1805 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1806 * block-by-MovSS is in effect. */
1807 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1808 }
1809 else
1810 {
1811 /*
1812 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1813 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1814 *
1815 * See Intel spec. 24.4.2 "Guest Non-Register State".
1816 */
1817 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1818 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1819 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1820 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1821 if (fPendingDbgMask & fBpHitMask)
1822 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1823 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1824 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1825 }
1826
1827 /*
1828 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1829 *
1830 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1831 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1832 */
1833 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1834 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1835 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1836
1837 /* PDPTEs. */
1838 /* We don't support EPT yet. */
1839 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1840 pVmcs->u64GuestPdpte0.u = 0;
1841 pVmcs->u64GuestPdpte1.u = 0;
1842 pVmcs->u64GuestPdpte2.u = 0;
1843 pVmcs->u64GuestPdpte3.u = 0;
1844}
1845
1846
1847/**
1848 * Saves the guest-state as part of VM-exit.
1849 *
1850 * @returns VBox status code.
1851 * @param pVCpu The cross context virtual CPU structure.
1852 * @param uExitReason The VM-exit reason.
1853 */
1854IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1855{
1856 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1857 Assert(pVmcs);
1858
1859 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1860 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1861
1862 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1863 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1864 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1865
1866 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1867}
1868
1869
1870/**
1871 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1872 *
1873 * @returns VBox status code.
1874 * @param pVCpu The cross context virtual CPU structure.
1875 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1876 */
1877IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1878{
1879 /*
1880 * Save guest MSRs.
1881 * See Intel spec. 27.4 "Saving MSRs".
1882 */
1883 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1884 const char *const pszFailure = "VMX-abort";
1885
1886 /*
1887 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1888 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1889 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1890 */
1891 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1892 if (!cMsrs)
1893 return VINF_SUCCESS;
1894
1895 /*
1896 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1897 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1898 * implementation causes a VMX-abort followed by a triple-fault.
1899 */
1900 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1901 if (fIsMsrCountValid)
1902 { /* likely */ }
1903 else
1904 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1905
1906 /*
1907 * Optimization if the guest hypervisor is using the same guest-physical page for both
1908 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1909 */
1910 PVMXAUTOMSR pMsrArea;
1911 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1912 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1913 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1914 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1915 else
1916 {
1917 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1918 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1919 if (RT_SUCCESS(rc))
1920 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1921 else
1922 {
1923 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1924 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1925 }
1926 }
1927
1928 /*
1929 * Update VM-exit MSR store area.
1930 */
1931 PVMXAUTOMSR pMsr = pMsrArea;
1932 Assert(pMsr);
1933 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1934 {
1935 if ( !pMsr->u32Reserved
1936 && pMsr->u32Msr != MSR_IA32_SMBASE
1937 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1938 {
1939 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1940 if (rcStrict == VINF_SUCCESS)
1941 continue;
1942
1943 /*
1944 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1945 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1946 * recording the MSR index in the auxiliary info. field and indicated further by our
1947 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1948 * if possible, or come up with a better, generic solution.
1949 */
1950 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1951 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1952 ? kVmxVDiag_Vmexit_MsrStoreRing3
1953 : kVmxVDiag_Vmexit_MsrStore;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1955 }
1956 else
1957 {
1958 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1959 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1960 }
1961 }
1962
1963 /*
1964 * Commit the VM-exit MSR store are to guest memory.
1965 */
1966 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1967 if (RT_SUCCESS(rc))
1968 return VINF_SUCCESS;
1969
1970 NOREF(uExitReason);
1971 NOREF(pszFailure);
1972
1973 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1974 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1975}
1976
1977
1978/**
1979 * Performs a VMX abort (due to an fatal error during VM-exit).
1980 *
1981 * @returns Strict VBox status code.
1982 * @param pVCpu The cross context virtual CPU structure.
1983 * @param enmAbort The VMX abort reason.
1984 */
1985IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1986{
1987 /*
1988 * Perform the VMX abort.
1989 * See Intel spec. 27.7 "VMX Aborts".
1990 */
1991 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1992
1993 /* We don't support SMX yet. */
1994 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1995 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1996 {
1997 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1998 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1999 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2000 }
2001
2002 return VINF_EM_TRIPLE_FAULT;
2003}
2004
2005
2006/**
2007 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2008 *
2009 * @param pVCpu The cross context virtual CPU structure.
2010 */
2011IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2012{
2013 /*
2014 * Load host control registers, debug registers and MSRs.
2015 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2016 */
2017 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2018 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2019
2020 /* CR0. */
2021 {
2022 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2023 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2024 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2025 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2026 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2027 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2028 CPUMSetGuestCR0(pVCpu, uValidCr0);
2029 }
2030
2031 /* CR4. */
2032 {
2033 /* CR4 MB1 bits are not modified. */
2034 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2035 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2036 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2037 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2038 if (fHostInLongMode)
2039 uValidCr4 |= X86_CR4_PAE;
2040 else
2041 uValidCr4 &= ~X86_CR4_PCIDE;
2042 CPUMSetGuestCR4(pVCpu, uValidCr4);
2043 }
2044
2045 /* CR3 (host value validated while checking host-state during VM-entry). */
2046 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2047
2048 /* DR7. */
2049 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2050
2051 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2052
2053 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2054 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2055 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2056 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2057
2058 /* FS, GS bases are loaded later while we load host segment registers. */
2059
2060 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2061 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2062 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2063 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2064 {
2065 if (fHostInLongMode)
2066 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2067 else
2068 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2069 }
2070
2071 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2072
2073 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2074 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2075 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2076
2077 /* We don't support IA32_BNDCFGS MSR yet. */
2078}
2079
2080
2081/**
2082 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2083 *
2084 * @param pVCpu The cross context virtual CPU structure.
2085 */
2086IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2087{
2088 /*
2089 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2090 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2091 *
2092 * Warning! Be careful to not touch fields that are reserved by VT-x,
2093 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2094 */
2095 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2096 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2097
2098 /* CS, SS, ES, DS, FS, GS. */
2099 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2100 {
2101 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2102 bool const fUnusable = RT_BOOL(HostSel == 0);
2103 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2104
2105 /* Selector. */
2106 pSelReg->Sel = HostSel;
2107 pSelReg->ValidSel = HostSel;
2108 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2109
2110 /* Limit. */
2111 pSelReg->u32Limit = 0xffffffff;
2112
2113 /* Base. */
2114 pSelReg->u64Base = 0;
2115
2116 /* Attributes. */
2117 if (iSegReg == X86_SREG_CS)
2118 {
2119 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2120 pSelReg->Attr.n.u1DescType = 1;
2121 pSelReg->Attr.n.u2Dpl = 0;
2122 pSelReg->Attr.n.u1Present = 1;
2123 pSelReg->Attr.n.u1Long = fHostInLongMode;
2124 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2125 pSelReg->Attr.n.u1Granularity = 1;
2126 Assert(!pSelReg->Attr.n.u1Unusable);
2127 Assert(!fUnusable);
2128 }
2129 else
2130 {
2131 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2132 pSelReg->Attr.n.u1DescType = 1;
2133 pSelReg->Attr.n.u2Dpl = 0;
2134 pSelReg->Attr.n.u1Present = 1;
2135 pSelReg->Attr.n.u1DefBig = 1;
2136 pSelReg->Attr.n.u1Granularity = 1;
2137 pSelReg->Attr.n.u1Unusable = fUnusable;
2138 }
2139 }
2140
2141 /* FS base. */
2142 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2143 || fHostInLongMode)
2144 {
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2146 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2147 }
2148
2149 /* GS base. */
2150 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2151 || fHostInLongMode)
2152 {
2153 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2154 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2155 }
2156
2157 /* TR. */
2158 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2159 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2160 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2161 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2162 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2163 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2164 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2165 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2166 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2167 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2168 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2169 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2170 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2171
2172 /* LDTR (Warning! do not touch the base and limits here). */
2173 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2174 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2175 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2176 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2177
2178 /* GDTR. */
2179 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2180 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2181 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2182
2183 /* IDTR.*/
2184 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2185 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2186 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2187}
2188
2189
2190/**
2191 * Checks host PDPTes as part of VM-exit.
2192 *
2193 * @param pVCpu The cross context virtual CPU structure.
2194 * @param uExitReason The VM-exit reason (for logging purposes).
2195 */
2196IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2197{
2198 /*
2199 * Check host PDPTEs.
2200 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2201 */
2202 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2203 const char *const pszFailure = "VMX-abort";
2204 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2205
2206 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2207 && !fHostInLongMode)
2208 {
2209 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2210 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2211 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2212 if (RT_SUCCESS(rc))
2213 {
2214 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2215 {
2216 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2217 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2218 { /* likely */ }
2219 else
2220 {
2221 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2222 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2223 }
2224 }
2225 }
2226 else
2227 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2228 }
2229
2230 NOREF(pszFailure);
2231 NOREF(uExitReason);
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/**
2237 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2238 *
2239 * @returns VBox status code.
2240 * @param pVCpu The cross context virtual CPU structure.
2241 * @param pszInstr The VMX instruction name (for logging purposes).
2242 */
2243IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2244{
2245 /*
2246 * Load host MSRs.
2247 * See Intel spec. 27.6 "Loading MSRs".
2248 */
2249 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2250 const char *const pszFailure = "VMX-abort";
2251
2252 /*
2253 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2254 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2255 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2256 */
2257 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2258 if (!cMsrs)
2259 return VINF_SUCCESS;
2260
2261 /*
2262 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2263 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2264 * implementation causes a VMX-abort followed by a triple-fault.
2265 */
2266 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2267 if (fIsMsrCountValid)
2268 { /* likely */ }
2269 else
2270 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2271
2272 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2273 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2274 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2275 if (RT_SUCCESS(rc))
2276 {
2277 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2278 Assert(pMsr);
2279 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2280 {
2281 if ( !pMsr->u32Reserved
2282 && pMsr->u32Msr != MSR_K8_FS_BASE
2283 && pMsr->u32Msr != MSR_K8_GS_BASE
2284 && pMsr->u32Msr != MSR_K6_EFER
2285 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2286 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2287 {
2288 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2289 if (rcStrict == VINF_SUCCESS)
2290 continue;
2291
2292 /*
2293 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2294 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2295 * recording the MSR index in the auxiliary info. field and indicated further by our
2296 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2297 * if possible, or come up with a better, generic solution.
2298 */
2299 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2300 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2301 ? kVmxVDiag_Vmexit_MsrLoadRing3
2302 : kVmxVDiag_Vmexit_MsrLoad;
2303 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2304 }
2305 else
2306 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2307 }
2308 }
2309 else
2310 {
2311 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2312 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2313 }
2314
2315 NOREF(uExitReason);
2316 NOREF(pszFailure);
2317 return VINF_SUCCESS;
2318}
2319
2320
2321/**
2322 * Loads the host state as part of VM-exit.
2323 *
2324 * @returns Strict VBox status code.
2325 * @param pVCpu The cross context virtual CPU structure.
2326 * @param uExitReason The VM-exit reason (for logging purposes).
2327 */
2328IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2329{
2330 /*
2331 * Load host state.
2332 * See Intel spec. 27.5 "Loading Host State".
2333 */
2334 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2335 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2336
2337 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2338 if ( CPUMIsGuestInLongMode(pVCpu)
2339 && !fHostInLongMode)
2340 {
2341 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2342 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2343 }
2344
2345 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2346 iemVmxVmexitLoadHostSegRegs(pVCpu);
2347
2348 /*
2349 * Load host RIP, RSP and RFLAGS.
2350 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2351 */
2352 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2353 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2354 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2355
2356 /* Clear address range monitoring. */
2357 EMMonitorWaitClear(pVCpu);
2358
2359 /* Perform the VMX transition (PGM updates). */
2360 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2361 if (rcStrict == VINF_SUCCESS)
2362 {
2363 /* Check host PDPTEs (only when we've fully switched page tables_. */
2364 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2365 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2366 if (RT_FAILURE(rc))
2367 {
2368 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2369 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2370 }
2371 }
2372 else if (RT_SUCCESS(rcStrict))
2373 {
2374 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2375 uExitReason));
2376 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2377 }
2378 else
2379 {
2380 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2381 return VBOXSTRICTRC_VAL(rcStrict);
2382 }
2383
2384 Assert(rcStrict == VINF_SUCCESS);
2385
2386 /* Load MSRs from the VM-exit auto-load MSR area. */
2387 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2388 if (RT_FAILURE(rc))
2389 {
2390 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2391 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2392 }
2393 return VINF_SUCCESS;
2394}
2395
2396
2397/**
2398 * Gets VM-exit instruction information along with any displacement for an
2399 * instruction VM-exit.
2400 *
2401 * @returns The VM-exit instruction information.
2402 * @param pVCpu The cross context virtual CPU structure.
2403 * @param uExitReason The VM-exit reason.
2404 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2405 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2406 * NULL.
2407 */
2408IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2409{
2410 RTGCPTR GCPtrDisp;
2411 VMXEXITINSTRINFO ExitInstrInfo;
2412 ExitInstrInfo.u = 0;
2413
2414 /*
2415 * Get and parse the ModR/M byte from our decoded opcodes.
2416 */
2417 uint8_t bRm;
2418 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2419 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2420 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2421 {
2422 /*
2423 * ModR/M indicates register addressing.
2424 *
2425 * The primary/secondary register operands are reported in the iReg1 or iReg2
2426 * fields depending on whether it is a read/write form.
2427 */
2428 uint8_t idxReg1;
2429 uint8_t idxReg2;
2430 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2431 {
2432 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2433 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2434 }
2435 else
2436 {
2437 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2438 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2439 }
2440 ExitInstrInfo.All.u2Scaling = 0;
2441 ExitInstrInfo.All.iReg1 = idxReg1;
2442 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2443 ExitInstrInfo.All.fIsRegOperand = 1;
2444 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2445 ExitInstrInfo.All.iSegReg = 0;
2446 ExitInstrInfo.All.iIdxReg = 0;
2447 ExitInstrInfo.All.fIdxRegInvalid = 1;
2448 ExitInstrInfo.All.iBaseReg = 0;
2449 ExitInstrInfo.All.fBaseRegInvalid = 1;
2450 ExitInstrInfo.All.iReg2 = idxReg2;
2451
2452 /* Displacement not applicable for register addressing. */
2453 GCPtrDisp = 0;
2454 }
2455 else
2456 {
2457 /*
2458 * ModR/M indicates memory addressing.
2459 */
2460 uint8_t uScale = 0;
2461 bool fBaseRegValid = false;
2462 bool fIdxRegValid = false;
2463 uint8_t iBaseReg = 0;
2464 uint8_t iIdxReg = 0;
2465 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2466 {
2467 /*
2468 * Parse the ModR/M, displacement for 16-bit addressing mode.
2469 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2470 */
2471 uint16_t u16Disp = 0;
2472 uint8_t const offDisp = offModRm + sizeof(bRm);
2473 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2474 {
2475 /* Displacement without any registers. */
2476 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2477 }
2478 else
2479 {
2480 /* Register (index and base). */
2481 switch (bRm & X86_MODRM_RM_MASK)
2482 {
2483 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2484 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2485 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2486 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2487 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2488 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2489 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2490 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2491 }
2492
2493 /* Register + displacement. */
2494 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2495 {
2496 case 0: break;
2497 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2498 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2499 default:
2500 {
2501 /* Register addressing, handled at the beginning. */
2502 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2503 break;
2504 }
2505 }
2506 }
2507
2508 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2509 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2510 }
2511 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2512 {
2513 /*
2514 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2515 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2516 */
2517 uint32_t u32Disp = 0;
2518 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2519 {
2520 /* Displacement without any registers. */
2521 uint8_t const offDisp = offModRm + sizeof(bRm);
2522 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2523 }
2524 else
2525 {
2526 /* Register (and perhaps scale, index and base). */
2527 uint8_t offDisp = offModRm + sizeof(bRm);
2528 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2529 if (iBaseReg == 4)
2530 {
2531 /* An SIB byte follows the ModR/M byte, parse it. */
2532 uint8_t bSib;
2533 uint8_t const offSib = offModRm + sizeof(bRm);
2534 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2535
2536 /* A displacement may follow SIB, update its offset. */
2537 offDisp += sizeof(bSib);
2538
2539 /* Get the scale. */
2540 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2541
2542 /* Get the index register. */
2543 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2544 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2545
2546 /* Get the base register. */
2547 iBaseReg = bSib & X86_SIB_BASE_MASK;
2548 fBaseRegValid = true;
2549 if (iBaseReg == 5)
2550 {
2551 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2552 {
2553 /* Mod is 0 implies a 32-bit displacement with no base. */
2554 fBaseRegValid = false;
2555 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2556 }
2557 else
2558 {
2559 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2560 iBaseReg = X86_GREG_xBP;
2561 }
2562 }
2563 }
2564
2565 /* Register + displacement. */
2566 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2567 {
2568 case 0: /* Handled above */ break;
2569 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2570 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2571 default:
2572 {
2573 /* Register addressing, handled at the beginning. */
2574 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2575 break;
2576 }
2577 }
2578 }
2579
2580 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2581 }
2582 else
2583 {
2584 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2585
2586 /*
2587 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2588 * See Intel instruction spec. 2.2 "IA-32e Mode".
2589 */
2590 uint64_t u64Disp = 0;
2591 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2592 if (fRipRelativeAddr)
2593 {
2594 /*
2595 * RIP-relative addressing mode.
2596 *
2597 * The displacement is 32-bit signed implying an offset range of +/-2G.
2598 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2599 */
2600 uint8_t const offDisp = offModRm + sizeof(bRm);
2601 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2602 }
2603 else
2604 {
2605 uint8_t offDisp = offModRm + sizeof(bRm);
2606
2607 /*
2608 * Register (and perhaps scale, index and base).
2609 *
2610 * REX.B extends the most-significant bit of the base register. However, REX.B
2611 * is ignored while determining whether an SIB follows the opcode. Hence, we
2612 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2613 *
2614 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2615 */
2616 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2617 if (iBaseReg == 4)
2618 {
2619 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2620 uint8_t bSib;
2621 uint8_t const offSib = offModRm + sizeof(bRm);
2622 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2623
2624 /* Displacement may follow SIB, update its offset. */
2625 offDisp += sizeof(bSib);
2626
2627 /* Get the scale. */
2628 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2629
2630 /* Get the index. */
2631 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2632 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2633
2634 /* Get the base. */
2635 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2636 fBaseRegValid = true;
2637 if (iBaseReg == 5)
2638 {
2639 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2640 {
2641 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2642 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2643 }
2644 else
2645 {
2646 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2647 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2648 }
2649 }
2650 }
2651 iBaseReg |= pVCpu->iem.s.uRexB;
2652
2653 /* Register + displacement. */
2654 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2655 {
2656 case 0: /* Handled above */ break;
2657 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2658 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2659 default:
2660 {
2661 /* Register addressing, handled at the beginning. */
2662 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2663 break;
2664 }
2665 }
2666 }
2667
2668 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2669 }
2670
2671 /*
2672 * The primary or secondary register operand is reported in iReg2 depending
2673 * on whether the primary operand is in read/write form.
2674 */
2675 uint8_t idxReg2;
2676 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2677 {
2678 idxReg2 = bRm & X86_MODRM_RM_MASK;
2679 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2680 idxReg2 |= pVCpu->iem.s.uRexB;
2681 }
2682 else
2683 {
2684 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2685 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2686 idxReg2 |= pVCpu->iem.s.uRexReg;
2687 }
2688 ExitInstrInfo.All.u2Scaling = uScale;
2689 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2690 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2691 ExitInstrInfo.All.fIsRegOperand = 0;
2692 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2693 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2694 ExitInstrInfo.All.iIdxReg = iIdxReg;
2695 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2696 ExitInstrInfo.All.iBaseReg = iBaseReg;
2697 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2698 ExitInstrInfo.All.iReg2 = idxReg2;
2699 }
2700
2701 /*
2702 * Handle exceptions to the norm for certain instructions.
2703 * (e.g. some instructions convey an instruction identity in place of iReg2).
2704 */
2705 switch (uExitReason)
2706 {
2707 case VMX_EXIT_GDTR_IDTR_ACCESS:
2708 {
2709 Assert(VMXINSTRID_IS_VALID(uInstrId));
2710 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2711 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2712 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2713 break;
2714 }
2715
2716 case VMX_EXIT_LDTR_TR_ACCESS:
2717 {
2718 Assert(VMXINSTRID_IS_VALID(uInstrId));
2719 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2720 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2721 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2722 break;
2723 }
2724
2725 case VMX_EXIT_RDRAND:
2726 case VMX_EXIT_RDSEED:
2727 {
2728 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2729 break;
2730 }
2731 }
2732
2733 /* Update displacement and return the constructed VM-exit instruction information field. */
2734 if (pGCPtrDisp)
2735 *pGCPtrDisp = GCPtrDisp;
2736
2737 return ExitInstrInfo.u;
2738}
2739
2740
2741/**
2742 * VMX VM-exit handler.
2743 *
2744 * @returns Strict VBox status code.
2745 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2746 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2747 * triple-fault.
2748 *
2749 * @param pVCpu The cross context virtual CPU structure.
2750 * @param uExitReason The VM-exit reason.
2751 *
2752 * @remarks Make sure VM-exit qualification is updated before calling this
2753 * function!
2754 */
2755IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2756{
2757# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2758 RT_NOREF2(pVCpu, uExitReason);
2759 return VINF_EM_RAW_EMULATE_INSTR;
2760# else
2761 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2762 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2763 | CPUMCTX_EXTRN_EFER /* MSRs */
2764 | CPUMCTX_EXTRN_SYSENTER_MSRS
2765 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2766 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2767 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2768 | CPUMCTX_EXTRN_TR /* Task register */
2769 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2770 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2771
2772 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2773 Assert(pVmcs);
2774
2775 /* Ensure VM-entry interruption information valid bit isn't set. */
2776 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2777
2778 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2779 pVmcs->u32RoExitReason = uExitReason;
2780 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2781 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2782
2783 /*
2784 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2785 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2786 */
2787 {
2788 uint8_t uVector;
2789 uint32_t fFlags;
2790 uint32_t uErrCode;
2791 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2792 if (!fInEventDelivery)
2793 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2794 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2795 }
2796
2797 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2798 Assert(pVmcs->u64RoIoRcx.u == 0);
2799 Assert(pVmcs->u64RoIoRsi.u == 0);
2800 Assert(pVmcs->u64RoIoRdi.u == 0);
2801 Assert(pVmcs->u64RoIoRip.u == 0);
2802
2803 /*
2804 * Save the guest state back into the VMCS.
2805 * We only need to save the state when the VM-entry was successful.
2806 */
2807 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2808 if (!fVmentryFailed)
2809 {
2810 /*
2811 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2812 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2813 *
2814 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2815 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2816 * as guest-CPU state would not been modified. Hence for now, we do this only when
2817 * the VM-entry succeeded.
2818 */
2819 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2820 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2821 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2822 {
2823 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2824 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2825 else
2826 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2827 }
2828
2829 /*
2830 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2831 * occurs in enclave mode/SMM which we don't support yet.
2832 *
2833 * If we ever add support for it, we can pass just the lower bits to the functions
2834 * below, till then an assert should suffice.
2835 */
2836 Assert(!RT_HI_U16(uExitReason));
2837
2838 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2839 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2840 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2841 if (RT_SUCCESS(rc))
2842 { /* likely */ }
2843 else
2844 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2845
2846 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2847 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2848 }
2849 else
2850 {
2851 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2852 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2853 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2854 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2855 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2856 }
2857
2858 /*
2859 * Clear any pending VMX nested-guest force-flags.
2860 * These force-flags have no effect on guest execution and will
2861 * be re-evaluated and setup on the next nested-guest VM-entry.
2862 */
2863 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2864 | VMCPU_FF_VMX_MTF
2865 | VMCPU_FF_VMX_APIC_WRITE
2866 | VMCPU_FF_VMX_INT_WINDOW
2867 | VMCPU_FF_VMX_NMI_WINDOW);
2868
2869 /* Restore the host (outer guest) state. */
2870 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2871 if (RT_SUCCESS(rcStrict))
2872 {
2873 Assert(rcStrict == VINF_SUCCESS);
2874 rcStrict = VINF_VMX_VMEXIT;
2875 }
2876 else
2877 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2878
2879 /* We're no longer in nested-guest execution mode. */
2880 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2881
2882# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2883 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2884 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2885 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2886 if (rcSched != VINF_SUCCESS)
2887 iemSetPassUpStatus(pVCpu, rcSched);
2888# endif
2889 return rcStrict;
2890# endif
2891}
2892
2893
2894/**
2895 * VMX VM-exit handler for VM-exits due to instruction execution.
2896 *
2897 * This is intended for instructions where the caller provides all the relevant
2898 * VM-exit information.
2899 *
2900 * @returns Strict VBox status code.
2901 * @param pVCpu The cross context virtual CPU structure.
2902 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2903 */
2904IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2905{
2906 /*
2907 * For instructions where any of the following fields are not applicable:
2908 * - VM-exit instruction info. is undefined.
2909 * - VM-exit qualification must be cleared.
2910 * - VM-exit guest-linear address is undefined.
2911 * - VM-exit guest-physical address is undefined.
2912 *
2913 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2914 * instruction execution. For VM-exits that are not due to instruction execution this
2915 * field is undefined.
2916 *
2917 * In our implementation in IEM, all undefined fields are generally cleared. However,
2918 * if the caller supplies information (from say the physical CPU directly) it is
2919 * then possible that the undefined fields are not cleared.
2920 *
2921 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2922 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2923 */
2924 Assert(pExitInfo);
2925 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2926 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2927 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2928
2929 /* Update all the relevant fields from the VM-exit instruction information struct. */
2930 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2931 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2932 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2933 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2934 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2935
2936 /* Perform the VM-exit. */
2937 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2938}
2939
2940
2941/**
2942 * VMX VM-exit handler for VM-exits due to instruction execution.
2943 *
2944 * This is intended for instructions that only provide the VM-exit instruction
2945 * length.
2946 *
2947 * @param pVCpu The cross context virtual CPU structure.
2948 * @param uExitReason The VM-exit reason.
2949 * @param cbInstr The instruction length in bytes.
2950 */
2951IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2952{
2953 VMXVEXITINFO ExitInfo;
2954 RT_ZERO(ExitInfo);
2955 ExitInfo.uReason = uExitReason;
2956 ExitInfo.cbInstr = cbInstr;
2957
2958#ifdef VBOX_STRICT
2959 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2960 switch (uExitReason)
2961 {
2962 case VMX_EXIT_INVEPT:
2963 case VMX_EXIT_INVPCID:
2964 case VMX_EXIT_LDTR_TR_ACCESS:
2965 case VMX_EXIT_GDTR_IDTR_ACCESS:
2966 case VMX_EXIT_VMCLEAR:
2967 case VMX_EXIT_VMPTRLD:
2968 case VMX_EXIT_VMPTRST:
2969 case VMX_EXIT_VMREAD:
2970 case VMX_EXIT_VMWRITE:
2971 case VMX_EXIT_VMXON:
2972 case VMX_EXIT_XRSTORS:
2973 case VMX_EXIT_XSAVES:
2974 case VMX_EXIT_RDRAND:
2975 case VMX_EXIT_RDSEED:
2976 case VMX_EXIT_IO_INSTR:
2977 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2978 break;
2979 }
2980#endif
2981
2982 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2983}
2984
2985
2986/**
2987 * VMX VM-exit handler for VM-exits due to instruction execution.
2988 *
2989 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2990 * instruction information and VM-exit qualification fields.
2991 *
2992 * @param pVCpu The cross context virtual CPU structure.
2993 * @param uExitReason The VM-exit reason.
2994 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2995 * @param cbInstr The instruction length in bytes.
2996 *
2997 * @remarks Do not use this for INS/OUTS instruction.
2998 */
2999IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
3000{
3001 VMXVEXITINFO ExitInfo;
3002 RT_ZERO(ExitInfo);
3003 ExitInfo.uReason = uExitReason;
3004 ExitInfo.cbInstr = cbInstr;
3005
3006 /*
3007 * Update the VM-exit qualification field with displacement bytes.
3008 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3009 */
3010 switch (uExitReason)
3011 {
3012 case VMX_EXIT_INVEPT:
3013 case VMX_EXIT_INVPCID:
3014 case VMX_EXIT_INVVPID:
3015 case VMX_EXIT_LDTR_TR_ACCESS:
3016 case VMX_EXIT_GDTR_IDTR_ACCESS:
3017 case VMX_EXIT_VMCLEAR:
3018 case VMX_EXIT_VMPTRLD:
3019 case VMX_EXIT_VMPTRST:
3020 case VMX_EXIT_VMREAD:
3021 case VMX_EXIT_VMWRITE:
3022 case VMX_EXIT_VMXON:
3023 case VMX_EXIT_XRSTORS:
3024 case VMX_EXIT_XSAVES:
3025 case VMX_EXIT_RDRAND:
3026 case VMX_EXIT_RDSEED:
3027 {
3028 /* Construct the VM-exit instruction information. */
3029 RTGCPTR GCPtrDisp;
3030 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3031
3032 /* Update the VM-exit instruction information. */
3033 ExitInfo.InstrInfo.u = uInstrInfo;
3034
3035 /* Update the VM-exit qualification. */
3036 ExitInfo.u64Qual = GCPtrDisp;
3037 break;
3038 }
3039
3040 default:
3041 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3042 break;
3043 }
3044
3045 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3046}
3047
3048
3049/**
3050 * VMX VM-exit handler for VM-exits due to INVLPG.
3051 *
3052 * @returns Strict VBox status code.
3053 * @param pVCpu The cross context virtual CPU structure.
3054 * @param GCPtrPage The guest-linear address of the page being invalidated.
3055 * @param cbInstr The instruction length in bytes.
3056 */
3057IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3058{
3059 VMXVEXITINFO ExitInfo;
3060 RT_ZERO(ExitInfo);
3061 ExitInfo.uReason = VMX_EXIT_INVLPG;
3062 ExitInfo.cbInstr = cbInstr;
3063 ExitInfo.u64Qual = GCPtrPage;
3064 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3065
3066 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3067}
3068
3069
3070/**
3071 * VMX VM-exit handler for VM-exits due to LMSW.
3072 *
3073 * @returns Strict VBox status code.
3074 * @param pVCpu The cross context virtual CPU structure.
3075 * @param uGuestCr0 The current guest CR0.
3076 * @param pu16NewMsw The machine-status word specified in LMSW's source
3077 * operand. This will be updated depending on the VMX
3078 * guest/host CR0 mask if LMSW is not intercepted.
3079 * @param GCPtrEffDst The guest-linear address of the source operand in case
3080 * of a memory operand. For register operand, pass
3081 * NIL_RTGCPTR.
3082 * @param cbInstr The instruction length in bytes.
3083 */
3084IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3085 uint8_t cbInstr)
3086{
3087 /*
3088 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3089 *
3090 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3091 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3092 */
3093 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3094 Assert(pVmcs);
3095 Assert(pu16NewMsw);
3096
3097 bool fIntercept = false;
3098 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3099 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3100
3101 /*
3102 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3103 * CR0.PE case first, before the rest of the bits in the MSW.
3104 *
3105 * If CR0.PE is owned by the host and CR0.PE differs between the
3106 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3107 */
3108 if ( (fGstHostMask & X86_CR0_PE)
3109 && (*pu16NewMsw & X86_CR0_PE)
3110 && !(fReadShadow & X86_CR0_PE))
3111 fIntercept = true;
3112
3113 /*
3114 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3115 * bits differ between the MSW (source operand) and the read-shadow, we must
3116 * cause a VM-exit.
3117 */
3118 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3119 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3120 fIntercept = true;
3121
3122 if (fIntercept)
3123 {
3124 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3125
3126 VMXVEXITINFO ExitInfo;
3127 RT_ZERO(ExitInfo);
3128 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3129 ExitInfo.cbInstr = cbInstr;
3130
3131 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3132 if (fMemOperand)
3133 {
3134 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3135 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3136 }
3137
3138 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3139 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3140 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3141 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3142
3143 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3144 }
3145
3146 /*
3147 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3148 * CR0 guest/host mask must be left unmodified.
3149 *
3150 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3151 */
3152 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3153 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3154
3155 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3156}
3157
3158
3159/**
3160 * VMX VM-exit handler for VM-exits due to CLTS.
3161 *
3162 * @returns Strict VBox status code.
3163 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3164 * VM-exit but must not modify the guest CR0.TS bit.
3165 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3166 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3167 * CR0 fixed bits in VMX operation).
3168 * @param pVCpu The cross context virtual CPU structure.
3169 * @param cbInstr The instruction length in bytes.
3170 */
3171IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3172{
3173 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3174 Assert(pVmcs);
3175
3176 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3177 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3178
3179 /*
3180 * If CR0.TS is owned by the host:
3181 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3182 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3183 * CLTS instruction completes without clearing CR0.TS.
3184 *
3185 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3186 */
3187 if (fGstHostMask & X86_CR0_TS)
3188 {
3189 if (fReadShadow & X86_CR0_TS)
3190 {
3191 Log2(("clts: Guest intercept -> VM-exit\n"));
3192
3193 VMXVEXITINFO ExitInfo;
3194 RT_ZERO(ExitInfo);
3195 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3196 ExitInfo.cbInstr = cbInstr;
3197 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3198 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3199 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3200 }
3201
3202 return VINF_VMX_MODIFIES_BEHAVIOR;
3203 }
3204
3205 /*
3206 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3207 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3208 */
3209 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3210}
3211
3212
3213/**
3214 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3215 * (CR0/CR4 write).
3216 *
3217 * @returns Strict VBox status code.
3218 * @param pVCpu The cross context virtual CPU structure.
3219 * @param iCrReg The control register (either CR0 or CR4).
3220 * @param uGuestCrX The current guest CR0/CR4.
3221 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3222 * if no VM-exit is caused.
3223 * @param iGReg The general register from which the CR0/CR4 value is
3224 * being loaded.
3225 * @param cbInstr The instruction length in bytes.
3226 */
3227IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3228 uint8_t cbInstr)
3229{
3230 Assert(puNewCrX);
3231 Assert(iCrReg == 0 || iCrReg == 4);
3232 Assert(iGReg < X86_GREG_COUNT);
3233
3234 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3235 Assert(pVmcs);
3236
3237 uint64_t uGuestCrX;
3238 uint64_t fGstHostMask;
3239 uint64_t fReadShadow;
3240 if (iCrReg == 0)
3241 {
3242 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3243 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3244 fGstHostMask = pVmcs->u64Cr0Mask.u;
3245 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3246 }
3247 else
3248 {
3249 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3250 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3251 fGstHostMask = pVmcs->u64Cr4Mask.u;
3252 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3253 }
3254
3255 /*
3256 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3257 * corresponding bits differ between the source operand and the read-shadow,
3258 * we must cause a VM-exit.
3259 *
3260 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3261 */
3262 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3263 {
3264 Assert(fGstHostMask != 0);
3265 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3266
3267 VMXVEXITINFO ExitInfo;
3268 RT_ZERO(ExitInfo);
3269 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3270 ExitInfo.cbInstr = cbInstr;
3271 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3272 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3273 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3274 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3275 }
3276
3277 /*
3278 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3279 * must not be modified the instruction.
3280 *
3281 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3282 */
3283 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3284
3285 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3286}
3287
3288
3289/**
3290 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3291 *
3292 * @returns VBox strict status code.
3293 * @param pVCpu The cross context virtual CPU structure.
3294 * @param iGReg The general register to which the CR3 value is being stored.
3295 * @param cbInstr The instruction length in bytes.
3296 */
3297IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3298{
3299 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3300 Assert(pVmcs);
3301 Assert(iGReg < X86_GREG_COUNT);
3302 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3303
3304 /*
3305 * If the CR3-store exiting control is set, we must cause a VM-exit.
3306 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3307 */
3308 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3309 {
3310 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3311
3312 VMXVEXITINFO ExitInfo;
3313 RT_ZERO(ExitInfo);
3314 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3315 ExitInfo.cbInstr = cbInstr;
3316 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3317 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3318 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3319 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3320 }
3321
3322 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3323}
3324
3325
3326/**
3327 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3328 *
3329 * @returns VBox strict status code.
3330 * @param pVCpu The cross context virtual CPU structure.
3331 * @param uNewCr3 The new CR3 value.
3332 * @param iGReg The general register from which the CR3 value is being
3333 * loaded.
3334 * @param cbInstr The instruction length in bytes.
3335 */
3336IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3337{
3338 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3339 Assert(pVmcs);
3340 Assert(iGReg < X86_GREG_COUNT);
3341
3342 /*
3343 * If the CR3-load exiting control is set and the new CR3 value does not
3344 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3345 *
3346 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3347 */
3348 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3349 {
3350 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3351 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3352
3353 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3354 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3355 if (!fIntercept)
3356 {
3357 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3358 {
3359 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3360 if (uNewCr3 != uCr3TargetValue)
3361 {
3362 fIntercept = true;
3363 break;
3364 }
3365 }
3366 }
3367
3368 if (fIntercept)
3369 {
3370 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3371
3372 VMXVEXITINFO ExitInfo;
3373 RT_ZERO(ExitInfo);
3374 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3375 ExitInfo.cbInstr = cbInstr;
3376 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3377 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3378 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3379 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3380 }
3381 }
3382
3383 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3384}
3385
3386
3387/**
3388 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3389 *
3390 * @returns VBox strict status code.
3391 * @param pVCpu The cross context virtual CPU structure.
3392 * @param iGReg The general register to which the CR8 value is being stored.
3393 * @param cbInstr The instruction length in bytes.
3394 */
3395IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3396{
3397 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3398 Assert(pVmcs);
3399 Assert(iGReg < X86_GREG_COUNT);
3400
3401 /*
3402 * If the CR8-store exiting control is set, we must cause a VM-exit.
3403 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3404 */
3405 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3406 {
3407 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3408
3409 VMXVEXITINFO ExitInfo;
3410 RT_ZERO(ExitInfo);
3411 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3412 ExitInfo.cbInstr = cbInstr;
3413 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3414 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3415 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3416 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3417 }
3418
3419 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3420}
3421
3422
3423/**
3424 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3425 *
3426 * @returns VBox strict status code.
3427 * @param pVCpu The cross context virtual CPU structure.
3428 * @param iGReg The general register from which the CR8 value is being
3429 * loaded.
3430 * @param cbInstr The instruction length in bytes.
3431 */
3432IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3433{
3434 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3435 Assert(pVmcs);
3436 Assert(iGReg < X86_GREG_COUNT);
3437
3438 /*
3439 * If the CR8-load exiting control is set, we must cause a VM-exit.
3440 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3441 */
3442 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3443 {
3444 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3445
3446 VMXVEXITINFO ExitInfo;
3447 RT_ZERO(ExitInfo);
3448 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3449 ExitInfo.cbInstr = cbInstr;
3450 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3451 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3452 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3453 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3454 }
3455
3456 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3457}
3458
3459
3460/**
3461 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3462 * GReg,DRx' (DRx read).
3463 *
3464 * @returns VBox strict status code.
3465 * @param pVCpu The cross context virtual CPU structure.
3466 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3467 * VMXINSTRID_MOV_FROM_DRX).
3468 * @param iDrReg The debug register being accessed.
3469 * @param iGReg The general register to/from which the DRx value is being
3470 * store/loaded.
3471 * @param cbInstr The instruction length in bytes.
3472 */
3473IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3474 uint8_t cbInstr)
3475{
3476 Assert(iDrReg <= 7);
3477 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3478 Assert(iGReg < X86_GREG_COUNT);
3479
3480 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3481 Assert(pVmcs);
3482
3483 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3484 {
3485 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3486 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3487 VMXVEXITINFO ExitInfo;
3488 RT_ZERO(ExitInfo);
3489 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3490 ExitInfo.cbInstr = cbInstr;
3491 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3492 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3493 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3494 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3495 }
3496
3497 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3498}
3499
3500
3501/**
3502 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3503 *
3504 * @returns VBox strict status code.
3505 * @param pVCpu The cross context virtual CPU structure.
3506 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3507 * VMXINSTRID_IO_OUT).
3508 * @param u16Port The I/O port being accessed.
3509 * @param fImm Whether the I/O port was encoded using an immediate operand
3510 * or the implicit DX register.
3511 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3512 * @param cbInstr The instruction length in bytes.
3513 */
3514IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3515 uint8_t cbInstr)
3516{
3517 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3518 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3519
3520 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3521 if (fIntercept)
3522 {
3523 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3524 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3525 VMXVEXITINFO ExitInfo;
3526 RT_ZERO(ExitInfo);
3527 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3528 ExitInfo.cbInstr = cbInstr;
3529 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3530 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3531 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3532 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3533 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3534 }
3535
3536 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3537}
3538
3539
3540/**
3541 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3542 *
3543 * @returns VBox strict status code.
3544 * @param pVCpu The cross context virtual CPU structure.
3545 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3546 * VMXINSTRID_IO_OUTS).
3547 * @param u16Port The I/O port being accessed.
3548 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3549 * @param fRep Whether the instruction has a REP prefix or not.
3550 * @param ExitInstrInfo The VM-exit instruction info. field.
3551 * @param cbInstr The instruction length in bytes.
3552 */
3553IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3554 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3555{
3556 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3557 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3558 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3559 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3560 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3561
3562 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3563 if (fIntercept)
3564 {
3565 /*
3566 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3567 */
3568 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3569 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3570 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3571 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3572 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3573
3574 uint32_t uDirection;
3575 uint64_t uGuestLinearAddr;
3576 if (uInstrId == VMXINSTRID_IO_INS)
3577 {
3578 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3579 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3580 }
3581 else
3582 {
3583 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3584 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3585 }
3586
3587 /*
3588 * If the segment is ununsable, the guest-linear address in undefined.
3589 * We shall clear it for consistency.
3590 *
3591 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3592 */
3593 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3594 uGuestLinearAddr = 0;
3595
3596 VMXVEXITINFO ExitInfo;
3597 RT_ZERO(ExitInfo);
3598 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3599 ExitInfo.cbInstr = cbInstr;
3600 ExitInfo.InstrInfo = ExitInstrInfo;
3601 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3602 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3603 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3604 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3605 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3606 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3607 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3608 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3609 }
3610
3611 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3612}
3613
3614
3615/**
3616 * VMX VM-exit handler for VM-exits due to MWAIT.
3617 *
3618 * @returns VBox strict status code.
3619 * @param pVCpu The cross context virtual CPU structure.
3620 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3621 * @param cbInstr The instruction length in bytes.
3622 */
3623IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3624{
3625 VMXVEXITINFO ExitInfo;
3626 RT_ZERO(ExitInfo);
3627 ExitInfo.uReason = VMX_EXIT_MWAIT;
3628 ExitInfo.cbInstr = cbInstr;
3629 ExitInfo.u64Qual = fMonitorHwArmed;
3630 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3631}
3632
3633
3634/**
3635 * VMX VM-exit handler for VM-exits due to PAUSE.
3636 *
3637 * @returns VBox strict status code.
3638 * @param pVCpu The cross context virtual CPU structure.
3639 * @param cbInstr The instruction length in bytes.
3640 */
3641IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3642{
3643 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3644 Assert(pVmcs);
3645
3646 /*
3647 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3648 * "PAUSE-loop exiting" control.
3649 *
3650 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3651 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3652 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3653 * a VM-exit.
3654 *
3655 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3656 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3657 */
3658 bool fIntercept = false;
3659 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3660 fIntercept = true;
3661 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3662 && pVCpu->iem.s.uCpl == 0)
3663 {
3664 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3665
3666 /*
3667 * A previous-PAUSE-tick value of 0 is used to identify the first time
3668 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3669 * consider this to be the first execution of PAUSE in a loop according
3670 * to the Intel.
3671 *
3672 * All subsequent records for the previous-PAUSE-tick we ensure that it
3673 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3674 */
3675 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3676 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3677 uint64_t const uTick = TMCpuTickGet(pVCpu);
3678 uint32_t const uPleGap = pVmcs->u32PleGap;
3679 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3680 if ( *puPrevPauseTick == 0
3681 || uTick - *puPrevPauseTick > uPleGap)
3682 *puFirstPauseLoopTick = uTick;
3683 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3684 fIntercept = true;
3685
3686 *puPrevPauseTick = uTick | 1;
3687 }
3688
3689 if (fIntercept)
3690 {
3691 VMXVEXITINFO ExitInfo;
3692 RT_ZERO(ExitInfo);
3693 ExitInfo.uReason = VMX_EXIT_PAUSE;
3694 ExitInfo.cbInstr = cbInstr;
3695 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3696 }
3697
3698 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3699}
3700
3701
3702/**
3703 * VMX VM-exit handler for VM-exits due to task switches.
3704 *
3705 * @returns VBox strict status code.
3706 * @param pVCpu The cross context virtual CPU structure.
3707 * @param enmTaskSwitch The cause of the task switch.
3708 * @param SelNewTss The selector of the new TSS.
3709 * @param cbInstr The instruction length in bytes.
3710 */
3711IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3712{
3713 /*
3714 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3715 *
3716 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3717 * instruction or delivery of the exception generated by one of these instructions
3718 * lead to a task switch through a task gate in the IDT, we need to provide the
3719 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3720 * leaves the VM-exit instruction length field undefined.
3721 *
3722 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3723 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3724 */
3725 Assert(cbInstr <= 15);
3726
3727 uint8_t uType;
3728 switch (enmTaskSwitch)
3729 {
3730 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3731 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3732 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3733 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3734 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3735 }
3736
3737 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3738 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3739 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3740 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3741 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3742}
3743
3744
3745/**
3746 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3747 *
3748 * @returns VBox strict status code.
3749 * @param pVCpu The cross context virtual CPU structure.
3750 */
3751IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3752{
3753 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3754 Assert(pVmcs);
3755
3756 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3757 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3758 {
3759 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3760 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3761
3762 /*
3763 * Calculate the current VMX-preemption timer value.
3764 * Only if the value has reached zero, we cause the VM-exit.
3765 */
3766 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3767 if (!uPreemptTimer)
3768 {
3769 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3770 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3771 pVmcs->u32PreemptTimer = 0;
3772
3773 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3774 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3775 }
3776 }
3777
3778 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3779}
3780
3781
3782/**
3783 * VMX VM-exit handler for VM-exits due to external interrupts.
3784 *
3785 * @returns VBox strict status code.
3786 * @param pVCpu The cross context virtual CPU structure.
3787 * @param uVector The external interrupt vector (pass 0 if the interrupt
3788 * is still pending since we typically won't know the
3789 * vector).
3790 * @param fIntPending Whether the external interrupt is pending or
3791 * acknowledged in the interrupt controller.
3792 */
3793IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3794{
3795 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3796 Assert(pVmcs);
3797 Assert(fIntPending || uVector == 0);
3798
3799 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3800 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3801 * functions require prior checking of a blanket intercept and which don't.
3802 * It is better for the caller to check a blanket intercept performance wise
3803 * than making a function call. Leaving this as a todo because it is more
3804 * a performance issue. */
3805
3806 /* The VM-exit is subject to "External interrupt exiting" being set. */
3807 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3808 {
3809 if (fIntPending)
3810 {
3811 /*
3812 * If the interrupt is pending and we don't need to acknowledge the
3813 * interrupt on VM-exit, cause the VM-exit immediately.
3814 *
3815 * See Intel spec 25.2 "Other Causes Of VM Exits".
3816 */
3817 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3818 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3819
3820 /*
3821 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3822 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3823 * acknowledged that the interrupt has been consumed.
3824 */
3825 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3826 }
3827
3828 /*
3829 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3830 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3831 * all set, we cause the VM-exit now. We need to record the external interrupt that
3832 * just occurred in the VM-exit interruption information field.
3833 *
3834 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3835 */
3836 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3837 {
3838 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3839 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3840 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3841 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3842 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3843 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3844 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3845 }
3846 }
3847
3848 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3849}
3850
3851
3852/**
3853 * VMX VM-exit handler for VM-exits due to NMIs.
3854 *
3855 * @returns VBox strict status code.
3856 * @param pVCpu The cross context virtual CPU structure.
3857 *
3858 * @remarks This function might import externally kept DR6 if necessary.
3859 */
3860IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3861{
3862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3863 Assert(pVmcs);
3864 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3865 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3866 NOREF(pVmcs);
3867 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3868}
3869
3870
3871/**
3872 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3873 *
3874 * @returns VBox strict status code.
3875 * @param pVCpu The cross context virtual CPU structure.
3876 * @param uVector The SIPI vector.
3877 */
3878IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3879{
3880 iemVmxVmcsSetExitQual(pVCpu, uVector);
3881 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3882}
3883
3884
3885/**
3886 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3887 * an event.
3888 *
3889 * @returns VBox strict status code.
3890 * @param pVCpu The cross context virtual CPU structure.
3891 */
3892IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3893{
3894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3895 Assert(pVmcs);
3896
3897 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3898 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3899 {
3900 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3901 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3902 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3903 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3904 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3905 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3906 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3907 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3908 iemVmxVmcsSetExitQual(pVCpu, 0);
3909 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3910
3911 /*
3912 * A VM-exit is not considered to occur during event delivery when the original
3913 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3914 * using the exception bitmap).
3915 *
3916 * Therefore, we must clear the original event from the IDT-vectoring fields which
3917 * would've been recorded before causing the VM-exit.
3918 *
3919 * 27.2.3 "Information for VM Exits During Event Delivery"
3920 */
3921 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3922 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3923
3924 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3925 }
3926
3927 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3928}
3929
3930
3931/**
3932 * VMX VM-exit handler for VM-exits due to delivery of an event.
3933 *
3934 * @returns VBox strict status code.
3935 * @param pVCpu The cross context virtual CPU structure.
3936 * @param uVector The interrupt / exception vector.
3937 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3938 * @param uErrCode The error code associated with the event.
3939 * @param uCr2 The CR2 value in case of a \#PF exception.
3940 * @param cbInstr The instruction length in bytes.
3941 */
3942IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3943 uint8_t cbInstr)
3944{
3945 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3946 Assert(pVmcs);
3947
3948 /*
3949 * If the event is being injected as part of VM-entry, it isn't subject to event
3950 * intercepts in the nested-guest. However, secondary exceptions that occur during
3951 * injection of any event -are- subject to event interception.
3952 *
3953 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3954 */
3955 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3956 {
3957 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
3958 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
3959 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3960 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
3961 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
3962 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
3963 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
3964 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
3965 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
3966
3967 /*
3968 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3969 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3970 *
3971 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3972 */
3973 if ( uVector == X86_XCPT_NMI
3974 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3975 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3976 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3977 else
3978 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3979
3980 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3981 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3982 }
3983
3984 /*
3985 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3986 * If not, the caller will continue delivery of the external interrupt as it would
3987 * normally. The interrupt is no longer pending in the interrupt controller at this
3988 * point.
3989 */
3990 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3991 {
3992 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3993 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3994 }
3995
3996 /*
3997 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3998 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3999 */
4000 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4001 bool fIntercept = false;
4002 bool fIsHwXcpt = false;
4003 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4004 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4005 {
4006 fIsHwXcpt = true;
4007
4008 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4009 if (uVector == X86_XCPT_NMI)
4010 {
4011 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
4012 fIntercept = true;
4013 }
4014 else
4015 {
4016 /* Page-faults are subject to masking using its error code. */
4017 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4018 if (uVector == X86_XCPT_PF)
4019 {
4020 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4021 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4022 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4023 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4024 }
4025
4026 /* Consult the exception bitmap for all other hardware exceptions. */
4027 Assert(uVector <= X86_XCPT_LAST);
4028 if (fXcptBitmap & RT_BIT(uVector))
4029 fIntercept = true;
4030 }
4031 }
4032 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4033
4034 /*
4035 * Now that we've determined whether the software interrupt or hardware exception
4036 * causes a VM-exit, we need to construct the relevant VM-exit information and
4037 * cause the VM-exit.
4038 */
4039 if (fIntercept)
4040 {
4041 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4042
4043 /* Construct the rest of the event related information fields and cause the VM-exit. */
4044 uint64_t uExitQual = 0;
4045 if (fIsHwXcpt)
4046 {
4047 if (uVector == X86_XCPT_PF)
4048 {
4049 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4050 uExitQual = uCr2;
4051 }
4052 else if (uVector == X86_XCPT_DB)
4053 {
4054 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4055 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4056 }
4057 }
4058
4059 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4060 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4061 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4062 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4063 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4064 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4065 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4066 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4067 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4068 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4069 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4070
4071 /*
4072 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4073 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4074 * length.
4075 */
4076 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4077 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4078 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4079 else
4080 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4081
4082 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4083 }
4084
4085 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4086}
4087
4088
4089/**
4090 * VMX VM-exit handler for VM-exits due to a triple fault.
4091 *
4092 * @returns VBox strict status code.
4093 * @param pVCpu The cross context virtual CPU structure.
4094 */
4095IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4096{
4097 /*
4098 * A VM-exit is not considered to occur during event delivery when the original
4099 * event results in a triple-fault.
4100 *
4101 * Therefore, we must clear the original event from the IDT-vectoring fields which
4102 * would've been recorded before causing the VM-exit.
4103 *
4104 * 27.2.3 "Information for VM Exits During Event Delivery"
4105 */
4106 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4107 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4108
4109 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4110}
4111
4112
4113/**
4114 * VMX VM-exit handler for APIC-accesses.
4115 *
4116 * @param pVCpu The cross context virtual CPU structure.
4117 * @param offAccess The offset of the register being accessed.
4118 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4119 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4120 */
4121IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4122{
4123 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4124
4125 VMXAPICACCESS enmAccess;
4126 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4127 if (fInEventDelivery)
4128 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4129 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4130 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4131 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4132 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4133 else
4134 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4135
4136 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4137 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4138 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4139 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4140}
4141
4142
4143/**
4144 * VMX VM-exit handler for APIC-write VM-exits.
4145 *
4146 * @param pVCpu The cross context virtual CPU structure.
4147 * @param offApic The write to the virtual-APIC page offset that caused this
4148 * VM-exit.
4149 */
4150IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4151{
4152 Assert(offApic < XAPIC_OFF_END + 4);
4153
4154 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4155 offApic &= UINT16_C(0xfff);
4156 iemVmxVmcsSetExitQual(pVCpu, offApic);
4157 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4158}
4159
4160
4161/**
4162 * VMX VM-exit handler for virtualized-EOIs.
4163 *
4164 * @param pVCpu The cross context virtual CPU structure.
4165 */
4166IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4167{
4168 iemVmxVmcsSetExitQual(pVCpu, uVector);
4169 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4170}
4171
4172
4173/**
4174 * Sets virtual-APIC write emulation as pending.
4175 *
4176 * @param pVCpu The cross context virtual CPU structure.
4177 * @param offApic The offset in the virtual-APIC page that was written.
4178 */
4179DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4180{
4181 Assert(offApic < XAPIC_OFF_END + 4);
4182
4183 /*
4184 * Record the currently updated APIC offset, as we need this later for figuring
4185 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4186 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4187 */
4188 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4189
4190 /*
4191 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4192 * virtualization or APIC-write emulation).
4193 */
4194 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4195 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4196}
4197
4198
4199/**
4200 * Clears any pending virtual-APIC write emulation.
4201 *
4202 * @returns The virtual-APIC offset that was written before clearing it.
4203 * @param pVCpu The cross context virtual CPU structure.
4204 */
4205DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4206{
4207 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4208 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4209 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4210 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4211 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4212 return offVirtApicWrite;
4213}
4214
4215
4216/**
4217 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4218 *
4219 * @returns The register from the virtual-APIC page.
4220 * @param pVCpu The cross context virtual CPU structure.
4221 * @param offReg The offset of the register being read.
4222 */
4223IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4224{
4225 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4226 Assert(pVmcs);
4227
4228 uint32_t uReg;
4229 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4230 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4231 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4232 if (RT_FAILURE(rc))
4233 {
4234 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4235 GCPhysVirtApic));
4236 uReg = 0;
4237 }
4238 return uReg;
4239}
4240
4241
4242/**
4243 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4244 *
4245 * @returns The register from the virtual-APIC page.
4246 * @param pVCpu The cross context virtual CPU structure.
4247 * @param offReg The offset of the register being read.
4248 */
4249IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4250{
4251 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4252 Assert(pVmcs);
4253
4254 uint64_t uReg;
4255 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4256 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4257 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4258 if (RT_FAILURE(rc))
4259 {
4260 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4261 GCPhysVirtApic));
4262 uReg = 0;
4263 }
4264 return uReg;
4265}
4266
4267
4268/**
4269 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4270 *
4271 * @param pVCpu The cross context virtual CPU structure.
4272 * @param offReg The offset of the register being written.
4273 * @param uReg The register value to write.
4274 */
4275IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4276{
4277 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4278 Assert(pVmcs);
4279 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4280 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4281 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4282 if (RT_FAILURE(rc))
4283 {
4284 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4285 GCPhysVirtApic));
4286 }
4287}
4288
4289
4290/**
4291 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4292 *
4293 * @param pVCpu The cross context virtual CPU structure.
4294 * @param offReg The offset of the register being written.
4295 * @param uReg The register value to write.
4296 */
4297IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4298{
4299 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4300 Assert(pVmcs);
4301 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4302 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4303 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4304 if (RT_FAILURE(rc))
4305 {
4306 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4307 GCPhysVirtApic));
4308 }
4309}
4310
4311
4312/**
4313 * Sets the vector in a virtual-APIC 256-bit sparse register.
4314 *
4315 * @param pVCpu The cross context virtual CPU structure.
4316 * @param offReg The offset of the 256-bit spare register.
4317 * @param uVector The vector to set.
4318 *
4319 * @remarks This is based on our APIC device code.
4320 */
4321IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4322{
4323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4324 Assert(pVmcs);
4325 uint32_t uReg;
4326 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4327 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4328 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4329 if (RT_SUCCESS(rc))
4330 {
4331 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4332 uReg |= RT_BIT(idxVectorBit);
4333 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4334 if (RT_FAILURE(rc))
4335 {
4336 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4337 uVector, offReg, GCPhysVirtApic));
4338 }
4339 }
4340 else
4341 {
4342 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4343 uVector, offReg, GCPhysVirtApic));
4344 }
4345}
4346
4347
4348/**
4349 * Clears the vector in a virtual-APIC 256-bit sparse register.
4350 *
4351 * @param pVCpu The cross context virtual CPU structure.
4352 * @param offReg The offset of the 256-bit spare register.
4353 * @param uVector The vector to clear.
4354 *
4355 * @remarks This is based on our APIC device code.
4356 */
4357IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4358{
4359 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4360 Assert(pVmcs);
4361 uint32_t uReg;
4362 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4363 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4364 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4365 if (RT_SUCCESS(rc))
4366 {
4367 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4368 uReg &= ~RT_BIT(idxVectorBit);
4369 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4370 if (RT_FAILURE(rc))
4371 {
4372 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4373 uVector, offReg, GCPhysVirtApic));
4374 }
4375 }
4376 else
4377 {
4378 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4379 uVector, offReg, GCPhysVirtApic));
4380 }
4381}
4382
4383
4384/**
4385 * Checks if a memory access to the APIC-access page must causes an APIC-access
4386 * VM-exit.
4387 *
4388 * @param pVCpu The cross context virtual CPU structure.
4389 * @param offAccess The offset of the register being accessed.
4390 * @param cbAccess The size of the access in bytes.
4391 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4392 * IEM_ACCESS_TYPE_WRITE).
4393 *
4394 * @remarks This must not be used for MSR-based APIC-access page accesses!
4395 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4396 */
4397IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4398{
4399 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4400 Assert(pVmcs);
4401 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4402
4403 /*
4404 * We must cause a VM-exit if any of the following are true:
4405 * - TPR shadowing isn't active.
4406 * - The access size exceeds 32-bits.
4407 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4408 *
4409 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4410 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4411 */
4412 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4413 || cbAccess > sizeof(uint32_t)
4414 || ((offAccess + cbAccess - 1) & 0xc)
4415 || offAccess >= XAPIC_OFF_END + 4)
4416 return true;
4417
4418 /*
4419 * If the access is part of an operation where we have already
4420 * virtualized a virtual-APIC write, we must cause a VM-exit.
4421 */
4422 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4423 return true;
4424
4425 /*
4426 * Check write accesses to the APIC-access page that cause VM-exits.
4427 */
4428 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4429 {
4430 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4431 {
4432 /*
4433 * With APIC-register virtualization, a write access to any of the
4434 * following registers are virtualized. Accessing any other register
4435 * causes a VM-exit.
4436 */
4437 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4438 switch (offAlignedAccess)
4439 {
4440 case XAPIC_OFF_ID:
4441 case XAPIC_OFF_TPR:
4442 case XAPIC_OFF_EOI:
4443 case XAPIC_OFF_LDR:
4444 case XAPIC_OFF_DFR:
4445 case XAPIC_OFF_SVR:
4446 case XAPIC_OFF_ESR:
4447 case XAPIC_OFF_ICR_LO:
4448 case XAPIC_OFF_ICR_HI:
4449 case XAPIC_OFF_LVT_TIMER:
4450 case XAPIC_OFF_LVT_THERMAL:
4451 case XAPIC_OFF_LVT_PERF:
4452 case XAPIC_OFF_LVT_LINT0:
4453 case XAPIC_OFF_LVT_LINT1:
4454 case XAPIC_OFF_LVT_ERROR:
4455 case XAPIC_OFF_TIMER_ICR:
4456 case XAPIC_OFF_TIMER_DCR:
4457 break;
4458 default:
4459 return true;
4460 }
4461 }
4462 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4463 {
4464 /*
4465 * With virtual-interrupt delivery, a write access to any of the
4466 * following registers are virtualized. Accessing any other register
4467 * causes a VM-exit.
4468 *
4469 * Note! The specification does not allow writing to offsets in-between
4470 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4471 */
4472 switch (offAccess)
4473 {
4474 case XAPIC_OFF_TPR:
4475 case XAPIC_OFF_EOI:
4476 case XAPIC_OFF_ICR_LO:
4477 break;
4478 default:
4479 return true;
4480 }
4481 }
4482 else
4483 {
4484 /*
4485 * Without APIC-register virtualization or virtual-interrupt delivery,
4486 * only TPR accesses are virtualized.
4487 */
4488 if (offAccess == XAPIC_OFF_TPR)
4489 { /* likely */ }
4490 else
4491 return true;
4492 }
4493 }
4494 else
4495 {
4496 /*
4497 * Check read accesses to the APIC-access page that cause VM-exits.
4498 */
4499 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4500 {
4501 /*
4502 * With APIC-register virtualization, a read access to any of the
4503 * following registers are virtualized. Accessing any other register
4504 * causes a VM-exit.
4505 */
4506 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4507 switch (offAlignedAccess)
4508 {
4509 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4510 case XAPIC_OFF_ID:
4511 case XAPIC_OFF_VERSION:
4512 case XAPIC_OFF_TPR:
4513 case XAPIC_OFF_EOI:
4514 case XAPIC_OFF_LDR:
4515 case XAPIC_OFF_DFR:
4516 case XAPIC_OFF_SVR:
4517 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4518 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4519 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4520 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4521 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4522 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4523 case XAPIC_OFF_ESR:
4524 case XAPIC_OFF_ICR_LO:
4525 case XAPIC_OFF_ICR_HI:
4526 case XAPIC_OFF_LVT_TIMER:
4527 case XAPIC_OFF_LVT_THERMAL:
4528 case XAPIC_OFF_LVT_PERF:
4529 case XAPIC_OFF_LVT_LINT0:
4530 case XAPIC_OFF_LVT_LINT1:
4531 case XAPIC_OFF_LVT_ERROR:
4532 case XAPIC_OFF_TIMER_ICR:
4533 case XAPIC_OFF_TIMER_DCR:
4534 break;
4535 default:
4536 return true;
4537 }
4538 }
4539 else
4540 {
4541 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4542 if (offAccess == XAPIC_OFF_TPR)
4543 { /* likely */ }
4544 else
4545 return true;
4546 }
4547 }
4548
4549 /* The APIC-access is virtualized, does not cause a VM-exit. */
4550 return false;
4551}
4552
4553
4554/**
4555 * Virtualizes a memory-based APIC-access where the address is not used to access
4556 * memory.
4557 *
4558 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4559 * page-faults but do not use the address to access memory.
4560 *
4561 * @param pVCpu The cross context virtual CPU structure.
4562 * @param pGCPhysAccess Pointer to the guest-physical address used.
4563 */
4564IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4565{
4566 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4567 Assert(pVmcs);
4568 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4569 Assert(pGCPhysAccess);
4570
4571 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4572 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4573 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4574
4575 if (GCPhysAccess == GCPhysApic)
4576 {
4577 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4578 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4579 uint16_t const cbAccess = 1;
4580 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4581 if (fIntercept)
4582 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4583
4584 *pGCPhysAccess = GCPhysApic | offAccess;
4585 return VINF_VMX_MODIFIES_BEHAVIOR;
4586 }
4587
4588 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4589}
4590
4591
4592/**
4593 * Virtualizes a memory-based APIC-access.
4594 *
4595 * @returns VBox strict status code.
4596 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4597 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4598 *
4599 * @param pVCpu The cross context virtual CPU structure.
4600 * @param offAccess The offset of the register being accessed (within the
4601 * APIC-access page).
4602 * @param cbAccess The size of the access in bytes.
4603 * @param pvData Pointer to the data being written or where to store the data
4604 * being read.
4605 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4606 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4607 */
4608IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4609 uint32_t fAccess)
4610{
4611 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4612 Assert(pVmcs);
4613 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4614 Assert(pvData);
4615 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4616 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4617 || (fAccess & IEM_ACCESS_INSTRUCTION));
4618
4619 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4620 if (fIntercept)
4621 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4622
4623 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4624 {
4625 /*
4626 * A write access to the APIC-access page that is virtualized (rather than
4627 * causing a VM-exit) writes data to the virtual-APIC page.
4628 */
4629 uint32_t const u32Data = *(uint32_t *)pvData;
4630 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4631
4632 /*
4633 * Record the currently updated APIC offset, as we need this later for figuring
4634 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4635 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4636 *
4637 * After completion of the current operation, we need to perform TPR virtualization,
4638 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4639 *
4640 * The current operation may be a REP-prefixed string instruction, execution of any
4641 * other instruction, or delivery of an event through the IDT.
4642 *
4643 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4644 * performed now but later after completion of the current operation.
4645 *
4646 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4647 */
4648 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4649 }
4650 else
4651 {
4652 /*
4653 * A read access from the APIC-access page that is virtualized (rather than
4654 * causing a VM-exit) returns data from the virtual-APIC page.
4655 *
4656 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4657 */
4658 Assert(cbAccess <= 4);
4659 Assert(offAccess < XAPIC_OFF_END + 4);
4660 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4661
4662 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4663 u32Data &= s_auAccessSizeMasks[cbAccess];
4664 *(uint32_t *)pvData = u32Data;
4665 }
4666
4667 return VINF_VMX_MODIFIES_BEHAVIOR;
4668}
4669
4670
4671/**
4672 * Virtualizes an MSR-based APIC read access.
4673 *
4674 * @returns VBox strict status code.
4675 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4676 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4677 * handled by the x2APIC device.
4678 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4679 * not within the range of valid MSRs, caller must raise \#GP(0).
4680 * @param pVCpu The cross context virtual CPU structure.
4681 * @param idMsr The x2APIC MSR being read.
4682 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4683 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4684 */
4685IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4686{
4687 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4688 Assert(pVmcs);
4689 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4690 Assert(pu64Value);
4691
4692 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4693 {
4694 /*
4695 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4696 * what the end of the valid x2APIC MSR range is. Hence the use of different
4697 * macros here.
4698 *
4699 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4700 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4701 */
4702 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4703 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4704 {
4705 uint16_t const offReg = (idMsr & 0xff) << 4;
4706 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4707 *pu64Value = u64Value;
4708 return VINF_VMX_MODIFIES_BEHAVIOR;
4709 }
4710 return VERR_OUT_OF_RANGE;
4711 }
4712
4713 if (idMsr == MSR_IA32_X2APIC_TPR)
4714 {
4715 uint16_t const offReg = (idMsr & 0xff) << 4;
4716 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4717 *pu64Value = u64Value;
4718 return VINF_VMX_MODIFIES_BEHAVIOR;
4719 }
4720
4721 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4722}
4723
4724
4725/**
4726 * Virtualizes an MSR-based APIC write access.
4727 *
4728 * @returns VBox strict status code.
4729 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4730 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4731 * not within the range of valid MSRs, caller must raise \#GP(0).
4732 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4733 *
4734 * @param pVCpu The cross context virtual CPU structure.
4735 * @param idMsr The x2APIC MSR being written.
4736 * @param u64Value The value of the x2APIC MSR being written.
4737 */
4738IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4739{
4740 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4741 Assert(pVmcs);
4742
4743 /*
4744 * Check if the access is to be virtualized.
4745 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4746 */
4747 if ( idMsr == MSR_IA32_X2APIC_TPR
4748 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4749 && ( idMsr == MSR_IA32_X2APIC_EOI
4750 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4751 {
4752 /* Validate the MSR write depending on the register. */
4753 switch (idMsr)
4754 {
4755 case MSR_IA32_X2APIC_TPR:
4756 case MSR_IA32_X2APIC_SELF_IPI:
4757 {
4758 if (u64Value & UINT64_C(0xffffffffffffff00))
4759 return VERR_OUT_OF_RANGE;
4760 break;
4761 }
4762 case MSR_IA32_X2APIC_EOI:
4763 {
4764 if (u64Value != 0)
4765 return VERR_OUT_OF_RANGE;
4766 break;
4767 }
4768 }
4769
4770 /* Write the MSR to the virtual-APIC page. */
4771 uint16_t const offReg = (idMsr & 0xff) << 4;
4772 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4773
4774 /*
4775 * Record the currently updated APIC offset, as we need this later for figuring
4776 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4777 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4778 */
4779 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4780
4781 return VINF_VMX_MODIFIES_BEHAVIOR;
4782 }
4783
4784 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4785}
4786
4787
4788/**
4789 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4790 *
4791 * @returns VBox status code.
4792 * @retval VINF_SUCCES when the highest set bit is found.
4793 * @retval VERR_NOT_FOUND when no bit is set.
4794 *
4795 * @param pVCpu The cross context virtual CPU structure.
4796 * @param offReg The offset of the APIC 256-bit sparse register.
4797 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4798 * set in the register. Only valid when VINF_SUCCESS is
4799 * returned.
4800 *
4801 * @remarks The format of the 256-bit sparse register here mirrors that found in
4802 * real APIC hardware.
4803 */
4804static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4805{
4806 Assert(offReg < XAPIC_OFF_END + 4);
4807 Assert(pidxHighestBit);
4808 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4809
4810 /*
4811 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4812 * However, in each fragment only the first 4 bytes are used.
4813 */
4814 uint8_t const cFrags = 8;
4815 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4816 {
4817 uint16_t const offFrag = iFrag * 16;
4818 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4819 if (!u32Frag)
4820 continue;
4821
4822 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4823 Assert(idxHighestBit > 0);
4824 --idxHighestBit;
4825 Assert(idxHighestBit <= UINT8_MAX);
4826 *pidxHighestBit = idxHighestBit;
4827 return VINF_SUCCESS;
4828 }
4829 return VERR_NOT_FOUND;
4830}
4831
4832
4833/**
4834 * Evaluates pending virtual interrupts.
4835 *
4836 * @param pVCpu The cross context virtual CPU structure.
4837 */
4838IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4839{
4840 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4841 Assert(pVmcs);
4842 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4843
4844 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4845 {
4846 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4847 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4848
4849 if ((uRvi >> 4) > (uPpr >> 4))
4850 {
4851 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4852 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4853 }
4854 else
4855 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4856 }
4857}
4858
4859
4860/**
4861 * Performs PPR virtualization.
4862 *
4863 * @returns VBox strict status code.
4864 * @param pVCpu The cross context virtual CPU structure.
4865 */
4866IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4867{
4868 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4869 Assert(pVmcs);
4870 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4871 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4872
4873 /*
4874 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4875 * or EOI-virtualization.
4876 *
4877 * See Intel spec. 29.1.3 "PPR Virtualization".
4878 */
4879 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4880 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4881
4882 uint32_t uPpr;
4883 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4884 uPpr = uTpr & 0xff;
4885 else
4886 uPpr = uSvi & 0xf0;
4887
4888 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4889 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4890}
4891
4892
4893/**
4894 * Performs VMX TPR virtualization.
4895 *
4896 * @returns VBox strict status code.
4897 * @param pVCpu The cross context virtual CPU structure.
4898 */
4899IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4900{
4901 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4902 Assert(pVmcs);
4903 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4904
4905 /*
4906 * We should have already performed the virtual-APIC write to the TPR offset
4907 * in the virtual-APIC page. We now perform TPR virtualization.
4908 *
4909 * See Intel spec. 29.1.2 "TPR Virtualization".
4910 */
4911 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4912 {
4913 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4914 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4915
4916 /*
4917 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4918 * See Intel spec. 29.1.2 "TPR Virtualization".
4919 */
4920 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4921 {
4922 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4923 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4924 }
4925 }
4926 else
4927 {
4928 iemVmxPprVirtualization(pVCpu);
4929 iemVmxEvalPendingVirtIntrs(pVCpu);
4930 }
4931
4932 return VINF_SUCCESS;
4933}
4934
4935
4936/**
4937 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4938 * not.
4939 *
4940 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4941 * @param pVCpu The cross context virtual CPU structure.
4942 * @param uVector The interrupt that was acknowledged using an EOI.
4943 */
4944IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4945{
4946 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4947 Assert(pVmcs);
4948 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4949
4950 if (uVector < 64)
4951 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4952 if (uVector < 128)
4953 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4954 if (uVector < 192)
4955 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4956 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4957}
4958
4959
4960/**
4961 * Performs EOI virtualization.
4962 *
4963 * @returns VBox strict status code.
4964 * @param pVCpu The cross context virtual CPU structure.
4965 */
4966IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4967{
4968 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4969 Assert(pVmcs);
4970 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4971
4972 /*
4973 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4974 * and get the next guest-interrupt that's in-service (if any).
4975 *
4976 * See Intel spec. 29.1.4 "EOI Virtualization".
4977 */
4978 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4979 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4980 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4981
4982 uint8_t uVector = uSvi;
4983 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4984
4985 uVector = 0;
4986 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4987
4988 if (uVector)
4989 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4990 else
4991 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4992
4993 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4994 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4995
4996 iemVmxPprVirtualization(pVCpu);
4997 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4998 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4999 iemVmxEvalPendingVirtIntrs(pVCpu);
5000 return VINF_SUCCESS;
5001}
5002
5003
5004/**
5005 * Performs self-IPI virtualization.
5006 *
5007 * @returns VBox strict status code.
5008 * @param pVCpu The cross context virtual CPU structure.
5009 */
5010IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5011{
5012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5013 Assert(pVmcs);
5014 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5015
5016 /*
5017 * We should have already performed the virtual-APIC write to the self-IPI offset
5018 * in the virtual-APIC page. We now perform self-IPI virtualization.
5019 *
5020 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5021 */
5022 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5023 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5024 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5025 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5026 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5027 if (uVector > uRvi)
5028 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5029 iemVmxEvalPendingVirtIntrs(pVCpu);
5030 return VINF_SUCCESS;
5031}
5032
5033
5034/**
5035 * Performs VMX APIC-write emulation.
5036 *
5037 * @returns VBox strict status code.
5038 * @param pVCpu The cross context virtual CPU structure.
5039 */
5040IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5041{
5042 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5043 Assert(pVmcs);
5044
5045 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5046 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5047
5048 /*
5049 * Perform APIC-write emulation based on the virtual-APIC register written.
5050 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5051 */
5052 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5053 VBOXSTRICTRC rcStrict;
5054 switch (offApicWrite)
5055 {
5056 case XAPIC_OFF_TPR:
5057 {
5058 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5059 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5060 uTpr &= UINT32_C(0x000000ff);
5061 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5062 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5063 rcStrict = iemVmxTprVirtualization(pVCpu);
5064 break;
5065 }
5066
5067 case XAPIC_OFF_EOI:
5068 {
5069 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5070 {
5071 /* Clear VEOI and perform EOI virtualization. */
5072 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5073 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5074 rcStrict = iemVmxEoiVirtualization(pVCpu);
5075 }
5076 else
5077 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5078 break;
5079 }
5080
5081 case XAPIC_OFF_ICR_LO:
5082 {
5083 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5084 {
5085 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5086 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5087 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5088 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5089 if ( !(uIcrLo & fIcrLoMb0)
5090 && (uIcrLo & fIcrLoMb1))
5091 {
5092 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5093 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5094 }
5095 else
5096 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5097 }
5098 else
5099 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5100 break;
5101 }
5102
5103 case XAPIC_OFF_ICR_HI:
5104 {
5105 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5106 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5107 uIcrHi &= UINT32_C(0xff000000);
5108 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5109 rcStrict = VINF_SUCCESS;
5110 break;
5111 }
5112
5113 default:
5114 {
5115 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5116 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5117 break;
5118 }
5119 }
5120
5121 return rcStrict;
5122}
5123
5124
5125/**
5126 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5127 *
5128 * @param pVCpu The cross context virtual CPU structure.
5129 * @param pszInstr The VMX instruction name (for logging purposes).
5130 */
5131IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5132{
5133 /*
5134 * Guest Control Registers, Debug Registers, and MSRs.
5135 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5136 */
5137 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5138 const char *const pszFailure = "VM-exit";
5139 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5140
5141 /* CR0 reserved bits. */
5142 {
5143 /* CR0 MB1 bits. */
5144 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5145 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5146 if (fUnrestrictedGuest)
5147 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5148 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5152
5153 /* CR0 MBZ bits. */
5154 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5155 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5156 { /* likely */ }
5157 else
5158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5159
5160 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5161 if ( !fUnrestrictedGuest
5162 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5163 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5165 }
5166
5167 /* CR4 reserved bits. */
5168 {
5169 /* CR4 MB1 bits. */
5170 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5171 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5172 { /* likely */ }
5173 else
5174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5175
5176 /* CR4 MBZ bits. */
5177 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5178 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5179 { /* likely */ }
5180 else
5181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5182 }
5183
5184 /* DEBUGCTL MSR. */
5185 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5186 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5190
5191 /* 64-bit CPU checks. */
5192 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5193 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5194 {
5195 if (fGstInLongMode)
5196 {
5197 /* PAE must be set. */
5198 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5199 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5203 }
5204 else
5205 {
5206 /* PCIDE should not be set. */
5207 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5208 { /* likely */ }
5209 else
5210 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5211 }
5212
5213 /* CR3. */
5214 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5215 { /* likely */ }
5216 else
5217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5218
5219 /* DR7. */
5220 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5221 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5225
5226 /* SYSENTER ESP and SYSENTER EIP. */
5227 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5228 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5229 { /* likely */ }
5230 else
5231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5232 }
5233
5234 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5235 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5236
5237 /* PAT MSR. */
5238 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5239 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5240 { /* likely */ }
5241 else
5242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5243
5244 /* EFER MSR. */
5245 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5246 {
5247 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5248 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5249 { /* likely */ }
5250 else
5251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5252
5253 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5254 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5255 if ( fGstLma == fGstInLongMode
5256 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5257 || fGstLma == fGstLme))
5258 { /* likely */ }
5259 else
5260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5261 }
5262
5263 /* We don't support IA32_BNDCFGS MSR yet. */
5264 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5265
5266 NOREF(pszInstr);
5267 NOREF(pszFailure);
5268 return VINF_SUCCESS;
5269}
5270
5271
5272/**
5273 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5274 *
5275 * @param pVCpu The cross context virtual CPU structure.
5276 * @param pszInstr The VMX instruction name (for logging purposes).
5277 */
5278IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5279{
5280 /*
5281 * Segment registers.
5282 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5283 */
5284 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5285 const char *const pszFailure = "VM-exit";
5286 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5287 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5288 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5289
5290 /* Selectors. */
5291 if ( !fGstInV86Mode
5292 && !fUnrestrictedGuest
5293 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5295
5296 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5297 {
5298 CPUMSELREG SelReg;
5299 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5300 if (RT_LIKELY(rc == VINF_SUCCESS))
5301 { /* likely */ }
5302 else
5303 return rc;
5304
5305 /*
5306 * Virtual-8086 mode checks.
5307 */
5308 if (fGstInV86Mode)
5309 {
5310 /* Base address. */
5311 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5312 { /* likely */ }
5313 else
5314 {
5315 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5317 }
5318
5319 /* Limit. */
5320 if (SelReg.u32Limit == 0xffff)
5321 { /* likely */ }
5322 else
5323 {
5324 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5326 }
5327
5328 /* Attribute. */
5329 if (SelReg.Attr.u == 0xf3)
5330 { /* likely */ }
5331 else
5332 {
5333 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5334 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5335 }
5336
5337 /* We're done; move to checking the next segment. */
5338 continue;
5339 }
5340
5341 /* Checks done by 64-bit CPUs. */
5342 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5343 {
5344 /* Base address. */
5345 if ( iSegReg == X86_SREG_FS
5346 || iSegReg == X86_SREG_GS)
5347 {
5348 if (X86_IS_CANONICAL(SelReg.u64Base))
5349 { /* likely */ }
5350 else
5351 {
5352 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5354 }
5355 }
5356 else if (iSegReg == X86_SREG_CS)
5357 {
5358 if (!RT_HI_U32(SelReg.u64Base))
5359 { /* likely */ }
5360 else
5361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5362 }
5363 else
5364 {
5365 if ( SelReg.Attr.n.u1Unusable
5366 || !RT_HI_U32(SelReg.u64Base))
5367 { /* likely */ }
5368 else
5369 {
5370 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5372 }
5373 }
5374 }
5375
5376 /*
5377 * Checks outside Virtual-8086 mode.
5378 */
5379 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5380 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5381 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5382 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5383 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5384 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5385 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5386 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5387
5388 /* Code or usable segment. */
5389 if ( iSegReg == X86_SREG_CS
5390 || fUsable)
5391 {
5392 /* Reserved bits (bits 31:17 and bits 11:8). */
5393 if (!(SelReg.Attr.u & 0xfffe0f00))
5394 { /* likely */ }
5395 else
5396 {
5397 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5399 }
5400
5401 /* Descriptor type. */
5402 if (fCodeDataSeg)
5403 { /* likely */ }
5404 else
5405 {
5406 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5407 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5408 }
5409
5410 /* Present. */
5411 if (fPresent)
5412 { /* likely */ }
5413 else
5414 {
5415 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5417 }
5418
5419 /* Granularity. */
5420 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5421 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5422 { /* likely */ }
5423 else
5424 {
5425 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5427 }
5428 }
5429
5430 if (iSegReg == X86_SREG_CS)
5431 {
5432 /* Segment Type and DPL. */
5433 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5434 && fUnrestrictedGuest)
5435 {
5436 if (uDpl == 0)
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5440 }
5441 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5442 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5443 {
5444 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5445 if (uDpl == AttrSs.n.u2Dpl)
5446 { /* likely */ }
5447 else
5448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5449 }
5450 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5451 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5452 {
5453 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5454 if (uDpl <= AttrSs.n.u2Dpl)
5455 { /* likely */ }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5458 }
5459 else
5460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5461
5462 /* Def/Big. */
5463 if ( fGstInLongMode
5464 && fSegLong)
5465 {
5466 if (uDefBig == 0)
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5470 }
5471 }
5472 else if (iSegReg == X86_SREG_SS)
5473 {
5474 /* Segment Type. */
5475 if ( !fUsable
5476 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5477 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5478 { /* likely */ }
5479 else
5480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5481
5482 /* DPL. */
5483 if (!fUnrestrictedGuest)
5484 {
5485 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5489 }
5490 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5491 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5492 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5493 {
5494 if (uDpl == 0)
5495 { /* likely */ }
5496 else
5497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5498 }
5499 }
5500 else
5501 {
5502 /* DS, ES, FS, GS. */
5503 if (fUsable)
5504 {
5505 /* Segment type. */
5506 if (uSegType & X86_SEL_TYPE_ACCESSED)
5507 { /* likely */ }
5508 else
5509 {
5510 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5512 }
5513
5514 if ( !(uSegType & X86_SEL_TYPE_CODE)
5515 || (uSegType & X86_SEL_TYPE_READ))
5516 { /* likely */ }
5517 else
5518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5519
5520 /* DPL. */
5521 if ( !fUnrestrictedGuest
5522 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5523 {
5524 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5525 { /* likely */ }
5526 else
5527 {
5528 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5530 }
5531 }
5532 }
5533 }
5534 }
5535
5536 /*
5537 * LDTR.
5538 */
5539 {
5540 CPUMSELREG Ldtr;
5541 Ldtr.Sel = pVmcs->GuestLdtr;
5542 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5543 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5544 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5545
5546 if (!Ldtr.Attr.n.u1Unusable)
5547 {
5548 /* Selector. */
5549 if (!(Ldtr.Sel & X86_SEL_LDT))
5550 { /* likely */ }
5551 else
5552 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5553
5554 /* Base. */
5555 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5556 {
5557 if (X86_IS_CANONICAL(Ldtr.u64Base))
5558 { /* likely */ }
5559 else
5560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5561 }
5562
5563 /* Attributes. */
5564 /* Reserved bits (bits 31:17 and bits 11:8). */
5565 if (!(Ldtr.Attr.u & 0xfffe0f00))
5566 { /* likely */ }
5567 else
5568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5569
5570 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5574
5575 if (!Ldtr.Attr.n.u1DescType)
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5579
5580 if (Ldtr.Attr.n.u1Present)
5581 { /* likely */ }
5582 else
5583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5584
5585 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5586 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5587 { /* likely */ }
5588 else
5589 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5590 }
5591 }
5592
5593 /*
5594 * TR.
5595 */
5596 {
5597 CPUMSELREG Tr;
5598 Tr.Sel = pVmcs->GuestTr;
5599 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5600 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5601 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5602
5603 /* Selector. */
5604 if (!(Tr.Sel & X86_SEL_LDT))
5605 { /* likely */ }
5606 else
5607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5608
5609 /* Base. */
5610 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5611 {
5612 if (X86_IS_CANONICAL(Tr.u64Base))
5613 { /* likely */ }
5614 else
5615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5616 }
5617
5618 /* Attributes. */
5619 /* Reserved bits (bits 31:17 and bits 11:8). */
5620 if (!(Tr.Attr.u & 0xfffe0f00))
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5624
5625 if (!Tr.Attr.n.u1Unusable)
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5629
5630 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5631 || ( !fGstInLongMode
5632 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5633 { /* likely */ }
5634 else
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5636
5637 if (!Tr.Attr.n.u1DescType)
5638 { /* likely */ }
5639 else
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5641
5642 if (Tr.Attr.n.u1Present)
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5646
5647 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5648 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5649 { /* likely */ }
5650 else
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5652 }
5653
5654 NOREF(pszInstr);
5655 NOREF(pszFailure);
5656 return VINF_SUCCESS;
5657}
5658
5659
5660/**
5661 * Checks guest GDTR and IDTR as part of VM-entry.
5662 *
5663 * @param pVCpu The cross context virtual CPU structure.
5664 * @param pszInstr The VMX instruction name (for logging purposes).
5665 */
5666IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5667{
5668 /*
5669 * GDTR and IDTR.
5670 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5671 */
5672 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5673 const char *const pszFailure = "VM-exit";
5674
5675 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5676 {
5677 /* Base. */
5678 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5679 { /* likely */ }
5680 else
5681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5682
5683 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5684 { /* likely */ }
5685 else
5686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5687 }
5688
5689 /* Limit. */
5690 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5691 { /* likely */ }
5692 else
5693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5694
5695 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5696 { /* likely */ }
5697 else
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5699
5700 NOREF(pszInstr);
5701 NOREF(pszFailure);
5702 return VINF_SUCCESS;
5703}
5704
5705
5706/**
5707 * Checks guest RIP and RFLAGS as part of VM-entry.
5708 *
5709 * @param pVCpu The cross context virtual CPU structure.
5710 * @param pszInstr The VMX instruction name (for logging purposes).
5711 */
5712IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5713{
5714 /*
5715 * RIP and RFLAGS.
5716 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5717 */
5718 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5719 const char *const pszFailure = "VM-exit";
5720 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5721
5722 /* RIP. */
5723 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5724 {
5725 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5726 if ( !fGstInLongMode
5727 || !AttrCs.n.u1Long)
5728 {
5729 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5730 { /* likely */ }
5731 else
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5733 }
5734
5735 if ( fGstInLongMode
5736 && AttrCs.n.u1Long)
5737 {
5738 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5739 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5740 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5744 }
5745 }
5746
5747 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5748 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5749 : pVmcs->u64GuestRFlags.s.Lo;
5750 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5751 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5752 { /* likely */ }
5753 else
5754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5755
5756 if ( fGstInLongMode
5757 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5758 {
5759 if (!(uGuestRFlags & X86_EFL_VM))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5763 }
5764
5765 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5766 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5767 {
5768 if (uGuestRFlags & X86_EFL_IF)
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5772 }
5773
5774 NOREF(pszInstr);
5775 NOREF(pszFailure);
5776 return VINF_SUCCESS;
5777}
5778
5779
5780/**
5781 * Checks guest non-register state as part of VM-entry.
5782 *
5783 * @param pVCpu The cross context virtual CPU structure.
5784 * @param pszInstr The VMX instruction name (for logging purposes).
5785 */
5786IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5787{
5788 /*
5789 * Guest non-register state.
5790 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5791 */
5792 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5793 const char *const pszFailure = "VM-exit";
5794
5795 /*
5796 * Activity state.
5797 */
5798 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5799 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5800 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5801 { /* likely */ }
5802 else
5803 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5804
5805 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5806 if ( !AttrSs.n.u2Dpl
5807 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5808 { /* likely */ }
5809 else
5810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5811
5812 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5813 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5814 {
5815 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5816 { /* likely */ }
5817 else
5818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5819 }
5820
5821 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5822 {
5823 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5824 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5825 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5826 switch (pVmcs->u32GuestActivityState)
5827 {
5828 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5829 {
5830 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5831 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5832 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5833 && ( uVector == X86_XCPT_DB
5834 || uVector == X86_XCPT_MC))
5835 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5836 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5837 { /* likely */ }
5838 else
5839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5840 break;
5841 }
5842
5843 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5844 {
5845 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5846 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5847 && uVector == X86_XCPT_MC))
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5851 break;
5852 }
5853
5854 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5855 default:
5856 break;
5857 }
5858 }
5859
5860 /*
5861 * Interruptibility state.
5862 */
5863 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5867
5868 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5869 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5873
5874 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5875 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5879
5880 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5881 {
5882 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5883 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5884 {
5885 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5886 { /* likely */ }
5887 else
5888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5889 }
5890 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5891 {
5892 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5893 { /* likely */ }
5894 else
5895 {
5896 /*
5897 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5898 * We update the VM-exit qualification only when blocking-by-STI is set
5899 * without blocking-by-MovSS being set. Although in practise it does not
5900 * make much difference since the order of checks are implementation defined.
5901 */
5902 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5903 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5905 }
5906
5907 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5908 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5909 { /* likely */ }
5910 else
5911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5912 }
5913 }
5914
5915 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5916 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5917 { /* likely */ }
5918 else
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5920
5921 /* We don't support SGX yet. So enclave-interruption must not be set. */
5922 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5923 { /* likely */ }
5924 else
5925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5926
5927 /*
5928 * Pending debug exceptions.
5929 */
5930 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5931 ? pVmcs->u64GuestPendingDbgXcpt.u
5932 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5933 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5934 { /* likely */ }
5935 else
5936 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5937
5938 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5939 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5940 {
5941 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5942 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5943 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5945
5946 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5947 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5948 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5950 }
5951
5952 /* We don't support RTM (Real-time Transactional Memory) yet. */
5953 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5954 { /* likely */ }
5955 else
5956 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5957
5958 /*
5959 * VMCS link pointer.
5960 */
5961 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5962 {
5963 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5964 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5965 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5966 { /* likely */ }
5967 else
5968 {
5969 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5971 }
5972
5973 /* Validate the address. */
5974 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5975 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5976 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5977 { /* likely */ }
5978 else
5979 {
5980 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5982 }
5983
5984 /* Read the VMCS-link pointer from guest memory. */
5985 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5986 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5987 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5988 if (RT_SUCCESS(rc))
5989 { /* likely */ }
5990 else
5991 {
5992 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5993 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5994 }
5995
5996 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5997 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5998 { /* likely */ }
5999 else
6000 {
6001 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6003 }
6004
6005 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6006 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6007 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6008 { /* likely */ }
6009 else
6010 {
6011 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6013 }
6014
6015 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6016 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6017 }
6018
6019 NOREF(pszInstr);
6020 NOREF(pszFailure);
6021 return VINF_SUCCESS;
6022}
6023
6024
6025/**
6026 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6027 * VM-entry.
6028 *
6029 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6030 * @param pVCpu The cross context virtual CPU structure.
6031 * @param pszInstr The VMX instruction name (for logging purposes).
6032 * @param pVmcs Pointer to the virtual VMCS.
6033 */
6034IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6035{
6036 /*
6037 * Check PDPTEs.
6038 * See Intel spec. 4.4.1 "PDPTE Registers".
6039 */
6040 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6041 const char *const pszFailure = "VM-exit";
6042
6043 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6044 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6045 if (RT_SUCCESS(rc))
6046 {
6047 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6048 {
6049 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6050 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6051 { /* likely */ }
6052 else
6053 {
6054 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6055 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6056 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6057 }
6058 }
6059 }
6060 else
6061 {
6062 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6063 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6064 }
6065
6066 NOREF(pszFailure);
6067 NOREF(pszInstr);
6068 return rc;
6069}
6070
6071
6072/**
6073 * Checks guest PDPTEs as part of VM-entry.
6074 *
6075 * @param pVCpu The cross context virtual CPU structure.
6076 * @param pszInstr The VMX instruction name (for logging purposes).
6077 */
6078IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6079{
6080 /*
6081 * Guest PDPTEs.
6082 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6083 */
6084 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6085 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6086
6087 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6088 int rc;
6089 if ( !fGstInLongMode
6090 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6091 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6092 {
6093 /*
6094 * We don't support nested-paging for nested-guests yet.
6095 *
6096 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6097 * rather we need to check the PDPTEs referenced by the guest CR3.
6098 */
6099 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6100 }
6101 else
6102 rc = VINF_SUCCESS;
6103 return rc;
6104}
6105
6106
6107/**
6108 * Checks guest-state as part of VM-entry.
6109 *
6110 * @returns VBox status code.
6111 * @param pVCpu The cross context virtual CPU structure.
6112 * @param pszInstr The VMX instruction name (for logging purposes).
6113 */
6114IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6115{
6116 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6117 if (RT_SUCCESS(rc))
6118 {
6119 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6120 if (RT_SUCCESS(rc))
6121 {
6122 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6123 if (RT_SUCCESS(rc))
6124 {
6125 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6126 if (RT_SUCCESS(rc))
6127 {
6128 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6129 if (RT_SUCCESS(rc))
6130 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6131 }
6132 }
6133 }
6134 }
6135 return rc;
6136}
6137
6138
6139/**
6140 * Checks host-state as part of VM-entry.
6141 *
6142 * @returns VBox status code.
6143 * @param pVCpu The cross context virtual CPU structure.
6144 * @param pszInstr The VMX instruction name (for logging purposes).
6145 */
6146IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6147{
6148 /*
6149 * Host Control Registers and MSRs.
6150 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6151 */
6152 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6153 const char * const pszFailure = "VMFail";
6154
6155 /* CR0 reserved bits. */
6156 {
6157 /* CR0 MB1 bits. */
6158 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6159 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6163
6164 /* CR0 MBZ bits. */
6165 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6166 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6167 { /* likely */ }
6168 else
6169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6170 }
6171
6172 /* CR4 reserved bits. */
6173 {
6174 /* CR4 MB1 bits. */
6175 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6176 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6177 { /* likely */ }
6178 else
6179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6180
6181 /* CR4 MBZ bits. */
6182 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6183 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6184 { /* likely */ }
6185 else
6186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6187 }
6188
6189 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6190 {
6191 /* CR3 reserved bits. */
6192 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6193 { /* likely */ }
6194 else
6195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6196
6197 /* SYSENTER ESP and SYSENTER EIP. */
6198 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6199 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6203 }
6204
6205 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6206 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6207
6208 /* PAT MSR. */
6209 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6210 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6211 { /* likely */ }
6212 else
6213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6214
6215 /* EFER MSR. */
6216 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6217 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6218 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6222
6223 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6224 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6225 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6226 if ( fHostInLongMode == fHostLma
6227 && fHostInLongMode == fHostLme)
6228 { /* likely */ }
6229 else
6230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6231
6232 /*
6233 * Host Segment and Descriptor-Table Registers.
6234 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6235 */
6236 /* Selector RPL and TI. */
6237 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6238 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6239 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6240 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6241 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6242 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6243 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6247
6248 /* CS and TR selectors cannot be 0. */
6249 if ( pVmcs->HostCs
6250 && pVmcs->HostTr)
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6254
6255 /* SS cannot be 0 if 32-bit host. */
6256 if ( fHostInLongMode
6257 || pVmcs->HostSs)
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6261
6262 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6263 {
6264 /* FS, GS, GDTR, IDTR, TR base address. */
6265 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6266 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6267 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6268 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6269 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6273 }
6274
6275 /*
6276 * Host address-space size for 64-bit CPUs.
6277 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6278 */
6279 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6280 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6281 {
6282 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6283
6284 /* Logical processor in IA-32e mode. */
6285 if (fCpuInLongMode)
6286 {
6287 if (fHostInLongMode)
6288 {
6289 /* PAE must be set. */
6290 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6291 { /* likely */ }
6292 else
6293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6294
6295 /* RIP must be canonical. */
6296 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6297 { /* likely */ }
6298 else
6299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6300 }
6301 else
6302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6303 }
6304 else
6305 {
6306 /* Logical processor is outside IA-32e mode. */
6307 if ( !fGstInLongMode
6308 && !fHostInLongMode)
6309 {
6310 /* PCIDE should not be set. */
6311 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6312 { /* likely */ }
6313 else
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6315
6316 /* The high 32-bits of RIP MBZ. */
6317 if (!pVmcs->u64HostRip.s.Hi)
6318 { /* likely */ }
6319 else
6320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6321 }
6322 else
6323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6324 }
6325 }
6326 else
6327 {
6328 /* Host address-space size for 32-bit CPUs. */
6329 if ( !fGstInLongMode
6330 && !fHostInLongMode)
6331 { /* likely */ }
6332 else
6333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6334 }
6335
6336 NOREF(pszInstr);
6337 NOREF(pszFailure);
6338 return VINF_SUCCESS;
6339}
6340
6341
6342/**
6343 * Checks VM-entry controls fields as part of VM-entry.
6344 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6345 *
6346 * @returns VBox status code.
6347 * @param pVCpu The cross context virtual CPU structure.
6348 * @param pszInstr The VMX instruction name (for logging purposes).
6349 */
6350IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6351{
6352 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6353 const char * const pszFailure = "VMFail";
6354
6355 /* VM-entry controls. */
6356 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6357 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6361
6362 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6363 { /* likely */ }
6364 else
6365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6366
6367 /* Event injection. */
6368 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6369 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6370 {
6371 /* Type and vector. */
6372 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6373 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6374 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6375 if ( !uRsvd
6376 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6377 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6378 { /* likely */ }
6379 else
6380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6381
6382 /* Exception error code. */
6383 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6384 {
6385 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6386 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6387 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6391
6392 /* Exceptions that provide an error code. */
6393 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6394 && ( uVector == X86_XCPT_DF
6395 || uVector == X86_XCPT_TS
6396 || uVector == X86_XCPT_NP
6397 || uVector == X86_XCPT_SS
6398 || uVector == X86_XCPT_GP
6399 || uVector == X86_XCPT_PF
6400 || uVector == X86_XCPT_AC))
6401 { /* likely */ }
6402 else
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6404
6405 /* Exception error-code reserved bits. */
6406 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6410
6411 /* Injecting a software interrupt, software exception or privileged software exception. */
6412 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6413 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6414 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6415 {
6416 /* Instruction length must be in the range 0-15. */
6417 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6418 { /* likely */ }
6419 else
6420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6421
6422 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6423 if ( pVmcs->u32EntryInstrLen == 0
6424 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6425 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6426 }
6427 }
6428 }
6429
6430 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6431 if (pVmcs->u32EntryMsrLoadCount)
6432 {
6433 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6434 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6435 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6436 { /* likely */ }
6437 else
6438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6439 }
6440
6441 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6442 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6443
6444 NOREF(pszInstr);
6445 NOREF(pszFailure);
6446 return VINF_SUCCESS;
6447}
6448
6449
6450/**
6451 * Checks VM-exit controls fields as part of VM-entry.
6452 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6453 *
6454 * @returns VBox status code.
6455 * @param pVCpu The cross context virtual CPU structure.
6456 * @param pszInstr The VMX instruction name (for logging purposes).
6457 */
6458IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6459{
6460 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6461 const char * const pszFailure = "VMFail";
6462
6463 /* VM-exit controls. */
6464 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6465 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6466 { /* likely */ }
6467 else
6468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6469
6470 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6474
6475 /* Save preemption timer without activating it. */
6476 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6477 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6478 { /* likely */ }
6479 else
6480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6481
6482 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6483 if (pVmcs->u32ExitMsrStoreCount)
6484 {
6485 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6486 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6487 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6488 { /* likely */ }
6489 else
6490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6491 }
6492
6493 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6494 if (pVmcs->u32ExitMsrLoadCount)
6495 {
6496 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6497 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6498 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6499 { /* likely */ }
6500 else
6501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6502 }
6503
6504 NOREF(pszInstr);
6505 NOREF(pszFailure);
6506 return VINF_SUCCESS;
6507}
6508
6509
6510/**
6511 * Checks VM-execution controls fields as part of VM-entry.
6512 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6513 *
6514 * @returns VBox status code.
6515 * @param pVCpu The cross context virtual CPU structure.
6516 * @param pszInstr The VMX instruction name (for logging purposes).
6517 *
6518 * @remarks This may update secondary-processor based VM-execution control fields
6519 * in the current VMCS if necessary.
6520 */
6521IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6522{
6523 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6524 const char * const pszFailure = "VMFail";
6525
6526 /* Pin-based VM-execution controls. */
6527 {
6528 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6529 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6530 { /* likely */ }
6531 else
6532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6533
6534 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6538 }
6539
6540 /* Processor-based VM-execution controls. */
6541 {
6542 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6543 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6544 { /* likely */ }
6545 else
6546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6547
6548 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6549 { /* likely */ }
6550 else
6551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6552 }
6553
6554 /* Secondary processor-based VM-execution controls. */
6555 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6556 {
6557 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6558 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6559 { /* likely */ }
6560 else
6561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6562
6563 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6564 { /* likely */ }
6565 else
6566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6567 }
6568 else
6569 Assert(!pVmcs->u32ProcCtls2);
6570
6571 /* CR3-target count. */
6572 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6573 { /* likely */ }
6574 else
6575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6576
6577 /* I/O bitmaps physical addresses. */
6578 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6579 {
6580 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6581 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6582 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6583 { /* likely */ }
6584 else
6585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6586
6587 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6588 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6589 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6590 { /* likely */ }
6591 else
6592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6593 }
6594
6595 /* MSR bitmap physical address. */
6596 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6597 {
6598 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6599 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6600 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6601 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6602 { /* likely */ }
6603 else
6604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6605
6606 /* Read the MSR bitmap. */
6607 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6608 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6609 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6610 if (RT_SUCCESS(rc))
6611 { /* likely */ }
6612 else
6613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6614 }
6615
6616 /* TPR shadow related controls. */
6617 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6618 {
6619 /* Virtual-APIC page physical address. */
6620 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6621 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6622 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6623 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6624 { /* likely */ }
6625 else
6626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6627
6628 /* TPR threshold without virtual-interrupt delivery. */
6629 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6630 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6632
6633 /* TPR threshold and VTPR. */
6634 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6635 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6636 {
6637 /* Read the VTPR from the virtual-APIC page. */
6638 uint8_t u8VTpr;
6639 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6640 if (RT_SUCCESS(rc))
6641 { /* likely */ }
6642 else
6643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6644
6645 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6646 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6647 { /* likely */ }
6648 else
6649 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6650 }
6651 }
6652 else
6653 {
6654 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6655 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6656 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6657 { /* likely */ }
6658 else
6659 {
6660 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6662 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6664 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6666 }
6667 }
6668
6669 /* NMI exiting and virtual-NMIs. */
6670 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6671 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6672 { /* likely */ }
6673 else
6674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6675
6676 /* Virtual-NMIs and NMI-window exiting. */
6677 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6678 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6679 { /* likely */ }
6680 else
6681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6682
6683 /* Virtualize APIC accesses. */
6684 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6685 {
6686 /* APIC-access physical address. */
6687 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6688 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6689 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6690 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6691 { /* likely */ }
6692 else
6693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6694
6695 /*
6696 * Disallow APIC-access page and virtual-APIC page from being the same address.
6697 * Note! This is not an Intel requirement, but one imposed by our implementation.
6698 */
6699 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6700 * redirecting accesses between the APIC-access page and the virtual-APIC
6701 * page. If any nested hypervisor requires this, we can implement it later. */
6702 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6703 {
6704 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6705 if (GCPhysVirtApic != GCPhysApicAccess)
6706 { /* likely */ }
6707 else
6708 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6709 }
6710
6711 /*
6712 * Register the handler for the APIC-access page.
6713 *
6714 * We don't deregister the APIC-access page handler during the VM-exit as a different
6715 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6716 *
6717 * We leave the page registered until the first access that happens outside VMX non-root
6718 * mode. Guest software is allowed to access structures such as the APIC-access page
6719 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6720 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6721 *
6722 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6723 */
6724 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6725 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6726 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6727 if (RT_SUCCESS(rc))
6728 { /* likely */ }
6729 else
6730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6731 }
6732
6733 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6734 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6735 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6736 { /* likely */ }
6737 else
6738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6739
6740 /* Virtual-interrupt delivery requires external interrupt exiting. */
6741 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6742 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6743 { /* likely */ }
6744 else
6745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6746
6747 /* VPID. */
6748 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6749 || pVmcs->u16Vpid != 0)
6750 { /* likely */ }
6751 else
6752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6753
6754 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6755 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6756 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6757 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6758 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6759 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6760 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6761
6762 /* VMCS shadowing. */
6763 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6764 {
6765 /* VMREAD-bitmap physical address. */
6766 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6767 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6768 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6769 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6770 { /* likely */ }
6771 else
6772 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6773
6774 /* VMWRITE-bitmap physical address. */
6775 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6776 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6777 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6778 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6779 { /* likely */ }
6780 else
6781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6782
6783 /* Read the VMREAD-bitmap. */
6784 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6785 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6786 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6787 if (RT_SUCCESS(rc))
6788 { /* likely */ }
6789 else
6790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6791
6792 /* Read the VMWRITE-bitmap. */
6793 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6794 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6795 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6796 if (RT_SUCCESS(rc))
6797 { /* likely */ }
6798 else
6799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6800 }
6801
6802 NOREF(pszInstr);
6803 NOREF(pszFailure);
6804 return VINF_SUCCESS;
6805}
6806
6807
6808/**
6809 * Loads the guest control registers, debug register and some MSRs as part of
6810 * VM-entry.
6811 *
6812 * @param pVCpu The cross context virtual CPU structure.
6813 */
6814IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6815{
6816 /*
6817 * Load guest control registers, debug registers and MSRs.
6818 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6819 */
6820 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6821
6822 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6823 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6824 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6825 CPUMSetGuestCR0(pVCpu, uGstCr0);
6826 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6827 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6828
6829 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6830 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6831
6832 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6833 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6834 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6835
6836 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6837 {
6838 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6839
6840 /* EFER MSR. */
6841 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6842 {
6843 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6844 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6845 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6846 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6847 if (fGstInLongMode)
6848 {
6849 /* If the nested-guest is in long mode, LMA and LME are both set. */
6850 Assert(fGstPaging);
6851 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6852 }
6853 else
6854 {
6855 /*
6856 * If the nested-guest is outside long mode:
6857 * - With paging: LMA is cleared, LME is cleared.
6858 * - Without paging: LMA is cleared, LME is left unmodified.
6859 */
6860 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6861 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6862 }
6863 }
6864 /* else: see below. */
6865 }
6866
6867 /* PAT MSR. */
6868 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6869 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6870
6871 /* EFER MSR. */
6872 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6873 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6874
6875 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6876 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6877
6878 /* We don't support IA32_BNDCFGS MSR yet. */
6879 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6880
6881 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6882}
6883
6884
6885/**
6886 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6887 *
6888 * @param pVCpu The cross context virtual CPU structure.
6889 */
6890IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6891{
6892 /*
6893 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6894 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6895 */
6896 /* CS, SS, ES, DS, FS, GS. */
6897 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6898 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6899 {
6900 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6901 CPUMSELREG VmcsSelReg;
6902 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6903 AssertRC(rc); NOREF(rc);
6904 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6905 {
6906 pGstSelReg->Sel = VmcsSelReg.Sel;
6907 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6908 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6909 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6910 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6911 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6912 }
6913 else
6914 {
6915 pGstSelReg->Sel = VmcsSelReg.Sel;
6916 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6917 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6918 switch (iSegReg)
6919 {
6920 case X86_SREG_CS:
6921 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6922 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6923 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6924 break;
6925
6926 case X86_SREG_SS:
6927 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6928 pGstSelReg->u32Limit = 0;
6929 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6930 break;
6931
6932 case X86_SREG_ES:
6933 case X86_SREG_DS:
6934 pGstSelReg->u64Base = 0;
6935 pGstSelReg->u32Limit = 0;
6936 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6937 break;
6938
6939 case X86_SREG_FS:
6940 case X86_SREG_GS:
6941 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6942 pGstSelReg->u32Limit = 0;
6943 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6944 break;
6945 }
6946 Assert(pGstSelReg->Attr.n.u1Unusable);
6947 }
6948 }
6949
6950 /* LDTR. */
6951 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6952 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6953 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6954 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6955 {
6956 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6957 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6958 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6959 }
6960 else
6961 {
6962 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6963 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6964 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6965 }
6966
6967 /* TR. */
6968 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6969 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6970 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6971 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6972 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6973 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6974 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6975
6976 /* GDTR. */
6977 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6978 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6979
6980 /* IDTR. */
6981 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6982 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6983}
6984
6985
6986/**
6987 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6988 *
6989 * @returns VBox status code.
6990 * @param pVCpu The cross context virtual CPU structure.
6991 * @param pszInstr The VMX instruction name (for logging purposes).
6992 */
6993IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6994{
6995 /*
6996 * Load guest MSRs.
6997 * See Intel spec. 26.4 "Loading MSRs".
6998 */
6999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7000 const char *const pszFailure = "VM-exit";
7001
7002 /*
7003 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7004 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7005 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7006 */
7007 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7008 if (!cMsrs)
7009 return VINF_SUCCESS;
7010
7011 /*
7012 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7013 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7014 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7015 */
7016 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7017 if (fIsMsrCountValid)
7018 { /* likely */ }
7019 else
7020 {
7021 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7023 }
7024
7025 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7026 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7027 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7028 if (RT_SUCCESS(rc))
7029 {
7030 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7031 Assert(pMsr);
7032 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7033 {
7034 if ( !pMsr->u32Reserved
7035 && pMsr->u32Msr != MSR_K8_FS_BASE
7036 && pMsr->u32Msr != MSR_K8_GS_BASE
7037 && pMsr->u32Msr != MSR_K6_EFER
7038 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7039 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7040 {
7041 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7042 if (rcStrict == VINF_SUCCESS)
7043 continue;
7044
7045 /*
7046 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7047 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7048 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7049 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7050 * MSR in ring-0 if possible, or come up with a better, generic solution.
7051 */
7052 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7053 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7054 ? kVmxVDiag_Vmentry_MsrLoadRing3
7055 : kVmxVDiag_Vmentry_MsrLoad;
7056 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7057 }
7058 else
7059 {
7060 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7062 }
7063 }
7064 }
7065 else
7066 {
7067 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7069 }
7070
7071 NOREF(pszInstr);
7072 NOREF(pszFailure);
7073 return VINF_SUCCESS;
7074}
7075
7076
7077/**
7078 * Loads the guest-state non-register state as part of VM-entry.
7079 *
7080 * @returns VBox status code.
7081 * @param pVCpu The cross context virtual CPU structure.
7082 *
7083 * @remarks This must be called only after loading the nested-guest register state
7084 * (especially nested-guest RIP).
7085 */
7086IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7087{
7088 /*
7089 * Load guest non-register state.
7090 * See Intel spec. 26.6 "Special Features of VM Entry"
7091 */
7092 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7093
7094 /*
7095 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7096 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7097 *
7098 * See Intel spec. 26.6.1 "Interruptibility State".
7099 */
7100 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7101 if ( !fEntryVectoring
7102 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7103 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7104 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7105 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7106
7107 /* NMI blocking. */
7108 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7109 {
7110 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7111 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7112 else
7113 {
7114 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7115 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7116 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7117 }
7118 }
7119 else
7120 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7121
7122 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7123
7124 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7125 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7126
7127 /* VPID is irrelevant. We don't support VPID yet. */
7128
7129 /* Clear address-range monitoring. */
7130 EMMonitorWaitClear(pVCpu);
7131}
7132
7133
7134/**
7135 * Loads the guest-state as part of VM-entry.
7136 *
7137 * @returns VBox status code.
7138 * @param pVCpu The cross context virtual CPU structure.
7139 * @param pszInstr The VMX instruction name (for logging purposes).
7140 *
7141 * @remarks This must be done after all the necessary steps prior to loading of
7142 * guest-state (e.g. checking various VMCS state).
7143 */
7144IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7145{
7146 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7147 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7148
7149 /*
7150 * Load guest RIP, RSP and RFLAGS.
7151 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7152 */
7153 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7154 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7155 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7156 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7157
7158 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7159 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7160 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7161
7162 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7163
7164 NOREF(pszInstr);
7165 return VINF_SUCCESS;
7166}
7167
7168
7169/**
7170 * Returns whether there are is a pending debug exception on VM-entry.
7171 *
7172 * @param pVCpu The cross context virtual CPU structure.
7173 * @param pszInstr The VMX instruction name (for logging purposes).
7174 */
7175IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7176{
7177 /*
7178 * Pending debug exceptions.
7179 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7180 */
7181 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7182 Assert(pVmcs);
7183
7184 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7185 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7186 if (fPendingDbgXcpt)
7187 {
7188 uint8_t uEntryIntInfoType;
7189 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7190 if (fEntryVectoring)
7191 {
7192 switch (uEntryIntInfoType)
7193 {
7194 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7195 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7196 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7197 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7198 fPendingDbgXcpt = false;
7199 break;
7200
7201 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7202 {
7203 /*
7204 * Whether the pending debug exception for software exceptions other than
7205 * #BP and #OF is delivered after injecting the exception or is discard
7206 * is CPU implementation specific. We will discard them (easier).
7207 */
7208 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7209 if ( uVector != X86_XCPT_BP
7210 && uVector != X86_XCPT_OF)
7211 fPendingDbgXcpt = false;
7212 RT_FALL_THRU();
7213 }
7214 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7215 {
7216 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7217 fPendingDbgXcpt = false;
7218 break;
7219 }
7220 }
7221 }
7222 else
7223 {
7224 /*
7225 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7226 * pending debug exception is held pending or is discarded is CPU implementation
7227 * specific. We will discard them (easier).
7228 */
7229 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7230 fPendingDbgXcpt = false;
7231
7232 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7233 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7234 fPendingDbgXcpt = false;
7235 }
7236 }
7237
7238 NOREF(pszInstr);
7239 return fPendingDbgXcpt;
7240}
7241
7242
7243/**
7244 * Set up the monitor-trap flag (MTF).
7245 *
7246 * @param pVCpu The cross context virtual CPU structure.
7247 * @param pszInstr The VMX instruction name (for logging purposes).
7248 */
7249IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7250{
7251 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7252 Assert(pVmcs);
7253 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7254 {
7255 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7256 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7257 }
7258 else
7259 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7260 NOREF(pszInstr);
7261}
7262
7263
7264/**
7265 * Set up the VMX-preemption timer.
7266 *
7267 * @param pVCpu The cross context virtual CPU structure.
7268 * @param pszInstr The VMX instruction name (for logging purposes).
7269 */
7270IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7271{
7272 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7273 Assert(pVmcs);
7274 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7275 {
7276 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7277 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7278 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7279
7280 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7281 }
7282 else
7283 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7284
7285 NOREF(pszInstr);
7286}
7287
7288
7289/**
7290 * Injects an event using TRPM given a VM-entry interruption info. and related
7291 * fields.
7292 *
7293 * @returns VBox status code.
7294 * @param pVCpu The cross context virtual CPU structure.
7295 * @param uEntryIntInfo The VM-entry interruption info.
7296 * @param uErrCode The error code associated with the event if any.
7297 * @param cbInstr The VM-entry instruction length (for software
7298 * interrupts and software exceptions). Pass 0
7299 * otherwise.
7300 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7301 */
7302IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7303 RTGCUINTPTR GCPtrFaultAddress)
7304{
7305 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7306
7307 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7308 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7309 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7310
7311 TRPMEVENT enmTrapType;
7312 switch (uType)
7313 {
7314 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7315 enmTrapType = TRPM_HARDWARE_INT;
7316 break;
7317
7318 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7319 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7320 enmTrapType = TRPM_TRAP;
7321 break;
7322
7323 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7324 enmTrapType = TRPM_SOFTWARE_INT;
7325 break;
7326
7327 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7328 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7329 enmTrapType = TRPM_SOFTWARE_INT;
7330 break;
7331
7332 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7333 Assert(uVector == X86_XCPT_DB);
7334 enmTrapType = TRPM_SOFTWARE_INT;
7335 break;
7336
7337 default:
7338 /* Shouldn't really happen. */
7339 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7340 break;
7341 }
7342
7343 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7344 AssertRCReturn(rc, rc);
7345
7346 if (fErrCodeValid)
7347 TRPMSetErrorCode(pVCpu, uErrCode);
7348
7349 if ( enmTrapType == TRPM_TRAP
7350 && uVector == X86_XCPT_PF)
7351 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7352 else if (enmTrapType == TRPM_SOFTWARE_INT)
7353 TRPMSetInstrLength(pVCpu, cbInstr);
7354
7355 return VINF_SUCCESS;
7356}
7357
7358
7359/**
7360 * Performs event injection (if any) as part of VM-entry.
7361 *
7362 * @param pVCpu The cross context virtual CPU structure.
7363 * @param pszInstr The VMX instruction name (for logging purposes).
7364 */
7365IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7366{
7367 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7368
7369 /*
7370 * Inject events.
7371 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7372 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7373 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7374 * the actually delivery of this event.
7375 *
7376 * See Intel spec. 26.5 "Event Injection".
7377 */
7378 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7379 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7380
7381 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7382 if (fEntryIntInfoValid)
7383 {
7384 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7385 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7386 {
7387 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7388 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7389 return VINF_SUCCESS;
7390 }
7391
7392 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7393 pVCpu->cpum.GstCtx.cr2);
7394 if (RT_SUCCESS(rc))
7395 {
7396 /*
7397 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7398 *
7399 * However, we do it here on VM-entry because while it continues to not be visible to
7400 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7401 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7402 * information field.
7403 *
7404 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7405 */
7406 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7407 }
7408 return rc;
7409 }
7410
7411 /*
7412 * Inject any pending guest debug exception.
7413 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7414 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7415 */
7416 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7417 if (fPendingDbgXcpt)
7418 {
7419 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7420 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7421 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7422 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7423 0 /* GCPtrFaultAddress */);
7424 }
7425
7426 NOREF(pszInstr);
7427 return VINF_SUCCESS;
7428}
7429
7430
7431/**
7432 * Initializes all read-only VMCS fields as part of VM-entry.
7433 *
7434 * @param pVCpu The cross context virtual CPU structure.
7435 */
7436IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7437{
7438 /*
7439 * Any VMCS field which we do not establish on every VM-exit but may potentially
7440 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7441 * specified to be undefined needs to be initialized here.
7442 *
7443 * Thus, it is especially important to clear the VM-exit qualification field
7444 * since it must be zero for VM-exits where it is not used. Similarly, the
7445 * VM-exit interruption information field's valid bit needs to be cleared for
7446 * the same reasons.
7447 */
7448 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7449 Assert(pVmcs);
7450
7451 /* 16-bit (none currently). */
7452 /* 32-bit. */
7453 pVmcs->u32RoVmInstrError = 0;
7454 pVmcs->u32RoExitReason = 0;
7455 pVmcs->u32RoExitIntInfo = 0;
7456 pVmcs->u32RoExitIntErrCode = 0;
7457 pVmcs->u32RoIdtVectoringInfo = 0;
7458 pVmcs->u32RoIdtVectoringErrCode = 0;
7459 pVmcs->u32RoExitInstrLen = 0;
7460 pVmcs->u32RoExitInstrInfo = 0;
7461
7462 /* 64-bit. */
7463 pVmcs->u64RoGuestPhysAddr.u = 0;
7464
7465 /* Natural-width. */
7466 pVmcs->u64RoExitQual.u = 0;
7467 pVmcs->u64RoIoRcx.u = 0;
7468 pVmcs->u64RoIoRsi.u = 0;
7469 pVmcs->u64RoIoRdi.u = 0;
7470 pVmcs->u64RoIoRip.u = 0;
7471 pVmcs->u64RoGuestLinearAddr.u = 0;
7472}
7473
7474
7475/**
7476 * VMLAUNCH/VMRESUME instruction execution worker.
7477 *
7478 * @returns Strict VBox status code.
7479 * @param pVCpu The cross context virtual CPU structure.
7480 * @param cbInstr The instruction length in bytes.
7481 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7482 * VMXINSTRID_VMRESUME).
7483 *
7484 * @remarks Common VMX instruction checks are already expected to by the caller,
7485 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7486 */
7487IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7488{
7489# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7490 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7491 return VINF_EM_RAW_EMULATE_INSTR;
7492# else
7493 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7494 || uInstrId == VMXINSTRID_VMRESUME);
7495 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7496
7497 /* Nested-guest intercept. */
7498 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7499 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7500
7501 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7502
7503 /*
7504 * Basic VM-entry checks.
7505 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7506 * The checks following that do not have to follow a specific order.
7507 *
7508 * See Intel spec. 26.1 "Basic VM-entry Checks".
7509 */
7510
7511 /* CPL. */
7512 if (pVCpu->iem.s.uCpl == 0)
7513 { /* likely */ }
7514 else
7515 {
7516 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7518 return iemRaiseGeneralProtectionFault0(pVCpu);
7519 }
7520
7521 /* Current VMCS valid. */
7522 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7523 { /* likely */ }
7524 else
7525 {
7526 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7527 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7528 iemVmxVmFailInvalid(pVCpu);
7529 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7530 return VINF_SUCCESS;
7531 }
7532
7533 /* Current VMCS is not a shadow VMCS. */
7534 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7535 { /* likely */ }
7536 else
7537 {
7538 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7539 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7540 iemVmxVmFailInvalid(pVCpu);
7541 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7542 return VINF_SUCCESS;
7543 }
7544
7545 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7546 * use block-by-STI here which is not quite correct. */
7547 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7548 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7549 { /* likely */ }
7550 else
7551 {
7552 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7553 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7554 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7556 return VINF_SUCCESS;
7557 }
7558
7559 if (uInstrId == VMXINSTRID_VMLAUNCH)
7560 {
7561 /* VMLAUNCH with non-clear VMCS. */
7562 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7563 { /* likely */ }
7564 else
7565 {
7566 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7567 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7568 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7569 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7570 return VINF_SUCCESS;
7571 }
7572 }
7573 else
7574 {
7575 /* VMRESUME with non-launched VMCS. */
7576 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7577 { /* likely */ }
7578 else
7579 {
7580 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7582 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7583 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7584 return VINF_SUCCESS;
7585 }
7586 }
7587
7588 /*
7589 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7590 * while entering VMX non-root mode. We do some of this while checking VM-execution
7591 * controls. The guest hypervisor should not make assumptions and cannot expect
7592 * predictable behavior if changes to these structures are made in guest memory while
7593 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7594 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7595 *
7596 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7597 */
7598 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7599 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7600 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7601 if (RT_SUCCESS(rc))
7602 {
7603 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7604 if (RT_SUCCESS(rc))
7605 {
7606 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7607 if (RT_SUCCESS(rc))
7608 {
7609 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7610 if (RT_SUCCESS(rc))
7611 {
7612 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7613 iemVmxVmentryInitReadOnlyFields(pVCpu);
7614
7615 /*
7616 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7617 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7618 * VM-exit when required.
7619 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7620 */
7621 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7622
7623 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7624 if (RT_SUCCESS(rc))
7625 {
7626 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7627 if (RT_SUCCESS(rc))
7628 {
7629 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7630 if (RT_SUCCESS(rc))
7631 {
7632 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7633
7634 /* VMLAUNCH instruction must update the VMCS launch state. */
7635 if (uInstrId == VMXINSTRID_VMLAUNCH)
7636 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7637
7638 /* Perform the VMX transition (PGM updates). */
7639 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7640 if (rcStrict == VINF_SUCCESS)
7641 { /* likely */ }
7642 else if (RT_SUCCESS(rcStrict))
7643 {
7644 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7645 VBOXSTRICTRC_VAL(rcStrict)));
7646 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7647 }
7648 else
7649 {
7650 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7651 return rcStrict;
7652 }
7653
7654 /* We've now entered nested-guest execution. */
7655 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7656
7657 /*
7658 * The priority of potential VM-exits during VM-entry is important.
7659 * The priorities of VM-exits and events are listed from highest
7660 * to lowest as follows:
7661 *
7662 * 1. Event injection.
7663 * 2. Trap on task-switch (T flag set in TSS).
7664 * 3. TPR below threshold / APIC-write.
7665 * 4. SMI, INIT.
7666 * 5. MTF exit.
7667 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7668 * 7. VMX-preemption timer.
7669 * 9. NMI-window exit.
7670 * 10. NMI injection.
7671 * 11. Interrupt-window exit.
7672 * 12. Virtual-interrupt injection.
7673 * 13. Interrupt injection.
7674 * 14. Process next instruction (fetch, decode, execute).
7675 */
7676
7677 /* Setup the VMX-preemption timer. */
7678 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7679
7680 /* Setup monitor-trap flag. */
7681 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7682
7683 /* Now that we've switched page tables, we can go ahead and inject any event. */
7684 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7685 if (RT_SUCCESS(rcStrict))
7686 {
7687 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7688# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7689 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7690 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7691 if (rcSched != VINF_SUCCESS)
7692 iemSetPassUpStatus(pVCpu, rcSched);
7693# endif
7694 return VINF_SUCCESS;
7695 }
7696
7697 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7698 return rcStrict;
7699 }
7700 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7701 }
7702 }
7703 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7704 }
7705
7706 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7707 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7708 return VINF_SUCCESS;
7709 }
7710 }
7711 }
7712
7713 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7714 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7715 return VINF_SUCCESS;
7716# endif
7717}
7718
7719
7720/**
7721 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7722 * (causes a VM-exit) or not.
7723 *
7724 * @returns @c true if the instruction is intercepted, @c false otherwise.
7725 * @param pVCpu The cross context virtual CPU structure.
7726 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7727 * VMX_EXIT_WRMSR).
7728 * @param idMsr The MSR.
7729 */
7730IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7731{
7732 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7733 Assert( uExitReason == VMX_EXIT_RDMSR
7734 || uExitReason == VMX_EXIT_WRMSR);
7735
7736 /* Consult the MSR bitmap if the feature is supported. */
7737 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7738 Assert(pVmcs);
7739 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7740 {
7741 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7742 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7743 if (uExitReason == VMX_EXIT_RDMSR)
7744 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7745 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7746 }
7747
7748 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7749 return true;
7750}
7751
7752
7753/**
7754 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7755 * intercepted (causes a VM-exit) or not.
7756 *
7757 * @returns @c true if the instruction is intercepted, @c false otherwise.
7758 * @param pVCpu The cross context virtual CPU structure.
7759 * @param u64FieldEnc The VMCS field encoding.
7760 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7761 * VMX_EXIT_VMREAD).
7762 */
7763IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7764{
7765 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7766 Assert( uExitReason == VMX_EXIT_VMREAD
7767 || uExitReason == VMX_EXIT_VMWRITE);
7768
7769 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7770 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7771 return true;
7772
7773 /*
7774 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7775 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7776 */
7777 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7778 return true;
7779
7780 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7781 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7782 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7783 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7784 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7785 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7786 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7787 pbBitmap += (u32FieldEnc >> 3);
7788 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7789 return true;
7790
7791 return false;
7792}
7793
7794
7795/**
7796 * VMREAD common (memory/register) instruction execution worker
7797 *
7798 * @returns Strict VBox status code.
7799 * @param pVCpu The cross context virtual CPU structure.
7800 * @param cbInstr The instruction length in bytes.
7801 * @param pu64Dst Where to write the VMCS value (only updated when
7802 * VINF_SUCCESS is returned).
7803 * @param u64FieldEnc The VMCS field encoding.
7804 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7805 * be NULL.
7806 */
7807IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7808 PCVMXVEXITINFO pExitInfo)
7809{
7810 /* Nested-guest intercept. */
7811 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7812 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7813 {
7814 if (pExitInfo)
7815 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7816 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7817 }
7818
7819 /* CPL. */
7820 if (pVCpu->iem.s.uCpl == 0)
7821 { /* likely */ }
7822 else
7823 {
7824 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7825 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7826 return iemRaiseGeneralProtectionFault0(pVCpu);
7827 }
7828
7829 /* VMCS pointer in root mode. */
7830 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7831 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7832 { /* likely */ }
7833 else
7834 {
7835 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7836 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7837 iemVmxVmFailInvalid(pVCpu);
7838 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7839 return VINF_SUCCESS;
7840 }
7841
7842 /* VMCS-link pointer in non-root mode. */
7843 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7844 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7845 { /* likely */ }
7846 else
7847 {
7848 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7849 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7850 iemVmxVmFailInvalid(pVCpu);
7851 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7852 return VINF_SUCCESS;
7853 }
7854
7855 /* Supported VMCS field. */
7856 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7857 { /* likely */ }
7858 else
7859 {
7860 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7862 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7863 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7864 return VINF_SUCCESS;
7865 }
7866
7867 /*
7868 * Setup reading from the current or shadow VMCS.
7869 */
7870 uint8_t *pbVmcs;
7871 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7872 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7873 else
7874 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7875 Assert(pbVmcs);
7876
7877 VMXVMCSFIELDENC FieldEnc;
7878 FieldEnc.u = u64FieldEnc;
7879 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7880 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7881 uint8_t const uWidthType = (uWidth << 2) | uType;
7882 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7883 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7884 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7885 Assert(offField < VMX_V_VMCS_SIZE);
7886
7887 /*
7888 * Read the VMCS component based on the field's effective width.
7889 *
7890 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7891 * indicates high bits (little endian).
7892 *
7893 * Note! The caller is responsible to trim the result and update registers
7894 * or memory locations are required. Here we just zero-extend to the largest
7895 * type (i.e. 64-bits).
7896 */
7897 uint8_t *pbField = pbVmcs + offField;
7898 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7899 switch (uEffWidth)
7900 {
7901 case VMX_VMCS_ENC_WIDTH_64BIT:
7902 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7903 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7904 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7905 }
7906 return VINF_SUCCESS;
7907}
7908
7909
7910/**
7911 * VMREAD (64-bit register) instruction execution worker.
7912 *
7913 * @returns Strict VBox status code.
7914 * @param pVCpu The cross context virtual CPU structure.
7915 * @param cbInstr The instruction length in bytes.
7916 * @param pu64Dst Where to store the VMCS field's value.
7917 * @param u64FieldEnc The VMCS field encoding.
7918 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7919 * be NULL.
7920 */
7921IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7922 PCVMXVEXITINFO pExitInfo)
7923{
7924 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7925 if (rcStrict == VINF_SUCCESS)
7926 {
7927 iemVmxVmreadSuccess(pVCpu, cbInstr);
7928 return VINF_SUCCESS;
7929 }
7930
7931 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7932 return rcStrict;
7933}
7934
7935
7936/**
7937 * VMREAD (32-bit register) instruction execution worker.
7938 *
7939 * @returns Strict VBox status code.
7940 * @param pVCpu The cross context virtual CPU structure.
7941 * @param cbInstr The instruction length in bytes.
7942 * @param pu32Dst Where to store the VMCS field's value.
7943 * @param u32FieldEnc The VMCS field encoding.
7944 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7945 * be NULL.
7946 */
7947IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7948 PCVMXVEXITINFO pExitInfo)
7949{
7950 uint64_t u64Dst;
7951 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7952 if (rcStrict == VINF_SUCCESS)
7953 {
7954 *pu32Dst = u64Dst;
7955 iemVmxVmreadSuccess(pVCpu, cbInstr);
7956 return VINF_SUCCESS;
7957 }
7958
7959 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7960 return rcStrict;
7961}
7962
7963
7964/**
7965 * VMREAD (memory) instruction execution worker.
7966 *
7967 * @returns Strict VBox status code.
7968 * @param pVCpu The cross context virtual CPU structure.
7969 * @param cbInstr The instruction length in bytes.
7970 * @param iEffSeg The effective segment register to use with @a u64Val.
7971 * Pass UINT8_MAX if it is a register access.
7972 * @param GCPtrDst The guest linear address to store the VMCS field's
7973 * value.
7974 * @param u64FieldEnc The VMCS field encoding.
7975 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7976 * be NULL.
7977 */
7978IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
7979 PCVMXVEXITINFO pExitInfo)
7980{
7981 uint64_t u64Dst;
7982 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7983 if (rcStrict == VINF_SUCCESS)
7984 {
7985 /*
7986 * Write the VMCS field's value to the location specified in guest-memory.
7987 */
7988 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7989 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7990 else
7991 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7992 if (rcStrict == VINF_SUCCESS)
7993 {
7994 iemVmxVmreadSuccess(pVCpu, cbInstr);
7995 return VINF_SUCCESS;
7996 }
7997
7998 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7999 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8000 return rcStrict;
8001 }
8002
8003 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8004 return rcStrict;
8005}
8006
8007
8008/**
8009 * VMWRITE instruction execution worker.
8010 *
8011 * @returns Strict VBox status code.
8012 * @param pVCpu The cross context virtual CPU structure.
8013 * @param cbInstr The instruction length in bytes.
8014 * @param iEffSeg The effective segment register to use with @a u64Val.
8015 * Pass UINT8_MAX if it is a register access.
8016 * @param u64Val The value to write (or guest linear address to the
8017 * value), @a iEffSeg will indicate if it's a memory
8018 * operand.
8019 * @param u64FieldEnc The VMCS field encoding.
8020 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8021 * be NULL.
8022 */
8023IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8024 PCVMXVEXITINFO pExitInfo)
8025{
8026 /* Nested-guest intercept. */
8027 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8028 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8029 {
8030 if (pExitInfo)
8031 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8032 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8033 }
8034
8035 /* CPL. */
8036 if (pVCpu->iem.s.uCpl == 0)
8037 { /* likely */ }
8038 else
8039 {
8040 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8041 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8042 return iemRaiseGeneralProtectionFault0(pVCpu);
8043 }
8044
8045 /* VMCS pointer in root mode. */
8046 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8047 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8048 { /* likely */ }
8049 else
8050 {
8051 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8052 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8053 iemVmxVmFailInvalid(pVCpu);
8054 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8055 return VINF_SUCCESS;
8056 }
8057
8058 /* VMCS-link pointer in non-root mode. */
8059 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8060 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8061 { /* likely */ }
8062 else
8063 {
8064 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8065 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8066 iemVmxVmFailInvalid(pVCpu);
8067 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8068 return VINF_SUCCESS;
8069 }
8070
8071 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8072 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8073 if (!fIsRegOperand)
8074 {
8075 /* Read the value from the specified guest memory location. */
8076 VBOXSTRICTRC rcStrict;
8077 RTGCPTR const GCPtrVal = u64Val;
8078 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8079 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8080 else
8081 {
8082 uint32_t u32Val;
8083 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8084 u64Val = u32Val;
8085 }
8086 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8087 {
8088 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8089 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8090 return rcStrict;
8091 }
8092 }
8093 else
8094 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8095
8096 /* Supported VMCS field. */
8097 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8098 { /* likely */ }
8099 else
8100 {
8101 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8102 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8103 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8104 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8105 return VINF_SUCCESS;
8106 }
8107
8108 /* Read-only VMCS field. */
8109 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8110 if ( !fIsFieldReadOnly
8111 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8112 { /* likely */ }
8113 else
8114 {
8115 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8116 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8117 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8118 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8119 return VINF_SUCCESS;
8120 }
8121
8122 /*
8123 * Setup writing to the current or shadow VMCS.
8124 */
8125 uint8_t *pbVmcs;
8126 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8127 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8128 else
8129 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8130 Assert(pbVmcs);
8131
8132 VMXVMCSFIELDENC FieldEnc;
8133 FieldEnc.u = u64FieldEnc;
8134 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8135 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8136 uint8_t const uWidthType = (uWidth << 2) | uType;
8137 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8138 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8139 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8140 Assert(offField < VMX_V_VMCS_SIZE);
8141
8142 /*
8143 * Write the VMCS component based on the field's effective width.
8144 *
8145 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8146 * indicates high bits (little endian).
8147 */
8148 uint8_t *pbField = pbVmcs + offField;
8149 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8150 switch (uEffWidth)
8151 {
8152 case VMX_VMCS_ENC_WIDTH_64BIT:
8153 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8154 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8155 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8156 }
8157
8158 iemVmxVmSucceed(pVCpu);
8159 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8160 return VINF_SUCCESS;
8161}
8162
8163
8164/**
8165 * VMCLEAR instruction execution worker.
8166 *
8167 * @returns Strict VBox status code.
8168 * @param pVCpu The cross context virtual CPU structure.
8169 * @param cbInstr The instruction length in bytes.
8170 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8171 * @param GCPtrVmcs The linear address of the VMCS pointer.
8172 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8173 * be NULL.
8174 *
8175 * @remarks Common VMX instruction checks are already expected to by the caller,
8176 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8177 */
8178IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8179 PCVMXVEXITINFO pExitInfo)
8180{
8181 /* Nested-guest intercept. */
8182 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8183 {
8184 if (pExitInfo)
8185 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8186 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8187 }
8188
8189 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8190
8191 /* CPL. */
8192 if (pVCpu->iem.s.uCpl == 0)
8193 { /* likely */ }
8194 else
8195 {
8196 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8197 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8198 return iemRaiseGeneralProtectionFault0(pVCpu);
8199 }
8200
8201 /* Get the VMCS pointer from the location specified by the source memory operand. */
8202 RTGCPHYS GCPhysVmcs;
8203 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8204 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8205 { /* likely */ }
8206 else
8207 {
8208 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8209 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8210 return rcStrict;
8211 }
8212
8213 /* VMCS pointer alignment. */
8214 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8215 { /* likely */ }
8216 else
8217 {
8218 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8219 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8220 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8221 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8222 return VINF_SUCCESS;
8223 }
8224
8225 /* VMCS physical-address width limits. */
8226 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8227 { /* likely */ }
8228 else
8229 {
8230 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8231 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8232 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8233 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8234 return VINF_SUCCESS;
8235 }
8236
8237 /* VMCS is not the VMXON region. */
8238 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8239 { /* likely */ }
8240 else
8241 {
8242 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8243 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8244 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8246 return VINF_SUCCESS;
8247 }
8248
8249 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8250 restriction imposed by our implementation. */
8251 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8252 { /* likely */ }
8253 else
8254 {
8255 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8256 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8257 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8258 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8259 return VINF_SUCCESS;
8260 }
8261
8262 /*
8263 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8264 *
8265 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8266 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8267 * to 'clear'.
8268 */
8269 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8270 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8271 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8272 {
8273 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8274 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8275 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8276 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8277 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8278 }
8279 else
8280 {
8281 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8282 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8283 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8284 if (RT_FAILURE(rcStrict))
8285 return rcStrict;
8286 }
8287
8288 iemVmxVmSucceed(pVCpu);
8289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8290 return VINF_SUCCESS;
8291}
8292
8293
8294/**
8295 * VMPTRST instruction execution worker.
8296 *
8297 * @returns Strict VBox status code.
8298 * @param pVCpu The cross context virtual CPU structure.
8299 * @param cbInstr The instruction length in bytes.
8300 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8301 * @param GCPtrVmcs The linear address of where to store the current VMCS
8302 * pointer.
8303 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8304 * be NULL.
8305 *
8306 * @remarks Common VMX instruction checks are already expected to by the caller,
8307 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8308 */
8309IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8310 PCVMXVEXITINFO pExitInfo)
8311{
8312 /* Nested-guest intercept. */
8313 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8314 {
8315 if (pExitInfo)
8316 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8317 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8318 }
8319
8320 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8321
8322 /* CPL. */
8323 if (pVCpu->iem.s.uCpl == 0)
8324 { /* likely */ }
8325 else
8326 {
8327 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8329 return iemRaiseGeneralProtectionFault0(pVCpu);
8330 }
8331
8332 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8333 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8334 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8335 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8336 {
8337 iemVmxVmSucceed(pVCpu);
8338 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8339 return rcStrict;
8340 }
8341
8342 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8343 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8344 return rcStrict;
8345}
8346
8347
8348/**
8349 * VMPTRLD instruction execution worker.
8350 *
8351 * @returns Strict VBox status code.
8352 * @param pVCpu The cross context virtual CPU structure.
8353 * @param cbInstr The instruction length in bytes.
8354 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8355 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8356 * be NULL.
8357 *
8358 * @remarks Common VMX instruction checks are already expected to by the caller,
8359 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8360 */
8361IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8362 PCVMXVEXITINFO pExitInfo)
8363{
8364 /* Nested-guest intercept. */
8365 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8366 {
8367 if (pExitInfo)
8368 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8369 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8370 }
8371
8372 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8373
8374 /* CPL. */
8375 if (pVCpu->iem.s.uCpl == 0)
8376 { /* likely */ }
8377 else
8378 {
8379 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8380 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8381 return iemRaiseGeneralProtectionFault0(pVCpu);
8382 }
8383
8384 /* Get the VMCS pointer from the location specified by the source memory operand. */
8385 RTGCPHYS GCPhysVmcs;
8386 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8387 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8388 { /* likely */ }
8389 else
8390 {
8391 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8393 return rcStrict;
8394 }
8395
8396 /* VMCS pointer alignment. */
8397 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8398 { /* likely */ }
8399 else
8400 {
8401 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8402 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8403 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8404 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8405 return VINF_SUCCESS;
8406 }
8407
8408 /* VMCS physical-address width limits. */
8409 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8410 { /* likely */ }
8411 else
8412 {
8413 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8416 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8417 return VINF_SUCCESS;
8418 }
8419
8420 /* VMCS is not the VMXON region. */
8421 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8427 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8429 return VINF_SUCCESS;
8430 }
8431
8432 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8433 restriction imposed by our implementation. */
8434 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8435 { /* likely */ }
8436 else
8437 {
8438 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8439 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8440 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8441 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8442 return VINF_SUCCESS;
8443 }
8444
8445 /* Read just the VMCS revision from the VMCS. */
8446 VMXVMCSREVID VmcsRevId;
8447 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8448 if (RT_SUCCESS(rc))
8449 { /* likely */ }
8450 else
8451 {
8452 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8454 return rc;
8455 }
8456
8457 /*
8458 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8459 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8460 */
8461 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8462 && ( !VmcsRevId.n.fIsShadowVmcs
8463 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8464 { /* likely */ }
8465 else
8466 {
8467 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8468 {
8469 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8470 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8471 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8472 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8473 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8474 return VINF_SUCCESS;
8475 }
8476
8477 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8478 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8479 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8480 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8481 return VINF_SUCCESS;
8482 }
8483
8484 /*
8485 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8486 * the cache of an existing, current VMCS back to guest memory before loading a new,
8487 * different current VMCS.
8488 */
8489 bool fLoadVmcsFromMem;
8490 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8491 {
8492 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8493 {
8494 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8495 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8496 fLoadVmcsFromMem = true;
8497 }
8498 else
8499 fLoadVmcsFromMem = false;
8500 }
8501 else
8502 fLoadVmcsFromMem = true;
8503
8504 if (fLoadVmcsFromMem)
8505 {
8506 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8507 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8508 sizeof(VMXVVMCS));
8509 if (RT_SUCCESS(rc))
8510 { /* likely */ }
8511 else
8512 {
8513 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8514 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8515 return rc;
8516 }
8517 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8518 }
8519
8520 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8521 iemVmxVmSucceed(pVCpu);
8522 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8523 return VINF_SUCCESS;
8524}
8525
8526
8527/**
8528 * INVVPID instruction execution worker.
8529 *
8530 * @returns Strict VBox status code.
8531 * @param pVCpu The cross context virtual CPU structure.
8532 * @param cbInstr The instruction length in bytes.
8533 * @param iEffSeg The segment of the invvpid descriptor.
8534 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8535 * @param u64InvvpidType The invalidation type.
8536 * @param pExitInfo Pointer to the VM-exit information struct. Optional,
8537 * can be NULL.
8538 *
8539 * @remarks Common VMX instruction checks are already expected to by the caller,
8540 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8541 */
8542IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8543 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8544{
8545 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8546 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8547 return iemRaiseUndefinedOpcode(pVCpu);
8548
8549 /* Nested-guest intercept. */
8550 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8551 {
8552 if (pExitInfo)
8553 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8554 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8555 }
8556
8557 /* CPL. */
8558 if (pVCpu->iem.s.uCpl != 0)
8559 {
8560 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8561 return iemRaiseGeneralProtectionFault0(pVCpu);
8562 }
8563
8564 /*
8565 * Validate INVVPID invalidation type.
8566 *
8567 * The instruction specifies exactly ONE of the supported invalidation types.
8568 *
8569 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8570 * supported. In theory, it's possible for a CPU to not support flushing individual
8571 * addresses but all the other types or any other combination. We do not take any
8572 * shortcuts here by assuming the types we currently expose to the guest.
8573 */
8574 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8575 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8576 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8577 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8578 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8579 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8580 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8581 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8582 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8583 { /* likely */ }
8584 else
8585 {
8586 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8588 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8590 return VINF_SUCCESS;
8591 }
8592
8593 /*
8594 * Fetch the invvpid descriptor from guest memory.
8595 */
8596 RTUINT128U uDesc;
8597 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8598 if (rcStrict == VINF_SUCCESS)
8599 {
8600 /*
8601 * Validate the descriptor.
8602 */
8603 if (uDesc.s.Lo > 0xfff)
8604 {
8605 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8607 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8609 return VINF_SUCCESS;
8610 }
8611
8612 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8613 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8614 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8615 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8616 switch (u64InvvpidType)
8617 {
8618 case VMXTLBFLUSHVPID_INDIV_ADDR:
8619 {
8620 if (uVpid != 0)
8621 {
8622 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8623 {
8624 /* Invalidate mappings for the linear address tagged with VPID. */
8625 /** @todo PGM support for VPID? Currently just flush everything. */
8626 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8627 iemVmxVmSucceed(pVCpu);
8628 }
8629 else
8630 {
8631 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8632 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8633 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8634 }
8635 }
8636 else
8637 {
8638 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8640 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8641 }
8642 break;
8643 }
8644
8645 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8646 {
8647 if (uVpid != 0)
8648 {
8649 /* Invalidate all mappings with VPID. */
8650 /** @todo PGM support for VPID? Currently just flush everything. */
8651 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8652 iemVmxVmSucceed(pVCpu);
8653 }
8654 else
8655 {
8656 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8657 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8658 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8659 }
8660 break;
8661 }
8662
8663 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8664 {
8665 /* Invalidate all mappings with non-zero VPIDs. */
8666 /** @todo PGM support for VPID? Currently just flush everything. */
8667 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8668 iemVmxVmSucceed(pVCpu);
8669 break;
8670 }
8671
8672 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8673 {
8674 if (uVpid != 0)
8675 {
8676 /* Invalidate all mappings with VPID except global translations. */
8677 /** @todo PGM support for VPID? Currently just flush everything. */
8678 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8679 iemVmxVmSucceed(pVCpu);
8680 }
8681 else
8682 {
8683 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8684 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8685 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8686 }
8687 break;
8688 }
8689 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8690 }
8691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8692 }
8693 return rcStrict;
8694}
8695
8696
8697/**
8698 * VMXON instruction execution worker.
8699 *
8700 * @returns Strict VBox status code.
8701 * @param pVCpu The cross context virtual CPU structure.
8702 * @param cbInstr The instruction length in bytes.
8703 * @param iEffSeg The effective segment register to use with @a
8704 * GCPtrVmxon.
8705 * @param GCPtrVmxon The linear address of the VMXON pointer.
8706 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8707 * Optional, can be NULL.
8708 *
8709 * @remarks Common VMX instruction checks are already expected to by the caller,
8710 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8711 */
8712IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8713 PCVMXVEXITINFO pExitInfo)
8714{
8715 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8716 {
8717 /* CPL. */
8718 if (pVCpu->iem.s.uCpl == 0)
8719 { /* likely */ }
8720 else
8721 {
8722 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8723 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8724 return iemRaiseGeneralProtectionFault0(pVCpu);
8725 }
8726
8727 /* A20M (A20 Masked) mode. */
8728 if (PGMPhysIsA20Enabled(pVCpu))
8729 { /* likely */ }
8730 else
8731 {
8732 Log(("vmxon: A20M mode -> #GP(0)\n"));
8733 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8734 return iemRaiseGeneralProtectionFault0(pVCpu);
8735 }
8736
8737 /* CR0. */
8738 {
8739 /* CR0 MB1 bits. */
8740 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8741 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8742 { /* likely */ }
8743 else
8744 {
8745 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8746 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8747 return iemRaiseGeneralProtectionFault0(pVCpu);
8748 }
8749
8750 /* CR0 MBZ bits. */
8751 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8752 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8753 { /* likely */ }
8754 else
8755 {
8756 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8757 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8758 return iemRaiseGeneralProtectionFault0(pVCpu);
8759 }
8760 }
8761
8762 /* CR4. */
8763 {
8764 /* CR4 MB1 bits. */
8765 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8766 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8767 { /* likely */ }
8768 else
8769 {
8770 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8771 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8772 return iemRaiseGeneralProtectionFault0(pVCpu);
8773 }
8774
8775 /* CR4 MBZ bits. */
8776 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8777 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8778 { /* likely */ }
8779 else
8780 {
8781 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8783 return iemRaiseGeneralProtectionFault0(pVCpu);
8784 }
8785 }
8786
8787 /* Feature control MSR's LOCK and VMXON bits. */
8788 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8789 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8790 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8791 { /* likely */ }
8792 else
8793 {
8794 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8795 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8796 return iemRaiseGeneralProtectionFault0(pVCpu);
8797 }
8798
8799 /* Get the VMXON pointer from the location specified by the source memory operand. */
8800 RTGCPHYS GCPhysVmxon;
8801 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8802 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8803 { /* likely */ }
8804 else
8805 {
8806 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8807 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8808 return rcStrict;
8809 }
8810
8811 /* VMXON region pointer alignment. */
8812 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8813 { /* likely */ }
8814 else
8815 {
8816 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8817 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8818 iemVmxVmFailInvalid(pVCpu);
8819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8820 return VINF_SUCCESS;
8821 }
8822
8823 /* VMXON physical-address width limits. */
8824 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8825 { /* likely */ }
8826 else
8827 {
8828 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8829 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8830 iemVmxVmFailInvalid(pVCpu);
8831 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8832 return VINF_SUCCESS;
8833 }
8834
8835 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8836 restriction imposed by our implementation. */
8837 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8838 { /* likely */ }
8839 else
8840 {
8841 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8843 iemVmxVmFailInvalid(pVCpu);
8844 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8845 return VINF_SUCCESS;
8846 }
8847
8848 /* Read the VMCS revision ID from the VMXON region. */
8849 VMXVMCSREVID VmcsRevId;
8850 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8851 if (RT_SUCCESS(rc))
8852 { /* likely */ }
8853 else
8854 {
8855 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8856 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8857 return rc;
8858 }
8859
8860 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8861 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8862 { /* likely */ }
8863 else
8864 {
8865 /* Revision ID mismatch. */
8866 if (!VmcsRevId.n.fIsShadowVmcs)
8867 {
8868 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8869 VmcsRevId.n.u31RevisionId));
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8871 iemVmxVmFailInvalid(pVCpu);
8872 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8873 return VINF_SUCCESS;
8874 }
8875
8876 /* Shadow VMCS disallowed. */
8877 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8878 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8879 iemVmxVmFailInvalid(pVCpu);
8880 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8881 return VINF_SUCCESS;
8882 }
8883
8884 /*
8885 * Record that we're in VMX operation, block INIT, block and disable A20M.
8886 */
8887 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8888 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8889 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8890
8891 /* Clear address-range monitoring. */
8892 EMMonitorWaitClear(pVCpu);
8893 /** @todo NSTVMX: Intel PT. */
8894
8895 iemVmxVmSucceed(pVCpu);
8896 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8897 return VINF_SUCCESS;
8898 }
8899 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8900 {
8901 /* Nested-guest intercept. */
8902 if (pExitInfo)
8903 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8904 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8905 }
8906
8907 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8908
8909 /* CPL. */
8910 if (pVCpu->iem.s.uCpl > 0)
8911 {
8912 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8913 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8914 return iemRaiseGeneralProtectionFault0(pVCpu);
8915 }
8916
8917 /* VMXON when already in VMX root mode. */
8918 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8919 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8920 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8921 return VINF_SUCCESS;
8922}
8923
8924
8925/**
8926 * Implements 'VMXOFF'.
8927 *
8928 * @remarks Common VMX instruction checks are already expected to by the caller,
8929 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8930 */
8931IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8932{
8933 /* Nested-guest intercept. */
8934 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8935 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8936
8937 /* CPL. */
8938 if (pVCpu->iem.s.uCpl == 0)
8939 { /* likely */ }
8940 else
8941 {
8942 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8943 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8944 return iemRaiseGeneralProtectionFault0(pVCpu);
8945 }
8946
8947 /* Dual monitor treatment of SMIs and SMM. */
8948 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8949 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8950 { /* likely */ }
8951 else
8952 {
8953 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8954 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8955 return VINF_SUCCESS;
8956 }
8957
8958 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8959 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8960 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8961
8962 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8963 { /** @todo NSTVMX: Unblock SMI. */ }
8964
8965 EMMonitorWaitClear(pVCpu);
8966 /** @todo NSTVMX: Unblock and enable A20M. */
8967
8968 iemVmxVmSucceed(pVCpu);
8969 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8970 return VINF_SUCCESS;
8971}
8972
8973
8974/**
8975 * Implements 'VMXON'.
8976 */
8977IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8978{
8979 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8980}
8981
8982
8983/**
8984 * Implements 'VMLAUNCH'.
8985 */
8986IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8987{
8988 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8989}
8990
8991
8992/**
8993 * Implements 'VMRESUME'.
8994 */
8995IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8996{
8997 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8998}
8999
9000
9001/**
9002 * Implements 'VMPTRLD'.
9003 */
9004IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9005{
9006 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9007}
9008
9009
9010/**
9011 * Implements 'VMPTRST'.
9012 */
9013IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9014{
9015 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9016}
9017
9018
9019/**
9020 * Implements 'VMCLEAR'.
9021 */
9022IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9023{
9024 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9025}
9026
9027
9028/**
9029 * Implements 'VMWRITE' register.
9030 */
9031IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9032{
9033 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9034}
9035
9036
9037/**
9038 * Implements 'VMWRITE' memory.
9039 */
9040IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9041{
9042 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9043}
9044
9045
9046/**
9047 * Implements 'VMREAD' register (64-bit).
9048 */
9049IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9050{
9051 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9052}
9053
9054
9055/**
9056 * Implements 'VMREAD' register (32-bit).
9057 */
9058IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9059{
9060 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9061}
9062
9063
9064/**
9065 * Implements 'VMREAD' memory, 64-bit register.
9066 */
9067IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9068{
9069 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9070}
9071
9072
9073/**
9074 * Implements 'VMREAD' memory, 32-bit register.
9075 */
9076IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9077{
9078 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9079}
9080
9081
9082/**
9083 * Implements 'INVVPID'.
9084 */
9085IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9086{
9087 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9088}
9089
9090
9091/**
9092 * Implements VMX's implementation of PAUSE.
9093 */
9094IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9095{
9096 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9097 {
9098 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9099 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9100 return rcStrict;
9101 }
9102
9103 /*
9104 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9105 * a VM-exit, the instruction operates normally.
9106 */
9107 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9108 return VINF_SUCCESS;
9109}
9110
9111#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9112
9113
9114/**
9115 * Implements 'VMCALL'.
9116 */
9117IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9118{
9119#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9120 /* Nested-guest intercept. */
9121 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9122 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9123#endif
9124
9125 /* Join forces with vmmcall. */
9126 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9127}
9128
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