VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78638

Last change on this file since 78638 was 78638, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Added IEMExecVmxVmexitTaskSwitch interface for handling VM-exits with decode info. from HM.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78638 2019-05-21 16:15:58Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
290 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
291 },
292 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
293 {
294 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
295 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
296 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
297 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
298 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
300 },
301 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
304 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
305 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
306 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
307 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
308 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
309 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
310 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
311 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
312 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
313 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
314 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
315 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
316 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
317 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
318 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
319 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
320 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
321 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
322 },
323 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
324 {
325 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
326 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
327 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
328 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
329 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
330 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
331 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
332 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
333 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 24-25 */ UINT16_MAX, UINT16_MAX
336 },
337 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
338 {
339 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
340 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
341 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
342 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
343 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
344 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
345 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
346 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
347 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
348 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
349 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
350 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
351 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
352 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
353 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
354 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
355 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
356 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
357 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
358 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
359 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
360 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
361 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
362 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
363 },
364 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
365 {
366 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
367 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
368 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 25 */ UINT16_MAX
371 },
372 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
373 {
374 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
375 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
376 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
377 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
378 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
379 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
380 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
381 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
382 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 24-25 */ UINT16_MAX, UINT16_MAX
385 },
386 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
387 {
388 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
389 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
390 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
391 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
392 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
393 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
394 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
397 },
398 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
399 {
400 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
401 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
402 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
403 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
404 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
405 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
406 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
407 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
408 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
409 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
410 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
411 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
412 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
413 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
414 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
415 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
416 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
417 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
418 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
419 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
420 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
421 },
422 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
423 {
424 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
425 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
426 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
427 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
428 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
429 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
430 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
431 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
432 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
433 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
434 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
435 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
436 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
437 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
438 }
439};
440
441
442/**
443 * Returns whether the given VMCS field is valid and supported by our emulation.
444 *
445 * @param pVCpu The cross context virtual CPU structure.
446 * @param u64FieldEnc The VMCS field encoding.
447 *
448 * @remarks This takes into account the CPU features exposed to the guest.
449 */
450IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
451{
452 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
453 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
454 if (!uFieldEncHi)
455 { /* likely */ }
456 else
457 return false;
458
459 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
460 switch (uFieldEncLo)
461 {
462 /*
463 * 16-bit fields.
464 */
465 /* Control fields. */
466 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
467 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
468 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
469
470 /* Guest-state fields. */
471 case VMX_VMCS16_GUEST_ES_SEL:
472 case VMX_VMCS16_GUEST_CS_SEL:
473 case VMX_VMCS16_GUEST_SS_SEL:
474 case VMX_VMCS16_GUEST_DS_SEL:
475 case VMX_VMCS16_GUEST_FS_SEL:
476 case VMX_VMCS16_GUEST_GS_SEL:
477 case VMX_VMCS16_GUEST_LDTR_SEL:
478 case VMX_VMCS16_GUEST_TR_SEL: return true;
479 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
480 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
481
482 /* Host-state fields. */
483 case VMX_VMCS16_HOST_ES_SEL:
484 case VMX_VMCS16_HOST_CS_SEL:
485 case VMX_VMCS16_HOST_SS_SEL:
486 case VMX_VMCS16_HOST_DS_SEL:
487 case VMX_VMCS16_HOST_FS_SEL:
488 case VMX_VMCS16_HOST_GS_SEL:
489 case VMX_VMCS16_HOST_TR_SEL: return true;
490
491 /*
492 * 64-bit fields.
493 */
494 /* Control fields. */
495 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
497 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
499 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
500 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
501 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
503 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
505 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
507 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
509 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
511 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
512 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
513 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
515 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
517 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
519 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
521 case VMX_VMCS64_CTRL_EPTP_FULL:
522 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
523 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
531 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
532 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
533 {
534 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
535 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
536 }
537 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
539 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
541 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
543 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
545 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
547 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
549
550 /* Read-only data fields. */
551 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
553
554 /* Guest-state fields. */
555 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
557 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
558 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
559 case VMX_VMCS64_GUEST_PAT_FULL:
560 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
561 case VMX_VMCS64_GUEST_EFER_FULL:
562 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
563 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
565 case VMX_VMCS64_GUEST_PDPTE0_FULL:
566 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
567 case VMX_VMCS64_GUEST_PDPTE1_FULL:
568 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
569 case VMX_VMCS64_GUEST_PDPTE2_FULL:
570 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
571 case VMX_VMCS64_GUEST_PDPTE3_FULL:
572 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
573 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
574 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
575
576 /* Host-state fields. */
577 case VMX_VMCS64_HOST_PAT_FULL:
578 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
579 case VMX_VMCS64_HOST_EFER_FULL:
580 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
581 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
583
584 /*
585 * 32-bit fields.
586 */
587 /* Control fields. */
588 case VMX_VMCS32_CTRL_PIN_EXEC:
589 case VMX_VMCS32_CTRL_PROC_EXEC:
590 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
591 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
593 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
594 case VMX_VMCS32_CTRL_EXIT:
595 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
597 case VMX_VMCS32_CTRL_ENTRY:
598 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
599 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
600 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
601 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
602 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
603 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
604 case VMX_VMCS32_CTRL_PLE_GAP:
605 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
606
607 /* Read-only data fields. */
608 case VMX_VMCS32_RO_VM_INSTR_ERROR:
609 case VMX_VMCS32_RO_EXIT_REASON:
610 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
612 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
613 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
614 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
615 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
616
617 /* Guest-state fields. */
618 case VMX_VMCS32_GUEST_ES_LIMIT:
619 case VMX_VMCS32_GUEST_CS_LIMIT:
620 case VMX_VMCS32_GUEST_SS_LIMIT:
621 case VMX_VMCS32_GUEST_DS_LIMIT:
622 case VMX_VMCS32_GUEST_FS_LIMIT:
623 case VMX_VMCS32_GUEST_GS_LIMIT:
624 case VMX_VMCS32_GUEST_LDTR_LIMIT:
625 case VMX_VMCS32_GUEST_TR_LIMIT:
626 case VMX_VMCS32_GUEST_GDTR_LIMIT:
627 case VMX_VMCS32_GUEST_IDTR_LIMIT:
628 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
629 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_INT_STATE:
637 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
638 case VMX_VMCS32_GUEST_SMBASE:
639 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
640 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
641
642 /* Host-state fields. */
643 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
644
645 /*
646 * Natural-width fields.
647 */
648 /* Control fields. */
649 case VMX_VMCS_CTRL_CR0_MASK:
650 case VMX_VMCS_CTRL_CR4_MASK:
651 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
652 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
657
658 /* Read-only data fields. */
659 case VMX_VMCS_RO_EXIT_QUALIFICATION:
660 case VMX_VMCS_RO_IO_RCX:
661 case VMX_VMCS_RO_IO_RSI:
662 case VMX_VMCS_RO_IO_RDI:
663 case VMX_VMCS_RO_IO_RIP:
664 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
665
666 /* Guest-state fields. */
667 case VMX_VMCS_GUEST_CR0:
668 case VMX_VMCS_GUEST_CR3:
669 case VMX_VMCS_GUEST_CR4:
670 case VMX_VMCS_GUEST_ES_BASE:
671 case VMX_VMCS_GUEST_CS_BASE:
672 case VMX_VMCS_GUEST_SS_BASE:
673 case VMX_VMCS_GUEST_DS_BASE:
674 case VMX_VMCS_GUEST_FS_BASE:
675 case VMX_VMCS_GUEST_GS_BASE:
676 case VMX_VMCS_GUEST_LDTR_BASE:
677 case VMX_VMCS_GUEST_TR_BASE:
678 case VMX_VMCS_GUEST_GDTR_BASE:
679 case VMX_VMCS_GUEST_IDTR_BASE:
680 case VMX_VMCS_GUEST_DR7:
681 case VMX_VMCS_GUEST_RSP:
682 case VMX_VMCS_GUEST_RIP:
683 case VMX_VMCS_GUEST_RFLAGS:
684 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
685 case VMX_VMCS_GUEST_SYSENTER_ESP:
686 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
687
688 /* Host-state fields. */
689 case VMX_VMCS_HOST_CR0:
690 case VMX_VMCS_HOST_CR3:
691 case VMX_VMCS_HOST_CR4:
692 case VMX_VMCS_HOST_FS_BASE:
693 case VMX_VMCS_HOST_GS_BASE:
694 case VMX_VMCS_HOST_TR_BASE:
695 case VMX_VMCS_HOST_GDTR_BASE:
696 case VMX_VMCS_HOST_IDTR_BASE:
697 case VMX_VMCS_HOST_SYSENTER_ESP:
698 case VMX_VMCS_HOST_SYSENTER_EIP:
699 case VMX_VMCS_HOST_RSP:
700 case VMX_VMCS_HOST_RIP: return true;
701 }
702
703 return false;
704}
705
706
707/**
708 * Gets a host selector from the VMCS.
709 *
710 * @param pVmcs Pointer to the virtual VMCS.
711 * @param iSelReg The index of the segment register (X86_SREG_XXX).
712 */
713DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
714{
715 Assert(iSegReg < X86_SREG_COUNT);
716 RTSEL HostSel;
717 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
718 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
719 uint8_t const uWidthType = (uWidth << 2) | uType;
720 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
721 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
722 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
723 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
724 uint8_t const *pbField = pbVmcs + offField;
725 HostSel = *(uint16_t *)pbField;
726 return HostSel;
727}
728
729
730/**
731 * Sets a guest segment register in the VMCS.
732 *
733 * @param pVmcs Pointer to the virtual VMCS.
734 * @param iSegReg The index of the segment register (X86_SREG_XXX).
735 * @param pSelReg Pointer to the segment register.
736 */
737IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
738{
739 Assert(pSelReg);
740 Assert(iSegReg < X86_SREG_COUNT);
741
742 /* Selector. */
743 {
744 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
745 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
746 uint8_t const uWidthType = (uWidth << 2) | uType;
747 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
748 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
749 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
750 uint8_t *pbVmcs = (uint8_t *)pVmcs;
751 uint8_t *pbField = pbVmcs + offField;
752 *(uint16_t *)pbField = pSelReg->Sel;
753 }
754
755 /* Limit. */
756 {
757 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
758 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
759 uint8_t const uWidthType = (uWidth << 2) | uType;
760 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
761 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
762 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
763 uint8_t *pbVmcs = (uint8_t *)pVmcs;
764 uint8_t *pbField = pbVmcs + offField;
765 *(uint32_t *)pbField = pSelReg->u32Limit;
766 }
767
768 /* Base. */
769 {
770 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
771 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
772 uint8_t const uWidthType = (uWidth << 2) | uType;
773 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
774 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
775 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
776 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
777 uint8_t const *pbField = pbVmcs + offField;
778 *(uint64_t *)pbField = pSelReg->u64Base;
779 }
780
781 /* Attributes. */
782 {
783 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
784 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
785 | X86DESCATTR_UNUSABLE;
786 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
787 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
788 uint8_t const uWidthType = (uWidth << 2) | uType;
789 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
790 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
791 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
792 uint8_t *pbVmcs = (uint8_t *)pVmcs;
793 uint8_t *pbField = pbVmcs + offField;
794 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
795 }
796}
797
798
799/**
800 * Gets a guest segment register from the VMCS.
801 *
802 * @returns VBox status code.
803 * @param pVmcs Pointer to the virtual VMCS.
804 * @param iSegReg The index of the segment register (X86_SREG_XXX).
805 * @param pSelReg Where to store the segment register (only updated when
806 * VINF_SUCCESS is returned).
807 *
808 * @remarks Warning! This does not validate the contents of the retrieved segment
809 * register.
810 */
811IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
812{
813 Assert(pSelReg);
814 Assert(iSegReg < X86_SREG_COUNT);
815
816 /* Selector. */
817 uint16_t u16Sel;
818 {
819 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
820 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
821 uint8_t const uWidthType = (uWidth << 2) | uType;
822 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
823 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
824 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
825 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
826 uint8_t const *pbField = pbVmcs + offField;
827 u16Sel = *(uint16_t *)pbField;
828 }
829
830 /* Limit. */
831 uint32_t u32Limit;
832 {
833 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
834 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
835 uint8_t const uWidthType = (uWidth << 2) | uType;
836 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
837 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
838 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
839 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
840 uint8_t const *pbField = pbVmcs + offField;
841 u32Limit = *(uint32_t *)pbField;
842 }
843
844 /* Base. */
845 uint64_t u64Base;
846 {
847 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
848 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
849 uint8_t const uWidthType = (uWidth << 2) | uType;
850 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
851 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
852 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
853 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
854 uint8_t const *pbField = pbVmcs + offField;
855 u64Base = *(uint64_t *)pbField;
856 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
857 }
858
859 /* Attributes. */
860 uint32_t u32Attr;
861 {
862 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
863 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
864 uint8_t const uWidthType = (uWidth << 2) | uType;
865 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
866 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
867 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
868 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
869 uint8_t const *pbField = pbVmcs + offField;
870 u32Attr = *(uint32_t *)pbField;
871 }
872
873 pSelReg->Sel = u16Sel;
874 pSelReg->ValidSel = u16Sel;
875 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
876 pSelReg->u32Limit = u32Limit;
877 pSelReg->u64Base = u64Base;
878 pSelReg->Attr.u = u32Attr;
879 return VINF_SUCCESS;
880}
881
882
883/**
884 * Gets a CR3 target value from the VMCS.
885 *
886 * @returns VBox status code.
887 * @param pVmcs Pointer to the virtual VMCS.
888 * @param idxCr3Target The index of the CR3-target value to retrieve.
889 * @param puValue Where to store the CR3-target value.
890 */
891IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
892{
893 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
898 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
903 return uCr3TargetValue;
904}
905
906
907/**
908 * Converts an IEM exception event type to a VMX event type.
909 *
910 * @returns The VMX event type.
911 * @param uVector The interrupt / exception vector.
912 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
913 */
914DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
915{
916 /* Paranoia (callers may use these interchangeably). */
917 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
929
930 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
931 {
932 if (uVector == X86_XCPT_NMI)
933 return VMX_EXIT_INT_INFO_TYPE_NMI;
934 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
935 }
936
937 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
938 {
939 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
940 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
941 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
942 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
943 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
944 }
945
946 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
947 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
948}
949
950
951/**
952 * Sets the VM-exit qualification VMCS field.
953 *
954 * @param pVCpu The cross context virtual CPU structure.
955 * @param uExitQual The VM-exit qualification.
956 */
957DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
958{
959 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
960 pVmcs->u64RoExitQual.u = uExitQual;
961}
962
963
964/**
965 * Sets the VM-exit interruption information field.
966 *
967 * @param pVCpu The cross context virtual CPU structure.
968 * @param uExitQual The VM-exit interruption information.
969 */
970DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
971{
972 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
973 pVmcs->u32RoExitIntInfo = uExitIntInfo;
974}
975
976
977/**
978 * Sets the VM-exit interruption error code.
979 *
980 * @param pVCpu The cross context virtual CPU structure.
981 * @param uErrCode The error code.
982 */
983DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
984{
985 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
986 pVmcs->u32RoExitIntErrCode = uErrCode;
987}
988
989
990/**
991 * Sets the IDT-vectoring information field.
992 *
993 * @param pVCpu The cross context virtual CPU structure.
994 * @param uIdtVectorInfo The IDT-vectoring information.
995 */
996DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
997{
998 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
999 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1000}
1001
1002
1003/**
1004 * Sets the IDT-vectoring error code field.
1005 *
1006 * @param pVCpu The cross context virtual CPU structure.
1007 * @param uErrCode The error code.
1008 */
1009DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1010{
1011 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1012 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1013}
1014
1015
1016/**
1017 * Sets the VM-exit guest-linear address VMCS field.
1018 *
1019 * @param pVCpu The cross context virtual CPU structure.
1020 * @param uGuestLinearAddr The VM-exit guest-linear address.
1021 */
1022DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1023{
1024 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1025 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1026}
1027
1028
1029/**
1030 * Sets the VM-exit guest-physical address VMCS field.
1031 *
1032 * @param pVCpu The cross context virtual CPU structure.
1033 * @param uGuestPhysAddr The VM-exit guest-physical address.
1034 */
1035DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1036{
1037 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1038 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1039}
1040
1041
1042/**
1043 * Sets the VM-exit instruction length VMCS field.
1044 *
1045 * @param pVCpu The cross context virtual CPU structure.
1046 * @param cbInstr The VM-exit instruction length in bytes.
1047 *
1048 * @remarks Callers may clear this field to 0. Hence, this function does not check
1049 * the validity of the instruction length.
1050 */
1051DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1052{
1053 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1054 pVmcs->u32RoExitInstrLen = cbInstr;
1055}
1056
1057
1058/**
1059 * Sets the VM-exit instruction info. VMCS field.
1060 *
1061 * @param pVCpu The cross context virtual CPU structure.
1062 * @param uExitInstrInfo The VM-exit instruction information.
1063 */
1064DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1065{
1066 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1067 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1068}
1069
1070
1071/**
1072 * Implements VMSucceed for VMX instruction success.
1073 *
1074 * @param pVCpu The cross context virtual CPU structure.
1075 */
1076DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1077{
1078 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1079}
1080
1081
1082/**
1083 * Implements VMFailInvalid for VMX instruction failure.
1084 *
1085 * @param pVCpu The cross context virtual CPU structure.
1086 */
1087DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1088{
1089 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1090}
1091
1092
1093/**
1094 * Implements VMFail for VMX instruction failure.
1095 *
1096 * @param pVCpu The cross context virtual CPU structure.
1097 * @param enmInsErr The VM instruction error.
1098 */
1099DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1100{
1101 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1102}
1103
1104
1105/**
1106 * Checks if the given auto-load/store MSR area count is valid for the
1107 * implementation.
1108 *
1109 * @returns @c true if it's within the valid limit, @c false otherwise.
1110 * @param pVCpu The cross context virtual CPU structure.
1111 * @param uMsrCount The MSR area count to check.
1112 */
1113DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1114{
1115 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1116 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1117 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1118 if (uMsrCount <= cMaxSupportedMsrs)
1119 return true;
1120 return false;
1121}
1122
1123
1124/**
1125 * Flushes the current VMCS contents back to guest memory.
1126 *
1127 * @returns VBox status code.
1128 * @param pVCpu The cross context virtual CPU structure.
1129 */
1130DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1131{
1132 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1133 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1134 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1135 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1136 return rc;
1137}
1138
1139
1140/**
1141 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1142 *
1143 * @param pVCpu The cross context virtual CPU structure.
1144 */
1145DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1146{
1147 iemVmxVmSucceed(pVCpu);
1148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1149}
1150
1151
1152/**
1153 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1154 * nested-guest.
1155 *
1156 * @param iSegReg The segment index (X86_SREG_XXX).
1157 */
1158IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1159{
1160 switch (iSegReg)
1161 {
1162 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1163 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1164 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1165 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1166 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1167 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1168 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1169 }
1170}
1171
1172
1173/**
1174 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1175 * nested-guest that is in Virtual-8086 mode.
1176 *
1177 * @param iSegReg The segment index (X86_SREG_XXX).
1178 */
1179IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1180{
1181 switch (iSegReg)
1182 {
1183 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1184 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1185 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1186 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1187 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1188 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1189 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1190 }
1191}
1192
1193
1194/**
1195 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1196 * nested-guest that is in Virtual-8086 mode.
1197 *
1198 * @param iSegReg The segment index (X86_SREG_XXX).
1199 */
1200IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1201{
1202 switch (iSegReg)
1203 {
1204 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1205 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1206 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1207 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1208 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1209 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1210 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1211 }
1212}
1213
1214
1215/**
1216 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1217 * nested-guest that is in Virtual-8086 mode.
1218 *
1219 * @param iSegReg The segment index (X86_SREG_XXX).
1220 */
1221IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1222{
1223 switch (iSegReg)
1224 {
1225 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1226 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1227 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1228 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1229 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1230 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1231 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1232 }
1233}
1234
1235
1236/**
1237 * Gets the instruction diagnostic for segment attributes reserved bits failure
1238 * during VM-entry of a nested-guest.
1239 *
1240 * @param iSegReg The segment index (X86_SREG_XXX).
1241 */
1242IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1243{
1244 switch (iSegReg)
1245 {
1246 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1247 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1248 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1249 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1250 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1251 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1252 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1253 }
1254}
1255
1256
1257/**
1258 * Gets the instruction diagnostic for segment attributes descriptor-type
1259 * (code/segment or system) failure during VM-entry of a nested-guest.
1260 *
1261 * @param iSegReg The segment index (X86_SREG_XXX).
1262 */
1263IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1264{
1265 switch (iSegReg)
1266 {
1267 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1268 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1269 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1270 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1271 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1272 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1273 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1274 }
1275}
1276
1277
1278/**
1279 * Gets the instruction diagnostic for segment attributes descriptor-type
1280 * (code/segment or system) failure during VM-entry of a nested-guest.
1281 *
1282 * @param iSegReg The segment index (X86_SREG_XXX).
1283 */
1284IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1285{
1286 switch (iSegReg)
1287 {
1288 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1289 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1290 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1291 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1292 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1293 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1294 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1295 }
1296}
1297
1298
1299/**
1300 * Gets the instruction diagnostic for segment attribute granularity failure during
1301 * VM-entry of a nested-guest.
1302 *
1303 * @param iSegReg The segment index (X86_SREG_XXX).
1304 */
1305IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1306{
1307 switch (iSegReg)
1308 {
1309 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1310 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1311 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1312 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1313 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1314 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1315 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1316 }
1317}
1318
1319/**
1320 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1321 * VM-entry of a nested-guest.
1322 *
1323 * @param iSegReg The segment index (X86_SREG_XXX).
1324 */
1325IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1326{
1327 switch (iSegReg)
1328 {
1329 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1330 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1331 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1332 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1333 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1334 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1335 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1336 }
1337}
1338
1339
1340/**
1341 * Gets the instruction diagnostic for segment attribute type accessed failure
1342 * during VM-entry of a nested-guest.
1343 *
1344 * @param iSegReg The segment index (X86_SREG_XXX).
1345 */
1346IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1347{
1348 switch (iSegReg)
1349 {
1350 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1351 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1352 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1353 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1354 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1355 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1356 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1357 }
1358}
1359
1360
1361/**
1362 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1363 * failure during VM-entry of a nested-guest.
1364 *
1365 * @param iSegReg The PDPTE entry index.
1366 */
1367IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1368{
1369 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1370 switch (iPdpte)
1371 {
1372 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1373 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1374 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1375 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1376 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1377 }
1378}
1379
1380
1381/**
1382 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1383 * failure during VM-exit of a nested-guest.
1384 *
1385 * @param iSegReg The PDPTE entry index.
1386 */
1387IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1388{
1389 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1390 switch (iPdpte)
1391 {
1392 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1393 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1394 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1395 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1396 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1397 }
1398}
1399
1400
1401/**
1402 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1403 * mask and the read-shadow (CR0/CR4 read).
1404 *
1405 * @returns The masked CR0/CR4.
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param iCrReg The control register (either CR0 or CR4).
1408 * @param uGuestCrX The current guest CR0 or guest CR4.
1409 */
1410IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1411{
1412 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1413 Assert(iCrReg == 0 || iCrReg == 4);
1414
1415 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1416 Assert(pVmcs);
1417
1418 /*
1419 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1420 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1421 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1422 *
1423 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1424 */
1425 uint64_t fGstHostMask;
1426 uint64_t fReadShadow;
1427 if (iCrReg == 0)
1428 {
1429 fGstHostMask = pVmcs->u64Cr0Mask.u;
1430 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1431 }
1432 else
1433 {
1434 fGstHostMask = pVmcs->u64Cr4Mask.u;
1435 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1436 }
1437
1438 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1439 return fMaskedCrX;
1440}
1441
1442
1443/**
1444 * Saves the guest control registers, debug registers and some MSRs are part of
1445 * VM-exit.
1446 *
1447 * @param pVCpu The cross context virtual CPU structure.
1448 */
1449IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1450{
1451 /*
1452 * Saves the guest control registers, debug registers and some MSRs.
1453 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1454 */
1455 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1456
1457 /* Save control registers. */
1458 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1459 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1460 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1461
1462 /* Save SYSENTER CS, ESP, EIP. */
1463 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1464 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1465 {
1466 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1467 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1468 }
1469 else
1470 {
1471 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1472 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1473 }
1474
1475 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1476 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1477 {
1478 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1479 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1480 }
1481
1482 /* Save PAT MSR. */
1483 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1484 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1485
1486 /* Save EFER MSR. */
1487 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1488 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1489
1490 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1491 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1492
1493 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1494}
1495
1496
1497/**
1498 * Saves the guest force-flags in preparation of entering the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 /* We shouldn't be called multiple times during VM-entry. */
1505 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1506
1507 /* MTF should not be set outside VMX non-root mode. */
1508 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1509
1510 /*
1511 * Preserve the required force-flags.
1512 *
1513 * We cache and clear force-flags that would affect the execution of the
1514 * nested-guest. Cached flags are then restored while returning to the guest
1515 * if necessary.
1516 *
1517 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1518 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1519 * instruction. Interrupt inhibition for any nested-guest instruction
1520 * is supplied by the guest-interruptibility state VMCS field and will
1521 * be set up as part of loading the guest state.
1522 *
1523 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1524 * successful VM-entry (due to invalid guest-state) need to continue
1525 * blocking NMIs if it was in effect before VM-entry.
1526 *
1527 * - MTF need not be preserved as it's used only in VMX non-root mode and
1528 * is supplied through the VM-execution controls.
1529 *
1530 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1531 * we will be able to generate interrupts that may cause VM-exits for
1532 * the nested-guest.
1533 */
1534 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1535}
1536
1537
1538/**
1539 * Restores the guest force-flags in preparation of exiting the nested-guest.
1540 *
1541 * @param pVCpu The cross context virtual CPU structure.
1542 */
1543IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1544{
1545 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1546 {
1547 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1548 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1549 }
1550}
1551
1552
1553/**
1554 * Perform a VMX transition updated PGM, IEM and CPUM.
1555 *
1556 * @param pVCpu The cross context virtual CPU structure.
1557 */
1558IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1559{
1560 /*
1561 * Inform PGM about paging mode changes.
1562 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1563 * see comment in iemMemPageTranslateAndCheckAccess().
1564 */
1565 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1566# ifdef IN_RING3
1567 Assert(rc != VINF_PGM_CHANGE_MODE);
1568# endif
1569 AssertRCReturn(rc, rc);
1570
1571 /* Inform CPUM (recompiler), can later be removed. */
1572 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1573
1574 /*
1575 * Flush the TLB with new CR3. This is required in case the PGM mode change
1576 * above doesn't actually change anything.
1577 */
1578 if (rc == VINF_SUCCESS)
1579 {
1580 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1581 AssertRCReturn(rc, rc);
1582 }
1583
1584 /* Re-initialize IEM cache/state after the drastic mode switch. */
1585 iemReInitExec(pVCpu);
1586 return rc;
1587}
1588
1589
1590/**
1591 * Calculates the current VMX-preemption timer value.
1592 *
1593 * @param pVCpu The cross context virtual CPU structure.
1594 */
1595IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1596{
1597 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1598 Assert(pVmcs);
1599
1600 /*
1601 * Assume the following:
1602 * PreemptTimerShift = 5
1603 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1604 * EntryTick = 50000 (TSC at time of VM-entry)
1605 *
1606 * CurTick Delta PreemptTimerVal
1607 * ----------------------------------
1608 * 60000 10000 2
1609 * 80000 30000 1
1610 * 90000 40000 0 -> VM-exit.
1611 *
1612 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1613 * The saved VMX-preemption timer value is calculated as follows:
1614 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1615 * E.g.:
1616 * Delta = 10000
1617 * Tmp = 10000 / (2 * 10000) = 0.5
1618 * NewPt = 2 - 0.5 = 2
1619 * Delta = 30000
1620 * Tmp = 30000 / (2 * 10000) = 1.5
1621 * NewPt = 2 - 1.5 = 1
1622 * Delta = 40000
1623 * Tmp = 40000 / 20000 = 2
1624 * NewPt = 2 - 2 = 0
1625 */
1626 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1627 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1628 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1629 uint64_t const uDelta = uCurTick - uEntryTick;
1630 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1631 uint32_t const uPreemptTimer = uVmcsPreemptVal
1632 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1633 return uPreemptTimer;
1634}
1635
1636
1637/**
1638 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1639 *
1640 * @param pVCpu The cross context virtual CPU structure.
1641 */
1642IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1643{
1644 /*
1645 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1646 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1647 */
1648 /* CS, SS, ES, DS, FS, GS. */
1649 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1650 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1651 {
1652 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1653 if (!pSelReg->Attr.n.u1Unusable)
1654 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1655 else
1656 {
1657 /*
1658 * For unusable segments the attributes are undefined except for CS and SS.
1659 * For the rest we don't bother preserving anything but the unusable bit.
1660 */
1661 switch (iSegReg)
1662 {
1663 case X86_SREG_CS:
1664 pVmcs->GuestCs = pSelReg->Sel;
1665 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1666 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1667 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1668 | X86DESCATTR_UNUSABLE);
1669 break;
1670
1671 case X86_SREG_SS:
1672 pVmcs->GuestSs = pSelReg->Sel;
1673 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1674 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1675 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1676 break;
1677
1678 case X86_SREG_DS:
1679 pVmcs->GuestDs = pSelReg->Sel;
1680 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1681 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1682 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1683 break;
1684
1685 case X86_SREG_ES:
1686 pVmcs->GuestEs = pSelReg->Sel;
1687 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1688 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1689 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1690 break;
1691
1692 case X86_SREG_FS:
1693 pVmcs->GuestFs = pSelReg->Sel;
1694 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1695 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1696 break;
1697
1698 case X86_SREG_GS:
1699 pVmcs->GuestGs = pSelReg->Sel;
1700 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1701 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1702 break;
1703 }
1704 }
1705 }
1706
1707 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1708 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1709 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1710 | X86DESCATTR_UNUSABLE;
1711 /* LDTR. */
1712 {
1713 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1714 pVmcs->GuestLdtr = pSelReg->Sel;
1715 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1716 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1717 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1718 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1719 }
1720
1721 /* TR. */
1722 {
1723 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1724 pVmcs->GuestTr = pSelReg->Sel;
1725 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1726 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1727 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1728 }
1729
1730 /* GDTR. */
1731 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1732 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1733
1734 /* IDTR. */
1735 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1736 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1737}
1738
1739
1740/**
1741 * Saves guest non-register state as part of VM-exit.
1742 *
1743 * @param pVCpu The cross context virtual CPU structure.
1744 * @param uExitReason The VM-exit reason.
1745 */
1746IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1747{
1748 /*
1749 * Save guest non-register state.
1750 * See Intel spec. 27.3.4 "Saving Non-Register State".
1751 */
1752 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1753
1754 /*
1755 * Activity state.
1756 * Most VM-exits will occur in the active state. However, if the first instruction
1757 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1758 * the VM-exit will be from the HLT activity state.
1759 *
1760 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1761 */
1762 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1763 * not? */
1764 EMSTATE const enmActivityState = EMGetState(pVCpu);
1765 switch (enmActivityState)
1766 {
1767 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1768 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1769 }
1770
1771 /*
1772 * Interruptibility-state.
1773 */
1774 /* NMI. */
1775 pVmcs->u32GuestIntrState = 0;
1776 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1777 {
1778 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1779 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1780 }
1781 else
1782 {
1783 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1784 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1785 }
1786
1787 /* Blocking-by-STI. */
1788 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1789 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1790 {
1791 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1792 * currently. */
1793 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1794 }
1795 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1796
1797 /*
1798 * Pending debug exceptions.
1799 */
1800 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1801 && uExitReason != VMX_EXIT_SMI
1802 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1803 && !HMVmxIsVmexitTrapLike(uExitReason))
1804 {
1805 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1806 * block-by-MovSS is in effect. */
1807 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1808 }
1809 else
1810 {
1811 /*
1812 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1813 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1814 *
1815 * See Intel spec. 24.4.2 "Guest Non-Register State".
1816 */
1817 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1818 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1819 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1820 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1821 if (fPendingDbgMask & fBpHitMask)
1822 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1823 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1824 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1825 }
1826
1827 /*
1828 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1829 *
1830 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1831 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1832 */
1833 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1834 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1835 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1836
1837 /* PDPTEs. */
1838 /* We don't support EPT yet. */
1839 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1840 pVmcs->u64GuestPdpte0.u = 0;
1841 pVmcs->u64GuestPdpte1.u = 0;
1842 pVmcs->u64GuestPdpte2.u = 0;
1843 pVmcs->u64GuestPdpte3.u = 0;
1844}
1845
1846
1847/**
1848 * Saves the guest-state as part of VM-exit.
1849 *
1850 * @returns VBox status code.
1851 * @param pVCpu The cross context virtual CPU structure.
1852 * @param uExitReason The VM-exit reason.
1853 */
1854IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1855{
1856 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1857 Assert(pVmcs);
1858
1859 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1860 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1861
1862 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1863 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1864 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1865
1866 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1867}
1868
1869
1870/**
1871 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1872 *
1873 * @returns VBox status code.
1874 * @param pVCpu The cross context virtual CPU structure.
1875 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1876 */
1877IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1878{
1879 /*
1880 * Save guest MSRs.
1881 * See Intel spec. 27.4 "Saving MSRs".
1882 */
1883 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1884 const char *const pszFailure = "VMX-abort";
1885
1886 /*
1887 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1888 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1889 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1890 */
1891 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1892 if (!cMsrs)
1893 return VINF_SUCCESS;
1894
1895 /*
1896 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1897 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1898 * implementation causes a VMX-abort followed by a triple-fault.
1899 */
1900 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1901 if (fIsMsrCountValid)
1902 { /* likely */ }
1903 else
1904 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1905
1906 /*
1907 * Optimization if the guest hypervisor is using the same guest-physical page for both
1908 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1909 */
1910 PVMXAUTOMSR pMsrArea;
1911 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1912 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1913 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1914 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1915 else
1916 {
1917 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1918 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1919 if (RT_SUCCESS(rc))
1920 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1921 else
1922 {
1923 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1924 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1925 }
1926 }
1927
1928 /*
1929 * Update VM-exit MSR store area.
1930 */
1931 PVMXAUTOMSR pMsr = pMsrArea;
1932 Assert(pMsr);
1933 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1934 {
1935 if ( !pMsr->u32Reserved
1936 && pMsr->u32Msr != MSR_IA32_SMBASE
1937 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1938 {
1939 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1940 if (rcStrict == VINF_SUCCESS)
1941 continue;
1942
1943 /*
1944 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1945 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1946 * recording the MSR index in the auxiliary info. field and indicated further by our
1947 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1948 * if possible, or come up with a better, generic solution.
1949 */
1950 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1951 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1952 ? kVmxVDiag_Vmexit_MsrStoreRing3
1953 : kVmxVDiag_Vmexit_MsrStore;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1955 }
1956 else
1957 {
1958 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1959 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1960 }
1961 }
1962
1963 /*
1964 * Commit the VM-exit MSR store are to guest memory.
1965 */
1966 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1967 if (RT_SUCCESS(rc))
1968 return VINF_SUCCESS;
1969
1970 NOREF(uExitReason);
1971 NOREF(pszFailure);
1972
1973 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1974 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1975}
1976
1977
1978/**
1979 * Performs a VMX abort (due to an fatal error during VM-exit).
1980 *
1981 * @returns Strict VBox status code.
1982 * @param pVCpu The cross context virtual CPU structure.
1983 * @param enmAbort The VMX abort reason.
1984 */
1985IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1986{
1987 /*
1988 * Perform the VMX abort.
1989 * See Intel spec. 27.7 "VMX Aborts".
1990 */
1991 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1992
1993 /* We don't support SMX yet. */
1994 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1995 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1996 {
1997 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1998 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1999 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2000 }
2001
2002 return VINF_EM_TRIPLE_FAULT;
2003}
2004
2005
2006/**
2007 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2008 *
2009 * @param pVCpu The cross context virtual CPU structure.
2010 */
2011IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2012{
2013 /*
2014 * Load host control registers, debug registers and MSRs.
2015 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2016 */
2017 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2018 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2019
2020 /* CR0. */
2021 {
2022 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2023 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2024 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2025 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2026 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2027 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2028 CPUMSetGuestCR0(pVCpu, uValidCr0);
2029 }
2030
2031 /* CR4. */
2032 {
2033 /* CR4 MB1 bits are not modified. */
2034 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2035 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2036 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2037 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2038 if (fHostInLongMode)
2039 uValidCr4 |= X86_CR4_PAE;
2040 else
2041 uValidCr4 &= ~X86_CR4_PCIDE;
2042 CPUMSetGuestCR4(pVCpu, uValidCr4);
2043 }
2044
2045 /* CR3 (host value validated while checking host-state during VM-entry). */
2046 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2047
2048 /* DR7. */
2049 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2050
2051 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2052
2053 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2054 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2055 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2056 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2057
2058 /* FS, GS bases are loaded later while we load host segment registers. */
2059
2060 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2061 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2062 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2063 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2064 {
2065 if (fHostInLongMode)
2066 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2067 else
2068 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2069 }
2070
2071 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2072
2073 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2074 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2075 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2076
2077 /* We don't support IA32_BNDCFGS MSR yet. */
2078}
2079
2080
2081/**
2082 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2083 *
2084 * @param pVCpu The cross context virtual CPU structure.
2085 */
2086IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2087{
2088 /*
2089 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2090 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2091 *
2092 * Warning! Be careful to not touch fields that are reserved by VT-x,
2093 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2094 */
2095 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2096 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2097
2098 /* CS, SS, ES, DS, FS, GS. */
2099 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2100 {
2101 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2102 bool const fUnusable = RT_BOOL(HostSel == 0);
2103 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2104
2105 /* Selector. */
2106 pSelReg->Sel = HostSel;
2107 pSelReg->ValidSel = HostSel;
2108 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2109
2110 /* Limit. */
2111 pSelReg->u32Limit = 0xffffffff;
2112
2113 /* Base. */
2114 pSelReg->u64Base = 0;
2115
2116 /* Attributes. */
2117 if (iSegReg == X86_SREG_CS)
2118 {
2119 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2120 pSelReg->Attr.n.u1DescType = 1;
2121 pSelReg->Attr.n.u2Dpl = 0;
2122 pSelReg->Attr.n.u1Present = 1;
2123 pSelReg->Attr.n.u1Long = fHostInLongMode;
2124 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2125 pSelReg->Attr.n.u1Granularity = 1;
2126 Assert(!pSelReg->Attr.n.u1Unusable);
2127 Assert(!fUnusable);
2128 }
2129 else
2130 {
2131 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2132 pSelReg->Attr.n.u1DescType = 1;
2133 pSelReg->Attr.n.u2Dpl = 0;
2134 pSelReg->Attr.n.u1Present = 1;
2135 pSelReg->Attr.n.u1DefBig = 1;
2136 pSelReg->Attr.n.u1Granularity = 1;
2137 pSelReg->Attr.n.u1Unusable = fUnusable;
2138 }
2139 }
2140
2141 /* FS base. */
2142 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2143 || fHostInLongMode)
2144 {
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2146 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2147 }
2148
2149 /* GS base. */
2150 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2151 || fHostInLongMode)
2152 {
2153 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2154 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2155 }
2156
2157 /* TR. */
2158 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2159 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2160 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2161 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2162 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2163 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2164 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2165 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2166 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2167 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2168 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2169 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2170 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2171
2172 /* LDTR (Warning! do not touch the base and limits here). */
2173 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2174 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2175 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2176 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2177
2178 /* GDTR. */
2179 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2180 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2181 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2182
2183 /* IDTR.*/
2184 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2185 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2186 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2187}
2188
2189
2190/**
2191 * Checks host PDPTes as part of VM-exit.
2192 *
2193 * @param pVCpu The cross context virtual CPU structure.
2194 * @param uExitReason The VM-exit reason (for logging purposes).
2195 */
2196IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2197{
2198 /*
2199 * Check host PDPTEs.
2200 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2201 */
2202 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2203 const char *const pszFailure = "VMX-abort";
2204 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2205
2206 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2207 && !fHostInLongMode)
2208 {
2209 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2210 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2211 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2212 if (RT_SUCCESS(rc))
2213 {
2214 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2215 {
2216 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2217 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2218 { /* likely */ }
2219 else
2220 {
2221 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2222 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2223 }
2224 }
2225 }
2226 else
2227 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2228 }
2229
2230 NOREF(pszFailure);
2231 NOREF(uExitReason);
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/**
2237 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2238 *
2239 * @returns VBox status code.
2240 * @param pVCpu The cross context virtual CPU structure.
2241 * @param pszInstr The VMX instruction name (for logging purposes).
2242 */
2243IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2244{
2245 /*
2246 * Load host MSRs.
2247 * See Intel spec. 27.6 "Loading MSRs".
2248 */
2249 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2250 const char *const pszFailure = "VMX-abort";
2251
2252 /*
2253 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2254 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2255 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2256 */
2257 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2258 if (!cMsrs)
2259 return VINF_SUCCESS;
2260
2261 /*
2262 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2263 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2264 * implementation causes a VMX-abort followed by a triple-fault.
2265 */
2266 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2267 if (fIsMsrCountValid)
2268 { /* likely */ }
2269 else
2270 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2271
2272 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2273 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2274 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2275 if (RT_SUCCESS(rc))
2276 {
2277 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2278 Assert(pMsr);
2279 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2280 {
2281 if ( !pMsr->u32Reserved
2282 && pMsr->u32Msr != MSR_K8_FS_BASE
2283 && pMsr->u32Msr != MSR_K8_GS_BASE
2284 && pMsr->u32Msr != MSR_K6_EFER
2285 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2286 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2287 {
2288 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2289 if (rcStrict == VINF_SUCCESS)
2290 continue;
2291
2292 /*
2293 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2294 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2295 * recording the MSR index in the auxiliary info. field and indicated further by our
2296 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2297 * if possible, or come up with a better, generic solution.
2298 */
2299 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2300 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2301 ? kVmxVDiag_Vmexit_MsrLoadRing3
2302 : kVmxVDiag_Vmexit_MsrLoad;
2303 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2304 }
2305 else
2306 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2307 }
2308 }
2309 else
2310 {
2311 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2312 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2313 }
2314
2315 NOREF(uExitReason);
2316 NOREF(pszFailure);
2317 return VINF_SUCCESS;
2318}
2319
2320
2321/**
2322 * Loads the host state as part of VM-exit.
2323 *
2324 * @returns Strict VBox status code.
2325 * @param pVCpu The cross context virtual CPU structure.
2326 * @param uExitReason The VM-exit reason (for logging purposes).
2327 */
2328IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2329{
2330 /*
2331 * Load host state.
2332 * See Intel spec. 27.5 "Loading Host State".
2333 */
2334 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2335 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2336
2337 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2338 if ( CPUMIsGuestInLongMode(pVCpu)
2339 && !fHostInLongMode)
2340 {
2341 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2342 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2343 }
2344
2345 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2346 iemVmxVmexitLoadHostSegRegs(pVCpu);
2347
2348 /*
2349 * Load host RIP, RSP and RFLAGS.
2350 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2351 */
2352 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2353 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2354 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2355
2356 /* Clear address range monitoring. */
2357 EMMonitorWaitClear(pVCpu);
2358
2359 /* Perform the VMX transition (PGM updates). */
2360 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2361 if (rcStrict == VINF_SUCCESS)
2362 {
2363 /* Check host PDPTEs (only when we've fully switched page tables_. */
2364 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2365 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2366 if (RT_FAILURE(rc))
2367 {
2368 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2369 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2370 }
2371 }
2372 else if (RT_SUCCESS(rcStrict))
2373 {
2374 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2375 uExitReason));
2376 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2377 }
2378 else
2379 {
2380 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2381 return VBOXSTRICTRC_VAL(rcStrict);
2382 }
2383
2384 Assert(rcStrict == VINF_SUCCESS);
2385
2386 /* Load MSRs from the VM-exit auto-load MSR area. */
2387 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2388 if (RT_FAILURE(rc))
2389 {
2390 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2391 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2392 }
2393 return VINF_SUCCESS;
2394}
2395
2396
2397/**
2398 * Gets VM-exit instruction information along with any displacement for an
2399 * instruction VM-exit.
2400 *
2401 * @returns The VM-exit instruction information.
2402 * @param pVCpu The cross context virtual CPU structure.
2403 * @param uExitReason The VM-exit reason.
2404 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2405 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2406 * NULL.
2407 */
2408IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2409{
2410 RTGCPTR GCPtrDisp;
2411 VMXEXITINSTRINFO ExitInstrInfo;
2412 ExitInstrInfo.u = 0;
2413
2414 /*
2415 * Get and parse the ModR/M byte from our decoded opcodes.
2416 */
2417 uint8_t bRm;
2418 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2419 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2420 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2421 {
2422 /*
2423 * ModR/M indicates register addressing.
2424 *
2425 * The primary/secondary register operands are reported in the iReg1 or iReg2
2426 * fields depending on whether it is a read/write form.
2427 */
2428 uint8_t idxReg1;
2429 uint8_t idxReg2;
2430 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2431 {
2432 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2433 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2434 }
2435 else
2436 {
2437 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2438 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2439 }
2440 ExitInstrInfo.All.u2Scaling = 0;
2441 ExitInstrInfo.All.iReg1 = idxReg1;
2442 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2443 ExitInstrInfo.All.fIsRegOperand = 1;
2444 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2445 ExitInstrInfo.All.iSegReg = 0;
2446 ExitInstrInfo.All.iIdxReg = 0;
2447 ExitInstrInfo.All.fIdxRegInvalid = 1;
2448 ExitInstrInfo.All.iBaseReg = 0;
2449 ExitInstrInfo.All.fBaseRegInvalid = 1;
2450 ExitInstrInfo.All.iReg2 = idxReg2;
2451
2452 /* Displacement not applicable for register addressing. */
2453 GCPtrDisp = 0;
2454 }
2455 else
2456 {
2457 /*
2458 * ModR/M indicates memory addressing.
2459 */
2460 uint8_t uScale = 0;
2461 bool fBaseRegValid = false;
2462 bool fIdxRegValid = false;
2463 uint8_t iBaseReg = 0;
2464 uint8_t iIdxReg = 0;
2465 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2466 {
2467 /*
2468 * Parse the ModR/M, displacement for 16-bit addressing mode.
2469 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2470 */
2471 uint16_t u16Disp = 0;
2472 uint8_t const offDisp = offModRm + sizeof(bRm);
2473 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2474 {
2475 /* Displacement without any registers. */
2476 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2477 }
2478 else
2479 {
2480 /* Register (index and base). */
2481 switch (bRm & X86_MODRM_RM_MASK)
2482 {
2483 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2484 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2485 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2486 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2487 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2488 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2489 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2490 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2491 }
2492
2493 /* Register + displacement. */
2494 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2495 {
2496 case 0: break;
2497 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2498 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2499 default:
2500 {
2501 /* Register addressing, handled at the beginning. */
2502 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2503 break;
2504 }
2505 }
2506 }
2507
2508 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2509 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2510 }
2511 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2512 {
2513 /*
2514 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2515 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2516 */
2517 uint32_t u32Disp = 0;
2518 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2519 {
2520 /* Displacement without any registers. */
2521 uint8_t const offDisp = offModRm + sizeof(bRm);
2522 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2523 }
2524 else
2525 {
2526 /* Register (and perhaps scale, index and base). */
2527 uint8_t offDisp = offModRm + sizeof(bRm);
2528 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2529 if (iBaseReg == 4)
2530 {
2531 /* An SIB byte follows the ModR/M byte, parse it. */
2532 uint8_t bSib;
2533 uint8_t const offSib = offModRm + sizeof(bRm);
2534 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2535
2536 /* A displacement may follow SIB, update its offset. */
2537 offDisp += sizeof(bSib);
2538
2539 /* Get the scale. */
2540 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2541
2542 /* Get the index register. */
2543 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2544 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2545
2546 /* Get the base register. */
2547 iBaseReg = bSib & X86_SIB_BASE_MASK;
2548 fBaseRegValid = true;
2549 if (iBaseReg == 5)
2550 {
2551 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2552 {
2553 /* Mod is 0 implies a 32-bit displacement with no base. */
2554 fBaseRegValid = false;
2555 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2556 }
2557 else
2558 {
2559 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2560 iBaseReg = X86_GREG_xBP;
2561 }
2562 }
2563 }
2564
2565 /* Register + displacement. */
2566 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2567 {
2568 case 0: /* Handled above */ break;
2569 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2570 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2571 default:
2572 {
2573 /* Register addressing, handled at the beginning. */
2574 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2575 break;
2576 }
2577 }
2578 }
2579
2580 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2581 }
2582 else
2583 {
2584 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2585
2586 /*
2587 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2588 * See Intel instruction spec. 2.2 "IA-32e Mode".
2589 */
2590 uint64_t u64Disp = 0;
2591 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2592 if (fRipRelativeAddr)
2593 {
2594 /*
2595 * RIP-relative addressing mode.
2596 *
2597 * The displacement is 32-bit signed implying an offset range of +/-2G.
2598 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2599 */
2600 uint8_t const offDisp = offModRm + sizeof(bRm);
2601 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2602 }
2603 else
2604 {
2605 uint8_t offDisp = offModRm + sizeof(bRm);
2606
2607 /*
2608 * Register (and perhaps scale, index and base).
2609 *
2610 * REX.B extends the most-significant bit of the base register. However, REX.B
2611 * is ignored while determining whether an SIB follows the opcode. Hence, we
2612 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2613 *
2614 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2615 */
2616 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2617 if (iBaseReg == 4)
2618 {
2619 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2620 uint8_t bSib;
2621 uint8_t const offSib = offModRm + sizeof(bRm);
2622 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2623
2624 /* Displacement may follow SIB, update its offset. */
2625 offDisp += sizeof(bSib);
2626
2627 /* Get the scale. */
2628 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2629
2630 /* Get the index. */
2631 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2632 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2633
2634 /* Get the base. */
2635 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2636 fBaseRegValid = true;
2637 if (iBaseReg == 5)
2638 {
2639 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2640 {
2641 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2642 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2643 }
2644 else
2645 {
2646 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2647 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2648 }
2649 }
2650 }
2651 iBaseReg |= pVCpu->iem.s.uRexB;
2652
2653 /* Register + displacement. */
2654 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2655 {
2656 case 0: /* Handled above */ break;
2657 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2658 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2659 default:
2660 {
2661 /* Register addressing, handled at the beginning. */
2662 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2663 break;
2664 }
2665 }
2666 }
2667
2668 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2669 }
2670
2671 /*
2672 * The primary or secondary register operand is reported in iReg2 depending
2673 * on whether the primary operand is in read/write form.
2674 */
2675 uint8_t idxReg2;
2676 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2677 {
2678 idxReg2 = bRm & X86_MODRM_RM_MASK;
2679 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2680 idxReg2 |= pVCpu->iem.s.uRexB;
2681 }
2682 else
2683 {
2684 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2685 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2686 idxReg2 |= pVCpu->iem.s.uRexReg;
2687 }
2688 ExitInstrInfo.All.u2Scaling = uScale;
2689 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2690 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2691 ExitInstrInfo.All.fIsRegOperand = 0;
2692 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2693 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2694 ExitInstrInfo.All.iIdxReg = iIdxReg;
2695 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2696 ExitInstrInfo.All.iBaseReg = iBaseReg;
2697 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2698 ExitInstrInfo.All.iReg2 = idxReg2;
2699 }
2700
2701 /*
2702 * Handle exceptions to the norm for certain instructions.
2703 * (e.g. some instructions convey an instruction identity in place of iReg2).
2704 */
2705 switch (uExitReason)
2706 {
2707 case VMX_EXIT_GDTR_IDTR_ACCESS:
2708 {
2709 Assert(VMXINSTRID_IS_VALID(uInstrId));
2710 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2711 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2712 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2713 break;
2714 }
2715
2716 case VMX_EXIT_LDTR_TR_ACCESS:
2717 {
2718 Assert(VMXINSTRID_IS_VALID(uInstrId));
2719 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2720 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2721 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2722 break;
2723 }
2724
2725 case VMX_EXIT_RDRAND:
2726 case VMX_EXIT_RDSEED:
2727 {
2728 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2729 break;
2730 }
2731 }
2732
2733 /* Update displacement and return the constructed VM-exit instruction information field. */
2734 if (pGCPtrDisp)
2735 *pGCPtrDisp = GCPtrDisp;
2736
2737 return ExitInstrInfo.u;
2738}
2739
2740
2741/**
2742 * VMX VM-exit handler.
2743 *
2744 * @returns Strict VBox status code.
2745 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2746 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2747 * triple-fault.
2748 *
2749 * @param pVCpu The cross context virtual CPU structure.
2750 * @param uExitReason The VM-exit reason.
2751 *
2752 * @remarks Make sure VM-exit qualification is updated before calling this
2753 * function!
2754 */
2755IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2756{
2757# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2758 RT_NOREF2(pVCpu, uExitReason);
2759 return VINF_EM_RAW_EMULATE_INSTR;
2760# else
2761 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2762 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2763 | CPUMCTX_EXTRN_EFER /* MSRs */
2764 | CPUMCTX_EXTRN_SYSENTER_MSRS
2765 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2766 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2767 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2768 | CPUMCTX_EXTRN_TR /* Task register */
2769 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2770 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2771
2772 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2773 Assert(pVmcs);
2774
2775 /* Ensure VM-entry interruption information valid bit isn't set. */
2776 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2777
2778 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2779 pVmcs->u32RoExitReason = uExitReason;
2780 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2781 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2782
2783 /*
2784 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2785 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2786 */
2787 {
2788 uint8_t uVector;
2789 uint32_t fFlags;
2790 uint32_t uErrCode;
2791 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2792 if (!fInEventDelivery)
2793 {
2794 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2795 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0); /* Not strictly needed but do it for consistency. */
2796 }
2797 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2798 }
2799
2800 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2801 Assert(pVmcs->u64RoIoRcx.u == 0);
2802 Assert(pVmcs->u64RoIoRsi.u == 0);
2803 Assert(pVmcs->u64RoIoRdi.u == 0);
2804 Assert(pVmcs->u64RoIoRip.u == 0);
2805
2806 /*
2807 * Save the guest state back into the VMCS.
2808 * We only need to save the state when the VM-entry was successful.
2809 */
2810 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2811 if (!fVmentryFailed)
2812 {
2813 /*
2814 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2815 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2816 *
2817 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2818 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2819 * as guest-CPU state would not been modified. Hence for now, we do this only when
2820 * the VM-entry succeeded.
2821 */
2822 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2823 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2824 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2825 {
2826 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2827 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2828 else
2829 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2830 }
2831
2832 /*
2833 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2834 * occurs in enclave mode/SMM which we don't support yet.
2835 *
2836 * If we ever add support for it, we can pass just the lower bits to the functions
2837 * below, till then an assert should suffice.
2838 */
2839 Assert(!RT_HI_U16(uExitReason));
2840
2841 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2842 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2843 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2844 if (RT_SUCCESS(rc))
2845 { /* likely */ }
2846 else
2847 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2848
2849 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2850 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2851 }
2852 else
2853 {
2854 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2855 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2856 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2857 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2858 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2859 }
2860
2861 /*
2862 * Clear any pending VMX nested-guest force-flags.
2863 * These force-flags have no effect on guest execution and will
2864 * be re-evaluated and setup on the next nested-guest VM-entry.
2865 */
2866 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2867 | VMCPU_FF_VMX_MTF
2868 | VMCPU_FF_VMX_APIC_WRITE
2869 | VMCPU_FF_VMX_INT_WINDOW
2870 | VMCPU_FF_VMX_NMI_WINDOW);
2871
2872 /* Restore the host (outer guest) state. */
2873 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2874 if (RT_SUCCESS(rcStrict))
2875 {
2876 Assert(rcStrict == VINF_SUCCESS);
2877 rcStrict = VINF_VMX_VMEXIT;
2878 }
2879 else
2880 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2881
2882 /* We're no longer in nested-guest execution mode. */
2883 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2884
2885# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2886 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2887 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2888 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2889 if (rcSched != VINF_SUCCESS)
2890 iemSetPassUpStatus(pVCpu, rcSched);
2891# endif
2892 return rcStrict;
2893# endif
2894}
2895
2896
2897/**
2898 * VMX VM-exit handler for VM-exits due to instruction execution.
2899 *
2900 * This is intended for instructions where the caller provides all the relevant
2901 * VM-exit information.
2902 *
2903 * @returns Strict VBox status code.
2904 * @param pVCpu The cross context virtual CPU structure.
2905 * @param pExitInfo Pointer to the VM-exit information.
2906 */
2907IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2908{
2909 /*
2910 * For instructions where any of the following fields are not applicable:
2911 * - VM-exit instruction info. is undefined.
2912 * - VM-exit qualification must be cleared.
2913 * - VM-exit guest-linear address is undefined.
2914 * - VM-exit guest-physical address is undefined.
2915 *
2916 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2917 * instruction execution. For VM-exits that are not due to instruction execution this
2918 * field is undefined.
2919 *
2920 * In our implementation in IEM, all undefined fields are generally cleared. However,
2921 * if the caller supplies information (from say the physical CPU directly) it is
2922 * then possible that the undefined fields are not cleared.
2923 *
2924 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2925 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2926 */
2927 Assert(pExitInfo);
2928 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2929 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2930 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2931
2932 /* Update all the relevant fields from the VM-exit instruction information struct. */
2933 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2934 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2935 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2936 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2937 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2938
2939 /* Perform the VM-exit. */
2940 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2941}
2942
2943
2944/**
2945 * VMX VM-exit handler for VM-exits due to instruction execution.
2946 *
2947 * This is intended for instructions that only provide the VM-exit instruction
2948 * length.
2949 *
2950 * @param pVCpu The cross context virtual CPU structure.
2951 * @param uExitReason The VM-exit reason.
2952 * @param cbInstr The instruction length in bytes.
2953 */
2954IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2955{
2956 VMXVEXITINFO ExitInfo;
2957 RT_ZERO(ExitInfo);
2958 ExitInfo.uReason = uExitReason;
2959 ExitInfo.cbInstr = cbInstr;
2960
2961#ifdef VBOX_STRICT
2962 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2963 switch (uExitReason)
2964 {
2965 case VMX_EXIT_INVEPT:
2966 case VMX_EXIT_INVPCID:
2967 case VMX_EXIT_LDTR_TR_ACCESS:
2968 case VMX_EXIT_GDTR_IDTR_ACCESS:
2969 case VMX_EXIT_VMCLEAR:
2970 case VMX_EXIT_VMPTRLD:
2971 case VMX_EXIT_VMPTRST:
2972 case VMX_EXIT_VMREAD:
2973 case VMX_EXIT_VMWRITE:
2974 case VMX_EXIT_VMXON:
2975 case VMX_EXIT_XRSTORS:
2976 case VMX_EXIT_XSAVES:
2977 case VMX_EXIT_RDRAND:
2978 case VMX_EXIT_RDSEED:
2979 case VMX_EXIT_IO_INSTR:
2980 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2981 break;
2982 }
2983#endif
2984
2985 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2986}
2987
2988
2989/**
2990 * VMX VM-exit handler for VM-exits due to instruction execution.
2991 *
2992 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2993 * instruction information and VM-exit qualification fields.
2994 *
2995 * @param pVCpu The cross context virtual CPU structure.
2996 * @param uExitReason The VM-exit reason.
2997 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2998 * @param cbInstr The instruction length in bytes.
2999 *
3000 * @remarks Do not use this for INS/OUTS instruction.
3001 */
3002IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
3003{
3004 VMXVEXITINFO ExitInfo;
3005 RT_ZERO(ExitInfo);
3006 ExitInfo.uReason = uExitReason;
3007 ExitInfo.cbInstr = cbInstr;
3008
3009 /*
3010 * Update the VM-exit qualification field with displacement bytes.
3011 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3012 */
3013 switch (uExitReason)
3014 {
3015 case VMX_EXIT_INVEPT:
3016 case VMX_EXIT_INVPCID:
3017 case VMX_EXIT_INVVPID:
3018 case VMX_EXIT_LDTR_TR_ACCESS:
3019 case VMX_EXIT_GDTR_IDTR_ACCESS:
3020 case VMX_EXIT_VMCLEAR:
3021 case VMX_EXIT_VMPTRLD:
3022 case VMX_EXIT_VMPTRST:
3023 case VMX_EXIT_VMREAD:
3024 case VMX_EXIT_VMWRITE:
3025 case VMX_EXIT_VMXON:
3026 case VMX_EXIT_XRSTORS:
3027 case VMX_EXIT_XSAVES:
3028 case VMX_EXIT_RDRAND:
3029 case VMX_EXIT_RDSEED:
3030 {
3031 /* Construct the VM-exit instruction information. */
3032 RTGCPTR GCPtrDisp;
3033 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3034
3035 /* Update the VM-exit instruction information. */
3036 ExitInfo.InstrInfo.u = uInstrInfo;
3037
3038 /* Update the VM-exit qualification. */
3039 ExitInfo.u64Qual = GCPtrDisp;
3040 break;
3041 }
3042
3043 default:
3044 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3045 break;
3046 }
3047
3048 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3049}
3050
3051
3052/**
3053 * VMX VM-exit handler for VM-exits due to INVLPG.
3054 *
3055 * @returns Strict VBox status code.
3056 * @param pVCpu The cross context virtual CPU structure.
3057 * @param GCPtrPage The guest-linear address of the page being invalidated.
3058 * @param cbInstr The instruction length in bytes.
3059 */
3060IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3061{
3062 VMXVEXITINFO ExitInfo;
3063 RT_ZERO(ExitInfo);
3064 ExitInfo.uReason = VMX_EXIT_INVLPG;
3065 ExitInfo.cbInstr = cbInstr;
3066 ExitInfo.u64Qual = GCPtrPage;
3067 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3068
3069 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to LMSW.
3075 *
3076 * @returns Strict VBox status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 * @param uGuestCr0 The current guest CR0.
3079 * @param pu16NewMsw The machine-status word specified in LMSW's source
3080 * operand. This will be updated depending on the VMX
3081 * guest/host CR0 mask if LMSW is not intercepted.
3082 * @param GCPtrEffDst The guest-linear address of the source operand in case
3083 * of a memory operand. For register operand, pass
3084 * NIL_RTGCPTR.
3085 * @param cbInstr The instruction length in bytes.
3086 */
3087IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3088 uint8_t cbInstr)
3089{
3090 /*
3091 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3092 *
3093 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3094 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3095 */
3096 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3097 Assert(pVmcs);
3098 Assert(pu16NewMsw);
3099
3100 bool fIntercept = false;
3101 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3102 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3103
3104 /*
3105 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3106 * CR0.PE case first, before the rest of the bits in the MSW.
3107 *
3108 * If CR0.PE is owned by the host and CR0.PE differs between the
3109 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3110 */
3111 if ( (fGstHostMask & X86_CR0_PE)
3112 && (*pu16NewMsw & X86_CR0_PE)
3113 && !(fReadShadow & X86_CR0_PE))
3114 fIntercept = true;
3115
3116 /*
3117 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3118 * bits differ between the MSW (source operand) and the read-shadow, we must
3119 * cause a VM-exit.
3120 */
3121 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3122 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3123 fIntercept = true;
3124
3125 if (fIntercept)
3126 {
3127 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3128
3129 VMXVEXITINFO ExitInfo;
3130 RT_ZERO(ExitInfo);
3131 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3132 ExitInfo.cbInstr = cbInstr;
3133
3134 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3135 if (fMemOperand)
3136 {
3137 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3138 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3139 }
3140
3141 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3142 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3143 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3144 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3145
3146 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3147 }
3148
3149 /*
3150 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3151 * CR0 guest/host mask must be left unmodified.
3152 *
3153 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3154 */
3155 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3156 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3157
3158 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3159}
3160
3161
3162/**
3163 * VMX VM-exit handler for VM-exits due to CLTS.
3164 *
3165 * @returns Strict VBox status code.
3166 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3167 * VM-exit but must not modify the guest CR0.TS bit.
3168 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3169 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3170 * CR0 fixed bits in VMX operation).
3171 * @param pVCpu The cross context virtual CPU structure.
3172 * @param cbInstr The instruction length in bytes.
3173 */
3174IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3175{
3176 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3177 Assert(pVmcs);
3178
3179 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3180 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3181
3182 /*
3183 * If CR0.TS is owned by the host:
3184 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3185 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3186 * CLTS instruction completes without clearing CR0.TS.
3187 *
3188 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3189 */
3190 if (fGstHostMask & X86_CR0_TS)
3191 {
3192 if (fReadShadow & X86_CR0_TS)
3193 {
3194 Log2(("clts: Guest intercept -> VM-exit\n"));
3195
3196 VMXVEXITINFO ExitInfo;
3197 RT_ZERO(ExitInfo);
3198 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3199 ExitInfo.cbInstr = cbInstr;
3200 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3201 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3202 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3203 }
3204
3205 return VINF_VMX_MODIFIES_BEHAVIOR;
3206 }
3207
3208 /*
3209 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3210 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3211 */
3212 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3213}
3214
3215
3216/**
3217 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3218 * (CR0/CR4 write).
3219 *
3220 * @returns Strict VBox status code.
3221 * @param pVCpu The cross context virtual CPU structure.
3222 * @param iCrReg The control register (either CR0 or CR4).
3223 * @param uGuestCrX The current guest CR0/CR4.
3224 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3225 * if no VM-exit is caused.
3226 * @param iGReg The general register from which the CR0/CR4 value is
3227 * being loaded.
3228 * @param cbInstr The instruction length in bytes.
3229 */
3230IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3231 uint8_t cbInstr)
3232{
3233 Assert(puNewCrX);
3234 Assert(iCrReg == 0 || iCrReg == 4);
3235 Assert(iGReg < X86_GREG_COUNT);
3236
3237 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3238 Assert(pVmcs);
3239
3240 uint64_t uGuestCrX;
3241 uint64_t fGstHostMask;
3242 uint64_t fReadShadow;
3243 if (iCrReg == 0)
3244 {
3245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3246 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3247 fGstHostMask = pVmcs->u64Cr0Mask.u;
3248 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3249 }
3250 else
3251 {
3252 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3253 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3254 fGstHostMask = pVmcs->u64Cr4Mask.u;
3255 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3256 }
3257
3258 /*
3259 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3260 * corresponding bits differ between the source operand and the read-shadow,
3261 * we must cause a VM-exit.
3262 *
3263 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3264 */
3265 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3266 {
3267 Assert(fGstHostMask != 0);
3268 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3269
3270 VMXVEXITINFO ExitInfo;
3271 RT_ZERO(ExitInfo);
3272 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3273 ExitInfo.cbInstr = cbInstr;
3274 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3277 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3278 }
3279
3280 /*
3281 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3282 * must not be modified the instruction.
3283 *
3284 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3285 */
3286 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3287
3288 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3289}
3290
3291
3292/**
3293 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3294 *
3295 * @returns VBox strict status code.
3296 * @param pVCpu The cross context virtual CPU structure.
3297 * @param iGReg The general register to which the CR3 value is being stored.
3298 * @param cbInstr The instruction length in bytes.
3299 */
3300IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3301{
3302 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3303 Assert(pVmcs);
3304 Assert(iGReg < X86_GREG_COUNT);
3305 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3306
3307 /*
3308 * If the CR3-store exiting control is set, we must cause a VM-exit.
3309 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3310 */
3311 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3312 {
3313 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3314
3315 VMXVEXITINFO ExitInfo;
3316 RT_ZERO(ExitInfo);
3317 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3318 ExitInfo.cbInstr = cbInstr;
3319 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3321 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3322 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3323 }
3324
3325 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3326}
3327
3328
3329/**
3330 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3331 *
3332 * @returns VBox strict status code.
3333 * @param pVCpu The cross context virtual CPU structure.
3334 * @param uNewCr3 The new CR3 value.
3335 * @param iGReg The general register from which the CR3 value is being
3336 * loaded.
3337 * @param cbInstr The instruction length in bytes.
3338 */
3339IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3340{
3341 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3342 Assert(pVmcs);
3343 Assert(iGReg < X86_GREG_COUNT);
3344
3345 /*
3346 * If the CR3-load exiting control is set and the new CR3 value does not
3347 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3348 *
3349 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3350 */
3351 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3352 {
3353 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3354 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3355
3356 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3357 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3358 if (!fIntercept)
3359 {
3360 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3361 {
3362 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3363 if (uNewCr3 != uCr3TargetValue)
3364 {
3365 fIntercept = true;
3366 break;
3367 }
3368 }
3369 }
3370
3371 if (fIntercept)
3372 {
3373 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3374
3375 VMXVEXITINFO ExitInfo;
3376 RT_ZERO(ExitInfo);
3377 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3378 ExitInfo.cbInstr = cbInstr;
3379 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3380 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3381 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3382 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3383 }
3384 }
3385
3386 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3387}
3388
3389
3390/**
3391 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3392 *
3393 * @returns VBox strict status code.
3394 * @param pVCpu The cross context virtual CPU structure.
3395 * @param iGReg The general register to which the CR8 value is being stored.
3396 * @param cbInstr The instruction length in bytes.
3397 */
3398IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3399{
3400 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3401 Assert(pVmcs);
3402 Assert(iGReg < X86_GREG_COUNT);
3403
3404 /*
3405 * If the CR8-store exiting control is set, we must cause a VM-exit.
3406 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3407 */
3408 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3409 {
3410 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3411
3412 VMXVEXITINFO ExitInfo;
3413 RT_ZERO(ExitInfo);
3414 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3415 ExitInfo.cbInstr = cbInstr;
3416 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3417 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3418 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3419 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3420 }
3421
3422 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3423}
3424
3425
3426/**
3427 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3428 *
3429 * @returns VBox strict status code.
3430 * @param pVCpu The cross context virtual CPU structure.
3431 * @param iGReg The general register from which the CR8 value is being
3432 * loaded.
3433 * @param cbInstr The instruction length in bytes.
3434 */
3435IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3436{
3437 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3438 Assert(pVmcs);
3439 Assert(iGReg < X86_GREG_COUNT);
3440
3441 /*
3442 * If the CR8-load exiting control is set, we must cause a VM-exit.
3443 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3444 */
3445 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3446 {
3447 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3448
3449 VMXVEXITINFO ExitInfo;
3450 RT_ZERO(ExitInfo);
3451 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3452 ExitInfo.cbInstr = cbInstr;
3453 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3454 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3455 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3456 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3457 }
3458
3459 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3460}
3461
3462
3463/**
3464 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3465 * GReg,DRx' (DRx read).
3466 *
3467 * @returns VBox strict status code.
3468 * @param pVCpu The cross context virtual CPU structure.
3469 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3470 * VMXINSTRID_MOV_FROM_DRX).
3471 * @param iDrReg The debug register being accessed.
3472 * @param iGReg The general register to/from which the DRx value is being
3473 * store/loaded.
3474 * @param cbInstr The instruction length in bytes.
3475 */
3476IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3477 uint8_t cbInstr)
3478{
3479 Assert(iDrReg <= 7);
3480 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3481 Assert(iGReg < X86_GREG_COUNT);
3482
3483 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3484 Assert(pVmcs);
3485
3486 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3487 {
3488 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3489 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3490 VMXVEXITINFO ExitInfo;
3491 RT_ZERO(ExitInfo);
3492 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3493 ExitInfo.cbInstr = cbInstr;
3494 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3495 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3496 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3497 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3498 }
3499
3500 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3501}
3502
3503
3504/**
3505 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3506 *
3507 * @returns VBox strict status code.
3508 * @param pVCpu The cross context virtual CPU structure.
3509 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3510 * VMXINSTRID_IO_OUT).
3511 * @param u16Port The I/O port being accessed.
3512 * @param fImm Whether the I/O port was encoded using an immediate operand
3513 * or the implicit DX register.
3514 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3515 * @param cbInstr The instruction length in bytes.
3516 */
3517IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3518 uint8_t cbInstr)
3519{
3520 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3521 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3522
3523 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3524 if (fIntercept)
3525 {
3526 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3527 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3528 VMXVEXITINFO ExitInfo;
3529 RT_ZERO(ExitInfo);
3530 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3531 ExitInfo.cbInstr = cbInstr;
3532 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3533 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3534 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3535 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3536 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3537 }
3538
3539 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3540}
3541
3542
3543/**
3544 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3549 * VMXINSTRID_IO_OUTS).
3550 * @param u16Port The I/O port being accessed.
3551 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3552 * @param fRep Whether the instruction has a REP prefix or not.
3553 * @param ExitInstrInfo The VM-exit instruction info. field.
3554 * @param cbInstr The instruction length in bytes.
3555 */
3556IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3557 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3558{
3559 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3560 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3561 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3562 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3563 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3564
3565 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3566 if (fIntercept)
3567 {
3568 /*
3569 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3570 */
3571 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3572 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3573 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3574 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3575 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3576
3577 uint32_t uDirection;
3578 uint64_t uGuestLinearAddr;
3579 if (uInstrId == VMXINSTRID_IO_INS)
3580 {
3581 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3582 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3583 }
3584 else
3585 {
3586 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3587 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3588 }
3589
3590 /*
3591 * If the segment is unusable, the guest-linear address in undefined.
3592 * We shall clear it for consistency.
3593 *
3594 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3595 */
3596 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3597 uGuestLinearAddr = 0;
3598
3599 VMXVEXITINFO ExitInfo;
3600 RT_ZERO(ExitInfo);
3601 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3602 ExitInfo.cbInstr = cbInstr;
3603 ExitInfo.InstrInfo = ExitInstrInfo;
3604 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3605 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3606 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3607 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3608 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3609 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3610 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3611 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3612 }
3613
3614 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3615}
3616
3617
3618/**
3619 * VMX VM-exit handler for VM-exits due to MWAIT.
3620 *
3621 * @returns VBox strict status code.
3622 * @param pVCpu The cross context virtual CPU structure.
3623 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3624 * @param cbInstr The instruction length in bytes.
3625 */
3626IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3627{
3628 VMXVEXITINFO ExitInfo;
3629 RT_ZERO(ExitInfo);
3630 ExitInfo.uReason = VMX_EXIT_MWAIT;
3631 ExitInfo.cbInstr = cbInstr;
3632 ExitInfo.u64Qual = fMonitorHwArmed;
3633 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3634}
3635
3636
3637/**
3638 * VMX VM-exit handler for VM-exits due to PAUSE.
3639 *
3640 * @returns VBox strict status code.
3641 * @param pVCpu The cross context virtual CPU structure.
3642 * @param cbInstr The instruction length in bytes.
3643 */
3644IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3645{
3646 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3647 Assert(pVmcs);
3648
3649 /*
3650 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3651 * "PAUSE-loop exiting" control.
3652 *
3653 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3654 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3655 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3656 * a VM-exit.
3657 *
3658 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3659 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3660 */
3661 bool fIntercept = false;
3662 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3663 fIntercept = true;
3664 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3665 && pVCpu->iem.s.uCpl == 0)
3666 {
3667 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3668
3669 /*
3670 * A previous-PAUSE-tick value of 0 is used to identify the first time
3671 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3672 * consider this to be the first execution of PAUSE in a loop according
3673 * to the Intel.
3674 *
3675 * All subsequent records for the previous-PAUSE-tick we ensure that it
3676 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3677 */
3678 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3679 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3680 uint64_t const uTick = TMCpuTickGet(pVCpu);
3681 uint32_t const uPleGap = pVmcs->u32PleGap;
3682 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3683 if ( *puPrevPauseTick == 0
3684 || uTick - *puPrevPauseTick > uPleGap)
3685 *puFirstPauseLoopTick = uTick;
3686 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3687 fIntercept = true;
3688
3689 *puPrevPauseTick = uTick | 1;
3690 }
3691
3692 if (fIntercept)
3693 {
3694 VMXVEXITINFO ExitInfo;
3695 RT_ZERO(ExitInfo);
3696 ExitInfo.uReason = VMX_EXIT_PAUSE;
3697 ExitInfo.cbInstr = cbInstr;
3698 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3699 }
3700
3701 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3702}
3703
3704
3705/**
3706 * VMX VM-exit handler for VM-exits due to task switches.
3707 *
3708 * @returns VBox strict status code.
3709 * @param pVCpu The cross context virtual CPU structure.
3710 * @param enmTaskSwitch The cause of the task switch.
3711 * @param SelNewTss The selector of the new TSS.
3712 * @param cbInstr The instruction length in bytes.
3713 */
3714IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3715{
3716 /*
3717 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3718 *
3719 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3720 * instruction or delivery of the exception generated by one of these instructions
3721 * lead to a task switch through a task gate in the IDT, we need to provide the
3722 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3723 * leaves the VM-exit instruction length field undefined.
3724 *
3725 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3726 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3727 */
3728 Assert(cbInstr <= 15);
3729
3730 uint8_t uType;
3731 switch (enmTaskSwitch)
3732 {
3733 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3734 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3735 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3736 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3737 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3738 }
3739
3740 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3741 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3742 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3743 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3745}
3746
3747
3748/**
3749 * VMX VM-exit handler for VM-exits due to task switches.
3750 *
3751 * This is intended for task switches where the caller provides all the relevant
3752 * VM-exit information.
3753 *
3754 * @returns VBox strict status code.
3755 * @param pVCpu The cross context virtual CPU structure.
3756 * @param pExitInfo Pointer to the VM-exit information.
3757 * @param pExitEventInfo Pointer to the VM-exit event information.
3758 */
3759IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PVMXVEXITINFO pExitInfo, PVMXVEXITEVENTINFO pExitEventInfo)
3760{
3761 Assert(pExitInfo);
3762 Assert(pExitEventInfo);
3763
3764 /* The VM-exit qualification is mandatory for all task-switch VM-exits. */
3765 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3766 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3767
3768 /*
3769 * Figure out if an instruction was the source of the task switch.
3770 *
3771 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3772 * of an event generated by a software interrupt (INT-N), privileged software
3773 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3774 * the instruction length.
3775 */
3776 bool fHasInstrLen;
3777 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3778 {
3779 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3780 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3781 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3782 if (fIdtVectInfoValid)
3783 {
3784 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3785 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3786 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3787
3788 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3789 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3790 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3791 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3792 fHasInstrLen = true;
3793 else
3794 fHasInstrLen = false;
3795 }
3796 else
3797 fHasInstrLen = false;
3798 }
3799 else
3800 {
3801 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3802 fHasInstrLen = true;
3803 }
3804
3805 if (fHasInstrLen)
3806 {
3807 Assert(pExitInfo->cbInstr > 0);
3808 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3809 }
3810 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3811}
3812
3813
3814/**
3815 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3816 *
3817 * @returns VBox strict status code.
3818 * @param pVCpu The cross context virtual CPU structure.
3819 */
3820IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3821{
3822 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3823 Assert(pVmcs);
3824
3825 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3826 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3827 {
3828 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3829 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3830
3831 /*
3832 * Calculate the current VMX-preemption timer value.
3833 * Only if the value has reached zero, we cause the VM-exit.
3834 */
3835 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3836 if (!uPreemptTimer)
3837 {
3838 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3839 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3840 pVmcs->u32PreemptTimer = 0;
3841
3842 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3843 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3844 }
3845 }
3846
3847 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3848}
3849
3850
3851/**
3852 * VMX VM-exit handler for VM-exits due to external interrupts.
3853 *
3854 * @returns VBox strict status code.
3855 * @param pVCpu The cross context virtual CPU structure.
3856 * @param uVector The external interrupt vector (pass 0 if the interrupt
3857 * is still pending since we typically won't know the
3858 * vector).
3859 * @param fIntPending Whether the external interrupt is pending or
3860 * acknowledged in the interrupt controller.
3861 */
3862IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3863{
3864 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3865 Assert(pVmcs);
3866 Assert(fIntPending || uVector == 0);
3867
3868 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3869 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3870 * functions require prior checking of a blanket intercept and which don't.
3871 * It is better for the caller to check a blanket intercept performance wise
3872 * than making a function call. Leaving this as a todo because it is more
3873 * a performance issue. */
3874
3875 /* The VM-exit is subject to "External interrupt exiting" being set. */
3876 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3877 {
3878 if (fIntPending)
3879 {
3880 /*
3881 * If the interrupt is pending and we don't need to acknowledge the
3882 * interrupt on VM-exit, cause the VM-exit immediately.
3883 *
3884 * See Intel spec 25.2 "Other Causes Of VM Exits".
3885 */
3886 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3887 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3888
3889 /*
3890 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3891 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3892 * acknowledged that the interrupt has been consumed.
3893 */
3894 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3895 }
3896
3897 /*
3898 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3899 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3900 * all set, we cause the VM-exit now. We need to record the external interrupt that
3901 * just occurred in the VM-exit interruption information field.
3902 *
3903 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3904 */
3905 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3906 {
3907 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3908 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3909 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3910 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3911 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3912 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3913 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3914 }
3915 }
3916
3917 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3918}
3919
3920
3921/**
3922 * VMX VM-exit handler for VM-exits due to NMIs.
3923 *
3924 * @returns VBox strict status code.
3925 * @param pVCpu The cross context virtual CPU structure.
3926 *
3927 * @remarks This function might import externally kept DR6 if necessary.
3928 */
3929IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3930{
3931 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3932 Assert(pVmcs);
3933 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3934 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3935 NOREF(pVmcs);
3936 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3937}
3938
3939
3940/**
3941 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3942 *
3943 * @returns VBox strict status code.
3944 * @param pVCpu The cross context virtual CPU structure.
3945 * @param uVector The SIPI vector.
3946 */
3947IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3948{
3949 iemVmxVmcsSetExitQual(pVCpu, uVector);
3950 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3951}
3952
3953
3954/**
3955 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3956 * an event.
3957 *
3958 * @returns VBox strict status code.
3959 * @param pVCpu The cross context virtual CPU structure.
3960 */
3961IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3962{
3963 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3964 Assert(pVmcs);
3965
3966 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3967 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3968 {
3969 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3970 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3971 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3972 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3973 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3974 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3975 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3976 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3977 iemVmxVmcsSetExitQual(pVCpu, 0);
3978 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3979
3980 /*
3981 * A VM-exit is not considered to occur during event delivery when the original
3982 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3983 * using the exception bitmap).
3984 *
3985 * Therefore, we must clear the original event from the IDT-vectoring fields which
3986 * would've been recorded before causing the VM-exit.
3987 *
3988 * 27.2.3 "Information for VM Exits During Event Delivery"
3989 */
3990 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3991 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3992
3993 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3994 }
3995
3996 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3997}
3998
3999
4000/**
4001 * VMX VM-exit handler for VM-exits due to delivery of an event.
4002 *
4003 * @returns VBox strict status code.
4004 * @param pVCpu The cross context virtual CPU structure.
4005 * @param uVector The interrupt / exception vector.
4006 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
4007 * @param uErrCode The error code associated with the event.
4008 * @param uCr2 The CR2 value in case of a \#PF exception.
4009 * @param cbInstr The instruction length in bytes.
4010 */
4011IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
4012 uint8_t cbInstr)
4013{
4014 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4015 Assert(pVmcs);
4016
4017 /*
4018 * If the event is being injected as part of VM-entry, it isn't subject to event
4019 * intercepts in the nested-guest. However, secondary exceptions that occur during
4020 * injection of any event -are- subject to event interception.
4021 *
4022 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
4023 */
4024 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
4025 {
4026 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
4027 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
4028 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4029 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
4030 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
4031 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
4032 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
4033 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
4034 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
4035
4036 /*
4037 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
4038 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
4039 *
4040 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
4041 */
4042 if ( uVector == X86_XCPT_NMI
4043 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
4044 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
4045 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
4046 else
4047 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
4048
4049 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4050 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4051 }
4052
4053 /*
4054 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4055 * If not, the caller will continue delivery of the external interrupt as it would
4056 * normally. The interrupt is no longer pending in the interrupt controller at this
4057 * point.
4058 */
4059 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4060 {
4061 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4062 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4063 }
4064
4065 /*
4066 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4067 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4068 */
4069 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4070 bool fIntercept = false;
4071 bool fIsHwXcpt = false;
4072 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4073 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4074 {
4075 fIsHwXcpt = true;
4076
4077 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4078 if (uVector == X86_XCPT_NMI)
4079 {
4080 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
4081 fIntercept = true;
4082 }
4083 else
4084 {
4085 /* Page-faults are subject to masking using its error code. */
4086 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4087 if (uVector == X86_XCPT_PF)
4088 {
4089 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4090 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4091 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4092 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4093 }
4094
4095 /* Consult the exception bitmap for all other hardware exceptions. */
4096 Assert(uVector <= X86_XCPT_LAST);
4097 if (fXcptBitmap & RT_BIT(uVector))
4098 fIntercept = true;
4099 }
4100 }
4101 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4102
4103 /*
4104 * Now that we've determined whether the software interrupt or hardware exception
4105 * causes a VM-exit, we need to construct the relevant VM-exit information and
4106 * cause the VM-exit.
4107 */
4108 if (fIntercept)
4109 {
4110 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4111
4112 /* Construct the rest of the event related information fields and cause the VM-exit. */
4113 uint64_t uExitQual = 0;
4114 if (fIsHwXcpt)
4115 {
4116 if (uVector == X86_XCPT_PF)
4117 {
4118 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4119 uExitQual = uCr2;
4120 }
4121 else if (uVector == X86_XCPT_DB)
4122 {
4123 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4124 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4125 }
4126 }
4127
4128 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4129 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4130 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4131 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4132 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4133 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4134 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4135 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4136 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4137 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4138 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4139
4140 /*
4141 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4142 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4143 * length.
4144 */
4145 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4146 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4147 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4148 else
4149 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4150
4151 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4152 }
4153
4154 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4155}
4156
4157
4158/**
4159 * VMX VM-exit handler for VM-exits due to a triple fault.
4160 *
4161 * @returns VBox strict status code.
4162 * @param pVCpu The cross context virtual CPU structure.
4163 */
4164IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4165{
4166 /*
4167 * A VM-exit is not considered to occur during event delivery when the original
4168 * event results in a triple-fault.
4169 *
4170 * Therefore, we must clear the original event from the IDT-vectoring fields which
4171 * would've been recorded before causing the VM-exit.
4172 *
4173 * 27.2.3 "Information for VM Exits During Event Delivery"
4174 */
4175 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4176 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4177
4178 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4179}
4180
4181
4182/**
4183 * VMX VM-exit handler for APIC-accesses.
4184 *
4185 * @param pVCpu The cross context virtual CPU structure.
4186 * @param offAccess The offset of the register being accessed.
4187 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4188 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4189 */
4190IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4191{
4192 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4193
4194 VMXAPICACCESS enmAccess;
4195 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4196 if (fInEventDelivery)
4197 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4198 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4199 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4200 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4201 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4202 else
4203 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4204
4205 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4206 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4207 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4208 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4209}
4210
4211
4212/**
4213 * VMX VM-exit handler for APIC-write VM-exits.
4214 *
4215 * @param pVCpu The cross context virtual CPU structure.
4216 * @param offApic The write to the virtual-APIC page offset that caused this
4217 * VM-exit.
4218 */
4219IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4220{
4221 Assert(offApic < XAPIC_OFF_END + 4);
4222
4223 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4224 offApic &= UINT16_C(0xfff);
4225 iemVmxVmcsSetExitQual(pVCpu, offApic);
4226 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4227}
4228
4229
4230/**
4231 * VMX VM-exit handler for virtualized-EOIs.
4232 *
4233 * @param pVCpu The cross context virtual CPU structure.
4234 */
4235IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4236{
4237 iemVmxVmcsSetExitQual(pVCpu, uVector);
4238 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4239}
4240
4241
4242/**
4243 * Sets virtual-APIC write emulation as pending.
4244 *
4245 * @param pVCpu The cross context virtual CPU structure.
4246 * @param offApic The offset in the virtual-APIC page that was written.
4247 */
4248DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4249{
4250 Assert(offApic < XAPIC_OFF_END + 4);
4251
4252 /*
4253 * Record the currently updated APIC offset, as we need this later for figuring
4254 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4255 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4256 */
4257 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4258
4259 /*
4260 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4261 * virtualization or APIC-write emulation).
4262 */
4263 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4264 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4265}
4266
4267
4268/**
4269 * Clears any pending virtual-APIC write emulation.
4270 *
4271 * @returns The virtual-APIC offset that was written before clearing it.
4272 * @param pVCpu The cross context virtual CPU structure.
4273 */
4274DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4275{
4276 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4277 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4278 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4279 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4280 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4281 return offVirtApicWrite;
4282}
4283
4284
4285/**
4286 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4287 *
4288 * @returns The register from the virtual-APIC page.
4289 * @param pVCpu The cross context virtual CPU structure.
4290 * @param offReg The offset of the register being read.
4291 */
4292IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4293{
4294 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4295 Assert(pVmcs);
4296
4297 uint32_t uReg;
4298 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4299 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4300 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4301 if (RT_FAILURE(rc))
4302 {
4303 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4304 GCPhysVirtApic));
4305 uReg = 0;
4306 }
4307 return uReg;
4308}
4309
4310
4311/**
4312 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4313 *
4314 * @returns The register from the virtual-APIC page.
4315 * @param pVCpu The cross context virtual CPU structure.
4316 * @param offReg The offset of the register being read.
4317 */
4318IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4319{
4320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4321 Assert(pVmcs);
4322
4323 uint64_t uReg;
4324 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4325 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4326 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4327 if (RT_FAILURE(rc))
4328 {
4329 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4330 GCPhysVirtApic));
4331 uReg = 0;
4332 }
4333 return uReg;
4334}
4335
4336
4337/**
4338 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4339 *
4340 * @param pVCpu The cross context virtual CPU structure.
4341 * @param offReg The offset of the register being written.
4342 * @param uReg The register value to write.
4343 */
4344IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4345{
4346 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4347 Assert(pVmcs);
4348 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4349 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4350 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4351 if (RT_FAILURE(rc))
4352 {
4353 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4354 GCPhysVirtApic));
4355 }
4356}
4357
4358
4359/**
4360 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4361 *
4362 * @param pVCpu The cross context virtual CPU structure.
4363 * @param offReg The offset of the register being written.
4364 * @param uReg The register value to write.
4365 */
4366IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4367{
4368 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4369 Assert(pVmcs);
4370 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4371 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4372 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4373 if (RT_FAILURE(rc))
4374 {
4375 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4376 GCPhysVirtApic));
4377 }
4378}
4379
4380
4381/**
4382 * Sets the vector in a virtual-APIC 256-bit sparse register.
4383 *
4384 * @param pVCpu The cross context virtual CPU structure.
4385 * @param offReg The offset of the 256-bit spare register.
4386 * @param uVector The vector to set.
4387 *
4388 * @remarks This is based on our APIC device code.
4389 */
4390IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4391{
4392 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4393 Assert(pVmcs);
4394 uint32_t uReg;
4395 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4396 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4397 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4398 if (RT_SUCCESS(rc))
4399 {
4400 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4401 uReg |= RT_BIT(idxVectorBit);
4402 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4403 if (RT_FAILURE(rc))
4404 {
4405 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4406 uVector, offReg, GCPhysVirtApic));
4407 }
4408 }
4409 else
4410 {
4411 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4412 uVector, offReg, GCPhysVirtApic));
4413 }
4414}
4415
4416
4417/**
4418 * Clears the vector in a virtual-APIC 256-bit sparse register.
4419 *
4420 * @param pVCpu The cross context virtual CPU structure.
4421 * @param offReg The offset of the 256-bit spare register.
4422 * @param uVector The vector to clear.
4423 *
4424 * @remarks This is based on our APIC device code.
4425 */
4426IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4427{
4428 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4429 Assert(pVmcs);
4430 uint32_t uReg;
4431 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4432 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4433 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4434 if (RT_SUCCESS(rc))
4435 {
4436 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4437 uReg &= ~RT_BIT(idxVectorBit);
4438 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4439 if (RT_FAILURE(rc))
4440 {
4441 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4442 uVector, offReg, GCPhysVirtApic));
4443 }
4444 }
4445 else
4446 {
4447 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4448 uVector, offReg, GCPhysVirtApic));
4449 }
4450}
4451
4452
4453/**
4454 * Checks if a memory access to the APIC-access page must causes an APIC-access
4455 * VM-exit.
4456 *
4457 * @param pVCpu The cross context virtual CPU structure.
4458 * @param offAccess The offset of the register being accessed.
4459 * @param cbAccess The size of the access in bytes.
4460 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4461 * IEM_ACCESS_TYPE_WRITE).
4462 *
4463 * @remarks This must not be used for MSR-based APIC-access page accesses!
4464 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4465 */
4466IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4467{
4468 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4469 Assert(pVmcs);
4470 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4471
4472 /*
4473 * We must cause a VM-exit if any of the following are true:
4474 * - TPR shadowing isn't active.
4475 * - The access size exceeds 32-bits.
4476 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4477 *
4478 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4479 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4480 */
4481 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4482 || cbAccess > sizeof(uint32_t)
4483 || ((offAccess + cbAccess - 1) & 0xc)
4484 || offAccess >= XAPIC_OFF_END + 4)
4485 return true;
4486
4487 /*
4488 * If the access is part of an operation where we have already
4489 * virtualized a virtual-APIC write, we must cause a VM-exit.
4490 */
4491 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4492 return true;
4493
4494 /*
4495 * Check write accesses to the APIC-access page that cause VM-exits.
4496 */
4497 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4498 {
4499 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4500 {
4501 /*
4502 * With APIC-register virtualization, a write access to any of the
4503 * following registers are virtualized. Accessing any other register
4504 * causes a VM-exit.
4505 */
4506 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4507 switch (offAlignedAccess)
4508 {
4509 case XAPIC_OFF_ID:
4510 case XAPIC_OFF_TPR:
4511 case XAPIC_OFF_EOI:
4512 case XAPIC_OFF_LDR:
4513 case XAPIC_OFF_DFR:
4514 case XAPIC_OFF_SVR:
4515 case XAPIC_OFF_ESR:
4516 case XAPIC_OFF_ICR_LO:
4517 case XAPIC_OFF_ICR_HI:
4518 case XAPIC_OFF_LVT_TIMER:
4519 case XAPIC_OFF_LVT_THERMAL:
4520 case XAPIC_OFF_LVT_PERF:
4521 case XAPIC_OFF_LVT_LINT0:
4522 case XAPIC_OFF_LVT_LINT1:
4523 case XAPIC_OFF_LVT_ERROR:
4524 case XAPIC_OFF_TIMER_ICR:
4525 case XAPIC_OFF_TIMER_DCR:
4526 break;
4527 default:
4528 return true;
4529 }
4530 }
4531 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4532 {
4533 /*
4534 * With virtual-interrupt delivery, a write access to any of the
4535 * following registers are virtualized. Accessing any other register
4536 * causes a VM-exit.
4537 *
4538 * Note! The specification does not allow writing to offsets in-between
4539 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4540 */
4541 switch (offAccess)
4542 {
4543 case XAPIC_OFF_TPR:
4544 case XAPIC_OFF_EOI:
4545 case XAPIC_OFF_ICR_LO:
4546 break;
4547 default:
4548 return true;
4549 }
4550 }
4551 else
4552 {
4553 /*
4554 * Without APIC-register virtualization or virtual-interrupt delivery,
4555 * only TPR accesses are virtualized.
4556 */
4557 if (offAccess == XAPIC_OFF_TPR)
4558 { /* likely */ }
4559 else
4560 return true;
4561 }
4562 }
4563 else
4564 {
4565 /*
4566 * Check read accesses to the APIC-access page that cause VM-exits.
4567 */
4568 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4569 {
4570 /*
4571 * With APIC-register virtualization, a read access to any of the
4572 * following registers are virtualized. Accessing any other register
4573 * causes a VM-exit.
4574 */
4575 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4576 switch (offAlignedAccess)
4577 {
4578 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4579 case XAPIC_OFF_ID:
4580 case XAPIC_OFF_VERSION:
4581 case XAPIC_OFF_TPR:
4582 case XAPIC_OFF_EOI:
4583 case XAPIC_OFF_LDR:
4584 case XAPIC_OFF_DFR:
4585 case XAPIC_OFF_SVR:
4586 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4587 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4588 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4589 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4590 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4591 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4592 case XAPIC_OFF_ESR:
4593 case XAPIC_OFF_ICR_LO:
4594 case XAPIC_OFF_ICR_HI:
4595 case XAPIC_OFF_LVT_TIMER:
4596 case XAPIC_OFF_LVT_THERMAL:
4597 case XAPIC_OFF_LVT_PERF:
4598 case XAPIC_OFF_LVT_LINT0:
4599 case XAPIC_OFF_LVT_LINT1:
4600 case XAPIC_OFF_LVT_ERROR:
4601 case XAPIC_OFF_TIMER_ICR:
4602 case XAPIC_OFF_TIMER_DCR:
4603 break;
4604 default:
4605 return true;
4606 }
4607 }
4608 else
4609 {
4610 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4611 if (offAccess == XAPIC_OFF_TPR)
4612 { /* likely */ }
4613 else
4614 return true;
4615 }
4616 }
4617
4618 /* The APIC-access is virtualized, does not cause a VM-exit. */
4619 return false;
4620}
4621
4622
4623/**
4624 * Virtualizes a memory-based APIC-access where the address is not used to access
4625 * memory.
4626 *
4627 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4628 * page-faults but do not use the address to access memory.
4629 *
4630 * @param pVCpu The cross context virtual CPU structure.
4631 * @param pGCPhysAccess Pointer to the guest-physical address used.
4632 */
4633IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4634{
4635 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4636 Assert(pVmcs);
4637 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4638 Assert(pGCPhysAccess);
4639
4640 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4641 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4642 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4643
4644 if (GCPhysAccess == GCPhysApic)
4645 {
4646 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4647 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4648 uint16_t const cbAccess = 1;
4649 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4650 if (fIntercept)
4651 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4652
4653 *pGCPhysAccess = GCPhysApic | offAccess;
4654 return VINF_VMX_MODIFIES_BEHAVIOR;
4655 }
4656
4657 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4658}
4659
4660
4661/**
4662 * Virtualizes a memory-based APIC-access.
4663 *
4664 * @returns VBox strict status code.
4665 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4666 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4667 *
4668 * @param pVCpu The cross context virtual CPU structure.
4669 * @param offAccess The offset of the register being accessed (within the
4670 * APIC-access page).
4671 * @param cbAccess The size of the access in bytes.
4672 * @param pvData Pointer to the data being written or where to store the data
4673 * being read.
4674 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4675 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4676 */
4677IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4678 uint32_t fAccess)
4679{
4680 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4681 Assert(pVmcs);
4682 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4683 Assert(pvData);
4684 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4685 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4686 || (fAccess & IEM_ACCESS_INSTRUCTION));
4687
4688 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4689 if (fIntercept)
4690 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4691
4692 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4693 {
4694 /*
4695 * A write access to the APIC-access page that is virtualized (rather than
4696 * causing a VM-exit) writes data to the virtual-APIC page.
4697 */
4698 uint32_t const u32Data = *(uint32_t *)pvData;
4699 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4700
4701 /*
4702 * Record the currently updated APIC offset, as we need this later for figuring
4703 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4704 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4705 *
4706 * After completion of the current operation, we need to perform TPR virtualization,
4707 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4708 *
4709 * The current operation may be a REP-prefixed string instruction, execution of any
4710 * other instruction, or delivery of an event through the IDT.
4711 *
4712 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4713 * performed now but later after completion of the current operation.
4714 *
4715 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4716 */
4717 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4718 }
4719 else
4720 {
4721 /*
4722 * A read access from the APIC-access page that is virtualized (rather than
4723 * causing a VM-exit) returns data from the virtual-APIC page.
4724 *
4725 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4726 */
4727 Assert(cbAccess <= 4);
4728 Assert(offAccess < XAPIC_OFF_END + 4);
4729 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4730
4731 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4732 u32Data &= s_auAccessSizeMasks[cbAccess];
4733 *(uint32_t *)pvData = u32Data;
4734 }
4735
4736 return VINF_VMX_MODIFIES_BEHAVIOR;
4737}
4738
4739
4740/**
4741 * Virtualizes an MSR-based APIC read access.
4742 *
4743 * @returns VBox strict status code.
4744 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4745 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4746 * handled by the x2APIC device.
4747 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4748 * not within the range of valid MSRs, caller must raise \#GP(0).
4749 * @param pVCpu The cross context virtual CPU structure.
4750 * @param idMsr The x2APIC MSR being read.
4751 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4752 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4753 */
4754IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4755{
4756 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4757 Assert(pVmcs);
4758 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4759 Assert(pu64Value);
4760
4761 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4762 {
4763 /*
4764 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4765 * what the end of the valid x2APIC MSR range is. Hence the use of different
4766 * macros here.
4767 *
4768 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4769 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4770 */
4771 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4772 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4773 {
4774 uint16_t const offReg = (idMsr & 0xff) << 4;
4775 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4776 *pu64Value = u64Value;
4777 return VINF_VMX_MODIFIES_BEHAVIOR;
4778 }
4779 return VERR_OUT_OF_RANGE;
4780 }
4781
4782 if (idMsr == MSR_IA32_X2APIC_TPR)
4783 {
4784 uint16_t const offReg = (idMsr & 0xff) << 4;
4785 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4786 *pu64Value = u64Value;
4787 return VINF_VMX_MODIFIES_BEHAVIOR;
4788 }
4789
4790 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4791}
4792
4793
4794/**
4795 * Virtualizes an MSR-based APIC write access.
4796 *
4797 * @returns VBox strict status code.
4798 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4799 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4800 * not within the range of valid MSRs, caller must raise \#GP(0).
4801 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4802 *
4803 * @param pVCpu The cross context virtual CPU structure.
4804 * @param idMsr The x2APIC MSR being written.
4805 * @param u64Value The value of the x2APIC MSR being written.
4806 */
4807IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4808{
4809 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4810 Assert(pVmcs);
4811
4812 /*
4813 * Check if the access is to be virtualized.
4814 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4815 */
4816 if ( idMsr == MSR_IA32_X2APIC_TPR
4817 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4818 && ( idMsr == MSR_IA32_X2APIC_EOI
4819 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4820 {
4821 /* Validate the MSR write depending on the register. */
4822 switch (idMsr)
4823 {
4824 case MSR_IA32_X2APIC_TPR:
4825 case MSR_IA32_X2APIC_SELF_IPI:
4826 {
4827 if (u64Value & UINT64_C(0xffffffffffffff00))
4828 return VERR_OUT_OF_RANGE;
4829 break;
4830 }
4831 case MSR_IA32_X2APIC_EOI:
4832 {
4833 if (u64Value != 0)
4834 return VERR_OUT_OF_RANGE;
4835 break;
4836 }
4837 }
4838
4839 /* Write the MSR to the virtual-APIC page. */
4840 uint16_t const offReg = (idMsr & 0xff) << 4;
4841 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4842
4843 /*
4844 * Record the currently updated APIC offset, as we need this later for figuring
4845 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4846 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4847 */
4848 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4849
4850 return VINF_VMX_MODIFIES_BEHAVIOR;
4851 }
4852
4853 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4854}
4855
4856
4857/**
4858 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4859 *
4860 * @returns VBox status code.
4861 * @retval VINF_SUCCESS when the highest set bit is found.
4862 * @retval VERR_NOT_FOUND when no bit is set.
4863 *
4864 * @param pVCpu The cross context virtual CPU structure.
4865 * @param offReg The offset of the APIC 256-bit sparse register.
4866 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4867 * set in the register. Only valid when VINF_SUCCESS is
4868 * returned.
4869 *
4870 * @remarks The format of the 256-bit sparse register here mirrors that found in
4871 * real APIC hardware.
4872 */
4873static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4874{
4875 Assert(offReg < XAPIC_OFF_END + 4);
4876 Assert(pidxHighestBit);
4877 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4878
4879 /*
4880 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4881 * However, in each fragment only the first 4 bytes are used.
4882 */
4883 uint8_t const cFrags = 8;
4884 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4885 {
4886 uint16_t const offFrag = iFrag * 16;
4887 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4888 if (!u32Frag)
4889 continue;
4890
4891 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4892 Assert(idxHighestBit > 0);
4893 --idxHighestBit;
4894 Assert(idxHighestBit <= UINT8_MAX);
4895 *pidxHighestBit = idxHighestBit;
4896 return VINF_SUCCESS;
4897 }
4898 return VERR_NOT_FOUND;
4899}
4900
4901
4902/**
4903 * Evaluates pending virtual interrupts.
4904 *
4905 * @param pVCpu The cross context virtual CPU structure.
4906 */
4907IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4908{
4909 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4910 Assert(pVmcs);
4911 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4912
4913 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4914 {
4915 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4916 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4917
4918 if ((uRvi >> 4) > (uPpr >> 4))
4919 {
4920 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4921 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4922 }
4923 else
4924 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4925 }
4926}
4927
4928
4929/**
4930 * Performs PPR virtualization.
4931 *
4932 * @returns VBox strict status code.
4933 * @param pVCpu The cross context virtual CPU structure.
4934 */
4935IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4936{
4937 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4938 Assert(pVmcs);
4939 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4940 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4941
4942 /*
4943 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4944 * or EOI-virtualization.
4945 *
4946 * See Intel spec. 29.1.3 "PPR Virtualization".
4947 */
4948 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4949 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4950
4951 uint32_t uPpr;
4952 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4953 uPpr = uTpr & 0xff;
4954 else
4955 uPpr = uSvi & 0xf0;
4956
4957 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4958 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4959}
4960
4961
4962/**
4963 * Performs VMX TPR virtualization.
4964 *
4965 * @returns VBox strict status code.
4966 * @param pVCpu The cross context virtual CPU structure.
4967 */
4968IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4969{
4970 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4971 Assert(pVmcs);
4972 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4973
4974 /*
4975 * We should have already performed the virtual-APIC write to the TPR offset
4976 * in the virtual-APIC page. We now perform TPR virtualization.
4977 *
4978 * See Intel spec. 29.1.2 "TPR Virtualization".
4979 */
4980 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4981 {
4982 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4983 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4984
4985 /*
4986 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4987 * See Intel spec. 29.1.2 "TPR Virtualization".
4988 */
4989 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4990 {
4991 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4992 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4993 }
4994 }
4995 else
4996 {
4997 iemVmxPprVirtualization(pVCpu);
4998 iemVmxEvalPendingVirtIntrs(pVCpu);
4999 }
5000
5001 return VINF_SUCCESS;
5002}
5003
5004
5005/**
5006 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
5007 * not.
5008 *
5009 * @returns @c true if the EOI write is intercepted, @c false otherwise.
5010 * @param pVCpu The cross context virtual CPU structure.
5011 * @param uVector The interrupt that was acknowledged using an EOI.
5012 */
5013IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
5014{
5015 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5016 Assert(pVmcs);
5017 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5018
5019 if (uVector < 64)
5020 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
5021 if (uVector < 128)
5022 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
5023 if (uVector < 192)
5024 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
5025 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
5026}
5027
5028
5029/**
5030 * Performs EOI virtualization.
5031 *
5032 * @returns VBox strict status code.
5033 * @param pVCpu The cross context virtual CPU structure.
5034 */
5035IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
5036{
5037 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5038 Assert(pVmcs);
5039 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5040
5041 /*
5042 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
5043 * and get the next guest-interrupt that's in-service (if any).
5044 *
5045 * See Intel spec. 29.1.4 "EOI Virtualization".
5046 */
5047 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5048 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5049 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5050
5051 uint8_t uVector = uSvi;
5052 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
5053
5054 uVector = 0;
5055 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5056
5057 if (uVector)
5058 Log2(("eoi_virt: next interrupt %#x\n", uVector));
5059 else
5060 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5061
5062 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5063 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5064
5065 iemVmxPprVirtualization(pVCpu);
5066 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5067 return iemVmxVmexitVirtEoi(pVCpu, uVector);
5068 iemVmxEvalPendingVirtIntrs(pVCpu);
5069 return VINF_SUCCESS;
5070}
5071
5072
5073/**
5074 * Performs self-IPI virtualization.
5075 *
5076 * @returns VBox strict status code.
5077 * @param pVCpu The cross context virtual CPU structure.
5078 */
5079IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5080{
5081 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5082 Assert(pVmcs);
5083 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5084
5085 /*
5086 * We should have already performed the virtual-APIC write to the self-IPI offset
5087 * in the virtual-APIC page. We now perform self-IPI virtualization.
5088 *
5089 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5090 */
5091 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5092 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5093 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5094 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5095 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5096 if (uVector > uRvi)
5097 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5098 iemVmxEvalPendingVirtIntrs(pVCpu);
5099 return VINF_SUCCESS;
5100}
5101
5102
5103/**
5104 * Performs VMX APIC-write emulation.
5105 *
5106 * @returns VBox strict status code.
5107 * @param pVCpu The cross context virtual CPU structure.
5108 */
5109IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5110{
5111 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5112 Assert(pVmcs);
5113
5114 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5115 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5116
5117 /*
5118 * Perform APIC-write emulation based on the virtual-APIC register written.
5119 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5120 */
5121 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5122 VBOXSTRICTRC rcStrict;
5123 switch (offApicWrite)
5124 {
5125 case XAPIC_OFF_TPR:
5126 {
5127 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5128 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5129 uTpr &= UINT32_C(0x000000ff);
5130 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5131 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5132 rcStrict = iemVmxTprVirtualization(pVCpu);
5133 break;
5134 }
5135
5136 case XAPIC_OFF_EOI:
5137 {
5138 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5139 {
5140 /* Clear VEOI and perform EOI virtualization. */
5141 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5142 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5143 rcStrict = iemVmxEoiVirtualization(pVCpu);
5144 }
5145 else
5146 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5147 break;
5148 }
5149
5150 case XAPIC_OFF_ICR_LO:
5151 {
5152 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5153 {
5154 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5155 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5156 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5157 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5158 if ( !(uIcrLo & fIcrLoMb0)
5159 && (uIcrLo & fIcrLoMb1))
5160 {
5161 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5162 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5163 }
5164 else
5165 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5166 }
5167 else
5168 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5169 break;
5170 }
5171
5172 case XAPIC_OFF_ICR_HI:
5173 {
5174 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5175 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5176 uIcrHi &= UINT32_C(0xff000000);
5177 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5178 rcStrict = VINF_SUCCESS;
5179 break;
5180 }
5181
5182 default:
5183 {
5184 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5185 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5186 break;
5187 }
5188 }
5189
5190 return rcStrict;
5191}
5192
5193
5194/**
5195 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5196 *
5197 * @param pVCpu The cross context virtual CPU structure.
5198 * @param pszInstr The VMX instruction name (for logging purposes).
5199 */
5200IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5201{
5202 /*
5203 * Guest Control Registers, Debug Registers, and MSRs.
5204 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5205 */
5206 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5207 const char *const pszFailure = "VM-exit";
5208 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5209
5210 /* CR0 reserved bits. */
5211 {
5212 /* CR0 MB1 bits. */
5213 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5214 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5215 if (fUnrestrictedGuest)
5216 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5217 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5218 { /* likely */ }
5219 else
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5221
5222 /* CR0 MBZ bits. */
5223 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5224 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5225 { /* likely */ }
5226 else
5227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5228
5229 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5230 if ( !fUnrestrictedGuest
5231 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5232 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5234 }
5235
5236 /* CR4 reserved bits. */
5237 {
5238 /* CR4 MB1 bits. */
5239 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5240 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5241 { /* likely */ }
5242 else
5243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5244
5245 /* CR4 MBZ bits. */
5246 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5247 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5251 }
5252
5253 /* DEBUGCTL MSR. */
5254 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5255 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5256 { /* likely */ }
5257 else
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5259
5260 /* 64-bit CPU checks. */
5261 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5262 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5263 {
5264 if (fGstInLongMode)
5265 {
5266 /* PAE must be set. */
5267 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5268 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5269 { /* likely */ }
5270 else
5271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5272 }
5273 else
5274 {
5275 /* PCIDE should not be set. */
5276 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5277 { /* likely */ }
5278 else
5279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5280 }
5281
5282 /* CR3. */
5283 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5284 { /* likely */ }
5285 else
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5287
5288 /* DR7. */
5289 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5290 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5291 { /* likely */ }
5292 else
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5294
5295 /* SYSENTER ESP and SYSENTER EIP. */
5296 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5297 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5298 { /* likely */ }
5299 else
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5301 }
5302
5303 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5304 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5305
5306 /* PAT MSR. */
5307 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5308 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5309 { /* likely */ }
5310 else
5311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5312
5313 /* EFER MSR. */
5314 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5315 {
5316 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5317 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5318 { /* likely */ }
5319 else
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5321
5322 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5323 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5324 if ( fGstLma == fGstInLongMode
5325 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5326 || fGstLma == fGstLme))
5327 { /* likely */ }
5328 else
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5330 }
5331
5332 /* We don't support IA32_BNDCFGS MSR yet. */
5333 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5334
5335 NOREF(pszInstr);
5336 NOREF(pszFailure);
5337 return VINF_SUCCESS;
5338}
5339
5340
5341/**
5342 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5343 *
5344 * @param pVCpu The cross context virtual CPU structure.
5345 * @param pszInstr The VMX instruction name (for logging purposes).
5346 */
5347IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5348{
5349 /*
5350 * Segment registers.
5351 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5352 */
5353 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5354 const char *const pszFailure = "VM-exit";
5355 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5356 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5357 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5358
5359 /* Selectors. */
5360 if ( !fGstInV86Mode
5361 && !fUnrestrictedGuest
5362 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5364
5365 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5366 {
5367 CPUMSELREG SelReg;
5368 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5369 if (RT_LIKELY(rc == VINF_SUCCESS))
5370 { /* likely */ }
5371 else
5372 return rc;
5373
5374 /*
5375 * Virtual-8086 mode checks.
5376 */
5377 if (fGstInV86Mode)
5378 {
5379 /* Base address. */
5380 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5381 { /* likely */ }
5382 else
5383 {
5384 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5386 }
5387
5388 /* Limit. */
5389 if (SelReg.u32Limit == 0xffff)
5390 { /* likely */ }
5391 else
5392 {
5393 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5395 }
5396
5397 /* Attribute. */
5398 if (SelReg.Attr.u == 0xf3)
5399 { /* likely */ }
5400 else
5401 {
5402 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5404 }
5405
5406 /* We're done; move to checking the next segment. */
5407 continue;
5408 }
5409
5410 /* Checks done by 64-bit CPUs. */
5411 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5412 {
5413 /* Base address. */
5414 if ( iSegReg == X86_SREG_FS
5415 || iSegReg == X86_SREG_GS)
5416 {
5417 if (X86_IS_CANONICAL(SelReg.u64Base))
5418 { /* likely */ }
5419 else
5420 {
5421 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5423 }
5424 }
5425 else if (iSegReg == X86_SREG_CS)
5426 {
5427 if (!RT_HI_U32(SelReg.u64Base))
5428 { /* likely */ }
5429 else
5430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5431 }
5432 else
5433 {
5434 if ( SelReg.Attr.n.u1Unusable
5435 || !RT_HI_U32(SelReg.u64Base))
5436 { /* likely */ }
5437 else
5438 {
5439 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5441 }
5442 }
5443 }
5444
5445 /*
5446 * Checks outside Virtual-8086 mode.
5447 */
5448 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5449 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5450 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5451 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5452 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5453 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5454 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5455 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5456
5457 /* Code or usable segment. */
5458 if ( iSegReg == X86_SREG_CS
5459 || fUsable)
5460 {
5461 /* Reserved bits (bits 31:17 and bits 11:8). */
5462 if (!(SelReg.Attr.u & 0xfffe0f00))
5463 { /* likely */ }
5464 else
5465 {
5466 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5468 }
5469
5470 /* Descriptor type. */
5471 if (fCodeDataSeg)
5472 { /* likely */ }
5473 else
5474 {
5475 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5477 }
5478
5479 /* Present. */
5480 if (fPresent)
5481 { /* likely */ }
5482 else
5483 {
5484 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5486 }
5487
5488 /* Granularity. */
5489 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5490 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5491 { /* likely */ }
5492 else
5493 {
5494 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5496 }
5497 }
5498
5499 if (iSegReg == X86_SREG_CS)
5500 {
5501 /* Segment Type and DPL. */
5502 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5503 && fUnrestrictedGuest)
5504 {
5505 if (uDpl == 0)
5506 { /* likely */ }
5507 else
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5509 }
5510 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5511 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5512 {
5513 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5514 if (uDpl == AttrSs.n.u2Dpl)
5515 { /* likely */ }
5516 else
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5518 }
5519 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5520 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5521 {
5522 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5523 if (uDpl <= AttrSs.n.u2Dpl)
5524 { /* likely */ }
5525 else
5526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5527 }
5528 else
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5530
5531 /* Def/Big. */
5532 if ( fGstInLongMode
5533 && fSegLong)
5534 {
5535 if (uDefBig == 0)
5536 { /* likely */ }
5537 else
5538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5539 }
5540 }
5541 else if (iSegReg == X86_SREG_SS)
5542 {
5543 /* Segment Type. */
5544 if ( !fUsable
5545 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5546 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5547 { /* likely */ }
5548 else
5549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5550
5551 /* DPL. */
5552 if (!fUnrestrictedGuest)
5553 {
5554 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5555 { /* likely */ }
5556 else
5557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5558 }
5559 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5560 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5561 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5562 {
5563 if (uDpl == 0)
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5567 }
5568 }
5569 else
5570 {
5571 /* DS, ES, FS, GS. */
5572 if (fUsable)
5573 {
5574 /* Segment type. */
5575 if (uSegType & X86_SEL_TYPE_ACCESSED)
5576 { /* likely */ }
5577 else
5578 {
5579 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5581 }
5582
5583 if ( !(uSegType & X86_SEL_TYPE_CODE)
5584 || (uSegType & X86_SEL_TYPE_READ))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5588
5589 /* DPL. */
5590 if ( !fUnrestrictedGuest
5591 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5592 {
5593 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5594 { /* likely */ }
5595 else
5596 {
5597 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5599 }
5600 }
5601 }
5602 }
5603 }
5604
5605 /*
5606 * LDTR.
5607 */
5608 {
5609 CPUMSELREG Ldtr;
5610 Ldtr.Sel = pVmcs->GuestLdtr;
5611 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5612 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5613 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5614
5615 if (!Ldtr.Attr.n.u1Unusable)
5616 {
5617 /* Selector. */
5618 if (!(Ldtr.Sel & X86_SEL_LDT))
5619 { /* likely */ }
5620 else
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5622
5623 /* Base. */
5624 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5625 {
5626 if (X86_IS_CANONICAL(Ldtr.u64Base))
5627 { /* likely */ }
5628 else
5629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5630 }
5631
5632 /* Attributes. */
5633 /* Reserved bits (bits 31:17 and bits 11:8). */
5634 if (!(Ldtr.Attr.u & 0xfffe0f00))
5635 { /* likely */ }
5636 else
5637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5638
5639 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5640 { /* likely */ }
5641 else
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5643
5644 if (!Ldtr.Attr.n.u1DescType)
5645 { /* likely */ }
5646 else
5647 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5648
5649 if (Ldtr.Attr.n.u1Present)
5650 { /* likely */ }
5651 else
5652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5653
5654 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5655 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5656 { /* likely */ }
5657 else
5658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5659 }
5660 }
5661
5662 /*
5663 * TR.
5664 */
5665 {
5666 CPUMSELREG Tr;
5667 Tr.Sel = pVmcs->GuestTr;
5668 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5669 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5670 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5671
5672 /* Selector. */
5673 if (!(Tr.Sel & X86_SEL_LDT))
5674 { /* likely */ }
5675 else
5676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5677
5678 /* Base. */
5679 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5680 {
5681 if (X86_IS_CANONICAL(Tr.u64Base))
5682 { /* likely */ }
5683 else
5684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5685 }
5686
5687 /* Attributes. */
5688 /* Reserved bits (bits 31:17 and bits 11:8). */
5689 if (!(Tr.Attr.u & 0xfffe0f00))
5690 { /* likely */ }
5691 else
5692 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5693
5694 if (!Tr.Attr.n.u1Unusable)
5695 { /* likely */ }
5696 else
5697 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5698
5699 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5700 || ( !fGstInLongMode
5701 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5702 { /* likely */ }
5703 else
5704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5705
5706 if (!Tr.Attr.n.u1DescType)
5707 { /* likely */ }
5708 else
5709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5710
5711 if (Tr.Attr.n.u1Present)
5712 { /* likely */ }
5713 else
5714 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5715
5716 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5717 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5718 { /* likely */ }
5719 else
5720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5721 }
5722
5723 NOREF(pszInstr);
5724 NOREF(pszFailure);
5725 return VINF_SUCCESS;
5726}
5727
5728
5729/**
5730 * Checks guest GDTR and IDTR as part of VM-entry.
5731 *
5732 * @param pVCpu The cross context virtual CPU structure.
5733 * @param pszInstr The VMX instruction name (for logging purposes).
5734 */
5735IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5736{
5737 /*
5738 * GDTR and IDTR.
5739 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5740 */
5741 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5742 const char *const pszFailure = "VM-exit";
5743
5744 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5745 {
5746 /* Base. */
5747 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5748 { /* likely */ }
5749 else
5750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5751
5752 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5753 { /* likely */ }
5754 else
5755 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5756 }
5757
5758 /* Limit. */
5759 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5763
5764 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5765 { /* likely */ }
5766 else
5767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5768
5769 NOREF(pszInstr);
5770 NOREF(pszFailure);
5771 return VINF_SUCCESS;
5772}
5773
5774
5775/**
5776 * Checks guest RIP and RFLAGS as part of VM-entry.
5777 *
5778 * @param pVCpu The cross context virtual CPU structure.
5779 * @param pszInstr The VMX instruction name (for logging purposes).
5780 */
5781IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5782{
5783 /*
5784 * RIP and RFLAGS.
5785 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5786 */
5787 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5788 const char *const pszFailure = "VM-exit";
5789 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5790
5791 /* RIP. */
5792 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5793 {
5794 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5795 if ( !fGstInLongMode
5796 || !AttrCs.n.u1Long)
5797 {
5798 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5799 { /* likely */ }
5800 else
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5802 }
5803
5804 if ( fGstInLongMode
5805 && AttrCs.n.u1Long)
5806 {
5807 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5808 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5809 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5810 { /* likely */ }
5811 else
5812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5813 }
5814 }
5815
5816 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5817 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5818 : pVmcs->u64GuestRFlags.s.Lo;
5819 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5820 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5821 { /* likely */ }
5822 else
5823 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5824
5825 if ( fGstInLongMode
5826 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5827 {
5828 if (!(uGuestRFlags & X86_EFL_VM))
5829 { /* likely */ }
5830 else
5831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5832 }
5833
5834 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5835 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5836 {
5837 if (uGuestRFlags & X86_EFL_IF)
5838 { /* likely */ }
5839 else
5840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5841 }
5842
5843 NOREF(pszInstr);
5844 NOREF(pszFailure);
5845 return VINF_SUCCESS;
5846}
5847
5848
5849/**
5850 * Checks guest non-register state as part of VM-entry.
5851 *
5852 * @param pVCpu The cross context virtual CPU structure.
5853 * @param pszInstr The VMX instruction name (for logging purposes).
5854 */
5855IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5856{
5857 /*
5858 * Guest non-register state.
5859 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5860 */
5861 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5862 const char *const pszFailure = "VM-exit";
5863
5864 /*
5865 * Activity state.
5866 */
5867 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5868 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5869 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5873
5874 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5875 if ( !AttrSs.n.u2Dpl
5876 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5877 { /* likely */ }
5878 else
5879 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5880
5881 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5882 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5883 {
5884 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5885 { /* likely */ }
5886 else
5887 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5888 }
5889
5890 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5891 {
5892 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5893 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5894 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5895 switch (pVmcs->u32GuestActivityState)
5896 {
5897 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5898 {
5899 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5900 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5901 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5902 && ( uVector == X86_XCPT_DB
5903 || uVector == X86_XCPT_MC))
5904 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5905 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5909 break;
5910 }
5911
5912 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5913 {
5914 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5915 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5916 && uVector == X86_XCPT_MC))
5917 { /* likely */ }
5918 else
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5920 break;
5921 }
5922
5923 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5924 default:
5925 break;
5926 }
5927 }
5928
5929 /*
5930 * Interruptibility state.
5931 */
5932 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5933 { /* likely */ }
5934 else
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5936
5937 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5938 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5942
5943 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5944 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5945 { /* likely */ }
5946 else
5947 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5948
5949 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5950 {
5951 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5952 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5953 {
5954 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5955 { /* likely */ }
5956 else
5957 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5958 }
5959 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5960 {
5961 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5962 { /* likely */ }
5963 else
5964 {
5965 /*
5966 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5967 * We update the VM-exit qualification only when blocking-by-STI is set
5968 * without blocking-by-MovSS being set. Although in practise it does not
5969 * make much difference since the order of checks are implementation defined.
5970 */
5971 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5972 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5974 }
5975
5976 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5977 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5978 { /* likely */ }
5979 else
5980 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5981 }
5982 }
5983
5984 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5985 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5986 { /* likely */ }
5987 else
5988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5989
5990 /* We don't support SGX yet. So enclave-interruption must not be set. */
5991 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5992 { /* likely */ }
5993 else
5994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5995
5996 /*
5997 * Pending debug exceptions.
5998 */
5999 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
6000 ? pVmcs->u64GuestPendingDbgXcpt.u
6001 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
6002 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
6003 { /* likely */ }
6004 else
6005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
6006
6007 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
6008 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
6009 {
6010 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
6011 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
6012 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
6013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
6014
6015 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
6016 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
6017 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
6018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
6019 }
6020
6021 /* We don't support RTM (Real-time Transactional Memory) yet. */
6022 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
6023 { /* likely */ }
6024 else
6025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
6026
6027 /*
6028 * VMCS link pointer.
6029 */
6030 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6031 {
6032 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6033 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
6034 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
6035 { /* likely */ }
6036 else
6037 {
6038 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
6040 }
6041
6042 /* Validate the address. */
6043 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
6044 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6045 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
6046 { /* likely */ }
6047 else
6048 {
6049 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6050 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6051 }
6052
6053 /* Read the VMCS-link pointer from guest memory. */
6054 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6055 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6056 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
6057 if (RT_SUCCESS(rc))
6058 { /* likely */ }
6059 else
6060 {
6061 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6063 }
6064
6065 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6066 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6067 { /* likely */ }
6068 else
6069 {
6070 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6072 }
6073
6074 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6075 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6076 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6077 { /* likely */ }
6078 else
6079 {
6080 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6082 }
6083
6084 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6085 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6086 }
6087
6088 NOREF(pszInstr);
6089 NOREF(pszFailure);
6090 return VINF_SUCCESS;
6091}
6092
6093
6094/**
6095 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6096 * VM-entry.
6097 *
6098 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6099 * @param pVCpu The cross context virtual CPU structure.
6100 * @param pszInstr The VMX instruction name (for logging purposes).
6101 * @param pVmcs Pointer to the virtual VMCS.
6102 */
6103IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6104{
6105 /*
6106 * Check PDPTEs.
6107 * See Intel spec. 4.4.1 "PDPTE Registers".
6108 */
6109 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6110 const char *const pszFailure = "VM-exit";
6111
6112 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6113 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6114 if (RT_SUCCESS(rc))
6115 {
6116 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6117 {
6118 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6119 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6120 { /* likely */ }
6121 else
6122 {
6123 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6124 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6126 }
6127 }
6128 }
6129 else
6130 {
6131 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6133 }
6134
6135 NOREF(pszFailure);
6136 NOREF(pszInstr);
6137 return rc;
6138}
6139
6140
6141/**
6142 * Checks guest PDPTEs as part of VM-entry.
6143 *
6144 * @param pVCpu The cross context virtual CPU structure.
6145 * @param pszInstr The VMX instruction name (for logging purposes).
6146 */
6147IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6148{
6149 /*
6150 * Guest PDPTEs.
6151 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6152 */
6153 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6154 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6155
6156 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6157 int rc;
6158 if ( !fGstInLongMode
6159 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6160 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6161 {
6162 /*
6163 * We don't support nested-paging for nested-guests yet.
6164 *
6165 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6166 * rather we need to check the PDPTEs referenced by the guest CR3.
6167 */
6168 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6169 }
6170 else
6171 rc = VINF_SUCCESS;
6172 return rc;
6173}
6174
6175
6176/**
6177 * Checks guest-state as part of VM-entry.
6178 *
6179 * @returns VBox status code.
6180 * @param pVCpu The cross context virtual CPU structure.
6181 * @param pszInstr The VMX instruction name (for logging purposes).
6182 */
6183IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6184{
6185 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6186 if (RT_SUCCESS(rc))
6187 {
6188 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6189 if (RT_SUCCESS(rc))
6190 {
6191 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6192 if (RT_SUCCESS(rc))
6193 {
6194 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6195 if (RT_SUCCESS(rc))
6196 {
6197 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6198 if (RT_SUCCESS(rc))
6199 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6200 }
6201 }
6202 }
6203 }
6204 return rc;
6205}
6206
6207
6208/**
6209 * Checks host-state as part of VM-entry.
6210 *
6211 * @returns VBox status code.
6212 * @param pVCpu The cross context virtual CPU structure.
6213 * @param pszInstr The VMX instruction name (for logging purposes).
6214 */
6215IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6216{
6217 /*
6218 * Host Control Registers and MSRs.
6219 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6220 */
6221 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6222 const char * const pszFailure = "VMFail";
6223
6224 /* CR0 reserved bits. */
6225 {
6226 /* CR0 MB1 bits. */
6227 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6228 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6232
6233 /* CR0 MBZ bits. */
6234 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6235 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6236 { /* likely */ }
6237 else
6238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6239 }
6240
6241 /* CR4 reserved bits. */
6242 {
6243 /* CR4 MB1 bits. */
6244 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6245 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6246 { /* likely */ }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6249
6250 /* CR4 MBZ bits. */
6251 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6252 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6256 }
6257
6258 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6259 {
6260 /* CR3 reserved bits. */
6261 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6262 { /* likely */ }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6265
6266 /* SYSENTER ESP and SYSENTER EIP. */
6267 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6268 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6269 { /* likely */ }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6272 }
6273
6274 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6275 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6276
6277 /* PAT MSR. */
6278 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6279 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6280 { /* likely */ }
6281 else
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6283
6284 /* EFER MSR. */
6285 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6286 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6287 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6288 { /* likely */ }
6289 else
6290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6291
6292 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6293 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6294 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6295 if ( fHostInLongMode == fHostLma
6296 && fHostInLongMode == fHostLme)
6297 { /* likely */ }
6298 else
6299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6300
6301 /*
6302 * Host Segment and Descriptor-Table Registers.
6303 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6304 */
6305 /* Selector RPL and TI. */
6306 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6307 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6308 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6309 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6310 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6311 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6312 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6313 { /* likely */ }
6314 else
6315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6316
6317 /* CS and TR selectors cannot be 0. */
6318 if ( pVmcs->HostCs
6319 && pVmcs->HostTr)
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6323
6324 /* SS cannot be 0 if 32-bit host. */
6325 if ( fHostInLongMode
6326 || pVmcs->HostSs)
6327 { /* likely */ }
6328 else
6329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6330
6331 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6332 {
6333 /* FS, GS, GDTR, IDTR, TR base address. */
6334 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6335 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6336 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6337 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6338 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6339 { /* likely */ }
6340 else
6341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6342 }
6343
6344 /*
6345 * Host address-space size for 64-bit CPUs.
6346 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6347 */
6348 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6349 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6350 {
6351 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6352
6353 /* Logical processor in IA-32e mode. */
6354 if (fCpuInLongMode)
6355 {
6356 if (fHostInLongMode)
6357 {
6358 /* PAE must be set. */
6359 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6360 { /* likely */ }
6361 else
6362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6363
6364 /* RIP must be canonical. */
6365 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6366 { /* likely */ }
6367 else
6368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6369 }
6370 else
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6372 }
6373 else
6374 {
6375 /* Logical processor is outside IA-32e mode. */
6376 if ( !fGstInLongMode
6377 && !fHostInLongMode)
6378 {
6379 /* PCIDE should not be set. */
6380 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6384
6385 /* The high 32-bits of RIP MBZ. */
6386 if (!pVmcs->u64HostRip.s.Hi)
6387 { /* likely */ }
6388 else
6389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6390 }
6391 else
6392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6393 }
6394 }
6395 else
6396 {
6397 /* Host address-space size for 32-bit CPUs. */
6398 if ( !fGstInLongMode
6399 && !fHostInLongMode)
6400 { /* likely */ }
6401 else
6402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6403 }
6404
6405 NOREF(pszInstr);
6406 NOREF(pszFailure);
6407 return VINF_SUCCESS;
6408}
6409
6410
6411/**
6412 * Checks VM-entry controls fields as part of VM-entry.
6413 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6414 *
6415 * @returns VBox status code.
6416 * @param pVCpu The cross context virtual CPU structure.
6417 * @param pszInstr The VMX instruction name (for logging purposes).
6418 */
6419IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6420{
6421 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6422 const char * const pszFailure = "VMFail";
6423
6424 /* VM-entry controls. */
6425 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6426 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6430
6431 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6432 { /* likely */ }
6433 else
6434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6435
6436 /* Event injection. */
6437 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6438 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6439 {
6440 /* Type and vector. */
6441 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6442 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6443 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6444 if ( !uRsvd
6445 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6446 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6447 { /* likely */ }
6448 else
6449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6450
6451 /* Exception error code. */
6452 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6453 {
6454 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6455 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6456 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6457 { /* likely */ }
6458 else
6459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6460
6461 /* Exceptions that provide an error code. */
6462 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6463 && ( uVector == X86_XCPT_DF
6464 || uVector == X86_XCPT_TS
6465 || uVector == X86_XCPT_NP
6466 || uVector == X86_XCPT_SS
6467 || uVector == X86_XCPT_GP
6468 || uVector == X86_XCPT_PF
6469 || uVector == X86_XCPT_AC))
6470 { /* likely */ }
6471 else
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6473
6474 /* Exception error-code reserved bits. */
6475 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6476 { /* likely */ }
6477 else
6478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6479
6480 /* Injecting a software interrupt, software exception or privileged software exception. */
6481 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6482 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6483 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6484 {
6485 /* Instruction length must be in the range 0-15. */
6486 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6487 { /* likely */ }
6488 else
6489 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6490
6491 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6492 if ( pVmcs->u32EntryInstrLen == 0
6493 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6495 }
6496 }
6497 }
6498
6499 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6500 if (pVmcs->u32EntryMsrLoadCount)
6501 {
6502 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6503 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6504 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6505 { /* likely */ }
6506 else
6507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6508 }
6509
6510 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6511 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6512
6513 NOREF(pszInstr);
6514 NOREF(pszFailure);
6515 return VINF_SUCCESS;
6516}
6517
6518
6519/**
6520 * Checks VM-exit controls fields as part of VM-entry.
6521 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6522 *
6523 * @returns VBox status code.
6524 * @param pVCpu The cross context virtual CPU structure.
6525 * @param pszInstr The VMX instruction name (for logging purposes).
6526 */
6527IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6528{
6529 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6530 const char * const pszFailure = "VMFail";
6531
6532 /* VM-exit controls. */
6533 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6534 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6538
6539 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6540 { /* likely */ }
6541 else
6542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6543
6544 /* Save preemption timer without activating it. */
6545 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6546 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6547 { /* likely */ }
6548 else
6549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6550
6551 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6552 if (pVmcs->u32ExitMsrStoreCount)
6553 {
6554 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6555 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6556 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6557 { /* likely */ }
6558 else
6559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6560 }
6561
6562 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6563 if (pVmcs->u32ExitMsrLoadCount)
6564 {
6565 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6566 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6567 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6568 { /* likely */ }
6569 else
6570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6571 }
6572
6573 NOREF(pszInstr);
6574 NOREF(pszFailure);
6575 return VINF_SUCCESS;
6576}
6577
6578
6579/**
6580 * Checks VM-execution controls fields as part of VM-entry.
6581 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6582 *
6583 * @returns VBox status code.
6584 * @param pVCpu The cross context virtual CPU structure.
6585 * @param pszInstr The VMX instruction name (for logging purposes).
6586 *
6587 * @remarks This may update secondary-processor based VM-execution control fields
6588 * in the current VMCS if necessary.
6589 */
6590IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6591{
6592 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6593 const char * const pszFailure = "VMFail";
6594
6595 /* Pin-based VM-execution controls. */
6596 {
6597 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6598 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6599 { /* likely */ }
6600 else
6601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6602
6603 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6604 { /* likely */ }
6605 else
6606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6607 }
6608
6609 /* Processor-based VM-execution controls. */
6610 {
6611 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6612 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6613 { /* likely */ }
6614 else
6615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6616
6617 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6618 { /* likely */ }
6619 else
6620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6621 }
6622
6623 /* Secondary processor-based VM-execution controls. */
6624 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6625 {
6626 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6627 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6628 { /* likely */ }
6629 else
6630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6631
6632 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6633 { /* likely */ }
6634 else
6635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6636 }
6637 else
6638 Assert(!pVmcs->u32ProcCtls2);
6639
6640 /* CR3-target count. */
6641 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6642 { /* likely */ }
6643 else
6644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6645
6646 /* I/O bitmaps physical addresses. */
6647 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6648 {
6649 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6650 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6651 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6652 { /* likely */ }
6653 else
6654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6655
6656 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6657 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6658 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6659 { /* likely */ }
6660 else
6661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6662 }
6663
6664 /* MSR bitmap physical address. */
6665 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6666 {
6667 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6668 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6669 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6670 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6671 { /* likely */ }
6672 else
6673 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6674
6675 /* Read the MSR bitmap. */
6676 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6677 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6678 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6679 if (RT_SUCCESS(rc))
6680 { /* likely */ }
6681 else
6682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6683 }
6684
6685 /* TPR shadow related controls. */
6686 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6687 {
6688 /* Virtual-APIC page physical address. */
6689 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6690 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6691 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6692 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6693 { /* likely */ }
6694 else
6695 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6696
6697 /* TPR threshold without virtual-interrupt delivery. */
6698 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6699 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6701
6702 /* TPR threshold and VTPR. */
6703 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6704 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6705 {
6706 /* Read the VTPR from the virtual-APIC page. */
6707 uint8_t u8VTpr;
6708 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6709 if (RT_SUCCESS(rc))
6710 { /* likely */ }
6711 else
6712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6713
6714 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6715 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6716 { /* likely */ }
6717 else
6718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6719 }
6720 }
6721 else
6722 {
6723 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6724 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6725 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6726 { /* likely */ }
6727 else
6728 {
6729 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6731 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6733 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6735 }
6736 }
6737
6738 /* NMI exiting and virtual-NMIs. */
6739 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6740 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6741 { /* likely */ }
6742 else
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6744
6745 /* Virtual-NMIs and NMI-window exiting. */
6746 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6747 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6751
6752 /* Virtualize APIC accesses. */
6753 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6754 {
6755 /* APIC-access physical address. */
6756 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6757 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6758 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6759 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6760 { /* likely */ }
6761 else
6762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6763
6764 /*
6765 * Disallow APIC-access page and virtual-APIC page from being the same address.
6766 * Note! This is not an Intel requirement, but one imposed by our implementation.
6767 */
6768 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6769 * redirecting accesses between the APIC-access page and the virtual-APIC
6770 * page. If any nested hypervisor requires this, we can implement it later. */
6771 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6772 {
6773 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6774 if (GCPhysVirtApic != GCPhysApicAccess)
6775 { /* likely */ }
6776 else
6777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6778 }
6779
6780 /*
6781 * Register the handler for the APIC-access page.
6782 *
6783 * We don't deregister the APIC-access page handler during the VM-exit as a different
6784 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6785 *
6786 * We leave the page registered until the first access that happens outside VMX non-root
6787 * mode. Guest software is allowed to access structures such as the APIC-access page
6788 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6789 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6790 *
6791 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6792 */
6793 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6794 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6795 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6796 if (RT_SUCCESS(rc))
6797 { /* likely */ }
6798 else
6799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6800 }
6801
6802 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6803 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6804 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6805 { /* likely */ }
6806 else
6807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6808
6809 /* Virtual-interrupt delivery requires external interrupt exiting. */
6810 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6811 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6812 { /* likely */ }
6813 else
6814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6815
6816 /* VPID. */
6817 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6818 || pVmcs->u16Vpid != 0)
6819 { /* likely */ }
6820 else
6821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6822
6823 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6824 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6825 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6826 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6827 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6828 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6829 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6830
6831 /* VMCS shadowing. */
6832 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6833 {
6834 /* VMREAD-bitmap physical address. */
6835 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6836 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6837 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6838 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6839 { /* likely */ }
6840 else
6841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6842
6843 /* VMWRITE-bitmap physical address. */
6844 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6845 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6846 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6847 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6848 { /* likely */ }
6849 else
6850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6851
6852 /* Read the VMREAD-bitmap. */
6853 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6854 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6855 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6856 if (RT_SUCCESS(rc))
6857 { /* likely */ }
6858 else
6859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6860
6861 /* Read the VMWRITE-bitmap. */
6862 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6863 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6864 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6865 if (RT_SUCCESS(rc))
6866 { /* likely */ }
6867 else
6868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6869 }
6870
6871 NOREF(pszInstr);
6872 NOREF(pszFailure);
6873 return VINF_SUCCESS;
6874}
6875
6876
6877/**
6878 * Loads the guest control registers, debug register and some MSRs as part of
6879 * VM-entry.
6880 *
6881 * @param pVCpu The cross context virtual CPU structure.
6882 */
6883IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6884{
6885 /*
6886 * Load guest control registers, debug registers and MSRs.
6887 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6888 */
6889 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6890
6891 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6892 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6893 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6894 CPUMSetGuestCR0(pVCpu, uGstCr0);
6895 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6896 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6897
6898 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6899 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6900
6901 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6902 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6903 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6904
6905 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6906 {
6907 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6908
6909 /* EFER MSR. */
6910 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6911 {
6912 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6913 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6914 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6915 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6916 if (fGstInLongMode)
6917 {
6918 /* If the nested-guest is in long mode, LMA and LME are both set. */
6919 Assert(fGstPaging);
6920 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6921 }
6922 else
6923 {
6924 /*
6925 * If the nested-guest is outside long mode:
6926 * - With paging: LMA is cleared, LME is cleared.
6927 * - Without paging: LMA is cleared, LME is left unmodified.
6928 */
6929 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6930 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6931 }
6932 }
6933 /* else: see below. */
6934 }
6935
6936 /* PAT MSR. */
6937 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6938 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6939
6940 /* EFER MSR. */
6941 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6942 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6943
6944 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6945 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6946
6947 /* We don't support IA32_BNDCFGS MSR yet. */
6948 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6949
6950 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6951}
6952
6953
6954/**
6955 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6956 *
6957 * @param pVCpu The cross context virtual CPU structure.
6958 */
6959IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6960{
6961 /*
6962 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6963 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6964 */
6965 /* CS, SS, ES, DS, FS, GS. */
6966 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6967 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6968 {
6969 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6970 CPUMSELREG VmcsSelReg;
6971 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6972 AssertRC(rc); NOREF(rc);
6973 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6974 {
6975 pGstSelReg->Sel = VmcsSelReg.Sel;
6976 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6977 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6978 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6979 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6980 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6981 }
6982 else
6983 {
6984 pGstSelReg->Sel = VmcsSelReg.Sel;
6985 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6986 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6987 switch (iSegReg)
6988 {
6989 case X86_SREG_CS:
6990 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6991 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6992 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6993 break;
6994
6995 case X86_SREG_SS:
6996 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6997 pGstSelReg->u32Limit = 0;
6998 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6999 break;
7000
7001 case X86_SREG_ES:
7002 case X86_SREG_DS:
7003 pGstSelReg->u64Base = 0;
7004 pGstSelReg->u32Limit = 0;
7005 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
7006 break;
7007
7008 case X86_SREG_FS:
7009 case X86_SREG_GS:
7010 pGstSelReg->u64Base = VmcsSelReg.u64Base;
7011 pGstSelReg->u32Limit = 0;
7012 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
7013 break;
7014 }
7015 Assert(pGstSelReg->Attr.n.u1Unusable);
7016 }
7017 }
7018
7019 /* LDTR. */
7020 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
7021 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
7022 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
7023 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
7024 {
7025 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
7026 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
7027 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
7028 }
7029 else
7030 {
7031 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
7032 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
7033 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
7034 }
7035
7036 /* TR. */
7037 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
7038 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
7039 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
7040 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
7041 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
7042 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
7043 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
7044
7045 /* GDTR. */
7046 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
7047 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
7048
7049 /* IDTR. */
7050 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
7051 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
7052}
7053
7054
7055/**
7056 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
7057 *
7058 * @returns VBox status code.
7059 * @param pVCpu The cross context virtual CPU structure.
7060 * @param pszInstr The VMX instruction name (for logging purposes).
7061 */
7062IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
7063{
7064 /*
7065 * Load guest MSRs.
7066 * See Intel spec. 26.4 "Loading MSRs".
7067 */
7068 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7069 const char *const pszFailure = "VM-exit";
7070
7071 /*
7072 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7073 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7074 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7075 */
7076 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7077 if (!cMsrs)
7078 return VINF_SUCCESS;
7079
7080 /*
7081 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7082 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7083 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7084 */
7085 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7086 if (fIsMsrCountValid)
7087 { /* likely */ }
7088 else
7089 {
7090 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7092 }
7093
7094 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7095 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7096 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7097 if (RT_SUCCESS(rc))
7098 {
7099 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7100 Assert(pMsr);
7101 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7102 {
7103 if ( !pMsr->u32Reserved
7104 && pMsr->u32Msr != MSR_K8_FS_BASE
7105 && pMsr->u32Msr != MSR_K8_GS_BASE
7106 && pMsr->u32Msr != MSR_K6_EFER
7107 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7108 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7109 {
7110 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7111 if (rcStrict == VINF_SUCCESS)
7112 continue;
7113
7114 /*
7115 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7116 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7117 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7118 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7119 * MSR in ring-0 if possible, or come up with a better, generic solution.
7120 */
7121 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7122 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7123 ? kVmxVDiag_Vmentry_MsrLoadRing3
7124 : kVmxVDiag_Vmentry_MsrLoad;
7125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7126 }
7127 else
7128 {
7129 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7131 }
7132 }
7133 }
7134 else
7135 {
7136 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7137 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7138 }
7139
7140 NOREF(pszInstr);
7141 NOREF(pszFailure);
7142 return VINF_SUCCESS;
7143}
7144
7145
7146/**
7147 * Loads the guest-state non-register state as part of VM-entry.
7148 *
7149 * @returns VBox status code.
7150 * @param pVCpu The cross context virtual CPU structure.
7151 *
7152 * @remarks This must be called only after loading the nested-guest register state
7153 * (especially nested-guest RIP).
7154 */
7155IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7156{
7157 /*
7158 * Load guest non-register state.
7159 * See Intel spec. 26.6 "Special Features of VM Entry"
7160 */
7161 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7162
7163 /*
7164 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7165 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7166 *
7167 * See Intel spec. 26.6.1 "Interruptibility State".
7168 */
7169 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7170 if ( !fEntryVectoring
7171 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7172 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7173 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7174 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7175
7176 /* NMI blocking. */
7177 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7178 {
7179 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7180 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7181 else
7182 {
7183 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7184 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7185 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7186 }
7187 }
7188 else
7189 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7190
7191 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7192
7193 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7194 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7195
7196 /* VPID is irrelevant. We don't support VPID yet. */
7197
7198 /* Clear address-range monitoring. */
7199 EMMonitorWaitClear(pVCpu);
7200}
7201
7202
7203/**
7204 * Loads the guest-state as part of VM-entry.
7205 *
7206 * @returns VBox status code.
7207 * @param pVCpu The cross context virtual CPU structure.
7208 * @param pszInstr The VMX instruction name (for logging purposes).
7209 *
7210 * @remarks This must be done after all the necessary steps prior to loading of
7211 * guest-state (e.g. checking various VMCS state).
7212 */
7213IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7214{
7215 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7216 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7217
7218 /*
7219 * Load guest RIP, RSP and RFLAGS.
7220 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7221 */
7222 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7223 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7224 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7225 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7226
7227 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7228 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7229 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7230
7231 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7232
7233 NOREF(pszInstr);
7234 return VINF_SUCCESS;
7235}
7236
7237
7238/**
7239 * Returns whether there are is a pending debug exception on VM-entry.
7240 *
7241 * @param pVCpu The cross context virtual CPU structure.
7242 * @param pszInstr The VMX instruction name (for logging purposes).
7243 */
7244IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7245{
7246 /*
7247 * Pending debug exceptions.
7248 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7249 */
7250 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7251 Assert(pVmcs);
7252
7253 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7254 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7255 if (fPendingDbgXcpt)
7256 {
7257 uint8_t uEntryIntInfoType;
7258 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7259 if (fEntryVectoring)
7260 {
7261 switch (uEntryIntInfoType)
7262 {
7263 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7264 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7265 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7266 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7267 fPendingDbgXcpt = false;
7268 break;
7269
7270 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7271 {
7272 /*
7273 * Whether the pending debug exception for software exceptions other than
7274 * #BP and #OF is delivered after injecting the exception or is discard
7275 * is CPU implementation specific. We will discard them (easier).
7276 */
7277 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7278 if ( uVector != X86_XCPT_BP
7279 && uVector != X86_XCPT_OF)
7280 fPendingDbgXcpt = false;
7281 RT_FALL_THRU();
7282 }
7283 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7284 {
7285 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7286 fPendingDbgXcpt = false;
7287 break;
7288 }
7289 }
7290 }
7291 else
7292 {
7293 /*
7294 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7295 * pending debug exception is held pending or is discarded is CPU implementation
7296 * specific. We will discard them (easier).
7297 */
7298 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7299 fPendingDbgXcpt = false;
7300
7301 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7302 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7303 fPendingDbgXcpt = false;
7304 }
7305 }
7306
7307 NOREF(pszInstr);
7308 return fPendingDbgXcpt;
7309}
7310
7311
7312/**
7313 * Set up the monitor-trap flag (MTF).
7314 *
7315 * @param pVCpu The cross context virtual CPU structure.
7316 * @param pszInstr The VMX instruction name (for logging purposes).
7317 */
7318IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7319{
7320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7321 Assert(pVmcs);
7322 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7323 {
7324 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7325 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7326 }
7327 else
7328 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7329 NOREF(pszInstr);
7330}
7331
7332
7333/**
7334 * Set up the VMX-preemption timer.
7335 *
7336 * @param pVCpu The cross context virtual CPU structure.
7337 * @param pszInstr The VMX instruction name (for logging purposes).
7338 */
7339IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7340{
7341 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7342 Assert(pVmcs);
7343 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7344 {
7345 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7346 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7347 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7348
7349 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7350 }
7351 else
7352 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7353
7354 NOREF(pszInstr);
7355}
7356
7357
7358/**
7359 * Injects an event using TRPM given a VM-entry interruption info. and related
7360 * fields.
7361 *
7362 * @returns VBox status code.
7363 * @param pVCpu The cross context virtual CPU structure.
7364 * @param uEntryIntInfo The VM-entry interruption info.
7365 * @param uErrCode The error code associated with the event if any.
7366 * @param cbInstr The VM-entry instruction length (for software
7367 * interrupts and software exceptions). Pass 0
7368 * otherwise.
7369 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7370 */
7371IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7372 RTGCUINTPTR GCPtrFaultAddress)
7373{
7374 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7375
7376 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7377 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7378 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7379
7380 TRPMEVENT enmTrapType;
7381 switch (uType)
7382 {
7383 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7384 enmTrapType = TRPM_HARDWARE_INT;
7385 break;
7386
7387 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7388 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7389 enmTrapType = TRPM_TRAP;
7390 break;
7391
7392 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7393 enmTrapType = TRPM_SOFTWARE_INT;
7394 break;
7395
7396 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7397 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7398 enmTrapType = TRPM_SOFTWARE_INT;
7399 break;
7400
7401 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7402 Assert(uVector == X86_XCPT_DB);
7403 enmTrapType = TRPM_SOFTWARE_INT;
7404 break;
7405
7406 default:
7407 /* Shouldn't really happen. */
7408 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7409 break;
7410 }
7411
7412 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7413 AssertRCReturn(rc, rc);
7414
7415 if (fErrCodeValid)
7416 TRPMSetErrorCode(pVCpu, uErrCode);
7417
7418 if ( enmTrapType == TRPM_TRAP
7419 && uVector == X86_XCPT_PF)
7420 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7421 else if (enmTrapType == TRPM_SOFTWARE_INT)
7422 TRPMSetInstrLength(pVCpu, cbInstr);
7423
7424 return VINF_SUCCESS;
7425}
7426
7427
7428/**
7429 * Performs event injection (if any) as part of VM-entry.
7430 *
7431 * @param pVCpu The cross context virtual CPU structure.
7432 * @param pszInstr The VMX instruction name (for logging purposes).
7433 */
7434IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7435{
7436 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7437
7438 /*
7439 * Inject events.
7440 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7441 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7442 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7443 * the actually delivery of this event.
7444 *
7445 * See Intel spec. 26.5 "Event Injection".
7446 */
7447 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7448 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7449
7450 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7451 if (fEntryIntInfoValid)
7452 {
7453 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7454 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7455 {
7456 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7457 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7458 return VINF_SUCCESS;
7459 }
7460
7461 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7462 pVCpu->cpum.GstCtx.cr2);
7463 if (RT_SUCCESS(rc))
7464 {
7465 /*
7466 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7467 *
7468 * However, we do it here on VM-entry because while it continues to not be visible to
7469 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7470 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7471 * information field.
7472 *
7473 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7474 */
7475 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7476 }
7477 return rc;
7478 }
7479
7480 /*
7481 * Inject any pending guest debug exception.
7482 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7483 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7484 */
7485 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7486 if (fPendingDbgXcpt)
7487 {
7488 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7489 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7490 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7491 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7492 0 /* GCPtrFaultAddress */);
7493 }
7494
7495 NOREF(pszInstr);
7496 return VINF_SUCCESS;
7497}
7498
7499
7500/**
7501 * Initializes all read-only VMCS fields as part of VM-entry.
7502 *
7503 * @param pVCpu The cross context virtual CPU structure.
7504 */
7505IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7506{
7507 /*
7508 * Any VMCS field which we do not establish on every VM-exit but may potentially
7509 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7510 * specified to be undefined needs to be initialized here.
7511 *
7512 * Thus, it is especially important to clear the VM-exit qualification field
7513 * since it must be zero for VM-exits where it is not used. Similarly, the
7514 * VM-exit interruption information field's valid bit needs to be cleared for
7515 * the same reasons.
7516 */
7517 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7518 Assert(pVmcs);
7519
7520 /* 16-bit (none currently). */
7521 /* 32-bit. */
7522 pVmcs->u32RoVmInstrError = 0;
7523 pVmcs->u32RoExitReason = 0;
7524 pVmcs->u32RoExitIntInfo = 0;
7525 pVmcs->u32RoExitIntErrCode = 0;
7526 pVmcs->u32RoIdtVectoringInfo = 0;
7527 pVmcs->u32RoIdtVectoringErrCode = 0;
7528 pVmcs->u32RoExitInstrLen = 0;
7529 pVmcs->u32RoExitInstrInfo = 0;
7530
7531 /* 64-bit. */
7532 pVmcs->u64RoGuestPhysAddr.u = 0;
7533
7534 /* Natural-width. */
7535 pVmcs->u64RoExitQual.u = 0;
7536 pVmcs->u64RoIoRcx.u = 0;
7537 pVmcs->u64RoIoRsi.u = 0;
7538 pVmcs->u64RoIoRdi.u = 0;
7539 pVmcs->u64RoIoRip.u = 0;
7540 pVmcs->u64RoGuestLinearAddr.u = 0;
7541}
7542
7543
7544/**
7545 * VMLAUNCH/VMRESUME instruction execution worker.
7546 *
7547 * @returns Strict VBox status code.
7548 * @param pVCpu The cross context virtual CPU structure.
7549 * @param cbInstr The instruction length in bytes.
7550 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7551 * VMXINSTRID_VMRESUME).
7552 *
7553 * @remarks Common VMX instruction checks are already expected to by the caller,
7554 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7555 */
7556IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7557{
7558# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7559 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7560 return VINF_EM_RAW_EMULATE_INSTR;
7561# else
7562 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7563 || uInstrId == VMXINSTRID_VMRESUME);
7564 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7565
7566 /* Nested-guest intercept. */
7567 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7568 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7569
7570 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7571
7572 /*
7573 * Basic VM-entry checks.
7574 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7575 * The checks following that do not have to follow a specific order.
7576 *
7577 * See Intel spec. 26.1 "Basic VM-entry Checks".
7578 */
7579
7580 /* CPL. */
7581 if (pVCpu->iem.s.uCpl == 0)
7582 { /* likely */ }
7583 else
7584 {
7585 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7587 return iemRaiseGeneralProtectionFault0(pVCpu);
7588 }
7589
7590 /* Current VMCS valid. */
7591 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7592 { /* likely */ }
7593 else
7594 {
7595 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7596 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7597 iemVmxVmFailInvalid(pVCpu);
7598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7599 return VINF_SUCCESS;
7600 }
7601
7602 /* Current VMCS is not a shadow VMCS. */
7603 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7604 { /* likely */ }
7605 else
7606 {
7607 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7608 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7609 iemVmxVmFailInvalid(pVCpu);
7610 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7611 return VINF_SUCCESS;
7612 }
7613
7614 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7615 * use block-by-STI here which is not quite correct. */
7616 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7617 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7618 { /* likely */ }
7619 else
7620 {
7621 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7622 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7623 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7624 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7625 return VINF_SUCCESS;
7626 }
7627
7628 if (uInstrId == VMXINSTRID_VMLAUNCH)
7629 {
7630 /* VMLAUNCH with non-clear VMCS. */
7631 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7632 { /* likely */ }
7633 else
7634 {
7635 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7636 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7637 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7638 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7639 return VINF_SUCCESS;
7640 }
7641 }
7642 else
7643 {
7644 /* VMRESUME with non-launched VMCS. */
7645 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7646 { /* likely */ }
7647 else
7648 {
7649 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7650 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7651 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7652 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7653 return VINF_SUCCESS;
7654 }
7655 }
7656
7657 /*
7658 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7659 * while entering VMX non-root mode. We do some of this while checking VM-execution
7660 * controls. The guest hypervisor should not make assumptions and cannot expect
7661 * predictable behavior if changes to these structures are made in guest memory while
7662 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7663 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7664 *
7665 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7666 */
7667 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7668 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7669 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7670 if (RT_SUCCESS(rc))
7671 {
7672 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7673 if (RT_SUCCESS(rc))
7674 {
7675 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7676 if (RT_SUCCESS(rc))
7677 {
7678 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7679 if (RT_SUCCESS(rc))
7680 {
7681 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7682 iemVmxVmentryInitReadOnlyFields(pVCpu);
7683
7684 /*
7685 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7686 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7687 * VM-exit when required.
7688 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7689 */
7690 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7691
7692 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7693 if (RT_SUCCESS(rc))
7694 {
7695 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7696 if (RT_SUCCESS(rc))
7697 {
7698 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7699 if (RT_SUCCESS(rc))
7700 {
7701 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7702
7703 /* VMLAUNCH instruction must update the VMCS launch state. */
7704 if (uInstrId == VMXINSTRID_VMLAUNCH)
7705 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7706
7707 /* Perform the VMX transition (PGM updates). */
7708 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7709 if (rcStrict == VINF_SUCCESS)
7710 { /* likely */ }
7711 else if (RT_SUCCESS(rcStrict))
7712 {
7713 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7714 VBOXSTRICTRC_VAL(rcStrict)));
7715 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7716 }
7717 else
7718 {
7719 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7720 return rcStrict;
7721 }
7722
7723 /* We've now entered nested-guest execution. */
7724 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7725
7726 /*
7727 * The priority of potential VM-exits during VM-entry is important.
7728 * The priorities of VM-exits and events are listed from highest
7729 * to lowest as follows:
7730 *
7731 * 1. Event injection.
7732 * 2. Trap on task-switch (T flag set in TSS).
7733 * 3. TPR below threshold / APIC-write.
7734 * 4. SMI, INIT.
7735 * 5. MTF exit.
7736 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7737 * 7. VMX-preemption timer.
7738 * 9. NMI-window exit.
7739 * 10. NMI injection.
7740 * 11. Interrupt-window exit.
7741 * 12. Virtual-interrupt injection.
7742 * 13. Interrupt injection.
7743 * 14. Process next instruction (fetch, decode, execute).
7744 */
7745
7746 /* Setup the VMX-preemption timer. */
7747 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7748
7749 /* Setup monitor-trap flag. */
7750 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7751
7752 /* Now that we've switched page tables, we can go ahead and inject any event. */
7753 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7754 if (RT_SUCCESS(rcStrict))
7755 {
7756 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7757# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7758 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7759 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7760 if (rcSched != VINF_SUCCESS)
7761 iemSetPassUpStatus(pVCpu, rcSched);
7762# endif
7763 return VINF_SUCCESS;
7764 }
7765
7766 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7767 return rcStrict;
7768 }
7769 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7770 }
7771 }
7772 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7773 }
7774
7775 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7776 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7777 return VINF_SUCCESS;
7778 }
7779 }
7780 }
7781
7782 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7783 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7784 return VINF_SUCCESS;
7785# endif
7786}
7787
7788
7789/**
7790 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7791 * (causes a VM-exit) or not.
7792 *
7793 * @returns @c true if the instruction is intercepted, @c false otherwise.
7794 * @param pVCpu The cross context virtual CPU structure.
7795 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7796 * VMX_EXIT_WRMSR).
7797 * @param idMsr The MSR.
7798 */
7799IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7800{
7801 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7802 Assert( uExitReason == VMX_EXIT_RDMSR
7803 || uExitReason == VMX_EXIT_WRMSR);
7804
7805 /* Consult the MSR bitmap if the feature is supported. */
7806 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7807 Assert(pVmcs);
7808 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7809 {
7810 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7811 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7812 if (uExitReason == VMX_EXIT_RDMSR)
7813 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7814 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7815 }
7816
7817 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7818 return true;
7819}
7820
7821
7822/**
7823 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7824 * intercepted (causes a VM-exit) or not.
7825 *
7826 * @returns @c true if the instruction is intercepted, @c false otherwise.
7827 * @param pVCpu The cross context virtual CPU structure.
7828 * @param u64FieldEnc The VMCS field encoding.
7829 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7830 * VMX_EXIT_VMREAD).
7831 */
7832IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7833{
7834 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7835 Assert( uExitReason == VMX_EXIT_VMREAD
7836 || uExitReason == VMX_EXIT_VMWRITE);
7837
7838 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7839 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7840 return true;
7841
7842 /*
7843 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7844 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7845 */
7846 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7847 return true;
7848
7849 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7850 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7851 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7852 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7853 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7854 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7855 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7856 pbBitmap += (u32FieldEnc >> 3);
7857 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7858 return true;
7859
7860 return false;
7861}
7862
7863
7864/**
7865 * VMREAD common (memory/register) instruction execution worker
7866 *
7867 * @returns Strict VBox status code.
7868 * @param pVCpu The cross context virtual CPU structure.
7869 * @param cbInstr The instruction length in bytes.
7870 * @param pu64Dst Where to write the VMCS value (only updated when
7871 * VINF_SUCCESS is returned).
7872 * @param u64FieldEnc The VMCS field encoding.
7873 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7874 * NULL.
7875 */
7876IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7877 PCVMXVEXITINFO pExitInfo)
7878{
7879 /* Nested-guest intercept. */
7880 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7881 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7882 {
7883 if (pExitInfo)
7884 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7885 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7886 }
7887
7888 /* CPL. */
7889 if (pVCpu->iem.s.uCpl == 0)
7890 { /* likely */ }
7891 else
7892 {
7893 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7894 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7895 return iemRaiseGeneralProtectionFault0(pVCpu);
7896 }
7897
7898 /* VMCS pointer in root mode. */
7899 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7900 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7901 { /* likely */ }
7902 else
7903 {
7904 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7905 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7906 iemVmxVmFailInvalid(pVCpu);
7907 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7908 return VINF_SUCCESS;
7909 }
7910
7911 /* VMCS-link pointer in non-root mode. */
7912 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7913 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7914 { /* likely */ }
7915 else
7916 {
7917 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7918 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7919 iemVmxVmFailInvalid(pVCpu);
7920 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7921 return VINF_SUCCESS;
7922 }
7923
7924 /* Supported VMCS field. */
7925 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7926 { /* likely */ }
7927 else
7928 {
7929 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7930 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7931 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7932 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7933 return VINF_SUCCESS;
7934 }
7935
7936 /*
7937 * Setup reading from the current or shadow VMCS.
7938 */
7939 uint8_t *pbVmcs;
7940 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7941 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7942 else
7943 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7944 Assert(pbVmcs);
7945
7946 VMXVMCSFIELDENC FieldEnc;
7947 FieldEnc.u = u64FieldEnc;
7948 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7949 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7950 uint8_t const uWidthType = (uWidth << 2) | uType;
7951 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7952 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7953 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7954 Assert(offField < VMX_V_VMCS_SIZE);
7955
7956 /*
7957 * Read the VMCS component based on the field's effective width.
7958 *
7959 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7960 * indicates high bits (little endian).
7961 *
7962 * Note! The caller is responsible to trim the result and update registers
7963 * or memory locations are required. Here we just zero-extend to the largest
7964 * type (i.e. 64-bits).
7965 */
7966 uint8_t *pbField = pbVmcs + offField;
7967 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7968 switch (uEffWidth)
7969 {
7970 case VMX_VMCS_ENC_WIDTH_64BIT:
7971 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7972 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7973 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7974 }
7975 return VINF_SUCCESS;
7976}
7977
7978
7979/**
7980 * VMREAD (64-bit register) instruction execution worker.
7981 *
7982 * @returns Strict VBox status code.
7983 * @param pVCpu The cross context virtual CPU structure.
7984 * @param cbInstr The instruction length in bytes.
7985 * @param pu64Dst Where to store the VMCS field's value.
7986 * @param u64FieldEnc The VMCS field encoding.
7987 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7988 * NULL.
7989 */
7990IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7991 PCVMXVEXITINFO pExitInfo)
7992{
7993 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7994 if (rcStrict == VINF_SUCCESS)
7995 {
7996 iemVmxVmreadSuccess(pVCpu, cbInstr);
7997 return VINF_SUCCESS;
7998 }
7999
8000 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8001 return rcStrict;
8002}
8003
8004
8005/**
8006 * VMREAD (32-bit register) instruction execution worker.
8007 *
8008 * @returns Strict VBox status code.
8009 * @param pVCpu The cross context virtual CPU structure.
8010 * @param cbInstr The instruction length in bytes.
8011 * @param pu32Dst Where to store the VMCS field's value.
8012 * @param u32FieldEnc The VMCS field encoding.
8013 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8014 * NULL.
8015 */
8016IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
8017 PCVMXVEXITINFO pExitInfo)
8018{
8019 uint64_t u64Dst;
8020 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
8021 if (rcStrict == VINF_SUCCESS)
8022 {
8023 *pu32Dst = u64Dst;
8024 iemVmxVmreadSuccess(pVCpu, cbInstr);
8025 return VINF_SUCCESS;
8026 }
8027
8028 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8029 return rcStrict;
8030}
8031
8032
8033/**
8034 * VMREAD (memory) instruction execution worker.
8035 *
8036 * @returns Strict VBox status code.
8037 * @param pVCpu The cross context virtual CPU structure.
8038 * @param cbInstr The instruction length in bytes.
8039 * @param iEffSeg The effective segment register to use with @a u64Val.
8040 * Pass UINT8_MAX if it is a register access.
8041 * @param GCPtrDst The guest linear address to store the VMCS field's
8042 * value.
8043 * @param u64FieldEnc The VMCS field encoding.
8044 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8045 * NULL.
8046 */
8047IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
8048 PCVMXVEXITINFO pExitInfo)
8049{
8050 uint64_t u64Dst;
8051 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
8052 if (rcStrict == VINF_SUCCESS)
8053 {
8054 /*
8055 * Write the VMCS field's value to the location specified in guest-memory.
8056 */
8057 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8058 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8059 else
8060 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8061 if (rcStrict == VINF_SUCCESS)
8062 {
8063 iemVmxVmreadSuccess(pVCpu, cbInstr);
8064 return VINF_SUCCESS;
8065 }
8066
8067 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8068 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8069 return rcStrict;
8070 }
8071
8072 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8073 return rcStrict;
8074}
8075
8076
8077/**
8078 * VMWRITE instruction execution worker.
8079 *
8080 * @returns Strict VBox status code.
8081 * @param pVCpu The cross context virtual CPU structure.
8082 * @param cbInstr The instruction length in bytes.
8083 * @param iEffSeg The effective segment register to use with @a u64Val.
8084 * Pass UINT8_MAX if it is a register access.
8085 * @param u64Val The value to write (or guest linear address to the
8086 * value), @a iEffSeg will indicate if it's a memory
8087 * operand.
8088 * @param u64FieldEnc The VMCS field encoding.
8089 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8090 * NULL.
8091 */
8092IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8093 PCVMXVEXITINFO pExitInfo)
8094{
8095 /* Nested-guest intercept. */
8096 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8097 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8098 {
8099 if (pExitInfo)
8100 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8101 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8102 }
8103
8104 /* CPL. */
8105 if (pVCpu->iem.s.uCpl == 0)
8106 { /* likely */ }
8107 else
8108 {
8109 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8110 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8111 return iemRaiseGeneralProtectionFault0(pVCpu);
8112 }
8113
8114 /* VMCS pointer in root mode. */
8115 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8116 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8117 { /* likely */ }
8118 else
8119 {
8120 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8122 iemVmxVmFailInvalid(pVCpu);
8123 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8124 return VINF_SUCCESS;
8125 }
8126
8127 /* VMCS-link pointer in non-root mode. */
8128 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8129 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8130 { /* likely */ }
8131 else
8132 {
8133 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8134 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8135 iemVmxVmFailInvalid(pVCpu);
8136 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8137 return VINF_SUCCESS;
8138 }
8139
8140 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8141 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8142 if (!fIsRegOperand)
8143 {
8144 /* Read the value from the specified guest memory location. */
8145 VBOXSTRICTRC rcStrict;
8146 RTGCPTR const GCPtrVal = u64Val;
8147 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8148 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8149 else
8150 {
8151 uint32_t u32Val;
8152 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8153 u64Val = u32Val;
8154 }
8155 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8156 {
8157 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8158 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8159 return rcStrict;
8160 }
8161 }
8162 else
8163 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8164
8165 /* Supported VMCS field. */
8166 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8167 { /* likely */ }
8168 else
8169 {
8170 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8171 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8172 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8173 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8174 return VINF_SUCCESS;
8175 }
8176
8177 /* Read-only VMCS field. */
8178 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8179 if ( !fIsFieldReadOnly
8180 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8181 { /* likely */ }
8182 else
8183 {
8184 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8185 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8186 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8187 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8188 return VINF_SUCCESS;
8189 }
8190
8191 /*
8192 * Setup writing to the current or shadow VMCS.
8193 */
8194 uint8_t *pbVmcs;
8195 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8196 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8197 else
8198 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8199 Assert(pbVmcs);
8200
8201 VMXVMCSFIELDENC FieldEnc;
8202 FieldEnc.u = u64FieldEnc;
8203 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8204 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8205 uint8_t const uWidthType = (uWidth << 2) | uType;
8206 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8207 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8208 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8209 Assert(offField < VMX_V_VMCS_SIZE);
8210
8211 /*
8212 * Write the VMCS component based on the field's effective width.
8213 *
8214 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8215 * indicates high bits (little endian).
8216 */
8217 uint8_t *pbField = pbVmcs + offField;
8218 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8219 switch (uEffWidth)
8220 {
8221 case VMX_VMCS_ENC_WIDTH_64BIT:
8222 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8223 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8224 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8225 }
8226
8227 iemVmxVmSucceed(pVCpu);
8228 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8229 return VINF_SUCCESS;
8230}
8231
8232
8233/**
8234 * VMCLEAR instruction execution worker.
8235 *
8236 * @returns Strict VBox status code.
8237 * @param pVCpu The cross context virtual CPU structure.
8238 * @param cbInstr The instruction length in bytes.
8239 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8240 * @param GCPtrVmcs The linear address of the VMCS pointer.
8241 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8242 * NULL.
8243 *
8244 * @remarks Common VMX instruction checks are already expected to by the caller,
8245 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8246 */
8247IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8248 PCVMXVEXITINFO pExitInfo)
8249{
8250 /* Nested-guest intercept. */
8251 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8252 {
8253 if (pExitInfo)
8254 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8255 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8256 }
8257
8258 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8259
8260 /* CPL. */
8261 if (pVCpu->iem.s.uCpl == 0)
8262 { /* likely */ }
8263 else
8264 {
8265 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8266 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8267 return iemRaiseGeneralProtectionFault0(pVCpu);
8268 }
8269
8270 /* Get the VMCS pointer from the location specified by the source memory operand. */
8271 RTGCPHYS GCPhysVmcs;
8272 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8273 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8274 { /* likely */ }
8275 else
8276 {
8277 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8278 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8279 return rcStrict;
8280 }
8281
8282 /* VMCS pointer alignment. */
8283 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8284 { /* likely */ }
8285 else
8286 {
8287 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8288 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8289 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8290 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8291 return VINF_SUCCESS;
8292 }
8293
8294 /* VMCS physical-address width limits. */
8295 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8296 { /* likely */ }
8297 else
8298 {
8299 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8300 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8301 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8302 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8303 return VINF_SUCCESS;
8304 }
8305
8306 /* VMCS is not the VMXON region. */
8307 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8308 { /* likely */ }
8309 else
8310 {
8311 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8313 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315 return VINF_SUCCESS;
8316 }
8317
8318 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8319 restriction imposed by our implementation. */
8320 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8321 { /* likely */ }
8322 else
8323 {
8324 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8325 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8326 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8327 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8328 return VINF_SUCCESS;
8329 }
8330
8331 /*
8332 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8333 *
8334 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8335 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8336 * to 'clear'.
8337 */
8338 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8339 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8340 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8341 {
8342 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8343 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8344 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8345 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8346 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8347 }
8348 else
8349 {
8350 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8351 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8352 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8353 if (RT_FAILURE(rcStrict))
8354 return rcStrict;
8355 }
8356
8357 iemVmxVmSucceed(pVCpu);
8358 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8359 return VINF_SUCCESS;
8360}
8361
8362
8363/**
8364 * VMPTRST instruction execution worker.
8365 *
8366 * @returns Strict VBox status code.
8367 * @param pVCpu The cross context virtual CPU structure.
8368 * @param cbInstr The instruction length in bytes.
8369 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8370 * @param GCPtrVmcs The linear address of where to store the current VMCS
8371 * pointer.
8372 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8373 * NULL.
8374 *
8375 * @remarks Common VMX instruction checks are already expected to by the caller,
8376 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8377 */
8378IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8379 PCVMXVEXITINFO pExitInfo)
8380{
8381 /* Nested-guest intercept. */
8382 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8383 {
8384 if (pExitInfo)
8385 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8386 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8387 }
8388
8389 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8390
8391 /* CPL. */
8392 if (pVCpu->iem.s.uCpl == 0)
8393 { /* likely */ }
8394 else
8395 {
8396 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8397 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8398 return iemRaiseGeneralProtectionFault0(pVCpu);
8399 }
8400
8401 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8402 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8403 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8404 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8405 {
8406 iemVmxVmSucceed(pVCpu);
8407 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8408 return rcStrict;
8409 }
8410
8411 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8412 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8413 return rcStrict;
8414}
8415
8416
8417/**
8418 * VMPTRLD instruction execution worker.
8419 *
8420 * @returns Strict VBox status code.
8421 * @param pVCpu The cross context virtual CPU structure.
8422 * @param cbInstr The instruction length in bytes.
8423 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8424 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8425 * NULL.
8426 *
8427 * @remarks Common VMX instruction checks are already expected to by the caller,
8428 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8429 */
8430IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8431 PCVMXVEXITINFO pExitInfo)
8432{
8433 /* Nested-guest intercept. */
8434 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8435 {
8436 if (pExitInfo)
8437 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8438 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8439 }
8440
8441 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8442
8443 /* CPL. */
8444 if (pVCpu->iem.s.uCpl == 0)
8445 { /* likely */ }
8446 else
8447 {
8448 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8449 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8450 return iemRaiseGeneralProtectionFault0(pVCpu);
8451 }
8452
8453 /* Get the VMCS pointer from the location specified by the source memory operand. */
8454 RTGCPHYS GCPhysVmcs;
8455 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8456 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8457 { /* likely */ }
8458 else
8459 {
8460 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8461 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8462 return rcStrict;
8463 }
8464
8465 /* VMCS pointer alignment. */
8466 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8467 { /* likely */ }
8468 else
8469 {
8470 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8471 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8472 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8473 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8474 return VINF_SUCCESS;
8475 }
8476
8477 /* VMCS physical-address width limits. */
8478 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8479 { /* likely */ }
8480 else
8481 {
8482 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8484 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8485 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8486 return VINF_SUCCESS;
8487 }
8488
8489 /* VMCS is not the VMXON region. */
8490 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8491 { /* likely */ }
8492 else
8493 {
8494 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8496 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8498 return VINF_SUCCESS;
8499 }
8500
8501 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8502 restriction imposed by our implementation. */
8503 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8504 { /* likely */ }
8505 else
8506 {
8507 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8508 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8509 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8510 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8511 return VINF_SUCCESS;
8512 }
8513
8514 /* Read just the VMCS revision from the VMCS. */
8515 VMXVMCSREVID VmcsRevId;
8516 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8517 if (RT_SUCCESS(rc))
8518 { /* likely */ }
8519 else
8520 {
8521 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8523 return rc;
8524 }
8525
8526 /*
8527 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8528 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8529 */
8530 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8531 && ( !VmcsRevId.n.fIsShadowVmcs
8532 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8533 { /* likely */ }
8534 else
8535 {
8536 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8537 {
8538 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8539 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8540 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8541 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8542 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8543 return VINF_SUCCESS;
8544 }
8545
8546 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8547 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8548 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8549 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8550 return VINF_SUCCESS;
8551 }
8552
8553 /*
8554 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8555 * the cache of an existing, current VMCS back to guest memory before loading a new,
8556 * different current VMCS.
8557 */
8558 bool fLoadVmcsFromMem;
8559 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8560 {
8561 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8562 {
8563 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8564 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8565 fLoadVmcsFromMem = true;
8566 }
8567 else
8568 fLoadVmcsFromMem = false;
8569 }
8570 else
8571 fLoadVmcsFromMem = true;
8572
8573 if (fLoadVmcsFromMem)
8574 {
8575 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8576 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8577 sizeof(VMXVVMCS));
8578 if (RT_SUCCESS(rc))
8579 { /* likely */ }
8580 else
8581 {
8582 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8583 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8584 return rc;
8585 }
8586 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8587 }
8588
8589 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8590 iemVmxVmSucceed(pVCpu);
8591 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8592 return VINF_SUCCESS;
8593}
8594
8595
8596/**
8597 * INVVPID instruction execution worker.
8598 *
8599 * @returns Strict VBox status code.
8600 * @param pVCpu The cross context virtual CPU structure.
8601 * @param cbInstr The instruction length in bytes.
8602 * @param iEffSeg The segment of the invvpid descriptor.
8603 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8604 * @param u64InvvpidType The invalidation type.
8605 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8606 * NULL.
8607 *
8608 * @remarks Common VMX instruction checks are already expected to by the caller,
8609 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8610 */
8611IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8612 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8613{
8614 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8615 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8616 return iemRaiseUndefinedOpcode(pVCpu);
8617
8618 /* Nested-guest intercept. */
8619 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8620 {
8621 if (pExitInfo)
8622 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8623 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8624 }
8625
8626 /* CPL. */
8627 if (pVCpu->iem.s.uCpl != 0)
8628 {
8629 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8630 return iemRaiseGeneralProtectionFault0(pVCpu);
8631 }
8632
8633 /*
8634 * Validate INVVPID invalidation type.
8635 *
8636 * The instruction specifies exactly ONE of the supported invalidation types.
8637 *
8638 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8639 * supported. In theory, it's possible for a CPU to not support flushing individual
8640 * addresses but all the other types or any other combination. We do not take any
8641 * shortcuts here by assuming the types we currently expose to the guest.
8642 */
8643 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8644 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8645 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8646 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8647 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8648 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8649 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8650 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8651 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8652 { /* likely */ }
8653 else
8654 {
8655 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8657 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8658 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8659 return VINF_SUCCESS;
8660 }
8661
8662 /*
8663 * Fetch the invvpid descriptor from guest memory.
8664 */
8665 RTUINT128U uDesc;
8666 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8667 if (rcStrict == VINF_SUCCESS)
8668 {
8669 /*
8670 * Validate the descriptor.
8671 */
8672 if (uDesc.s.Lo > 0xfff)
8673 {
8674 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8675 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8676 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8677 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8678 return VINF_SUCCESS;
8679 }
8680
8681 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8682 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8683 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8684 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8685 switch (u64InvvpidType)
8686 {
8687 case VMXTLBFLUSHVPID_INDIV_ADDR:
8688 {
8689 if (uVpid != 0)
8690 {
8691 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8692 {
8693 /* Invalidate mappings for the linear address tagged with VPID. */
8694 /** @todo PGM support for VPID? Currently just flush everything. */
8695 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8696 iemVmxVmSucceed(pVCpu);
8697 }
8698 else
8699 {
8700 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8701 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8702 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8703 }
8704 }
8705 else
8706 {
8707 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8709 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8710 }
8711 break;
8712 }
8713
8714 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8715 {
8716 if (uVpid != 0)
8717 {
8718 /* Invalidate all mappings with VPID. */
8719 /** @todo PGM support for VPID? Currently just flush everything. */
8720 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8721 iemVmxVmSucceed(pVCpu);
8722 }
8723 else
8724 {
8725 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8726 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8727 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8728 }
8729 break;
8730 }
8731
8732 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8733 {
8734 /* Invalidate all mappings with non-zero VPIDs. */
8735 /** @todo PGM support for VPID? Currently just flush everything. */
8736 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8737 iemVmxVmSucceed(pVCpu);
8738 break;
8739 }
8740
8741 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8742 {
8743 if (uVpid != 0)
8744 {
8745 /* Invalidate all mappings with VPID except global translations. */
8746 /** @todo PGM support for VPID? Currently just flush everything. */
8747 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8748 iemVmxVmSucceed(pVCpu);
8749 }
8750 else
8751 {
8752 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8753 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8754 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8755 }
8756 break;
8757 }
8758 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8759 }
8760 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8761 }
8762 return rcStrict;
8763}
8764
8765
8766/**
8767 * VMXON instruction execution worker.
8768 *
8769 * @returns Strict VBox status code.
8770 * @param pVCpu The cross context virtual CPU structure.
8771 * @param cbInstr The instruction length in bytes.
8772 * @param iEffSeg The effective segment register to use with @a
8773 * GCPtrVmxon.
8774 * @param GCPtrVmxon The linear address of the VMXON pointer.
8775 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8776 * NULL.
8777 *
8778 * @remarks Common VMX instruction checks are already expected to by the caller,
8779 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8780 */
8781IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8782 PCVMXVEXITINFO pExitInfo)
8783{
8784 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8785 {
8786 /* CPL. */
8787 if (pVCpu->iem.s.uCpl == 0)
8788 { /* likely */ }
8789 else
8790 {
8791 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8792 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8793 return iemRaiseGeneralProtectionFault0(pVCpu);
8794 }
8795
8796 /* A20M (A20 Masked) mode. */
8797 if (PGMPhysIsA20Enabled(pVCpu))
8798 { /* likely */ }
8799 else
8800 {
8801 Log(("vmxon: A20M mode -> #GP(0)\n"));
8802 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8803 return iemRaiseGeneralProtectionFault0(pVCpu);
8804 }
8805
8806 /* CR0. */
8807 {
8808 /* CR0 MB1 bits. */
8809 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8810 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8811 { /* likely */ }
8812 else
8813 {
8814 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8815 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8816 return iemRaiseGeneralProtectionFault0(pVCpu);
8817 }
8818
8819 /* CR0 MBZ bits. */
8820 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8821 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8822 { /* likely */ }
8823 else
8824 {
8825 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8826 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8827 return iemRaiseGeneralProtectionFault0(pVCpu);
8828 }
8829 }
8830
8831 /* CR4. */
8832 {
8833 /* CR4 MB1 bits. */
8834 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8835 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8836 { /* likely */ }
8837 else
8838 {
8839 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8840 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8841 return iemRaiseGeneralProtectionFault0(pVCpu);
8842 }
8843
8844 /* CR4 MBZ bits. */
8845 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8846 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8847 { /* likely */ }
8848 else
8849 {
8850 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8851 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8852 return iemRaiseGeneralProtectionFault0(pVCpu);
8853 }
8854 }
8855
8856 /* Feature control MSR's LOCK and VMXON bits. */
8857 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8858 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8859 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8860 { /* likely */ }
8861 else
8862 {
8863 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8864 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8865 return iemRaiseGeneralProtectionFault0(pVCpu);
8866 }
8867
8868 /* Get the VMXON pointer from the location specified by the source memory operand. */
8869 RTGCPHYS GCPhysVmxon;
8870 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8871 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8872 { /* likely */ }
8873 else
8874 {
8875 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8876 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8877 return rcStrict;
8878 }
8879
8880 /* VMXON region pointer alignment. */
8881 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8882 { /* likely */ }
8883 else
8884 {
8885 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8886 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8887 iemVmxVmFailInvalid(pVCpu);
8888 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8889 return VINF_SUCCESS;
8890 }
8891
8892 /* VMXON physical-address width limits. */
8893 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8894 { /* likely */ }
8895 else
8896 {
8897 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8898 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8899 iemVmxVmFailInvalid(pVCpu);
8900 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8901 return VINF_SUCCESS;
8902 }
8903
8904 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8905 restriction imposed by our implementation. */
8906 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8907 { /* likely */ }
8908 else
8909 {
8910 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8911 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8912 iemVmxVmFailInvalid(pVCpu);
8913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8914 return VINF_SUCCESS;
8915 }
8916
8917 /* Read the VMCS revision ID from the VMXON region. */
8918 VMXVMCSREVID VmcsRevId;
8919 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8920 if (RT_SUCCESS(rc))
8921 { /* likely */ }
8922 else
8923 {
8924 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8925 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8926 return rc;
8927 }
8928
8929 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8930 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8931 { /* likely */ }
8932 else
8933 {
8934 /* Revision ID mismatch. */
8935 if (!VmcsRevId.n.fIsShadowVmcs)
8936 {
8937 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8938 VmcsRevId.n.u31RevisionId));
8939 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8940 iemVmxVmFailInvalid(pVCpu);
8941 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8942 return VINF_SUCCESS;
8943 }
8944
8945 /* Shadow VMCS disallowed. */
8946 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8947 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8948 iemVmxVmFailInvalid(pVCpu);
8949 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8950 return VINF_SUCCESS;
8951 }
8952
8953 /*
8954 * Record that we're in VMX operation, block INIT, block and disable A20M.
8955 */
8956 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8957 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8958 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8959
8960 /* Clear address-range monitoring. */
8961 EMMonitorWaitClear(pVCpu);
8962 /** @todo NSTVMX: Intel PT. */
8963
8964 iemVmxVmSucceed(pVCpu);
8965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8966 return VINF_SUCCESS;
8967 }
8968 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8969 {
8970 /* Nested-guest intercept. */
8971 if (pExitInfo)
8972 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8973 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8974 }
8975
8976 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8977
8978 /* CPL. */
8979 if (pVCpu->iem.s.uCpl > 0)
8980 {
8981 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8982 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8983 return iemRaiseGeneralProtectionFault0(pVCpu);
8984 }
8985
8986 /* VMXON when already in VMX root mode. */
8987 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8988 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8989 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8990 return VINF_SUCCESS;
8991}
8992
8993
8994/**
8995 * Implements 'VMXOFF'.
8996 *
8997 * @remarks Common VMX instruction checks are already expected to by the caller,
8998 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8999 */
9000IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9001{
9002 /* Nested-guest intercept. */
9003 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9004 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9005
9006 /* CPL. */
9007 if (pVCpu->iem.s.uCpl == 0)
9008 { /* likely */ }
9009 else
9010 {
9011 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9012 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9013 return iemRaiseGeneralProtectionFault0(pVCpu);
9014 }
9015
9016 /* Dual monitor treatment of SMIs and SMM. */
9017 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9018 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9019 { /* likely */ }
9020 else
9021 {
9022 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9023 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9024 return VINF_SUCCESS;
9025 }
9026
9027 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9028 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9029 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9030
9031 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9032 { /** @todo NSTVMX: Unblock SMI. */ }
9033
9034 EMMonitorWaitClear(pVCpu);
9035 /** @todo NSTVMX: Unblock and enable A20M. */
9036
9037 iemVmxVmSucceed(pVCpu);
9038 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9039 return VINF_SUCCESS;
9040}
9041
9042
9043/**
9044 * Implements 'VMXON'.
9045 */
9046IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9047{
9048 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9049}
9050
9051
9052/**
9053 * Implements 'VMLAUNCH'.
9054 */
9055IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9056{
9057 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9058}
9059
9060
9061/**
9062 * Implements 'VMRESUME'.
9063 */
9064IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9065{
9066 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9067}
9068
9069
9070/**
9071 * Implements 'VMPTRLD'.
9072 */
9073IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9074{
9075 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9076}
9077
9078
9079/**
9080 * Implements 'VMPTRST'.
9081 */
9082IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9083{
9084 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9085}
9086
9087
9088/**
9089 * Implements 'VMCLEAR'.
9090 */
9091IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9092{
9093 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9094}
9095
9096
9097/**
9098 * Implements 'VMWRITE' register.
9099 */
9100IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9101{
9102 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9103}
9104
9105
9106/**
9107 * Implements 'VMWRITE' memory.
9108 */
9109IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9110{
9111 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9112}
9113
9114
9115/**
9116 * Implements 'VMREAD' register (64-bit).
9117 */
9118IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9119{
9120 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9121}
9122
9123
9124/**
9125 * Implements 'VMREAD' register (32-bit).
9126 */
9127IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9128{
9129 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9130}
9131
9132
9133/**
9134 * Implements 'VMREAD' memory, 64-bit register.
9135 */
9136IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9137{
9138 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9139}
9140
9141
9142/**
9143 * Implements 'VMREAD' memory, 32-bit register.
9144 */
9145IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9146{
9147 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9148}
9149
9150
9151/**
9152 * Implements 'INVVPID'.
9153 */
9154IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9155{
9156 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9157}
9158
9159
9160/**
9161 * Implements VMX's implementation of PAUSE.
9162 */
9163IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9164{
9165 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9166 {
9167 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9168 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9169 return rcStrict;
9170 }
9171
9172 /*
9173 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9174 * a VM-exit, the instruction operates normally.
9175 */
9176 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9177 return VINF_SUCCESS;
9178}
9179
9180#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9181
9182
9183/**
9184 * Implements 'VMCALL'.
9185 */
9186IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9187{
9188#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9189 /* Nested-guest intercept. */
9190 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9191 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9192#endif
9193
9194 /* Join forces with vmmcall. */
9195 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9196}
9197
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