VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78654

Last change on this file since 78654 was 78654, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 PAUSE instruction doesn't pass extra info other than the length.
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File size: 362.7 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78654 2019-05-22 10:48:06Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64FieldEnc The VMCS field encoding.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the VM-exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param uExitQual The VM-exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = uExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitQual The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1404 * mask and the read-shadow (CR0/CR4 read).
1405 *
1406 * @returns The masked CR0/CR4.
1407 * @param pVCpu The cross context virtual CPU structure.
1408 * @param iCrReg The control register (either CR0 or CR4).
1409 * @param uGuestCrX The current guest CR0 or guest CR4.
1410 */
1411IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1412{
1413 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1414 Assert(iCrReg == 0 || iCrReg == 4);
1415
1416 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1417 Assert(pVmcs);
1418
1419 /*
1420 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1421 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1422 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1423 *
1424 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1425 */
1426 uint64_t fGstHostMask;
1427 uint64_t fReadShadow;
1428 if (iCrReg == 0)
1429 {
1430 fGstHostMask = pVmcs->u64Cr0Mask.u;
1431 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1432 }
1433 else
1434 {
1435 fGstHostMask = pVmcs->u64Cr4Mask.u;
1436 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1437 }
1438
1439 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1440 return fMaskedCrX;
1441}
1442
1443
1444/**
1445 * Saves the guest control registers, debug registers and some MSRs are part of
1446 * VM-exit.
1447 *
1448 * @param pVCpu The cross context virtual CPU structure.
1449 */
1450IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1451{
1452 /*
1453 * Saves the guest control registers, debug registers and some MSRs.
1454 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1455 */
1456 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1457
1458 /* Save control registers. */
1459 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1460 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1461 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1462
1463 /* Save SYSENTER CS, ESP, EIP. */
1464 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1465 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1466 {
1467 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1468 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1469 }
1470 else
1471 {
1472 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1473 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1474 }
1475
1476 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1477 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1478 {
1479 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1480 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1481 }
1482
1483 /* Save PAT MSR. */
1484 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1485 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1486
1487 /* Save EFER MSR. */
1488 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1489 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1490
1491 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1492 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1493
1494 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1495}
1496
1497
1498/**
1499 * Saves the guest force-flags in preparation of entering the nested-guest.
1500 *
1501 * @param pVCpu The cross context virtual CPU structure.
1502 */
1503IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1504{
1505 /* We shouldn't be called multiple times during VM-entry. */
1506 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1507
1508 /* MTF should not be set outside VMX non-root mode. */
1509 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1510
1511 /*
1512 * Preserve the required force-flags.
1513 *
1514 * We cache and clear force-flags that would affect the execution of the
1515 * nested-guest. Cached flags are then restored while returning to the guest
1516 * if necessary.
1517 *
1518 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1519 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1520 * instruction. Interrupt inhibition for any nested-guest instruction
1521 * is supplied by the guest-interruptibility state VMCS field and will
1522 * be set up as part of loading the guest state.
1523 *
1524 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1525 * successful VM-entry (due to invalid guest-state) need to continue
1526 * blocking NMIs if it was in effect before VM-entry.
1527 *
1528 * - MTF need not be preserved as it's used only in VMX non-root mode and
1529 * is supplied through the VM-execution controls.
1530 *
1531 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1532 * we will be able to generate interrupts that may cause VM-exits for
1533 * the nested-guest.
1534 */
1535 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1536}
1537
1538
1539/**
1540 * Restores the guest force-flags in preparation of exiting the nested-guest.
1541 *
1542 * @param pVCpu The cross context virtual CPU structure.
1543 */
1544IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1545{
1546 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1547 {
1548 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1549 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1550 }
1551}
1552
1553
1554/**
1555 * Perform a VMX transition updated PGM, IEM and CPUM.
1556 *
1557 * @param pVCpu The cross context virtual CPU structure.
1558 */
1559IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1560{
1561 /*
1562 * Inform PGM about paging mode changes.
1563 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1564 * see comment in iemMemPageTranslateAndCheckAccess().
1565 */
1566 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1567# ifdef IN_RING3
1568 Assert(rc != VINF_PGM_CHANGE_MODE);
1569# endif
1570 AssertRCReturn(rc, rc);
1571
1572 /* Inform CPUM (recompiler), can later be removed. */
1573 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1574
1575 /*
1576 * Flush the TLB with new CR3. This is required in case the PGM mode change
1577 * above doesn't actually change anything.
1578 */
1579 if (rc == VINF_SUCCESS)
1580 {
1581 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1582 AssertRCReturn(rc, rc);
1583 }
1584
1585 /* Re-initialize IEM cache/state after the drastic mode switch. */
1586 iemReInitExec(pVCpu);
1587 return rc;
1588}
1589
1590
1591/**
1592 * Calculates the current VMX-preemption timer value.
1593 *
1594 * @param pVCpu The cross context virtual CPU structure.
1595 */
1596IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1597{
1598 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1599 Assert(pVmcs);
1600
1601 /*
1602 * Assume the following:
1603 * PreemptTimerShift = 5
1604 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1605 * EntryTick = 50000 (TSC at time of VM-entry)
1606 *
1607 * CurTick Delta PreemptTimerVal
1608 * ----------------------------------
1609 * 60000 10000 2
1610 * 80000 30000 1
1611 * 90000 40000 0 -> VM-exit.
1612 *
1613 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1614 * The saved VMX-preemption timer value is calculated as follows:
1615 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1616 * E.g.:
1617 * Delta = 10000
1618 * Tmp = 10000 / (2 * 10000) = 0.5
1619 * NewPt = 2 - 0.5 = 2
1620 * Delta = 30000
1621 * Tmp = 30000 / (2 * 10000) = 1.5
1622 * NewPt = 2 - 1.5 = 1
1623 * Delta = 40000
1624 * Tmp = 40000 / 20000 = 2
1625 * NewPt = 2 - 2 = 0
1626 */
1627 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1628 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1629 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1630 uint64_t const uDelta = uCurTick - uEntryTick;
1631 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1632 uint32_t const uPreemptTimer = uVmcsPreemptVal
1633 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1634 return uPreemptTimer;
1635}
1636
1637
1638/**
1639 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1640 *
1641 * @param pVCpu The cross context virtual CPU structure.
1642 */
1643IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1644{
1645 /*
1646 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1647 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1648 */
1649 /* CS, SS, ES, DS, FS, GS. */
1650 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1651 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1652 {
1653 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1654 if (!pSelReg->Attr.n.u1Unusable)
1655 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1656 else
1657 {
1658 /*
1659 * For unusable segments the attributes are undefined except for CS and SS.
1660 * For the rest we don't bother preserving anything but the unusable bit.
1661 */
1662 switch (iSegReg)
1663 {
1664 case X86_SREG_CS:
1665 pVmcs->GuestCs = pSelReg->Sel;
1666 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1667 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1668 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE);
1670 break;
1671
1672 case X86_SREG_SS:
1673 pVmcs->GuestSs = pSelReg->Sel;
1674 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1675 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1676 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1677 break;
1678
1679 case X86_SREG_DS:
1680 pVmcs->GuestDs = pSelReg->Sel;
1681 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1682 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1683 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1684 break;
1685
1686 case X86_SREG_ES:
1687 pVmcs->GuestEs = pSelReg->Sel;
1688 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1689 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1690 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1691 break;
1692
1693 case X86_SREG_FS:
1694 pVmcs->GuestFs = pSelReg->Sel;
1695 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1696 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1697 break;
1698
1699 case X86_SREG_GS:
1700 pVmcs->GuestGs = pSelReg->Sel;
1701 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1702 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1703 break;
1704 }
1705 }
1706 }
1707
1708 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1709 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1710 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1711 | X86DESCATTR_UNUSABLE;
1712 /* LDTR. */
1713 {
1714 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1715 pVmcs->GuestLdtr = pSelReg->Sel;
1716 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1717 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1718 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1719 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1720 }
1721
1722 /* TR. */
1723 {
1724 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1725 pVmcs->GuestTr = pSelReg->Sel;
1726 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1727 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1728 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1729 }
1730
1731 /* GDTR. */
1732 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1733 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1734
1735 /* IDTR. */
1736 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1737 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1738}
1739
1740
1741/**
1742 * Saves guest non-register state as part of VM-exit.
1743 *
1744 * @param pVCpu The cross context virtual CPU structure.
1745 * @param uExitReason The VM-exit reason.
1746 */
1747IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1748{
1749 /*
1750 * Save guest non-register state.
1751 * See Intel spec. 27.3.4 "Saving Non-Register State".
1752 */
1753 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1754
1755 /*
1756 * Activity state.
1757 * Most VM-exits will occur in the active state. However, if the first instruction
1758 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1759 * the VM-exit will be from the HLT activity state.
1760 *
1761 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1762 */
1763 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1764 * not? */
1765 EMSTATE const enmActivityState = EMGetState(pVCpu);
1766 switch (enmActivityState)
1767 {
1768 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1769 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1770 }
1771
1772 /*
1773 * Interruptibility-state.
1774 */
1775 /* NMI. */
1776 pVmcs->u32GuestIntrState = 0;
1777 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1778 {
1779 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1780 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1781 }
1782 else
1783 {
1784 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1785 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1786 }
1787
1788 /* Blocking-by-STI. */
1789 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1790 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1791 {
1792 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1793 * currently. */
1794 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1795 }
1796 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1797
1798 /*
1799 * Pending debug exceptions.
1800 */
1801 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1802 && uExitReason != VMX_EXIT_SMI
1803 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1804 && !HMVmxIsVmexitTrapLike(uExitReason))
1805 {
1806 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1807 * block-by-MovSS is in effect. */
1808 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1809 }
1810 else
1811 {
1812 /*
1813 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1814 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1815 *
1816 * See Intel spec. 24.4.2 "Guest Non-Register State".
1817 */
1818 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1819 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1820 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1821 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1822 if (fPendingDbgMask & fBpHitMask)
1823 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1824 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1825 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1826 }
1827
1828 /*
1829 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1830 *
1831 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1832 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1833 */
1834 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1835 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1836 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1837
1838 /* PDPTEs. */
1839 /* We don't support EPT yet. */
1840 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1841 pVmcs->u64GuestPdpte0.u = 0;
1842 pVmcs->u64GuestPdpte1.u = 0;
1843 pVmcs->u64GuestPdpte2.u = 0;
1844 pVmcs->u64GuestPdpte3.u = 0;
1845}
1846
1847
1848/**
1849 * Saves the guest-state as part of VM-exit.
1850 *
1851 * @returns VBox status code.
1852 * @param pVCpu The cross context virtual CPU structure.
1853 * @param uExitReason The VM-exit reason.
1854 */
1855IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1856{
1857 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1858 Assert(pVmcs);
1859
1860 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1861 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1862
1863 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1864 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1865 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1866
1867 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1868}
1869
1870
1871/**
1872 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1873 *
1874 * @returns VBox status code.
1875 * @param pVCpu The cross context virtual CPU structure.
1876 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1877 */
1878IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1879{
1880 /*
1881 * Save guest MSRs.
1882 * See Intel spec. 27.4 "Saving MSRs".
1883 */
1884 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1885 const char *const pszFailure = "VMX-abort";
1886
1887 /*
1888 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1889 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1890 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1891 */
1892 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1893 if (!cMsrs)
1894 return VINF_SUCCESS;
1895
1896 /*
1897 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1898 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1899 * implementation causes a VMX-abort followed by a triple-fault.
1900 */
1901 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1902 if (fIsMsrCountValid)
1903 { /* likely */ }
1904 else
1905 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1906
1907 /*
1908 * Optimization if the guest hypervisor is using the same guest-physical page for both
1909 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1910 */
1911 PVMXAUTOMSR pMsrArea;
1912 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1913 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1914 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1915 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1916 else
1917 {
1918 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1919 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1920 if (RT_SUCCESS(rc))
1921 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1922 else
1923 {
1924 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1925 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1926 }
1927 }
1928
1929 /*
1930 * Update VM-exit MSR store area.
1931 */
1932 PVMXAUTOMSR pMsr = pMsrArea;
1933 Assert(pMsr);
1934 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1935 {
1936 if ( !pMsr->u32Reserved
1937 && pMsr->u32Msr != MSR_IA32_SMBASE
1938 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1939 {
1940 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1941 if (rcStrict == VINF_SUCCESS)
1942 continue;
1943
1944 /*
1945 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1946 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1947 * recording the MSR index in the auxiliary info. field and indicated further by our
1948 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1949 * if possible, or come up with a better, generic solution.
1950 */
1951 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1952 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1953 ? kVmxVDiag_Vmexit_MsrStoreRing3
1954 : kVmxVDiag_Vmexit_MsrStore;
1955 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1956 }
1957 else
1958 {
1959 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1961 }
1962 }
1963
1964 /*
1965 * Commit the VM-exit MSR store are to guest memory.
1966 */
1967 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1968 if (RT_SUCCESS(rc))
1969 return VINF_SUCCESS;
1970
1971 NOREF(uExitReason);
1972 NOREF(pszFailure);
1973
1974 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1975 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1976}
1977
1978
1979/**
1980 * Performs a VMX abort (due to an fatal error during VM-exit).
1981 *
1982 * @returns Strict VBox status code.
1983 * @param pVCpu The cross context virtual CPU structure.
1984 * @param enmAbort The VMX abort reason.
1985 */
1986IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1987{
1988 /*
1989 * Perform the VMX abort.
1990 * See Intel spec. 27.7 "VMX Aborts".
1991 */
1992 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1993
1994 /* We don't support SMX yet. */
1995 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1996 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1997 {
1998 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1999 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2000 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2001 }
2002
2003 return VINF_EM_TRIPLE_FAULT;
2004}
2005
2006
2007/**
2008 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2009 *
2010 * @param pVCpu The cross context virtual CPU structure.
2011 */
2012IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2013{
2014 /*
2015 * Load host control registers, debug registers and MSRs.
2016 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2017 */
2018 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2019 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2020
2021 /* CR0. */
2022 {
2023 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2024 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2025 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2026 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2027 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2028 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2029 CPUMSetGuestCR0(pVCpu, uValidCr0);
2030 }
2031
2032 /* CR4. */
2033 {
2034 /* CR4 MB1 bits are not modified. */
2035 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2036 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2037 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2038 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2039 if (fHostInLongMode)
2040 uValidCr4 |= X86_CR4_PAE;
2041 else
2042 uValidCr4 &= ~X86_CR4_PCIDE;
2043 CPUMSetGuestCR4(pVCpu, uValidCr4);
2044 }
2045
2046 /* CR3 (host value validated while checking host-state during VM-entry). */
2047 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2048
2049 /* DR7. */
2050 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2051
2052 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2053
2054 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2055 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2056 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2057 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2058
2059 /* FS, GS bases are loaded later while we load host segment registers. */
2060
2061 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2062 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2063 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2064 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2065 {
2066 if (fHostInLongMode)
2067 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2068 else
2069 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2070 }
2071
2072 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2073
2074 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2075 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2076 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2077
2078 /* We don't support IA32_BNDCFGS MSR yet. */
2079}
2080
2081
2082/**
2083 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2084 *
2085 * @param pVCpu The cross context virtual CPU structure.
2086 */
2087IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2088{
2089 /*
2090 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2091 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2092 *
2093 * Warning! Be careful to not touch fields that are reserved by VT-x,
2094 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2095 */
2096 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2097 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2098
2099 /* CS, SS, ES, DS, FS, GS. */
2100 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2101 {
2102 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2103 bool const fUnusable = RT_BOOL(HostSel == 0);
2104 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2105
2106 /* Selector. */
2107 pSelReg->Sel = HostSel;
2108 pSelReg->ValidSel = HostSel;
2109 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2110
2111 /* Limit. */
2112 pSelReg->u32Limit = 0xffffffff;
2113
2114 /* Base. */
2115 pSelReg->u64Base = 0;
2116
2117 /* Attributes. */
2118 if (iSegReg == X86_SREG_CS)
2119 {
2120 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2121 pSelReg->Attr.n.u1DescType = 1;
2122 pSelReg->Attr.n.u2Dpl = 0;
2123 pSelReg->Attr.n.u1Present = 1;
2124 pSelReg->Attr.n.u1Long = fHostInLongMode;
2125 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2126 pSelReg->Attr.n.u1Granularity = 1;
2127 Assert(!pSelReg->Attr.n.u1Unusable);
2128 Assert(!fUnusable);
2129 }
2130 else
2131 {
2132 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2133 pSelReg->Attr.n.u1DescType = 1;
2134 pSelReg->Attr.n.u2Dpl = 0;
2135 pSelReg->Attr.n.u1Present = 1;
2136 pSelReg->Attr.n.u1DefBig = 1;
2137 pSelReg->Attr.n.u1Granularity = 1;
2138 pSelReg->Attr.n.u1Unusable = fUnusable;
2139 }
2140 }
2141
2142 /* FS base. */
2143 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2144 || fHostInLongMode)
2145 {
2146 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2147 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2148 }
2149
2150 /* GS base. */
2151 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2152 || fHostInLongMode)
2153 {
2154 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2155 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2156 }
2157
2158 /* TR. */
2159 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2160 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2161 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2162 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2163 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2164 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2165 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2166 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2167 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2168 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2169 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2170 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2171 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2172
2173 /* LDTR (Warning! do not touch the base and limits here). */
2174 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2175 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2176 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2177 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2178
2179 /* GDTR. */
2180 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2181 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2182 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2183
2184 /* IDTR.*/
2185 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2186 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2187 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2188}
2189
2190
2191/**
2192 * Checks host PDPTes as part of VM-exit.
2193 *
2194 * @param pVCpu The cross context virtual CPU structure.
2195 * @param uExitReason The VM-exit reason (for logging purposes).
2196 */
2197IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2198{
2199 /*
2200 * Check host PDPTEs.
2201 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2202 */
2203 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2204 const char *const pszFailure = "VMX-abort";
2205 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2206
2207 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2208 && !fHostInLongMode)
2209 {
2210 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2211 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2212 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2213 if (RT_SUCCESS(rc))
2214 {
2215 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2216 {
2217 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2218 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2219 { /* likely */ }
2220 else
2221 {
2222 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2223 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2224 }
2225 }
2226 }
2227 else
2228 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2229 }
2230
2231 NOREF(pszFailure);
2232 NOREF(uExitReason);
2233 return VINF_SUCCESS;
2234}
2235
2236
2237/**
2238 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2239 *
2240 * @returns VBox status code.
2241 * @param pVCpu The cross context virtual CPU structure.
2242 * @param pszInstr The VMX instruction name (for logging purposes).
2243 */
2244IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2245{
2246 /*
2247 * Load host MSRs.
2248 * See Intel spec. 27.6 "Loading MSRs".
2249 */
2250 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2251 const char *const pszFailure = "VMX-abort";
2252
2253 /*
2254 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2255 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2256 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2257 */
2258 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2259 if (!cMsrs)
2260 return VINF_SUCCESS;
2261
2262 /*
2263 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2264 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2265 * implementation causes a VMX-abort followed by a triple-fault.
2266 */
2267 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2268 if (fIsMsrCountValid)
2269 { /* likely */ }
2270 else
2271 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2272
2273 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2274 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2275 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2276 if (RT_SUCCESS(rc))
2277 {
2278 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2279 Assert(pMsr);
2280 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2281 {
2282 if ( !pMsr->u32Reserved
2283 && pMsr->u32Msr != MSR_K8_FS_BASE
2284 && pMsr->u32Msr != MSR_K8_GS_BASE
2285 && pMsr->u32Msr != MSR_K6_EFER
2286 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2287 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2288 {
2289 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2290 if (rcStrict == VINF_SUCCESS)
2291 continue;
2292
2293 /*
2294 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2295 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2296 * recording the MSR index in the auxiliary info. field and indicated further by our
2297 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2298 * if possible, or come up with a better, generic solution.
2299 */
2300 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2301 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2302 ? kVmxVDiag_Vmexit_MsrLoadRing3
2303 : kVmxVDiag_Vmexit_MsrLoad;
2304 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2305 }
2306 else
2307 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2308 }
2309 }
2310 else
2311 {
2312 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2313 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2314 }
2315
2316 NOREF(uExitReason);
2317 NOREF(pszFailure);
2318 return VINF_SUCCESS;
2319}
2320
2321
2322/**
2323 * Loads the host state as part of VM-exit.
2324 *
2325 * @returns Strict VBox status code.
2326 * @param pVCpu The cross context virtual CPU structure.
2327 * @param uExitReason The VM-exit reason (for logging purposes).
2328 */
2329IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2330{
2331 /*
2332 * Load host state.
2333 * See Intel spec. 27.5 "Loading Host State".
2334 */
2335 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2336 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2337
2338 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2339 if ( CPUMIsGuestInLongMode(pVCpu)
2340 && !fHostInLongMode)
2341 {
2342 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2343 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2344 }
2345
2346 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2347 iemVmxVmexitLoadHostSegRegs(pVCpu);
2348
2349 /*
2350 * Load host RIP, RSP and RFLAGS.
2351 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2352 */
2353 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2354 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2355 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2356
2357 /* Clear address range monitoring. */
2358 EMMonitorWaitClear(pVCpu);
2359
2360 /* Perform the VMX transition (PGM updates). */
2361 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2362 if (rcStrict == VINF_SUCCESS)
2363 {
2364 /* Check host PDPTEs (only when we've fully switched page tables_. */
2365 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2366 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2367 if (RT_FAILURE(rc))
2368 {
2369 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2370 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2371 }
2372 }
2373 else if (RT_SUCCESS(rcStrict))
2374 {
2375 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2376 uExitReason));
2377 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2378 }
2379 else
2380 {
2381 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2382 return VBOXSTRICTRC_VAL(rcStrict);
2383 }
2384
2385 Assert(rcStrict == VINF_SUCCESS);
2386
2387 /* Load MSRs from the VM-exit auto-load MSR area. */
2388 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2389 if (RT_FAILURE(rc))
2390 {
2391 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2392 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2393 }
2394 return VINF_SUCCESS;
2395}
2396
2397
2398/**
2399 * Gets VM-exit instruction information along with any displacement for an
2400 * instruction VM-exit.
2401 *
2402 * @returns The VM-exit instruction information.
2403 * @param pVCpu The cross context virtual CPU structure.
2404 * @param uExitReason The VM-exit reason.
2405 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2406 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2407 * NULL.
2408 */
2409IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2410{
2411 RTGCPTR GCPtrDisp;
2412 VMXEXITINSTRINFO ExitInstrInfo;
2413 ExitInstrInfo.u = 0;
2414
2415 /*
2416 * Get and parse the ModR/M byte from our decoded opcodes.
2417 */
2418 uint8_t bRm;
2419 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2420 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2421 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2422 {
2423 /*
2424 * ModR/M indicates register addressing.
2425 *
2426 * The primary/secondary register operands are reported in the iReg1 or iReg2
2427 * fields depending on whether it is a read/write form.
2428 */
2429 uint8_t idxReg1;
2430 uint8_t idxReg2;
2431 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2432 {
2433 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2434 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2435 }
2436 else
2437 {
2438 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2439 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2440 }
2441 ExitInstrInfo.All.u2Scaling = 0;
2442 ExitInstrInfo.All.iReg1 = idxReg1;
2443 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2444 ExitInstrInfo.All.fIsRegOperand = 1;
2445 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2446 ExitInstrInfo.All.iSegReg = 0;
2447 ExitInstrInfo.All.iIdxReg = 0;
2448 ExitInstrInfo.All.fIdxRegInvalid = 1;
2449 ExitInstrInfo.All.iBaseReg = 0;
2450 ExitInstrInfo.All.fBaseRegInvalid = 1;
2451 ExitInstrInfo.All.iReg2 = idxReg2;
2452
2453 /* Displacement not applicable for register addressing. */
2454 GCPtrDisp = 0;
2455 }
2456 else
2457 {
2458 /*
2459 * ModR/M indicates memory addressing.
2460 */
2461 uint8_t uScale = 0;
2462 bool fBaseRegValid = false;
2463 bool fIdxRegValid = false;
2464 uint8_t iBaseReg = 0;
2465 uint8_t iIdxReg = 0;
2466 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2467 {
2468 /*
2469 * Parse the ModR/M, displacement for 16-bit addressing mode.
2470 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2471 */
2472 uint16_t u16Disp = 0;
2473 uint8_t const offDisp = offModRm + sizeof(bRm);
2474 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2475 {
2476 /* Displacement without any registers. */
2477 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2478 }
2479 else
2480 {
2481 /* Register (index and base). */
2482 switch (bRm & X86_MODRM_RM_MASK)
2483 {
2484 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2485 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2486 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2487 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2488 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2489 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2490 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2491 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2492 }
2493
2494 /* Register + displacement. */
2495 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2496 {
2497 case 0: break;
2498 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2499 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2500 default:
2501 {
2502 /* Register addressing, handled at the beginning. */
2503 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2504 break;
2505 }
2506 }
2507 }
2508
2509 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2510 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2511 }
2512 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2513 {
2514 /*
2515 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2516 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2517 */
2518 uint32_t u32Disp = 0;
2519 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2520 {
2521 /* Displacement without any registers. */
2522 uint8_t const offDisp = offModRm + sizeof(bRm);
2523 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2524 }
2525 else
2526 {
2527 /* Register (and perhaps scale, index and base). */
2528 uint8_t offDisp = offModRm + sizeof(bRm);
2529 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2530 if (iBaseReg == 4)
2531 {
2532 /* An SIB byte follows the ModR/M byte, parse it. */
2533 uint8_t bSib;
2534 uint8_t const offSib = offModRm + sizeof(bRm);
2535 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2536
2537 /* A displacement may follow SIB, update its offset. */
2538 offDisp += sizeof(bSib);
2539
2540 /* Get the scale. */
2541 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2542
2543 /* Get the index register. */
2544 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2545 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2546
2547 /* Get the base register. */
2548 iBaseReg = bSib & X86_SIB_BASE_MASK;
2549 fBaseRegValid = true;
2550 if (iBaseReg == 5)
2551 {
2552 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2553 {
2554 /* Mod is 0 implies a 32-bit displacement with no base. */
2555 fBaseRegValid = false;
2556 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2557 }
2558 else
2559 {
2560 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2561 iBaseReg = X86_GREG_xBP;
2562 }
2563 }
2564 }
2565
2566 /* Register + displacement. */
2567 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2568 {
2569 case 0: /* Handled above */ break;
2570 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2571 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2572 default:
2573 {
2574 /* Register addressing, handled at the beginning. */
2575 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2576 break;
2577 }
2578 }
2579 }
2580
2581 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2582 }
2583 else
2584 {
2585 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2586
2587 /*
2588 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2589 * See Intel instruction spec. 2.2 "IA-32e Mode".
2590 */
2591 uint64_t u64Disp = 0;
2592 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2593 if (fRipRelativeAddr)
2594 {
2595 /*
2596 * RIP-relative addressing mode.
2597 *
2598 * The displacement is 32-bit signed implying an offset range of +/-2G.
2599 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2600 */
2601 uint8_t const offDisp = offModRm + sizeof(bRm);
2602 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2603 }
2604 else
2605 {
2606 uint8_t offDisp = offModRm + sizeof(bRm);
2607
2608 /*
2609 * Register (and perhaps scale, index and base).
2610 *
2611 * REX.B extends the most-significant bit of the base register. However, REX.B
2612 * is ignored while determining whether an SIB follows the opcode. Hence, we
2613 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2614 *
2615 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2616 */
2617 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2618 if (iBaseReg == 4)
2619 {
2620 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2621 uint8_t bSib;
2622 uint8_t const offSib = offModRm + sizeof(bRm);
2623 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2624
2625 /* Displacement may follow SIB, update its offset. */
2626 offDisp += sizeof(bSib);
2627
2628 /* Get the scale. */
2629 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2630
2631 /* Get the index. */
2632 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2633 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2634
2635 /* Get the base. */
2636 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2637 fBaseRegValid = true;
2638 if (iBaseReg == 5)
2639 {
2640 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2641 {
2642 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2643 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2644 }
2645 else
2646 {
2647 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2648 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2649 }
2650 }
2651 }
2652 iBaseReg |= pVCpu->iem.s.uRexB;
2653
2654 /* Register + displacement. */
2655 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2656 {
2657 case 0: /* Handled above */ break;
2658 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2659 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2660 default:
2661 {
2662 /* Register addressing, handled at the beginning. */
2663 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2664 break;
2665 }
2666 }
2667 }
2668
2669 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2670 }
2671
2672 /*
2673 * The primary or secondary register operand is reported in iReg2 depending
2674 * on whether the primary operand is in read/write form.
2675 */
2676 uint8_t idxReg2;
2677 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2678 {
2679 idxReg2 = bRm & X86_MODRM_RM_MASK;
2680 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2681 idxReg2 |= pVCpu->iem.s.uRexB;
2682 }
2683 else
2684 {
2685 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2686 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2687 idxReg2 |= pVCpu->iem.s.uRexReg;
2688 }
2689 ExitInstrInfo.All.u2Scaling = uScale;
2690 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2691 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2692 ExitInstrInfo.All.fIsRegOperand = 0;
2693 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2694 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2695 ExitInstrInfo.All.iIdxReg = iIdxReg;
2696 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2697 ExitInstrInfo.All.iBaseReg = iBaseReg;
2698 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2699 ExitInstrInfo.All.iReg2 = idxReg2;
2700 }
2701
2702 /*
2703 * Handle exceptions to the norm for certain instructions.
2704 * (e.g. some instructions convey an instruction identity in place of iReg2).
2705 */
2706 switch (uExitReason)
2707 {
2708 case VMX_EXIT_GDTR_IDTR_ACCESS:
2709 {
2710 Assert(VMXINSTRID_IS_VALID(uInstrId));
2711 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2712 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2713 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2714 break;
2715 }
2716
2717 case VMX_EXIT_LDTR_TR_ACCESS:
2718 {
2719 Assert(VMXINSTRID_IS_VALID(uInstrId));
2720 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2721 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2722 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2723 break;
2724 }
2725
2726 case VMX_EXIT_RDRAND:
2727 case VMX_EXIT_RDSEED:
2728 {
2729 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2730 break;
2731 }
2732 }
2733
2734 /* Update displacement and return the constructed VM-exit instruction information field. */
2735 if (pGCPtrDisp)
2736 *pGCPtrDisp = GCPtrDisp;
2737
2738 return ExitInstrInfo.u;
2739}
2740
2741
2742/**
2743 * VMX VM-exit handler.
2744 *
2745 * @returns Strict VBox status code.
2746 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2747 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2748 * triple-fault.
2749 *
2750 * @param pVCpu The cross context virtual CPU structure.
2751 * @param uExitReason The VM-exit reason.
2752 *
2753 * @remarks Make sure VM-exit qualification is updated before calling this
2754 * function!
2755 */
2756IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2757{
2758# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2759 RT_NOREF2(pVCpu, uExitReason);
2760 return VINF_EM_RAW_EMULATE_INSTR;
2761# else
2762 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2763 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2764 | CPUMCTX_EXTRN_EFER /* MSRs */
2765 | CPUMCTX_EXTRN_SYSENTER_MSRS
2766 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2767 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2768 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2769 | CPUMCTX_EXTRN_TR /* Task register */
2770 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2771 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2772
2773 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2774 Assert(pVmcs);
2775
2776 /* Ensure VM-entry interruption information valid bit isn't set. */
2777 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2778
2779 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2780 pVmcs->u32RoExitReason = uExitReason;
2781 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2782 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2783
2784 /*
2785 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2786 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2787 */
2788 {
2789 uint8_t uVector;
2790 uint32_t fFlags;
2791 uint32_t uErrCode;
2792 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2793 if (!fInEventDelivery)
2794 {
2795 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2796 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0); /* Not strictly needed but do it for consistency. */
2797 }
2798 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2799 }
2800
2801 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2802 Assert(pVmcs->u64RoIoRcx.u == 0);
2803 Assert(pVmcs->u64RoIoRsi.u == 0);
2804 Assert(pVmcs->u64RoIoRdi.u == 0);
2805 Assert(pVmcs->u64RoIoRip.u == 0);
2806
2807 /*
2808 * Save the guest state back into the VMCS.
2809 * We only need to save the state when the VM-entry was successful.
2810 */
2811 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2812 if (!fVmentryFailed)
2813 {
2814 /*
2815 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2816 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2817 *
2818 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2819 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2820 * as guest-CPU state would not been modified. Hence for now, we do this only when
2821 * the VM-entry succeeded.
2822 */
2823 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2824 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2825 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2826 {
2827 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2828 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2829 else
2830 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2831 }
2832
2833 /*
2834 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2835 * occurs in enclave mode/SMM which we don't support yet.
2836 *
2837 * If we ever add support for it, we can pass just the lower bits to the functions
2838 * below, till then an assert should suffice.
2839 */
2840 Assert(!RT_HI_U16(uExitReason));
2841
2842 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2843 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2844 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2845 if (RT_SUCCESS(rc))
2846 { /* likely */ }
2847 else
2848 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2849
2850 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2851 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2852 }
2853 else
2854 {
2855 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2856 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2857 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2858 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2859 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2860 }
2861
2862 /*
2863 * Clear any pending VMX nested-guest force-flags.
2864 * These force-flags have no effect on guest execution and will
2865 * be re-evaluated and setup on the next nested-guest VM-entry.
2866 */
2867 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2868 | VMCPU_FF_VMX_MTF
2869 | VMCPU_FF_VMX_APIC_WRITE
2870 | VMCPU_FF_VMX_INT_WINDOW
2871 | VMCPU_FF_VMX_NMI_WINDOW);
2872
2873 /* Restore the host (outer guest) state. */
2874 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2875 if (RT_SUCCESS(rcStrict))
2876 {
2877 Assert(rcStrict == VINF_SUCCESS);
2878 rcStrict = VINF_VMX_VMEXIT;
2879 }
2880 else
2881 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2882
2883 /* Notify HM that we've completed the VM-exit. */
2884 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2885
2886 /* We're no longer in nested-guest execution mode. */
2887 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2888
2889# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2890 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2891 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2892 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2893 if (rcSched != VINF_SUCCESS)
2894 iemSetPassUpStatus(pVCpu, rcSched);
2895# endif
2896 return rcStrict;
2897# endif
2898}
2899
2900
2901/**
2902 * VMX VM-exit handler for VM-exits due to instruction execution.
2903 *
2904 * This is intended for instructions where the caller provides all the relevant
2905 * VM-exit information.
2906 *
2907 * @returns Strict VBox status code.
2908 * @param pVCpu The cross context virtual CPU structure.
2909 * @param pExitInfo Pointer to the VM-exit information.
2910 */
2911IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2912{
2913 /*
2914 * For instructions where any of the following fields are not applicable:
2915 * - VM-exit instruction info. is undefined.
2916 * - VM-exit qualification must be cleared.
2917 * - VM-exit guest-linear address is undefined.
2918 * - VM-exit guest-physical address is undefined.
2919 *
2920 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2921 * instruction execution. For VM-exits that are not due to instruction execution this
2922 * field is undefined.
2923 *
2924 * In our implementation in IEM, all undefined fields are generally cleared. However,
2925 * if the caller supplies information (from say the physical CPU directly) it is
2926 * then possible that the undefined fields are not cleared.
2927 *
2928 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2929 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2930 */
2931 Assert(pExitInfo);
2932 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2933 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2934 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2935
2936 /* Update all the relevant fields from the VM-exit instruction information struct. */
2937 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2938 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2939 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2940 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2941 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2942
2943 /* Perform the VM-exit. */
2944 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2945}
2946
2947
2948/**
2949 * VMX VM-exit handler for VM-exits due to instruction execution.
2950 *
2951 * This is intended for instructions that only provide the VM-exit instruction
2952 * length.
2953 *
2954 * @param pVCpu The cross context virtual CPU structure.
2955 * @param uExitReason The VM-exit reason.
2956 * @param cbInstr The instruction length in bytes.
2957 */
2958IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2959{
2960 VMXVEXITINFO ExitInfo;
2961 RT_ZERO(ExitInfo);
2962 ExitInfo.uReason = uExitReason;
2963 ExitInfo.cbInstr = cbInstr;
2964
2965#ifdef VBOX_STRICT
2966 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2967 switch (uExitReason)
2968 {
2969 case VMX_EXIT_INVEPT:
2970 case VMX_EXIT_INVPCID:
2971 case VMX_EXIT_LDTR_TR_ACCESS:
2972 case VMX_EXIT_GDTR_IDTR_ACCESS:
2973 case VMX_EXIT_VMCLEAR:
2974 case VMX_EXIT_VMPTRLD:
2975 case VMX_EXIT_VMPTRST:
2976 case VMX_EXIT_VMREAD:
2977 case VMX_EXIT_VMWRITE:
2978 case VMX_EXIT_VMXON:
2979 case VMX_EXIT_XRSTORS:
2980 case VMX_EXIT_XSAVES:
2981 case VMX_EXIT_RDRAND:
2982 case VMX_EXIT_RDSEED:
2983 case VMX_EXIT_IO_INSTR:
2984 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2985 break;
2986 }
2987#endif
2988
2989 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2990}
2991
2992
2993/**
2994 * VMX VM-exit handler for VM-exits due to instruction execution.
2995 *
2996 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2997 * instruction information and VM-exit qualification fields.
2998 *
2999 * @param pVCpu The cross context virtual CPU structure.
3000 * @param uExitReason The VM-exit reason.
3001 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
3002 * @param cbInstr The instruction length in bytes.
3003 *
3004 * @remarks Do not use this for INS/OUTS instruction.
3005 */
3006IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
3007{
3008 VMXVEXITINFO ExitInfo;
3009 RT_ZERO(ExitInfo);
3010 ExitInfo.uReason = uExitReason;
3011 ExitInfo.cbInstr = cbInstr;
3012
3013 /*
3014 * Update the VM-exit qualification field with displacement bytes.
3015 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3016 */
3017 switch (uExitReason)
3018 {
3019 case VMX_EXIT_INVEPT:
3020 case VMX_EXIT_INVPCID:
3021 case VMX_EXIT_INVVPID:
3022 case VMX_EXIT_LDTR_TR_ACCESS:
3023 case VMX_EXIT_GDTR_IDTR_ACCESS:
3024 case VMX_EXIT_VMCLEAR:
3025 case VMX_EXIT_VMPTRLD:
3026 case VMX_EXIT_VMPTRST:
3027 case VMX_EXIT_VMREAD:
3028 case VMX_EXIT_VMWRITE:
3029 case VMX_EXIT_VMXON:
3030 case VMX_EXIT_XRSTORS:
3031 case VMX_EXIT_XSAVES:
3032 case VMX_EXIT_RDRAND:
3033 case VMX_EXIT_RDSEED:
3034 {
3035 /* Construct the VM-exit instruction information. */
3036 RTGCPTR GCPtrDisp;
3037 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3038
3039 /* Update the VM-exit instruction information. */
3040 ExitInfo.InstrInfo.u = uInstrInfo;
3041
3042 /* Update the VM-exit qualification. */
3043 ExitInfo.u64Qual = GCPtrDisp;
3044 break;
3045 }
3046
3047 default:
3048 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3049 break;
3050 }
3051
3052 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3053}
3054
3055
3056/**
3057 * VMX VM-exit handler for VM-exits due to INVLPG.
3058 *
3059 * @returns Strict VBox status code.
3060 * @param pVCpu The cross context virtual CPU structure.
3061 * @param GCPtrPage The guest-linear address of the page being invalidated.
3062 * @param cbInstr The instruction length in bytes.
3063 */
3064IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3065{
3066 VMXVEXITINFO ExitInfo;
3067 RT_ZERO(ExitInfo);
3068 ExitInfo.uReason = VMX_EXIT_INVLPG;
3069 ExitInfo.cbInstr = cbInstr;
3070 ExitInfo.u64Qual = GCPtrPage;
3071 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3072
3073 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3074}
3075
3076
3077/**
3078 * VMX VM-exit handler for VM-exits due to LMSW.
3079 *
3080 * @returns Strict VBox status code.
3081 * @param pVCpu The cross context virtual CPU structure.
3082 * @param uGuestCr0 The current guest CR0.
3083 * @param pu16NewMsw The machine-status word specified in LMSW's source
3084 * operand. This will be updated depending on the VMX
3085 * guest/host CR0 mask if LMSW is not intercepted.
3086 * @param GCPtrEffDst The guest-linear address of the source operand in case
3087 * of a memory operand. For register operand, pass
3088 * NIL_RTGCPTR.
3089 * @param cbInstr The instruction length in bytes.
3090 */
3091IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3092 uint8_t cbInstr)
3093{
3094 /*
3095 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3096 *
3097 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3098 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3099 */
3100 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3101 Assert(pVmcs);
3102 Assert(pu16NewMsw);
3103
3104 bool fIntercept = false;
3105 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3106 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3107
3108 /*
3109 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3110 * CR0.PE case first, before the rest of the bits in the MSW.
3111 *
3112 * If CR0.PE is owned by the host and CR0.PE differs between the
3113 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3114 */
3115 if ( (fGstHostMask & X86_CR0_PE)
3116 && (*pu16NewMsw & X86_CR0_PE)
3117 && !(fReadShadow & X86_CR0_PE))
3118 fIntercept = true;
3119
3120 /*
3121 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3122 * bits differ between the MSW (source operand) and the read-shadow, we must
3123 * cause a VM-exit.
3124 */
3125 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3126 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3127 fIntercept = true;
3128
3129 if (fIntercept)
3130 {
3131 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3132
3133 VMXVEXITINFO ExitInfo;
3134 RT_ZERO(ExitInfo);
3135 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3136 ExitInfo.cbInstr = cbInstr;
3137
3138 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3139 if (fMemOperand)
3140 {
3141 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3142 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3143 }
3144
3145 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3146 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3147 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3148 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3149
3150 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3151 }
3152
3153 /*
3154 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3155 * CR0 guest/host mask must be left unmodified.
3156 *
3157 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3158 */
3159 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3160 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3161
3162 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3163}
3164
3165
3166/**
3167 * VMX VM-exit handler for VM-exits due to CLTS.
3168 *
3169 * @returns Strict VBox status code.
3170 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3171 * VM-exit but must not modify the guest CR0.TS bit.
3172 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3173 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3174 * CR0 fixed bits in VMX operation).
3175 * @param pVCpu The cross context virtual CPU structure.
3176 * @param cbInstr The instruction length in bytes.
3177 */
3178IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3179{
3180 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3181 Assert(pVmcs);
3182
3183 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3184 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3185
3186 /*
3187 * If CR0.TS is owned by the host:
3188 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3189 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3190 * CLTS instruction completes without clearing CR0.TS.
3191 *
3192 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3193 */
3194 if (fGstHostMask & X86_CR0_TS)
3195 {
3196 if (fReadShadow & X86_CR0_TS)
3197 {
3198 Log2(("clts: Guest intercept -> VM-exit\n"));
3199
3200 VMXVEXITINFO ExitInfo;
3201 RT_ZERO(ExitInfo);
3202 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3203 ExitInfo.cbInstr = cbInstr;
3204 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3205 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3206 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3207 }
3208
3209 return VINF_VMX_MODIFIES_BEHAVIOR;
3210 }
3211
3212 /*
3213 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3214 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3215 */
3216 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3217}
3218
3219
3220/**
3221 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3222 * (CR0/CR4 write).
3223 *
3224 * @returns Strict VBox status code.
3225 * @param pVCpu The cross context virtual CPU structure.
3226 * @param iCrReg The control register (either CR0 or CR4).
3227 * @param uGuestCrX The current guest CR0/CR4.
3228 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3229 * if no VM-exit is caused.
3230 * @param iGReg The general register from which the CR0/CR4 value is
3231 * being loaded.
3232 * @param cbInstr The instruction length in bytes.
3233 */
3234IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3235 uint8_t cbInstr)
3236{
3237 Assert(puNewCrX);
3238 Assert(iCrReg == 0 || iCrReg == 4);
3239 Assert(iGReg < X86_GREG_COUNT);
3240
3241 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3242 Assert(pVmcs);
3243
3244 uint64_t uGuestCrX;
3245 uint64_t fGstHostMask;
3246 uint64_t fReadShadow;
3247 if (iCrReg == 0)
3248 {
3249 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3250 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3251 fGstHostMask = pVmcs->u64Cr0Mask.u;
3252 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3253 }
3254 else
3255 {
3256 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3257 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3258 fGstHostMask = pVmcs->u64Cr4Mask.u;
3259 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3260 }
3261
3262 /*
3263 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3264 * corresponding bits differ between the source operand and the read-shadow,
3265 * we must cause a VM-exit.
3266 *
3267 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3268 */
3269 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3270 {
3271 Assert(fGstHostMask != 0);
3272 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3273
3274 VMXVEXITINFO ExitInfo;
3275 RT_ZERO(ExitInfo);
3276 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3277 ExitInfo.cbInstr = cbInstr;
3278 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3279 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3280 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3281 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3282 }
3283
3284 /*
3285 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3286 * must not be modified the instruction.
3287 *
3288 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3289 */
3290 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3291
3292 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3293}
3294
3295
3296/**
3297 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3298 *
3299 * @returns VBox strict status code.
3300 * @param pVCpu The cross context virtual CPU structure.
3301 * @param iGReg The general register to which the CR3 value is being stored.
3302 * @param cbInstr The instruction length in bytes.
3303 */
3304IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3305{
3306 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3307 Assert(pVmcs);
3308 Assert(iGReg < X86_GREG_COUNT);
3309 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3310
3311 /*
3312 * If the CR3-store exiting control is set, we must cause a VM-exit.
3313 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3314 */
3315 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3316 {
3317 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3318
3319 VMXVEXITINFO ExitInfo;
3320 RT_ZERO(ExitInfo);
3321 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3322 ExitInfo.cbInstr = cbInstr;
3323 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3324 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3325 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3326 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3327 }
3328
3329 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3330}
3331
3332
3333/**
3334 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3335 *
3336 * @returns VBox strict status code.
3337 * @param pVCpu The cross context virtual CPU structure.
3338 * @param uNewCr3 The new CR3 value.
3339 * @param iGReg The general register from which the CR3 value is being
3340 * loaded.
3341 * @param cbInstr The instruction length in bytes.
3342 */
3343IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3344{
3345 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3346 Assert(pVmcs);
3347 Assert(iGReg < X86_GREG_COUNT);
3348
3349 /*
3350 * If the CR3-load exiting control is set and the new CR3 value does not
3351 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3352 *
3353 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3354 */
3355 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3356 {
3357 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3358 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3359
3360 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3361 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3362 if (!fIntercept)
3363 {
3364 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3365 {
3366 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3367 if (uNewCr3 != uCr3TargetValue)
3368 {
3369 fIntercept = true;
3370 break;
3371 }
3372 }
3373 }
3374
3375 if (fIntercept)
3376 {
3377 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3378
3379 VMXVEXITINFO ExitInfo;
3380 RT_ZERO(ExitInfo);
3381 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3382 ExitInfo.cbInstr = cbInstr;
3383 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3384 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3385 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3386 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3387 }
3388 }
3389
3390 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3391}
3392
3393
3394/**
3395 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3396 *
3397 * @returns VBox strict status code.
3398 * @param pVCpu The cross context virtual CPU structure.
3399 * @param iGReg The general register to which the CR8 value is being stored.
3400 * @param cbInstr The instruction length in bytes.
3401 */
3402IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3403{
3404 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3405 Assert(pVmcs);
3406 Assert(iGReg < X86_GREG_COUNT);
3407
3408 /*
3409 * If the CR8-store exiting control is set, we must cause a VM-exit.
3410 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3411 */
3412 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3413 {
3414 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3415
3416 VMXVEXITINFO ExitInfo;
3417 RT_ZERO(ExitInfo);
3418 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3419 ExitInfo.cbInstr = cbInstr;
3420 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3421 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3422 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3423 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3424 }
3425
3426 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3427}
3428
3429
3430/**
3431 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3432 *
3433 * @returns VBox strict status code.
3434 * @param pVCpu The cross context virtual CPU structure.
3435 * @param iGReg The general register from which the CR8 value is being
3436 * loaded.
3437 * @param cbInstr The instruction length in bytes.
3438 */
3439IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3440{
3441 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3442 Assert(pVmcs);
3443 Assert(iGReg < X86_GREG_COUNT);
3444
3445 /*
3446 * If the CR8-load exiting control is set, we must cause a VM-exit.
3447 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3448 */
3449 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3450 {
3451 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3452
3453 VMXVEXITINFO ExitInfo;
3454 RT_ZERO(ExitInfo);
3455 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3456 ExitInfo.cbInstr = cbInstr;
3457 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3458 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3459 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3460 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3461 }
3462
3463 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3464}
3465
3466
3467/**
3468 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3469 * GReg,DRx' (DRx read).
3470 *
3471 * @returns VBox strict status code.
3472 * @param pVCpu The cross context virtual CPU structure.
3473 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3474 * VMXINSTRID_MOV_FROM_DRX).
3475 * @param iDrReg The debug register being accessed.
3476 * @param iGReg The general register to/from which the DRx value is being
3477 * store/loaded.
3478 * @param cbInstr The instruction length in bytes.
3479 */
3480IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3481 uint8_t cbInstr)
3482{
3483 Assert(iDrReg <= 7);
3484 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3485 Assert(iGReg < X86_GREG_COUNT);
3486
3487 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3488 Assert(pVmcs);
3489
3490 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3491 {
3492 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3493 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3494 VMXVEXITINFO ExitInfo;
3495 RT_ZERO(ExitInfo);
3496 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3497 ExitInfo.cbInstr = cbInstr;
3498 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3499 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3500 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3501 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3502 }
3503
3504 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3505}
3506
3507
3508/**
3509 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3510 *
3511 * @returns VBox strict status code.
3512 * @param pVCpu The cross context virtual CPU structure.
3513 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3514 * VMXINSTRID_IO_OUT).
3515 * @param u16Port The I/O port being accessed.
3516 * @param fImm Whether the I/O port was encoded using an immediate operand
3517 * or the implicit DX register.
3518 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3519 * @param cbInstr The instruction length in bytes.
3520 */
3521IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3522 uint8_t cbInstr)
3523{
3524 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3525 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3526
3527 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3528 if (fIntercept)
3529 {
3530 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3531 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3532 VMXVEXITINFO ExitInfo;
3533 RT_ZERO(ExitInfo);
3534 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3535 ExitInfo.cbInstr = cbInstr;
3536 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3537 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3538 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3539 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3540 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3541 }
3542
3543 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3544}
3545
3546
3547/**
3548 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3549 *
3550 * @returns VBox strict status code.
3551 * @param pVCpu The cross context virtual CPU structure.
3552 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3553 * VMXINSTRID_IO_OUTS).
3554 * @param u16Port The I/O port being accessed.
3555 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3556 * @param fRep Whether the instruction has a REP prefix or not.
3557 * @param ExitInstrInfo The VM-exit instruction info. field.
3558 * @param cbInstr The instruction length in bytes.
3559 */
3560IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3561 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3562{
3563 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3564 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3565 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3566 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3567 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3568
3569 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3570 if (fIntercept)
3571 {
3572 /*
3573 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3574 */
3575 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3576 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3577 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3578 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3579 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3580
3581 uint32_t uDirection;
3582 uint64_t uGuestLinearAddr;
3583 if (uInstrId == VMXINSTRID_IO_INS)
3584 {
3585 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3586 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3587 }
3588 else
3589 {
3590 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3591 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3592 }
3593
3594 /*
3595 * If the segment is unusable, the guest-linear address in undefined.
3596 * We shall clear it for consistency.
3597 *
3598 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3599 */
3600 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3601 uGuestLinearAddr = 0;
3602
3603 VMXVEXITINFO ExitInfo;
3604 RT_ZERO(ExitInfo);
3605 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3606 ExitInfo.cbInstr = cbInstr;
3607 ExitInfo.InstrInfo = ExitInstrInfo;
3608 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3609 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3610 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3611 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3612 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3613 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3614 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3615 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3616 }
3617
3618 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3619}
3620
3621
3622/**
3623 * VMX VM-exit handler for VM-exits due to MWAIT.
3624 *
3625 * @returns VBox strict status code.
3626 * @param pVCpu The cross context virtual CPU structure.
3627 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3628 * @param cbInstr The instruction length in bytes.
3629 */
3630IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3631{
3632 VMXVEXITINFO ExitInfo;
3633 RT_ZERO(ExitInfo);
3634 ExitInfo.uReason = VMX_EXIT_MWAIT;
3635 ExitInfo.cbInstr = cbInstr;
3636 ExitInfo.u64Qual = fMonitorHwArmed;
3637 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3638}
3639
3640
3641/**
3642 * VMX VM-exit handler for VM-exits due to PAUSE.
3643 *
3644 * @returns VBox strict status code.
3645 * @param pVCpu The cross context virtual CPU structure.
3646 * @param cbInstr The instruction length in bytes.
3647 */
3648IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3649{
3650 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3651 Assert(pVmcs);
3652
3653 /*
3654 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3655 * "PAUSE-loop exiting" control.
3656 *
3657 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3658 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3659 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3660 * a VM-exit.
3661 *
3662 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3663 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3664 */
3665 bool fIntercept = false;
3666 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3667 fIntercept = true;
3668 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3669 && pVCpu->iem.s.uCpl == 0)
3670 {
3671 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3672
3673 /*
3674 * A previous-PAUSE-tick value of 0 is used to identify the first time
3675 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3676 * consider this to be the first execution of PAUSE in a loop according
3677 * to the Intel.
3678 *
3679 * All subsequent records for the previous-PAUSE-tick we ensure that it
3680 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3681 */
3682 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3683 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3684 uint64_t const uTick = TMCpuTickGet(pVCpu);
3685 uint32_t const uPleGap = pVmcs->u32PleGap;
3686 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3687 if ( *puPrevPauseTick == 0
3688 || uTick - *puPrevPauseTick > uPleGap)
3689 *puFirstPauseLoopTick = uTick;
3690 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3691 fIntercept = true;
3692
3693 *puPrevPauseTick = uTick | 1;
3694 }
3695
3696 if (fIntercept)
3697 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3698
3699 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3700}
3701
3702
3703/**
3704 * VMX VM-exit handler for VM-exits due to task switches.
3705 *
3706 * @returns VBox strict status code.
3707 * @param pVCpu The cross context virtual CPU structure.
3708 * @param enmTaskSwitch The cause of the task switch.
3709 * @param SelNewTss The selector of the new TSS.
3710 * @param cbInstr The instruction length in bytes.
3711 */
3712IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3713{
3714 /*
3715 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3716 *
3717 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3718 * instruction or delivery of the exception generated by one of these instructions
3719 * lead to a task switch through a task gate in the IDT, we need to provide the
3720 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3721 * leaves the VM-exit instruction length field undefined.
3722 *
3723 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3724 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3725 */
3726 Assert(cbInstr <= 15);
3727
3728 uint8_t uType;
3729 switch (enmTaskSwitch)
3730 {
3731 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3732 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3733 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3734 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3735 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3736 }
3737
3738 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3739 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3740 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3741 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3742 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3743}
3744
3745
3746/**
3747 * VMX VM-exit handler for VM-exits due to task switches.
3748 *
3749 * This is intended for task switches where the caller provides all the relevant
3750 * VM-exit information.
3751 *
3752 * @returns VBox strict status code.
3753 * @param pVCpu The cross context virtual CPU structure.
3754 * @param pExitInfo Pointer to the VM-exit information.
3755 * @param pExitEventInfo Pointer to the VM-exit event information.
3756 */
3757IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PVMXVEXITINFO pExitInfo, PVMXVEXITEVENTINFO pExitEventInfo)
3758{
3759 Assert(pExitInfo);
3760 Assert(pExitEventInfo);
3761
3762 /* The VM-exit qualification is mandatory for all task-switch VM-exits. */
3763 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3764 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3765
3766 /*
3767 * Figure out if an instruction was the source of the task switch.
3768 *
3769 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3770 * of an event generated by a software interrupt (INT-N), privileged software
3771 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3772 * the instruction length.
3773 */
3774 bool fHasInstrLen;
3775 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3776 {
3777 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3778 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3779 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3780 if (fIdtVectInfoValid)
3781 {
3782 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3783 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3784 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3785
3786 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3787 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3788 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3789 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3790 fHasInstrLen = true;
3791 else
3792 fHasInstrLen = false;
3793 }
3794 else
3795 fHasInstrLen = false;
3796 }
3797 else
3798 {
3799 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3800 fHasInstrLen = true;
3801 }
3802
3803 if (fHasInstrLen)
3804 {
3805 Assert(pExitInfo->cbInstr > 0);
3806 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3807 }
3808 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3809}
3810
3811
3812/**
3813 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3814 *
3815 * @returns VBox strict status code.
3816 * @param pVCpu The cross context virtual CPU structure.
3817 */
3818IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3819{
3820 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3821 Assert(pVmcs);
3822
3823 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3824 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3825 {
3826 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3827 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3828
3829 /*
3830 * Calculate the current VMX-preemption timer value.
3831 * Only if the value has reached zero, we cause the VM-exit.
3832 */
3833 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3834 if (!uPreemptTimer)
3835 {
3836 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3837 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3838 pVmcs->u32PreemptTimer = 0;
3839
3840 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3841 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3842 }
3843 }
3844
3845 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3846}
3847
3848
3849/**
3850 * VMX VM-exit handler for VM-exits due to external interrupts.
3851 *
3852 * @returns VBox strict status code.
3853 * @param pVCpu The cross context virtual CPU structure.
3854 * @param uVector The external interrupt vector (pass 0 if the interrupt
3855 * is still pending since we typically won't know the
3856 * vector).
3857 * @param fIntPending Whether the external interrupt is pending or
3858 * acknowledged in the interrupt controller.
3859 */
3860IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3861{
3862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3863 Assert(pVmcs);
3864 Assert(fIntPending || uVector == 0);
3865
3866 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3867 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3868 * functions require prior checking of a blanket intercept and which don't.
3869 * It is better for the caller to check a blanket intercept performance wise
3870 * than making a function call. Leaving this as a todo because it is more
3871 * a performance issue. */
3872
3873 /* The VM-exit is subject to "External interrupt exiting" being set. */
3874 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3875 {
3876 if (fIntPending)
3877 {
3878 /*
3879 * If the interrupt is pending and we don't need to acknowledge the
3880 * interrupt on VM-exit, cause the VM-exit immediately.
3881 *
3882 * See Intel spec 25.2 "Other Causes Of VM Exits".
3883 */
3884 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3885 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3886
3887 /*
3888 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3889 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3890 * acknowledged that the interrupt has been consumed.
3891 */
3892 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3893 }
3894
3895 /*
3896 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3897 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3898 * all set, we cause the VM-exit now. We need to record the external interrupt that
3899 * just occurred in the VM-exit interruption information field.
3900 *
3901 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3902 */
3903 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3904 {
3905 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3906 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3907 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3908 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3909 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3910 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3911 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3912 }
3913 }
3914
3915 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3916}
3917
3918
3919/**
3920 * VMX VM-exit handler for VM-exits due to NMIs.
3921 *
3922 * @returns VBox strict status code.
3923 * @param pVCpu The cross context virtual CPU structure.
3924 *
3925 * @remarks This function might import externally kept DR6 if necessary.
3926 */
3927IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3928{
3929 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3930 Assert(pVmcs);
3931 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3932 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3933 NOREF(pVmcs);
3934 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3935}
3936
3937
3938/**
3939 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3940 *
3941 * @returns VBox strict status code.
3942 * @param pVCpu The cross context virtual CPU structure.
3943 * @param uVector The SIPI vector.
3944 */
3945IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3946{
3947 iemVmxVmcsSetExitQual(pVCpu, uVector);
3948 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3949}
3950
3951
3952/**
3953 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3954 * an event.
3955 *
3956 * @returns VBox strict status code.
3957 * @param pVCpu The cross context virtual CPU structure.
3958 */
3959IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3960{
3961 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3962 Assert(pVmcs);
3963
3964 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3965 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3966 {
3967 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3968 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3969 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3970 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3971 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3972 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3973 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3974 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3975 iemVmxVmcsSetExitQual(pVCpu, 0);
3976 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3977
3978 /*
3979 * A VM-exit is not considered to occur during event delivery when the original
3980 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3981 * using the exception bitmap).
3982 *
3983 * Therefore, we must clear the original event from the IDT-vectoring fields which
3984 * would've been recorded before causing the VM-exit.
3985 *
3986 * 27.2.3 "Information for VM Exits During Event Delivery"
3987 */
3988 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3989 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3990
3991 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3992 }
3993
3994 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3995}
3996
3997
3998/**
3999 * VMX VM-exit handler for VM-exits due to delivery of an event.
4000 *
4001 * @returns VBox strict status code.
4002 * @param pVCpu The cross context virtual CPU structure.
4003 * @param uVector The interrupt / exception vector.
4004 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
4005 * @param uErrCode The error code associated with the event.
4006 * @param uCr2 The CR2 value in case of a \#PF exception.
4007 * @param cbInstr The instruction length in bytes.
4008 */
4009IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
4010 uint8_t cbInstr)
4011{
4012 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4013 Assert(pVmcs);
4014
4015 /*
4016 * If the event is being injected as part of VM-entry, it isn't subject to event
4017 * intercepts in the nested-guest. However, secondary exceptions that occur during
4018 * injection of any event -are- subject to event interception.
4019 *
4020 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
4021 */
4022 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
4023 {
4024 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
4025 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
4026 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4027 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
4028 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
4029 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
4030 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
4031 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
4032 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
4033
4034 /*
4035 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
4036 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
4037 *
4038 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
4039 */
4040 if ( uVector == X86_XCPT_NMI
4041 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
4042 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
4043 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
4044 else
4045 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
4046
4047 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4048 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4049 }
4050
4051 /*
4052 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4053 * If not, the caller will continue delivery of the external interrupt as it would
4054 * normally. The interrupt is no longer pending in the interrupt controller at this
4055 * point.
4056 */
4057 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4058 {
4059 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4060 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4061 }
4062
4063 /*
4064 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4065 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4066 */
4067 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4068 bool fIntercept = false;
4069 bool fIsHwXcpt = false;
4070 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4071 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4072 {
4073 fIsHwXcpt = true;
4074
4075 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4076 if (uVector == X86_XCPT_NMI)
4077 {
4078 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
4079 fIntercept = true;
4080 }
4081 else
4082 {
4083 /* Page-faults are subject to masking using its error code. */
4084 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4085 if (uVector == X86_XCPT_PF)
4086 {
4087 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4088 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4089 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4090 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4091 }
4092
4093 /* Consult the exception bitmap for all other hardware exceptions. */
4094 Assert(uVector <= X86_XCPT_LAST);
4095 if (fXcptBitmap & RT_BIT(uVector))
4096 fIntercept = true;
4097 }
4098 }
4099 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4100
4101 /*
4102 * Now that we've determined whether the software interrupt or hardware exception
4103 * causes a VM-exit, we need to construct the relevant VM-exit information and
4104 * cause the VM-exit.
4105 */
4106 if (fIntercept)
4107 {
4108 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4109
4110 /* Construct the rest of the event related information fields and cause the VM-exit. */
4111 uint64_t uExitQual = 0;
4112 if (fIsHwXcpt)
4113 {
4114 if (uVector == X86_XCPT_PF)
4115 {
4116 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4117 uExitQual = uCr2;
4118 }
4119 else if (uVector == X86_XCPT_DB)
4120 {
4121 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4122 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4123 }
4124 }
4125
4126 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4127 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4128 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4129 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4130 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4131 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4132 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4133 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4134 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4135 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4136 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4137
4138 /*
4139 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4140 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4141 * length.
4142 */
4143 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4144 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4145 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4146 else
4147 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4148
4149 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4150 }
4151
4152 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4153}
4154
4155
4156/**
4157 * VMX VM-exit handler for VM-exits due to a triple fault.
4158 *
4159 * @returns VBox strict status code.
4160 * @param pVCpu The cross context virtual CPU structure.
4161 */
4162IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4163{
4164 /*
4165 * A VM-exit is not considered to occur during event delivery when the original
4166 * event results in a triple-fault.
4167 *
4168 * Therefore, we must clear the original event from the IDT-vectoring fields which
4169 * would've been recorded before causing the VM-exit.
4170 *
4171 * 27.2.3 "Information for VM Exits During Event Delivery"
4172 */
4173 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4174 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4175
4176 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4177}
4178
4179
4180/**
4181 * VMX VM-exit handler for APIC-accesses.
4182 *
4183 * @param pVCpu The cross context virtual CPU structure.
4184 * @param offAccess The offset of the register being accessed.
4185 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4186 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4187 */
4188IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4189{
4190 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4191
4192 VMXAPICACCESS enmAccess;
4193 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4194 if (fInEventDelivery)
4195 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4196 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4197 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4198 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4199 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4200 else
4201 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4202
4203 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4204 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4205 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4206 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4207}
4208
4209
4210/**
4211 * VMX VM-exit handler for APIC-write VM-exits.
4212 *
4213 * @param pVCpu The cross context virtual CPU structure.
4214 * @param offApic The write to the virtual-APIC page offset that caused this
4215 * VM-exit.
4216 */
4217IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4218{
4219 Assert(offApic < XAPIC_OFF_END + 4);
4220
4221 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4222 offApic &= UINT16_C(0xfff);
4223 iemVmxVmcsSetExitQual(pVCpu, offApic);
4224 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4225}
4226
4227
4228/**
4229 * VMX VM-exit handler for virtualized-EOIs.
4230 *
4231 * @param pVCpu The cross context virtual CPU structure.
4232 */
4233IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4234{
4235 iemVmxVmcsSetExitQual(pVCpu, uVector);
4236 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4237}
4238
4239
4240/**
4241 * Sets virtual-APIC write emulation as pending.
4242 *
4243 * @param pVCpu The cross context virtual CPU structure.
4244 * @param offApic The offset in the virtual-APIC page that was written.
4245 */
4246DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4247{
4248 Assert(offApic < XAPIC_OFF_END + 4);
4249
4250 /*
4251 * Record the currently updated APIC offset, as we need this later for figuring
4252 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4253 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4254 */
4255 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4256
4257 /*
4258 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4259 * virtualization or APIC-write emulation).
4260 */
4261 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4262 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4263}
4264
4265
4266/**
4267 * Clears any pending virtual-APIC write emulation.
4268 *
4269 * @returns The virtual-APIC offset that was written before clearing it.
4270 * @param pVCpu The cross context virtual CPU structure.
4271 */
4272DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4273{
4274 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4275 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4276 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4277 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4278 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4279 return offVirtApicWrite;
4280}
4281
4282
4283/**
4284 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4285 *
4286 * @returns The register from the virtual-APIC page.
4287 * @param pVCpu The cross context virtual CPU structure.
4288 * @param offReg The offset of the register being read.
4289 */
4290IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4291{
4292 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4293 Assert(pVmcs);
4294
4295 uint32_t uReg;
4296 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4297 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4298 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4299 if (RT_FAILURE(rc))
4300 {
4301 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4302 GCPhysVirtApic));
4303 uReg = 0;
4304 }
4305 return uReg;
4306}
4307
4308
4309/**
4310 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4311 *
4312 * @returns The register from the virtual-APIC page.
4313 * @param pVCpu The cross context virtual CPU structure.
4314 * @param offReg The offset of the register being read.
4315 */
4316IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4317{
4318 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4319 Assert(pVmcs);
4320
4321 uint64_t uReg;
4322 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4323 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4324 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4325 if (RT_FAILURE(rc))
4326 {
4327 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4328 GCPhysVirtApic));
4329 uReg = 0;
4330 }
4331 return uReg;
4332}
4333
4334
4335/**
4336 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4337 *
4338 * @param pVCpu The cross context virtual CPU structure.
4339 * @param offReg The offset of the register being written.
4340 * @param uReg The register value to write.
4341 */
4342IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4343{
4344 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4345 Assert(pVmcs);
4346 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4347 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4348 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4349 if (RT_FAILURE(rc))
4350 {
4351 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4352 GCPhysVirtApic));
4353 }
4354}
4355
4356
4357/**
4358 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4359 *
4360 * @param pVCpu The cross context virtual CPU structure.
4361 * @param offReg The offset of the register being written.
4362 * @param uReg The register value to write.
4363 */
4364IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4365{
4366 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4367 Assert(pVmcs);
4368 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4369 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4370 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4371 if (RT_FAILURE(rc))
4372 {
4373 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4374 GCPhysVirtApic));
4375 }
4376}
4377
4378
4379/**
4380 * Sets the vector in a virtual-APIC 256-bit sparse register.
4381 *
4382 * @param pVCpu The cross context virtual CPU structure.
4383 * @param offReg The offset of the 256-bit spare register.
4384 * @param uVector The vector to set.
4385 *
4386 * @remarks This is based on our APIC device code.
4387 */
4388IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4389{
4390 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4391 Assert(pVmcs);
4392 uint32_t uReg;
4393 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4394 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4395 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4396 if (RT_SUCCESS(rc))
4397 {
4398 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4399 uReg |= RT_BIT(idxVectorBit);
4400 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4401 if (RT_FAILURE(rc))
4402 {
4403 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4404 uVector, offReg, GCPhysVirtApic));
4405 }
4406 }
4407 else
4408 {
4409 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4410 uVector, offReg, GCPhysVirtApic));
4411 }
4412}
4413
4414
4415/**
4416 * Clears the vector in a virtual-APIC 256-bit sparse register.
4417 *
4418 * @param pVCpu The cross context virtual CPU structure.
4419 * @param offReg The offset of the 256-bit spare register.
4420 * @param uVector The vector to clear.
4421 *
4422 * @remarks This is based on our APIC device code.
4423 */
4424IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4425{
4426 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4427 Assert(pVmcs);
4428 uint32_t uReg;
4429 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4430 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4431 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4432 if (RT_SUCCESS(rc))
4433 {
4434 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4435 uReg &= ~RT_BIT(idxVectorBit);
4436 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4437 if (RT_FAILURE(rc))
4438 {
4439 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4440 uVector, offReg, GCPhysVirtApic));
4441 }
4442 }
4443 else
4444 {
4445 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4446 uVector, offReg, GCPhysVirtApic));
4447 }
4448}
4449
4450
4451/**
4452 * Checks if a memory access to the APIC-access page must causes an APIC-access
4453 * VM-exit.
4454 *
4455 * @param pVCpu The cross context virtual CPU structure.
4456 * @param offAccess The offset of the register being accessed.
4457 * @param cbAccess The size of the access in bytes.
4458 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4459 * IEM_ACCESS_TYPE_WRITE).
4460 *
4461 * @remarks This must not be used for MSR-based APIC-access page accesses!
4462 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4463 */
4464IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4465{
4466 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4467 Assert(pVmcs);
4468 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4469
4470 /*
4471 * We must cause a VM-exit if any of the following are true:
4472 * - TPR shadowing isn't active.
4473 * - The access size exceeds 32-bits.
4474 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4475 *
4476 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4477 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4478 */
4479 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4480 || cbAccess > sizeof(uint32_t)
4481 || ((offAccess + cbAccess - 1) & 0xc)
4482 || offAccess >= XAPIC_OFF_END + 4)
4483 return true;
4484
4485 /*
4486 * If the access is part of an operation where we have already
4487 * virtualized a virtual-APIC write, we must cause a VM-exit.
4488 */
4489 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4490 return true;
4491
4492 /*
4493 * Check write accesses to the APIC-access page that cause VM-exits.
4494 */
4495 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4496 {
4497 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4498 {
4499 /*
4500 * With APIC-register virtualization, a write access to any of the
4501 * following registers are virtualized. Accessing any other register
4502 * causes a VM-exit.
4503 */
4504 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4505 switch (offAlignedAccess)
4506 {
4507 case XAPIC_OFF_ID:
4508 case XAPIC_OFF_TPR:
4509 case XAPIC_OFF_EOI:
4510 case XAPIC_OFF_LDR:
4511 case XAPIC_OFF_DFR:
4512 case XAPIC_OFF_SVR:
4513 case XAPIC_OFF_ESR:
4514 case XAPIC_OFF_ICR_LO:
4515 case XAPIC_OFF_ICR_HI:
4516 case XAPIC_OFF_LVT_TIMER:
4517 case XAPIC_OFF_LVT_THERMAL:
4518 case XAPIC_OFF_LVT_PERF:
4519 case XAPIC_OFF_LVT_LINT0:
4520 case XAPIC_OFF_LVT_LINT1:
4521 case XAPIC_OFF_LVT_ERROR:
4522 case XAPIC_OFF_TIMER_ICR:
4523 case XAPIC_OFF_TIMER_DCR:
4524 break;
4525 default:
4526 return true;
4527 }
4528 }
4529 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4530 {
4531 /*
4532 * With virtual-interrupt delivery, a write access to any of the
4533 * following registers are virtualized. Accessing any other register
4534 * causes a VM-exit.
4535 *
4536 * Note! The specification does not allow writing to offsets in-between
4537 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4538 */
4539 switch (offAccess)
4540 {
4541 case XAPIC_OFF_TPR:
4542 case XAPIC_OFF_EOI:
4543 case XAPIC_OFF_ICR_LO:
4544 break;
4545 default:
4546 return true;
4547 }
4548 }
4549 else
4550 {
4551 /*
4552 * Without APIC-register virtualization or virtual-interrupt delivery,
4553 * only TPR accesses are virtualized.
4554 */
4555 if (offAccess == XAPIC_OFF_TPR)
4556 { /* likely */ }
4557 else
4558 return true;
4559 }
4560 }
4561 else
4562 {
4563 /*
4564 * Check read accesses to the APIC-access page that cause VM-exits.
4565 */
4566 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4567 {
4568 /*
4569 * With APIC-register virtualization, a read access to any of the
4570 * following registers are virtualized. Accessing any other register
4571 * causes a VM-exit.
4572 */
4573 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4574 switch (offAlignedAccess)
4575 {
4576 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4577 case XAPIC_OFF_ID:
4578 case XAPIC_OFF_VERSION:
4579 case XAPIC_OFF_TPR:
4580 case XAPIC_OFF_EOI:
4581 case XAPIC_OFF_LDR:
4582 case XAPIC_OFF_DFR:
4583 case XAPIC_OFF_SVR:
4584 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4585 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4586 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4587 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4588 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4589 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4590 case XAPIC_OFF_ESR:
4591 case XAPIC_OFF_ICR_LO:
4592 case XAPIC_OFF_ICR_HI:
4593 case XAPIC_OFF_LVT_TIMER:
4594 case XAPIC_OFF_LVT_THERMAL:
4595 case XAPIC_OFF_LVT_PERF:
4596 case XAPIC_OFF_LVT_LINT0:
4597 case XAPIC_OFF_LVT_LINT1:
4598 case XAPIC_OFF_LVT_ERROR:
4599 case XAPIC_OFF_TIMER_ICR:
4600 case XAPIC_OFF_TIMER_DCR:
4601 break;
4602 default:
4603 return true;
4604 }
4605 }
4606 else
4607 {
4608 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4609 if (offAccess == XAPIC_OFF_TPR)
4610 { /* likely */ }
4611 else
4612 return true;
4613 }
4614 }
4615
4616 /* The APIC-access is virtualized, does not cause a VM-exit. */
4617 return false;
4618}
4619
4620
4621/**
4622 * Virtualizes a memory-based APIC-access where the address is not used to access
4623 * memory.
4624 *
4625 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4626 * page-faults but do not use the address to access memory.
4627 *
4628 * @param pVCpu The cross context virtual CPU structure.
4629 * @param pGCPhysAccess Pointer to the guest-physical address used.
4630 */
4631IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4632{
4633 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4634 Assert(pVmcs);
4635 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4636 Assert(pGCPhysAccess);
4637
4638 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4639 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4640 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4641
4642 if (GCPhysAccess == GCPhysApic)
4643 {
4644 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4645 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4646 uint16_t const cbAccess = 1;
4647 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4648 if (fIntercept)
4649 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4650
4651 *pGCPhysAccess = GCPhysApic | offAccess;
4652 return VINF_VMX_MODIFIES_BEHAVIOR;
4653 }
4654
4655 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4656}
4657
4658
4659/**
4660 * Virtualizes a memory-based APIC-access.
4661 *
4662 * @returns VBox strict status code.
4663 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4664 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4665 *
4666 * @param pVCpu The cross context virtual CPU structure.
4667 * @param offAccess The offset of the register being accessed (within the
4668 * APIC-access page).
4669 * @param cbAccess The size of the access in bytes.
4670 * @param pvData Pointer to the data being written or where to store the data
4671 * being read.
4672 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4673 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4674 */
4675IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4676 uint32_t fAccess)
4677{
4678 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4679 Assert(pVmcs);
4680 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4681 Assert(pvData);
4682 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4683 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4684 || (fAccess & IEM_ACCESS_INSTRUCTION));
4685
4686 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4687 if (fIntercept)
4688 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4689
4690 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4691 {
4692 /*
4693 * A write access to the APIC-access page that is virtualized (rather than
4694 * causing a VM-exit) writes data to the virtual-APIC page.
4695 */
4696 uint32_t const u32Data = *(uint32_t *)pvData;
4697 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4698
4699 /*
4700 * Record the currently updated APIC offset, as we need this later for figuring
4701 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4702 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4703 *
4704 * After completion of the current operation, we need to perform TPR virtualization,
4705 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4706 *
4707 * The current operation may be a REP-prefixed string instruction, execution of any
4708 * other instruction, or delivery of an event through the IDT.
4709 *
4710 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4711 * performed now but later after completion of the current operation.
4712 *
4713 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4714 */
4715 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4716 }
4717 else
4718 {
4719 /*
4720 * A read access from the APIC-access page that is virtualized (rather than
4721 * causing a VM-exit) returns data from the virtual-APIC page.
4722 *
4723 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4724 */
4725 Assert(cbAccess <= 4);
4726 Assert(offAccess < XAPIC_OFF_END + 4);
4727 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4728
4729 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4730 u32Data &= s_auAccessSizeMasks[cbAccess];
4731 *(uint32_t *)pvData = u32Data;
4732 }
4733
4734 return VINF_VMX_MODIFIES_BEHAVIOR;
4735}
4736
4737
4738/**
4739 * Virtualizes an MSR-based APIC read access.
4740 *
4741 * @returns VBox strict status code.
4742 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4743 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4744 * handled by the x2APIC device.
4745 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4746 * not within the range of valid MSRs, caller must raise \#GP(0).
4747 * @param pVCpu The cross context virtual CPU structure.
4748 * @param idMsr The x2APIC MSR being read.
4749 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4750 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4751 */
4752IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4753{
4754 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4755 Assert(pVmcs);
4756 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4757 Assert(pu64Value);
4758
4759 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4760 {
4761 /*
4762 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4763 * what the end of the valid x2APIC MSR range is. Hence the use of different
4764 * macros here.
4765 *
4766 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4767 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4768 */
4769 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4770 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4771 {
4772 uint16_t const offReg = (idMsr & 0xff) << 4;
4773 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4774 *pu64Value = u64Value;
4775 return VINF_VMX_MODIFIES_BEHAVIOR;
4776 }
4777 return VERR_OUT_OF_RANGE;
4778 }
4779
4780 if (idMsr == MSR_IA32_X2APIC_TPR)
4781 {
4782 uint16_t const offReg = (idMsr & 0xff) << 4;
4783 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4784 *pu64Value = u64Value;
4785 return VINF_VMX_MODIFIES_BEHAVIOR;
4786 }
4787
4788 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4789}
4790
4791
4792/**
4793 * Virtualizes an MSR-based APIC write access.
4794 *
4795 * @returns VBox strict status code.
4796 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4797 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4798 * not within the range of valid MSRs, caller must raise \#GP(0).
4799 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4800 *
4801 * @param pVCpu The cross context virtual CPU structure.
4802 * @param idMsr The x2APIC MSR being written.
4803 * @param u64Value The value of the x2APIC MSR being written.
4804 */
4805IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4806{
4807 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4808 Assert(pVmcs);
4809
4810 /*
4811 * Check if the access is to be virtualized.
4812 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4813 */
4814 if ( idMsr == MSR_IA32_X2APIC_TPR
4815 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4816 && ( idMsr == MSR_IA32_X2APIC_EOI
4817 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4818 {
4819 /* Validate the MSR write depending on the register. */
4820 switch (idMsr)
4821 {
4822 case MSR_IA32_X2APIC_TPR:
4823 case MSR_IA32_X2APIC_SELF_IPI:
4824 {
4825 if (u64Value & UINT64_C(0xffffffffffffff00))
4826 return VERR_OUT_OF_RANGE;
4827 break;
4828 }
4829 case MSR_IA32_X2APIC_EOI:
4830 {
4831 if (u64Value != 0)
4832 return VERR_OUT_OF_RANGE;
4833 break;
4834 }
4835 }
4836
4837 /* Write the MSR to the virtual-APIC page. */
4838 uint16_t const offReg = (idMsr & 0xff) << 4;
4839 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4840
4841 /*
4842 * Record the currently updated APIC offset, as we need this later for figuring
4843 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4844 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4845 */
4846 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4847
4848 return VINF_VMX_MODIFIES_BEHAVIOR;
4849 }
4850
4851 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4852}
4853
4854
4855/**
4856 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4857 *
4858 * @returns VBox status code.
4859 * @retval VINF_SUCCESS when the highest set bit is found.
4860 * @retval VERR_NOT_FOUND when no bit is set.
4861 *
4862 * @param pVCpu The cross context virtual CPU structure.
4863 * @param offReg The offset of the APIC 256-bit sparse register.
4864 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4865 * set in the register. Only valid when VINF_SUCCESS is
4866 * returned.
4867 *
4868 * @remarks The format of the 256-bit sparse register here mirrors that found in
4869 * real APIC hardware.
4870 */
4871static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4872{
4873 Assert(offReg < XAPIC_OFF_END + 4);
4874 Assert(pidxHighestBit);
4875 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4876
4877 /*
4878 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4879 * However, in each fragment only the first 4 bytes are used.
4880 */
4881 uint8_t const cFrags = 8;
4882 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4883 {
4884 uint16_t const offFrag = iFrag * 16;
4885 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4886 if (!u32Frag)
4887 continue;
4888
4889 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4890 Assert(idxHighestBit > 0);
4891 --idxHighestBit;
4892 Assert(idxHighestBit <= UINT8_MAX);
4893 *pidxHighestBit = idxHighestBit;
4894 return VINF_SUCCESS;
4895 }
4896 return VERR_NOT_FOUND;
4897}
4898
4899
4900/**
4901 * Evaluates pending virtual interrupts.
4902 *
4903 * @param pVCpu The cross context virtual CPU structure.
4904 */
4905IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4906{
4907 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4908 Assert(pVmcs);
4909 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4910
4911 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4912 {
4913 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4914 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4915
4916 if ((uRvi >> 4) > (uPpr >> 4))
4917 {
4918 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4919 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4920 }
4921 else
4922 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4923 }
4924}
4925
4926
4927/**
4928 * Performs PPR virtualization.
4929 *
4930 * @returns VBox strict status code.
4931 * @param pVCpu The cross context virtual CPU structure.
4932 */
4933IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4934{
4935 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4936 Assert(pVmcs);
4937 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4938 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4939
4940 /*
4941 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4942 * or EOI-virtualization.
4943 *
4944 * See Intel spec. 29.1.3 "PPR Virtualization".
4945 */
4946 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4947 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4948
4949 uint32_t uPpr;
4950 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4951 uPpr = uTpr & 0xff;
4952 else
4953 uPpr = uSvi & 0xf0;
4954
4955 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4956 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4957}
4958
4959
4960/**
4961 * Performs VMX TPR virtualization.
4962 *
4963 * @returns VBox strict status code.
4964 * @param pVCpu The cross context virtual CPU structure.
4965 */
4966IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4967{
4968 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4969 Assert(pVmcs);
4970 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4971
4972 /*
4973 * We should have already performed the virtual-APIC write to the TPR offset
4974 * in the virtual-APIC page. We now perform TPR virtualization.
4975 *
4976 * See Intel spec. 29.1.2 "TPR Virtualization".
4977 */
4978 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4979 {
4980 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4981 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4982
4983 /*
4984 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4985 * See Intel spec. 29.1.2 "TPR Virtualization".
4986 */
4987 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4988 {
4989 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4990 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4991 }
4992 }
4993 else
4994 {
4995 iemVmxPprVirtualization(pVCpu);
4996 iemVmxEvalPendingVirtIntrs(pVCpu);
4997 }
4998
4999 return VINF_SUCCESS;
5000}
5001
5002
5003/**
5004 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
5005 * not.
5006 *
5007 * @returns @c true if the EOI write is intercepted, @c false otherwise.
5008 * @param pVCpu The cross context virtual CPU structure.
5009 * @param uVector The interrupt that was acknowledged using an EOI.
5010 */
5011IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
5012{
5013 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5014 Assert(pVmcs);
5015 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5016
5017 if (uVector < 64)
5018 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
5019 if (uVector < 128)
5020 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
5021 if (uVector < 192)
5022 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
5023 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
5024}
5025
5026
5027/**
5028 * Performs EOI virtualization.
5029 *
5030 * @returns VBox strict status code.
5031 * @param pVCpu The cross context virtual CPU structure.
5032 */
5033IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
5034{
5035 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5036 Assert(pVmcs);
5037 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5038
5039 /*
5040 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
5041 * and get the next guest-interrupt that's in-service (if any).
5042 *
5043 * See Intel spec. 29.1.4 "EOI Virtualization".
5044 */
5045 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5046 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5047 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5048
5049 uint8_t uVector = uSvi;
5050 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
5051
5052 uVector = 0;
5053 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5054
5055 if (uVector)
5056 Log2(("eoi_virt: next interrupt %#x\n", uVector));
5057 else
5058 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5059
5060 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5061 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5062
5063 iemVmxPprVirtualization(pVCpu);
5064 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5065 return iemVmxVmexitVirtEoi(pVCpu, uVector);
5066 iemVmxEvalPendingVirtIntrs(pVCpu);
5067 return VINF_SUCCESS;
5068}
5069
5070
5071/**
5072 * Performs self-IPI virtualization.
5073 *
5074 * @returns VBox strict status code.
5075 * @param pVCpu The cross context virtual CPU structure.
5076 */
5077IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5078{
5079 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5080 Assert(pVmcs);
5081 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5082
5083 /*
5084 * We should have already performed the virtual-APIC write to the self-IPI offset
5085 * in the virtual-APIC page. We now perform self-IPI virtualization.
5086 *
5087 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5088 */
5089 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5090 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5091 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5092 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5093 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5094 if (uVector > uRvi)
5095 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5096 iemVmxEvalPendingVirtIntrs(pVCpu);
5097 return VINF_SUCCESS;
5098}
5099
5100
5101/**
5102 * Performs VMX APIC-write emulation.
5103 *
5104 * @returns VBox strict status code.
5105 * @param pVCpu The cross context virtual CPU structure.
5106 */
5107IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5108{
5109 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5110 Assert(pVmcs);
5111
5112 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5113 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5114
5115 /*
5116 * Perform APIC-write emulation based on the virtual-APIC register written.
5117 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5118 */
5119 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5120 VBOXSTRICTRC rcStrict;
5121 switch (offApicWrite)
5122 {
5123 case XAPIC_OFF_TPR:
5124 {
5125 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5126 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5127 uTpr &= UINT32_C(0x000000ff);
5128 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5129 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5130 rcStrict = iemVmxTprVirtualization(pVCpu);
5131 break;
5132 }
5133
5134 case XAPIC_OFF_EOI:
5135 {
5136 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5137 {
5138 /* Clear VEOI and perform EOI virtualization. */
5139 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5140 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5141 rcStrict = iemVmxEoiVirtualization(pVCpu);
5142 }
5143 else
5144 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5145 break;
5146 }
5147
5148 case XAPIC_OFF_ICR_LO:
5149 {
5150 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5151 {
5152 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5153 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5154 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5155 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5156 if ( !(uIcrLo & fIcrLoMb0)
5157 && (uIcrLo & fIcrLoMb1))
5158 {
5159 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5160 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5161 }
5162 else
5163 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5164 }
5165 else
5166 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5167 break;
5168 }
5169
5170 case XAPIC_OFF_ICR_HI:
5171 {
5172 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5173 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5174 uIcrHi &= UINT32_C(0xff000000);
5175 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5176 rcStrict = VINF_SUCCESS;
5177 break;
5178 }
5179
5180 default:
5181 {
5182 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5183 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5184 break;
5185 }
5186 }
5187
5188 return rcStrict;
5189}
5190
5191
5192/**
5193 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5194 *
5195 * @param pVCpu The cross context virtual CPU structure.
5196 * @param pszInstr The VMX instruction name (for logging purposes).
5197 */
5198IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5199{
5200 /*
5201 * Guest Control Registers, Debug Registers, and MSRs.
5202 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5203 */
5204 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5205 const char *const pszFailure = "VM-exit";
5206 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5207
5208 /* CR0 reserved bits. */
5209 {
5210 /* CR0 MB1 bits. */
5211 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5212 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5213 if (fUnrestrictedGuest)
5214 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5215 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5216 { /* likely */ }
5217 else
5218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5219
5220 /* CR0 MBZ bits. */
5221 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5222 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5226
5227 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5228 if ( !fUnrestrictedGuest
5229 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5230 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5232 }
5233
5234 /* CR4 reserved bits. */
5235 {
5236 /* CR4 MB1 bits. */
5237 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5238 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5239 { /* likely */ }
5240 else
5241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5242
5243 /* CR4 MBZ bits. */
5244 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5245 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5249 }
5250
5251 /* DEBUGCTL MSR. */
5252 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5253 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5254 { /* likely */ }
5255 else
5256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5257
5258 /* 64-bit CPU checks. */
5259 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5260 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5261 {
5262 if (fGstInLongMode)
5263 {
5264 /* PAE must be set. */
5265 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5266 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5267 { /* likely */ }
5268 else
5269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5270 }
5271 else
5272 {
5273 /* PCIDE should not be set. */
5274 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5275 { /* likely */ }
5276 else
5277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5278 }
5279
5280 /* CR3. */
5281 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5282 { /* likely */ }
5283 else
5284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5285
5286 /* DR7. */
5287 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5288 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5292
5293 /* SYSENTER ESP and SYSENTER EIP. */
5294 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5295 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5296 { /* likely */ }
5297 else
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5299 }
5300
5301 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5302 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5303
5304 /* PAT MSR. */
5305 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5306 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5307 { /* likely */ }
5308 else
5309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5310
5311 /* EFER MSR. */
5312 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5313 {
5314 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5315 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5316 { /* likely */ }
5317 else
5318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5319
5320 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5321 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5322 if ( fGstLma == fGstInLongMode
5323 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5324 || fGstLma == fGstLme))
5325 { /* likely */ }
5326 else
5327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5328 }
5329
5330 /* We don't support IA32_BNDCFGS MSR yet. */
5331 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5332
5333 NOREF(pszInstr);
5334 NOREF(pszFailure);
5335 return VINF_SUCCESS;
5336}
5337
5338
5339/**
5340 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5341 *
5342 * @param pVCpu The cross context virtual CPU structure.
5343 * @param pszInstr The VMX instruction name (for logging purposes).
5344 */
5345IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5346{
5347 /*
5348 * Segment registers.
5349 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5350 */
5351 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5352 const char *const pszFailure = "VM-exit";
5353 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5354 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5355 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5356
5357 /* Selectors. */
5358 if ( !fGstInV86Mode
5359 && !fUnrestrictedGuest
5360 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5362
5363 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5364 {
5365 CPUMSELREG SelReg;
5366 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5367 if (RT_LIKELY(rc == VINF_SUCCESS))
5368 { /* likely */ }
5369 else
5370 return rc;
5371
5372 /*
5373 * Virtual-8086 mode checks.
5374 */
5375 if (fGstInV86Mode)
5376 {
5377 /* Base address. */
5378 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5379 { /* likely */ }
5380 else
5381 {
5382 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5384 }
5385
5386 /* Limit. */
5387 if (SelReg.u32Limit == 0xffff)
5388 { /* likely */ }
5389 else
5390 {
5391 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5393 }
5394
5395 /* Attribute. */
5396 if (SelReg.Attr.u == 0xf3)
5397 { /* likely */ }
5398 else
5399 {
5400 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5402 }
5403
5404 /* We're done; move to checking the next segment. */
5405 continue;
5406 }
5407
5408 /* Checks done by 64-bit CPUs. */
5409 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5410 {
5411 /* Base address. */
5412 if ( iSegReg == X86_SREG_FS
5413 || iSegReg == X86_SREG_GS)
5414 {
5415 if (X86_IS_CANONICAL(SelReg.u64Base))
5416 { /* likely */ }
5417 else
5418 {
5419 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5421 }
5422 }
5423 else if (iSegReg == X86_SREG_CS)
5424 {
5425 if (!RT_HI_U32(SelReg.u64Base))
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5429 }
5430 else
5431 {
5432 if ( SelReg.Attr.n.u1Unusable
5433 || !RT_HI_U32(SelReg.u64Base))
5434 { /* likely */ }
5435 else
5436 {
5437 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5439 }
5440 }
5441 }
5442
5443 /*
5444 * Checks outside Virtual-8086 mode.
5445 */
5446 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5447 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5448 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5449 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5450 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5451 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5452 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5453 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5454
5455 /* Code or usable segment. */
5456 if ( iSegReg == X86_SREG_CS
5457 || fUsable)
5458 {
5459 /* Reserved bits (bits 31:17 and bits 11:8). */
5460 if (!(SelReg.Attr.u & 0xfffe0f00))
5461 { /* likely */ }
5462 else
5463 {
5464 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5466 }
5467
5468 /* Descriptor type. */
5469 if (fCodeDataSeg)
5470 { /* likely */ }
5471 else
5472 {
5473 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5475 }
5476
5477 /* Present. */
5478 if (fPresent)
5479 { /* likely */ }
5480 else
5481 {
5482 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5484 }
5485
5486 /* Granularity. */
5487 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5488 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5489 { /* likely */ }
5490 else
5491 {
5492 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5494 }
5495 }
5496
5497 if (iSegReg == X86_SREG_CS)
5498 {
5499 /* Segment Type and DPL. */
5500 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5501 && fUnrestrictedGuest)
5502 {
5503 if (uDpl == 0)
5504 { /* likely */ }
5505 else
5506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5507 }
5508 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5509 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5510 {
5511 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5512 if (uDpl == AttrSs.n.u2Dpl)
5513 { /* likely */ }
5514 else
5515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5516 }
5517 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5518 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5519 {
5520 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5521 if (uDpl <= AttrSs.n.u2Dpl)
5522 { /* likely */ }
5523 else
5524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5525 }
5526 else
5527 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5528
5529 /* Def/Big. */
5530 if ( fGstInLongMode
5531 && fSegLong)
5532 {
5533 if (uDefBig == 0)
5534 { /* likely */ }
5535 else
5536 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5537 }
5538 }
5539 else if (iSegReg == X86_SREG_SS)
5540 {
5541 /* Segment Type. */
5542 if ( !fUsable
5543 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5544 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5545 { /* likely */ }
5546 else
5547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5548
5549 /* DPL. */
5550 if (!fUnrestrictedGuest)
5551 {
5552 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5553 { /* likely */ }
5554 else
5555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5556 }
5557 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5558 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5559 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5560 {
5561 if (uDpl == 0)
5562 { /* likely */ }
5563 else
5564 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5565 }
5566 }
5567 else
5568 {
5569 /* DS, ES, FS, GS. */
5570 if (fUsable)
5571 {
5572 /* Segment type. */
5573 if (uSegType & X86_SEL_TYPE_ACCESSED)
5574 { /* likely */ }
5575 else
5576 {
5577 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5579 }
5580
5581 if ( !(uSegType & X86_SEL_TYPE_CODE)
5582 || (uSegType & X86_SEL_TYPE_READ))
5583 { /* likely */ }
5584 else
5585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5586
5587 /* DPL. */
5588 if ( !fUnrestrictedGuest
5589 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5590 {
5591 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5592 { /* likely */ }
5593 else
5594 {
5595 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5596 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5597 }
5598 }
5599 }
5600 }
5601 }
5602
5603 /*
5604 * LDTR.
5605 */
5606 {
5607 CPUMSELREG Ldtr;
5608 Ldtr.Sel = pVmcs->GuestLdtr;
5609 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5610 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5611 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5612
5613 if (!Ldtr.Attr.n.u1Unusable)
5614 {
5615 /* Selector. */
5616 if (!(Ldtr.Sel & X86_SEL_LDT))
5617 { /* likely */ }
5618 else
5619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5620
5621 /* Base. */
5622 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5623 {
5624 if (X86_IS_CANONICAL(Ldtr.u64Base))
5625 { /* likely */ }
5626 else
5627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5628 }
5629
5630 /* Attributes. */
5631 /* Reserved bits (bits 31:17 and bits 11:8). */
5632 if (!(Ldtr.Attr.u & 0xfffe0f00))
5633 { /* likely */ }
5634 else
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5636
5637 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5638 { /* likely */ }
5639 else
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5641
5642 if (!Ldtr.Attr.n.u1DescType)
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5646
5647 if (Ldtr.Attr.n.u1Present)
5648 { /* likely */ }
5649 else
5650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5651
5652 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5653 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5654 { /* likely */ }
5655 else
5656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5657 }
5658 }
5659
5660 /*
5661 * TR.
5662 */
5663 {
5664 CPUMSELREG Tr;
5665 Tr.Sel = pVmcs->GuestTr;
5666 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5667 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5668 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5669
5670 /* Selector. */
5671 if (!(Tr.Sel & X86_SEL_LDT))
5672 { /* likely */ }
5673 else
5674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5675
5676 /* Base. */
5677 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5678 {
5679 if (X86_IS_CANONICAL(Tr.u64Base))
5680 { /* likely */ }
5681 else
5682 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5683 }
5684
5685 /* Attributes. */
5686 /* Reserved bits (bits 31:17 and bits 11:8). */
5687 if (!(Tr.Attr.u & 0xfffe0f00))
5688 { /* likely */ }
5689 else
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5691
5692 if (!Tr.Attr.n.u1Unusable)
5693 { /* likely */ }
5694 else
5695 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5696
5697 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5698 || ( !fGstInLongMode
5699 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5700 { /* likely */ }
5701 else
5702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5703
5704 if (!Tr.Attr.n.u1DescType)
5705 { /* likely */ }
5706 else
5707 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5708
5709 if (Tr.Attr.n.u1Present)
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5713
5714 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5715 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5716 { /* likely */ }
5717 else
5718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5719 }
5720
5721 NOREF(pszInstr);
5722 NOREF(pszFailure);
5723 return VINF_SUCCESS;
5724}
5725
5726
5727/**
5728 * Checks guest GDTR and IDTR as part of VM-entry.
5729 *
5730 * @param pVCpu The cross context virtual CPU structure.
5731 * @param pszInstr The VMX instruction name (for logging purposes).
5732 */
5733IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5734{
5735 /*
5736 * GDTR and IDTR.
5737 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5738 */
5739 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5740 const char *const pszFailure = "VM-exit";
5741
5742 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5743 {
5744 /* Base. */
5745 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5749
5750 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5751 { /* likely */ }
5752 else
5753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5754 }
5755
5756 /* Limit. */
5757 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5758 { /* likely */ }
5759 else
5760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5761
5762 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5763 { /* likely */ }
5764 else
5765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5766
5767 NOREF(pszInstr);
5768 NOREF(pszFailure);
5769 return VINF_SUCCESS;
5770}
5771
5772
5773/**
5774 * Checks guest RIP and RFLAGS as part of VM-entry.
5775 *
5776 * @param pVCpu The cross context virtual CPU structure.
5777 * @param pszInstr The VMX instruction name (for logging purposes).
5778 */
5779IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5780{
5781 /*
5782 * RIP and RFLAGS.
5783 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5784 */
5785 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5786 const char *const pszFailure = "VM-exit";
5787 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5788
5789 /* RIP. */
5790 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5791 {
5792 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5793 if ( !fGstInLongMode
5794 || !AttrCs.n.u1Long)
5795 {
5796 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5797 { /* likely */ }
5798 else
5799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5800 }
5801
5802 if ( fGstInLongMode
5803 && AttrCs.n.u1Long)
5804 {
5805 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5806 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5807 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5808 { /* likely */ }
5809 else
5810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5811 }
5812 }
5813
5814 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5815 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5816 : pVmcs->u64GuestRFlags.s.Lo;
5817 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5818 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5819 { /* likely */ }
5820 else
5821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5822
5823 if ( fGstInLongMode
5824 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5825 {
5826 if (!(uGuestRFlags & X86_EFL_VM))
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5830 }
5831
5832 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5833 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5834 {
5835 if (uGuestRFlags & X86_EFL_IF)
5836 { /* likely */ }
5837 else
5838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5839 }
5840
5841 NOREF(pszInstr);
5842 NOREF(pszFailure);
5843 return VINF_SUCCESS;
5844}
5845
5846
5847/**
5848 * Checks guest non-register state as part of VM-entry.
5849 *
5850 * @param pVCpu The cross context virtual CPU structure.
5851 * @param pszInstr The VMX instruction name (for logging purposes).
5852 */
5853IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5854{
5855 /*
5856 * Guest non-register state.
5857 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5858 */
5859 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5860 const char *const pszFailure = "VM-exit";
5861
5862 /*
5863 * Activity state.
5864 */
5865 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5866 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5867 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5868 { /* likely */ }
5869 else
5870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5871
5872 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5873 if ( !AttrSs.n.u2Dpl
5874 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5875 { /* likely */ }
5876 else
5877 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5878
5879 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5880 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5881 {
5882 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5886 }
5887
5888 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5889 {
5890 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5891 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5892 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5893 switch (pVmcs->u32GuestActivityState)
5894 {
5895 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5896 {
5897 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5898 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5899 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5900 && ( uVector == X86_XCPT_DB
5901 || uVector == X86_XCPT_MC))
5902 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5903 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5904 { /* likely */ }
5905 else
5906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5907 break;
5908 }
5909
5910 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5911 {
5912 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5913 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5914 && uVector == X86_XCPT_MC))
5915 { /* likely */ }
5916 else
5917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5918 break;
5919 }
5920
5921 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5922 default:
5923 break;
5924 }
5925 }
5926
5927 /*
5928 * Interruptibility state.
5929 */
5930 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5931 { /* likely */ }
5932 else
5933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5934
5935 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5936 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5937 { /* likely */ }
5938 else
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5940
5941 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5942 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5943 { /* likely */ }
5944 else
5945 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5946
5947 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5948 {
5949 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5950 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5951 {
5952 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5956 }
5957 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5958 {
5959 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5960 { /* likely */ }
5961 else
5962 {
5963 /*
5964 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5965 * We update the VM-exit qualification only when blocking-by-STI is set
5966 * without blocking-by-MovSS being set. Although in practise it does not
5967 * make much difference since the order of checks are implementation defined.
5968 */
5969 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5970 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5972 }
5973
5974 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5975 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5976 { /* likely */ }
5977 else
5978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5979 }
5980 }
5981
5982 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5983 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5984 { /* likely */ }
5985 else
5986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5987
5988 /* We don't support SGX yet. So enclave-interruption must not be set. */
5989 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5990 { /* likely */ }
5991 else
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5993
5994 /*
5995 * Pending debug exceptions.
5996 */
5997 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5998 ? pVmcs->u64GuestPendingDbgXcpt.u
5999 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
6000 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
6001 { /* likely */ }
6002 else
6003 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
6004
6005 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
6006 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
6007 {
6008 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
6009 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
6010 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
6011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
6012
6013 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
6014 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
6015 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
6016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
6017 }
6018
6019 /* We don't support RTM (Real-time Transactional Memory) yet. */
6020 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
6021 { /* likely */ }
6022 else
6023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
6024
6025 /*
6026 * VMCS link pointer.
6027 */
6028 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6029 {
6030 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6031 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
6032 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
6033 { /* likely */ }
6034 else
6035 {
6036 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
6038 }
6039
6040 /* Validate the address. */
6041 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
6042 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6043 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
6044 { /* likely */ }
6045 else
6046 {
6047 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6049 }
6050
6051 /* Read the VMCS-link pointer from guest memory. */
6052 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6053 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6054 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
6055 if (RT_SUCCESS(rc))
6056 { /* likely */ }
6057 else
6058 {
6059 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6061 }
6062
6063 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6064 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6065 { /* likely */ }
6066 else
6067 {
6068 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6070 }
6071
6072 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6073 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6074 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6075 { /* likely */ }
6076 else
6077 {
6078 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6080 }
6081
6082 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6083 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6084 }
6085
6086 NOREF(pszInstr);
6087 NOREF(pszFailure);
6088 return VINF_SUCCESS;
6089}
6090
6091
6092/**
6093 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6094 * VM-entry.
6095 *
6096 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6097 * @param pVCpu The cross context virtual CPU structure.
6098 * @param pszInstr The VMX instruction name (for logging purposes).
6099 * @param pVmcs Pointer to the virtual VMCS.
6100 */
6101IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6102{
6103 /*
6104 * Check PDPTEs.
6105 * See Intel spec. 4.4.1 "PDPTE Registers".
6106 */
6107 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6108 const char *const pszFailure = "VM-exit";
6109
6110 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6111 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6112 if (RT_SUCCESS(rc))
6113 {
6114 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6115 {
6116 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6117 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6118 { /* likely */ }
6119 else
6120 {
6121 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6122 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6124 }
6125 }
6126 }
6127 else
6128 {
6129 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6131 }
6132
6133 NOREF(pszFailure);
6134 NOREF(pszInstr);
6135 return rc;
6136}
6137
6138
6139/**
6140 * Checks guest PDPTEs as part of VM-entry.
6141 *
6142 * @param pVCpu The cross context virtual CPU structure.
6143 * @param pszInstr The VMX instruction name (for logging purposes).
6144 */
6145IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6146{
6147 /*
6148 * Guest PDPTEs.
6149 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6150 */
6151 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6152 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6153
6154 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6155 int rc;
6156 if ( !fGstInLongMode
6157 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6158 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6159 {
6160 /*
6161 * We don't support nested-paging for nested-guests yet.
6162 *
6163 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6164 * rather we need to check the PDPTEs referenced by the guest CR3.
6165 */
6166 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6167 }
6168 else
6169 rc = VINF_SUCCESS;
6170 return rc;
6171}
6172
6173
6174/**
6175 * Checks guest-state as part of VM-entry.
6176 *
6177 * @returns VBox status code.
6178 * @param pVCpu The cross context virtual CPU structure.
6179 * @param pszInstr The VMX instruction name (for logging purposes).
6180 */
6181IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6182{
6183 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6184 if (RT_SUCCESS(rc))
6185 {
6186 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6187 if (RT_SUCCESS(rc))
6188 {
6189 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6190 if (RT_SUCCESS(rc))
6191 {
6192 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6193 if (RT_SUCCESS(rc))
6194 {
6195 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6196 if (RT_SUCCESS(rc))
6197 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6198 }
6199 }
6200 }
6201 }
6202 return rc;
6203}
6204
6205
6206/**
6207 * Checks host-state as part of VM-entry.
6208 *
6209 * @returns VBox status code.
6210 * @param pVCpu The cross context virtual CPU structure.
6211 * @param pszInstr The VMX instruction name (for logging purposes).
6212 */
6213IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6214{
6215 /*
6216 * Host Control Registers and MSRs.
6217 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6218 */
6219 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6220 const char * const pszFailure = "VMFail";
6221
6222 /* CR0 reserved bits. */
6223 {
6224 /* CR0 MB1 bits. */
6225 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6226 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6227 { /* likely */ }
6228 else
6229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6230
6231 /* CR0 MBZ bits. */
6232 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6233 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6234 { /* likely */ }
6235 else
6236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6237 }
6238
6239 /* CR4 reserved bits. */
6240 {
6241 /* CR4 MB1 bits. */
6242 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6243 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6247
6248 /* CR4 MBZ bits. */
6249 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6250 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6254 }
6255
6256 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6257 {
6258 /* CR3 reserved bits. */
6259 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6260 { /* likely */ }
6261 else
6262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6263
6264 /* SYSENTER ESP and SYSENTER EIP. */
6265 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6266 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6267 { /* likely */ }
6268 else
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6270 }
6271
6272 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6273 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6274
6275 /* PAT MSR. */
6276 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6277 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6278 { /* likely */ }
6279 else
6280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6281
6282 /* EFER MSR. */
6283 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6284 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6285 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6286 { /* likely */ }
6287 else
6288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6289
6290 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6291 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6292 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6293 if ( fHostInLongMode == fHostLma
6294 && fHostInLongMode == fHostLme)
6295 { /* likely */ }
6296 else
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6298
6299 /*
6300 * Host Segment and Descriptor-Table Registers.
6301 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6302 */
6303 /* Selector RPL and TI. */
6304 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6305 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6306 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6307 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6308 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6309 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6310 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6311 { /* likely */ }
6312 else
6313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6314
6315 /* CS and TR selectors cannot be 0. */
6316 if ( pVmcs->HostCs
6317 && pVmcs->HostTr)
6318 { /* likely */ }
6319 else
6320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6321
6322 /* SS cannot be 0 if 32-bit host. */
6323 if ( fHostInLongMode
6324 || pVmcs->HostSs)
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6328
6329 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6330 {
6331 /* FS, GS, GDTR, IDTR, TR base address. */
6332 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6333 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6334 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6335 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6336 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6337 { /* likely */ }
6338 else
6339 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6340 }
6341
6342 /*
6343 * Host address-space size for 64-bit CPUs.
6344 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6345 */
6346 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6347 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6348 {
6349 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6350
6351 /* Logical processor in IA-32e mode. */
6352 if (fCpuInLongMode)
6353 {
6354 if (fHostInLongMode)
6355 {
6356 /* PAE must be set. */
6357 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6361
6362 /* RIP must be canonical. */
6363 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6364 { /* likely */ }
6365 else
6366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6367 }
6368 else
6369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6370 }
6371 else
6372 {
6373 /* Logical processor is outside IA-32e mode. */
6374 if ( !fGstInLongMode
6375 && !fHostInLongMode)
6376 {
6377 /* PCIDE should not be set. */
6378 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6379 { /* likely */ }
6380 else
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6382
6383 /* The high 32-bits of RIP MBZ. */
6384 if (!pVmcs->u64HostRip.s.Hi)
6385 { /* likely */ }
6386 else
6387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6388 }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6391 }
6392 }
6393 else
6394 {
6395 /* Host address-space size for 32-bit CPUs. */
6396 if ( !fGstInLongMode
6397 && !fHostInLongMode)
6398 { /* likely */ }
6399 else
6400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6401 }
6402
6403 NOREF(pszInstr);
6404 NOREF(pszFailure);
6405 return VINF_SUCCESS;
6406}
6407
6408
6409/**
6410 * Checks VM-entry controls fields as part of VM-entry.
6411 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6412 *
6413 * @returns VBox status code.
6414 * @param pVCpu The cross context virtual CPU structure.
6415 * @param pszInstr The VMX instruction name (for logging purposes).
6416 */
6417IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6418{
6419 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6420 const char * const pszFailure = "VMFail";
6421
6422 /* VM-entry controls. */
6423 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6424 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6425 { /* likely */ }
6426 else
6427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6428
6429 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6430 { /* likely */ }
6431 else
6432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6433
6434 /* Event injection. */
6435 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6436 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6437 {
6438 /* Type and vector. */
6439 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6440 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6441 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6442 if ( !uRsvd
6443 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6444 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6445 { /* likely */ }
6446 else
6447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6448
6449 /* Exception error code. */
6450 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6451 {
6452 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6453 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6454 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6455 { /* likely */ }
6456 else
6457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6458
6459 /* Exceptions that provide an error code. */
6460 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6461 && ( uVector == X86_XCPT_DF
6462 || uVector == X86_XCPT_TS
6463 || uVector == X86_XCPT_NP
6464 || uVector == X86_XCPT_SS
6465 || uVector == X86_XCPT_GP
6466 || uVector == X86_XCPT_PF
6467 || uVector == X86_XCPT_AC))
6468 { /* likely */ }
6469 else
6470 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6471
6472 /* Exception error-code reserved bits. */
6473 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6474 { /* likely */ }
6475 else
6476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6477
6478 /* Injecting a software interrupt, software exception or privileged software exception. */
6479 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6480 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6481 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6482 {
6483 /* Instruction length must be in the range 0-15. */
6484 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6485 { /* likely */ }
6486 else
6487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6488
6489 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6490 if ( pVmcs->u32EntryInstrLen == 0
6491 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6493 }
6494 }
6495 }
6496
6497 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6498 if (pVmcs->u32EntryMsrLoadCount)
6499 {
6500 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6501 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6502 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6503 { /* likely */ }
6504 else
6505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6506 }
6507
6508 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6509 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6510
6511 NOREF(pszInstr);
6512 NOREF(pszFailure);
6513 return VINF_SUCCESS;
6514}
6515
6516
6517/**
6518 * Checks VM-exit controls fields as part of VM-entry.
6519 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6520 *
6521 * @returns VBox status code.
6522 * @param pVCpu The cross context virtual CPU structure.
6523 * @param pszInstr The VMX instruction name (for logging purposes).
6524 */
6525IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6526{
6527 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6528 const char * const pszFailure = "VMFail";
6529
6530 /* VM-exit controls. */
6531 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6532 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6533 { /* likely */ }
6534 else
6535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6536
6537 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6538 { /* likely */ }
6539 else
6540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6541
6542 /* Save preemption timer without activating it. */
6543 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6544 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6545 { /* likely */ }
6546 else
6547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6548
6549 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6550 if (pVmcs->u32ExitMsrStoreCount)
6551 {
6552 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6553 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6554 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6555 { /* likely */ }
6556 else
6557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6558 }
6559
6560 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6561 if (pVmcs->u32ExitMsrLoadCount)
6562 {
6563 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6564 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6565 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6566 { /* likely */ }
6567 else
6568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6569 }
6570
6571 NOREF(pszInstr);
6572 NOREF(pszFailure);
6573 return VINF_SUCCESS;
6574}
6575
6576
6577/**
6578 * Checks VM-execution controls fields as part of VM-entry.
6579 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6580 *
6581 * @returns VBox status code.
6582 * @param pVCpu The cross context virtual CPU structure.
6583 * @param pszInstr The VMX instruction name (for logging purposes).
6584 *
6585 * @remarks This may update secondary-processor based VM-execution control fields
6586 * in the current VMCS if necessary.
6587 */
6588IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6589{
6590 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6591 const char * const pszFailure = "VMFail";
6592
6593 /* Pin-based VM-execution controls. */
6594 {
6595 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6596 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6597 { /* likely */ }
6598 else
6599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6600
6601 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6602 { /* likely */ }
6603 else
6604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6605 }
6606
6607 /* Processor-based VM-execution controls. */
6608 {
6609 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6610 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6611 { /* likely */ }
6612 else
6613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6614
6615 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6619 }
6620
6621 /* Secondary processor-based VM-execution controls. */
6622 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6623 {
6624 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6625 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6626 { /* likely */ }
6627 else
6628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6629
6630 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6631 { /* likely */ }
6632 else
6633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6634 }
6635 else
6636 Assert(!pVmcs->u32ProcCtls2);
6637
6638 /* CR3-target count. */
6639 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6640 { /* likely */ }
6641 else
6642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6643
6644 /* I/O bitmaps physical addresses. */
6645 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6646 {
6647 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6648 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6649 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6653
6654 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6655 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6656 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6657 { /* likely */ }
6658 else
6659 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6660 }
6661
6662 /* MSR bitmap physical address. */
6663 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6664 {
6665 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6666 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6667 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6668 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6669 { /* likely */ }
6670 else
6671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6672
6673 /* Read the MSR bitmap. */
6674 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6675 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6676 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6677 if (RT_SUCCESS(rc))
6678 { /* likely */ }
6679 else
6680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6681 }
6682
6683 /* TPR shadow related controls. */
6684 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6685 {
6686 /* Virtual-APIC page physical address. */
6687 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6688 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6689 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6690 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6691 { /* likely */ }
6692 else
6693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6694
6695 /* TPR threshold without virtual-interrupt delivery. */
6696 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6697 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6699
6700 /* TPR threshold and VTPR. */
6701 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6702 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6703 {
6704 /* Read the VTPR from the virtual-APIC page. */
6705 uint8_t u8VTpr;
6706 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6707 if (RT_SUCCESS(rc))
6708 { /* likely */ }
6709 else
6710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6711
6712 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6713 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6717 }
6718 }
6719 else
6720 {
6721 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6722 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6723 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6724 { /* likely */ }
6725 else
6726 {
6727 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6729 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6731 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6733 }
6734 }
6735
6736 /* NMI exiting and virtual-NMIs. */
6737 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6738 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6739 { /* likely */ }
6740 else
6741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6742
6743 /* Virtual-NMIs and NMI-window exiting. */
6744 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6745 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6746 { /* likely */ }
6747 else
6748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6749
6750 /* Virtualize APIC accesses. */
6751 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6752 {
6753 /* APIC-access physical address. */
6754 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6755 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6756 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6757 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6758 { /* likely */ }
6759 else
6760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6761
6762 /*
6763 * Disallow APIC-access page and virtual-APIC page from being the same address.
6764 * Note! This is not an Intel requirement, but one imposed by our implementation.
6765 */
6766 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6767 * redirecting accesses between the APIC-access page and the virtual-APIC
6768 * page. If any nested hypervisor requires this, we can implement it later. */
6769 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6770 {
6771 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6772 if (GCPhysVirtApic != GCPhysApicAccess)
6773 { /* likely */ }
6774 else
6775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6776 }
6777
6778 /*
6779 * Register the handler for the APIC-access page.
6780 *
6781 * We don't deregister the APIC-access page handler during the VM-exit as a different
6782 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6783 *
6784 * We leave the page registered until the first access that happens outside VMX non-root
6785 * mode. Guest software is allowed to access structures such as the APIC-access page
6786 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6787 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6788 *
6789 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6790 */
6791 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6792 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6793 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6794 if (RT_SUCCESS(rc))
6795 { /* likely */ }
6796 else
6797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6798 }
6799
6800 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6801 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6802 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6803 { /* likely */ }
6804 else
6805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6806
6807 /* Virtual-interrupt delivery requires external interrupt exiting. */
6808 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6809 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6810 { /* likely */ }
6811 else
6812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6813
6814 /* VPID. */
6815 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6816 || pVmcs->u16Vpid != 0)
6817 { /* likely */ }
6818 else
6819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6820
6821 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6822 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6823 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6824 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6825 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6826 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6827 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6828
6829 /* VMCS shadowing. */
6830 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6831 {
6832 /* VMREAD-bitmap physical address. */
6833 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6834 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6835 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6836 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6837 { /* likely */ }
6838 else
6839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6840
6841 /* VMWRITE-bitmap physical address. */
6842 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6843 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6844 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6845 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6846 { /* likely */ }
6847 else
6848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6849
6850 /* Read the VMREAD-bitmap. */
6851 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6852 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6853 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6854 if (RT_SUCCESS(rc))
6855 { /* likely */ }
6856 else
6857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6858
6859 /* Read the VMWRITE-bitmap. */
6860 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6861 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6862 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6863 if (RT_SUCCESS(rc))
6864 { /* likely */ }
6865 else
6866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6867 }
6868
6869 NOREF(pszInstr);
6870 NOREF(pszFailure);
6871 return VINF_SUCCESS;
6872}
6873
6874
6875/**
6876 * Loads the guest control registers, debug register and some MSRs as part of
6877 * VM-entry.
6878 *
6879 * @param pVCpu The cross context virtual CPU structure.
6880 */
6881IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6882{
6883 /*
6884 * Load guest control registers, debug registers and MSRs.
6885 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6886 */
6887 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6888
6889 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6890 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6891 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6892 CPUMSetGuestCR0(pVCpu, uGstCr0);
6893 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6894 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6895
6896 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6897 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6898
6899 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6900 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6901 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6902
6903 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6904 {
6905 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6906
6907 /* EFER MSR. */
6908 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6909 {
6910 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6911 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6912 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6913 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6914 if (fGstInLongMode)
6915 {
6916 /* If the nested-guest is in long mode, LMA and LME are both set. */
6917 Assert(fGstPaging);
6918 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6919 }
6920 else
6921 {
6922 /*
6923 * If the nested-guest is outside long mode:
6924 * - With paging: LMA is cleared, LME is cleared.
6925 * - Without paging: LMA is cleared, LME is left unmodified.
6926 */
6927 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6928 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6929 }
6930 }
6931 /* else: see below. */
6932 }
6933
6934 /* PAT MSR. */
6935 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6936 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6937
6938 /* EFER MSR. */
6939 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6940 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6941
6942 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6943 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6944
6945 /* We don't support IA32_BNDCFGS MSR yet. */
6946 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6947
6948 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6949}
6950
6951
6952/**
6953 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6954 *
6955 * @param pVCpu The cross context virtual CPU structure.
6956 */
6957IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6958{
6959 /*
6960 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6961 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6962 */
6963 /* CS, SS, ES, DS, FS, GS. */
6964 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6965 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6966 {
6967 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6968 CPUMSELREG VmcsSelReg;
6969 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6970 AssertRC(rc); NOREF(rc);
6971 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6972 {
6973 pGstSelReg->Sel = VmcsSelReg.Sel;
6974 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6975 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6976 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6977 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6978 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6979 }
6980 else
6981 {
6982 pGstSelReg->Sel = VmcsSelReg.Sel;
6983 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6984 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6985 switch (iSegReg)
6986 {
6987 case X86_SREG_CS:
6988 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6989 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6990 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6991 break;
6992
6993 case X86_SREG_SS:
6994 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6995 pGstSelReg->u32Limit = 0;
6996 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6997 break;
6998
6999 case X86_SREG_ES:
7000 case X86_SREG_DS:
7001 pGstSelReg->u64Base = 0;
7002 pGstSelReg->u32Limit = 0;
7003 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
7004 break;
7005
7006 case X86_SREG_FS:
7007 case X86_SREG_GS:
7008 pGstSelReg->u64Base = VmcsSelReg.u64Base;
7009 pGstSelReg->u32Limit = 0;
7010 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
7011 break;
7012 }
7013 Assert(pGstSelReg->Attr.n.u1Unusable);
7014 }
7015 }
7016
7017 /* LDTR. */
7018 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
7019 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
7020 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
7021 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
7022 {
7023 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
7024 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
7025 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
7026 }
7027 else
7028 {
7029 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
7030 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
7031 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
7032 }
7033
7034 /* TR. */
7035 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
7036 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
7037 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
7038 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
7039 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
7040 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
7041 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
7042
7043 /* GDTR. */
7044 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
7045 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
7046
7047 /* IDTR. */
7048 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
7049 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
7050}
7051
7052
7053/**
7054 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
7055 *
7056 * @returns VBox status code.
7057 * @param pVCpu The cross context virtual CPU structure.
7058 * @param pszInstr The VMX instruction name (for logging purposes).
7059 */
7060IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
7061{
7062 /*
7063 * Load guest MSRs.
7064 * See Intel spec. 26.4 "Loading MSRs".
7065 */
7066 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7067 const char *const pszFailure = "VM-exit";
7068
7069 /*
7070 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7071 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7072 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7073 */
7074 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7075 if (!cMsrs)
7076 return VINF_SUCCESS;
7077
7078 /*
7079 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7080 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7081 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7082 */
7083 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7084 if (fIsMsrCountValid)
7085 { /* likely */ }
7086 else
7087 {
7088 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7090 }
7091
7092 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7093 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7094 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7095 if (RT_SUCCESS(rc))
7096 {
7097 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7098 Assert(pMsr);
7099 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7100 {
7101 if ( !pMsr->u32Reserved
7102 && pMsr->u32Msr != MSR_K8_FS_BASE
7103 && pMsr->u32Msr != MSR_K8_GS_BASE
7104 && pMsr->u32Msr != MSR_K6_EFER
7105 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7106 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7107 {
7108 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7109 if (rcStrict == VINF_SUCCESS)
7110 continue;
7111
7112 /*
7113 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7114 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7115 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7116 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7117 * MSR in ring-0 if possible, or come up with a better, generic solution.
7118 */
7119 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7120 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7121 ? kVmxVDiag_Vmentry_MsrLoadRing3
7122 : kVmxVDiag_Vmentry_MsrLoad;
7123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7124 }
7125 else
7126 {
7127 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7129 }
7130 }
7131 }
7132 else
7133 {
7134 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7136 }
7137
7138 NOREF(pszInstr);
7139 NOREF(pszFailure);
7140 return VINF_SUCCESS;
7141}
7142
7143
7144/**
7145 * Loads the guest-state non-register state as part of VM-entry.
7146 *
7147 * @returns VBox status code.
7148 * @param pVCpu The cross context virtual CPU structure.
7149 *
7150 * @remarks This must be called only after loading the nested-guest register state
7151 * (especially nested-guest RIP).
7152 */
7153IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7154{
7155 /*
7156 * Load guest non-register state.
7157 * See Intel spec. 26.6 "Special Features of VM Entry"
7158 */
7159 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7160
7161 /*
7162 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7163 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7164 *
7165 * See Intel spec. 26.6.1 "Interruptibility State".
7166 */
7167 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7168 if ( !fEntryVectoring
7169 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7170 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7171 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7172 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7173
7174 /* NMI blocking. */
7175 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7176 {
7177 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7178 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7179 else
7180 {
7181 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7182 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7183 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7184 }
7185 }
7186 else
7187 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7188
7189 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7190
7191 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7192 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7193
7194 /* VPID is irrelevant. We don't support VPID yet. */
7195
7196 /* Clear address-range monitoring. */
7197 EMMonitorWaitClear(pVCpu);
7198}
7199
7200
7201/**
7202 * Loads the guest-state as part of VM-entry.
7203 *
7204 * @returns VBox status code.
7205 * @param pVCpu The cross context virtual CPU structure.
7206 * @param pszInstr The VMX instruction name (for logging purposes).
7207 *
7208 * @remarks This must be done after all the necessary steps prior to loading of
7209 * guest-state (e.g. checking various VMCS state).
7210 */
7211IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7212{
7213 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7214 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7215
7216 /*
7217 * Load guest RIP, RSP and RFLAGS.
7218 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7219 */
7220 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7221 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7222 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7223 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7224
7225 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7226 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7227 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7228
7229 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7230
7231 NOREF(pszInstr);
7232 return VINF_SUCCESS;
7233}
7234
7235
7236/**
7237 * Returns whether there are is a pending debug exception on VM-entry.
7238 *
7239 * @param pVCpu The cross context virtual CPU structure.
7240 * @param pszInstr The VMX instruction name (for logging purposes).
7241 */
7242IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7243{
7244 /*
7245 * Pending debug exceptions.
7246 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7247 */
7248 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7249 Assert(pVmcs);
7250
7251 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7252 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7253 if (fPendingDbgXcpt)
7254 {
7255 uint8_t uEntryIntInfoType;
7256 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7257 if (fEntryVectoring)
7258 {
7259 switch (uEntryIntInfoType)
7260 {
7261 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7262 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7263 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7264 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7265 fPendingDbgXcpt = false;
7266 break;
7267
7268 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7269 {
7270 /*
7271 * Whether the pending debug exception for software exceptions other than
7272 * #BP and #OF is delivered after injecting the exception or is discard
7273 * is CPU implementation specific. We will discard them (easier).
7274 */
7275 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7276 if ( uVector != X86_XCPT_BP
7277 && uVector != X86_XCPT_OF)
7278 fPendingDbgXcpt = false;
7279 RT_FALL_THRU();
7280 }
7281 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7282 {
7283 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7284 fPendingDbgXcpt = false;
7285 break;
7286 }
7287 }
7288 }
7289 else
7290 {
7291 /*
7292 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7293 * pending debug exception is held pending or is discarded is CPU implementation
7294 * specific. We will discard them (easier).
7295 */
7296 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7297 fPendingDbgXcpt = false;
7298
7299 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7300 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7301 fPendingDbgXcpt = false;
7302 }
7303 }
7304
7305 NOREF(pszInstr);
7306 return fPendingDbgXcpt;
7307}
7308
7309
7310/**
7311 * Set up the monitor-trap flag (MTF).
7312 *
7313 * @param pVCpu The cross context virtual CPU structure.
7314 * @param pszInstr The VMX instruction name (for logging purposes).
7315 */
7316IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7317{
7318 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7319 Assert(pVmcs);
7320 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7321 {
7322 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7323 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7324 }
7325 else
7326 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7327 NOREF(pszInstr);
7328}
7329
7330
7331/**
7332 * Set up the VMX-preemption timer.
7333 *
7334 * @param pVCpu The cross context virtual CPU structure.
7335 * @param pszInstr The VMX instruction name (for logging purposes).
7336 */
7337IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7338{
7339 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7340 Assert(pVmcs);
7341 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7342 {
7343 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7344 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7345 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7346
7347 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7348 }
7349 else
7350 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7351
7352 NOREF(pszInstr);
7353}
7354
7355
7356/**
7357 * Injects an event using TRPM given a VM-entry interruption info. and related
7358 * fields.
7359 *
7360 * @returns VBox status code.
7361 * @param pVCpu The cross context virtual CPU structure.
7362 * @param uEntryIntInfo The VM-entry interruption info.
7363 * @param uErrCode The error code associated with the event if any.
7364 * @param cbInstr The VM-entry instruction length (for software
7365 * interrupts and software exceptions). Pass 0
7366 * otherwise.
7367 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7368 */
7369IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7370 RTGCUINTPTR GCPtrFaultAddress)
7371{
7372 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7373
7374 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7375 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7376 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7377
7378 TRPMEVENT enmTrapType;
7379 switch (uType)
7380 {
7381 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7382 enmTrapType = TRPM_HARDWARE_INT;
7383 break;
7384
7385 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7386 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7387 enmTrapType = TRPM_TRAP;
7388 break;
7389
7390 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7391 enmTrapType = TRPM_SOFTWARE_INT;
7392 break;
7393
7394 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7395 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7396 enmTrapType = TRPM_SOFTWARE_INT;
7397 break;
7398
7399 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7400 Assert(uVector == X86_XCPT_DB);
7401 enmTrapType = TRPM_SOFTWARE_INT;
7402 break;
7403
7404 default:
7405 /* Shouldn't really happen. */
7406 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7407 break;
7408 }
7409
7410 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7411 AssertRCReturn(rc, rc);
7412
7413 if (fErrCodeValid)
7414 TRPMSetErrorCode(pVCpu, uErrCode);
7415
7416 if ( enmTrapType == TRPM_TRAP
7417 && uVector == X86_XCPT_PF)
7418 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7419 else if (enmTrapType == TRPM_SOFTWARE_INT)
7420 TRPMSetInstrLength(pVCpu, cbInstr);
7421
7422 return VINF_SUCCESS;
7423}
7424
7425
7426/**
7427 * Performs event injection (if any) as part of VM-entry.
7428 *
7429 * @param pVCpu The cross context virtual CPU structure.
7430 * @param pszInstr The VMX instruction name (for logging purposes).
7431 */
7432IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7433{
7434 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7435
7436 /*
7437 * Inject events.
7438 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7439 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7440 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7441 * the actually delivery of this event.
7442 *
7443 * See Intel spec. 26.5 "Event Injection".
7444 */
7445 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7446 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7447
7448 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7449 if (fEntryIntInfoValid)
7450 {
7451 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7452 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7453 {
7454 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7455 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7456 return VINF_SUCCESS;
7457 }
7458
7459 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7460 pVCpu->cpum.GstCtx.cr2);
7461 if (RT_SUCCESS(rc))
7462 {
7463 /*
7464 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7465 *
7466 * However, we do it here on VM-entry because while it continues to not be visible to
7467 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7468 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7469 * information field.
7470 *
7471 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7472 */
7473 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7474 }
7475 return rc;
7476 }
7477
7478 /*
7479 * Inject any pending guest debug exception.
7480 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7481 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7482 */
7483 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7484 if (fPendingDbgXcpt)
7485 {
7486 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7487 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7488 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7489 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7490 0 /* GCPtrFaultAddress */);
7491 }
7492
7493 NOREF(pszInstr);
7494 return VINF_SUCCESS;
7495}
7496
7497
7498/**
7499 * Initializes all read-only VMCS fields as part of VM-entry.
7500 *
7501 * @param pVCpu The cross context virtual CPU structure.
7502 */
7503IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7504{
7505 /*
7506 * Any VMCS field which we do not establish on every VM-exit but may potentially
7507 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7508 * specified to be undefined needs to be initialized here.
7509 *
7510 * Thus, it is especially important to clear the VM-exit qualification field
7511 * since it must be zero for VM-exits where it is not used. Similarly, the
7512 * VM-exit interruption information field's valid bit needs to be cleared for
7513 * the same reasons.
7514 */
7515 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7516 Assert(pVmcs);
7517
7518 /* 16-bit (none currently). */
7519 /* 32-bit. */
7520 pVmcs->u32RoVmInstrError = 0;
7521 pVmcs->u32RoExitReason = 0;
7522 pVmcs->u32RoExitIntInfo = 0;
7523 pVmcs->u32RoExitIntErrCode = 0;
7524 pVmcs->u32RoIdtVectoringInfo = 0;
7525 pVmcs->u32RoIdtVectoringErrCode = 0;
7526 pVmcs->u32RoExitInstrLen = 0;
7527 pVmcs->u32RoExitInstrInfo = 0;
7528
7529 /* 64-bit. */
7530 pVmcs->u64RoGuestPhysAddr.u = 0;
7531
7532 /* Natural-width. */
7533 pVmcs->u64RoExitQual.u = 0;
7534 pVmcs->u64RoIoRcx.u = 0;
7535 pVmcs->u64RoIoRsi.u = 0;
7536 pVmcs->u64RoIoRdi.u = 0;
7537 pVmcs->u64RoIoRip.u = 0;
7538 pVmcs->u64RoGuestLinearAddr.u = 0;
7539}
7540
7541
7542/**
7543 * VMLAUNCH/VMRESUME instruction execution worker.
7544 *
7545 * @returns Strict VBox status code.
7546 * @param pVCpu The cross context virtual CPU structure.
7547 * @param cbInstr The instruction length in bytes.
7548 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7549 * VMXINSTRID_VMRESUME).
7550 *
7551 * @remarks Common VMX instruction checks are already expected to by the caller,
7552 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7553 */
7554IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7555{
7556# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7557 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7558 return VINF_EM_RAW_EMULATE_INSTR;
7559# else
7560 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7561 || uInstrId == VMXINSTRID_VMRESUME);
7562 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7563
7564 /* Nested-guest intercept. */
7565 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7566 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7567
7568 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7569
7570 /*
7571 * Basic VM-entry checks.
7572 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7573 * The checks following that do not have to follow a specific order.
7574 *
7575 * See Intel spec. 26.1 "Basic VM-entry Checks".
7576 */
7577
7578 /* CPL. */
7579 if (pVCpu->iem.s.uCpl == 0)
7580 { /* likely */ }
7581 else
7582 {
7583 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7584 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7585 return iemRaiseGeneralProtectionFault0(pVCpu);
7586 }
7587
7588 /* Current VMCS valid. */
7589 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7590 { /* likely */ }
7591 else
7592 {
7593 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7595 iemVmxVmFailInvalid(pVCpu);
7596 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7597 return VINF_SUCCESS;
7598 }
7599
7600 /* Current VMCS is not a shadow VMCS. */
7601 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7602 { /* likely */ }
7603 else
7604 {
7605 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7606 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7607 iemVmxVmFailInvalid(pVCpu);
7608 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7609 return VINF_SUCCESS;
7610 }
7611
7612 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7613 * use block-by-STI here which is not quite correct. */
7614 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7615 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7616 { /* likely */ }
7617 else
7618 {
7619 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7621 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7622 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7623 return VINF_SUCCESS;
7624 }
7625
7626 if (uInstrId == VMXINSTRID_VMLAUNCH)
7627 {
7628 /* VMLAUNCH with non-clear VMCS. */
7629 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7630 { /* likely */ }
7631 else
7632 {
7633 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7634 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7635 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7636 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7637 return VINF_SUCCESS;
7638 }
7639 }
7640 else
7641 {
7642 /* VMRESUME with non-launched VMCS. */
7643 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7644 { /* likely */ }
7645 else
7646 {
7647 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7648 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7649 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7651 return VINF_SUCCESS;
7652 }
7653 }
7654
7655 /*
7656 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7657 * while entering VMX non-root mode. We do some of this while checking VM-execution
7658 * controls. The guest hypervisor should not make assumptions and cannot expect
7659 * predictable behavior if changes to these structures are made in guest memory while
7660 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7661 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7662 *
7663 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7664 */
7665 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7666 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7667 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7668 if (RT_SUCCESS(rc))
7669 {
7670 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7671 if (RT_SUCCESS(rc))
7672 {
7673 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7674 if (RT_SUCCESS(rc))
7675 {
7676 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7677 if (RT_SUCCESS(rc))
7678 {
7679 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7680 iemVmxVmentryInitReadOnlyFields(pVCpu);
7681
7682 /*
7683 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7684 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7685 * VM-exit when required.
7686 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7687 */
7688 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7689
7690 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7691 if (RT_SUCCESS(rc))
7692 {
7693 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7694 if (RT_SUCCESS(rc))
7695 {
7696 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7697 if (RT_SUCCESS(rc))
7698 {
7699 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7700
7701 /* VMLAUNCH instruction must update the VMCS launch state. */
7702 if (uInstrId == VMXINSTRID_VMLAUNCH)
7703 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7704
7705 /* Perform the VMX transition (PGM updates). */
7706 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7707 if (rcStrict == VINF_SUCCESS)
7708 { /* likely */ }
7709 else if (RT_SUCCESS(rcStrict))
7710 {
7711 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7712 VBOXSTRICTRC_VAL(rcStrict)));
7713 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7714 }
7715 else
7716 {
7717 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7718 return rcStrict;
7719 }
7720
7721 /* We've now entered nested-guest execution. */
7722 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7723
7724 /*
7725 * The priority of potential VM-exits during VM-entry is important.
7726 * The priorities of VM-exits and events are listed from highest
7727 * to lowest as follows:
7728 *
7729 * 1. Event injection.
7730 * 2. Trap on task-switch (T flag set in TSS).
7731 * 3. TPR below threshold / APIC-write.
7732 * 4. SMI, INIT.
7733 * 5. MTF exit.
7734 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7735 * 7. VMX-preemption timer.
7736 * 9. NMI-window exit.
7737 * 10. NMI injection.
7738 * 11. Interrupt-window exit.
7739 * 12. Virtual-interrupt injection.
7740 * 13. Interrupt injection.
7741 * 14. Process next instruction (fetch, decode, execute).
7742 */
7743
7744 /* Setup the VMX-preemption timer. */
7745 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7746
7747 /* Setup monitor-trap flag. */
7748 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7749
7750 /* Now that we've switched page tables, we can go ahead and inject any event. */
7751 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7752 if (RT_SUCCESS(rcStrict))
7753 {
7754 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7755# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7756 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7757 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7758 if (rcSched != VINF_SUCCESS)
7759 iemSetPassUpStatus(pVCpu, rcSched);
7760# endif
7761 return VINF_SUCCESS;
7762 }
7763
7764 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7765 return rcStrict;
7766 }
7767 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7768 }
7769 }
7770 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7771 }
7772
7773 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7775 return VINF_SUCCESS;
7776 }
7777 }
7778 }
7779
7780 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7781 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7782 return VINF_SUCCESS;
7783# endif
7784}
7785
7786
7787/**
7788 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7789 * (causes a VM-exit) or not.
7790 *
7791 * @returns @c true if the instruction is intercepted, @c false otherwise.
7792 * @param pVCpu The cross context virtual CPU structure.
7793 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7794 * VMX_EXIT_WRMSR).
7795 * @param idMsr The MSR.
7796 */
7797IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7798{
7799 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7800 Assert( uExitReason == VMX_EXIT_RDMSR
7801 || uExitReason == VMX_EXIT_WRMSR);
7802
7803 /* Consult the MSR bitmap if the feature is supported. */
7804 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7805 Assert(pVmcs);
7806 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7807 {
7808 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7809 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7810 if (uExitReason == VMX_EXIT_RDMSR)
7811 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7812 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7813 }
7814
7815 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7816 return true;
7817}
7818
7819
7820/**
7821 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7822 * intercepted (causes a VM-exit) or not.
7823 *
7824 * @returns @c true if the instruction is intercepted, @c false otherwise.
7825 * @param pVCpu The cross context virtual CPU structure.
7826 * @param u64FieldEnc The VMCS field encoding.
7827 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7828 * VMX_EXIT_VMREAD).
7829 */
7830IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7831{
7832 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7833 Assert( uExitReason == VMX_EXIT_VMREAD
7834 || uExitReason == VMX_EXIT_VMWRITE);
7835
7836 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7837 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7838 return true;
7839
7840 /*
7841 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7842 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7843 */
7844 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7845 return true;
7846
7847 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7848 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7849 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7850 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7851 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7852 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7853 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7854 pbBitmap += (u32FieldEnc >> 3);
7855 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7856 return true;
7857
7858 return false;
7859}
7860
7861
7862/**
7863 * VMREAD common (memory/register) instruction execution worker
7864 *
7865 * @returns Strict VBox status code.
7866 * @param pVCpu The cross context virtual CPU structure.
7867 * @param cbInstr The instruction length in bytes.
7868 * @param pu64Dst Where to write the VMCS value (only updated when
7869 * VINF_SUCCESS is returned).
7870 * @param u64FieldEnc The VMCS field encoding.
7871 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7872 * NULL.
7873 */
7874IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7875 PCVMXVEXITINFO pExitInfo)
7876{
7877 /* Nested-guest intercept. */
7878 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7879 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7880 {
7881 if (pExitInfo)
7882 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7883 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7884 }
7885
7886 /* CPL. */
7887 if (pVCpu->iem.s.uCpl == 0)
7888 { /* likely */ }
7889 else
7890 {
7891 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7892 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7893 return iemRaiseGeneralProtectionFault0(pVCpu);
7894 }
7895
7896 /* VMCS pointer in root mode. */
7897 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7898 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7899 { /* likely */ }
7900 else
7901 {
7902 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7903 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7904 iemVmxVmFailInvalid(pVCpu);
7905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7906 return VINF_SUCCESS;
7907 }
7908
7909 /* VMCS-link pointer in non-root mode. */
7910 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7911 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7912 { /* likely */ }
7913 else
7914 {
7915 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7916 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7917 iemVmxVmFailInvalid(pVCpu);
7918 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7919 return VINF_SUCCESS;
7920 }
7921
7922 /* Supported VMCS field. */
7923 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7924 { /* likely */ }
7925 else
7926 {
7927 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7928 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7929 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7930 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7931 return VINF_SUCCESS;
7932 }
7933
7934 /*
7935 * Setup reading from the current or shadow VMCS.
7936 */
7937 uint8_t *pbVmcs;
7938 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7939 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7940 else
7941 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7942 Assert(pbVmcs);
7943
7944 VMXVMCSFIELDENC FieldEnc;
7945 FieldEnc.u = u64FieldEnc;
7946 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7947 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7948 uint8_t const uWidthType = (uWidth << 2) | uType;
7949 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7950 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7951 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7952 Assert(offField < VMX_V_VMCS_SIZE);
7953
7954 /*
7955 * Read the VMCS component based on the field's effective width.
7956 *
7957 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7958 * indicates high bits (little endian).
7959 *
7960 * Note! The caller is responsible to trim the result and update registers
7961 * or memory locations are required. Here we just zero-extend to the largest
7962 * type (i.e. 64-bits).
7963 */
7964 uint8_t *pbField = pbVmcs + offField;
7965 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7966 switch (uEffWidth)
7967 {
7968 case VMX_VMCS_ENC_WIDTH_64BIT:
7969 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7970 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7971 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7972 }
7973 return VINF_SUCCESS;
7974}
7975
7976
7977/**
7978 * VMREAD (64-bit register) instruction execution worker.
7979 *
7980 * @returns Strict VBox status code.
7981 * @param pVCpu The cross context virtual CPU structure.
7982 * @param cbInstr The instruction length in bytes.
7983 * @param pu64Dst Where to store the VMCS field's value.
7984 * @param u64FieldEnc The VMCS field encoding.
7985 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7986 * NULL.
7987 */
7988IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7989 PCVMXVEXITINFO pExitInfo)
7990{
7991 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7992 if (rcStrict == VINF_SUCCESS)
7993 {
7994 iemVmxVmreadSuccess(pVCpu, cbInstr);
7995 return VINF_SUCCESS;
7996 }
7997
7998 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7999 return rcStrict;
8000}
8001
8002
8003/**
8004 * VMREAD (32-bit register) instruction execution worker.
8005 *
8006 * @returns Strict VBox status code.
8007 * @param pVCpu The cross context virtual CPU structure.
8008 * @param cbInstr The instruction length in bytes.
8009 * @param pu32Dst Where to store the VMCS field's value.
8010 * @param u32FieldEnc The VMCS field encoding.
8011 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8012 * NULL.
8013 */
8014IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
8015 PCVMXVEXITINFO pExitInfo)
8016{
8017 uint64_t u64Dst;
8018 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
8019 if (rcStrict == VINF_SUCCESS)
8020 {
8021 *pu32Dst = u64Dst;
8022 iemVmxVmreadSuccess(pVCpu, cbInstr);
8023 return VINF_SUCCESS;
8024 }
8025
8026 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8027 return rcStrict;
8028}
8029
8030
8031/**
8032 * VMREAD (memory) instruction execution worker.
8033 *
8034 * @returns Strict VBox status code.
8035 * @param pVCpu The cross context virtual CPU structure.
8036 * @param cbInstr The instruction length in bytes.
8037 * @param iEffSeg The effective segment register to use with @a u64Val.
8038 * Pass UINT8_MAX if it is a register access.
8039 * @param GCPtrDst The guest linear address to store the VMCS field's
8040 * value.
8041 * @param u64FieldEnc The VMCS field encoding.
8042 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8043 * NULL.
8044 */
8045IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
8046 PCVMXVEXITINFO pExitInfo)
8047{
8048 uint64_t u64Dst;
8049 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
8050 if (rcStrict == VINF_SUCCESS)
8051 {
8052 /*
8053 * Write the VMCS field's value to the location specified in guest-memory.
8054 */
8055 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8056 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8057 else
8058 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8059 if (rcStrict == VINF_SUCCESS)
8060 {
8061 iemVmxVmreadSuccess(pVCpu, cbInstr);
8062 return VINF_SUCCESS;
8063 }
8064
8065 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8066 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8067 return rcStrict;
8068 }
8069
8070 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8071 return rcStrict;
8072}
8073
8074
8075/**
8076 * VMWRITE instruction execution worker.
8077 *
8078 * @returns Strict VBox status code.
8079 * @param pVCpu The cross context virtual CPU structure.
8080 * @param cbInstr The instruction length in bytes.
8081 * @param iEffSeg The effective segment register to use with @a u64Val.
8082 * Pass UINT8_MAX if it is a register access.
8083 * @param u64Val The value to write (or guest linear address to the
8084 * value), @a iEffSeg will indicate if it's a memory
8085 * operand.
8086 * @param u64FieldEnc The VMCS field encoding.
8087 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8088 * NULL.
8089 */
8090IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8091 PCVMXVEXITINFO pExitInfo)
8092{
8093 /* Nested-guest intercept. */
8094 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8095 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8096 {
8097 if (pExitInfo)
8098 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8099 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8100 }
8101
8102 /* CPL. */
8103 if (pVCpu->iem.s.uCpl == 0)
8104 { /* likely */ }
8105 else
8106 {
8107 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8109 return iemRaiseGeneralProtectionFault0(pVCpu);
8110 }
8111
8112 /* VMCS pointer in root mode. */
8113 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8114 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8115 { /* likely */ }
8116 else
8117 {
8118 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8119 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8120 iemVmxVmFailInvalid(pVCpu);
8121 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8122 return VINF_SUCCESS;
8123 }
8124
8125 /* VMCS-link pointer in non-root mode. */
8126 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8127 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8128 { /* likely */ }
8129 else
8130 {
8131 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8132 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8133 iemVmxVmFailInvalid(pVCpu);
8134 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8135 return VINF_SUCCESS;
8136 }
8137
8138 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8139 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8140 if (!fIsRegOperand)
8141 {
8142 /* Read the value from the specified guest memory location. */
8143 VBOXSTRICTRC rcStrict;
8144 RTGCPTR const GCPtrVal = u64Val;
8145 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8146 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8147 else
8148 {
8149 uint32_t u32Val;
8150 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8151 u64Val = u32Val;
8152 }
8153 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8154 {
8155 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8157 return rcStrict;
8158 }
8159 }
8160 else
8161 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8162
8163 /* Supported VMCS field. */
8164 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8165 { /* likely */ }
8166 else
8167 {
8168 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8170 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173 }
8174
8175 /* Read-only VMCS field. */
8176 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8177 if ( !fIsFieldReadOnly
8178 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8179 { /* likely */ }
8180 else
8181 {
8182 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8183 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8184 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8185 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8186 return VINF_SUCCESS;
8187 }
8188
8189 /*
8190 * Setup writing to the current or shadow VMCS.
8191 */
8192 uint8_t *pbVmcs;
8193 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8194 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8195 else
8196 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8197 Assert(pbVmcs);
8198
8199 VMXVMCSFIELDENC FieldEnc;
8200 FieldEnc.u = u64FieldEnc;
8201 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8202 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8203 uint8_t const uWidthType = (uWidth << 2) | uType;
8204 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8205 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8206 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8207 Assert(offField < VMX_V_VMCS_SIZE);
8208
8209 /*
8210 * Write the VMCS component based on the field's effective width.
8211 *
8212 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8213 * indicates high bits (little endian).
8214 */
8215 uint8_t *pbField = pbVmcs + offField;
8216 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8217 switch (uEffWidth)
8218 {
8219 case VMX_VMCS_ENC_WIDTH_64BIT:
8220 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8221 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8222 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8223 }
8224
8225 iemVmxVmSucceed(pVCpu);
8226 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8227 return VINF_SUCCESS;
8228}
8229
8230
8231/**
8232 * VMCLEAR instruction execution worker.
8233 *
8234 * @returns Strict VBox status code.
8235 * @param pVCpu The cross context virtual CPU structure.
8236 * @param cbInstr The instruction length in bytes.
8237 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8238 * @param GCPtrVmcs The linear address of the VMCS pointer.
8239 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8240 * NULL.
8241 *
8242 * @remarks Common VMX instruction checks are already expected to by the caller,
8243 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8244 */
8245IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8246 PCVMXVEXITINFO pExitInfo)
8247{
8248 /* Nested-guest intercept. */
8249 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8250 {
8251 if (pExitInfo)
8252 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8253 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8254 }
8255
8256 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8257
8258 /* CPL. */
8259 if (pVCpu->iem.s.uCpl == 0)
8260 { /* likely */ }
8261 else
8262 {
8263 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8264 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8265 return iemRaiseGeneralProtectionFault0(pVCpu);
8266 }
8267
8268 /* Get the VMCS pointer from the location specified by the source memory operand. */
8269 RTGCPHYS GCPhysVmcs;
8270 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8271 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8272 { /* likely */ }
8273 else
8274 {
8275 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8276 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8277 return rcStrict;
8278 }
8279
8280 /* VMCS pointer alignment. */
8281 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8282 { /* likely */ }
8283 else
8284 {
8285 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8286 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8287 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8288 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8289 return VINF_SUCCESS;
8290 }
8291
8292 /* VMCS physical-address width limits. */
8293 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8294 { /* likely */ }
8295 else
8296 {
8297 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8298 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8299 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8300 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8301 return VINF_SUCCESS;
8302 }
8303
8304 /* VMCS is not the VMXON region. */
8305 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8306 { /* likely */ }
8307 else
8308 {
8309 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8311 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8312 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8313 return VINF_SUCCESS;
8314 }
8315
8316 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8317 restriction imposed by our implementation. */
8318 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8319 { /* likely */ }
8320 else
8321 {
8322 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8323 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8324 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8325 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8326 return VINF_SUCCESS;
8327 }
8328
8329 /*
8330 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8331 *
8332 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8333 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8334 * to 'clear'.
8335 */
8336 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8337 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8338 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8339 {
8340 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8341 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8342 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8343 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8344 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8345 }
8346 else
8347 {
8348 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8349 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8350 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8351 if (RT_FAILURE(rcStrict))
8352 return rcStrict;
8353 }
8354
8355 iemVmxVmSucceed(pVCpu);
8356 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8357 return VINF_SUCCESS;
8358}
8359
8360
8361/**
8362 * VMPTRST instruction execution worker.
8363 *
8364 * @returns Strict VBox status code.
8365 * @param pVCpu The cross context virtual CPU structure.
8366 * @param cbInstr The instruction length in bytes.
8367 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8368 * @param GCPtrVmcs The linear address of where to store the current VMCS
8369 * pointer.
8370 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8371 * NULL.
8372 *
8373 * @remarks Common VMX instruction checks are already expected to by the caller,
8374 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8375 */
8376IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8377 PCVMXVEXITINFO pExitInfo)
8378{
8379 /* Nested-guest intercept. */
8380 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8381 {
8382 if (pExitInfo)
8383 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8384 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8385 }
8386
8387 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8388
8389 /* CPL. */
8390 if (pVCpu->iem.s.uCpl == 0)
8391 { /* likely */ }
8392 else
8393 {
8394 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8395 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8396 return iemRaiseGeneralProtectionFault0(pVCpu);
8397 }
8398
8399 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8400 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8401 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8402 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8403 {
8404 iemVmxVmSucceed(pVCpu);
8405 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8406 return rcStrict;
8407 }
8408
8409 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8410 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8411 return rcStrict;
8412}
8413
8414
8415/**
8416 * VMPTRLD instruction execution worker.
8417 *
8418 * @returns Strict VBox status code.
8419 * @param pVCpu The cross context virtual CPU structure.
8420 * @param cbInstr The instruction length in bytes.
8421 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8422 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8423 * NULL.
8424 *
8425 * @remarks Common VMX instruction checks are already expected to by the caller,
8426 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8427 */
8428IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8429 PCVMXVEXITINFO pExitInfo)
8430{
8431 /* Nested-guest intercept. */
8432 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8433 {
8434 if (pExitInfo)
8435 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8436 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8437 }
8438
8439 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8440
8441 /* CPL. */
8442 if (pVCpu->iem.s.uCpl == 0)
8443 { /* likely */ }
8444 else
8445 {
8446 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8447 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8448 return iemRaiseGeneralProtectionFault0(pVCpu);
8449 }
8450
8451 /* Get the VMCS pointer from the location specified by the source memory operand. */
8452 RTGCPHYS GCPhysVmcs;
8453 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8454 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8455 { /* likely */ }
8456 else
8457 {
8458 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8460 return rcStrict;
8461 }
8462
8463 /* VMCS pointer alignment. */
8464 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8465 { /* likely */ }
8466 else
8467 {
8468 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8469 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8470 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8471 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8472 return VINF_SUCCESS;
8473 }
8474
8475 /* VMCS physical-address width limits. */
8476 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8477 { /* likely */ }
8478 else
8479 {
8480 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8481 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8482 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8483 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8484 return VINF_SUCCESS;
8485 }
8486
8487 /* VMCS is not the VMXON region. */
8488 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8489 { /* likely */ }
8490 else
8491 {
8492 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8493 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8494 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8495 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8496 return VINF_SUCCESS;
8497 }
8498
8499 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8500 restriction imposed by our implementation. */
8501 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8502 { /* likely */ }
8503 else
8504 {
8505 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8507 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8508 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8509 return VINF_SUCCESS;
8510 }
8511
8512 /* Read just the VMCS revision from the VMCS. */
8513 VMXVMCSREVID VmcsRevId;
8514 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8515 if (RT_SUCCESS(rc))
8516 { /* likely */ }
8517 else
8518 {
8519 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8520 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8521 return rc;
8522 }
8523
8524 /*
8525 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8526 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8527 */
8528 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8529 && ( !VmcsRevId.n.fIsShadowVmcs
8530 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8531 { /* likely */ }
8532 else
8533 {
8534 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8535 {
8536 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8537 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8538 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8539 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8540 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8541 return VINF_SUCCESS;
8542 }
8543
8544 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8545 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8546 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8547 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8548 return VINF_SUCCESS;
8549 }
8550
8551 /*
8552 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8553 * the cache of an existing, current VMCS back to guest memory before loading a new,
8554 * different current VMCS.
8555 */
8556 bool fLoadVmcsFromMem;
8557 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8558 {
8559 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8560 {
8561 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8562 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8563 fLoadVmcsFromMem = true;
8564 }
8565 else
8566 fLoadVmcsFromMem = false;
8567 }
8568 else
8569 fLoadVmcsFromMem = true;
8570
8571 if (fLoadVmcsFromMem)
8572 {
8573 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8574 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8575 sizeof(VMXVVMCS));
8576 if (RT_SUCCESS(rc))
8577 { /* likely */ }
8578 else
8579 {
8580 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8582 return rc;
8583 }
8584 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8585 }
8586
8587 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8588 iemVmxVmSucceed(pVCpu);
8589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8590 return VINF_SUCCESS;
8591}
8592
8593
8594/**
8595 * INVVPID instruction execution worker.
8596 *
8597 * @returns Strict VBox status code.
8598 * @param pVCpu The cross context virtual CPU structure.
8599 * @param cbInstr The instruction length in bytes.
8600 * @param iEffSeg The segment of the invvpid descriptor.
8601 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8602 * @param u64InvvpidType The invalidation type.
8603 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8604 * NULL.
8605 *
8606 * @remarks Common VMX instruction checks are already expected to by the caller,
8607 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8608 */
8609IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8610 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8611{
8612 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8613 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8614 return iemRaiseUndefinedOpcode(pVCpu);
8615
8616 /* Nested-guest intercept. */
8617 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8618 {
8619 if (pExitInfo)
8620 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8621 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8622 }
8623
8624 /* CPL. */
8625 if (pVCpu->iem.s.uCpl != 0)
8626 {
8627 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8628 return iemRaiseGeneralProtectionFault0(pVCpu);
8629 }
8630
8631 /*
8632 * Validate INVVPID invalidation type.
8633 *
8634 * The instruction specifies exactly ONE of the supported invalidation types.
8635 *
8636 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8637 * supported. In theory, it's possible for a CPU to not support flushing individual
8638 * addresses but all the other types or any other combination. We do not take any
8639 * shortcuts here by assuming the types we currently expose to the guest.
8640 */
8641 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8642 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8643 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8644 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8645 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8646 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8647 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8648 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8649 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8650 { /* likely */ }
8651 else
8652 {
8653 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8654 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8655 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8656 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8657 return VINF_SUCCESS;
8658 }
8659
8660 /*
8661 * Fetch the invvpid descriptor from guest memory.
8662 */
8663 RTUINT128U uDesc;
8664 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8665 if (rcStrict == VINF_SUCCESS)
8666 {
8667 /*
8668 * Validate the descriptor.
8669 */
8670 if (uDesc.s.Lo > 0xfff)
8671 {
8672 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8673 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8674 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8675 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8676 return VINF_SUCCESS;
8677 }
8678
8679 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8680 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8681 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8682 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8683 switch (u64InvvpidType)
8684 {
8685 case VMXTLBFLUSHVPID_INDIV_ADDR:
8686 {
8687 if (uVpid != 0)
8688 {
8689 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8690 {
8691 /* Invalidate mappings for the linear address tagged with VPID. */
8692 /** @todo PGM support for VPID? Currently just flush everything. */
8693 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8694 iemVmxVmSucceed(pVCpu);
8695 }
8696 else
8697 {
8698 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8699 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8700 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8701 }
8702 }
8703 else
8704 {
8705 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8706 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8707 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8708 }
8709 break;
8710 }
8711
8712 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8713 {
8714 if (uVpid != 0)
8715 {
8716 /* Invalidate all mappings with VPID. */
8717 /** @todo PGM support for VPID? Currently just flush everything. */
8718 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8719 iemVmxVmSucceed(pVCpu);
8720 }
8721 else
8722 {
8723 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8724 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8725 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8726 }
8727 break;
8728 }
8729
8730 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8731 {
8732 /* Invalidate all mappings with non-zero VPIDs. */
8733 /** @todo PGM support for VPID? Currently just flush everything. */
8734 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8735 iemVmxVmSucceed(pVCpu);
8736 break;
8737 }
8738
8739 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8740 {
8741 if (uVpid != 0)
8742 {
8743 /* Invalidate all mappings with VPID except global translations. */
8744 /** @todo PGM support for VPID? Currently just flush everything. */
8745 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8746 iemVmxVmSucceed(pVCpu);
8747 }
8748 else
8749 {
8750 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8751 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8752 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8753 }
8754 break;
8755 }
8756 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8757 }
8758 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8759 }
8760 return rcStrict;
8761}
8762
8763
8764/**
8765 * VMXON instruction execution worker.
8766 *
8767 * @returns Strict VBox status code.
8768 * @param pVCpu The cross context virtual CPU structure.
8769 * @param cbInstr The instruction length in bytes.
8770 * @param iEffSeg The effective segment register to use with @a
8771 * GCPtrVmxon.
8772 * @param GCPtrVmxon The linear address of the VMXON pointer.
8773 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8774 * NULL.
8775 *
8776 * @remarks Common VMX instruction checks are already expected to by the caller,
8777 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8778 */
8779IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8780 PCVMXVEXITINFO pExitInfo)
8781{
8782 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8783 {
8784 /* CPL. */
8785 if (pVCpu->iem.s.uCpl == 0)
8786 { /* likely */ }
8787 else
8788 {
8789 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8790 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8791 return iemRaiseGeneralProtectionFault0(pVCpu);
8792 }
8793
8794 /* A20M (A20 Masked) mode. */
8795 if (PGMPhysIsA20Enabled(pVCpu))
8796 { /* likely */ }
8797 else
8798 {
8799 Log(("vmxon: A20M mode -> #GP(0)\n"));
8800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8801 return iemRaiseGeneralProtectionFault0(pVCpu);
8802 }
8803
8804 /* CR0. */
8805 {
8806 /* CR0 MB1 bits. */
8807 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8808 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8809 { /* likely */ }
8810 else
8811 {
8812 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8813 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8814 return iemRaiseGeneralProtectionFault0(pVCpu);
8815 }
8816
8817 /* CR0 MBZ bits. */
8818 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8819 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8820 { /* likely */ }
8821 else
8822 {
8823 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8825 return iemRaiseGeneralProtectionFault0(pVCpu);
8826 }
8827 }
8828
8829 /* CR4. */
8830 {
8831 /* CR4 MB1 bits. */
8832 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8833 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8834 { /* likely */ }
8835 else
8836 {
8837 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8838 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8839 return iemRaiseGeneralProtectionFault0(pVCpu);
8840 }
8841
8842 /* CR4 MBZ bits. */
8843 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8844 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8845 { /* likely */ }
8846 else
8847 {
8848 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8849 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8850 return iemRaiseGeneralProtectionFault0(pVCpu);
8851 }
8852 }
8853
8854 /* Feature control MSR's LOCK and VMXON bits. */
8855 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8856 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8857 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8858 { /* likely */ }
8859 else
8860 {
8861 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8862 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8863 return iemRaiseGeneralProtectionFault0(pVCpu);
8864 }
8865
8866 /* Get the VMXON pointer from the location specified by the source memory operand. */
8867 RTGCPHYS GCPhysVmxon;
8868 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8869 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8870 { /* likely */ }
8871 else
8872 {
8873 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8874 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8875 return rcStrict;
8876 }
8877
8878 /* VMXON region pointer alignment. */
8879 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8880 { /* likely */ }
8881 else
8882 {
8883 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8884 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8885 iemVmxVmFailInvalid(pVCpu);
8886 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8887 return VINF_SUCCESS;
8888 }
8889
8890 /* VMXON physical-address width limits. */
8891 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8892 { /* likely */ }
8893 else
8894 {
8895 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8896 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8897 iemVmxVmFailInvalid(pVCpu);
8898 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8899 return VINF_SUCCESS;
8900 }
8901
8902 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8903 restriction imposed by our implementation. */
8904 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8905 { /* likely */ }
8906 else
8907 {
8908 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8909 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8910 iemVmxVmFailInvalid(pVCpu);
8911 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8912 return VINF_SUCCESS;
8913 }
8914
8915 /* Read the VMCS revision ID from the VMXON region. */
8916 VMXVMCSREVID VmcsRevId;
8917 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8918 if (RT_SUCCESS(rc))
8919 { /* likely */ }
8920 else
8921 {
8922 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8923 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8924 return rc;
8925 }
8926
8927 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8928 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8929 { /* likely */ }
8930 else
8931 {
8932 /* Revision ID mismatch. */
8933 if (!VmcsRevId.n.fIsShadowVmcs)
8934 {
8935 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8936 VmcsRevId.n.u31RevisionId));
8937 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8938 iemVmxVmFailInvalid(pVCpu);
8939 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8940 return VINF_SUCCESS;
8941 }
8942
8943 /* Shadow VMCS disallowed. */
8944 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8945 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8946 iemVmxVmFailInvalid(pVCpu);
8947 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8948 return VINF_SUCCESS;
8949 }
8950
8951 /*
8952 * Record that we're in VMX operation, block INIT, block and disable A20M.
8953 */
8954 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8955 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8956 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8957
8958 /* Clear address-range monitoring. */
8959 EMMonitorWaitClear(pVCpu);
8960 /** @todo NSTVMX: Intel PT. */
8961
8962 iemVmxVmSucceed(pVCpu);
8963 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8964 return VINF_SUCCESS;
8965 }
8966 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8967 {
8968 /* Nested-guest intercept. */
8969 if (pExitInfo)
8970 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8971 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8972 }
8973
8974 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8975
8976 /* CPL. */
8977 if (pVCpu->iem.s.uCpl > 0)
8978 {
8979 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8980 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8981 return iemRaiseGeneralProtectionFault0(pVCpu);
8982 }
8983
8984 /* VMXON when already in VMX root mode. */
8985 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8986 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8987 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8988 return VINF_SUCCESS;
8989}
8990
8991
8992/**
8993 * Implements 'VMXOFF'.
8994 *
8995 * @remarks Common VMX instruction checks are already expected to by the caller,
8996 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8997 */
8998IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8999{
9000 /* Nested-guest intercept. */
9001 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9002 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9003
9004 /* CPL. */
9005 if (pVCpu->iem.s.uCpl == 0)
9006 { /* likely */ }
9007 else
9008 {
9009 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9010 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9011 return iemRaiseGeneralProtectionFault0(pVCpu);
9012 }
9013
9014 /* Dual monitor treatment of SMIs and SMM. */
9015 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9016 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9017 { /* likely */ }
9018 else
9019 {
9020 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9021 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9022 return VINF_SUCCESS;
9023 }
9024
9025 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9026 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9027 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9028
9029 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9030 { /** @todo NSTVMX: Unblock SMI. */ }
9031
9032 EMMonitorWaitClear(pVCpu);
9033 /** @todo NSTVMX: Unblock and enable A20M. */
9034
9035 iemVmxVmSucceed(pVCpu);
9036 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9037 return VINF_SUCCESS;
9038}
9039
9040
9041/**
9042 * Implements 'VMXON'.
9043 */
9044IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9045{
9046 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9047}
9048
9049
9050/**
9051 * Implements 'VMLAUNCH'.
9052 */
9053IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9054{
9055 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9056}
9057
9058
9059/**
9060 * Implements 'VMRESUME'.
9061 */
9062IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9063{
9064 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9065}
9066
9067
9068/**
9069 * Implements 'VMPTRLD'.
9070 */
9071IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9072{
9073 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9074}
9075
9076
9077/**
9078 * Implements 'VMPTRST'.
9079 */
9080IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9081{
9082 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9083}
9084
9085
9086/**
9087 * Implements 'VMCLEAR'.
9088 */
9089IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9090{
9091 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9092}
9093
9094
9095/**
9096 * Implements 'VMWRITE' register.
9097 */
9098IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9099{
9100 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9101}
9102
9103
9104/**
9105 * Implements 'VMWRITE' memory.
9106 */
9107IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9108{
9109 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9110}
9111
9112
9113/**
9114 * Implements 'VMREAD' register (64-bit).
9115 */
9116IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9117{
9118 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9119}
9120
9121
9122/**
9123 * Implements 'VMREAD' register (32-bit).
9124 */
9125IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9126{
9127 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9128}
9129
9130
9131/**
9132 * Implements 'VMREAD' memory, 64-bit register.
9133 */
9134IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9135{
9136 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9137}
9138
9139
9140/**
9141 * Implements 'VMREAD' memory, 32-bit register.
9142 */
9143IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9144{
9145 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9146}
9147
9148
9149/**
9150 * Implements 'INVVPID'.
9151 */
9152IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9153{
9154 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9155}
9156
9157
9158/**
9159 * Implements VMX's implementation of PAUSE.
9160 */
9161IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9162{
9163 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9164 {
9165 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9166 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9167 return rcStrict;
9168 }
9169
9170 /*
9171 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9172 * a VM-exit, the instruction operates normally.
9173 */
9174 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9175 return VINF_SUCCESS;
9176}
9177
9178#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9179
9180
9181/**
9182 * Implements 'VMCALL'.
9183 */
9184IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9185{
9186#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9187 /* Nested-guest intercept. */
9188 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9189 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9190#endif
9191
9192 /* Join forces with vmmcall. */
9193 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9194}
9195
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