VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78927

Last change on this file since 78927 was 78927, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Comment.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78927 2019-06-03 10:40:33Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64FieldEnc The VMCS field encoding.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the VM-exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param uExitQual The VM-exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = uExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitQual The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
1984 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
1986 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1987 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1988 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1989 CPUMSetGuestCR0(pVCpu, uValidCr0);
1990 }
1991
1992 /* CR4. */
1993 {
1994 /* CR4 MB1 bits are not modified. */
1995 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1996 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1997 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1998 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1999 if (fHostInLongMode)
2000 uValidCr4 |= X86_CR4_PAE;
2001 else
2002 uValidCr4 &= ~X86_CR4_PCIDE;
2003 CPUMSetGuestCR4(pVCpu, uValidCr4);
2004 }
2005
2006 /* CR3 (host value validated while checking host-state during VM-entry). */
2007 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2008
2009 /* DR7. */
2010 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2011
2012 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2013
2014 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2015 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2016 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2017 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2018
2019 /* FS, GS bases are loaded later while we load host segment registers. */
2020
2021 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2022 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2023 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2024 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2025 {
2026 if (fHostInLongMode)
2027 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2028 else
2029 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2030 }
2031
2032 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2033
2034 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2035 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2036 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2037
2038 /* We don't support IA32_BNDCFGS MSR yet. */
2039}
2040
2041
2042/**
2043 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2044 *
2045 * @param pVCpu The cross context virtual CPU structure.
2046 */
2047IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2048{
2049 /*
2050 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2051 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2052 *
2053 * Warning! Be careful to not touch fields that are reserved by VT-x,
2054 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2055 */
2056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2057 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2058
2059 /* CS, SS, ES, DS, FS, GS. */
2060 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2061 {
2062 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2063 bool const fUnusable = RT_BOOL(HostSel == 0);
2064 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2065
2066 /* Selector. */
2067 pSelReg->Sel = HostSel;
2068 pSelReg->ValidSel = HostSel;
2069 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2070
2071 /* Limit. */
2072 pSelReg->u32Limit = 0xffffffff;
2073
2074 /* Base. */
2075 pSelReg->u64Base = 0;
2076
2077 /* Attributes. */
2078 if (iSegReg == X86_SREG_CS)
2079 {
2080 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2081 pSelReg->Attr.n.u1DescType = 1;
2082 pSelReg->Attr.n.u2Dpl = 0;
2083 pSelReg->Attr.n.u1Present = 1;
2084 pSelReg->Attr.n.u1Long = fHostInLongMode;
2085 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2086 pSelReg->Attr.n.u1Granularity = 1;
2087 Assert(!pSelReg->Attr.n.u1Unusable);
2088 Assert(!fUnusable);
2089 }
2090 else
2091 {
2092 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2093 pSelReg->Attr.n.u1DescType = 1;
2094 pSelReg->Attr.n.u2Dpl = 0;
2095 pSelReg->Attr.n.u1Present = 1;
2096 pSelReg->Attr.n.u1DefBig = 1;
2097 pSelReg->Attr.n.u1Granularity = 1;
2098 pSelReg->Attr.n.u1Unusable = fUnusable;
2099 }
2100 }
2101
2102 /* FS base. */
2103 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2104 || fHostInLongMode)
2105 {
2106 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2107 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2108 }
2109
2110 /* GS base. */
2111 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2112 || fHostInLongMode)
2113 {
2114 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2115 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2116 }
2117
2118 /* TR. */
2119 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2120 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2121 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2122 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2123 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2124 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2125 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2126 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2127 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2128 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2132
2133 /* LDTR (Warning! do not touch the base and limits here). */
2134 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2135 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2136 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2137 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2138
2139 /* GDTR. */
2140 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2141 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2142 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2143
2144 /* IDTR.*/
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2146 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2147 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2148}
2149
2150
2151/**
2152 * Checks host PDPTes as part of VM-exit.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param uExitReason The VM-exit reason (for logging purposes).
2156 */
2157IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2158{
2159 /*
2160 * Check host PDPTEs.
2161 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2162 */
2163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2164 const char *const pszFailure = "VMX-abort";
2165 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2166
2167 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2168 && !fHostInLongMode)
2169 {
2170 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2171 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2172 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2173 if (RT_SUCCESS(rc))
2174 {
2175 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2176 {
2177 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2178 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2179 { /* likely */ }
2180 else
2181 {
2182 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2183 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2184 }
2185 }
2186 }
2187 else
2188 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2189 }
2190
2191 NOREF(pszFailure);
2192 NOREF(uExitReason);
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2199 *
2200 * @returns VBox status code.
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param pszInstr The VMX instruction name (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Load host MSRs.
2208 * See Intel spec. 27.6 "Loading MSRs".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212
2213 /*
2214 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2215 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2216 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2217 */
2218 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2219 if (!cMsrs)
2220 return VINF_SUCCESS;
2221
2222 /*
2223 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2224 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2225 * implementation causes a VMX-abort followed by a triple-fault.
2226 */
2227 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2228 if (fIsMsrCountValid)
2229 { /* likely */ }
2230 else
2231 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2232
2233 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2234 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2235 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2236 if (RT_SUCCESS(rc))
2237 {
2238 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2239 Assert(pMsr);
2240 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2241 {
2242 if ( !pMsr->u32Reserved
2243 && pMsr->u32Msr != MSR_K8_FS_BASE
2244 && pMsr->u32Msr != MSR_K8_GS_BASE
2245 && pMsr->u32Msr != MSR_K6_EFER
2246 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2247 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2248 {
2249 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2250 if (rcStrict == VINF_SUCCESS)
2251 continue;
2252
2253 /*
2254 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2255 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2256 * recording the MSR index in the auxiliary info. field and indicated further by our
2257 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2258 * if possible, or come up with a better, generic solution.
2259 */
2260 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2261 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2262 ? kVmxVDiag_Vmexit_MsrLoadRing3
2263 : kVmxVDiag_Vmexit_MsrLoad;
2264 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2265 }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2268 }
2269 }
2270 else
2271 {
2272 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2273 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2274 }
2275
2276 NOREF(uExitReason);
2277 NOREF(pszFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Loads the host state as part of VM-exit.
2284 *
2285 * @returns Strict VBox status code.
2286 * @param pVCpu The cross context virtual CPU structure.
2287 * @param uExitReason The VM-exit reason (for logging purposes).
2288 */
2289IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2290{
2291 /*
2292 * Load host state.
2293 * See Intel spec. 27.5 "Loading Host State".
2294 */
2295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2296 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2297
2298 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2299 if ( CPUMIsGuestInLongMode(pVCpu)
2300 && !fHostInLongMode)
2301 {
2302 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2303 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2304 }
2305
2306 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2307 iemVmxVmexitLoadHostSegRegs(pVCpu);
2308
2309 /*
2310 * Load host RIP, RSP and RFLAGS.
2311 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2312 */
2313 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2314 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2315 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2316
2317 /* Clear address range monitoring. */
2318 EMMonitorWaitClear(pVCpu);
2319
2320 /* Perform the VMX transition (PGM updates). */
2321 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2322 if (rcStrict == VINF_SUCCESS)
2323 {
2324 /* Check host PDPTEs (only when we've fully switched page tables_. */
2325 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2326 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2327 if (RT_FAILURE(rc))
2328 {
2329 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2330 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2331 }
2332 }
2333 else if (RT_SUCCESS(rcStrict))
2334 {
2335 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2336 uExitReason));
2337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2338 }
2339 else
2340 {
2341 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2342 return VBOXSTRICTRC_VAL(rcStrict);
2343 }
2344
2345 Assert(rcStrict == VINF_SUCCESS);
2346
2347 /* Load MSRs from the VM-exit auto-load MSR area. */
2348 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2349 if (RT_FAILURE(rc))
2350 {
2351 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2352 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2353 }
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/**
2359 * Gets VM-exit instruction information along with any displacement for an
2360 * instruction VM-exit.
2361 *
2362 * @returns The VM-exit instruction information.
2363 * @param pVCpu The cross context virtual CPU structure.
2364 * @param uExitReason The VM-exit reason.
2365 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2366 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2367 * NULL.
2368 */
2369IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2370{
2371 RTGCPTR GCPtrDisp;
2372 VMXEXITINSTRINFO ExitInstrInfo;
2373 ExitInstrInfo.u = 0;
2374
2375 /*
2376 * Get and parse the ModR/M byte from our decoded opcodes.
2377 */
2378 uint8_t bRm;
2379 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2380 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2381 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2382 {
2383 /*
2384 * ModR/M indicates register addressing.
2385 *
2386 * The primary/secondary register operands are reported in the iReg1 or iReg2
2387 * fields depending on whether it is a read/write form.
2388 */
2389 uint8_t idxReg1;
2390 uint8_t idxReg2;
2391 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2392 {
2393 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2394 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2395 }
2396 else
2397 {
2398 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2399 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2400 }
2401 ExitInstrInfo.All.u2Scaling = 0;
2402 ExitInstrInfo.All.iReg1 = idxReg1;
2403 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2404 ExitInstrInfo.All.fIsRegOperand = 1;
2405 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2406 ExitInstrInfo.All.iSegReg = 0;
2407 ExitInstrInfo.All.iIdxReg = 0;
2408 ExitInstrInfo.All.fIdxRegInvalid = 1;
2409 ExitInstrInfo.All.iBaseReg = 0;
2410 ExitInstrInfo.All.fBaseRegInvalid = 1;
2411 ExitInstrInfo.All.iReg2 = idxReg2;
2412
2413 /* Displacement not applicable for register addressing. */
2414 GCPtrDisp = 0;
2415 }
2416 else
2417 {
2418 /*
2419 * ModR/M indicates memory addressing.
2420 */
2421 uint8_t uScale = 0;
2422 bool fBaseRegValid = false;
2423 bool fIdxRegValid = false;
2424 uint8_t iBaseReg = 0;
2425 uint8_t iIdxReg = 0;
2426 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2427 {
2428 /*
2429 * Parse the ModR/M, displacement for 16-bit addressing mode.
2430 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2431 */
2432 uint16_t u16Disp = 0;
2433 uint8_t const offDisp = offModRm + sizeof(bRm);
2434 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2435 {
2436 /* Displacement without any registers. */
2437 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2438 }
2439 else
2440 {
2441 /* Register (index and base). */
2442 switch (bRm & X86_MODRM_RM_MASK)
2443 {
2444 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2445 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2446 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2447 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2448 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2449 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2450 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2451 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2452 }
2453
2454 /* Register + displacement. */
2455 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2456 {
2457 case 0: break;
2458 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2459 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2460 default:
2461 {
2462 /* Register addressing, handled at the beginning. */
2463 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2464 break;
2465 }
2466 }
2467 }
2468
2469 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2470 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2471 }
2472 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2473 {
2474 /*
2475 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2476 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2477 */
2478 uint32_t u32Disp = 0;
2479 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2480 {
2481 /* Displacement without any registers. */
2482 uint8_t const offDisp = offModRm + sizeof(bRm);
2483 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2484 }
2485 else
2486 {
2487 /* Register (and perhaps scale, index and base). */
2488 uint8_t offDisp = offModRm + sizeof(bRm);
2489 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2490 if (iBaseReg == 4)
2491 {
2492 /* An SIB byte follows the ModR/M byte, parse it. */
2493 uint8_t bSib;
2494 uint8_t const offSib = offModRm + sizeof(bRm);
2495 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2496
2497 /* A displacement may follow SIB, update its offset. */
2498 offDisp += sizeof(bSib);
2499
2500 /* Get the scale. */
2501 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2502
2503 /* Get the index register. */
2504 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2505 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2506
2507 /* Get the base register. */
2508 iBaseReg = bSib & X86_SIB_BASE_MASK;
2509 fBaseRegValid = true;
2510 if (iBaseReg == 5)
2511 {
2512 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2513 {
2514 /* Mod is 0 implies a 32-bit displacement with no base. */
2515 fBaseRegValid = false;
2516 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2517 }
2518 else
2519 {
2520 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2521 iBaseReg = X86_GREG_xBP;
2522 }
2523 }
2524 }
2525
2526 /* Register + displacement. */
2527 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2528 {
2529 case 0: /* Handled above */ break;
2530 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2531 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2532 default:
2533 {
2534 /* Register addressing, handled at the beginning. */
2535 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2536 break;
2537 }
2538 }
2539 }
2540
2541 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2542 }
2543 else
2544 {
2545 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2546
2547 /*
2548 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2549 * See Intel instruction spec. 2.2 "IA-32e Mode".
2550 */
2551 uint64_t u64Disp = 0;
2552 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2553 if (fRipRelativeAddr)
2554 {
2555 /*
2556 * RIP-relative addressing mode.
2557 *
2558 * The displacement is 32-bit signed implying an offset range of +/-2G.
2559 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2560 */
2561 uint8_t const offDisp = offModRm + sizeof(bRm);
2562 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2563 }
2564 else
2565 {
2566 uint8_t offDisp = offModRm + sizeof(bRm);
2567
2568 /*
2569 * Register (and perhaps scale, index and base).
2570 *
2571 * REX.B extends the most-significant bit of the base register. However, REX.B
2572 * is ignored while determining whether an SIB follows the opcode. Hence, we
2573 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2574 *
2575 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2576 */
2577 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2578 if (iBaseReg == 4)
2579 {
2580 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2581 uint8_t bSib;
2582 uint8_t const offSib = offModRm + sizeof(bRm);
2583 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2584
2585 /* Displacement may follow SIB, update its offset. */
2586 offDisp += sizeof(bSib);
2587
2588 /* Get the scale. */
2589 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2590
2591 /* Get the index. */
2592 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2593 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2594
2595 /* Get the base. */
2596 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2597 fBaseRegValid = true;
2598 if (iBaseReg == 5)
2599 {
2600 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2601 {
2602 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2603 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2604 }
2605 else
2606 {
2607 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2608 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2609 }
2610 }
2611 }
2612 iBaseReg |= pVCpu->iem.s.uRexB;
2613
2614 /* Register + displacement. */
2615 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2616 {
2617 case 0: /* Handled above */ break;
2618 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2619 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2620 default:
2621 {
2622 /* Register addressing, handled at the beginning. */
2623 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2624 break;
2625 }
2626 }
2627 }
2628
2629 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2630 }
2631
2632 /*
2633 * The primary or secondary register operand is reported in iReg2 depending
2634 * on whether the primary operand is in read/write form.
2635 */
2636 uint8_t idxReg2;
2637 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2638 {
2639 idxReg2 = bRm & X86_MODRM_RM_MASK;
2640 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2641 idxReg2 |= pVCpu->iem.s.uRexB;
2642 }
2643 else
2644 {
2645 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2646 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2647 idxReg2 |= pVCpu->iem.s.uRexReg;
2648 }
2649 ExitInstrInfo.All.u2Scaling = uScale;
2650 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2651 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2652 ExitInstrInfo.All.fIsRegOperand = 0;
2653 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2654 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2655 ExitInstrInfo.All.iIdxReg = iIdxReg;
2656 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2657 ExitInstrInfo.All.iBaseReg = iBaseReg;
2658 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2659 ExitInstrInfo.All.iReg2 = idxReg2;
2660 }
2661
2662 /*
2663 * Handle exceptions to the norm for certain instructions.
2664 * (e.g. some instructions convey an instruction identity in place of iReg2).
2665 */
2666 switch (uExitReason)
2667 {
2668 case VMX_EXIT_GDTR_IDTR_ACCESS:
2669 {
2670 Assert(VMXINSTRID_IS_VALID(uInstrId));
2671 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2672 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2673 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2674 break;
2675 }
2676
2677 case VMX_EXIT_LDTR_TR_ACCESS:
2678 {
2679 Assert(VMXINSTRID_IS_VALID(uInstrId));
2680 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2681 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2682 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2683 break;
2684 }
2685
2686 case VMX_EXIT_RDRAND:
2687 case VMX_EXIT_RDSEED:
2688 {
2689 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2690 break;
2691 }
2692 }
2693
2694 /* Update displacement and return the constructed VM-exit instruction information field. */
2695 if (pGCPtrDisp)
2696 *pGCPtrDisp = GCPtrDisp;
2697
2698 return ExitInstrInfo.u;
2699}
2700
2701
2702/**
2703 * VMX VM-exit handler.
2704 *
2705 * @returns Strict VBox status code.
2706 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2707 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2708 * triple-fault.
2709 *
2710 * @param pVCpu The cross context virtual CPU structure.
2711 * @param uExitReason The VM-exit reason.
2712 *
2713 * @remarks Make sure VM-exit qualification is updated before calling this
2714 * function!
2715 */
2716IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2717{
2718# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2719 RT_NOREF2(pVCpu, uExitReason);
2720 return VINF_EM_RAW_EMULATE_INSTR;
2721# else
2722 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2723 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2724 | CPUMCTX_EXTRN_EFER /* MSRs */
2725 | CPUMCTX_EXTRN_SYSENTER_MSRS
2726 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2727 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2728 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2729 | CPUMCTX_EXTRN_TR /* Task register */
2730 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2731 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2732
2733 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2734 Assert(pVmcs);
2735
2736 /* Ensure VM-entry interruption information valid bit isn't set. */
2737 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2738
2739 /*
2740 * Update the VM-exit reason. Other VMCS data fields are expected to be updated by the caller already.
2741 */
2742 pVmcs->u32RoExitReason = uExitReason;
2743 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2744 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2745
2746 /*
2747 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2748 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2749 */
2750 {
2751 uint8_t uVector;
2752 uint32_t fFlags;
2753 uint32_t uErrCode;
2754 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2755 if (fInEventDelivery)
2756 {
2757 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2758 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2759 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2760 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2761 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2762 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2763 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2764 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2765 }
2766 }
2767
2768 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2769 Assert(pVmcs->u64RoIoRcx.u == 0);
2770 Assert(pVmcs->u64RoIoRsi.u == 0);
2771 Assert(pVmcs->u64RoIoRdi.u == 0);
2772 Assert(pVmcs->u64RoIoRip.u == 0);
2773
2774 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2775 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2776 {
2777 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2778 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2779 }
2780
2781 /*
2782 * Save the guest state back into the VMCS.
2783 * We only need to save the state when the VM-entry was successful.
2784 */
2785 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2786 if (!fVmentryFailed)
2787 {
2788 /*
2789 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2790 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2791 *
2792 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2793 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2794 * as guest-CPU state would not been modified. Hence for now, we do this only when
2795 * the VM-entry succeeded.
2796 */
2797 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2798 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2799 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2800 {
2801 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2802 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2803 else
2804 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2805 }
2806
2807 /*
2808 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2809 * occurs in enclave mode/SMM which we don't support yet.
2810 *
2811 * If we ever add support for it, we can pass just the lower bits to the functions
2812 * below, till then an assert should suffice.
2813 */
2814 Assert(!RT_HI_U16(uExitReason));
2815
2816 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2817 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2818 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2819 if (RT_SUCCESS(rc))
2820 { /* likely */ }
2821 else
2822 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2823
2824 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2825 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2826 }
2827 else
2828 {
2829 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2830 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2831 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2832 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2833 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2834 }
2835
2836 /*
2837 * Clear any pending VMX nested-guest force-flags.
2838 * These force-flags have no effect on guest execution and will
2839 * be re-evaluated and setup on the next nested-guest VM-entry.
2840 */
2841 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2842 | VMCPU_FF_VMX_MTF
2843 | VMCPU_FF_VMX_APIC_WRITE
2844 | VMCPU_FF_VMX_INT_WINDOW
2845 | VMCPU_FF_VMX_NMI_WINDOW);
2846
2847 /* Restore the host (outer guest) state. */
2848 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2849 if (RT_SUCCESS(rcStrict))
2850 {
2851 Assert(rcStrict == VINF_SUCCESS);
2852 rcStrict = VINF_VMX_VMEXIT;
2853 }
2854 else
2855 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2856
2857 /* Notify HM that we've completed the VM-exit. */
2858 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2859
2860 /* We're no longer in nested-guest execution mode. */
2861 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2862
2863# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2864 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2865 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2866 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2867 if (rcSched != VINF_SUCCESS)
2868 iemSetPassUpStatus(pVCpu, rcSched);
2869# endif
2870 return rcStrict;
2871# endif
2872}
2873
2874
2875/**
2876 * VMX VM-exit handler for VM-exits due to instruction execution.
2877 *
2878 * This is intended for instructions where the caller provides all the relevant
2879 * VM-exit information.
2880 *
2881 * @returns Strict VBox status code.
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param pExitInfo Pointer to the VM-exit information.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2886{
2887 /*
2888 * For instructions where any of the following fields are not applicable:
2889 * - VM-exit instruction info. is undefined.
2890 * - VM-exit qualification must be cleared.
2891 * - VM-exit guest-linear address is undefined.
2892 * - VM-exit guest-physical address is undefined.
2893 *
2894 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2895 * instruction execution. For VM-exits that are not due to instruction execution this
2896 * field is undefined.
2897 *
2898 * In our implementation in IEM, all undefined fields are generally cleared. However,
2899 * if the caller supplies information (from say the physical CPU directly) it is
2900 * then possible that the undefined fields are not cleared.
2901 *
2902 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2903 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2904 */
2905 Assert(pExitInfo);
2906 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2907 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2908 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2909
2910 /* Update all the relevant fields from the VM-exit instruction information struct. */
2911 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2912 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2913 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2914 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2915 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2916
2917 /* Perform the VM-exit. */
2918 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2919}
2920
2921
2922/**
2923 * VMX VM-exit handler for VM-exits due to instruction execution.
2924 *
2925 * This is intended for instructions that only provide the VM-exit instruction
2926 * length.
2927 *
2928 * @param pVCpu The cross context virtual CPU structure.
2929 * @param uExitReason The VM-exit reason.
2930 * @param cbInstr The instruction length in bytes.
2931 */
2932IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2933{
2934 VMXVEXITINFO ExitInfo;
2935 RT_ZERO(ExitInfo);
2936 ExitInfo.uReason = uExitReason;
2937 ExitInfo.cbInstr = cbInstr;
2938
2939#ifdef VBOX_STRICT
2940 /*
2941 * To prevent us from shooting ourselves in the foot.
2942 * The follow instructions should convey more than just the instruction length.
2943 */
2944 switch (uExitReason)
2945 {
2946 case VMX_EXIT_INVEPT:
2947 case VMX_EXIT_INVPCID:
2948 case VMX_EXIT_LDTR_TR_ACCESS:
2949 case VMX_EXIT_GDTR_IDTR_ACCESS:
2950 case VMX_EXIT_VMCLEAR:
2951 case VMX_EXIT_VMPTRLD:
2952 case VMX_EXIT_VMPTRST:
2953 case VMX_EXIT_VMREAD:
2954 case VMX_EXIT_VMWRITE:
2955 case VMX_EXIT_VMXON:
2956 case VMX_EXIT_XRSTORS:
2957 case VMX_EXIT_XSAVES:
2958 case VMX_EXIT_RDRAND:
2959 case VMX_EXIT_RDSEED:
2960 case VMX_EXIT_IO_INSTR:
2961 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2962 break;
2963 }
2964#endif
2965
2966 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2967}
2968
2969
2970/**
2971 * VMX VM-exit handler for VM-exits due to instruction execution.
2972 *
2973 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2974 * instruction information and VM-exit qualification fields.
2975 *
2976 * @param pVCpu The cross context virtual CPU structure.
2977 * @param uExitReason The VM-exit reason.
2978 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2979 * @param cbInstr The instruction length in bytes.
2980 *
2981 * @remarks Do not use this for INS/OUTS instruction.
2982 */
2983IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2984{
2985 VMXVEXITINFO ExitInfo;
2986 RT_ZERO(ExitInfo);
2987 ExitInfo.uReason = uExitReason;
2988 ExitInfo.cbInstr = cbInstr;
2989
2990 /*
2991 * Update the VM-exit qualification field with displacement bytes.
2992 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2993 */
2994 switch (uExitReason)
2995 {
2996 case VMX_EXIT_INVEPT:
2997 case VMX_EXIT_INVPCID:
2998 case VMX_EXIT_INVVPID:
2999 case VMX_EXIT_LDTR_TR_ACCESS:
3000 case VMX_EXIT_GDTR_IDTR_ACCESS:
3001 case VMX_EXIT_VMCLEAR:
3002 case VMX_EXIT_VMPTRLD:
3003 case VMX_EXIT_VMPTRST:
3004 case VMX_EXIT_VMREAD:
3005 case VMX_EXIT_VMWRITE:
3006 case VMX_EXIT_VMXON:
3007 case VMX_EXIT_XRSTORS:
3008 case VMX_EXIT_XSAVES:
3009 case VMX_EXIT_RDRAND:
3010 case VMX_EXIT_RDSEED:
3011 {
3012 /* Construct the VM-exit instruction information. */
3013 RTGCPTR GCPtrDisp;
3014 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3015
3016 /* Update the VM-exit instruction information. */
3017 ExitInfo.InstrInfo.u = uInstrInfo;
3018
3019 /* Update the VM-exit qualification. */
3020 ExitInfo.u64Qual = GCPtrDisp;
3021 break;
3022 }
3023
3024 default:
3025 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3026 break;
3027 }
3028
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030}
3031
3032
3033/**
3034 * VMX VM-exit handler for VM-exits due to INVLPG.
3035 *
3036 * @returns Strict VBox status code.
3037 * @param pVCpu The cross context virtual CPU structure.
3038 * @param GCPtrPage The guest-linear address of the page being invalidated.
3039 * @param cbInstr The instruction length in bytes.
3040 */
3041IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3042{
3043 VMXVEXITINFO ExitInfo;
3044 RT_ZERO(ExitInfo);
3045 ExitInfo.uReason = VMX_EXIT_INVLPG;
3046 ExitInfo.cbInstr = cbInstr;
3047 ExitInfo.u64Qual = GCPtrPage;
3048 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3049
3050 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3051}
3052
3053
3054/**
3055 * VMX VM-exit handler for VM-exits due to LMSW.
3056 *
3057 * @returns Strict VBox status code.
3058 * @param pVCpu The cross context virtual CPU structure.
3059 * @param uGuestCr0 The current guest CR0.
3060 * @param pu16NewMsw The machine-status word specified in LMSW's source
3061 * operand. This will be updated depending on the VMX
3062 * guest/host CR0 mask if LMSW is not intercepted.
3063 * @param GCPtrEffDst The guest-linear address of the source operand in case
3064 * of a memory operand. For register operand, pass
3065 * NIL_RTGCPTR.
3066 * @param cbInstr The instruction length in bytes.
3067 */
3068IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3069 uint8_t cbInstr)
3070{
3071 Assert(pu16NewMsw);
3072
3073 uint16_t const uNewMsw = *pu16NewMsw;
3074 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3075 {
3076 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3077
3078 VMXVEXITINFO ExitInfo;
3079 RT_ZERO(ExitInfo);
3080 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3081 ExitInfo.cbInstr = cbInstr;
3082
3083 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3084 if (fMemOperand)
3085 {
3086 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3087 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3088 }
3089
3090 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3094
3095 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3096 }
3097
3098 /*
3099 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3100 * CR0 guest/host mask must be left unmodified.
3101 *
3102 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3103 */
3104 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3105 Assert(pVmcs);
3106 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3107 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3108 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3109
3110 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3111}
3112
3113
3114/**
3115 * VMX VM-exit handler for VM-exits due to CLTS.
3116 *
3117 * @returns Strict VBox status code.
3118 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3119 * VM-exit but must not modify the guest CR0.TS bit.
3120 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3121 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3122 * CR0 fixed bits in VMX operation).
3123 * @param pVCpu The cross context virtual CPU structure.
3124 * @param cbInstr The instruction length in bytes.
3125 */
3126IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3127{
3128 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3129 Assert(pVmcs);
3130
3131 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3132 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3133
3134 /*
3135 * If CR0.TS is owned by the host:
3136 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3137 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3138 * CLTS instruction completes without clearing CR0.TS.
3139 *
3140 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3141 */
3142 if (fGstHostMask & X86_CR0_TS)
3143 {
3144 if (fReadShadow & X86_CR0_TS)
3145 {
3146 Log2(("clts: Guest intercept -> VM-exit\n"));
3147
3148 VMXVEXITINFO ExitInfo;
3149 RT_ZERO(ExitInfo);
3150 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3151 ExitInfo.cbInstr = cbInstr;
3152 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3153 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3154 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3155 }
3156
3157 return VINF_VMX_MODIFIES_BEHAVIOR;
3158 }
3159
3160 /*
3161 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3162 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3163 */
3164 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3165}
3166
3167
3168/**
3169 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3170 * (CR0/CR4 write).
3171 *
3172 * @returns Strict VBox status code.
3173 * @param pVCpu The cross context virtual CPU structure.
3174 * @param iCrReg The control register (either CR0 or CR4).
3175 * @param uGuestCrX The current guest CR0/CR4.
3176 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3177 * if no VM-exit is caused.
3178 * @param iGReg The general register from which the CR0/CR4 value is
3179 * being loaded.
3180 * @param cbInstr The instruction length in bytes.
3181 */
3182IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3183 uint8_t cbInstr)
3184{
3185 Assert(puNewCrX);
3186 Assert(iCrReg == 0 || iCrReg == 4);
3187 Assert(iGReg < X86_GREG_COUNT);
3188
3189 uint64_t const uNewCrX = *puNewCrX;
3190 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3191 {
3192 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3193
3194 VMXVEXITINFO ExitInfo;
3195 RT_ZERO(ExitInfo);
3196 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3197 ExitInfo.cbInstr = cbInstr;
3198 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3201 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3202 }
3203
3204 /*
3205 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3206 * must not be modified the instruction.
3207 *
3208 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3209 */
3210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3211 Assert(pVmcs);
3212 uint64_t uGuestCrX;
3213 uint64_t fGstHostMask;
3214 if (iCrReg == 0)
3215 {
3216 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3217 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3218 fGstHostMask = pVmcs->u64Cr0Mask.u;
3219 }
3220 else
3221 {
3222 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3223 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3224 fGstHostMask = pVmcs->u64Cr4Mask.u;
3225 }
3226
3227 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3228 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3229}
3230
3231
3232/**
3233 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3234 *
3235 * @returns VBox strict status code.
3236 * @param pVCpu The cross context virtual CPU structure.
3237 * @param iGReg The general register to which the CR3 value is being stored.
3238 * @param cbInstr The instruction length in bytes.
3239 */
3240IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3241{
3242 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3243 Assert(pVmcs);
3244 Assert(iGReg < X86_GREG_COUNT);
3245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3246
3247 /*
3248 * If the CR3-store exiting control is set, we must cause a VM-exit.
3249 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3250 */
3251 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3252 {
3253 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3254
3255 VMXVEXITINFO ExitInfo;
3256 RT_ZERO(ExitInfo);
3257 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3258 ExitInfo.cbInstr = cbInstr;
3259 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3260 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3261 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3262 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3263 }
3264
3265 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3266}
3267
3268
3269/**
3270 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3271 *
3272 * @returns VBox strict status code.
3273 * @param pVCpu The cross context virtual CPU structure.
3274 * @param uNewCr3 The new CR3 value.
3275 * @param iGReg The general register from which the CR3 value is being
3276 * loaded.
3277 * @param cbInstr The instruction length in bytes.
3278 */
3279IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3280{
3281 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3282 Assert(pVmcs);
3283 Assert(iGReg < X86_GREG_COUNT);
3284
3285 /*
3286 * If the CR3-load exiting control is set and the new CR3 value does not
3287 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3288 *
3289 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3290 */
3291 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3292 {
3293 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3294 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3295
3296 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3297 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3298 if (!fIntercept)
3299 {
3300 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3301 {
3302 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3303 if (uNewCr3 != uCr3TargetValue)
3304 {
3305 fIntercept = true;
3306 break;
3307 }
3308 }
3309 }
3310
3311 if (fIntercept)
3312 {
3313 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3314
3315 VMXVEXITINFO ExitInfo;
3316 RT_ZERO(ExitInfo);
3317 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3318 ExitInfo.cbInstr = cbInstr;
3319 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3321 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3322 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3323 }
3324 }
3325
3326 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3327}
3328
3329
3330/**
3331 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3332 *
3333 * @returns VBox strict status code.
3334 * @param pVCpu The cross context virtual CPU structure.
3335 * @param iGReg The general register to which the CR8 value is being stored.
3336 * @param cbInstr The instruction length in bytes.
3337 */
3338IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3339{
3340 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3341 Assert(pVmcs);
3342 Assert(iGReg < X86_GREG_COUNT);
3343
3344 /*
3345 * If the CR8-store exiting control is set, we must cause a VM-exit.
3346 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3347 */
3348 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3349 {
3350 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3351
3352 VMXVEXITINFO ExitInfo;
3353 RT_ZERO(ExitInfo);
3354 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3355 ExitInfo.cbInstr = cbInstr;
3356 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3357 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3358 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3359 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3360 }
3361
3362 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3363}
3364
3365
3366/**
3367 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3368 *
3369 * @returns VBox strict status code.
3370 * @param pVCpu The cross context virtual CPU structure.
3371 * @param iGReg The general register from which the CR8 value is being
3372 * loaded.
3373 * @param cbInstr The instruction length in bytes.
3374 */
3375IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3376{
3377 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3378 Assert(pVmcs);
3379 Assert(iGReg < X86_GREG_COUNT);
3380
3381 /*
3382 * If the CR8-load exiting control is set, we must cause a VM-exit.
3383 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3384 */
3385 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3386 {
3387 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3388
3389 VMXVEXITINFO ExitInfo;
3390 RT_ZERO(ExitInfo);
3391 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3392 ExitInfo.cbInstr = cbInstr;
3393 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3394 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3395 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3396 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3397 }
3398
3399 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3400}
3401
3402
3403/**
3404 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3405 * GReg,DRx' (DRx read).
3406 *
3407 * @returns VBox strict status code.
3408 * @param pVCpu The cross context virtual CPU structure.
3409 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3410 * VMXINSTRID_MOV_FROM_DRX).
3411 * @param iDrReg The debug register being accessed.
3412 * @param iGReg The general register to/from which the DRx value is being
3413 * store/loaded.
3414 * @param cbInstr The instruction length in bytes.
3415 */
3416IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3417 uint8_t cbInstr)
3418{
3419 Assert(iDrReg <= 7);
3420 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3421 Assert(iGReg < X86_GREG_COUNT);
3422
3423 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3424 Assert(pVmcs);
3425
3426 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3427 {
3428 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3429 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3430 VMXVEXITINFO ExitInfo;
3431 RT_ZERO(ExitInfo);
3432 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3433 ExitInfo.cbInstr = cbInstr;
3434 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3435 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3436 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3437 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3438 }
3439
3440 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3441}
3442
3443
3444/**
3445 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3446 *
3447 * @returns VBox strict status code.
3448 * @param pVCpu The cross context virtual CPU structure.
3449 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3450 * VMXINSTRID_IO_OUT).
3451 * @param u16Port The I/O port being accessed.
3452 * @param fImm Whether the I/O port was encoded using an immediate operand
3453 * or the implicit DX register.
3454 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3455 * @param cbInstr The instruction length in bytes.
3456 */
3457IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3458 uint8_t cbInstr)
3459{
3460 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3461 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3462
3463 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3464 if (fIntercept)
3465 {
3466 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3467 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3468 VMXVEXITINFO ExitInfo;
3469 RT_ZERO(ExitInfo);
3470 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3471 ExitInfo.cbInstr = cbInstr;
3472 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3473 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3474 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3476 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3477 }
3478
3479 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480}
3481
3482
3483/**
3484 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3485 *
3486 * @returns VBox strict status code.
3487 * @param pVCpu The cross context virtual CPU structure.
3488 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3489 * VMXINSTRID_IO_OUTS).
3490 * @param u16Port The I/O port being accessed.
3491 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3492 * @param fRep Whether the instruction has a REP prefix or not.
3493 * @param ExitInstrInfo The VM-exit instruction info. field.
3494 * @param cbInstr The instruction length in bytes.
3495 */
3496IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3497 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3498{
3499 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3500 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3501 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3502 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3503 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3504
3505 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3506 if (fIntercept)
3507 {
3508 /*
3509 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3510 */
3511 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3512 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3513 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3514 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3515 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3516
3517 uint32_t uDirection;
3518 uint64_t uGuestLinearAddr;
3519 if (uInstrId == VMXINSTRID_IO_INS)
3520 {
3521 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3522 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3523 }
3524 else
3525 {
3526 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3527 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3528 }
3529
3530 /*
3531 * If the segment is unusable, the guest-linear address in undefined.
3532 * We shall clear it for consistency.
3533 *
3534 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3535 */
3536 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3537 uGuestLinearAddr = 0;
3538
3539 VMXVEXITINFO ExitInfo;
3540 RT_ZERO(ExitInfo);
3541 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3542 ExitInfo.cbInstr = cbInstr;
3543 ExitInfo.InstrInfo = ExitInstrInfo;
3544 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3545 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3546 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3547 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3548 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3549 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3550 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3551 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3552 }
3553
3554 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3555}
3556
3557
3558/**
3559 * VMX VM-exit handler for VM-exits due to MWAIT.
3560 *
3561 * @returns VBox strict status code.
3562 * @param pVCpu The cross context virtual CPU structure.
3563 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3564 * @param cbInstr The instruction length in bytes.
3565 */
3566IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3567{
3568 VMXVEXITINFO ExitInfo;
3569 RT_ZERO(ExitInfo);
3570 ExitInfo.uReason = VMX_EXIT_MWAIT;
3571 ExitInfo.cbInstr = cbInstr;
3572 ExitInfo.u64Qual = fMonitorHwArmed;
3573 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3574}
3575
3576
3577/**
3578 * VMX VM-exit handler for VM-exits due to PAUSE.
3579 *
3580 * @returns VBox strict status code.
3581 * @param pVCpu The cross context virtual CPU structure.
3582 * @param cbInstr The instruction length in bytes.
3583 */
3584IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3585{
3586 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3587 Assert(pVmcs);
3588
3589 /*
3590 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3591 * "PAUSE-loop exiting" control.
3592 *
3593 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3594 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3595 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3596 * a VM-exit.
3597 *
3598 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3599 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3600 */
3601 bool fIntercept = false;
3602 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3603 fIntercept = true;
3604 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3605 && pVCpu->iem.s.uCpl == 0)
3606 {
3607 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3608
3609 /*
3610 * A previous-PAUSE-tick value of 0 is used to identify the first time
3611 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3612 * consider this to be the first execution of PAUSE in a loop according
3613 * to the Intel.
3614 *
3615 * All subsequent records for the previous-PAUSE-tick we ensure that it
3616 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3617 */
3618 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3619 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3620 uint64_t const uTick = TMCpuTickGet(pVCpu);
3621 uint32_t const uPleGap = pVmcs->u32PleGap;
3622 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3623 if ( *puPrevPauseTick == 0
3624 || uTick - *puPrevPauseTick > uPleGap)
3625 *puFirstPauseLoopTick = uTick;
3626 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3627 fIntercept = true;
3628
3629 *puPrevPauseTick = uTick | 1;
3630 }
3631
3632 if (fIntercept)
3633 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3634
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636}
3637
3638
3639/**
3640 * VMX VM-exit handler for VM-exits due to task switches.
3641 *
3642 * @returns VBox strict status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 * @param enmTaskSwitch The cause of the task switch.
3645 * @param SelNewTss The selector of the new TSS.
3646 * @param cbInstr The instruction length in bytes.
3647 */
3648IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3649{
3650 /*
3651 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3652 *
3653 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3654 * instruction or delivery of the exception generated by one of these instructions
3655 * lead to a task switch through a task gate in the IDT, we need to provide the
3656 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3657 * leaves the VM-exit instruction length field undefined.
3658 *
3659 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3660 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3661 */
3662 Assert(cbInstr <= 15);
3663
3664 uint8_t uType;
3665 switch (enmTaskSwitch)
3666 {
3667 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3668 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3669 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3670 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3671 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3672 }
3673
3674 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3675 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3676 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3677 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3678 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3679}
3680
3681
3682/**
3683 * VMX VM-exit handler for VM-exits due to task switches.
3684 *
3685 * This is intended for task switches where the caller provides all the relevant
3686 * VM-exit information.
3687 *
3688 * @returns VBox strict status code.
3689 * @param pVCpu The cross context virtual CPU structure.
3690 * @param pExitInfo Pointer to the VM-exit information.
3691 * @param pExitEventInfo Pointer to the VM-exit event information.
3692 */
3693IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PVMXVEXITINFO pExitInfo, PVMXVEXITEVENTINFO pExitEventInfo)
3694{
3695 Assert(pExitInfo);
3696 Assert(pExitEventInfo);
3697
3698 /* The VM-exit qualification is mandatory for all task-switch VM-exits. */
3699 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3700 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3701
3702 /*
3703 * Figure out if an instruction was the source of the task switch.
3704 *
3705 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3706 * of an event generated by a software interrupt (INT-N), privileged software
3707 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3708 * the instruction length.
3709 */
3710 bool fHasInstrLen;
3711 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3712 {
3713 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3714 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3715 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3716 if (fIdtVectInfoValid)
3717 {
3718 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3719 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3720 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3721
3722 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3723 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3724 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3725 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3726 fHasInstrLen = true;
3727 else
3728 fHasInstrLen = false;
3729 }
3730 else
3731 fHasInstrLen = false;
3732 }
3733 else
3734 {
3735 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3736 fHasInstrLen = true;
3737 }
3738
3739 if (fHasInstrLen)
3740 {
3741 Assert(pExitInfo->cbInstr > 0);
3742 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3743 }
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3745}
3746
3747
3748/**
3749 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3750 *
3751 * @returns VBox strict status code.
3752 * @param pVCpu The cross context virtual CPU structure.
3753 */
3754IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3755{
3756 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3757 Assert(pVmcs);
3758
3759 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3760 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3761 {
3762 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3763 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3764
3765 /*
3766 * Calculate the current VMX-preemption timer value.
3767 * Only if the value has reached zero, we cause the VM-exit.
3768 */
3769 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3770 if (!uPreemptTimer)
3771 {
3772 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3773 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3774 pVmcs->u32PreemptTimer = 0;
3775
3776 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3777 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3778 }
3779 }
3780
3781 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3782}
3783
3784
3785/**
3786 * VMX VM-exit handler for VM-exits due to external interrupts.
3787 *
3788 * @returns VBox strict status code.
3789 * @param pVCpu The cross context virtual CPU structure.
3790 * @param uVector The external interrupt vector (pass 0 if the interrupt
3791 * is still pending since we typically won't know the
3792 * vector).
3793 * @param fIntPending Whether the external interrupt is pending or
3794 * acknowledged in the interrupt controller.
3795 */
3796IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3797{
3798 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3799 Assert(pVmcs);
3800 Assert(fIntPending || uVector == 0);
3801
3802 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3803 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3804 * functions require prior checking of a blanket intercept and which don't.
3805 * It is better for the caller to check a blanket intercept performance wise
3806 * than making a function call. Leaving this as a todo because it is more
3807 * a performance issue. */
3808
3809 /* The VM-exit is subject to "External interrupt exiting" being set. */
3810 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3811 {
3812 if (fIntPending)
3813 {
3814 /*
3815 * If the interrupt is pending and we don't need to acknowledge the
3816 * interrupt on VM-exit, cause the VM-exit immediately.
3817 *
3818 * See Intel spec 25.2 "Other Causes Of VM Exits".
3819 */
3820 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3821 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3822
3823 /*
3824 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3825 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3826 * acknowledged that the interrupt has been consumed.
3827 */
3828 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3829 }
3830
3831 /*
3832 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3833 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3834 * all set, we cause the VM-exit now. We need to record the external interrupt that
3835 * just occurred in the VM-exit interruption information field.
3836 *
3837 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3838 */
3839 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3840 {
3841 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3842 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3843 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3844 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3845 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3846 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3847 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3848 }
3849 }
3850
3851 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3852}
3853
3854
3855/**
3856 * VMX VM-exit handler for VM-exits due to NMIs.
3857 *
3858 * @returns VBox strict status code.
3859 * @param pVCpu The cross context virtual CPU structure.
3860 *
3861 * @remarks This function might import externally kept DR6 if necessary.
3862 */
3863IEM_STATIC VBOXSTRICTRC iemVmxVmexitNmi(PVMCPU pVCpu)
3864{
3865 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3866 Assert(pVmcs);
3867 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
3868 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents);
3869 NOREF(pVmcs);
3870 return iemVmxVmexitEvent(pVCpu, X86_XCPT_NMI, IEM_XCPT_FLAGS_T_CPU_XCPT, 0 /* uErrCode */, 0 /* uCr2 */, 0 /* cbInstr */);
3871}
3872
3873
3874/**
3875 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3876 *
3877 * @returns VBox strict status code.
3878 * @param pVCpu The cross context virtual CPU structure.
3879 * @param uVector The SIPI vector.
3880 */
3881IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3882{
3883 iemVmxVmcsSetExitQual(pVCpu, uVector);
3884 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3885}
3886
3887
3888/**
3889 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3890 * an event.
3891 *
3892 * @returns VBox strict status code.
3893 * @param pVCpu The cross context virtual CPU structure.
3894 */
3895IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3896{
3897 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3898 Assert(pVmcs);
3899
3900 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3901 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3902 {
3903 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3904 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3905 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3906 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3907 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3908 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3909 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3910 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3911 iemVmxVmcsSetExitQual(pVCpu, 0);
3912 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3913
3914 /*
3915 * A VM-exit is not considered to occur during event delivery when the original
3916 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3917 * using the exception bitmap).
3918 *
3919 * Therefore, we must clear the original event from the IDT-vectoring fields which
3920 * would've been recorded before causing the VM-exit.
3921 *
3922 * 27.2.3 "Information for VM Exits During Event Delivery"
3923 */
3924 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3925 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3926
3927 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3928 }
3929
3930 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3931}
3932
3933
3934/**
3935 * VMX VM-exit handler for VM-exits due to delivery of an event.
3936 *
3937 * @returns VBox strict status code.
3938 * @param pVCpu The cross context virtual CPU structure.
3939 * @param uVector The interrupt / exception vector.
3940 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3941 * @param uErrCode The error code associated with the event.
3942 * @param uCr2 The CR2 value in case of a \#PF exception.
3943 * @param cbInstr The instruction length in bytes.
3944 */
3945IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3946 uint8_t cbInstr)
3947{
3948 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3949 Assert(pVmcs);
3950
3951 /*
3952 * If the event is being injected as part of VM-entry, it is -not- subject to event
3953 * intercepts in the nested-guest. However, secondary exceptions that occur during
3954 * injection of any event -are- subject to event interception.
3955 *
3956 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3957 */
3958 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3959 {
3960 /*
3961 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3962 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3963 *
3964 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3965 */
3966 if ( uVector == X86_XCPT_NMI
3967 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3968 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3969 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3970 else
3971 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3972
3973 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3974 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3975 }
3976
3977 /*
3978 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3979 * If not, the caller will continue delivery of the external interrupt as it would
3980 * normally. The interrupt is no longer pending in the interrupt controller at this
3981 * point.
3982 */
3983 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3984 {
3985 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3986 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3987 }
3988
3989 /*
3990 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
3991 * generated by INT3, INT1 (ICEBP) and INTO respectively.
3992 */
3993 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3994 bool fIntercept = false;
3995 bool fIsHwXcpt = false;
3996 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3997 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3998 {
3999 fIsHwXcpt = true;
4000
4001 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4002 if (uVector == X86_XCPT_NMI)
4003 {
4004 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
4005 fIntercept = true;
4006 }
4007 else
4008 {
4009 /* Page-faults are subject to masking using its error code. */
4010 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4011 if (uVector == X86_XCPT_PF)
4012 {
4013 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4014 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4015 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4016 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4017 }
4018
4019 /* Consult the exception bitmap for all other hardware exceptions. */
4020 Assert(uVector <= X86_XCPT_LAST);
4021 if (fXcptBitmap & RT_BIT(uVector))
4022 fIntercept = true;
4023 }
4024 }
4025 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4026
4027 /*
4028 * Now that we've determined whether the software interrupt or hardware exception
4029 * causes a VM-exit, we need to construct the relevant VM-exit information and
4030 * cause the VM-exit.
4031 */
4032 if (fIntercept)
4033 {
4034 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4035
4036 /* Construct the rest of the event related information fields and cause the VM-exit. */
4037 uint64_t uExitQual = 0;
4038 if (fIsHwXcpt)
4039 {
4040 if (uVector == X86_XCPT_PF)
4041 {
4042 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4043 uExitQual = uCr2;
4044 }
4045 else if (uVector == X86_XCPT_DB)
4046 {
4047 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4048 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4049 }
4050 }
4051
4052 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4053 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4054 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4055 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4056 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4057 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4058 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4059 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4060 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4061 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4062 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4063
4064 /*
4065 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4066 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4067 * length.
4068 */
4069 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4070 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4071 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4072 else
4073 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4074
4075 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4076 }
4077
4078 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4079}
4080
4081
4082/**
4083 * VMX VM-exit handler for VM-exits due to a triple fault.
4084 *
4085 * @returns VBox strict status code.
4086 * @param pVCpu The cross context virtual CPU structure.
4087 */
4088IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4089{
4090 /*
4091 * A VM-exit is not considered to occur during event delivery when the original
4092 * event results in a triple-fault.
4093 *
4094 * Therefore, we must clear the original event from the IDT-vectoring fields which
4095 * would've been recorded before causing the VM-exit.
4096 *
4097 * 27.2.3 "Information for VM Exits During Event Delivery"
4098 */
4099 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4100 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4101
4102 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4103}
4104
4105
4106/**
4107 * VMX VM-exit handler for APIC-accesses.
4108 *
4109 * @param pVCpu The cross context virtual CPU structure.
4110 * @param offAccess The offset of the register being accessed.
4111 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4112 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4113 */
4114IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4115{
4116 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4117
4118 VMXAPICACCESS enmAccess;
4119 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4120 if (fInEventDelivery)
4121 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4122 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4123 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4124 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4125 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4126 else
4127 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4128
4129 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4130 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4131 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4132 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4133}
4134
4135
4136/**
4137 * VMX VM-exit handler for APIC-write VM-exits.
4138 *
4139 * @param pVCpu The cross context virtual CPU structure.
4140 * @param offApic The write to the virtual-APIC page offset that caused this
4141 * VM-exit.
4142 */
4143IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4144{
4145 Assert(offApic < XAPIC_OFF_END + 4);
4146
4147 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4148 offApic &= UINT16_C(0xfff);
4149 iemVmxVmcsSetExitQual(pVCpu, offApic);
4150 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4151}
4152
4153
4154/**
4155 * VMX VM-exit handler for virtualized-EOIs.
4156 *
4157 * @param pVCpu The cross context virtual CPU structure.
4158 */
4159IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4160{
4161 iemVmxVmcsSetExitQual(pVCpu, uVector);
4162 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4163}
4164
4165
4166/**
4167 * Sets virtual-APIC write emulation as pending.
4168 *
4169 * @param pVCpu The cross context virtual CPU structure.
4170 * @param offApic The offset in the virtual-APIC page that was written.
4171 */
4172DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4173{
4174 Assert(offApic < XAPIC_OFF_END + 4);
4175
4176 /*
4177 * Record the currently updated APIC offset, as we need this later for figuring
4178 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4179 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4180 */
4181 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4182
4183 /*
4184 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4185 * virtualization or APIC-write emulation).
4186 */
4187 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4188 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4189}
4190
4191
4192/**
4193 * Clears any pending virtual-APIC write emulation.
4194 *
4195 * @returns The virtual-APIC offset that was written before clearing it.
4196 * @param pVCpu The cross context virtual CPU structure.
4197 */
4198DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4199{
4200 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4201 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4202 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4203 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4204 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4205 return offVirtApicWrite;
4206}
4207
4208
4209/**
4210 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4211 *
4212 * @returns The register from the virtual-APIC page.
4213 * @param pVCpu The cross context virtual CPU structure.
4214 * @param offReg The offset of the register being read.
4215 */
4216IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4217{
4218 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4219 Assert(pVmcs);
4220
4221 uint32_t uReg;
4222 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4223 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4224 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4225 if (RT_FAILURE(rc))
4226 {
4227 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4228 GCPhysVirtApic));
4229 uReg = 0;
4230 }
4231 return uReg;
4232}
4233
4234
4235/**
4236 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4237 *
4238 * @returns The register from the virtual-APIC page.
4239 * @param pVCpu The cross context virtual CPU structure.
4240 * @param offReg The offset of the register being read.
4241 */
4242IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4243{
4244 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4245 Assert(pVmcs);
4246
4247 uint64_t uReg;
4248 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4249 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4250 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4251 if (RT_FAILURE(rc))
4252 {
4253 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4254 GCPhysVirtApic));
4255 uReg = 0;
4256 }
4257 return uReg;
4258}
4259
4260
4261/**
4262 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4263 *
4264 * @param pVCpu The cross context virtual CPU structure.
4265 * @param offReg The offset of the register being written.
4266 * @param uReg The register value to write.
4267 */
4268IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4269{
4270 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4271 Assert(pVmcs);
4272 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4273 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4274 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4275 if (RT_FAILURE(rc))
4276 {
4277 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4278 GCPhysVirtApic));
4279 }
4280}
4281
4282
4283/**
4284 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4285 *
4286 * @param pVCpu The cross context virtual CPU structure.
4287 * @param offReg The offset of the register being written.
4288 * @param uReg The register value to write.
4289 */
4290IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4291{
4292 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4293 Assert(pVmcs);
4294 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4295 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4296 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4297 if (RT_FAILURE(rc))
4298 {
4299 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4300 GCPhysVirtApic));
4301 }
4302}
4303
4304
4305/**
4306 * Sets the vector in a virtual-APIC 256-bit sparse register.
4307 *
4308 * @param pVCpu The cross context virtual CPU structure.
4309 * @param offReg The offset of the 256-bit spare register.
4310 * @param uVector The vector to set.
4311 *
4312 * @remarks This is based on our APIC device code.
4313 */
4314IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4315{
4316 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4317 Assert(pVmcs);
4318 uint32_t uReg;
4319 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4320 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4321 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4322 if (RT_SUCCESS(rc))
4323 {
4324 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4325 uReg |= RT_BIT(idxVectorBit);
4326 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4327 if (RT_FAILURE(rc))
4328 {
4329 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4330 uVector, offReg, GCPhysVirtApic));
4331 }
4332 }
4333 else
4334 {
4335 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4336 uVector, offReg, GCPhysVirtApic));
4337 }
4338}
4339
4340
4341/**
4342 * Clears the vector in a virtual-APIC 256-bit sparse register.
4343 *
4344 * @param pVCpu The cross context virtual CPU structure.
4345 * @param offReg The offset of the 256-bit spare register.
4346 * @param uVector The vector to clear.
4347 *
4348 * @remarks This is based on our APIC device code.
4349 */
4350IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4351{
4352 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4353 Assert(pVmcs);
4354 uint32_t uReg;
4355 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4356 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4357 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4358 if (RT_SUCCESS(rc))
4359 {
4360 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4361 uReg &= ~RT_BIT(idxVectorBit);
4362 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4363 if (RT_FAILURE(rc))
4364 {
4365 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4366 uVector, offReg, GCPhysVirtApic));
4367 }
4368 }
4369 else
4370 {
4371 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4372 uVector, offReg, GCPhysVirtApic));
4373 }
4374}
4375
4376
4377/**
4378 * Checks if a memory access to the APIC-access page must causes an APIC-access
4379 * VM-exit.
4380 *
4381 * @param pVCpu The cross context virtual CPU structure.
4382 * @param offAccess The offset of the register being accessed.
4383 * @param cbAccess The size of the access in bytes.
4384 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4385 * IEM_ACCESS_TYPE_WRITE).
4386 *
4387 * @remarks This must not be used for MSR-based APIC-access page accesses!
4388 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4389 */
4390IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4391{
4392 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4393 Assert(pVmcs);
4394 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4395
4396 /*
4397 * We must cause a VM-exit if any of the following are true:
4398 * - TPR shadowing isn't active.
4399 * - The access size exceeds 32-bits.
4400 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4401 *
4402 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4403 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4404 */
4405 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4406 || cbAccess > sizeof(uint32_t)
4407 || ((offAccess + cbAccess - 1) & 0xc)
4408 || offAccess >= XAPIC_OFF_END + 4)
4409 return true;
4410
4411 /*
4412 * If the access is part of an operation where we have already
4413 * virtualized a virtual-APIC write, we must cause a VM-exit.
4414 */
4415 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4416 return true;
4417
4418 /*
4419 * Check write accesses to the APIC-access page that cause VM-exits.
4420 */
4421 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4422 {
4423 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4424 {
4425 /*
4426 * With APIC-register virtualization, a write access to any of the
4427 * following registers are virtualized. Accessing any other register
4428 * causes a VM-exit.
4429 */
4430 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4431 switch (offAlignedAccess)
4432 {
4433 case XAPIC_OFF_ID:
4434 case XAPIC_OFF_TPR:
4435 case XAPIC_OFF_EOI:
4436 case XAPIC_OFF_LDR:
4437 case XAPIC_OFF_DFR:
4438 case XAPIC_OFF_SVR:
4439 case XAPIC_OFF_ESR:
4440 case XAPIC_OFF_ICR_LO:
4441 case XAPIC_OFF_ICR_HI:
4442 case XAPIC_OFF_LVT_TIMER:
4443 case XAPIC_OFF_LVT_THERMAL:
4444 case XAPIC_OFF_LVT_PERF:
4445 case XAPIC_OFF_LVT_LINT0:
4446 case XAPIC_OFF_LVT_LINT1:
4447 case XAPIC_OFF_LVT_ERROR:
4448 case XAPIC_OFF_TIMER_ICR:
4449 case XAPIC_OFF_TIMER_DCR:
4450 break;
4451 default:
4452 return true;
4453 }
4454 }
4455 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4456 {
4457 /*
4458 * With virtual-interrupt delivery, a write access to any of the
4459 * following registers are virtualized. Accessing any other register
4460 * causes a VM-exit.
4461 *
4462 * Note! The specification does not allow writing to offsets in-between
4463 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4464 */
4465 switch (offAccess)
4466 {
4467 case XAPIC_OFF_TPR:
4468 case XAPIC_OFF_EOI:
4469 case XAPIC_OFF_ICR_LO:
4470 break;
4471 default:
4472 return true;
4473 }
4474 }
4475 else
4476 {
4477 /*
4478 * Without APIC-register virtualization or virtual-interrupt delivery,
4479 * only TPR accesses are virtualized.
4480 */
4481 if (offAccess == XAPIC_OFF_TPR)
4482 { /* likely */ }
4483 else
4484 return true;
4485 }
4486 }
4487 else
4488 {
4489 /*
4490 * Check read accesses to the APIC-access page that cause VM-exits.
4491 */
4492 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4493 {
4494 /*
4495 * With APIC-register virtualization, a read access to any of the
4496 * following registers are virtualized. Accessing any other register
4497 * causes a VM-exit.
4498 */
4499 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4500 switch (offAlignedAccess)
4501 {
4502 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4503 case XAPIC_OFF_ID:
4504 case XAPIC_OFF_VERSION:
4505 case XAPIC_OFF_TPR:
4506 case XAPIC_OFF_EOI:
4507 case XAPIC_OFF_LDR:
4508 case XAPIC_OFF_DFR:
4509 case XAPIC_OFF_SVR:
4510 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4511 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4512 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4513 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4514 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4515 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4516 case XAPIC_OFF_ESR:
4517 case XAPIC_OFF_ICR_LO:
4518 case XAPIC_OFF_ICR_HI:
4519 case XAPIC_OFF_LVT_TIMER:
4520 case XAPIC_OFF_LVT_THERMAL:
4521 case XAPIC_OFF_LVT_PERF:
4522 case XAPIC_OFF_LVT_LINT0:
4523 case XAPIC_OFF_LVT_LINT1:
4524 case XAPIC_OFF_LVT_ERROR:
4525 case XAPIC_OFF_TIMER_ICR:
4526 case XAPIC_OFF_TIMER_DCR:
4527 break;
4528 default:
4529 return true;
4530 }
4531 }
4532 else
4533 {
4534 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4535 if (offAccess == XAPIC_OFF_TPR)
4536 { /* likely */ }
4537 else
4538 return true;
4539 }
4540 }
4541
4542 /* The APIC-access is virtualized, does not cause a VM-exit. */
4543 return false;
4544}
4545
4546
4547/**
4548 * Virtualizes a memory-based APIC-access where the address is not used to access
4549 * memory.
4550 *
4551 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4552 * page-faults but do not use the address to access memory.
4553 *
4554 * @param pVCpu The cross context virtual CPU structure.
4555 * @param pGCPhysAccess Pointer to the guest-physical address used.
4556 */
4557IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4558{
4559 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4560 Assert(pVmcs);
4561 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4562 Assert(pGCPhysAccess);
4563
4564 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4565 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4566 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4567
4568 if (GCPhysAccess == GCPhysApic)
4569 {
4570 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4571 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4572 uint16_t const cbAccess = 1;
4573 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4574 if (fIntercept)
4575 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4576
4577 *pGCPhysAccess = GCPhysApic | offAccess;
4578 return VINF_VMX_MODIFIES_BEHAVIOR;
4579 }
4580
4581 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4582}
4583
4584
4585/**
4586 * Virtualizes a memory-based APIC-access.
4587 *
4588 * @returns VBox strict status code.
4589 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4590 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4591 *
4592 * @param pVCpu The cross context virtual CPU structure.
4593 * @param offAccess The offset of the register being accessed (within the
4594 * APIC-access page).
4595 * @param cbAccess The size of the access in bytes.
4596 * @param pvData Pointer to the data being written or where to store the data
4597 * being read.
4598 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4599 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4600 */
4601IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4602 uint32_t fAccess)
4603{
4604 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4605 Assert(pVmcs);
4606 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4607 Assert(pvData);
4608 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4609 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4610 || (fAccess & IEM_ACCESS_INSTRUCTION));
4611
4612 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4613 if (fIntercept)
4614 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4615
4616 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4617 {
4618 /*
4619 * A write access to the APIC-access page that is virtualized (rather than
4620 * causing a VM-exit) writes data to the virtual-APIC page.
4621 */
4622 uint32_t const u32Data = *(uint32_t *)pvData;
4623 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4624
4625 /*
4626 * Record the currently updated APIC offset, as we need this later for figuring
4627 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4628 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4629 *
4630 * After completion of the current operation, we need to perform TPR virtualization,
4631 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4632 *
4633 * The current operation may be a REP-prefixed string instruction, execution of any
4634 * other instruction, or delivery of an event through the IDT.
4635 *
4636 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4637 * performed now but later after completion of the current operation.
4638 *
4639 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4640 */
4641 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4642 }
4643 else
4644 {
4645 /*
4646 * A read access from the APIC-access page that is virtualized (rather than
4647 * causing a VM-exit) returns data from the virtual-APIC page.
4648 *
4649 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4650 */
4651 Assert(cbAccess <= 4);
4652 Assert(offAccess < XAPIC_OFF_END + 4);
4653 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4654
4655 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4656 u32Data &= s_auAccessSizeMasks[cbAccess];
4657 *(uint32_t *)pvData = u32Data;
4658 }
4659
4660 return VINF_VMX_MODIFIES_BEHAVIOR;
4661}
4662
4663
4664/**
4665 * Virtualizes an MSR-based APIC read access.
4666 *
4667 * @returns VBox strict status code.
4668 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4669 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4670 * handled by the x2APIC device.
4671 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4672 * not within the range of valid MSRs, caller must raise \#GP(0).
4673 * @param pVCpu The cross context virtual CPU structure.
4674 * @param idMsr The x2APIC MSR being read.
4675 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4676 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4677 */
4678IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4679{
4680 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4681 Assert(pVmcs);
4682 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4683 Assert(pu64Value);
4684
4685 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4686 {
4687 /*
4688 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4689 * what the end of the valid x2APIC MSR range is. Hence the use of different
4690 * macros here.
4691 *
4692 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4693 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4694 */
4695 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4696 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4697 {
4698 uint16_t const offReg = (idMsr & 0xff) << 4;
4699 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4700 *pu64Value = u64Value;
4701 return VINF_VMX_MODIFIES_BEHAVIOR;
4702 }
4703 return VERR_OUT_OF_RANGE;
4704 }
4705
4706 if (idMsr == MSR_IA32_X2APIC_TPR)
4707 {
4708 uint16_t const offReg = (idMsr & 0xff) << 4;
4709 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4710 *pu64Value = u64Value;
4711 return VINF_VMX_MODIFIES_BEHAVIOR;
4712 }
4713
4714 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4715}
4716
4717
4718/**
4719 * Virtualizes an MSR-based APIC write access.
4720 *
4721 * @returns VBox strict status code.
4722 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4723 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4724 * not within the range of valid MSRs, caller must raise \#GP(0).
4725 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4726 *
4727 * @param pVCpu The cross context virtual CPU structure.
4728 * @param idMsr The x2APIC MSR being written.
4729 * @param u64Value The value of the x2APIC MSR being written.
4730 */
4731IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4732{
4733 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4734 Assert(pVmcs);
4735
4736 /*
4737 * Check if the access is to be virtualized.
4738 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4739 */
4740 if ( idMsr == MSR_IA32_X2APIC_TPR
4741 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4742 && ( idMsr == MSR_IA32_X2APIC_EOI
4743 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4744 {
4745 /* Validate the MSR write depending on the register. */
4746 switch (idMsr)
4747 {
4748 case MSR_IA32_X2APIC_TPR:
4749 case MSR_IA32_X2APIC_SELF_IPI:
4750 {
4751 if (u64Value & UINT64_C(0xffffffffffffff00))
4752 return VERR_OUT_OF_RANGE;
4753 break;
4754 }
4755 case MSR_IA32_X2APIC_EOI:
4756 {
4757 if (u64Value != 0)
4758 return VERR_OUT_OF_RANGE;
4759 break;
4760 }
4761 }
4762
4763 /* Write the MSR to the virtual-APIC page. */
4764 uint16_t const offReg = (idMsr & 0xff) << 4;
4765 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4766
4767 /*
4768 * Record the currently updated APIC offset, as we need this later for figuring
4769 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4770 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4771 */
4772 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4773
4774 return VINF_VMX_MODIFIES_BEHAVIOR;
4775 }
4776
4777 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4778}
4779
4780
4781/**
4782 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4783 *
4784 * @returns VBox status code.
4785 * @retval VINF_SUCCESS when the highest set bit is found.
4786 * @retval VERR_NOT_FOUND when no bit is set.
4787 *
4788 * @param pVCpu The cross context virtual CPU structure.
4789 * @param offReg The offset of the APIC 256-bit sparse register.
4790 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4791 * set in the register. Only valid when VINF_SUCCESS is
4792 * returned.
4793 *
4794 * @remarks The format of the 256-bit sparse register here mirrors that found in
4795 * real APIC hardware.
4796 */
4797static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4798{
4799 Assert(offReg < XAPIC_OFF_END + 4);
4800 Assert(pidxHighestBit);
4801 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4802
4803 /*
4804 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4805 * However, in each fragment only the first 4 bytes are used.
4806 */
4807 uint8_t const cFrags = 8;
4808 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4809 {
4810 uint16_t const offFrag = iFrag * 16;
4811 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4812 if (!u32Frag)
4813 continue;
4814
4815 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4816 Assert(idxHighestBit > 0);
4817 --idxHighestBit;
4818 Assert(idxHighestBit <= UINT8_MAX);
4819 *pidxHighestBit = idxHighestBit;
4820 return VINF_SUCCESS;
4821 }
4822 return VERR_NOT_FOUND;
4823}
4824
4825
4826/**
4827 * Evaluates pending virtual interrupts.
4828 *
4829 * @param pVCpu The cross context virtual CPU structure.
4830 */
4831IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4832{
4833 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4834 Assert(pVmcs);
4835 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4836
4837 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4838 {
4839 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4840 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4841
4842 if ((uRvi >> 4) > (uPpr >> 4))
4843 {
4844 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4845 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4846 }
4847 else
4848 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4849 }
4850}
4851
4852
4853/**
4854 * Performs PPR virtualization.
4855 *
4856 * @returns VBox strict status code.
4857 * @param pVCpu The cross context virtual CPU structure.
4858 */
4859IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4860{
4861 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4862 Assert(pVmcs);
4863 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4864 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4865
4866 /*
4867 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4868 * or EOI-virtualization.
4869 *
4870 * See Intel spec. 29.1.3 "PPR Virtualization".
4871 */
4872 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4873 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4874
4875 uint32_t uPpr;
4876 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4877 uPpr = uTpr & 0xff;
4878 else
4879 uPpr = uSvi & 0xf0;
4880
4881 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4882 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4883}
4884
4885
4886/**
4887 * Performs VMX TPR virtualization.
4888 *
4889 * @returns VBox strict status code.
4890 * @param pVCpu The cross context virtual CPU structure.
4891 */
4892IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4893{
4894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4895 Assert(pVmcs);
4896 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4897
4898 /*
4899 * We should have already performed the virtual-APIC write to the TPR offset
4900 * in the virtual-APIC page. We now perform TPR virtualization.
4901 *
4902 * See Intel spec. 29.1.2 "TPR Virtualization".
4903 */
4904 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4905 {
4906 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4907 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4908
4909 /*
4910 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4911 * See Intel spec. 29.1.2 "TPR Virtualization".
4912 */
4913 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4914 {
4915 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4916 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4917 }
4918 }
4919 else
4920 {
4921 iemVmxPprVirtualization(pVCpu);
4922 iemVmxEvalPendingVirtIntrs(pVCpu);
4923 }
4924
4925 return VINF_SUCCESS;
4926}
4927
4928
4929/**
4930 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4931 * not.
4932 *
4933 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4934 * @param pVCpu The cross context virtual CPU structure.
4935 * @param uVector The interrupt that was acknowledged using an EOI.
4936 */
4937IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4938{
4939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4940 Assert(pVmcs);
4941 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4942
4943 if (uVector < 64)
4944 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4945 if (uVector < 128)
4946 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4947 if (uVector < 192)
4948 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4949 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4950}
4951
4952
4953/**
4954 * Performs EOI virtualization.
4955 *
4956 * @returns VBox strict status code.
4957 * @param pVCpu The cross context virtual CPU structure.
4958 */
4959IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4960{
4961 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4962 Assert(pVmcs);
4963 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4964
4965 /*
4966 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4967 * and get the next guest-interrupt that's in-service (if any).
4968 *
4969 * See Intel spec. 29.1.4 "EOI Virtualization".
4970 */
4971 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4972 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4973 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4974
4975 uint8_t uVector = uSvi;
4976 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4977
4978 uVector = 0;
4979 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4980
4981 if (uVector)
4982 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4983 else
4984 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4985
4986 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4987 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4988
4989 iemVmxPprVirtualization(pVCpu);
4990 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4991 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4992 iemVmxEvalPendingVirtIntrs(pVCpu);
4993 return VINF_SUCCESS;
4994}
4995
4996
4997/**
4998 * Performs self-IPI virtualization.
4999 *
5000 * @returns VBox strict status code.
5001 * @param pVCpu The cross context virtual CPU structure.
5002 */
5003IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5004{
5005 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5006 Assert(pVmcs);
5007 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5008
5009 /*
5010 * We should have already performed the virtual-APIC write to the self-IPI offset
5011 * in the virtual-APIC page. We now perform self-IPI virtualization.
5012 *
5013 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5014 */
5015 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5016 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5017 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5018 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5019 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5020 if (uVector > uRvi)
5021 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5022 iemVmxEvalPendingVirtIntrs(pVCpu);
5023 return VINF_SUCCESS;
5024}
5025
5026
5027/**
5028 * Performs VMX APIC-write emulation.
5029 *
5030 * @returns VBox strict status code.
5031 * @param pVCpu The cross context virtual CPU structure.
5032 */
5033IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5034{
5035 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5036 Assert(pVmcs);
5037
5038 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5039 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5040
5041 /*
5042 * Perform APIC-write emulation based on the virtual-APIC register written.
5043 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5044 */
5045 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5046 VBOXSTRICTRC rcStrict;
5047 switch (offApicWrite)
5048 {
5049 case XAPIC_OFF_TPR:
5050 {
5051 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5052 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5053 uTpr &= UINT32_C(0x000000ff);
5054 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5055 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5056 rcStrict = iemVmxTprVirtualization(pVCpu);
5057 break;
5058 }
5059
5060 case XAPIC_OFF_EOI:
5061 {
5062 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5063 {
5064 /* Clear VEOI and perform EOI virtualization. */
5065 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5066 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5067 rcStrict = iemVmxEoiVirtualization(pVCpu);
5068 }
5069 else
5070 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5071 break;
5072 }
5073
5074 case XAPIC_OFF_ICR_LO:
5075 {
5076 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5077 {
5078 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5079 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5080 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5081 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5082 if ( !(uIcrLo & fIcrLoMb0)
5083 && (uIcrLo & fIcrLoMb1))
5084 {
5085 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5086 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5087 }
5088 else
5089 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5090 }
5091 else
5092 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5093 break;
5094 }
5095
5096 case XAPIC_OFF_ICR_HI:
5097 {
5098 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5099 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5100 uIcrHi &= UINT32_C(0xff000000);
5101 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5102 rcStrict = VINF_SUCCESS;
5103 break;
5104 }
5105
5106 default:
5107 {
5108 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5109 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5110 break;
5111 }
5112 }
5113
5114 return rcStrict;
5115}
5116
5117
5118/**
5119 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5120 *
5121 * @param pVCpu The cross context virtual CPU structure.
5122 * @param pszInstr The VMX instruction name (for logging purposes).
5123 */
5124IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5125{
5126 /*
5127 * Guest Control Registers, Debug Registers, and MSRs.
5128 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5129 */
5130 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5131 const char *const pszFailure = "VM-exit";
5132 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5133
5134 /* CR0 reserved bits. */
5135 {
5136 /* CR0 MB1 bits. */
5137 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5138 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5139 if (fUnrestrictedGuest)
5140 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5141 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5142 { /* likely */ }
5143 else
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5145
5146 /* CR0 MBZ bits. */
5147 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5148 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5152
5153 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5154 if ( !fUnrestrictedGuest
5155 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5156 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5158 }
5159
5160 /* CR4 reserved bits. */
5161 {
5162 /* CR4 MB1 bits. */
5163 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5164 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5165 { /* likely */ }
5166 else
5167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5168
5169 /* CR4 MBZ bits. */
5170 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5171 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5172 { /* likely */ }
5173 else
5174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5175 }
5176
5177 /* DEBUGCTL MSR. */
5178 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5179 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5180 { /* likely */ }
5181 else
5182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5183
5184 /* 64-bit CPU checks. */
5185 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5186 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5187 {
5188 if (fGstInLongMode)
5189 {
5190 /* PAE must be set. */
5191 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5192 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5196 }
5197 else
5198 {
5199 /* PCIDE should not be set. */
5200 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5201 { /* likely */ }
5202 else
5203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5204 }
5205
5206 /* CR3. */
5207 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5208 { /* likely */ }
5209 else
5210 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5211
5212 /* DR7. */
5213 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5214 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5215 { /* likely */ }
5216 else
5217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5218
5219 /* SYSENTER ESP and SYSENTER EIP. */
5220 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5221 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5225 }
5226
5227 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5228 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5229
5230 /* PAT MSR. */
5231 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5232 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5236
5237 /* EFER MSR. */
5238 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5239 {
5240 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5241 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5245
5246 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5247 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5248 if ( fGstLma == fGstInLongMode
5249 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5250 || fGstLma == fGstLme))
5251 { /* likely */ }
5252 else
5253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5254 }
5255
5256 /* We don't support IA32_BNDCFGS MSR yet. */
5257 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5258
5259 NOREF(pszInstr);
5260 NOREF(pszFailure);
5261 return VINF_SUCCESS;
5262}
5263
5264
5265/**
5266 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5267 *
5268 * @param pVCpu The cross context virtual CPU structure.
5269 * @param pszInstr The VMX instruction name (for logging purposes).
5270 */
5271IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5272{
5273 /*
5274 * Segment registers.
5275 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5276 */
5277 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5278 const char *const pszFailure = "VM-exit";
5279 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5280 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5281 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5282
5283 /* Selectors. */
5284 if ( !fGstInV86Mode
5285 && !fUnrestrictedGuest
5286 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5288
5289 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5290 {
5291 CPUMSELREG SelReg;
5292 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5293 if (RT_LIKELY(rc == VINF_SUCCESS))
5294 { /* likely */ }
5295 else
5296 return rc;
5297
5298 /*
5299 * Virtual-8086 mode checks.
5300 */
5301 if (fGstInV86Mode)
5302 {
5303 /* Base address. */
5304 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5305 { /* likely */ }
5306 else
5307 {
5308 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5310 }
5311
5312 /* Limit. */
5313 if (SelReg.u32Limit == 0xffff)
5314 { /* likely */ }
5315 else
5316 {
5317 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5319 }
5320
5321 /* Attribute. */
5322 if (SelReg.Attr.u == 0xf3)
5323 { /* likely */ }
5324 else
5325 {
5326 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5328 }
5329
5330 /* We're done; move to checking the next segment. */
5331 continue;
5332 }
5333
5334 /* Checks done by 64-bit CPUs. */
5335 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5336 {
5337 /* Base address. */
5338 if ( iSegReg == X86_SREG_FS
5339 || iSegReg == X86_SREG_GS)
5340 {
5341 if (X86_IS_CANONICAL(SelReg.u64Base))
5342 { /* likely */ }
5343 else
5344 {
5345 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5346 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5347 }
5348 }
5349 else if (iSegReg == X86_SREG_CS)
5350 {
5351 if (!RT_HI_U32(SelReg.u64Base))
5352 { /* likely */ }
5353 else
5354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5355 }
5356 else
5357 {
5358 if ( SelReg.Attr.n.u1Unusable
5359 || !RT_HI_U32(SelReg.u64Base))
5360 { /* likely */ }
5361 else
5362 {
5363 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5364 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5365 }
5366 }
5367 }
5368
5369 /*
5370 * Checks outside Virtual-8086 mode.
5371 */
5372 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5373 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5374 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5375 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5376 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5377 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5378 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5379 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5380
5381 /* Code or usable segment. */
5382 if ( iSegReg == X86_SREG_CS
5383 || fUsable)
5384 {
5385 /* Reserved bits (bits 31:17 and bits 11:8). */
5386 if (!(SelReg.Attr.u & 0xfffe0f00))
5387 { /* likely */ }
5388 else
5389 {
5390 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5392 }
5393
5394 /* Descriptor type. */
5395 if (fCodeDataSeg)
5396 { /* likely */ }
5397 else
5398 {
5399 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5401 }
5402
5403 /* Present. */
5404 if (fPresent)
5405 { /* likely */ }
5406 else
5407 {
5408 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5410 }
5411
5412 /* Granularity. */
5413 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5414 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5415 { /* likely */ }
5416 else
5417 {
5418 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5420 }
5421 }
5422
5423 if (iSegReg == X86_SREG_CS)
5424 {
5425 /* Segment Type and DPL. */
5426 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5427 && fUnrestrictedGuest)
5428 {
5429 if (uDpl == 0)
5430 { /* likely */ }
5431 else
5432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5433 }
5434 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5435 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5436 {
5437 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5438 if (uDpl == AttrSs.n.u2Dpl)
5439 { /* likely */ }
5440 else
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5442 }
5443 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5444 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5445 {
5446 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5447 if (uDpl <= AttrSs.n.u2Dpl)
5448 { /* likely */ }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5451 }
5452 else
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5454
5455 /* Def/Big. */
5456 if ( fGstInLongMode
5457 && fSegLong)
5458 {
5459 if (uDefBig == 0)
5460 { /* likely */ }
5461 else
5462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5463 }
5464 }
5465 else if (iSegReg == X86_SREG_SS)
5466 {
5467 /* Segment Type. */
5468 if ( !fUsable
5469 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5470 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5471 { /* likely */ }
5472 else
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5474
5475 /* DPL. */
5476 if (!fUnrestrictedGuest)
5477 {
5478 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5479 { /* likely */ }
5480 else
5481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5482 }
5483 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5484 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5485 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5486 {
5487 if (uDpl == 0)
5488 { /* likely */ }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5491 }
5492 }
5493 else
5494 {
5495 /* DS, ES, FS, GS. */
5496 if (fUsable)
5497 {
5498 /* Segment type. */
5499 if (uSegType & X86_SEL_TYPE_ACCESSED)
5500 { /* likely */ }
5501 else
5502 {
5503 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5505 }
5506
5507 if ( !(uSegType & X86_SEL_TYPE_CODE)
5508 || (uSegType & X86_SEL_TYPE_READ))
5509 { /* likely */ }
5510 else
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5512
5513 /* DPL. */
5514 if ( !fUnrestrictedGuest
5515 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5516 {
5517 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5518 { /* likely */ }
5519 else
5520 {
5521 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5523 }
5524 }
5525 }
5526 }
5527 }
5528
5529 /*
5530 * LDTR.
5531 */
5532 {
5533 CPUMSELREG Ldtr;
5534 Ldtr.Sel = pVmcs->GuestLdtr;
5535 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5536 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5537 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5538
5539 if (!Ldtr.Attr.n.u1Unusable)
5540 {
5541 /* Selector. */
5542 if (!(Ldtr.Sel & X86_SEL_LDT))
5543 { /* likely */ }
5544 else
5545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5546
5547 /* Base. */
5548 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5549 {
5550 if (X86_IS_CANONICAL(Ldtr.u64Base))
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5554 }
5555
5556 /* Attributes. */
5557 /* Reserved bits (bits 31:17 and bits 11:8). */
5558 if (!(Ldtr.Attr.u & 0xfffe0f00))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5562
5563 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5567
5568 if (!Ldtr.Attr.n.u1DescType)
5569 { /* likely */ }
5570 else
5571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5572
5573 if (Ldtr.Attr.n.u1Present)
5574 { /* likely */ }
5575 else
5576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5577
5578 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5579 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5580 { /* likely */ }
5581 else
5582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5583 }
5584 }
5585
5586 /*
5587 * TR.
5588 */
5589 {
5590 CPUMSELREG Tr;
5591 Tr.Sel = pVmcs->GuestTr;
5592 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5593 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5594 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5595
5596 /* Selector. */
5597 if (!(Tr.Sel & X86_SEL_LDT))
5598 { /* likely */ }
5599 else
5600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5601
5602 /* Base. */
5603 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5604 {
5605 if (X86_IS_CANONICAL(Tr.u64Base))
5606 { /* likely */ }
5607 else
5608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5609 }
5610
5611 /* Attributes. */
5612 /* Reserved bits (bits 31:17 and bits 11:8). */
5613 if (!(Tr.Attr.u & 0xfffe0f00))
5614 { /* likely */ }
5615 else
5616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5617
5618 if (!Tr.Attr.n.u1Unusable)
5619 { /* likely */ }
5620 else
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5622
5623 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5624 || ( !fGstInLongMode
5625 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5629
5630 if (!Tr.Attr.n.u1DescType)
5631 { /* likely */ }
5632 else
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5634
5635 if (Tr.Attr.n.u1Present)
5636 { /* likely */ }
5637 else
5638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5639
5640 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5641 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5642 { /* likely */ }
5643 else
5644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5645 }
5646
5647 NOREF(pszInstr);
5648 NOREF(pszFailure);
5649 return VINF_SUCCESS;
5650}
5651
5652
5653/**
5654 * Checks guest GDTR and IDTR as part of VM-entry.
5655 *
5656 * @param pVCpu The cross context virtual CPU structure.
5657 * @param pszInstr The VMX instruction name (for logging purposes).
5658 */
5659IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5660{
5661 /*
5662 * GDTR and IDTR.
5663 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5664 */
5665 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5666 const char *const pszFailure = "VM-exit";
5667
5668 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5669 {
5670 /* Base. */
5671 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5672 { /* likely */ }
5673 else
5674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5675
5676 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5677 { /* likely */ }
5678 else
5679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5680 }
5681
5682 /* Limit. */
5683 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5684 { /* likely */ }
5685 else
5686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5687
5688 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5689 { /* likely */ }
5690 else
5691 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5692
5693 NOREF(pszInstr);
5694 NOREF(pszFailure);
5695 return VINF_SUCCESS;
5696}
5697
5698
5699/**
5700 * Checks guest RIP and RFLAGS as part of VM-entry.
5701 *
5702 * @param pVCpu The cross context virtual CPU structure.
5703 * @param pszInstr The VMX instruction name (for logging purposes).
5704 */
5705IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5706{
5707 /*
5708 * RIP and RFLAGS.
5709 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5710 */
5711 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5712 const char *const pszFailure = "VM-exit";
5713 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5714
5715 /* RIP. */
5716 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5717 {
5718 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5719 if ( !fGstInLongMode
5720 || !AttrCs.n.u1Long)
5721 {
5722 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5723 { /* likely */ }
5724 else
5725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5726 }
5727
5728 if ( fGstInLongMode
5729 && AttrCs.n.u1Long)
5730 {
5731 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5732 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5733 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5734 { /* likely */ }
5735 else
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5737 }
5738 }
5739
5740 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5741 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5742 : pVmcs->u64GuestRFlags.s.Lo;
5743 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5744 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5745 { /* likely */ }
5746 else
5747 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5748
5749 if ( fGstInLongMode
5750 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5751 {
5752 if (!(uGuestRFlags & X86_EFL_VM))
5753 { /* likely */ }
5754 else
5755 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5756 }
5757
5758 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5759 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5760 {
5761 if (uGuestRFlags & X86_EFL_IF)
5762 { /* likely */ }
5763 else
5764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5765 }
5766
5767 NOREF(pszInstr);
5768 NOREF(pszFailure);
5769 return VINF_SUCCESS;
5770}
5771
5772
5773/**
5774 * Checks guest non-register state as part of VM-entry.
5775 *
5776 * @param pVCpu The cross context virtual CPU structure.
5777 * @param pszInstr The VMX instruction name (for logging purposes).
5778 */
5779IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5780{
5781 /*
5782 * Guest non-register state.
5783 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5784 */
5785 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5786 const char *const pszFailure = "VM-exit";
5787
5788 /*
5789 * Activity state.
5790 */
5791 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5792 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5793 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5794 { /* likely */ }
5795 else
5796 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5797
5798 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5799 if ( !AttrSs.n.u2Dpl
5800 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5801 { /* likely */ }
5802 else
5803 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5804
5805 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5806 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5807 {
5808 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5812 }
5813
5814 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5815 {
5816 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5817 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5818 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5819 switch (pVmcs->u32GuestActivityState)
5820 {
5821 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5822 {
5823 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5824 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5825 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5826 && ( uVector == X86_XCPT_DB
5827 || uVector == X86_XCPT_MC))
5828 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5829 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5830 { /* likely */ }
5831 else
5832 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5833 break;
5834 }
5835
5836 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5837 {
5838 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5839 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5840 && uVector == X86_XCPT_MC))
5841 { /* likely */ }
5842 else
5843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5844 break;
5845 }
5846
5847 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5848 default:
5849 break;
5850 }
5851 }
5852
5853 /*
5854 * Interruptibility state.
5855 */
5856 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5857 { /* likely */ }
5858 else
5859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5860
5861 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5862 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5863 { /* likely */ }
5864 else
5865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5866
5867 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5868 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5872
5873 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5874 {
5875 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5876 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5877 {
5878 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5882 }
5883 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5884 {
5885 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5886 { /* likely */ }
5887 else
5888 {
5889 /*
5890 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5891 * We update the VM-exit qualification only when blocking-by-STI is set
5892 * without blocking-by-MovSS being set. Although in practise it does not
5893 * make much difference since the order of checks are implementation defined.
5894 */
5895 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5896 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5898 }
5899
5900 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5901 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5902 { /* likely */ }
5903 else
5904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5905 }
5906 }
5907
5908 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5909 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5910 { /* likely */ }
5911 else
5912 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5913
5914 /* We don't support SGX yet. So enclave-interruption must not be set. */
5915 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5916 { /* likely */ }
5917 else
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5919
5920 /*
5921 * Pending debug exceptions.
5922 */
5923 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5924 ? pVmcs->u64GuestPendingDbgXcpt.u
5925 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5926 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5927 { /* likely */ }
5928 else
5929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5930
5931 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5932 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5933 {
5934 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5935 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5936 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5938
5939 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5940 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5941 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5943 }
5944
5945 /* We don't support RTM (Real-time Transactional Memory) yet. */
5946 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5947 { /* likely */ }
5948 else
5949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5950
5951 /*
5952 * VMCS link pointer.
5953 */
5954 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5955 {
5956 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5957 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5958 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5959 { /* likely */ }
5960 else
5961 {
5962 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5964 }
5965
5966 /* Validate the address. */
5967 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5968 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5969 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5970 { /* likely */ }
5971 else
5972 {
5973 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5975 }
5976
5977 /* Read the VMCS-link pointer from guest memory. */
5978 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5979 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5980 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5981 if (RT_SUCCESS(rc))
5982 { /* likely */ }
5983 else
5984 {
5985 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5987 }
5988
5989 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5990 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5991 { /* likely */ }
5992 else
5993 {
5994 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5996 }
5997
5998 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5999 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6000 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6001 { /* likely */ }
6002 else
6003 {
6004 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6006 }
6007
6008 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6009 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6010 }
6011
6012 NOREF(pszInstr);
6013 NOREF(pszFailure);
6014 return VINF_SUCCESS;
6015}
6016
6017
6018/**
6019 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6020 * VM-entry.
6021 *
6022 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6023 * @param pVCpu The cross context virtual CPU structure.
6024 * @param pszInstr The VMX instruction name (for logging purposes).
6025 * @param pVmcs Pointer to the virtual VMCS.
6026 */
6027IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6028{
6029 /*
6030 * Check PDPTEs.
6031 * See Intel spec. 4.4.1 "PDPTE Registers".
6032 */
6033 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6034 const char *const pszFailure = "VM-exit";
6035
6036 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6037 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6038 if (RT_SUCCESS(rc))
6039 {
6040 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6041 {
6042 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6043 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6044 { /* likely */ }
6045 else
6046 {
6047 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6048 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6050 }
6051 }
6052 }
6053 else
6054 {
6055 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6056 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6057 }
6058
6059 NOREF(pszFailure);
6060 NOREF(pszInstr);
6061 return rc;
6062}
6063
6064
6065/**
6066 * Checks guest PDPTEs as part of VM-entry.
6067 *
6068 * @param pVCpu The cross context virtual CPU structure.
6069 * @param pszInstr The VMX instruction name (for logging purposes).
6070 */
6071IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6072{
6073 /*
6074 * Guest PDPTEs.
6075 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6076 */
6077 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6078 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6079
6080 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6081 int rc;
6082 if ( !fGstInLongMode
6083 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6084 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6085 {
6086 /*
6087 * We don't support nested-paging for nested-guests yet.
6088 *
6089 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6090 * rather we need to check the PDPTEs referenced by the guest CR3.
6091 */
6092 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6093 }
6094 else
6095 rc = VINF_SUCCESS;
6096 return rc;
6097}
6098
6099
6100/**
6101 * Checks guest-state as part of VM-entry.
6102 *
6103 * @returns VBox status code.
6104 * @param pVCpu The cross context virtual CPU structure.
6105 * @param pszInstr The VMX instruction name (for logging purposes).
6106 */
6107IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6108{
6109 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6110 if (RT_SUCCESS(rc))
6111 {
6112 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6113 if (RT_SUCCESS(rc))
6114 {
6115 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6116 if (RT_SUCCESS(rc))
6117 {
6118 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6119 if (RT_SUCCESS(rc))
6120 {
6121 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6122 if (RT_SUCCESS(rc))
6123 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6124 }
6125 }
6126 }
6127 }
6128 return rc;
6129}
6130
6131
6132/**
6133 * Checks host-state as part of VM-entry.
6134 *
6135 * @returns VBox status code.
6136 * @param pVCpu The cross context virtual CPU structure.
6137 * @param pszInstr The VMX instruction name (for logging purposes).
6138 */
6139IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6140{
6141 /*
6142 * Host Control Registers and MSRs.
6143 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6144 */
6145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6146 const char * const pszFailure = "VMFail";
6147
6148 /* CR0 reserved bits. */
6149 {
6150 /* CR0 MB1 bits. */
6151 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6152 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6153 { /* likely */ }
6154 else
6155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6156
6157 /* CR0 MBZ bits. */
6158 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6159 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6163 }
6164
6165 /* CR4 reserved bits. */
6166 {
6167 /* CR4 MB1 bits. */
6168 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6169 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6173
6174 /* CR4 MBZ bits. */
6175 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6176 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6177 { /* likely */ }
6178 else
6179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6180 }
6181
6182 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6183 {
6184 /* CR3 reserved bits. */
6185 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6186 { /* likely */ }
6187 else
6188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6189
6190 /* SYSENTER ESP and SYSENTER EIP. */
6191 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6192 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6193 { /* likely */ }
6194 else
6195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6196 }
6197
6198 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6200
6201 /* PAT MSR. */
6202 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6203 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6204 { /* likely */ }
6205 else
6206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6207
6208 /* EFER MSR. */
6209 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6210 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6211 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6215
6216 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6217 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6218 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6219 if ( fHostInLongMode == fHostLma
6220 && fHostInLongMode == fHostLme)
6221 { /* likely */ }
6222 else
6223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6224
6225 /*
6226 * Host Segment and Descriptor-Table Registers.
6227 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6228 */
6229 /* Selector RPL and TI. */
6230 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6231 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6232 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6233 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6234 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6235 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6236 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6237 { /* likely */ }
6238 else
6239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6240
6241 /* CS and TR selectors cannot be 0. */
6242 if ( pVmcs->HostCs
6243 && pVmcs->HostTr)
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6247
6248 /* SS cannot be 0 if 32-bit host. */
6249 if ( fHostInLongMode
6250 || pVmcs->HostSs)
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6254
6255 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6256 {
6257 /* FS, GS, GDTR, IDTR, TR base address. */
6258 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6259 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6260 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6261 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6262 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6266 }
6267
6268 /*
6269 * Host address-space size for 64-bit CPUs.
6270 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6271 */
6272 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6273 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6274 {
6275 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6276
6277 /* Logical processor in IA-32e mode. */
6278 if (fCpuInLongMode)
6279 {
6280 if (fHostInLongMode)
6281 {
6282 /* PAE must be set. */
6283 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6284 { /* likely */ }
6285 else
6286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6287
6288 /* RIP must be canonical. */
6289 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6293 }
6294 else
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6296 }
6297 else
6298 {
6299 /* Logical processor is outside IA-32e mode. */
6300 if ( !fGstInLongMode
6301 && !fHostInLongMode)
6302 {
6303 /* PCIDE should not be set. */
6304 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6305 { /* likely */ }
6306 else
6307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6308
6309 /* The high 32-bits of RIP MBZ. */
6310 if (!pVmcs->u64HostRip.s.Hi)
6311 { /* likely */ }
6312 else
6313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6314 }
6315 else
6316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6317 }
6318 }
6319 else
6320 {
6321 /* Host address-space size for 32-bit CPUs. */
6322 if ( !fGstInLongMode
6323 && !fHostInLongMode)
6324 { /* likely */ }
6325 else
6326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6327 }
6328
6329 NOREF(pszInstr);
6330 NOREF(pszFailure);
6331 return VINF_SUCCESS;
6332}
6333
6334
6335/**
6336 * Checks VM-entry controls fields as part of VM-entry.
6337 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6338 *
6339 * @returns VBox status code.
6340 * @param pVCpu The cross context virtual CPU structure.
6341 * @param pszInstr The VMX instruction name (for logging purposes).
6342 */
6343IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6344{
6345 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6346 const char * const pszFailure = "VMFail";
6347
6348 /* VM-entry controls. */
6349 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6350 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6351 { /* likely */ }
6352 else
6353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6354
6355 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6356 { /* likely */ }
6357 else
6358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6359
6360 /* Event injection. */
6361 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6362 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6363 {
6364 /* Type and vector. */
6365 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6366 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6367 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6368 if ( !uRsvd
6369 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6370 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6371 { /* likely */ }
6372 else
6373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6374
6375 /* Exception error code. */
6376 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6377 {
6378 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6379 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6380 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6384
6385 /* Exceptions that provide an error code. */
6386 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6387 && ( uVector == X86_XCPT_DF
6388 || uVector == X86_XCPT_TS
6389 || uVector == X86_XCPT_NP
6390 || uVector == X86_XCPT_SS
6391 || uVector == X86_XCPT_GP
6392 || uVector == X86_XCPT_PF
6393 || uVector == X86_XCPT_AC))
6394 { /* likely */ }
6395 else
6396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6397
6398 /* Exception error-code reserved bits. */
6399 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6400 { /* likely */ }
6401 else
6402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6403
6404 /* Injecting a software interrupt, software exception or privileged software exception. */
6405 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6406 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6407 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6408 {
6409 /* Instruction length must be in the range 0-15. */
6410 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6411 { /* likely */ }
6412 else
6413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6414
6415 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6416 if ( pVmcs->u32EntryInstrLen == 0
6417 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6419 }
6420 }
6421 }
6422
6423 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6424 if (pVmcs->u32EntryMsrLoadCount)
6425 {
6426 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6427 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6428 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6429 { /* likely */ }
6430 else
6431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6432 }
6433
6434 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6435 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6436
6437 NOREF(pszInstr);
6438 NOREF(pszFailure);
6439 return VINF_SUCCESS;
6440}
6441
6442
6443/**
6444 * Checks VM-exit controls fields as part of VM-entry.
6445 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6446 *
6447 * @returns VBox status code.
6448 * @param pVCpu The cross context virtual CPU structure.
6449 * @param pszInstr The VMX instruction name (for logging purposes).
6450 */
6451IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6452{
6453 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6454 const char * const pszFailure = "VMFail";
6455
6456 /* VM-exit controls. */
6457 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6458 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6459 { /* likely */ }
6460 else
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6462
6463 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6464 { /* likely */ }
6465 else
6466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6467
6468 /* Save preemption timer without activating it. */
6469 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6470 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6474
6475 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6476 if (pVmcs->u32ExitMsrStoreCount)
6477 {
6478 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6479 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6480 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6481 { /* likely */ }
6482 else
6483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6484 }
6485
6486 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6487 if (pVmcs->u32ExitMsrLoadCount)
6488 {
6489 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6490 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6491 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6492 { /* likely */ }
6493 else
6494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6495 }
6496
6497 NOREF(pszInstr);
6498 NOREF(pszFailure);
6499 return VINF_SUCCESS;
6500}
6501
6502
6503/**
6504 * Checks VM-execution controls fields as part of VM-entry.
6505 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6506 *
6507 * @returns VBox status code.
6508 * @param pVCpu The cross context virtual CPU structure.
6509 * @param pszInstr The VMX instruction name (for logging purposes).
6510 *
6511 * @remarks This may update secondary-processor based VM-execution control fields
6512 * in the current VMCS if necessary.
6513 */
6514IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6515{
6516 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6517 const char * const pszFailure = "VMFail";
6518
6519 /* Pin-based VM-execution controls. */
6520 {
6521 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6522 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6523 { /* likely */ }
6524 else
6525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6526
6527 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6528 { /* likely */ }
6529 else
6530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6531 }
6532
6533 /* Processor-based VM-execution controls. */
6534 {
6535 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6536 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6537 { /* likely */ }
6538 else
6539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6540
6541 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6542 { /* likely */ }
6543 else
6544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6545 }
6546
6547 /* Secondary processor-based VM-execution controls. */
6548 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6549 {
6550 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6551 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6552 { /* likely */ }
6553 else
6554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6555
6556 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6557 { /* likely */ }
6558 else
6559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6560 }
6561 else
6562 Assert(!pVmcs->u32ProcCtls2);
6563
6564 /* CR3-target count. */
6565 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6566 { /* likely */ }
6567 else
6568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6569
6570 /* I/O bitmaps physical addresses. */
6571 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6572 {
6573 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6574 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6575 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6576 { /* likely */ }
6577 else
6578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6579
6580 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6581 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6582 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6583 { /* likely */ }
6584 else
6585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6586 }
6587
6588 /* MSR bitmap physical address. */
6589 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6590 {
6591 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6592 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6593 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6594 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6595 { /* likely */ }
6596 else
6597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6598
6599 /* Read the MSR bitmap. */
6600 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6601 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6602 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6603 if (RT_SUCCESS(rc))
6604 { /* likely */ }
6605 else
6606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6607 }
6608
6609 /* TPR shadow related controls. */
6610 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6611 {
6612 /* Virtual-APIC page physical address. */
6613 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6614 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6615 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6616 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6617 { /* likely */ }
6618 else
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6620
6621 /* TPR threshold without virtual-interrupt delivery. */
6622 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6623 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6624 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6625
6626 /* TPR threshold and VTPR. */
6627 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6628 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6629 {
6630 /* Read the VTPR from the virtual-APIC page. */
6631 uint8_t u8VTpr;
6632 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6633 if (RT_SUCCESS(rc))
6634 { /* likely */ }
6635 else
6636 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6637
6638 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6639 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6640 { /* likely */ }
6641 else
6642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6643 }
6644 }
6645 else
6646 {
6647 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6648 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6649 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6650 { /* likely */ }
6651 else
6652 {
6653 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6655 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6657 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6659 }
6660 }
6661
6662 /* NMI exiting and virtual-NMIs. */
6663 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6664 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6665 { /* likely */ }
6666 else
6667 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6668
6669 /* Virtual-NMIs and NMI-window exiting. */
6670 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6671 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6672 { /* likely */ }
6673 else
6674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6675
6676 /* Virtualize APIC accesses. */
6677 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6678 {
6679 /* APIC-access physical address. */
6680 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6681 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6682 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6683 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6684 { /* likely */ }
6685 else
6686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6687
6688 /*
6689 * Disallow APIC-access page and virtual-APIC page from being the same address.
6690 * Note! This is not an Intel requirement, but one imposed by our implementation.
6691 */
6692 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6693 * redirecting accesses between the APIC-access page and the virtual-APIC
6694 * page. If any nested hypervisor requires this, we can implement it later. */
6695 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6696 {
6697 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6698 if (GCPhysVirtApic != GCPhysApicAccess)
6699 { /* likely */ }
6700 else
6701 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6702 }
6703
6704 /*
6705 * Register the handler for the APIC-access page.
6706 *
6707 * We don't deregister the APIC-access page handler during the VM-exit as a different
6708 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6709 *
6710 * We leave the page registered until the first access that happens outside VMX non-root
6711 * mode. Guest software is allowed to access structures such as the APIC-access page
6712 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6713 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6714 *
6715 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6716 */
6717 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6718 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6719 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6720 if (RT_SUCCESS(rc))
6721 { /* likely */ }
6722 else
6723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6724 }
6725
6726 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6727 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6728 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6729 { /* likely */ }
6730 else
6731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6732
6733 /* Virtual-interrupt delivery requires external interrupt exiting. */
6734 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6735 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6736 { /* likely */ }
6737 else
6738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6739
6740 /* VPID. */
6741 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6742 || pVmcs->u16Vpid != 0)
6743 { /* likely */ }
6744 else
6745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6746
6747 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6748 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6749 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6750 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6751 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6752 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6753 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6754
6755 /* VMCS shadowing. */
6756 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6757 {
6758 /* VMREAD-bitmap physical address. */
6759 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6760 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6761 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6762 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6763 { /* likely */ }
6764 else
6765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6766
6767 /* VMWRITE-bitmap physical address. */
6768 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6769 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6770 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6771 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6772 { /* likely */ }
6773 else
6774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6775
6776 /* Read the VMREAD-bitmap. */
6777 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6778 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6779 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6780 if (RT_SUCCESS(rc))
6781 { /* likely */ }
6782 else
6783 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6784
6785 /* Read the VMWRITE-bitmap. */
6786 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6787 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6788 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6789 if (RT_SUCCESS(rc))
6790 { /* likely */ }
6791 else
6792 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6793 }
6794
6795 NOREF(pszInstr);
6796 NOREF(pszFailure);
6797 return VINF_SUCCESS;
6798}
6799
6800
6801/**
6802 * Loads the guest control registers, debug register and some MSRs as part of
6803 * VM-entry.
6804 *
6805 * @param pVCpu The cross context virtual CPU structure.
6806 */
6807IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6808{
6809 /*
6810 * Load guest control registers, debug registers and MSRs.
6811 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6812 */
6813 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6814
6815 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6816 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6817 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6818 CPUMSetGuestCR0(pVCpu, uGstCr0);
6819 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6820 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6821
6822 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6823 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6824
6825 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6826 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6827 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6828
6829 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6830 {
6831 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6832
6833 /* EFER MSR. */
6834 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6835 {
6836 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6837 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6838 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6839 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6840 if (fGstInLongMode)
6841 {
6842 /* If the nested-guest is in long mode, LMA and LME are both set. */
6843 Assert(fGstPaging);
6844 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6845 }
6846 else
6847 {
6848 /*
6849 * If the nested-guest is outside long mode:
6850 * - With paging: LMA is cleared, LME is cleared.
6851 * - Without paging: LMA is cleared, LME is left unmodified.
6852 */
6853 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6854 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6855 }
6856 }
6857 /* else: see below. */
6858 }
6859
6860 /* PAT MSR. */
6861 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6862 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6863
6864 /* EFER MSR. */
6865 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6866 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6867
6868 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6869 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6870
6871 /* We don't support IA32_BNDCFGS MSR yet. */
6872 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6873
6874 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6875}
6876
6877
6878/**
6879 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6880 *
6881 * @param pVCpu The cross context virtual CPU structure.
6882 */
6883IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6884{
6885 /*
6886 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6887 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6888 */
6889 /* CS, SS, ES, DS, FS, GS. */
6890 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6891 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6892 {
6893 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6894 CPUMSELREG VmcsSelReg;
6895 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6896 AssertRC(rc); NOREF(rc);
6897 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6898 {
6899 pGstSelReg->Sel = VmcsSelReg.Sel;
6900 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6901 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6902 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6903 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6904 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6905 }
6906 else
6907 {
6908 pGstSelReg->Sel = VmcsSelReg.Sel;
6909 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6910 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6911 switch (iSegReg)
6912 {
6913 case X86_SREG_CS:
6914 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6915 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6916 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6917 break;
6918
6919 case X86_SREG_SS:
6920 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6921 pGstSelReg->u32Limit = 0;
6922 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6923 break;
6924
6925 case X86_SREG_ES:
6926 case X86_SREG_DS:
6927 pGstSelReg->u64Base = 0;
6928 pGstSelReg->u32Limit = 0;
6929 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6930 break;
6931
6932 case X86_SREG_FS:
6933 case X86_SREG_GS:
6934 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6935 pGstSelReg->u32Limit = 0;
6936 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6937 break;
6938 }
6939 Assert(pGstSelReg->Attr.n.u1Unusable);
6940 }
6941 }
6942
6943 /* LDTR. */
6944 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6945 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6946 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6947 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6948 {
6949 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6950 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6951 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6952 }
6953 else
6954 {
6955 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6956 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6957 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6958 }
6959
6960 /* TR. */
6961 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6962 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6963 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6964 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6965 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6966 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6967 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6968
6969 /* GDTR. */
6970 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6971 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6972
6973 /* IDTR. */
6974 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6975 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6976}
6977
6978
6979/**
6980 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6981 *
6982 * @returns VBox status code.
6983 * @param pVCpu The cross context virtual CPU structure.
6984 * @param pszInstr The VMX instruction name (for logging purposes).
6985 */
6986IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6987{
6988 /*
6989 * Load guest MSRs.
6990 * See Intel spec. 26.4 "Loading MSRs".
6991 */
6992 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6993 const char *const pszFailure = "VM-exit";
6994
6995 /*
6996 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6997 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6998 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6999 */
7000 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7001 if (!cMsrs)
7002 return VINF_SUCCESS;
7003
7004 /*
7005 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7006 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7007 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7008 */
7009 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7010 if (fIsMsrCountValid)
7011 { /* likely */ }
7012 else
7013 {
7014 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7016 }
7017
7018 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7019 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7020 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7021 if (RT_SUCCESS(rc))
7022 {
7023 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7024 Assert(pMsr);
7025 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7026 {
7027 if ( !pMsr->u32Reserved
7028 && pMsr->u32Msr != MSR_K8_FS_BASE
7029 && pMsr->u32Msr != MSR_K8_GS_BASE
7030 && pMsr->u32Msr != MSR_K6_EFER
7031 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7032 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7033 {
7034 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7035 if (rcStrict == VINF_SUCCESS)
7036 continue;
7037
7038 /*
7039 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7040 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7041 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7042 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7043 * MSR in ring-0 if possible, or come up with a better, generic solution.
7044 */
7045 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7046 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7047 ? kVmxVDiag_Vmentry_MsrLoadRing3
7048 : kVmxVDiag_Vmentry_MsrLoad;
7049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7050 }
7051 else
7052 {
7053 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7054 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7055 }
7056 }
7057 }
7058 else
7059 {
7060 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7062 }
7063
7064 NOREF(pszInstr);
7065 NOREF(pszFailure);
7066 return VINF_SUCCESS;
7067}
7068
7069
7070/**
7071 * Loads the guest-state non-register state as part of VM-entry.
7072 *
7073 * @returns VBox status code.
7074 * @param pVCpu The cross context virtual CPU structure.
7075 *
7076 * @remarks This must be called only after loading the nested-guest register state
7077 * (especially nested-guest RIP).
7078 */
7079IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7080{
7081 /*
7082 * Load guest non-register state.
7083 * See Intel spec. 26.6 "Special Features of VM Entry"
7084 */
7085 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7086
7087 /*
7088 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7089 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7090 *
7091 * See Intel spec. 26.6.1 "Interruptibility State".
7092 */
7093 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7094 if ( !fEntryVectoring
7095 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7096 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7097 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7098 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7099
7100 /* NMI blocking. */
7101 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7102 {
7103 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7104 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7105 else
7106 {
7107 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7108 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7109 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7110 }
7111 }
7112 else
7113 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7114
7115 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7116
7117 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7118 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7119
7120 /* VPID is irrelevant. We don't support VPID yet. */
7121
7122 /* Clear address-range monitoring. */
7123 EMMonitorWaitClear(pVCpu);
7124}
7125
7126
7127/**
7128 * Loads the guest-state as part of VM-entry.
7129 *
7130 * @returns VBox status code.
7131 * @param pVCpu The cross context virtual CPU structure.
7132 * @param pszInstr The VMX instruction name (for logging purposes).
7133 *
7134 * @remarks This must be done after all the necessary steps prior to loading of
7135 * guest-state (e.g. checking various VMCS state).
7136 */
7137IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7138{
7139 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7140 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7141
7142 /*
7143 * Load guest RIP, RSP and RFLAGS.
7144 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7145 */
7146 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7147 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7148 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7149 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7150
7151 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7152 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7153 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7154
7155 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7156
7157 NOREF(pszInstr);
7158 return VINF_SUCCESS;
7159}
7160
7161
7162/**
7163 * Returns whether there are is a pending debug exception on VM-entry.
7164 *
7165 * @param pVCpu The cross context virtual CPU structure.
7166 * @param pszInstr The VMX instruction name (for logging purposes).
7167 */
7168IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7169{
7170 /*
7171 * Pending debug exceptions.
7172 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7173 */
7174 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7175 Assert(pVmcs);
7176
7177 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7178 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7179 if (fPendingDbgXcpt)
7180 {
7181 uint8_t uEntryIntInfoType;
7182 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7183 if (fEntryVectoring)
7184 {
7185 switch (uEntryIntInfoType)
7186 {
7187 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7188 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7189 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7190 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7191 fPendingDbgXcpt = false;
7192 break;
7193
7194 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7195 {
7196 /*
7197 * Whether the pending debug exception for software exceptions other than
7198 * #BP and #OF is delivered after injecting the exception or is discard
7199 * is CPU implementation specific. We will discard them (easier).
7200 */
7201 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7202 if ( uVector != X86_XCPT_BP
7203 && uVector != X86_XCPT_OF)
7204 fPendingDbgXcpt = false;
7205 RT_FALL_THRU();
7206 }
7207 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7208 {
7209 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7210 fPendingDbgXcpt = false;
7211 break;
7212 }
7213 }
7214 }
7215 else
7216 {
7217 /*
7218 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7219 * pending debug exception is held pending or is discarded is CPU implementation
7220 * specific. We will discard them (easier).
7221 */
7222 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7223 fPendingDbgXcpt = false;
7224
7225 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7226 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7227 fPendingDbgXcpt = false;
7228 }
7229 }
7230
7231 NOREF(pszInstr);
7232 return fPendingDbgXcpt;
7233}
7234
7235
7236/**
7237 * Set up the monitor-trap flag (MTF).
7238 *
7239 * @param pVCpu The cross context virtual CPU structure.
7240 * @param pszInstr The VMX instruction name (for logging purposes).
7241 */
7242IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7243{
7244 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7245 Assert(pVmcs);
7246 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7247 {
7248 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7249 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7250 }
7251 else
7252 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7253 NOREF(pszInstr);
7254}
7255
7256
7257/**
7258 * Sets up NMI-window exiting.
7259 *
7260 * @param pVCpu The cross context virtual CPU structure.
7261 * @param pszInstr The VMX instruction name (for logging purposes).
7262 */
7263IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7264{
7265 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7266 Assert(pVmcs);
7267 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7268 {
7269 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7270 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7271 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7272 }
7273 else
7274 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7275 NOREF(pszInstr);
7276}
7277
7278
7279/**
7280 * Set up the VMX-preemption timer.
7281 *
7282 * @param pVCpu The cross context virtual CPU structure.
7283 * @param pszInstr The VMX instruction name (for logging purposes).
7284 */
7285IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7286{
7287 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7288 Assert(pVmcs);
7289 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7290 {
7291 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7292 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7293 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7294
7295 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7296 }
7297 else
7298 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7299
7300 NOREF(pszInstr);
7301}
7302
7303
7304/**
7305 * Injects an event using TRPM given a VM-entry interruption info. and related
7306 * fields.
7307 *
7308 * @returns VBox status code.
7309 * @param pVCpu The cross context virtual CPU structure.
7310 * @param uEntryIntInfo The VM-entry interruption info.
7311 * @param uErrCode The error code associated with the event if any.
7312 * @param cbInstr The VM-entry instruction length (for software
7313 * interrupts and software exceptions). Pass 0
7314 * otherwise.
7315 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7316 */
7317IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7318 RTGCUINTPTR GCPtrFaultAddress)
7319{
7320 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7321
7322 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7323 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7324 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7325
7326 TRPMEVENT enmTrapType;
7327 switch (uType)
7328 {
7329 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7330 enmTrapType = TRPM_HARDWARE_INT;
7331 break;
7332
7333 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7334 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7335 enmTrapType = TRPM_TRAP;
7336 break;
7337
7338 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7339 enmTrapType = TRPM_SOFTWARE_INT;
7340 break;
7341
7342 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7343 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7344 enmTrapType = TRPM_SOFTWARE_INT;
7345 break;
7346
7347 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7348 Assert(uVector == X86_XCPT_DB);
7349 enmTrapType = TRPM_SOFTWARE_INT;
7350 break;
7351
7352 default:
7353 /* Shouldn't really happen. */
7354 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7355 break;
7356 }
7357
7358 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7359 AssertRCReturn(rc, rc);
7360
7361 if (fErrCodeValid)
7362 TRPMSetErrorCode(pVCpu, uErrCode);
7363
7364 if ( enmTrapType == TRPM_TRAP
7365 && uVector == X86_XCPT_PF)
7366 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7367 else if (enmTrapType == TRPM_SOFTWARE_INT)
7368 TRPMSetInstrLength(pVCpu, cbInstr);
7369
7370 return VINF_SUCCESS;
7371}
7372
7373
7374/**
7375 * Performs event injection (if any) as part of VM-entry.
7376 *
7377 * @param pVCpu The cross context virtual CPU structure.
7378 * @param pszInstr The VMX instruction name (for logging purposes).
7379 */
7380IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7381{
7382 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7383
7384 /*
7385 * Inject events.
7386 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7387 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7388 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7389 * the actually delivery of this event.
7390 *
7391 * See Intel spec. 26.5 "Event Injection".
7392 */
7393 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7394 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7395
7396 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7397 if (fEntryIntInfoValid)
7398 {
7399 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7400 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7401 {
7402 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7403 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7404 return VINF_SUCCESS;
7405 }
7406
7407 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7408 pVCpu->cpum.GstCtx.cr2);
7409 if (RT_SUCCESS(rc))
7410 {
7411 /*
7412 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7413 *
7414 * However, we do it here on VM-entry because while it continues to not be visible to
7415 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7416 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7417 * information field.
7418 *
7419 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7420 */
7421 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7422 }
7423 return rc;
7424 }
7425
7426 /*
7427 * Inject any pending guest debug exception.
7428 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7429 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7430 */
7431 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7432 if (fPendingDbgXcpt)
7433 {
7434 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7435 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7436 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7437 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7438 0 /* GCPtrFaultAddress */);
7439 }
7440
7441 NOREF(pszInstr);
7442 return VINF_SUCCESS;
7443}
7444
7445
7446/**
7447 * Initializes all read-only VMCS fields as part of VM-entry.
7448 *
7449 * @param pVCpu The cross context virtual CPU structure.
7450 */
7451IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7452{
7453 /*
7454 * Any VMCS field which we do not establish on every VM-exit but may potentially
7455 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7456 * specified to be undefined needs to be initialized here.
7457 *
7458 * Thus, it is especially important to clear the VM-exit qualification field
7459 * since it must be zero for VM-exits where it is not used. Similarly, the
7460 * VM-exit interruption information field's valid bit needs to be cleared for
7461 * the same reasons.
7462 */
7463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7464 Assert(pVmcs);
7465
7466 /* 16-bit (none currently). */
7467 /* 32-bit. */
7468 pVmcs->u32RoVmInstrError = 0;
7469 pVmcs->u32RoExitReason = 0;
7470 pVmcs->u32RoExitIntInfo = 0;
7471 pVmcs->u32RoExitIntErrCode = 0;
7472 pVmcs->u32RoIdtVectoringInfo = 0;
7473 pVmcs->u32RoIdtVectoringErrCode = 0;
7474 pVmcs->u32RoExitInstrLen = 0;
7475 pVmcs->u32RoExitInstrInfo = 0;
7476
7477 /* 64-bit. */
7478 pVmcs->u64RoGuestPhysAddr.u = 0;
7479
7480 /* Natural-width. */
7481 pVmcs->u64RoExitQual.u = 0;
7482 pVmcs->u64RoIoRcx.u = 0;
7483 pVmcs->u64RoIoRsi.u = 0;
7484 pVmcs->u64RoIoRdi.u = 0;
7485 pVmcs->u64RoIoRip.u = 0;
7486 pVmcs->u64RoGuestLinearAddr.u = 0;
7487}
7488
7489
7490/**
7491 * VMLAUNCH/VMRESUME instruction execution worker.
7492 *
7493 * @returns Strict VBox status code.
7494 * @param pVCpu The cross context virtual CPU structure.
7495 * @param cbInstr The instruction length in bytes.
7496 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7497 * VMXINSTRID_VMRESUME).
7498 *
7499 * @remarks Common VMX instruction checks are already expected to by the caller,
7500 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7501 */
7502IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7503{
7504# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7505 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7506 return VINF_EM_RAW_EMULATE_INSTR;
7507# else
7508 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7509 || uInstrId == VMXINSTRID_VMRESUME);
7510 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7511
7512 /* Nested-guest intercept. */
7513 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7514 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7515
7516 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7517
7518 /*
7519 * Basic VM-entry checks.
7520 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7521 * The checks following that do not have to follow a specific order.
7522 *
7523 * See Intel spec. 26.1 "Basic VM-entry Checks".
7524 */
7525
7526 /* CPL. */
7527 if (pVCpu->iem.s.uCpl == 0)
7528 { /* likely */ }
7529 else
7530 {
7531 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7532 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7533 return iemRaiseGeneralProtectionFault0(pVCpu);
7534 }
7535
7536 /* Current VMCS valid. */
7537 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7538 { /* likely */ }
7539 else
7540 {
7541 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7542 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7543 iemVmxVmFailInvalid(pVCpu);
7544 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7545 return VINF_SUCCESS;
7546 }
7547
7548 /* Current VMCS is not a shadow VMCS. */
7549 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7550 { /* likely */ }
7551 else
7552 {
7553 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7554 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7555 iemVmxVmFailInvalid(pVCpu);
7556 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7557 return VINF_SUCCESS;
7558 }
7559
7560 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7561 * use block-by-STI here which is not quite correct. */
7562 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7563 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7564 { /* likely */ }
7565 else
7566 {
7567 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7569 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7570 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7571 return VINF_SUCCESS;
7572 }
7573
7574 if (uInstrId == VMXINSTRID_VMLAUNCH)
7575 {
7576 /* VMLAUNCH with non-clear VMCS. */
7577 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7578 { /* likely */ }
7579 else
7580 {
7581 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7582 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7583 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7584 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7585 return VINF_SUCCESS;
7586 }
7587 }
7588 else
7589 {
7590 /* VMRESUME with non-launched VMCS. */
7591 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7592 { /* likely */ }
7593 else
7594 {
7595 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7596 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7597 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7599 return VINF_SUCCESS;
7600 }
7601 }
7602
7603 /*
7604 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7605 * while entering VMX non-root mode. We do some of this while checking VM-execution
7606 * controls. The guest hypervisor should not make assumptions and cannot expect
7607 * predictable behavior if changes to these structures are made in guest memory while
7608 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7609 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7610 *
7611 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7612 */
7613 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7614 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7615 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7616 if (RT_SUCCESS(rc))
7617 {
7618 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7619 if (RT_SUCCESS(rc))
7620 {
7621 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7622 if (RT_SUCCESS(rc))
7623 {
7624 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7625 if (RT_SUCCESS(rc))
7626 {
7627 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7628 iemVmxVmentryInitReadOnlyFields(pVCpu);
7629
7630 /*
7631 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7632 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7633 * VM-exit when required.
7634 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7635 */
7636 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7637
7638 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7639 if (RT_SUCCESS(rc))
7640 {
7641 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7642 if (RT_SUCCESS(rc))
7643 {
7644 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7645 if (RT_SUCCESS(rc))
7646 {
7647 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7648
7649 /* VMLAUNCH instruction must update the VMCS launch state. */
7650 if (uInstrId == VMXINSTRID_VMLAUNCH)
7651 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7652
7653 /* Perform the VMX transition (PGM updates). */
7654 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7655 if (rcStrict == VINF_SUCCESS)
7656 { /* likely */ }
7657 else if (RT_SUCCESS(rcStrict))
7658 {
7659 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7660 VBOXSTRICTRC_VAL(rcStrict)));
7661 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7662 }
7663 else
7664 {
7665 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7666 return rcStrict;
7667 }
7668
7669 /* We've now entered nested-guest execution. */
7670 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7671
7672 /*
7673 * The priority of potential VM-exits during VM-entry is important.
7674 * The priorities of VM-exits and events are listed from highest
7675 * to lowest as follows:
7676 *
7677 * 1. Event injection.
7678 * 2. Trap on task-switch (T flag set in TSS).
7679 * 3. TPR below threshold / APIC-write.
7680 * 4. SMI, INIT.
7681 * 5. MTF exit.
7682 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7683 * 7. VMX-preemption timer.
7684 * 9. NMI-window exit.
7685 * 10. NMI injection.
7686 * 11. Interrupt-window exit.
7687 * 12. Virtual-interrupt injection.
7688 * 13. Interrupt injection.
7689 * 14. Process next instruction (fetch, decode, execute).
7690 */
7691
7692 /* Setup the VMX-preemption timer. */
7693 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7694
7695 /* Setup monitor-trap flag. */
7696 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7697
7698 /* Setup NMI-window exiting. */
7699 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7700
7701 /* Now that we've switched page tables, we can go ahead and inject any event. */
7702 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7703 if (RT_SUCCESS(rcStrict))
7704 {
7705 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7706# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7707 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7708 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7709 if (rcSched != VINF_SUCCESS)
7710 iemSetPassUpStatus(pVCpu, rcSched);
7711# endif
7712 return VINF_SUCCESS;
7713 }
7714
7715 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7716 return rcStrict;
7717 }
7718 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7719 }
7720 }
7721 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7722 }
7723
7724 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7725 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7726 return VINF_SUCCESS;
7727 }
7728 }
7729 }
7730
7731 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7732 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7733 return VINF_SUCCESS;
7734# endif
7735}
7736
7737
7738/**
7739 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7740 * (causes a VM-exit) or not.
7741 *
7742 * @returns @c true if the instruction is intercepted, @c false otherwise.
7743 * @param pVCpu The cross context virtual CPU structure.
7744 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7745 * VMX_EXIT_WRMSR).
7746 * @param idMsr The MSR.
7747 */
7748IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7749{
7750 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7751 Assert( uExitReason == VMX_EXIT_RDMSR
7752 || uExitReason == VMX_EXIT_WRMSR);
7753
7754 /* Consult the MSR bitmap if the feature is supported. */
7755 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7756 Assert(pVmcs);
7757 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7758 {
7759 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7760 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7761 if (uExitReason == VMX_EXIT_RDMSR)
7762 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7763 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7764 }
7765
7766 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7767 return true;
7768}
7769
7770
7771/**
7772 * VMREAD common (memory/register) instruction execution worker
7773 *
7774 * @returns Strict VBox status code.
7775 * @param pVCpu The cross context virtual CPU structure.
7776 * @param cbInstr The instruction length in bytes.
7777 * @param pu64Dst Where to write the VMCS value (only updated when
7778 * VINF_SUCCESS is returned).
7779 * @param u64FieldEnc The VMCS field encoding.
7780 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7781 * NULL.
7782 */
7783IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7784 PCVMXVEXITINFO pExitInfo)
7785{
7786 /* Nested-guest intercept. */
7787 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7788 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7789 {
7790 if (pExitInfo)
7791 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7792 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7793 }
7794
7795 /* CPL. */
7796 if (pVCpu->iem.s.uCpl == 0)
7797 { /* likely */ }
7798 else
7799 {
7800 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7801 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7802 return iemRaiseGeneralProtectionFault0(pVCpu);
7803 }
7804
7805 /* VMCS pointer in root mode. */
7806 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7807 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7808 { /* likely */ }
7809 else
7810 {
7811 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7813 iemVmxVmFailInvalid(pVCpu);
7814 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7815 return VINF_SUCCESS;
7816 }
7817
7818 /* VMCS-link pointer in non-root mode. */
7819 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7820 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7821 { /* likely */ }
7822 else
7823 {
7824 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7825 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7826 iemVmxVmFailInvalid(pVCpu);
7827 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7828 return VINF_SUCCESS;
7829 }
7830
7831 /* Supported VMCS field. */
7832 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7833 { /* likely */ }
7834 else
7835 {
7836 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7837 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7838 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7839 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7840 return VINF_SUCCESS;
7841 }
7842
7843 /*
7844 * Setup reading from the current or shadow VMCS.
7845 */
7846 uint8_t *pbVmcs;
7847 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7848 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7849 else
7850 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7851 Assert(pbVmcs);
7852
7853 VMXVMCSFIELDENC FieldEnc;
7854 FieldEnc.u = u64FieldEnc;
7855 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7856 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7857 uint8_t const uWidthType = (uWidth << 2) | uType;
7858 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7859 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7860 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7861 Assert(offField < VMX_V_VMCS_SIZE);
7862
7863 /*
7864 * Read the VMCS component based on the field's effective width.
7865 *
7866 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7867 * indicates high bits (little endian).
7868 *
7869 * Note! The caller is responsible to trim the result and update registers
7870 * or memory locations are required. Here we just zero-extend to the largest
7871 * type (i.e. 64-bits).
7872 */
7873 uint8_t *pbField = pbVmcs + offField;
7874 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7875 switch (uEffWidth)
7876 {
7877 case VMX_VMCS_ENC_WIDTH_64BIT:
7878 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7879 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7880 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7881 }
7882 return VINF_SUCCESS;
7883}
7884
7885
7886/**
7887 * VMREAD (64-bit register) instruction execution worker.
7888 *
7889 * @returns Strict VBox status code.
7890 * @param pVCpu The cross context virtual CPU structure.
7891 * @param cbInstr The instruction length in bytes.
7892 * @param pu64Dst Where to store the VMCS field's value.
7893 * @param u64FieldEnc The VMCS field encoding.
7894 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7895 * NULL.
7896 */
7897IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7898 PCVMXVEXITINFO pExitInfo)
7899{
7900 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7901 if (rcStrict == VINF_SUCCESS)
7902 {
7903 iemVmxVmreadSuccess(pVCpu, cbInstr);
7904 return VINF_SUCCESS;
7905 }
7906
7907 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7908 return rcStrict;
7909}
7910
7911
7912/**
7913 * VMREAD (32-bit register) instruction execution worker.
7914 *
7915 * @returns Strict VBox status code.
7916 * @param pVCpu The cross context virtual CPU structure.
7917 * @param cbInstr The instruction length in bytes.
7918 * @param pu32Dst Where to store the VMCS field's value.
7919 * @param u32FieldEnc The VMCS field encoding.
7920 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7921 * NULL.
7922 */
7923IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7924 PCVMXVEXITINFO pExitInfo)
7925{
7926 uint64_t u64Dst;
7927 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7928 if (rcStrict == VINF_SUCCESS)
7929 {
7930 *pu32Dst = u64Dst;
7931 iemVmxVmreadSuccess(pVCpu, cbInstr);
7932 return VINF_SUCCESS;
7933 }
7934
7935 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7936 return rcStrict;
7937}
7938
7939
7940/**
7941 * VMREAD (memory) instruction execution worker.
7942 *
7943 * @returns Strict VBox status code.
7944 * @param pVCpu The cross context virtual CPU structure.
7945 * @param cbInstr The instruction length in bytes.
7946 * @param iEffSeg The effective segment register to use with @a u64Val.
7947 * Pass UINT8_MAX if it is a register access.
7948 * @param GCPtrDst The guest linear address to store the VMCS field's
7949 * value.
7950 * @param u64FieldEnc The VMCS field encoding.
7951 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7952 * NULL.
7953 */
7954IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
7955 PCVMXVEXITINFO pExitInfo)
7956{
7957 uint64_t u64Dst;
7958 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7959 if (rcStrict == VINF_SUCCESS)
7960 {
7961 /*
7962 * Write the VMCS field's value to the location specified in guest-memory.
7963 */
7964 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7965 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7966 else
7967 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7968 if (rcStrict == VINF_SUCCESS)
7969 {
7970 iemVmxVmreadSuccess(pVCpu, cbInstr);
7971 return VINF_SUCCESS;
7972 }
7973
7974 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7975 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7976 return rcStrict;
7977 }
7978
7979 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7980 return rcStrict;
7981}
7982
7983
7984/**
7985 * VMWRITE instruction execution worker.
7986 *
7987 * @returns Strict VBox status code.
7988 * @param pVCpu The cross context virtual CPU structure.
7989 * @param cbInstr The instruction length in bytes.
7990 * @param iEffSeg The effective segment register to use with @a u64Val.
7991 * Pass UINT8_MAX if it is a register access.
7992 * @param u64Val The value to write (or guest linear address to the
7993 * value), @a iEffSeg will indicate if it's a memory
7994 * operand.
7995 * @param u64FieldEnc The VMCS field encoding.
7996 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7997 * NULL.
7998 */
7999IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8000 PCVMXVEXITINFO pExitInfo)
8001{
8002 /* Nested-guest intercept. */
8003 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8004 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8005 {
8006 if (pExitInfo)
8007 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8008 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8009 }
8010
8011 /* CPL. */
8012 if (pVCpu->iem.s.uCpl == 0)
8013 { /* likely */ }
8014 else
8015 {
8016 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8017 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8018 return iemRaiseGeneralProtectionFault0(pVCpu);
8019 }
8020
8021 /* VMCS pointer in root mode. */
8022 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8023 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8024 { /* likely */ }
8025 else
8026 {
8027 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8028 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8029 iemVmxVmFailInvalid(pVCpu);
8030 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8031 return VINF_SUCCESS;
8032 }
8033
8034 /* VMCS-link pointer in non-root mode. */
8035 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8036 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8037 { /* likely */ }
8038 else
8039 {
8040 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8041 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8042 iemVmxVmFailInvalid(pVCpu);
8043 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8044 return VINF_SUCCESS;
8045 }
8046
8047 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8048 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8049 if (!fIsRegOperand)
8050 {
8051 /* Read the value from the specified guest memory location. */
8052 VBOXSTRICTRC rcStrict;
8053 RTGCPTR const GCPtrVal = u64Val;
8054 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8055 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8056 else
8057 {
8058 uint32_t u32Val;
8059 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8060 u64Val = u32Val;
8061 }
8062 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8063 {
8064 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8065 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8066 return rcStrict;
8067 }
8068 }
8069 else
8070 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8071
8072 /* Supported VMCS field. */
8073 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8074 { /* likely */ }
8075 else
8076 {
8077 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8078 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8079 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8080 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8081 return VINF_SUCCESS;
8082 }
8083
8084 /* Read-only VMCS field. */
8085 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8086 if ( !fIsFieldReadOnly
8087 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8088 { /* likely */ }
8089 else
8090 {
8091 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8092 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8093 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8094 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8095 return VINF_SUCCESS;
8096 }
8097
8098 /*
8099 * Setup writing to the current or shadow VMCS.
8100 */
8101 uint8_t *pbVmcs;
8102 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8103 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8104 else
8105 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8106 Assert(pbVmcs);
8107
8108 VMXVMCSFIELDENC FieldEnc;
8109 FieldEnc.u = u64FieldEnc;
8110 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8111 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8112 uint8_t const uWidthType = (uWidth << 2) | uType;
8113 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8114 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8115 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8116 Assert(offField < VMX_V_VMCS_SIZE);
8117
8118 /*
8119 * Write the VMCS component based on the field's effective width.
8120 *
8121 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8122 * indicates high bits (little endian).
8123 */
8124 uint8_t *pbField = pbVmcs + offField;
8125 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8126 switch (uEffWidth)
8127 {
8128 case VMX_VMCS_ENC_WIDTH_64BIT:
8129 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8130 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8131 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8132 }
8133
8134 iemVmxVmSucceed(pVCpu);
8135 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8136 return VINF_SUCCESS;
8137}
8138
8139
8140/**
8141 * VMCLEAR instruction execution worker.
8142 *
8143 * @returns Strict VBox status code.
8144 * @param pVCpu The cross context virtual CPU structure.
8145 * @param cbInstr The instruction length in bytes.
8146 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8147 * @param GCPtrVmcs The linear address of the VMCS pointer.
8148 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8149 * NULL.
8150 *
8151 * @remarks Common VMX instruction checks are already expected to by the caller,
8152 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8153 */
8154IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8155 PCVMXVEXITINFO pExitInfo)
8156{
8157 /* Nested-guest intercept. */
8158 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8159 {
8160 if (pExitInfo)
8161 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8162 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8163 }
8164
8165 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8166
8167 /* CPL. */
8168 if (pVCpu->iem.s.uCpl == 0)
8169 { /* likely */ }
8170 else
8171 {
8172 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8174 return iemRaiseGeneralProtectionFault0(pVCpu);
8175 }
8176
8177 /* Get the VMCS pointer from the location specified by the source memory operand. */
8178 RTGCPHYS GCPhysVmcs;
8179 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8180 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8181 { /* likely */ }
8182 else
8183 {
8184 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8185 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8186 return rcStrict;
8187 }
8188
8189 /* VMCS pointer alignment. */
8190 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8191 { /* likely */ }
8192 else
8193 {
8194 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8195 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8196 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8197 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8198 return VINF_SUCCESS;
8199 }
8200
8201 /* VMCS physical-address width limits. */
8202 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8203 { /* likely */ }
8204 else
8205 {
8206 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8207 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8208 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8209 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8210 return VINF_SUCCESS;
8211 }
8212
8213 /* VMCS is not the VMXON region. */
8214 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8215 { /* likely */ }
8216 else
8217 {
8218 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8219 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8220 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8221 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8222 return VINF_SUCCESS;
8223 }
8224
8225 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8226 restriction imposed by our implementation. */
8227 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8228 { /* likely */ }
8229 else
8230 {
8231 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8232 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8233 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8234 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8235 return VINF_SUCCESS;
8236 }
8237
8238 /*
8239 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8240 *
8241 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8242 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8243 * to 'clear'.
8244 */
8245 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8246 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8247 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8248 {
8249 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8250 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8251 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8252 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8253 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8254 }
8255 else
8256 {
8257 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8258 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8259 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8260 if (RT_FAILURE(rcStrict))
8261 return rcStrict;
8262 }
8263
8264 iemVmxVmSucceed(pVCpu);
8265 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8266 return VINF_SUCCESS;
8267}
8268
8269
8270/**
8271 * VMPTRST instruction execution worker.
8272 *
8273 * @returns Strict VBox status code.
8274 * @param pVCpu The cross context virtual CPU structure.
8275 * @param cbInstr The instruction length in bytes.
8276 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8277 * @param GCPtrVmcs The linear address of where to store the current VMCS
8278 * pointer.
8279 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8280 * NULL.
8281 *
8282 * @remarks Common VMX instruction checks are already expected to by the caller,
8283 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8284 */
8285IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8286 PCVMXVEXITINFO pExitInfo)
8287{
8288 /* Nested-guest intercept. */
8289 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8290 {
8291 if (pExitInfo)
8292 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8293 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8294 }
8295
8296 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8297
8298 /* CPL. */
8299 if (pVCpu->iem.s.uCpl == 0)
8300 { /* likely */ }
8301 else
8302 {
8303 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8304 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8305 return iemRaiseGeneralProtectionFault0(pVCpu);
8306 }
8307
8308 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8309 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8310 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8311 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8312 {
8313 iemVmxVmSucceed(pVCpu);
8314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315 return rcStrict;
8316 }
8317
8318 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8319 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8320 return rcStrict;
8321}
8322
8323
8324/**
8325 * VMPTRLD instruction execution worker.
8326 *
8327 * @returns Strict VBox status code.
8328 * @param pVCpu The cross context virtual CPU structure.
8329 * @param cbInstr The instruction length in bytes.
8330 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8331 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8332 * NULL.
8333 *
8334 * @remarks Common VMX instruction checks are already expected to by the caller,
8335 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8336 */
8337IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8338 PCVMXVEXITINFO pExitInfo)
8339{
8340 /* Nested-guest intercept. */
8341 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8342 {
8343 if (pExitInfo)
8344 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8345 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8346 }
8347
8348 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8349
8350 /* CPL. */
8351 if (pVCpu->iem.s.uCpl == 0)
8352 { /* likely */ }
8353 else
8354 {
8355 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8356 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8357 return iemRaiseGeneralProtectionFault0(pVCpu);
8358 }
8359
8360 /* Get the VMCS pointer from the location specified by the source memory operand. */
8361 RTGCPHYS GCPhysVmcs;
8362 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8363 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8364 { /* likely */ }
8365 else
8366 {
8367 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8368 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8369 return rcStrict;
8370 }
8371
8372 /* VMCS pointer alignment. */
8373 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8374 { /* likely */ }
8375 else
8376 {
8377 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8378 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8379 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8380 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8381 return VINF_SUCCESS;
8382 }
8383
8384 /* VMCS physical-address width limits. */
8385 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8386 { /* likely */ }
8387 else
8388 {
8389 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8390 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8391 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8392 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8393 return VINF_SUCCESS;
8394 }
8395
8396 /* VMCS is not the VMXON region. */
8397 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8398 { /* likely */ }
8399 else
8400 {
8401 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8402 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8403 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8404 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8405 return VINF_SUCCESS;
8406 }
8407
8408 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8409 restriction imposed by our implementation. */
8410 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8411 { /* likely */ }
8412 else
8413 {
8414 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8416 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8417 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8418 return VINF_SUCCESS;
8419 }
8420
8421 /* Read just the VMCS revision from the VMCS. */
8422 VMXVMCSREVID VmcsRevId;
8423 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8424 if (RT_SUCCESS(rc))
8425 { /* likely */ }
8426 else
8427 {
8428 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8429 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8430 return rc;
8431 }
8432
8433 /*
8434 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8435 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8436 */
8437 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8438 && ( !VmcsRevId.n.fIsShadowVmcs
8439 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8440 { /* likely */ }
8441 else
8442 {
8443 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8444 {
8445 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8446 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8447 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8448 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8449 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8450 return VINF_SUCCESS;
8451 }
8452
8453 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8454 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8455 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8456 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8457 return VINF_SUCCESS;
8458 }
8459
8460 /*
8461 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8462 * the cache of an existing, current VMCS back to guest memory before loading a new,
8463 * different current VMCS.
8464 */
8465 bool fLoadVmcsFromMem;
8466 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8467 {
8468 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8469 {
8470 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8471 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8472 fLoadVmcsFromMem = true;
8473 }
8474 else
8475 fLoadVmcsFromMem = false;
8476 }
8477 else
8478 fLoadVmcsFromMem = true;
8479
8480 if (fLoadVmcsFromMem)
8481 {
8482 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8483 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8484 sizeof(VMXVVMCS));
8485 if (RT_SUCCESS(rc))
8486 { /* likely */ }
8487 else
8488 {
8489 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8490 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8491 return rc;
8492 }
8493 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8494 }
8495
8496 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8497 iemVmxVmSucceed(pVCpu);
8498 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8499 return VINF_SUCCESS;
8500}
8501
8502
8503/**
8504 * INVVPID instruction execution worker.
8505 *
8506 * @returns Strict VBox status code.
8507 * @param pVCpu The cross context virtual CPU structure.
8508 * @param cbInstr The instruction length in bytes.
8509 * @param iEffSeg The segment of the invvpid descriptor.
8510 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8511 * @param u64InvvpidType The invalidation type.
8512 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8513 * NULL.
8514 *
8515 * @remarks Common VMX instruction checks are already expected to by the caller,
8516 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8517 */
8518IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8519 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8520{
8521 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8522 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8523 return iemRaiseUndefinedOpcode(pVCpu);
8524
8525 /* Nested-guest intercept. */
8526 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8527 {
8528 if (pExitInfo)
8529 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8530 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8531 }
8532
8533 /* CPL. */
8534 if (pVCpu->iem.s.uCpl != 0)
8535 {
8536 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8537 return iemRaiseGeneralProtectionFault0(pVCpu);
8538 }
8539
8540 /*
8541 * Validate INVVPID invalidation type.
8542 *
8543 * The instruction specifies exactly ONE of the supported invalidation types.
8544 *
8545 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8546 * supported. In theory, it's possible for a CPU to not support flushing individual
8547 * addresses but all the other types or any other combination. We do not take any
8548 * shortcuts here by assuming the types we currently expose to the guest.
8549 */
8550 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8551 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8552 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8553 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8554 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8555 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8556 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8557 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8558 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8559 { /* likely */ }
8560 else
8561 {
8562 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8564 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8565 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8566 return VINF_SUCCESS;
8567 }
8568
8569 /*
8570 * Fetch the invvpid descriptor from guest memory.
8571 */
8572 RTUINT128U uDesc;
8573 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8574 if (rcStrict == VINF_SUCCESS)
8575 {
8576 /*
8577 * Validate the descriptor.
8578 */
8579 if (uDesc.s.Lo > 0xfff)
8580 {
8581 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8582 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8583 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8584 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8585 return VINF_SUCCESS;
8586 }
8587
8588 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8589 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8590 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8591 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8592 switch (u64InvvpidType)
8593 {
8594 case VMXTLBFLUSHVPID_INDIV_ADDR:
8595 {
8596 if (uVpid != 0)
8597 {
8598 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8599 {
8600 /* Invalidate mappings for the linear address tagged with VPID. */
8601 /** @todo PGM support for VPID? Currently just flush everything. */
8602 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8603 iemVmxVmSucceed(pVCpu);
8604 }
8605 else
8606 {
8607 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8608 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8609 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8610 }
8611 }
8612 else
8613 {
8614 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8616 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8617 }
8618 break;
8619 }
8620
8621 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8622 {
8623 if (uVpid != 0)
8624 {
8625 /* Invalidate all mappings with VPID. */
8626 /** @todo PGM support for VPID? Currently just flush everything. */
8627 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8628 iemVmxVmSucceed(pVCpu);
8629 }
8630 else
8631 {
8632 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8633 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8634 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8635 }
8636 break;
8637 }
8638
8639 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8640 {
8641 /* Invalidate all mappings with non-zero VPIDs. */
8642 /** @todo PGM support for VPID? Currently just flush everything. */
8643 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8644 iemVmxVmSucceed(pVCpu);
8645 break;
8646 }
8647
8648 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8649 {
8650 if (uVpid != 0)
8651 {
8652 /* Invalidate all mappings with VPID except global translations. */
8653 /** @todo PGM support for VPID? Currently just flush everything. */
8654 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8655 iemVmxVmSucceed(pVCpu);
8656 }
8657 else
8658 {
8659 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8660 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8661 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8662 }
8663 break;
8664 }
8665 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8666 }
8667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8668 }
8669 return rcStrict;
8670}
8671
8672
8673/**
8674 * VMXON instruction execution worker.
8675 *
8676 * @returns Strict VBox status code.
8677 * @param pVCpu The cross context virtual CPU structure.
8678 * @param cbInstr The instruction length in bytes.
8679 * @param iEffSeg The effective segment register to use with @a
8680 * GCPtrVmxon.
8681 * @param GCPtrVmxon The linear address of the VMXON pointer.
8682 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8683 * NULL.
8684 *
8685 * @remarks Common VMX instruction checks are already expected to by the caller,
8686 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8687 */
8688IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8689 PCVMXVEXITINFO pExitInfo)
8690{
8691 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8692 {
8693 /* CPL. */
8694 if (pVCpu->iem.s.uCpl == 0)
8695 { /* likely */ }
8696 else
8697 {
8698 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8699 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8700 return iemRaiseGeneralProtectionFault0(pVCpu);
8701 }
8702
8703 /* A20M (A20 Masked) mode. */
8704 if (PGMPhysIsA20Enabled(pVCpu))
8705 { /* likely */ }
8706 else
8707 {
8708 Log(("vmxon: A20M mode -> #GP(0)\n"));
8709 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8710 return iemRaiseGeneralProtectionFault0(pVCpu);
8711 }
8712
8713 /* CR0. */
8714 {
8715 /* CR0 MB1 bits. */
8716 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8717 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8718 { /* likely */ }
8719 else
8720 {
8721 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8722 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8723 return iemRaiseGeneralProtectionFault0(pVCpu);
8724 }
8725
8726 /* CR0 MBZ bits. */
8727 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8728 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8729 { /* likely */ }
8730 else
8731 {
8732 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8733 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8734 return iemRaiseGeneralProtectionFault0(pVCpu);
8735 }
8736 }
8737
8738 /* CR4. */
8739 {
8740 /* CR4 MB1 bits. */
8741 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8742 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8743 { /* likely */ }
8744 else
8745 {
8746 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8747 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8748 return iemRaiseGeneralProtectionFault0(pVCpu);
8749 }
8750
8751 /* CR4 MBZ bits. */
8752 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8753 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8754 { /* likely */ }
8755 else
8756 {
8757 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8758 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8759 return iemRaiseGeneralProtectionFault0(pVCpu);
8760 }
8761 }
8762
8763 /* Feature control MSR's LOCK and VMXON bits. */
8764 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8765 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8766 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8767 { /* likely */ }
8768 else
8769 {
8770 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8771 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8772 return iemRaiseGeneralProtectionFault0(pVCpu);
8773 }
8774
8775 /* Get the VMXON pointer from the location specified by the source memory operand. */
8776 RTGCPHYS GCPhysVmxon;
8777 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8778 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8779 { /* likely */ }
8780 else
8781 {
8782 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8784 return rcStrict;
8785 }
8786
8787 /* VMXON region pointer alignment. */
8788 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8789 { /* likely */ }
8790 else
8791 {
8792 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8793 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8794 iemVmxVmFailInvalid(pVCpu);
8795 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8796 return VINF_SUCCESS;
8797 }
8798
8799 /* VMXON physical-address width limits. */
8800 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8801 { /* likely */ }
8802 else
8803 {
8804 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8805 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8806 iemVmxVmFailInvalid(pVCpu);
8807 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8808 return VINF_SUCCESS;
8809 }
8810
8811 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8812 restriction imposed by our implementation. */
8813 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8814 { /* likely */ }
8815 else
8816 {
8817 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8818 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8819 iemVmxVmFailInvalid(pVCpu);
8820 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8821 return VINF_SUCCESS;
8822 }
8823
8824 /* Read the VMCS revision ID from the VMXON region. */
8825 VMXVMCSREVID VmcsRevId;
8826 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8827 if (RT_SUCCESS(rc))
8828 { /* likely */ }
8829 else
8830 {
8831 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8832 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8833 return rc;
8834 }
8835
8836 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8837 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8838 { /* likely */ }
8839 else
8840 {
8841 /* Revision ID mismatch. */
8842 if (!VmcsRevId.n.fIsShadowVmcs)
8843 {
8844 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8845 VmcsRevId.n.u31RevisionId));
8846 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8847 iemVmxVmFailInvalid(pVCpu);
8848 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8849 return VINF_SUCCESS;
8850 }
8851
8852 /* Shadow VMCS disallowed. */
8853 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8854 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8855 iemVmxVmFailInvalid(pVCpu);
8856 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8857 return VINF_SUCCESS;
8858 }
8859
8860 /*
8861 * Record that we're in VMX operation, block INIT, block and disable A20M.
8862 */
8863 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8864 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8865 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8866
8867 /* Clear address-range monitoring. */
8868 EMMonitorWaitClear(pVCpu);
8869 /** @todo NSTVMX: Intel PT. */
8870
8871 iemVmxVmSucceed(pVCpu);
8872 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8873 return VINF_SUCCESS;
8874 }
8875 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8876 {
8877 /* Nested-guest intercept. */
8878 if (pExitInfo)
8879 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8880 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8881 }
8882
8883 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8884
8885 /* CPL. */
8886 if (pVCpu->iem.s.uCpl > 0)
8887 {
8888 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8889 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8890 return iemRaiseGeneralProtectionFault0(pVCpu);
8891 }
8892
8893 /* VMXON when already in VMX root mode. */
8894 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8895 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8896 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8897 return VINF_SUCCESS;
8898}
8899
8900
8901/**
8902 * Implements 'VMXOFF'.
8903 *
8904 * @remarks Common VMX instruction checks are already expected to by the caller,
8905 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8906 */
8907IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8908{
8909 /* Nested-guest intercept. */
8910 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8911 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8912
8913 /* CPL. */
8914 if (pVCpu->iem.s.uCpl == 0)
8915 { /* likely */ }
8916 else
8917 {
8918 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8919 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8920 return iemRaiseGeneralProtectionFault0(pVCpu);
8921 }
8922
8923 /* Dual monitor treatment of SMIs and SMM. */
8924 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8925 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8926 { /* likely */ }
8927 else
8928 {
8929 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8930 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8931 return VINF_SUCCESS;
8932 }
8933
8934 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8935 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8936 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8937
8938 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8939 { /** @todo NSTVMX: Unblock SMI. */ }
8940
8941 EMMonitorWaitClear(pVCpu);
8942 /** @todo NSTVMX: Unblock and enable A20M. */
8943
8944 iemVmxVmSucceed(pVCpu);
8945 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8946 return VINF_SUCCESS;
8947}
8948
8949
8950/**
8951 * Implements 'VMXON'.
8952 */
8953IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8954{
8955 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8956}
8957
8958
8959/**
8960 * Implements 'VMLAUNCH'.
8961 */
8962IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8963{
8964 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8965}
8966
8967
8968/**
8969 * Implements 'VMRESUME'.
8970 */
8971IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8972{
8973 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8974}
8975
8976
8977/**
8978 * Implements 'VMPTRLD'.
8979 */
8980IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8981{
8982 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8983}
8984
8985
8986/**
8987 * Implements 'VMPTRST'.
8988 */
8989IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8990{
8991 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8992}
8993
8994
8995/**
8996 * Implements 'VMCLEAR'.
8997 */
8998IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8999{
9000 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9001}
9002
9003
9004/**
9005 * Implements 'VMWRITE' register.
9006 */
9007IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9008{
9009 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9010}
9011
9012
9013/**
9014 * Implements 'VMWRITE' memory.
9015 */
9016IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9017{
9018 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9019}
9020
9021
9022/**
9023 * Implements 'VMREAD' register (64-bit).
9024 */
9025IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9026{
9027 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9028}
9029
9030
9031/**
9032 * Implements 'VMREAD' register (32-bit).
9033 */
9034IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9035{
9036 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9037}
9038
9039
9040/**
9041 * Implements 'VMREAD' memory, 64-bit register.
9042 */
9043IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9044{
9045 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9046}
9047
9048
9049/**
9050 * Implements 'VMREAD' memory, 32-bit register.
9051 */
9052IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9053{
9054 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9055}
9056
9057
9058/**
9059 * Implements 'INVVPID'.
9060 */
9061IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9062{
9063 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9064}
9065
9066
9067/**
9068 * Implements VMX's implementation of PAUSE.
9069 */
9070IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9071{
9072 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9073 {
9074 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9075 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9076 return rcStrict;
9077 }
9078
9079 /*
9080 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9081 * a VM-exit, the instruction operates normally.
9082 */
9083 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9084 return VINF_SUCCESS;
9085}
9086
9087#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9088
9089
9090/**
9091 * Implements 'VMCALL'.
9092 */
9093IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9094{
9095#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9096 /* Nested-guest intercept. */
9097 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9098 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9099#endif
9100
9101 /* Join forces with vmmcall. */
9102 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9103}
9104
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