VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 78982

Last change on this file since 78982 was 78982, checked in by vboxsync, 5 years ago

VMM/IEM: Nested VMX: bugref:9180 Setup interrupt-window exiting similar to NMI-window exiting. Check for interrupt-window exiting before executing subsequent instructions in iemExecOneInner..
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 78982 2019-06-05 08:58:53Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64FieldEnc The VMCS field encoding.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the VM-exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param uExitQual The VM-exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = uExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitQual The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
1984 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
1986 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1987 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1988 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1989 CPUMSetGuestCR0(pVCpu, uValidCr0);
1990 }
1991
1992 /* CR4. */
1993 {
1994 /* CR4 MB1 bits are not modified. */
1995 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1996 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1997 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1998 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1999 if (fHostInLongMode)
2000 uValidCr4 |= X86_CR4_PAE;
2001 else
2002 uValidCr4 &= ~X86_CR4_PCIDE;
2003 CPUMSetGuestCR4(pVCpu, uValidCr4);
2004 }
2005
2006 /* CR3 (host value validated while checking host-state during VM-entry). */
2007 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2008
2009 /* DR7. */
2010 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2011
2012 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2013
2014 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2015 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2016 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2017 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2018
2019 /* FS, GS bases are loaded later while we load host segment registers. */
2020
2021 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2022 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2023 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2024 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2025 {
2026 if (fHostInLongMode)
2027 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2028 else
2029 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2030 }
2031
2032 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2033
2034 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2035 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2036 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2037
2038 /* We don't support IA32_BNDCFGS MSR yet. */
2039}
2040
2041
2042/**
2043 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2044 *
2045 * @param pVCpu The cross context virtual CPU structure.
2046 */
2047IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2048{
2049 /*
2050 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2051 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2052 *
2053 * Warning! Be careful to not touch fields that are reserved by VT-x,
2054 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2055 */
2056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2057 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2058
2059 /* CS, SS, ES, DS, FS, GS. */
2060 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2061 {
2062 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2063 bool const fUnusable = RT_BOOL(HostSel == 0);
2064 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2065
2066 /* Selector. */
2067 pSelReg->Sel = HostSel;
2068 pSelReg->ValidSel = HostSel;
2069 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2070
2071 /* Limit. */
2072 pSelReg->u32Limit = 0xffffffff;
2073
2074 /* Base. */
2075 pSelReg->u64Base = 0;
2076
2077 /* Attributes. */
2078 if (iSegReg == X86_SREG_CS)
2079 {
2080 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2081 pSelReg->Attr.n.u1DescType = 1;
2082 pSelReg->Attr.n.u2Dpl = 0;
2083 pSelReg->Attr.n.u1Present = 1;
2084 pSelReg->Attr.n.u1Long = fHostInLongMode;
2085 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2086 pSelReg->Attr.n.u1Granularity = 1;
2087 Assert(!pSelReg->Attr.n.u1Unusable);
2088 Assert(!fUnusable);
2089 }
2090 else
2091 {
2092 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2093 pSelReg->Attr.n.u1DescType = 1;
2094 pSelReg->Attr.n.u2Dpl = 0;
2095 pSelReg->Attr.n.u1Present = 1;
2096 pSelReg->Attr.n.u1DefBig = 1;
2097 pSelReg->Attr.n.u1Granularity = 1;
2098 pSelReg->Attr.n.u1Unusable = fUnusable;
2099 }
2100 }
2101
2102 /* FS base. */
2103 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2104 || fHostInLongMode)
2105 {
2106 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2107 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2108 }
2109
2110 /* GS base. */
2111 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2112 || fHostInLongMode)
2113 {
2114 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2115 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2116 }
2117
2118 /* TR. */
2119 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2120 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2121 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2122 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2123 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2124 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2125 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2126 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2127 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2128 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2132
2133 /* LDTR (Warning! do not touch the base and limits here). */
2134 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2135 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2136 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2137 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2138
2139 /* GDTR. */
2140 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2141 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2142 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2143
2144 /* IDTR.*/
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2146 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2147 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2148}
2149
2150
2151/**
2152 * Checks host PDPTes as part of VM-exit.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param uExitReason The VM-exit reason (for logging purposes).
2156 */
2157IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2158{
2159 /*
2160 * Check host PDPTEs.
2161 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2162 */
2163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2164 const char *const pszFailure = "VMX-abort";
2165 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2166
2167 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2168 && !fHostInLongMode)
2169 {
2170 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2171 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2172 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2173 if (RT_SUCCESS(rc))
2174 {
2175 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2176 {
2177 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2178 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2179 { /* likely */ }
2180 else
2181 {
2182 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2183 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2184 }
2185 }
2186 }
2187 else
2188 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2189 }
2190
2191 NOREF(pszFailure);
2192 NOREF(uExitReason);
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2199 *
2200 * @returns VBox status code.
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param pszInstr The VMX instruction name (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Load host MSRs.
2208 * See Intel spec. 27.6 "Loading MSRs".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212
2213 /*
2214 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2215 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2216 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2217 */
2218 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2219 if (!cMsrs)
2220 return VINF_SUCCESS;
2221
2222 /*
2223 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2224 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2225 * implementation causes a VMX-abort followed by a triple-fault.
2226 */
2227 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2228 if (fIsMsrCountValid)
2229 { /* likely */ }
2230 else
2231 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2232
2233 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2234 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2235 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2236 if (RT_SUCCESS(rc))
2237 {
2238 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2239 Assert(pMsr);
2240 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2241 {
2242 if ( !pMsr->u32Reserved
2243 && pMsr->u32Msr != MSR_K8_FS_BASE
2244 && pMsr->u32Msr != MSR_K8_GS_BASE
2245 && pMsr->u32Msr != MSR_K6_EFER
2246 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2247 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2248 {
2249 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2250 if (rcStrict == VINF_SUCCESS)
2251 continue;
2252
2253 /*
2254 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2255 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2256 * recording the MSR index in the auxiliary info. field and indicated further by our
2257 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2258 * if possible, or come up with a better, generic solution.
2259 */
2260 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2261 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2262 ? kVmxVDiag_Vmexit_MsrLoadRing3
2263 : kVmxVDiag_Vmexit_MsrLoad;
2264 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2265 }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2268 }
2269 }
2270 else
2271 {
2272 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2273 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2274 }
2275
2276 NOREF(uExitReason);
2277 NOREF(pszFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Loads the host state as part of VM-exit.
2284 *
2285 * @returns Strict VBox status code.
2286 * @param pVCpu The cross context virtual CPU structure.
2287 * @param uExitReason The VM-exit reason (for logging purposes).
2288 */
2289IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2290{
2291 /*
2292 * Load host state.
2293 * See Intel spec. 27.5 "Loading Host State".
2294 */
2295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2296 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2297
2298 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2299 if ( CPUMIsGuestInLongMode(pVCpu)
2300 && !fHostInLongMode)
2301 {
2302 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2303 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2304 }
2305
2306 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2307 iemVmxVmexitLoadHostSegRegs(pVCpu);
2308
2309 /*
2310 * Load host RIP, RSP and RFLAGS.
2311 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2312 */
2313 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2314 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2315 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2316
2317 /* Clear address range monitoring. */
2318 EMMonitorWaitClear(pVCpu);
2319
2320 /* Perform the VMX transition (PGM updates). */
2321 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2322 if (rcStrict == VINF_SUCCESS)
2323 {
2324 /* Check host PDPTEs (only when we've fully switched page tables_. */
2325 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2326 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2327 if (RT_FAILURE(rc))
2328 {
2329 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2330 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2331 }
2332 }
2333 else if (RT_SUCCESS(rcStrict))
2334 {
2335 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2336 uExitReason));
2337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2338 }
2339 else
2340 {
2341 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2342 return VBOXSTRICTRC_VAL(rcStrict);
2343 }
2344
2345 Assert(rcStrict == VINF_SUCCESS);
2346
2347 /* Load MSRs from the VM-exit auto-load MSR area. */
2348 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2349 if (RT_FAILURE(rc))
2350 {
2351 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2352 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2353 }
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/**
2359 * Gets VM-exit instruction information along with any displacement for an
2360 * instruction VM-exit.
2361 *
2362 * @returns The VM-exit instruction information.
2363 * @param pVCpu The cross context virtual CPU structure.
2364 * @param uExitReason The VM-exit reason.
2365 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2366 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2367 * NULL.
2368 */
2369IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2370{
2371 RTGCPTR GCPtrDisp;
2372 VMXEXITINSTRINFO ExitInstrInfo;
2373 ExitInstrInfo.u = 0;
2374
2375 /*
2376 * Get and parse the ModR/M byte from our decoded opcodes.
2377 */
2378 uint8_t bRm;
2379 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2380 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2381 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2382 {
2383 /*
2384 * ModR/M indicates register addressing.
2385 *
2386 * The primary/secondary register operands are reported in the iReg1 or iReg2
2387 * fields depending on whether it is a read/write form.
2388 */
2389 uint8_t idxReg1;
2390 uint8_t idxReg2;
2391 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2392 {
2393 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2394 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2395 }
2396 else
2397 {
2398 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2399 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2400 }
2401 ExitInstrInfo.All.u2Scaling = 0;
2402 ExitInstrInfo.All.iReg1 = idxReg1;
2403 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2404 ExitInstrInfo.All.fIsRegOperand = 1;
2405 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2406 ExitInstrInfo.All.iSegReg = 0;
2407 ExitInstrInfo.All.iIdxReg = 0;
2408 ExitInstrInfo.All.fIdxRegInvalid = 1;
2409 ExitInstrInfo.All.iBaseReg = 0;
2410 ExitInstrInfo.All.fBaseRegInvalid = 1;
2411 ExitInstrInfo.All.iReg2 = idxReg2;
2412
2413 /* Displacement not applicable for register addressing. */
2414 GCPtrDisp = 0;
2415 }
2416 else
2417 {
2418 /*
2419 * ModR/M indicates memory addressing.
2420 */
2421 uint8_t uScale = 0;
2422 bool fBaseRegValid = false;
2423 bool fIdxRegValid = false;
2424 uint8_t iBaseReg = 0;
2425 uint8_t iIdxReg = 0;
2426 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2427 {
2428 /*
2429 * Parse the ModR/M, displacement for 16-bit addressing mode.
2430 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2431 */
2432 uint16_t u16Disp = 0;
2433 uint8_t const offDisp = offModRm + sizeof(bRm);
2434 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2435 {
2436 /* Displacement without any registers. */
2437 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2438 }
2439 else
2440 {
2441 /* Register (index and base). */
2442 switch (bRm & X86_MODRM_RM_MASK)
2443 {
2444 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2445 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2446 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2447 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2448 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2449 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2450 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2451 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2452 }
2453
2454 /* Register + displacement. */
2455 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2456 {
2457 case 0: break;
2458 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2459 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2460 default:
2461 {
2462 /* Register addressing, handled at the beginning. */
2463 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2464 break;
2465 }
2466 }
2467 }
2468
2469 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2470 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2471 }
2472 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2473 {
2474 /*
2475 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2476 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2477 */
2478 uint32_t u32Disp = 0;
2479 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2480 {
2481 /* Displacement without any registers. */
2482 uint8_t const offDisp = offModRm + sizeof(bRm);
2483 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2484 }
2485 else
2486 {
2487 /* Register (and perhaps scale, index and base). */
2488 uint8_t offDisp = offModRm + sizeof(bRm);
2489 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2490 if (iBaseReg == 4)
2491 {
2492 /* An SIB byte follows the ModR/M byte, parse it. */
2493 uint8_t bSib;
2494 uint8_t const offSib = offModRm + sizeof(bRm);
2495 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2496
2497 /* A displacement may follow SIB, update its offset. */
2498 offDisp += sizeof(bSib);
2499
2500 /* Get the scale. */
2501 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2502
2503 /* Get the index register. */
2504 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2505 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2506
2507 /* Get the base register. */
2508 iBaseReg = bSib & X86_SIB_BASE_MASK;
2509 fBaseRegValid = true;
2510 if (iBaseReg == 5)
2511 {
2512 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2513 {
2514 /* Mod is 0 implies a 32-bit displacement with no base. */
2515 fBaseRegValid = false;
2516 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2517 }
2518 else
2519 {
2520 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2521 iBaseReg = X86_GREG_xBP;
2522 }
2523 }
2524 }
2525
2526 /* Register + displacement. */
2527 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2528 {
2529 case 0: /* Handled above */ break;
2530 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2531 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2532 default:
2533 {
2534 /* Register addressing, handled at the beginning. */
2535 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2536 break;
2537 }
2538 }
2539 }
2540
2541 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2542 }
2543 else
2544 {
2545 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2546
2547 /*
2548 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2549 * See Intel instruction spec. 2.2 "IA-32e Mode".
2550 */
2551 uint64_t u64Disp = 0;
2552 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2553 if (fRipRelativeAddr)
2554 {
2555 /*
2556 * RIP-relative addressing mode.
2557 *
2558 * The displacement is 32-bit signed implying an offset range of +/-2G.
2559 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2560 */
2561 uint8_t const offDisp = offModRm + sizeof(bRm);
2562 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2563 }
2564 else
2565 {
2566 uint8_t offDisp = offModRm + sizeof(bRm);
2567
2568 /*
2569 * Register (and perhaps scale, index and base).
2570 *
2571 * REX.B extends the most-significant bit of the base register. However, REX.B
2572 * is ignored while determining whether an SIB follows the opcode. Hence, we
2573 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2574 *
2575 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2576 */
2577 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2578 if (iBaseReg == 4)
2579 {
2580 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2581 uint8_t bSib;
2582 uint8_t const offSib = offModRm + sizeof(bRm);
2583 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2584
2585 /* Displacement may follow SIB, update its offset. */
2586 offDisp += sizeof(bSib);
2587
2588 /* Get the scale. */
2589 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2590
2591 /* Get the index. */
2592 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2593 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2594
2595 /* Get the base. */
2596 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2597 fBaseRegValid = true;
2598 if (iBaseReg == 5)
2599 {
2600 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2601 {
2602 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2603 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2604 }
2605 else
2606 {
2607 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2608 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2609 }
2610 }
2611 }
2612 iBaseReg |= pVCpu->iem.s.uRexB;
2613
2614 /* Register + displacement. */
2615 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2616 {
2617 case 0: /* Handled above */ break;
2618 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2619 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2620 default:
2621 {
2622 /* Register addressing, handled at the beginning. */
2623 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2624 break;
2625 }
2626 }
2627 }
2628
2629 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2630 }
2631
2632 /*
2633 * The primary or secondary register operand is reported in iReg2 depending
2634 * on whether the primary operand is in read/write form.
2635 */
2636 uint8_t idxReg2;
2637 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2638 {
2639 idxReg2 = bRm & X86_MODRM_RM_MASK;
2640 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2641 idxReg2 |= pVCpu->iem.s.uRexB;
2642 }
2643 else
2644 {
2645 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2646 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2647 idxReg2 |= pVCpu->iem.s.uRexReg;
2648 }
2649 ExitInstrInfo.All.u2Scaling = uScale;
2650 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2651 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2652 ExitInstrInfo.All.fIsRegOperand = 0;
2653 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2654 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2655 ExitInstrInfo.All.iIdxReg = iIdxReg;
2656 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2657 ExitInstrInfo.All.iBaseReg = iBaseReg;
2658 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2659 ExitInstrInfo.All.iReg2 = idxReg2;
2660 }
2661
2662 /*
2663 * Handle exceptions to the norm for certain instructions.
2664 * (e.g. some instructions convey an instruction identity in place of iReg2).
2665 */
2666 switch (uExitReason)
2667 {
2668 case VMX_EXIT_GDTR_IDTR_ACCESS:
2669 {
2670 Assert(VMXINSTRID_IS_VALID(uInstrId));
2671 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2672 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2673 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2674 break;
2675 }
2676
2677 case VMX_EXIT_LDTR_TR_ACCESS:
2678 {
2679 Assert(VMXINSTRID_IS_VALID(uInstrId));
2680 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2681 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2682 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2683 break;
2684 }
2685
2686 case VMX_EXIT_RDRAND:
2687 case VMX_EXIT_RDSEED:
2688 {
2689 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2690 break;
2691 }
2692 }
2693
2694 /* Update displacement and return the constructed VM-exit instruction information field. */
2695 if (pGCPtrDisp)
2696 *pGCPtrDisp = GCPtrDisp;
2697
2698 return ExitInstrInfo.u;
2699}
2700
2701
2702/**
2703 * VMX VM-exit handler.
2704 *
2705 * @returns Strict VBox status code.
2706 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2707 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2708 * triple-fault.
2709 *
2710 * @param pVCpu The cross context virtual CPU structure.
2711 * @param uExitReason The VM-exit reason.
2712 *
2713 * @remarks Make sure VM-exit qualification is updated before calling this
2714 * function!
2715 */
2716IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2717{
2718# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2719 RT_NOREF2(pVCpu, uExitReason);
2720 return VINF_EM_RAW_EMULATE_INSTR;
2721# else
2722 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2723 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2724 | CPUMCTX_EXTRN_EFER /* MSRs */
2725 | CPUMCTX_EXTRN_SYSENTER_MSRS
2726 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2727 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2728 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2729 | CPUMCTX_EXTRN_TR /* Task register */
2730 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2731 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2732
2733 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2734 Assert(pVmcs);
2735
2736 /* Ensure VM-entry interruption information valid bit isn't set. */
2737 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2738
2739 /*
2740 * Update the VM-exit reason. Other VMCS data fields are expected to be updated by the caller already.
2741 */
2742 pVmcs->u32RoExitReason = uExitReason;
2743 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2744 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2745
2746 /*
2747 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2748 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2749 */
2750 {
2751 uint8_t uVector;
2752 uint32_t fFlags;
2753 uint32_t uErrCode;
2754 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2755 if (fInEventDelivery)
2756 {
2757 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2758 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2759 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2760 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2761 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2762 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2763 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2764 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2765 }
2766 }
2767
2768 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2769 Assert(pVmcs->u64RoIoRcx.u == 0);
2770 Assert(pVmcs->u64RoIoRsi.u == 0);
2771 Assert(pVmcs->u64RoIoRdi.u == 0);
2772 Assert(pVmcs->u64RoIoRip.u == 0);
2773
2774 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2775 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2776 {
2777 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2778 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2779 }
2780
2781 /*
2782 * Save the guest state back into the VMCS.
2783 * We only need to save the state when the VM-entry was successful.
2784 */
2785 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2786 if (!fVmentryFailed)
2787 {
2788 /*
2789 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2790 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2791 *
2792 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2793 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2794 * as guest-CPU state would not been modified. Hence for now, we do this only when
2795 * the VM-entry succeeded.
2796 */
2797 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2798 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2799 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2800 {
2801 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2802 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2803 else
2804 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2805 }
2806
2807 /*
2808 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2809 * occurs in enclave mode/SMM which we don't support yet.
2810 *
2811 * If we ever add support for it, we can pass just the lower bits to the functions
2812 * below, till then an assert should suffice.
2813 */
2814 Assert(!RT_HI_U16(uExitReason));
2815
2816 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2817 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2818 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2819 if (RT_SUCCESS(rc))
2820 { /* likely */ }
2821 else
2822 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2823
2824 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2825 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2826 }
2827 else
2828 {
2829 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2830 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2831 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2832 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2833 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2834 }
2835
2836 /*
2837 * Clear any pending VMX nested-guest force-flags.
2838 * These force-flags have no effect on guest execution and will
2839 * be re-evaluated and setup on the next nested-guest VM-entry.
2840 */
2841 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2842 | VMCPU_FF_VMX_MTF
2843 | VMCPU_FF_VMX_APIC_WRITE
2844 | VMCPU_FF_VMX_INT_WINDOW
2845 | VMCPU_FF_VMX_NMI_WINDOW);
2846
2847 /* Restore the host (outer guest) state. */
2848 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2849 if (RT_SUCCESS(rcStrict))
2850 {
2851 Assert(rcStrict == VINF_SUCCESS);
2852 rcStrict = VINF_VMX_VMEXIT;
2853 }
2854 else
2855 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2856
2857 /* Notify HM that we've completed the VM-exit. */
2858 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2859
2860 /* We're no longer in nested-guest execution mode. */
2861 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2862
2863# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2864 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2865 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2866 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2867 if (rcSched != VINF_SUCCESS)
2868 iemSetPassUpStatus(pVCpu, rcSched);
2869# endif
2870 return rcStrict;
2871# endif
2872}
2873
2874
2875/**
2876 * VMX VM-exit handler for VM-exits due to instruction execution.
2877 *
2878 * This is intended for instructions where the caller provides all the relevant
2879 * VM-exit information.
2880 *
2881 * @returns Strict VBox status code.
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param pExitInfo Pointer to the VM-exit information.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2886{
2887 /*
2888 * For instructions where any of the following fields are not applicable:
2889 * - VM-exit instruction info. is undefined.
2890 * - VM-exit qualification must be cleared.
2891 * - VM-exit guest-linear address is undefined.
2892 * - VM-exit guest-physical address is undefined.
2893 *
2894 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2895 * instruction execution. For VM-exits that are not due to instruction execution this
2896 * field is undefined.
2897 *
2898 * In our implementation in IEM, all undefined fields are generally cleared. However,
2899 * if the caller supplies information (from say the physical CPU directly) it is
2900 * then possible that the undefined fields are not cleared.
2901 *
2902 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2903 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2904 */
2905 Assert(pExitInfo);
2906 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2907 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2908 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2909
2910 /* Update all the relevant fields from the VM-exit instruction information struct. */
2911 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2912 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2913 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2914 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2915 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2916
2917 /* Perform the VM-exit. */
2918 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2919}
2920
2921
2922/**
2923 * VMX VM-exit handler for VM-exits due to instruction execution.
2924 *
2925 * This is intended for instructions that only provide the VM-exit instruction
2926 * length.
2927 *
2928 * @param pVCpu The cross context virtual CPU structure.
2929 * @param uExitReason The VM-exit reason.
2930 * @param cbInstr The instruction length in bytes.
2931 */
2932IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2933{
2934 VMXVEXITINFO ExitInfo;
2935 RT_ZERO(ExitInfo);
2936 ExitInfo.uReason = uExitReason;
2937 ExitInfo.cbInstr = cbInstr;
2938
2939#ifdef VBOX_STRICT
2940 /*
2941 * To prevent us from shooting ourselves in the foot.
2942 * The follow instructions should convey more than just the instruction length.
2943 */
2944 switch (uExitReason)
2945 {
2946 case VMX_EXIT_INVEPT:
2947 case VMX_EXIT_INVPCID:
2948 case VMX_EXIT_LDTR_TR_ACCESS:
2949 case VMX_EXIT_GDTR_IDTR_ACCESS:
2950 case VMX_EXIT_VMCLEAR:
2951 case VMX_EXIT_VMPTRLD:
2952 case VMX_EXIT_VMPTRST:
2953 case VMX_EXIT_VMREAD:
2954 case VMX_EXIT_VMWRITE:
2955 case VMX_EXIT_VMXON:
2956 case VMX_EXIT_XRSTORS:
2957 case VMX_EXIT_XSAVES:
2958 case VMX_EXIT_RDRAND:
2959 case VMX_EXIT_RDSEED:
2960 case VMX_EXIT_IO_INSTR:
2961 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2962 break;
2963 }
2964#endif
2965
2966 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2967}
2968
2969
2970/**
2971 * VMX VM-exit handler for VM-exits due to instruction execution.
2972 *
2973 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2974 * instruction information and VM-exit qualification fields.
2975 *
2976 * @param pVCpu The cross context virtual CPU structure.
2977 * @param uExitReason The VM-exit reason.
2978 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2979 * @param cbInstr The instruction length in bytes.
2980 *
2981 * @remarks Do not use this for INS/OUTS instruction.
2982 */
2983IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2984{
2985 VMXVEXITINFO ExitInfo;
2986 RT_ZERO(ExitInfo);
2987 ExitInfo.uReason = uExitReason;
2988 ExitInfo.cbInstr = cbInstr;
2989
2990 /*
2991 * Update the VM-exit qualification field with displacement bytes.
2992 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2993 */
2994 switch (uExitReason)
2995 {
2996 case VMX_EXIT_INVEPT:
2997 case VMX_EXIT_INVPCID:
2998 case VMX_EXIT_INVVPID:
2999 case VMX_EXIT_LDTR_TR_ACCESS:
3000 case VMX_EXIT_GDTR_IDTR_ACCESS:
3001 case VMX_EXIT_VMCLEAR:
3002 case VMX_EXIT_VMPTRLD:
3003 case VMX_EXIT_VMPTRST:
3004 case VMX_EXIT_VMREAD:
3005 case VMX_EXIT_VMWRITE:
3006 case VMX_EXIT_VMXON:
3007 case VMX_EXIT_XRSTORS:
3008 case VMX_EXIT_XSAVES:
3009 case VMX_EXIT_RDRAND:
3010 case VMX_EXIT_RDSEED:
3011 {
3012 /* Construct the VM-exit instruction information. */
3013 RTGCPTR GCPtrDisp;
3014 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3015
3016 /* Update the VM-exit instruction information. */
3017 ExitInfo.InstrInfo.u = uInstrInfo;
3018
3019 /* Update the VM-exit qualification. */
3020 ExitInfo.u64Qual = GCPtrDisp;
3021 break;
3022 }
3023
3024 default:
3025 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3026 break;
3027 }
3028
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030}
3031
3032
3033/**
3034 * VMX VM-exit handler for VM-exits due to INVLPG.
3035 *
3036 * @returns Strict VBox status code.
3037 * @param pVCpu The cross context virtual CPU structure.
3038 * @param GCPtrPage The guest-linear address of the page being invalidated.
3039 * @param cbInstr The instruction length in bytes.
3040 */
3041IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3042{
3043 VMXVEXITINFO ExitInfo;
3044 RT_ZERO(ExitInfo);
3045 ExitInfo.uReason = VMX_EXIT_INVLPG;
3046 ExitInfo.cbInstr = cbInstr;
3047 ExitInfo.u64Qual = GCPtrPage;
3048 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3049
3050 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3051}
3052
3053
3054/**
3055 * VMX VM-exit handler for VM-exits due to LMSW.
3056 *
3057 * @returns Strict VBox status code.
3058 * @param pVCpu The cross context virtual CPU structure.
3059 * @param uGuestCr0 The current guest CR0.
3060 * @param pu16NewMsw The machine-status word specified in LMSW's source
3061 * operand. This will be updated depending on the VMX
3062 * guest/host CR0 mask if LMSW is not intercepted.
3063 * @param GCPtrEffDst The guest-linear address of the source operand in case
3064 * of a memory operand. For register operand, pass
3065 * NIL_RTGCPTR.
3066 * @param cbInstr The instruction length in bytes.
3067 */
3068IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3069 uint8_t cbInstr)
3070{
3071 Assert(pu16NewMsw);
3072
3073 uint16_t const uNewMsw = *pu16NewMsw;
3074 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3075 {
3076 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3077
3078 VMXVEXITINFO ExitInfo;
3079 RT_ZERO(ExitInfo);
3080 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3081 ExitInfo.cbInstr = cbInstr;
3082
3083 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3084 if (fMemOperand)
3085 {
3086 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3087 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3088 }
3089
3090 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3094
3095 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3096 }
3097
3098 /*
3099 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3100 * CR0 guest/host mask must be left unmodified.
3101 *
3102 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3103 */
3104 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3105 Assert(pVmcs);
3106 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3107 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3108 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3109
3110 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3111}
3112
3113
3114/**
3115 * VMX VM-exit handler for VM-exits due to CLTS.
3116 *
3117 * @returns Strict VBox status code.
3118 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3119 * VM-exit but must not modify the guest CR0.TS bit.
3120 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3121 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3122 * CR0 fixed bits in VMX operation).
3123 * @param pVCpu The cross context virtual CPU structure.
3124 * @param cbInstr The instruction length in bytes.
3125 */
3126IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3127{
3128 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3129 Assert(pVmcs);
3130
3131 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3132 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3133
3134 /*
3135 * If CR0.TS is owned by the host:
3136 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3137 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3138 * CLTS instruction completes without clearing CR0.TS.
3139 *
3140 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3141 */
3142 if (fGstHostMask & X86_CR0_TS)
3143 {
3144 if (fReadShadow & X86_CR0_TS)
3145 {
3146 Log2(("clts: Guest intercept -> VM-exit\n"));
3147
3148 VMXVEXITINFO ExitInfo;
3149 RT_ZERO(ExitInfo);
3150 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3151 ExitInfo.cbInstr = cbInstr;
3152 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3153 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3154 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3155 }
3156
3157 return VINF_VMX_MODIFIES_BEHAVIOR;
3158 }
3159
3160 /*
3161 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3162 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3163 */
3164 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3165}
3166
3167
3168/**
3169 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3170 * (CR0/CR4 write).
3171 *
3172 * @returns Strict VBox status code.
3173 * @param pVCpu The cross context virtual CPU structure.
3174 * @param iCrReg The control register (either CR0 or CR4).
3175 * @param uGuestCrX The current guest CR0/CR4.
3176 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3177 * if no VM-exit is caused.
3178 * @param iGReg The general register from which the CR0/CR4 value is
3179 * being loaded.
3180 * @param cbInstr The instruction length in bytes.
3181 */
3182IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3183 uint8_t cbInstr)
3184{
3185 Assert(puNewCrX);
3186 Assert(iCrReg == 0 || iCrReg == 4);
3187 Assert(iGReg < X86_GREG_COUNT);
3188
3189 uint64_t const uNewCrX = *puNewCrX;
3190 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3191 {
3192 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3193
3194 VMXVEXITINFO ExitInfo;
3195 RT_ZERO(ExitInfo);
3196 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3197 ExitInfo.cbInstr = cbInstr;
3198 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3201 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3202 }
3203
3204 /*
3205 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3206 * must not be modified the instruction.
3207 *
3208 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3209 */
3210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3211 Assert(pVmcs);
3212 uint64_t uGuestCrX;
3213 uint64_t fGstHostMask;
3214 if (iCrReg == 0)
3215 {
3216 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3217 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3218 fGstHostMask = pVmcs->u64Cr0Mask.u;
3219 }
3220 else
3221 {
3222 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3223 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3224 fGstHostMask = pVmcs->u64Cr4Mask.u;
3225 }
3226
3227 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3228 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3229}
3230
3231
3232/**
3233 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3234 *
3235 * @returns VBox strict status code.
3236 * @param pVCpu The cross context virtual CPU structure.
3237 * @param iGReg The general register to which the CR3 value is being stored.
3238 * @param cbInstr The instruction length in bytes.
3239 */
3240IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3241{
3242 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3243 Assert(pVmcs);
3244 Assert(iGReg < X86_GREG_COUNT);
3245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3246
3247 /*
3248 * If the CR3-store exiting control is set, we must cause a VM-exit.
3249 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3250 */
3251 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3252 {
3253 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3254
3255 VMXVEXITINFO ExitInfo;
3256 RT_ZERO(ExitInfo);
3257 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3258 ExitInfo.cbInstr = cbInstr;
3259 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3260 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3261 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3262 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3263 }
3264
3265 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3266}
3267
3268
3269/**
3270 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3271 *
3272 * @returns VBox strict status code.
3273 * @param pVCpu The cross context virtual CPU structure.
3274 * @param uNewCr3 The new CR3 value.
3275 * @param iGReg The general register from which the CR3 value is being
3276 * loaded.
3277 * @param cbInstr The instruction length in bytes.
3278 */
3279IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3280{
3281 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3282 Assert(pVmcs);
3283 Assert(iGReg < X86_GREG_COUNT);
3284
3285 /*
3286 * If the CR3-load exiting control is set and the new CR3 value does not
3287 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3288 *
3289 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3290 */
3291 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3292 {
3293 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3294 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3295
3296 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3297 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3298 if (!fIntercept)
3299 {
3300 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3301 {
3302 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3303 if (uNewCr3 != uCr3TargetValue)
3304 {
3305 fIntercept = true;
3306 break;
3307 }
3308 }
3309 }
3310
3311 if (fIntercept)
3312 {
3313 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3314
3315 VMXVEXITINFO ExitInfo;
3316 RT_ZERO(ExitInfo);
3317 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3318 ExitInfo.cbInstr = cbInstr;
3319 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3321 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3322 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3323 }
3324 }
3325
3326 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3327}
3328
3329
3330/**
3331 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3332 *
3333 * @returns VBox strict status code.
3334 * @param pVCpu The cross context virtual CPU structure.
3335 * @param iGReg The general register to which the CR8 value is being stored.
3336 * @param cbInstr The instruction length in bytes.
3337 */
3338IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3339{
3340 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3341 Assert(pVmcs);
3342 Assert(iGReg < X86_GREG_COUNT);
3343
3344 /*
3345 * If the CR8-store exiting control is set, we must cause a VM-exit.
3346 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3347 */
3348 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3349 {
3350 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3351
3352 VMXVEXITINFO ExitInfo;
3353 RT_ZERO(ExitInfo);
3354 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3355 ExitInfo.cbInstr = cbInstr;
3356 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3357 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3358 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3359 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3360 }
3361
3362 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3363}
3364
3365
3366/**
3367 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3368 *
3369 * @returns VBox strict status code.
3370 * @param pVCpu The cross context virtual CPU structure.
3371 * @param iGReg The general register from which the CR8 value is being
3372 * loaded.
3373 * @param cbInstr The instruction length in bytes.
3374 */
3375IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3376{
3377 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3378 Assert(pVmcs);
3379 Assert(iGReg < X86_GREG_COUNT);
3380
3381 /*
3382 * If the CR8-load exiting control is set, we must cause a VM-exit.
3383 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3384 */
3385 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3386 {
3387 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3388
3389 VMXVEXITINFO ExitInfo;
3390 RT_ZERO(ExitInfo);
3391 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3392 ExitInfo.cbInstr = cbInstr;
3393 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3394 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3395 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3396 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3397 }
3398
3399 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3400}
3401
3402
3403/**
3404 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3405 * GReg,DRx' (DRx read).
3406 *
3407 * @returns VBox strict status code.
3408 * @param pVCpu The cross context virtual CPU structure.
3409 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3410 * VMXINSTRID_MOV_FROM_DRX).
3411 * @param iDrReg The debug register being accessed.
3412 * @param iGReg The general register to/from which the DRx value is being
3413 * store/loaded.
3414 * @param cbInstr The instruction length in bytes.
3415 */
3416IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3417 uint8_t cbInstr)
3418{
3419 Assert(iDrReg <= 7);
3420 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3421 Assert(iGReg < X86_GREG_COUNT);
3422
3423 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3424 Assert(pVmcs);
3425
3426 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3427 {
3428 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3429 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3430 VMXVEXITINFO ExitInfo;
3431 RT_ZERO(ExitInfo);
3432 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3433 ExitInfo.cbInstr = cbInstr;
3434 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3435 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3436 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3437 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3438 }
3439
3440 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3441}
3442
3443
3444/**
3445 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3446 *
3447 * @returns VBox strict status code.
3448 * @param pVCpu The cross context virtual CPU structure.
3449 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3450 * VMXINSTRID_IO_OUT).
3451 * @param u16Port The I/O port being accessed.
3452 * @param fImm Whether the I/O port was encoded using an immediate operand
3453 * or the implicit DX register.
3454 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3455 * @param cbInstr The instruction length in bytes.
3456 */
3457IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3458 uint8_t cbInstr)
3459{
3460 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3461 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3462
3463 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3464 if (fIntercept)
3465 {
3466 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3467 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3468 VMXVEXITINFO ExitInfo;
3469 RT_ZERO(ExitInfo);
3470 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3471 ExitInfo.cbInstr = cbInstr;
3472 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3473 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3474 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3476 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3477 }
3478
3479 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480}
3481
3482
3483/**
3484 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3485 *
3486 * @returns VBox strict status code.
3487 * @param pVCpu The cross context virtual CPU structure.
3488 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3489 * VMXINSTRID_IO_OUTS).
3490 * @param u16Port The I/O port being accessed.
3491 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3492 * @param fRep Whether the instruction has a REP prefix or not.
3493 * @param ExitInstrInfo The VM-exit instruction info. field.
3494 * @param cbInstr The instruction length in bytes.
3495 */
3496IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3497 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3498{
3499 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3500 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3501 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3502 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3503 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3504
3505 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3506 if (fIntercept)
3507 {
3508 /*
3509 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3510 */
3511 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3512 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3513 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3514 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3515 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3516
3517 uint32_t uDirection;
3518 uint64_t uGuestLinearAddr;
3519 if (uInstrId == VMXINSTRID_IO_INS)
3520 {
3521 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3522 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3523 }
3524 else
3525 {
3526 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3527 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3528 }
3529
3530 /*
3531 * If the segment is unusable, the guest-linear address in undefined.
3532 * We shall clear it for consistency.
3533 *
3534 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3535 */
3536 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3537 uGuestLinearAddr = 0;
3538
3539 VMXVEXITINFO ExitInfo;
3540 RT_ZERO(ExitInfo);
3541 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3542 ExitInfo.cbInstr = cbInstr;
3543 ExitInfo.InstrInfo = ExitInstrInfo;
3544 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3545 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3546 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3547 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3548 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3549 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3550 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3551 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3552 }
3553
3554 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3555}
3556
3557
3558/**
3559 * VMX VM-exit handler for VM-exits due to MWAIT.
3560 *
3561 * @returns VBox strict status code.
3562 * @param pVCpu The cross context virtual CPU structure.
3563 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3564 * @param cbInstr The instruction length in bytes.
3565 */
3566IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3567{
3568 VMXVEXITINFO ExitInfo;
3569 RT_ZERO(ExitInfo);
3570 ExitInfo.uReason = VMX_EXIT_MWAIT;
3571 ExitInfo.cbInstr = cbInstr;
3572 ExitInfo.u64Qual = fMonitorHwArmed;
3573 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3574}
3575
3576
3577/**
3578 * VMX VM-exit handler for VM-exits due to PAUSE.
3579 *
3580 * @returns VBox strict status code.
3581 * @param pVCpu The cross context virtual CPU structure.
3582 * @param cbInstr The instruction length in bytes.
3583 */
3584IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3585{
3586 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3587 Assert(pVmcs);
3588
3589 /*
3590 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3591 * "PAUSE-loop exiting" control.
3592 *
3593 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3594 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3595 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3596 * a VM-exit.
3597 *
3598 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3599 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3600 */
3601 bool fIntercept = false;
3602 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3603 fIntercept = true;
3604 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3605 && pVCpu->iem.s.uCpl == 0)
3606 {
3607 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3608
3609 /*
3610 * A previous-PAUSE-tick value of 0 is used to identify the first time
3611 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3612 * consider this to be the first execution of PAUSE in a loop according
3613 * to the Intel.
3614 *
3615 * All subsequent records for the previous-PAUSE-tick we ensure that it
3616 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3617 */
3618 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3619 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3620 uint64_t const uTick = TMCpuTickGet(pVCpu);
3621 uint32_t const uPleGap = pVmcs->u32PleGap;
3622 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3623 if ( *puPrevPauseTick == 0
3624 || uTick - *puPrevPauseTick > uPleGap)
3625 *puFirstPauseLoopTick = uTick;
3626 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3627 fIntercept = true;
3628
3629 *puPrevPauseTick = uTick | 1;
3630 }
3631
3632 if (fIntercept)
3633 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3634
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636}
3637
3638
3639/**
3640 * VMX VM-exit handler for VM-exits due to task switches.
3641 *
3642 * @returns VBox strict status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 * @param enmTaskSwitch The cause of the task switch.
3645 * @param SelNewTss The selector of the new TSS.
3646 * @param cbInstr The instruction length in bytes.
3647 */
3648IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3649{
3650 /*
3651 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3652 *
3653 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3654 * instruction or delivery of the exception generated by one of these instructions
3655 * lead to a task switch through a task gate in the IDT, we need to provide the
3656 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3657 * leaves the VM-exit instruction length field undefined.
3658 *
3659 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3660 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3661 */
3662 Assert(cbInstr <= 15);
3663
3664 uint8_t uType;
3665 switch (enmTaskSwitch)
3666 {
3667 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3668 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3669 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3670 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3671 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3672 }
3673
3674 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3675 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3676 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3677 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3678 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3679}
3680
3681
3682/**
3683 * VMX VM-exit handler for VM-exits due to task switches.
3684 *
3685 * This is intended for task switches where the caller provides all the relevant
3686 * VM-exit information.
3687 *
3688 * @returns VBox strict status code.
3689 * @param pVCpu The cross context virtual CPU structure.
3690 * @param pExitInfo Pointer to the VM-exit information.
3691 * @param pExitEventInfo Pointer to the VM-exit event information.
3692 */
3693IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3694 PCVMXVEXITEVENTINFO pExitEventInfo)
3695{
3696 Assert(pExitInfo);
3697 Assert(pExitEventInfo);
3698
3699 /* The VM-exit qualification is mandatory for all task-switch VM-exits. */
3700 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3701 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3702
3703 /*
3704 * Figure out if an instruction was the source of the task switch.
3705 *
3706 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3707 * of an event generated by a software interrupt (INT-N), privileged software
3708 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3709 * the instruction length.
3710 */
3711 bool fHasInstrLen;
3712 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3713 {
3714 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3715 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3716 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3717 if (fIdtVectInfoValid)
3718 {
3719 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3720 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3721 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3722
3723 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3724 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3725 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3726 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3727 fHasInstrLen = true;
3728 else
3729 fHasInstrLen = false;
3730 }
3731 else
3732 fHasInstrLen = false;
3733 }
3734 else
3735 {
3736 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3737 fHasInstrLen = true;
3738 }
3739
3740 if (fHasInstrLen)
3741 {
3742 Assert(pExitInfo->cbInstr > 0);
3743 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3744 }
3745 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3746}
3747
3748
3749/**
3750 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3751 *
3752 * @returns VBox strict status code.
3753 * @param pVCpu The cross context virtual CPU structure.
3754 */
3755IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3756{
3757 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3758 Assert(pVmcs);
3759
3760 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3761 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3762 {
3763 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3764 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3765
3766 /*
3767 * Calculate the current VMX-preemption timer value.
3768 * Only if the value has reached zero, we cause the VM-exit.
3769 */
3770 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3771 if (!uPreemptTimer)
3772 {
3773 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3774 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3775 pVmcs->u32PreemptTimer = 0;
3776
3777 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3778 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3779 }
3780 }
3781
3782 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3783}
3784
3785
3786/**
3787 * VMX VM-exit handler for VM-exits due to external interrupts.
3788 *
3789 * @returns VBox strict status code.
3790 * @param pVCpu The cross context virtual CPU structure.
3791 * @param uVector The external interrupt vector (pass 0 if the interrupt
3792 * is still pending since we typically won't know the
3793 * vector).
3794 * @param fIntPending Whether the external interrupt is pending or
3795 * acknowledged in the interrupt controller.
3796 */
3797IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3798{
3799 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3800 Assert(pVmcs);
3801 Assert(fIntPending || uVector == 0);
3802
3803 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3804 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3805 * functions require prior checking of a blanket intercept and which don't.
3806 * It is better for the caller to check a blanket intercept performance wise
3807 * than making a function call. Leaving this as a todo because it is more
3808 * a performance issue. */
3809
3810 /* The VM-exit is subject to "External interrupt exiting" being set. */
3811 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3812 {
3813 if (fIntPending)
3814 {
3815 /*
3816 * If the interrupt is pending and we don't need to acknowledge the
3817 * interrupt on VM-exit, cause the VM-exit immediately.
3818 *
3819 * See Intel spec 25.2 "Other Causes Of VM Exits".
3820 */
3821 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3822 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3823
3824 /*
3825 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3826 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3827 * acknowledged that the interrupt has been consumed.
3828 */
3829 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3830 }
3831
3832 /*
3833 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3834 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3835 * all set, we cause the VM-exit now. We need to record the external interrupt that
3836 * just occurred in the VM-exit interruption information field.
3837 *
3838 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3839 */
3840 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3841 {
3842 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3843 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3844 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3845 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3846 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3847 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3848 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3849 }
3850 }
3851
3852 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3853}
3854
3855
3856/**
3857 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3858 *
3859 * @returns VBox strict status code.
3860 * @param pVCpu The cross context virtual CPU structure.
3861 * @param uVector The SIPI vector.
3862 */
3863IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3864{
3865 iemVmxVmcsSetExitQual(pVCpu, uVector);
3866 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3867}
3868
3869
3870/**
3871 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3872 * an event.
3873 *
3874 * @returns VBox strict status code.
3875 * @param pVCpu The cross context virtual CPU structure.
3876 */
3877IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3878{
3879 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3880 Assert(pVmcs);
3881
3882 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3883 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3884 {
3885 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3886 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3887 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3888 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3889 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3890 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3891 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3892 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3893 iemVmxVmcsSetExitQual(pVCpu, 0);
3894 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3895
3896 /*
3897 * A VM-exit is not considered to occur during event delivery when the original
3898 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3899 * using the exception bitmap).
3900 *
3901 * Therefore, we must clear the original event from the IDT-vectoring fields which
3902 * would've been recorded before causing the VM-exit.
3903 *
3904 * 27.2.3 "Information for VM Exits During Event Delivery"
3905 */
3906 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3907 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3908
3909 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3910 }
3911
3912 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3913}
3914
3915
3916/**
3917 * VMX VM-exit handler for VM-exit due to delivery of an events.
3918 *
3919 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3920 * all the relevant VM-exit information.
3921 *
3922 * @returns VBox strict status code.
3923 * @param pVCpu The cross context virtual CPU structure.
3924 * @param pExitInfo Pointer to the VM-exit information.
3925 * @param pExitEventInfo Pointer to the VM-exit event information.
3926 */
3927IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3928{
3929 Assert(pExitInfo);
3930 Assert(pExitEventInfo);
3931 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3932
3933 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
3934 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3935 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3936 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3937 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3938 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3939 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3940}
3941
3942
3943/**
3944 * VMX VM-exit handler for VM-exits due to delivery of an event.
3945 *
3946 * @returns VBox strict status code.
3947 * @param pVCpu The cross context virtual CPU structure.
3948 * @param uVector The interrupt / exception vector.
3949 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3950 * @param uErrCode The error code associated with the event.
3951 * @param uCr2 The CR2 value in case of a \#PF exception.
3952 * @param cbInstr The instruction length in bytes.
3953 */
3954IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3955 uint8_t cbInstr)
3956{
3957 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3958 Assert(pVmcs);
3959
3960 /*
3961 * If the event is being injected as part of VM-entry, it is -not- subject to event
3962 * intercepts in the nested-guest. However, secondary exceptions that occur during
3963 * injection of any event -are- subject to event interception.
3964 *
3965 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3966 */
3967 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3968 {
3969 /*
3970 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3971 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3972 *
3973 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3974 */
3975 if ( uVector == X86_XCPT_NMI
3976 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3977 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3978 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3979 else
3980 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3981
3982 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3983 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3984 }
3985
3986 /*
3987 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3988 * If not, the caller will continue delivery of the external interrupt as it would
3989 * normally. The interrupt is no longer pending in the interrupt controller at this
3990 * point.
3991 */
3992 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3993 {
3994 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3995 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3996 }
3997
3998 /*
3999 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
4000 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
4001 * interrupts.
4002 */
4003 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4004 bool fIntercept;
4005 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4006 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4007 {
4008 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
4009 }
4010 else
4011 {
4012 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4013 fIntercept = false;
4014 }
4015
4016 /*
4017 * Now that we've determined whether the event causes a VM-exit, we need to construct the
4018 * relevant VM-exit information and cause the VM-exit.
4019 */
4020 if (fIntercept)
4021 {
4022 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4023
4024 /* Construct the rest of the event related information fields and cause the VM-exit. */
4025 uint64_t uExitQual;
4026 if (uVector == X86_XCPT_PF)
4027 {
4028 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4029 uExitQual = uCr2;
4030 }
4031 else if (uVector == X86_XCPT_DB)
4032 {
4033 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4034 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4035 }
4036 else
4037 uExitQual = 0;
4038
4039 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4040 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4041 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4042 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4043 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4044 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4045 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4046 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4047 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4048 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4049 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4050
4051 /*
4052 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
4053 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4054 * length.
4055 */
4056 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4057 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4058 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4059 else
4060 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4061
4062 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4063 }
4064
4065 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4066}
4067
4068
4069/**
4070 * VMX VM-exit handler for VM-exits due to a triple fault.
4071 *
4072 * @returns VBox strict status code.
4073 * @param pVCpu The cross context virtual CPU structure.
4074 */
4075IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4076{
4077 /*
4078 * A VM-exit is not considered to occur during event delivery when the original
4079 * event results in a triple-fault.
4080 *
4081 * Therefore, we must clear the original event from the IDT-vectoring fields which
4082 * would've been recorded before causing the VM-exit.
4083 *
4084 * 27.2.3 "Information for VM Exits During Event Delivery"
4085 */
4086 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4087 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4088
4089 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4090}
4091
4092
4093/**
4094 * VMX VM-exit handler for APIC accesses.
4095 *
4096 * @param pVCpu The cross context virtual CPU structure.
4097 * @param offAccess The offset of the register being accessed.
4098 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4099 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4100 */
4101IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4102{
4103 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4104
4105 VMXAPICACCESS enmAccess;
4106 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4107 if (fInEventDelivery)
4108 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4109 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4110 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4111 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4112 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4113 else
4114 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4115
4116 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4117 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4118 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4119 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4120}
4121
4122
4123/**
4124 * VMX VM-exit handler for APIC accesses.
4125 *
4126 * This is intended for APIC accesses where the caller provides all the
4127 * relevant VM-exit information.
4128 *
4129 * @returns VBox strict status code.
4130 * @param pVCpu The cross context virtual CPU structure.
4131 * @param pExitInfo Pointer to the VM-exit information.
4132 * @param pExitEventInfo Pointer to the VM-exit event information.
4133 */
4134IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
4135 PCVMXVEXITEVENTINFO pExitEventInfo)
4136{
4137 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4138 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4139 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4140 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4141 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
4142 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4143 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4144 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4145}
4146
4147
4148/**
4149 * VMX VM-exit handler for APIC-write VM-exits.
4150 *
4151 * @param pVCpu The cross context virtual CPU structure.
4152 * @param offApic The write to the virtual-APIC page offset that caused this
4153 * VM-exit.
4154 */
4155IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4156{
4157 Assert(offApic < XAPIC_OFF_END + 4);
4158
4159 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4160 offApic &= UINT16_C(0xfff);
4161 iemVmxVmcsSetExitQual(pVCpu, offApic);
4162 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4163}
4164
4165
4166/**
4167 * VMX VM-exit handler for virtualized-EOIs.
4168 *
4169 * @param pVCpu The cross context virtual CPU structure.
4170 */
4171IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4172{
4173 iemVmxVmcsSetExitQual(pVCpu, uVector);
4174 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4175}
4176
4177
4178/**
4179 * Sets virtual-APIC write emulation as pending.
4180 *
4181 * @param pVCpu The cross context virtual CPU structure.
4182 * @param offApic The offset in the virtual-APIC page that was written.
4183 */
4184DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4185{
4186 Assert(offApic < XAPIC_OFF_END + 4);
4187
4188 /*
4189 * Record the currently updated APIC offset, as we need this later for figuring
4190 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4191 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4192 */
4193 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4194
4195 /*
4196 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4197 * virtualization or APIC-write emulation).
4198 */
4199 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4200 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4201}
4202
4203
4204/**
4205 * Clears any pending virtual-APIC write emulation.
4206 *
4207 * @returns The virtual-APIC offset that was written before clearing it.
4208 * @param pVCpu The cross context virtual CPU structure.
4209 */
4210DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4211{
4212 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4213 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4214 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4215 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4216 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4217 return offVirtApicWrite;
4218}
4219
4220
4221/**
4222 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4223 *
4224 * @returns The register from the virtual-APIC page.
4225 * @param pVCpu The cross context virtual CPU structure.
4226 * @param offReg The offset of the register being read.
4227 */
4228IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4229{
4230 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4231 Assert(pVmcs);
4232
4233 uint32_t uReg;
4234 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4235 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4236 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4237 if (RT_FAILURE(rc))
4238 {
4239 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4240 GCPhysVirtApic));
4241 uReg = 0;
4242 }
4243 return uReg;
4244}
4245
4246
4247/**
4248 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4249 *
4250 * @returns The register from the virtual-APIC page.
4251 * @param pVCpu The cross context virtual CPU structure.
4252 * @param offReg The offset of the register being read.
4253 */
4254IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4255{
4256 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4257 Assert(pVmcs);
4258
4259 uint64_t uReg;
4260 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4261 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4262 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4263 if (RT_FAILURE(rc))
4264 {
4265 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4266 GCPhysVirtApic));
4267 uReg = 0;
4268 }
4269 return uReg;
4270}
4271
4272
4273/**
4274 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4275 *
4276 * @param pVCpu The cross context virtual CPU structure.
4277 * @param offReg The offset of the register being written.
4278 * @param uReg The register value to write.
4279 */
4280IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4281{
4282 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4283 Assert(pVmcs);
4284 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4285 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4286 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4287 if (RT_FAILURE(rc))
4288 {
4289 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4290 GCPhysVirtApic));
4291 }
4292}
4293
4294
4295/**
4296 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4297 *
4298 * @param pVCpu The cross context virtual CPU structure.
4299 * @param offReg The offset of the register being written.
4300 * @param uReg The register value to write.
4301 */
4302IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4303{
4304 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4305 Assert(pVmcs);
4306 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4307 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4308 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4309 if (RT_FAILURE(rc))
4310 {
4311 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4312 GCPhysVirtApic));
4313 }
4314}
4315
4316
4317/**
4318 * Sets the vector in a virtual-APIC 256-bit sparse register.
4319 *
4320 * @param pVCpu The cross context virtual CPU structure.
4321 * @param offReg The offset of the 256-bit spare register.
4322 * @param uVector The vector to set.
4323 *
4324 * @remarks This is based on our APIC device code.
4325 */
4326IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4327{
4328 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4329 Assert(pVmcs);
4330 uint32_t uReg;
4331 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4332 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4333 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4334 if (RT_SUCCESS(rc))
4335 {
4336 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4337 uReg |= RT_BIT(idxVectorBit);
4338 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4339 if (RT_FAILURE(rc))
4340 {
4341 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4342 uVector, offReg, GCPhysVirtApic));
4343 }
4344 }
4345 else
4346 {
4347 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4348 uVector, offReg, GCPhysVirtApic));
4349 }
4350}
4351
4352
4353/**
4354 * Clears the vector in a virtual-APIC 256-bit sparse register.
4355 *
4356 * @param pVCpu The cross context virtual CPU structure.
4357 * @param offReg The offset of the 256-bit spare register.
4358 * @param uVector The vector to clear.
4359 *
4360 * @remarks This is based on our APIC device code.
4361 */
4362IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4363{
4364 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4365 Assert(pVmcs);
4366 uint32_t uReg;
4367 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4368 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4369 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4370 if (RT_SUCCESS(rc))
4371 {
4372 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4373 uReg &= ~RT_BIT(idxVectorBit);
4374 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4375 if (RT_FAILURE(rc))
4376 {
4377 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4378 uVector, offReg, GCPhysVirtApic));
4379 }
4380 }
4381 else
4382 {
4383 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4384 uVector, offReg, GCPhysVirtApic));
4385 }
4386}
4387
4388
4389/**
4390 * Checks if a memory access to the APIC-access page must causes an APIC-access
4391 * VM-exit.
4392 *
4393 * @param pVCpu The cross context virtual CPU structure.
4394 * @param offAccess The offset of the register being accessed.
4395 * @param cbAccess The size of the access in bytes.
4396 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4397 * IEM_ACCESS_TYPE_WRITE).
4398 *
4399 * @remarks This must not be used for MSR-based APIC-access page accesses!
4400 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4401 */
4402IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4403{
4404 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4405 Assert(pVmcs);
4406 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4407
4408 /*
4409 * We must cause a VM-exit if any of the following are true:
4410 * - TPR shadowing isn't active.
4411 * - The access size exceeds 32-bits.
4412 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4413 *
4414 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4415 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4416 */
4417 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4418 || cbAccess > sizeof(uint32_t)
4419 || ((offAccess + cbAccess - 1) & 0xc)
4420 || offAccess >= XAPIC_OFF_END + 4)
4421 return true;
4422
4423 /*
4424 * If the access is part of an operation where we have already
4425 * virtualized a virtual-APIC write, we must cause a VM-exit.
4426 */
4427 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4428 return true;
4429
4430 /*
4431 * Check write accesses to the APIC-access page that cause VM-exits.
4432 */
4433 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4434 {
4435 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4436 {
4437 /*
4438 * With APIC-register virtualization, a write access to any of the
4439 * following registers are virtualized. Accessing any other register
4440 * causes a VM-exit.
4441 */
4442 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4443 switch (offAlignedAccess)
4444 {
4445 case XAPIC_OFF_ID:
4446 case XAPIC_OFF_TPR:
4447 case XAPIC_OFF_EOI:
4448 case XAPIC_OFF_LDR:
4449 case XAPIC_OFF_DFR:
4450 case XAPIC_OFF_SVR:
4451 case XAPIC_OFF_ESR:
4452 case XAPIC_OFF_ICR_LO:
4453 case XAPIC_OFF_ICR_HI:
4454 case XAPIC_OFF_LVT_TIMER:
4455 case XAPIC_OFF_LVT_THERMAL:
4456 case XAPIC_OFF_LVT_PERF:
4457 case XAPIC_OFF_LVT_LINT0:
4458 case XAPIC_OFF_LVT_LINT1:
4459 case XAPIC_OFF_LVT_ERROR:
4460 case XAPIC_OFF_TIMER_ICR:
4461 case XAPIC_OFF_TIMER_DCR:
4462 break;
4463 default:
4464 return true;
4465 }
4466 }
4467 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4468 {
4469 /*
4470 * With virtual-interrupt delivery, a write access to any of the
4471 * following registers are virtualized. Accessing any other register
4472 * causes a VM-exit.
4473 *
4474 * Note! The specification does not allow writing to offsets in-between
4475 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4476 */
4477 switch (offAccess)
4478 {
4479 case XAPIC_OFF_TPR:
4480 case XAPIC_OFF_EOI:
4481 case XAPIC_OFF_ICR_LO:
4482 break;
4483 default:
4484 return true;
4485 }
4486 }
4487 else
4488 {
4489 /*
4490 * Without APIC-register virtualization or virtual-interrupt delivery,
4491 * only TPR accesses are virtualized.
4492 */
4493 if (offAccess == XAPIC_OFF_TPR)
4494 { /* likely */ }
4495 else
4496 return true;
4497 }
4498 }
4499 else
4500 {
4501 /*
4502 * Check read accesses to the APIC-access page that cause VM-exits.
4503 */
4504 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4505 {
4506 /*
4507 * With APIC-register virtualization, a read access to any of the
4508 * following registers are virtualized. Accessing any other register
4509 * causes a VM-exit.
4510 */
4511 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4512 switch (offAlignedAccess)
4513 {
4514 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4515 case XAPIC_OFF_ID:
4516 case XAPIC_OFF_VERSION:
4517 case XAPIC_OFF_TPR:
4518 case XAPIC_OFF_EOI:
4519 case XAPIC_OFF_LDR:
4520 case XAPIC_OFF_DFR:
4521 case XAPIC_OFF_SVR:
4522 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4523 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4524 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4525 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4526 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4527 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4528 case XAPIC_OFF_ESR:
4529 case XAPIC_OFF_ICR_LO:
4530 case XAPIC_OFF_ICR_HI:
4531 case XAPIC_OFF_LVT_TIMER:
4532 case XAPIC_OFF_LVT_THERMAL:
4533 case XAPIC_OFF_LVT_PERF:
4534 case XAPIC_OFF_LVT_LINT0:
4535 case XAPIC_OFF_LVT_LINT1:
4536 case XAPIC_OFF_LVT_ERROR:
4537 case XAPIC_OFF_TIMER_ICR:
4538 case XAPIC_OFF_TIMER_DCR:
4539 break;
4540 default:
4541 return true;
4542 }
4543 }
4544 else
4545 {
4546 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4547 if (offAccess == XAPIC_OFF_TPR)
4548 { /* likely */ }
4549 else
4550 return true;
4551 }
4552 }
4553
4554 /* The APIC access is virtualized, does not cause a VM-exit. */
4555 return false;
4556}
4557
4558
4559/**
4560 * Virtualizes a memory-based APIC access where the address is not used to access
4561 * memory.
4562 *
4563 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4564 * page-faults but do not use the address to access memory.
4565 *
4566 * @param pVCpu The cross context virtual CPU structure.
4567 * @param pGCPhysAccess Pointer to the guest-physical address used.
4568 */
4569IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4570{
4571 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4572 Assert(pVmcs);
4573 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4574 Assert(pGCPhysAccess);
4575
4576 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4577 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4578 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4579
4580 if (GCPhysAccess == GCPhysApic)
4581 {
4582 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4583 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4584 uint16_t const cbAccess = 1;
4585 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4586 if (fIntercept)
4587 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4588
4589 *pGCPhysAccess = GCPhysApic | offAccess;
4590 return VINF_VMX_MODIFIES_BEHAVIOR;
4591 }
4592
4593 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4594}
4595
4596
4597/**
4598 * Virtualizes a memory-based APIC access.
4599 *
4600 * @returns VBox strict status code.
4601 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4602 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4603 *
4604 * @param pVCpu The cross context virtual CPU structure.
4605 * @param offAccess The offset of the register being accessed (within the
4606 * APIC-access page).
4607 * @param cbAccess The size of the access in bytes.
4608 * @param pvData Pointer to the data being written or where to store the data
4609 * being read.
4610 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4611 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4612 */
4613IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4614 uint32_t fAccess)
4615{
4616 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4617 Assert(pVmcs);
4618 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4619 Assert(pvData);
4620 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4621 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4622 || (fAccess & IEM_ACCESS_INSTRUCTION));
4623
4624 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4625 if (fIntercept)
4626 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4627
4628 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4629 {
4630 /*
4631 * A write access to the APIC-access page that is virtualized (rather than
4632 * causing a VM-exit) writes data to the virtual-APIC page.
4633 */
4634 uint32_t const u32Data = *(uint32_t *)pvData;
4635 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4636
4637 /*
4638 * Record the currently updated APIC offset, as we need this later for figuring
4639 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4640 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4641 *
4642 * After completion of the current operation, we need to perform TPR virtualization,
4643 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4644 *
4645 * The current operation may be a REP-prefixed string instruction, execution of any
4646 * other instruction, or delivery of an event through the IDT.
4647 *
4648 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4649 * performed now but later after completion of the current operation.
4650 *
4651 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4652 */
4653 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4654 }
4655 else
4656 {
4657 /*
4658 * A read access from the APIC-access page that is virtualized (rather than
4659 * causing a VM-exit) returns data from the virtual-APIC page.
4660 *
4661 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4662 */
4663 Assert(cbAccess <= 4);
4664 Assert(offAccess < XAPIC_OFF_END + 4);
4665 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4666
4667 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4668 u32Data &= s_auAccessSizeMasks[cbAccess];
4669 *(uint32_t *)pvData = u32Data;
4670 }
4671
4672 return VINF_VMX_MODIFIES_BEHAVIOR;
4673}
4674
4675
4676/**
4677 * Virtualizes an MSR-based APIC read access.
4678 *
4679 * @returns VBox strict status code.
4680 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4681 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4682 * handled by the x2APIC device.
4683 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4684 * not within the range of valid MSRs, caller must raise \#GP(0).
4685 * @param pVCpu The cross context virtual CPU structure.
4686 * @param idMsr The x2APIC MSR being read.
4687 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4688 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4689 */
4690IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4691{
4692 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4693 Assert(pVmcs);
4694 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4695 Assert(pu64Value);
4696
4697 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4698 {
4699 /*
4700 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4701 * what the end of the valid x2APIC MSR range is. Hence the use of different
4702 * macros here.
4703 *
4704 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4705 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4706 */
4707 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4708 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4709 {
4710 uint16_t const offReg = (idMsr & 0xff) << 4;
4711 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4712 *pu64Value = u64Value;
4713 return VINF_VMX_MODIFIES_BEHAVIOR;
4714 }
4715 return VERR_OUT_OF_RANGE;
4716 }
4717
4718 if (idMsr == MSR_IA32_X2APIC_TPR)
4719 {
4720 uint16_t const offReg = (idMsr & 0xff) << 4;
4721 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4722 *pu64Value = u64Value;
4723 return VINF_VMX_MODIFIES_BEHAVIOR;
4724 }
4725
4726 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4727}
4728
4729
4730/**
4731 * Virtualizes an MSR-based APIC write access.
4732 *
4733 * @returns VBox strict status code.
4734 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4735 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4736 * not within the range of valid MSRs, caller must raise \#GP(0).
4737 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4738 *
4739 * @param pVCpu The cross context virtual CPU structure.
4740 * @param idMsr The x2APIC MSR being written.
4741 * @param u64Value The value of the x2APIC MSR being written.
4742 */
4743IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4744{
4745 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4746 Assert(pVmcs);
4747
4748 /*
4749 * Check if the access is to be virtualized.
4750 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4751 */
4752 if ( idMsr == MSR_IA32_X2APIC_TPR
4753 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4754 && ( idMsr == MSR_IA32_X2APIC_EOI
4755 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4756 {
4757 /* Validate the MSR write depending on the register. */
4758 switch (idMsr)
4759 {
4760 case MSR_IA32_X2APIC_TPR:
4761 case MSR_IA32_X2APIC_SELF_IPI:
4762 {
4763 if (u64Value & UINT64_C(0xffffffffffffff00))
4764 return VERR_OUT_OF_RANGE;
4765 break;
4766 }
4767 case MSR_IA32_X2APIC_EOI:
4768 {
4769 if (u64Value != 0)
4770 return VERR_OUT_OF_RANGE;
4771 break;
4772 }
4773 }
4774
4775 /* Write the MSR to the virtual-APIC page. */
4776 uint16_t const offReg = (idMsr & 0xff) << 4;
4777 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4778
4779 /*
4780 * Record the currently updated APIC offset, as we need this later for figuring
4781 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4782 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4783 */
4784 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4785
4786 return VINF_VMX_MODIFIES_BEHAVIOR;
4787 }
4788
4789 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4790}
4791
4792
4793/**
4794 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4795 *
4796 * @returns VBox status code.
4797 * @retval VINF_SUCCESS when the highest set bit is found.
4798 * @retval VERR_NOT_FOUND when no bit is set.
4799 *
4800 * @param pVCpu The cross context virtual CPU structure.
4801 * @param offReg The offset of the APIC 256-bit sparse register.
4802 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4803 * set in the register. Only valid when VINF_SUCCESS is
4804 * returned.
4805 *
4806 * @remarks The format of the 256-bit sparse register here mirrors that found in
4807 * real APIC hardware.
4808 */
4809static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4810{
4811 Assert(offReg < XAPIC_OFF_END + 4);
4812 Assert(pidxHighestBit);
4813 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4814
4815 /*
4816 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4817 * However, in each fragment only the first 4 bytes are used.
4818 */
4819 uint8_t const cFrags = 8;
4820 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4821 {
4822 uint16_t const offFrag = iFrag * 16;
4823 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4824 if (!u32Frag)
4825 continue;
4826
4827 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4828 Assert(idxHighestBit > 0);
4829 --idxHighestBit;
4830 Assert(idxHighestBit <= UINT8_MAX);
4831 *pidxHighestBit = idxHighestBit;
4832 return VINF_SUCCESS;
4833 }
4834 return VERR_NOT_FOUND;
4835}
4836
4837
4838/**
4839 * Evaluates pending virtual interrupts.
4840 *
4841 * @param pVCpu The cross context virtual CPU structure.
4842 */
4843IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4844{
4845 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4846 Assert(pVmcs);
4847 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4848
4849 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4850 {
4851 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4852 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4853
4854 if ((uRvi >> 4) > (uPpr >> 4))
4855 {
4856 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4857 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4858 }
4859 else
4860 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4861 }
4862}
4863
4864
4865/**
4866 * Performs PPR virtualization.
4867 *
4868 * @returns VBox strict status code.
4869 * @param pVCpu The cross context virtual CPU structure.
4870 */
4871IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4872{
4873 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4874 Assert(pVmcs);
4875 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4876 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4877
4878 /*
4879 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4880 * or EOI-virtualization.
4881 *
4882 * See Intel spec. 29.1.3 "PPR Virtualization".
4883 */
4884 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4885 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4886
4887 uint32_t uPpr;
4888 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4889 uPpr = uTpr & 0xff;
4890 else
4891 uPpr = uSvi & 0xf0;
4892
4893 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4894 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4895}
4896
4897
4898/**
4899 * Performs VMX TPR virtualization.
4900 *
4901 * @returns VBox strict status code.
4902 * @param pVCpu The cross context virtual CPU structure.
4903 */
4904IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4905{
4906 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4907 Assert(pVmcs);
4908 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4909
4910 /*
4911 * We should have already performed the virtual-APIC write to the TPR offset
4912 * in the virtual-APIC page. We now perform TPR virtualization.
4913 *
4914 * See Intel spec. 29.1.2 "TPR Virtualization".
4915 */
4916 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4917 {
4918 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4919 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4920
4921 /*
4922 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4923 * See Intel spec. 29.1.2 "TPR Virtualization".
4924 */
4925 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4926 {
4927 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4928 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4929 }
4930 }
4931 else
4932 {
4933 iemVmxPprVirtualization(pVCpu);
4934 iemVmxEvalPendingVirtIntrs(pVCpu);
4935 }
4936
4937 return VINF_SUCCESS;
4938}
4939
4940
4941/**
4942 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4943 * not.
4944 *
4945 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4946 * @param pVCpu The cross context virtual CPU structure.
4947 * @param uVector The interrupt that was acknowledged using an EOI.
4948 */
4949IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4950{
4951 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4952 Assert(pVmcs);
4953 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4954
4955 if (uVector < 64)
4956 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4957 if (uVector < 128)
4958 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4959 if (uVector < 192)
4960 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4961 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4962}
4963
4964
4965/**
4966 * Performs EOI virtualization.
4967 *
4968 * @returns VBox strict status code.
4969 * @param pVCpu The cross context virtual CPU structure.
4970 */
4971IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4972{
4973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4974 Assert(pVmcs);
4975 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4976
4977 /*
4978 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4979 * and get the next guest-interrupt that's in-service (if any).
4980 *
4981 * See Intel spec. 29.1.4 "EOI Virtualization".
4982 */
4983 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4984 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4985 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4986
4987 uint8_t uVector = uSvi;
4988 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4989
4990 uVector = 0;
4991 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4992
4993 if (uVector)
4994 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4995 else
4996 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4997
4998 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4999 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5000
5001 iemVmxPprVirtualization(pVCpu);
5002 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5003 return iemVmxVmexitVirtEoi(pVCpu, uVector);
5004 iemVmxEvalPendingVirtIntrs(pVCpu);
5005 return VINF_SUCCESS;
5006}
5007
5008
5009/**
5010 * Performs self-IPI virtualization.
5011 *
5012 * @returns VBox strict status code.
5013 * @param pVCpu The cross context virtual CPU structure.
5014 */
5015IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
5016{
5017 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5018 Assert(pVmcs);
5019 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5020
5021 /*
5022 * We should have already performed the virtual-APIC write to the self-IPI offset
5023 * in the virtual-APIC page. We now perform self-IPI virtualization.
5024 *
5025 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5026 */
5027 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5028 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5029 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5030 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5031 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5032 if (uVector > uRvi)
5033 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5034 iemVmxEvalPendingVirtIntrs(pVCpu);
5035 return VINF_SUCCESS;
5036}
5037
5038
5039/**
5040 * Performs VMX APIC-write emulation.
5041 *
5042 * @returns VBox strict status code.
5043 * @param pVCpu The cross context virtual CPU structure.
5044 */
5045IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5046{
5047 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5048 Assert(pVmcs);
5049
5050 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5051 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5052
5053 /*
5054 * Perform APIC-write emulation based on the virtual-APIC register written.
5055 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5056 */
5057 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5058 VBOXSTRICTRC rcStrict;
5059 switch (offApicWrite)
5060 {
5061 case XAPIC_OFF_TPR:
5062 {
5063 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5064 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5065 uTpr &= UINT32_C(0x000000ff);
5066 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5067 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5068 rcStrict = iemVmxTprVirtualization(pVCpu);
5069 break;
5070 }
5071
5072 case XAPIC_OFF_EOI:
5073 {
5074 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5075 {
5076 /* Clear VEOI and perform EOI virtualization. */
5077 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5078 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5079 rcStrict = iemVmxEoiVirtualization(pVCpu);
5080 }
5081 else
5082 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5083 break;
5084 }
5085
5086 case XAPIC_OFF_ICR_LO:
5087 {
5088 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5089 {
5090 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5091 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5092 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5093 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5094 if ( !(uIcrLo & fIcrLoMb0)
5095 && (uIcrLo & fIcrLoMb1))
5096 {
5097 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5098 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5099 }
5100 else
5101 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5102 }
5103 else
5104 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5105 break;
5106 }
5107
5108 case XAPIC_OFF_ICR_HI:
5109 {
5110 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5111 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5112 uIcrHi &= UINT32_C(0xff000000);
5113 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5114 rcStrict = VINF_SUCCESS;
5115 break;
5116 }
5117
5118 default:
5119 {
5120 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5121 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5122 break;
5123 }
5124 }
5125
5126 return rcStrict;
5127}
5128
5129
5130/**
5131 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5132 *
5133 * @param pVCpu The cross context virtual CPU structure.
5134 * @param pszInstr The VMX instruction name (for logging purposes).
5135 */
5136IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5137{
5138 /*
5139 * Guest Control Registers, Debug Registers, and MSRs.
5140 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5141 */
5142 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5143 const char *const pszFailure = "VM-exit";
5144 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5145
5146 /* CR0 reserved bits. */
5147 {
5148 /* CR0 MB1 bits. */
5149 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5150 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5151 if (fUnrestrictedGuest)
5152 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5153 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5154 { /* likely */ }
5155 else
5156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5157
5158 /* CR0 MBZ bits. */
5159 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5160 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5161 { /* likely */ }
5162 else
5163 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5164
5165 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5166 if ( !fUnrestrictedGuest
5167 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5168 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5170 }
5171
5172 /* CR4 reserved bits. */
5173 {
5174 /* CR4 MB1 bits. */
5175 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5176 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5177 { /* likely */ }
5178 else
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5180
5181 /* CR4 MBZ bits. */
5182 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5183 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5184 { /* likely */ }
5185 else
5186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5187 }
5188
5189 /* DEBUGCTL MSR. */
5190 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5191 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5192 { /* likely */ }
5193 else
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5195
5196 /* 64-bit CPU checks. */
5197 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5198 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5199 {
5200 if (fGstInLongMode)
5201 {
5202 /* PAE must be set. */
5203 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5204 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5208 }
5209 else
5210 {
5211 /* PCIDE should not be set. */
5212 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5216 }
5217
5218 /* CR3. */
5219 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5220 { /* likely */ }
5221 else
5222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5223
5224 /* DR7. */
5225 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5226 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5230
5231 /* SYSENTER ESP and SYSENTER EIP. */
5232 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5233 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5237 }
5238
5239 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5240 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5241
5242 /* PAT MSR. */
5243 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5244 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5245 { /* likely */ }
5246 else
5247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5248
5249 /* EFER MSR. */
5250 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5251 {
5252 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5253 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5254 { /* likely */ }
5255 else
5256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5257
5258 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5259 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5260 if ( fGstLma == fGstInLongMode
5261 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5262 || fGstLma == fGstLme))
5263 { /* likely */ }
5264 else
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5266 }
5267
5268 /* We don't support IA32_BNDCFGS MSR yet. */
5269 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5270
5271 NOREF(pszInstr);
5272 NOREF(pszFailure);
5273 return VINF_SUCCESS;
5274}
5275
5276
5277/**
5278 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5279 *
5280 * @param pVCpu The cross context virtual CPU structure.
5281 * @param pszInstr The VMX instruction name (for logging purposes).
5282 */
5283IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5284{
5285 /*
5286 * Segment registers.
5287 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5288 */
5289 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5290 const char *const pszFailure = "VM-exit";
5291 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5292 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5293 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5294
5295 /* Selectors. */
5296 if ( !fGstInV86Mode
5297 && !fUnrestrictedGuest
5298 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5300
5301 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5302 {
5303 CPUMSELREG SelReg;
5304 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5305 if (RT_LIKELY(rc == VINF_SUCCESS))
5306 { /* likely */ }
5307 else
5308 return rc;
5309
5310 /*
5311 * Virtual-8086 mode checks.
5312 */
5313 if (fGstInV86Mode)
5314 {
5315 /* Base address. */
5316 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5317 { /* likely */ }
5318 else
5319 {
5320 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5321 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5322 }
5323
5324 /* Limit. */
5325 if (SelReg.u32Limit == 0xffff)
5326 { /* likely */ }
5327 else
5328 {
5329 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5330 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5331 }
5332
5333 /* Attribute. */
5334 if (SelReg.Attr.u == 0xf3)
5335 { /* likely */ }
5336 else
5337 {
5338 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5339 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5340 }
5341
5342 /* We're done; move to checking the next segment. */
5343 continue;
5344 }
5345
5346 /* Checks done by 64-bit CPUs. */
5347 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5348 {
5349 /* Base address. */
5350 if ( iSegReg == X86_SREG_FS
5351 || iSegReg == X86_SREG_GS)
5352 {
5353 if (X86_IS_CANONICAL(SelReg.u64Base))
5354 { /* likely */ }
5355 else
5356 {
5357 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5359 }
5360 }
5361 else if (iSegReg == X86_SREG_CS)
5362 {
5363 if (!RT_HI_U32(SelReg.u64Base))
5364 { /* likely */ }
5365 else
5366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5367 }
5368 else
5369 {
5370 if ( SelReg.Attr.n.u1Unusable
5371 || !RT_HI_U32(SelReg.u64Base))
5372 { /* likely */ }
5373 else
5374 {
5375 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5377 }
5378 }
5379 }
5380
5381 /*
5382 * Checks outside Virtual-8086 mode.
5383 */
5384 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5385 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5386 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5387 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5388 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5389 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5390 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5391 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5392
5393 /* Code or usable segment. */
5394 if ( iSegReg == X86_SREG_CS
5395 || fUsable)
5396 {
5397 /* Reserved bits (bits 31:17 and bits 11:8). */
5398 if (!(SelReg.Attr.u & 0xfffe0f00))
5399 { /* likely */ }
5400 else
5401 {
5402 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5404 }
5405
5406 /* Descriptor type. */
5407 if (fCodeDataSeg)
5408 { /* likely */ }
5409 else
5410 {
5411 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5412 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5413 }
5414
5415 /* Present. */
5416 if (fPresent)
5417 { /* likely */ }
5418 else
5419 {
5420 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5422 }
5423
5424 /* Granularity. */
5425 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5426 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5427 { /* likely */ }
5428 else
5429 {
5430 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5432 }
5433 }
5434
5435 if (iSegReg == X86_SREG_CS)
5436 {
5437 /* Segment Type and DPL. */
5438 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5439 && fUnrestrictedGuest)
5440 {
5441 if (uDpl == 0)
5442 { /* likely */ }
5443 else
5444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5445 }
5446 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5447 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5448 {
5449 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5450 if (uDpl == AttrSs.n.u2Dpl)
5451 { /* likely */ }
5452 else
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5454 }
5455 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5456 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5457 {
5458 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5459 if (uDpl <= AttrSs.n.u2Dpl)
5460 { /* likely */ }
5461 else
5462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5463 }
5464 else
5465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5466
5467 /* Def/Big. */
5468 if ( fGstInLongMode
5469 && fSegLong)
5470 {
5471 if (uDefBig == 0)
5472 { /* likely */ }
5473 else
5474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5475 }
5476 }
5477 else if (iSegReg == X86_SREG_SS)
5478 {
5479 /* Segment Type. */
5480 if ( !fUsable
5481 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5482 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5486
5487 /* DPL. */
5488 if (!fUnrestrictedGuest)
5489 {
5490 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5491 { /* likely */ }
5492 else
5493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5494 }
5495 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5496 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5497 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5498 {
5499 if (uDpl == 0)
5500 { /* likely */ }
5501 else
5502 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5503 }
5504 }
5505 else
5506 {
5507 /* DS, ES, FS, GS. */
5508 if (fUsable)
5509 {
5510 /* Segment type. */
5511 if (uSegType & X86_SEL_TYPE_ACCESSED)
5512 { /* likely */ }
5513 else
5514 {
5515 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5517 }
5518
5519 if ( !(uSegType & X86_SEL_TYPE_CODE)
5520 || (uSegType & X86_SEL_TYPE_READ))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5524
5525 /* DPL. */
5526 if ( !fUnrestrictedGuest
5527 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5528 {
5529 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5530 { /* likely */ }
5531 else
5532 {
5533 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5534 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5535 }
5536 }
5537 }
5538 }
5539 }
5540
5541 /*
5542 * LDTR.
5543 */
5544 {
5545 CPUMSELREG Ldtr;
5546 Ldtr.Sel = pVmcs->GuestLdtr;
5547 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5548 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5549 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5550
5551 if (!Ldtr.Attr.n.u1Unusable)
5552 {
5553 /* Selector. */
5554 if (!(Ldtr.Sel & X86_SEL_LDT))
5555 { /* likely */ }
5556 else
5557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5558
5559 /* Base. */
5560 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5561 {
5562 if (X86_IS_CANONICAL(Ldtr.u64Base))
5563 { /* likely */ }
5564 else
5565 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5566 }
5567
5568 /* Attributes. */
5569 /* Reserved bits (bits 31:17 and bits 11:8). */
5570 if (!(Ldtr.Attr.u & 0xfffe0f00))
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5574
5575 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5579
5580 if (!Ldtr.Attr.n.u1DescType)
5581 { /* likely */ }
5582 else
5583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5584
5585 if (Ldtr.Attr.n.u1Present)
5586 { /* likely */ }
5587 else
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5589
5590 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5591 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5592 { /* likely */ }
5593 else
5594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5595 }
5596 }
5597
5598 /*
5599 * TR.
5600 */
5601 {
5602 CPUMSELREG Tr;
5603 Tr.Sel = pVmcs->GuestTr;
5604 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5605 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5606 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5607
5608 /* Selector. */
5609 if (!(Tr.Sel & X86_SEL_LDT))
5610 { /* likely */ }
5611 else
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5613
5614 /* Base. */
5615 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5616 {
5617 if (X86_IS_CANONICAL(Tr.u64Base))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5621 }
5622
5623 /* Attributes. */
5624 /* Reserved bits (bits 31:17 and bits 11:8). */
5625 if (!(Tr.Attr.u & 0xfffe0f00))
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5629
5630 if (!Tr.Attr.n.u1Unusable)
5631 { /* likely */ }
5632 else
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5634
5635 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5636 || ( !fGstInLongMode
5637 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5638 { /* likely */ }
5639 else
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5641
5642 if (!Tr.Attr.n.u1DescType)
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5646
5647 if (Tr.Attr.n.u1Present)
5648 { /* likely */ }
5649 else
5650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5651
5652 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5653 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5654 { /* likely */ }
5655 else
5656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5657 }
5658
5659 NOREF(pszInstr);
5660 NOREF(pszFailure);
5661 return VINF_SUCCESS;
5662}
5663
5664
5665/**
5666 * Checks guest GDTR and IDTR as part of VM-entry.
5667 *
5668 * @param pVCpu The cross context virtual CPU structure.
5669 * @param pszInstr The VMX instruction name (for logging purposes).
5670 */
5671IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5672{
5673 /*
5674 * GDTR and IDTR.
5675 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5676 */
5677 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5678 const char *const pszFailure = "VM-exit";
5679
5680 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5681 {
5682 /* Base. */
5683 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5684 { /* likely */ }
5685 else
5686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5687
5688 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5689 { /* likely */ }
5690 else
5691 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5692 }
5693
5694 /* Limit. */
5695 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5696 { /* likely */ }
5697 else
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5699
5700 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5701 { /* likely */ }
5702 else
5703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5704
5705 NOREF(pszInstr);
5706 NOREF(pszFailure);
5707 return VINF_SUCCESS;
5708}
5709
5710
5711/**
5712 * Checks guest RIP and RFLAGS as part of VM-entry.
5713 *
5714 * @param pVCpu The cross context virtual CPU structure.
5715 * @param pszInstr The VMX instruction name (for logging purposes).
5716 */
5717IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5718{
5719 /*
5720 * RIP and RFLAGS.
5721 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5722 */
5723 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5724 const char *const pszFailure = "VM-exit";
5725 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5726
5727 /* RIP. */
5728 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5729 {
5730 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5731 if ( !fGstInLongMode
5732 || !AttrCs.n.u1Long)
5733 {
5734 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5735 { /* likely */ }
5736 else
5737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5738 }
5739
5740 if ( fGstInLongMode
5741 && AttrCs.n.u1Long)
5742 {
5743 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5744 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5745 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5749 }
5750 }
5751
5752 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5753 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5754 : pVmcs->u64GuestRFlags.s.Lo;
5755 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5756 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5757 { /* likely */ }
5758 else
5759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5760
5761 if ( fGstInLongMode
5762 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5763 {
5764 if (!(uGuestRFlags & X86_EFL_VM))
5765 { /* likely */ }
5766 else
5767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5768 }
5769
5770 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5771 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5772 {
5773 if (uGuestRFlags & X86_EFL_IF)
5774 { /* likely */ }
5775 else
5776 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5777 }
5778
5779 NOREF(pszInstr);
5780 NOREF(pszFailure);
5781 return VINF_SUCCESS;
5782}
5783
5784
5785/**
5786 * Checks guest non-register state as part of VM-entry.
5787 *
5788 * @param pVCpu The cross context virtual CPU structure.
5789 * @param pszInstr The VMX instruction name (for logging purposes).
5790 */
5791IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5792{
5793 /*
5794 * Guest non-register state.
5795 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5796 */
5797 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5798 const char *const pszFailure = "VM-exit";
5799
5800 /*
5801 * Activity state.
5802 */
5803 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5804 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5805 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5806 { /* likely */ }
5807 else
5808 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5809
5810 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5811 if ( !AttrSs.n.u2Dpl
5812 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5813 { /* likely */ }
5814 else
5815 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5816
5817 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5818 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5819 {
5820 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5821 { /* likely */ }
5822 else
5823 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5824 }
5825
5826 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5827 {
5828 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5829 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5830 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5831 switch (pVmcs->u32GuestActivityState)
5832 {
5833 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5834 {
5835 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5836 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5837 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5838 && ( uVector == X86_XCPT_DB
5839 || uVector == X86_XCPT_MC))
5840 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5841 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5845 break;
5846 }
5847
5848 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5849 {
5850 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5851 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5852 && uVector == X86_XCPT_MC))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5856 break;
5857 }
5858
5859 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5860 default:
5861 break;
5862 }
5863 }
5864
5865 /*
5866 * Interruptibility state.
5867 */
5868 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5872
5873 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5874 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5875 { /* likely */ }
5876 else
5877 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5878
5879 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5880 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5881 { /* likely */ }
5882 else
5883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5884
5885 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5886 {
5887 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5888 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5889 {
5890 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5891 { /* likely */ }
5892 else
5893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5894 }
5895 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5896 {
5897 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5898 { /* likely */ }
5899 else
5900 {
5901 /*
5902 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5903 * We update the VM-exit qualification only when blocking-by-STI is set
5904 * without blocking-by-MovSS being set. Although in practise it does not
5905 * make much difference since the order of checks are implementation defined.
5906 */
5907 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5908 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5909 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5910 }
5911
5912 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5913 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5914 { /* likely */ }
5915 else
5916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5917 }
5918 }
5919
5920 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5921 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5922 { /* likely */ }
5923 else
5924 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5925
5926 /* We don't support SGX yet. So enclave-interruption must not be set. */
5927 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5931
5932 /*
5933 * Pending debug exceptions.
5934 */
5935 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5936 ? pVmcs->u64GuestPendingDbgXcpt.u
5937 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5938 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5942
5943 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5944 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5945 {
5946 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5947 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5948 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5950
5951 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5952 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5953 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5954 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5955 }
5956
5957 /* We don't support RTM (Real-time Transactional Memory) yet. */
5958 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5959 { /* likely */ }
5960 else
5961 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5962
5963 /*
5964 * VMCS link pointer.
5965 */
5966 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5967 {
5968 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5969 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5970 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5971 { /* likely */ }
5972 else
5973 {
5974 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5976 }
5977
5978 /* Validate the address. */
5979 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5980 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5981 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5982 { /* likely */ }
5983 else
5984 {
5985 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5987 }
5988
5989 /* Read the VMCS-link pointer from guest memory. */
5990 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5991 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5992 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5993 if (RT_SUCCESS(rc))
5994 { /* likely */ }
5995 else
5996 {
5997 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5998 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5999 }
6000
6001 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6002 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6003 { /* likely */ }
6004 else
6005 {
6006 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6008 }
6009
6010 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6011 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6012 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6013 { /* likely */ }
6014 else
6015 {
6016 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6018 }
6019
6020 /* Finally update our cache of the guest physical address of the shadow VMCS. */
6021 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6022 }
6023
6024 NOREF(pszInstr);
6025 NOREF(pszFailure);
6026 return VINF_SUCCESS;
6027}
6028
6029
6030/**
6031 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
6032 * VM-entry.
6033 *
6034 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6035 * @param pVCpu The cross context virtual CPU structure.
6036 * @param pszInstr The VMX instruction name (for logging purposes).
6037 * @param pVmcs Pointer to the virtual VMCS.
6038 */
6039IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6040{
6041 /*
6042 * Check PDPTEs.
6043 * See Intel spec. 4.4.1 "PDPTE Registers".
6044 */
6045 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6046 const char *const pszFailure = "VM-exit";
6047
6048 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6049 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6050 if (RT_SUCCESS(rc))
6051 {
6052 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6053 {
6054 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6055 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6056 { /* likely */ }
6057 else
6058 {
6059 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6060 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6062 }
6063 }
6064 }
6065 else
6066 {
6067 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6069 }
6070
6071 NOREF(pszFailure);
6072 NOREF(pszInstr);
6073 return rc;
6074}
6075
6076
6077/**
6078 * Checks guest PDPTEs as part of VM-entry.
6079 *
6080 * @param pVCpu The cross context virtual CPU structure.
6081 * @param pszInstr The VMX instruction name (for logging purposes).
6082 */
6083IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6084{
6085 /*
6086 * Guest PDPTEs.
6087 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6088 */
6089 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6090 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6091
6092 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6093 int rc;
6094 if ( !fGstInLongMode
6095 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6096 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6097 {
6098 /*
6099 * We don't support nested-paging for nested-guests yet.
6100 *
6101 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6102 * rather we need to check the PDPTEs referenced by the guest CR3.
6103 */
6104 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6105 }
6106 else
6107 rc = VINF_SUCCESS;
6108 return rc;
6109}
6110
6111
6112/**
6113 * Checks guest-state as part of VM-entry.
6114 *
6115 * @returns VBox status code.
6116 * @param pVCpu The cross context virtual CPU structure.
6117 * @param pszInstr The VMX instruction name (for logging purposes).
6118 */
6119IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6120{
6121 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6122 if (RT_SUCCESS(rc))
6123 {
6124 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6125 if (RT_SUCCESS(rc))
6126 {
6127 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6128 if (RT_SUCCESS(rc))
6129 {
6130 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6131 if (RT_SUCCESS(rc))
6132 {
6133 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6134 if (RT_SUCCESS(rc))
6135 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6136 }
6137 }
6138 }
6139 }
6140 return rc;
6141}
6142
6143
6144/**
6145 * Checks host-state as part of VM-entry.
6146 *
6147 * @returns VBox status code.
6148 * @param pVCpu The cross context virtual CPU structure.
6149 * @param pszInstr The VMX instruction name (for logging purposes).
6150 */
6151IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6152{
6153 /*
6154 * Host Control Registers and MSRs.
6155 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6156 */
6157 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6158 const char * const pszFailure = "VMFail";
6159
6160 /* CR0 reserved bits. */
6161 {
6162 /* CR0 MB1 bits. */
6163 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6164 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6165 { /* likely */ }
6166 else
6167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6168
6169 /* CR0 MBZ bits. */
6170 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6171 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6172 { /* likely */ }
6173 else
6174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6175 }
6176
6177 /* CR4 reserved bits. */
6178 {
6179 /* CR4 MB1 bits. */
6180 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6181 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6182 { /* likely */ }
6183 else
6184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6185
6186 /* CR4 MBZ bits. */
6187 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6188 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6189 { /* likely */ }
6190 else
6191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6192 }
6193
6194 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6195 {
6196 /* CR3 reserved bits. */
6197 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6198 { /* likely */ }
6199 else
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6201
6202 /* SYSENTER ESP and SYSENTER EIP. */
6203 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6204 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6205 { /* likely */ }
6206 else
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6208 }
6209
6210 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6211 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6212
6213 /* PAT MSR. */
6214 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6215 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6219
6220 /* EFER MSR. */
6221 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6222 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6223 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6224 { /* likely */ }
6225 else
6226 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6227
6228 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6229 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6230 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6231 if ( fHostInLongMode == fHostLma
6232 && fHostInLongMode == fHostLme)
6233 { /* likely */ }
6234 else
6235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6236
6237 /*
6238 * Host Segment and Descriptor-Table Registers.
6239 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6240 */
6241 /* Selector RPL and TI. */
6242 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6243 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6244 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6245 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6246 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6247 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6248 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6249 { /* likely */ }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6252
6253 /* CS and TR selectors cannot be 0. */
6254 if ( pVmcs->HostCs
6255 && pVmcs->HostTr)
6256 { /* likely */ }
6257 else
6258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6259
6260 /* SS cannot be 0 if 32-bit host. */
6261 if ( fHostInLongMode
6262 || pVmcs->HostSs)
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6266
6267 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6268 {
6269 /* FS, GS, GDTR, IDTR, TR base address. */
6270 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6271 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6272 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6273 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6274 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6275 { /* likely */ }
6276 else
6277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6278 }
6279
6280 /*
6281 * Host address-space size for 64-bit CPUs.
6282 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6283 */
6284 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6285 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6286 {
6287 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6288
6289 /* Logical processor in IA-32e mode. */
6290 if (fCpuInLongMode)
6291 {
6292 if (fHostInLongMode)
6293 {
6294 /* PAE must be set. */
6295 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6296 { /* likely */ }
6297 else
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6299
6300 /* RIP must be canonical. */
6301 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6305 }
6306 else
6307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6308 }
6309 else
6310 {
6311 /* Logical processor is outside IA-32e mode. */
6312 if ( !fGstInLongMode
6313 && !fHostInLongMode)
6314 {
6315 /* PCIDE should not be set. */
6316 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6317 { /* likely */ }
6318 else
6319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6320
6321 /* The high 32-bits of RIP MBZ. */
6322 if (!pVmcs->u64HostRip.s.Hi)
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6326 }
6327 else
6328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6329 }
6330 }
6331 else
6332 {
6333 /* Host address-space size for 32-bit CPUs. */
6334 if ( !fGstInLongMode
6335 && !fHostInLongMode)
6336 { /* likely */ }
6337 else
6338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6339 }
6340
6341 NOREF(pszInstr);
6342 NOREF(pszFailure);
6343 return VINF_SUCCESS;
6344}
6345
6346
6347/**
6348 * Checks VM-entry controls fields as part of VM-entry.
6349 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6350 *
6351 * @returns VBox status code.
6352 * @param pVCpu The cross context virtual CPU structure.
6353 * @param pszInstr The VMX instruction name (for logging purposes).
6354 */
6355IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6356{
6357 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6358 const char * const pszFailure = "VMFail";
6359
6360 /* VM-entry controls. */
6361 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6362 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6363 { /* likely */ }
6364 else
6365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6366
6367 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6368 { /* likely */ }
6369 else
6370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6371
6372 /* Event injection. */
6373 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6374 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6375 {
6376 /* Type and vector. */
6377 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6378 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6379 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6380 if ( !uRsvd
6381 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6382 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6383 { /* likely */ }
6384 else
6385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6386
6387 /* Exception error code. */
6388 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6389 {
6390 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6391 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6392 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6393 { /* likely */ }
6394 else
6395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6396
6397 /* Exceptions that provide an error code. */
6398 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6399 && ( uVector == X86_XCPT_DF
6400 || uVector == X86_XCPT_TS
6401 || uVector == X86_XCPT_NP
6402 || uVector == X86_XCPT_SS
6403 || uVector == X86_XCPT_GP
6404 || uVector == X86_XCPT_PF
6405 || uVector == X86_XCPT_AC))
6406 { /* likely */ }
6407 else
6408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6409
6410 /* Exception error-code reserved bits. */
6411 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6415
6416 /* Injecting a software interrupt, software exception or privileged software exception. */
6417 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6418 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6419 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6420 {
6421 /* Instruction length must be in the range 0-15. */
6422 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6423 { /* likely */ }
6424 else
6425 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6426
6427 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6428 if ( pVmcs->u32EntryInstrLen == 0
6429 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6431 }
6432 }
6433 }
6434
6435 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6436 if (pVmcs->u32EntryMsrLoadCount)
6437 {
6438 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6439 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6440 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6441 { /* likely */ }
6442 else
6443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6444 }
6445
6446 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6447 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6448
6449 NOREF(pszInstr);
6450 NOREF(pszFailure);
6451 return VINF_SUCCESS;
6452}
6453
6454
6455/**
6456 * Checks VM-exit controls fields as part of VM-entry.
6457 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6458 *
6459 * @returns VBox status code.
6460 * @param pVCpu The cross context virtual CPU structure.
6461 * @param pszInstr The VMX instruction name (for logging purposes).
6462 */
6463IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6464{
6465 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6466 const char * const pszFailure = "VMFail";
6467
6468 /* VM-exit controls. */
6469 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6470 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6474
6475 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6476 { /* likely */ }
6477 else
6478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6479
6480 /* Save preemption timer without activating it. */
6481 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6482 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6483 { /* likely */ }
6484 else
6485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6486
6487 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6488 if (pVmcs->u32ExitMsrStoreCount)
6489 {
6490 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6491 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6492 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6493 { /* likely */ }
6494 else
6495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6496 }
6497
6498 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6499 if (pVmcs->u32ExitMsrLoadCount)
6500 {
6501 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6502 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6503 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6507 }
6508
6509 NOREF(pszInstr);
6510 NOREF(pszFailure);
6511 return VINF_SUCCESS;
6512}
6513
6514
6515/**
6516 * Checks VM-execution controls fields as part of VM-entry.
6517 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6518 *
6519 * @returns VBox status code.
6520 * @param pVCpu The cross context virtual CPU structure.
6521 * @param pszInstr The VMX instruction name (for logging purposes).
6522 *
6523 * @remarks This may update secondary-processor based VM-execution control fields
6524 * in the current VMCS if necessary.
6525 */
6526IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6527{
6528 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6529 const char * const pszFailure = "VMFail";
6530
6531 /* Pin-based VM-execution controls. */
6532 {
6533 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6534 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6538
6539 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6540 { /* likely */ }
6541 else
6542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6543 }
6544
6545 /* Processor-based VM-execution controls. */
6546 {
6547 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6548 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6549 { /* likely */ }
6550 else
6551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6552
6553 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6557 }
6558
6559 /* Secondary processor-based VM-execution controls. */
6560 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6561 {
6562 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6563 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6564 { /* likely */ }
6565 else
6566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6567
6568 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6569 { /* likely */ }
6570 else
6571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6572 }
6573 else
6574 Assert(!pVmcs->u32ProcCtls2);
6575
6576 /* CR3-target count. */
6577 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6578 { /* likely */ }
6579 else
6580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6581
6582 /* I/O bitmaps physical addresses. */
6583 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6584 {
6585 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6586 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6587 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6588 { /* likely */ }
6589 else
6590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6591
6592 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6593 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6594 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6595 { /* likely */ }
6596 else
6597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6598 }
6599
6600 /* MSR bitmap physical address. */
6601 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6602 {
6603 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6604 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6605 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6606 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6607 { /* likely */ }
6608 else
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6610
6611 /* Read the MSR bitmap. */
6612 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6613 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6614 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6615 if (RT_SUCCESS(rc))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6619 }
6620
6621 /* TPR shadow related controls. */
6622 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6623 {
6624 /* Virtual-APIC page physical address. */
6625 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6626 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6627 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6628 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6629 { /* likely */ }
6630 else
6631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6632
6633 /* TPR threshold without virtual-interrupt delivery. */
6634 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6635 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6636 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6637
6638 /* TPR threshold and VTPR. */
6639 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6640 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6641 {
6642 /* Read the VTPR from the virtual-APIC page. */
6643 uint8_t u8VTpr;
6644 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6645 if (RT_SUCCESS(rc))
6646 { /* likely */ }
6647 else
6648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6649
6650 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6651 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6652 { /* likely */ }
6653 else
6654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6655 }
6656 }
6657 else
6658 {
6659 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6660 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6661 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6662 { /* likely */ }
6663 else
6664 {
6665 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6667 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6668 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6669 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6671 }
6672 }
6673
6674 /* NMI exiting and virtual-NMIs. */
6675 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6676 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6677 { /* likely */ }
6678 else
6679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6680
6681 /* Virtual-NMIs and NMI-window exiting. */
6682 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6683 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6684 { /* likely */ }
6685 else
6686 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6687
6688 /* Virtualize APIC accesses. */
6689 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6690 {
6691 /* APIC-access physical address. */
6692 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6693 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6694 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6695 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6696 { /* likely */ }
6697 else
6698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6699
6700 /*
6701 * Disallow APIC-access page and virtual-APIC page from being the same address.
6702 * Note! This is not an Intel requirement, but one imposed by our implementation.
6703 */
6704 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6705 * redirecting accesses between the APIC-access page and the virtual-APIC
6706 * page. If any nested hypervisor requires this, we can implement it later. */
6707 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6708 {
6709 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6710 if (GCPhysVirtApic != GCPhysApicAccess)
6711 { /* likely */ }
6712 else
6713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6714 }
6715
6716 /*
6717 * Register the handler for the APIC-access page.
6718 *
6719 * We don't deregister the APIC-access page handler during the VM-exit as a different
6720 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6721 *
6722 * We leave the page registered until the first access that happens outside VMX non-root
6723 * mode. Guest software is allowed to access structures such as the APIC-access page
6724 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6725 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6726 *
6727 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6728 */
6729 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6730 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6731 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6732 if (RT_SUCCESS(rc))
6733 { /* likely */ }
6734 else
6735 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6736 }
6737
6738 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6739 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6740 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6741 { /* likely */ }
6742 else
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6744
6745 /* Virtual-interrupt delivery requires external interrupt exiting. */
6746 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6747 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6751
6752 /* VPID. */
6753 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6754 || pVmcs->u16Vpid != 0)
6755 { /* likely */ }
6756 else
6757 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6758
6759 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6760 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6761 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6762 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6763 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6764 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6765 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6766
6767 /* VMCS shadowing. */
6768 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6769 {
6770 /* VMREAD-bitmap physical address. */
6771 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6772 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6773 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6774 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6775 { /* likely */ }
6776 else
6777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6778
6779 /* VMWRITE-bitmap physical address. */
6780 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6781 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6782 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6783 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6784 { /* likely */ }
6785 else
6786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6787
6788 /* Read the VMREAD-bitmap. */
6789 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6790 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6791 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6792 if (RT_SUCCESS(rc))
6793 { /* likely */ }
6794 else
6795 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6796
6797 /* Read the VMWRITE-bitmap. */
6798 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6799 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6800 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6801 if (RT_SUCCESS(rc))
6802 { /* likely */ }
6803 else
6804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6805 }
6806
6807 NOREF(pszInstr);
6808 NOREF(pszFailure);
6809 return VINF_SUCCESS;
6810}
6811
6812
6813/**
6814 * Loads the guest control registers, debug register and some MSRs as part of
6815 * VM-entry.
6816 *
6817 * @param pVCpu The cross context virtual CPU structure.
6818 */
6819IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6820{
6821 /*
6822 * Load guest control registers, debug registers and MSRs.
6823 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6824 */
6825 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6826
6827 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6828 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6829 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6830 CPUMSetGuestCR0(pVCpu, uGstCr0);
6831 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6832 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6833
6834 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6835 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6836
6837 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6838 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6839 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6840
6841 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6842 {
6843 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6844
6845 /* EFER MSR. */
6846 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6847 {
6848 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6849 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6850 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6851 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6852 if (fGstInLongMode)
6853 {
6854 /* If the nested-guest is in long mode, LMA and LME are both set. */
6855 Assert(fGstPaging);
6856 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6857 }
6858 else
6859 {
6860 /*
6861 * If the nested-guest is outside long mode:
6862 * - With paging: LMA is cleared, LME is cleared.
6863 * - Without paging: LMA is cleared, LME is left unmodified.
6864 */
6865 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6866 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6867 }
6868 }
6869 /* else: see below. */
6870 }
6871
6872 /* PAT MSR. */
6873 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6874 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6875
6876 /* EFER MSR. */
6877 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6878 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6879
6880 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6881 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6882
6883 /* We don't support IA32_BNDCFGS MSR yet. */
6884 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6885
6886 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6887}
6888
6889
6890/**
6891 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6892 *
6893 * @param pVCpu The cross context virtual CPU structure.
6894 */
6895IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6896{
6897 /*
6898 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6899 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6900 */
6901 /* CS, SS, ES, DS, FS, GS. */
6902 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6903 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6904 {
6905 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6906 CPUMSELREG VmcsSelReg;
6907 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6908 AssertRC(rc); NOREF(rc);
6909 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6910 {
6911 pGstSelReg->Sel = VmcsSelReg.Sel;
6912 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6913 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6914 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6915 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6916 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6917 }
6918 else
6919 {
6920 pGstSelReg->Sel = VmcsSelReg.Sel;
6921 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6922 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6923 switch (iSegReg)
6924 {
6925 case X86_SREG_CS:
6926 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6927 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6928 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6929 break;
6930
6931 case X86_SREG_SS:
6932 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6933 pGstSelReg->u32Limit = 0;
6934 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6935 break;
6936
6937 case X86_SREG_ES:
6938 case X86_SREG_DS:
6939 pGstSelReg->u64Base = 0;
6940 pGstSelReg->u32Limit = 0;
6941 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6942 break;
6943
6944 case X86_SREG_FS:
6945 case X86_SREG_GS:
6946 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6947 pGstSelReg->u32Limit = 0;
6948 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6949 break;
6950 }
6951 Assert(pGstSelReg->Attr.n.u1Unusable);
6952 }
6953 }
6954
6955 /* LDTR. */
6956 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6957 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6958 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6959 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6960 {
6961 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6962 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6963 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6964 }
6965 else
6966 {
6967 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6968 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6969 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6970 }
6971
6972 /* TR. */
6973 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6974 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6975 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6976 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6977 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6978 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6979 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6980
6981 /* GDTR. */
6982 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6983 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6984
6985 /* IDTR. */
6986 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6987 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6988}
6989
6990
6991/**
6992 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6993 *
6994 * @returns VBox status code.
6995 * @param pVCpu The cross context virtual CPU structure.
6996 * @param pszInstr The VMX instruction name (for logging purposes).
6997 */
6998IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6999{
7000 /*
7001 * Load guest MSRs.
7002 * See Intel spec. 26.4 "Loading MSRs".
7003 */
7004 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7005 const char *const pszFailure = "VM-exit";
7006
7007 /*
7008 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
7009 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
7010 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
7011 */
7012 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
7013 if (!cMsrs)
7014 return VINF_SUCCESS;
7015
7016 /*
7017 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7018 * exceeded including possibly raising #MC exceptions during VMX transition. Our
7019 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7020 */
7021 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7022 if (fIsMsrCountValid)
7023 { /* likely */ }
7024 else
7025 {
7026 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7028 }
7029
7030 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7031 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
7032 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7033 if (RT_SUCCESS(rc))
7034 {
7035 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7036 Assert(pMsr);
7037 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7038 {
7039 if ( !pMsr->u32Reserved
7040 && pMsr->u32Msr != MSR_K8_FS_BASE
7041 && pMsr->u32Msr != MSR_K8_GS_BASE
7042 && pMsr->u32Msr != MSR_K6_EFER
7043 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7044 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7045 {
7046 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7047 if (rcStrict == VINF_SUCCESS)
7048 continue;
7049
7050 /*
7051 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7052 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7053 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7054 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7055 * MSR in ring-0 if possible, or come up with a better, generic solution.
7056 */
7057 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7058 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7059 ? kVmxVDiag_Vmentry_MsrLoadRing3
7060 : kVmxVDiag_Vmentry_MsrLoad;
7061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7062 }
7063 else
7064 {
7065 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7067 }
7068 }
7069 }
7070 else
7071 {
7072 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7073 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7074 }
7075
7076 NOREF(pszInstr);
7077 NOREF(pszFailure);
7078 return VINF_SUCCESS;
7079}
7080
7081
7082/**
7083 * Loads the guest-state non-register state as part of VM-entry.
7084 *
7085 * @returns VBox status code.
7086 * @param pVCpu The cross context virtual CPU structure.
7087 *
7088 * @remarks This must be called only after loading the nested-guest register state
7089 * (especially nested-guest RIP).
7090 */
7091IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7092{
7093 /*
7094 * Load guest non-register state.
7095 * See Intel spec. 26.6 "Special Features of VM Entry"
7096 */
7097 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7098
7099 /*
7100 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7101 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7102 *
7103 * See Intel spec. 26.6.1 "Interruptibility State".
7104 */
7105 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7106 if ( !fEntryVectoring
7107 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7108 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7109 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7110 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7111
7112 /* NMI blocking. */
7113 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7114 {
7115 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7116 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7117 else
7118 {
7119 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7120 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7121 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7122 }
7123 }
7124 else
7125 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7126
7127 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7128
7129 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7130 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7131
7132 /* VPID is irrelevant. We don't support VPID yet. */
7133
7134 /* Clear address-range monitoring. */
7135 EMMonitorWaitClear(pVCpu);
7136}
7137
7138
7139/**
7140 * Loads the guest-state as part of VM-entry.
7141 *
7142 * @returns VBox status code.
7143 * @param pVCpu The cross context virtual CPU structure.
7144 * @param pszInstr The VMX instruction name (for logging purposes).
7145 *
7146 * @remarks This must be done after all the necessary steps prior to loading of
7147 * guest-state (e.g. checking various VMCS state).
7148 */
7149IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7150{
7151 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7152 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7153
7154 /*
7155 * Load guest RIP, RSP and RFLAGS.
7156 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7157 */
7158 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7159 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7160 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7161 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7162
7163 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7164 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7165 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7166
7167 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7168
7169 NOREF(pszInstr);
7170 return VINF_SUCCESS;
7171}
7172
7173
7174/**
7175 * Returns whether there are is a pending debug exception on VM-entry.
7176 *
7177 * @param pVCpu The cross context virtual CPU structure.
7178 * @param pszInstr The VMX instruction name (for logging purposes).
7179 */
7180IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7181{
7182 /*
7183 * Pending debug exceptions.
7184 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7185 */
7186 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7187 Assert(pVmcs);
7188
7189 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7190 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7191 if (fPendingDbgXcpt)
7192 {
7193 uint8_t uEntryIntInfoType;
7194 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7195 if (fEntryVectoring)
7196 {
7197 switch (uEntryIntInfoType)
7198 {
7199 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7200 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7201 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7202 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7203 fPendingDbgXcpt = false;
7204 break;
7205
7206 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7207 {
7208 /*
7209 * Whether the pending debug exception for software exceptions other than
7210 * #BP and #OF is delivered after injecting the exception or is discard
7211 * is CPU implementation specific. We will discard them (easier).
7212 */
7213 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7214 if ( uVector != X86_XCPT_BP
7215 && uVector != X86_XCPT_OF)
7216 fPendingDbgXcpt = false;
7217 RT_FALL_THRU();
7218 }
7219 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7220 {
7221 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7222 fPendingDbgXcpt = false;
7223 break;
7224 }
7225 }
7226 }
7227 else
7228 {
7229 /*
7230 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7231 * pending debug exception is held pending or is discarded is CPU implementation
7232 * specific. We will discard them (easier).
7233 */
7234 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7235 fPendingDbgXcpt = false;
7236
7237 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7238 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7239 fPendingDbgXcpt = false;
7240 }
7241 }
7242
7243 NOREF(pszInstr);
7244 return fPendingDbgXcpt;
7245}
7246
7247
7248/**
7249 * Set up the monitor-trap flag (MTF).
7250 *
7251 * @param pVCpu The cross context virtual CPU structure.
7252 * @param pszInstr The VMX instruction name (for logging purposes).
7253 */
7254IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7255{
7256 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7257 Assert(pVmcs);
7258 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7259 {
7260 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7261 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7262 }
7263 else
7264 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7265 NOREF(pszInstr);
7266}
7267
7268
7269/**
7270 * Sets up NMI-window exiting.
7271 *
7272 * @param pVCpu The cross context virtual CPU structure.
7273 * @param pszInstr The VMX instruction name (for logging purposes).
7274 */
7275IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7276{
7277 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7278 Assert(pVmcs);
7279 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7280 {
7281 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7282 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7283 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7284 }
7285 else
7286 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7287 NOREF(pszInstr);
7288}
7289
7290
7291/**
7292 * Sets up interrupt-window exiting.
7293 *
7294 * @param pVCpu The cross context virtual CPU structure.
7295 * @param pszInstr The VMX instruction name (for logging purposes).
7296 */
7297IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7298{
7299 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7300 Assert(pVmcs);
7301 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7302 {
7303 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7304 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7305 }
7306 else
7307 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7308 NOREF(pszInstr);
7309}
7310
7311
7312/**
7313 * Set up the VMX-preemption timer.
7314 *
7315 * @param pVCpu The cross context virtual CPU structure.
7316 * @param pszInstr The VMX instruction name (for logging purposes).
7317 */
7318IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7319{
7320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7321 Assert(pVmcs);
7322 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7323 {
7324 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7325 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7326 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7327
7328 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7329 }
7330 else
7331 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7332
7333 NOREF(pszInstr);
7334}
7335
7336
7337/**
7338 * Injects an event using TRPM given a VM-entry interruption info. and related
7339 * fields.
7340 *
7341 * @returns VBox status code.
7342 * @param pVCpu The cross context virtual CPU structure.
7343 * @param uEntryIntInfo The VM-entry interruption info.
7344 * @param uErrCode The error code associated with the event if any.
7345 * @param cbInstr The VM-entry instruction length (for software
7346 * interrupts and software exceptions). Pass 0
7347 * otherwise.
7348 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7349 */
7350IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7351 RTGCUINTPTR GCPtrFaultAddress)
7352{
7353 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7354
7355 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7356 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7357 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7358
7359 TRPMEVENT enmTrapType;
7360 switch (uType)
7361 {
7362 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7363 enmTrapType = TRPM_HARDWARE_INT;
7364 break;
7365
7366 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7367 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7368 enmTrapType = TRPM_TRAP;
7369 break;
7370
7371 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7372 enmTrapType = TRPM_SOFTWARE_INT;
7373 break;
7374
7375 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7376 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7377 enmTrapType = TRPM_SOFTWARE_INT;
7378 break;
7379
7380 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7381 Assert(uVector == X86_XCPT_DB);
7382 enmTrapType = TRPM_SOFTWARE_INT;
7383 break;
7384
7385 default:
7386 /* Shouldn't really happen. */
7387 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7388 break;
7389 }
7390
7391 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7392 AssertRCReturn(rc, rc);
7393
7394 if (fErrCodeValid)
7395 TRPMSetErrorCode(pVCpu, uErrCode);
7396
7397 if ( enmTrapType == TRPM_TRAP
7398 && uVector == X86_XCPT_PF)
7399 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7400 else if (enmTrapType == TRPM_SOFTWARE_INT)
7401 TRPMSetInstrLength(pVCpu, cbInstr);
7402
7403 return VINF_SUCCESS;
7404}
7405
7406
7407/**
7408 * Performs event injection (if any) as part of VM-entry.
7409 *
7410 * @param pVCpu The cross context virtual CPU structure.
7411 * @param pszInstr The VMX instruction name (for logging purposes).
7412 */
7413IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7414{
7415 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7416
7417 /*
7418 * Inject events.
7419 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7420 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7421 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7422 * the actually delivery of this event.
7423 *
7424 * See Intel spec. 26.5 "Event Injection".
7425 */
7426 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7427 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7428
7429 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7430 if (fEntryIntInfoValid)
7431 {
7432 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7433 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7434 {
7435 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7436 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7437 return VINF_SUCCESS;
7438 }
7439
7440 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7441 pVCpu->cpum.GstCtx.cr2);
7442 if (RT_SUCCESS(rc))
7443 {
7444 /*
7445 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7446 *
7447 * However, we do it here on VM-entry because while it continues to not be visible to
7448 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7449 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7450 * information field.
7451 *
7452 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7453 */
7454 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7455 }
7456 return rc;
7457 }
7458
7459 /*
7460 * Inject any pending guest debug exception.
7461 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7462 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7463 */
7464 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7465 if (fPendingDbgXcpt)
7466 {
7467 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7468 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7469 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7470 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7471 0 /* GCPtrFaultAddress */);
7472 }
7473
7474 NOREF(pszInstr);
7475 return VINF_SUCCESS;
7476}
7477
7478
7479/**
7480 * Initializes all read-only VMCS fields as part of VM-entry.
7481 *
7482 * @param pVCpu The cross context virtual CPU structure.
7483 */
7484IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7485{
7486 /*
7487 * Any VMCS field which we do not establish on every VM-exit but may potentially
7488 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7489 * specified to be undefined needs to be initialized here.
7490 *
7491 * Thus, it is especially important to clear the VM-exit qualification field
7492 * since it must be zero for VM-exits where it is not used. Similarly, the
7493 * VM-exit interruption information field's valid bit needs to be cleared for
7494 * the same reasons.
7495 */
7496 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7497 Assert(pVmcs);
7498
7499 /* 16-bit (none currently). */
7500 /* 32-bit. */
7501 pVmcs->u32RoVmInstrError = 0;
7502 pVmcs->u32RoExitReason = 0;
7503 pVmcs->u32RoExitIntInfo = 0;
7504 pVmcs->u32RoExitIntErrCode = 0;
7505 pVmcs->u32RoIdtVectoringInfo = 0;
7506 pVmcs->u32RoIdtVectoringErrCode = 0;
7507 pVmcs->u32RoExitInstrLen = 0;
7508 pVmcs->u32RoExitInstrInfo = 0;
7509
7510 /* 64-bit. */
7511 pVmcs->u64RoGuestPhysAddr.u = 0;
7512
7513 /* Natural-width. */
7514 pVmcs->u64RoExitQual.u = 0;
7515 pVmcs->u64RoIoRcx.u = 0;
7516 pVmcs->u64RoIoRsi.u = 0;
7517 pVmcs->u64RoIoRdi.u = 0;
7518 pVmcs->u64RoIoRip.u = 0;
7519 pVmcs->u64RoGuestLinearAddr.u = 0;
7520}
7521
7522
7523/**
7524 * VMLAUNCH/VMRESUME instruction execution worker.
7525 *
7526 * @returns Strict VBox status code.
7527 * @param pVCpu The cross context virtual CPU structure.
7528 * @param cbInstr The instruction length in bytes.
7529 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7530 * VMXINSTRID_VMRESUME).
7531 *
7532 * @remarks Common VMX instruction checks are already expected to by the caller,
7533 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7534 */
7535IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7536{
7537# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7538 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7539 return VINF_EM_RAW_EMULATE_INSTR;
7540# else
7541 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7542 || uInstrId == VMXINSTRID_VMRESUME);
7543 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7544
7545 /* Nested-guest intercept. */
7546 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7547 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7548
7549 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7550
7551 /*
7552 * Basic VM-entry checks.
7553 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7554 * The checks following that do not have to follow a specific order.
7555 *
7556 * See Intel spec. 26.1 "Basic VM-entry Checks".
7557 */
7558
7559 /* CPL. */
7560 if (pVCpu->iem.s.uCpl == 0)
7561 { /* likely */ }
7562 else
7563 {
7564 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7565 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7566 return iemRaiseGeneralProtectionFault0(pVCpu);
7567 }
7568
7569 /* Current VMCS valid. */
7570 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7571 { /* likely */ }
7572 else
7573 {
7574 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7576 iemVmxVmFailInvalid(pVCpu);
7577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7578 return VINF_SUCCESS;
7579 }
7580
7581 /* Current VMCS is not a shadow VMCS. */
7582 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7583 { /* likely */ }
7584 else
7585 {
7586 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7588 iemVmxVmFailInvalid(pVCpu);
7589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7590 return VINF_SUCCESS;
7591 }
7592
7593 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7594 * use block-by-STI here which is not quite correct. */
7595 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7596 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7597 { /* likely */ }
7598 else
7599 {
7600 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7601 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7602 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7603 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7604 return VINF_SUCCESS;
7605 }
7606
7607 if (uInstrId == VMXINSTRID_VMLAUNCH)
7608 {
7609 /* VMLAUNCH with non-clear VMCS. */
7610 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7611 { /* likely */ }
7612 else
7613 {
7614 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7616 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7617 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7618 return VINF_SUCCESS;
7619 }
7620 }
7621 else
7622 {
7623 /* VMRESUME with non-launched VMCS. */
7624 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7625 { /* likely */ }
7626 else
7627 {
7628 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7629 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7630 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7631 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7632 return VINF_SUCCESS;
7633 }
7634 }
7635
7636 /*
7637 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7638 * while entering VMX non-root mode. We do some of this while checking VM-execution
7639 * controls. The guest hypervisor should not make assumptions and cannot expect
7640 * predictable behavior if changes to these structures are made in guest memory while
7641 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7642 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7643 *
7644 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7645 */
7646 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7647 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7648 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7649 if (RT_SUCCESS(rc))
7650 {
7651 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7652 if (RT_SUCCESS(rc))
7653 {
7654 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7655 if (RT_SUCCESS(rc))
7656 {
7657 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7658 if (RT_SUCCESS(rc))
7659 {
7660 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7661 iemVmxVmentryInitReadOnlyFields(pVCpu);
7662
7663 /*
7664 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7665 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7666 * VM-exit when required.
7667 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7668 */
7669 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7670
7671 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7672 if (RT_SUCCESS(rc))
7673 {
7674 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7675 if (RT_SUCCESS(rc))
7676 {
7677 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7678 if (RT_SUCCESS(rc))
7679 {
7680 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7681
7682 /* VMLAUNCH instruction must update the VMCS launch state. */
7683 if (uInstrId == VMXINSTRID_VMLAUNCH)
7684 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7685
7686 /* Perform the VMX transition (PGM updates). */
7687 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7688 if (rcStrict == VINF_SUCCESS)
7689 { /* likely */ }
7690 else if (RT_SUCCESS(rcStrict))
7691 {
7692 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7693 VBOXSTRICTRC_VAL(rcStrict)));
7694 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7695 }
7696 else
7697 {
7698 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7699 return rcStrict;
7700 }
7701
7702 /* We've now entered nested-guest execution. */
7703 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7704
7705 /*
7706 * The priority of potential VM-exits during VM-entry is important.
7707 * The priorities of VM-exits and events are listed from highest
7708 * to lowest as follows:
7709 *
7710 * 1. Event injection.
7711 * 2. Trap on task-switch (T flag set in TSS).
7712 * 3. TPR below threshold / APIC-write.
7713 * 4. SMI, INIT.
7714 * 5. MTF exit.
7715 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7716 * 7. VMX-preemption timer.
7717 * 9. NMI-window exit.
7718 * 10. NMI injection.
7719 * 11. Interrupt-window exit.
7720 * 12. Virtual-interrupt injection.
7721 * 13. Interrupt injection.
7722 * 14. Process next instruction (fetch, decode, execute).
7723 */
7724
7725 /* Setup the VMX-preemption timer. */
7726 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7727
7728 /* Setup monitor-trap flag. */
7729 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7730
7731 /* Setup NMI-window exiting. */
7732 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7733
7734 /* Setup interrupt-window exiting. */
7735 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7736
7737 /* Now that we've switched page tables, we can go ahead and inject any event. */
7738 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7739 if (RT_SUCCESS(rcStrict))
7740 {
7741 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7742# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7743 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7744 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7745 if (rcSched != VINF_SUCCESS)
7746 iemSetPassUpStatus(pVCpu, rcSched);
7747# endif
7748 return VINF_SUCCESS;
7749 }
7750
7751 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7752 return rcStrict;
7753 }
7754 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7755 }
7756 }
7757 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7758 }
7759
7760 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7761 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7762 return VINF_SUCCESS;
7763 }
7764 }
7765 }
7766
7767 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7768 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7769 return VINF_SUCCESS;
7770# endif
7771}
7772
7773
7774/**
7775 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7776 * (causes a VM-exit) or not.
7777 *
7778 * @returns @c true if the instruction is intercepted, @c false otherwise.
7779 * @param pVCpu The cross context virtual CPU structure.
7780 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7781 * VMX_EXIT_WRMSR).
7782 * @param idMsr The MSR.
7783 */
7784IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7785{
7786 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7787 Assert( uExitReason == VMX_EXIT_RDMSR
7788 || uExitReason == VMX_EXIT_WRMSR);
7789
7790 /* Consult the MSR bitmap if the feature is supported. */
7791 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7792 Assert(pVmcs);
7793 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7794 {
7795 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7796 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7797 if (uExitReason == VMX_EXIT_RDMSR)
7798 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7799 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7800 }
7801
7802 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7803 return true;
7804}
7805
7806
7807/**
7808 * VMREAD common (memory/register) instruction execution worker
7809 *
7810 * @returns Strict VBox status code.
7811 * @param pVCpu The cross context virtual CPU structure.
7812 * @param cbInstr The instruction length in bytes.
7813 * @param pu64Dst Where to write the VMCS value (only updated when
7814 * VINF_SUCCESS is returned).
7815 * @param u64FieldEnc The VMCS field encoding.
7816 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7817 * NULL.
7818 */
7819IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7820 PCVMXVEXITINFO pExitInfo)
7821{
7822 /* Nested-guest intercept. */
7823 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7824 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7825 {
7826 if (pExitInfo)
7827 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7828 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7829 }
7830
7831 /* CPL. */
7832 if (pVCpu->iem.s.uCpl == 0)
7833 { /* likely */ }
7834 else
7835 {
7836 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7837 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7838 return iemRaiseGeneralProtectionFault0(pVCpu);
7839 }
7840
7841 /* VMCS pointer in root mode. */
7842 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7843 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7844 { /* likely */ }
7845 else
7846 {
7847 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7848 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7849 iemVmxVmFailInvalid(pVCpu);
7850 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7851 return VINF_SUCCESS;
7852 }
7853
7854 /* VMCS-link pointer in non-root mode. */
7855 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7856 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7857 { /* likely */ }
7858 else
7859 {
7860 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7862 iemVmxVmFailInvalid(pVCpu);
7863 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7864 return VINF_SUCCESS;
7865 }
7866
7867 /* Supported VMCS field. */
7868 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7869 { /* likely */ }
7870 else
7871 {
7872 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7873 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7874 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7875 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7876 return VINF_SUCCESS;
7877 }
7878
7879 /*
7880 * Setup reading from the current or shadow VMCS.
7881 */
7882 uint8_t *pbVmcs;
7883 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7884 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7885 else
7886 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7887 Assert(pbVmcs);
7888
7889 VMXVMCSFIELDENC FieldEnc;
7890 FieldEnc.u = u64FieldEnc;
7891 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7892 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7893 uint8_t const uWidthType = (uWidth << 2) | uType;
7894 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7895 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7896 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7897 Assert(offField < VMX_V_VMCS_SIZE);
7898
7899 /*
7900 * Read the VMCS component based on the field's effective width.
7901 *
7902 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7903 * indicates high bits (little endian).
7904 *
7905 * Note! The caller is responsible to trim the result and update registers
7906 * or memory locations are required. Here we just zero-extend to the largest
7907 * type (i.e. 64-bits).
7908 */
7909 uint8_t *pbField = pbVmcs + offField;
7910 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7911 switch (uEffWidth)
7912 {
7913 case VMX_VMCS_ENC_WIDTH_64BIT:
7914 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7915 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7916 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7917 }
7918 return VINF_SUCCESS;
7919}
7920
7921
7922/**
7923 * VMREAD (64-bit register) instruction execution worker.
7924 *
7925 * @returns Strict VBox status code.
7926 * @param pVCpu The cross context virtual CPU structure.
7927 * @param cbInstr The instruction length in bytes.
7928 * @param pu64Dst Where to store the VMCS field's value.
7929 * @param u64FieldEnc The VMCS field encoding.
7930 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7931 * NULL.
7932 */
7933IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7934 PCVMXVEXITINFO pExitInfo)
7935{
7936 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7937 if (rcStrict == VINF_SUCCESS)
7938 {
7939 iemVmxVmreadSuccess(pVCpu, cbInstr);
7940 return VINF_SUCCESS;
7941 }
7942
7943 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7944 return rcStrict;
7945}
7946
7947
7948/**
7949 * VMREAD (32-bit register) instruction execution worker.
7950 *
7951 * @returns Strict VBox status code.
7952 * @param pVCpu The cross context virtual CPU structure.
7953 * @param cbInstr The instruction length in bytes.
7954 * @param pu32Dst Where to store the VMCS field's value.
7955 * @param u32FieldEnc The VMCS field encoding.
7956 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7957 * NULL.
7958 */
7959IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7960 PCVMXVEXITINFO pExitInfo)
7961{
7962 uint64_t u64Dst;
7963 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7964 if (rcStrict == VINF_SUCCESS)
7965 {
7966 *pu32Dst = u64Dst;
7967 iemVmxVmreadSuccess(pVCpu, cbInstr);
7968 return VINF_SUCCESS;
7969 }
7970
7971 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7972 return rcStrict;
7973}
7974
7975
7976/**
7977 * VMREAD (memory) instruction execution worker.
7978 *
7979 * @returns Strict VBox status code.
7980 * @param pVCpu The cross context virtual CPU structure.
7981 * @param cbInstr The instruction length in bytes.
7982 * @param iEffSeg The effective segment register to use with @a u64Val.
7983 * Pass UINT8_MAX if it is a register access.
7984 * @param GCPtrDst The guest linear address to store the VMCS field's
7985 * value.
7986 * @param u64FieldEnc The VMCS field encoding.
7987 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7988 * NULL.
7989 */
7990IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
7991 PCVMXVEXITINFO pExitInfo)
7992{
7993 uint64_t u64Dst;
7994 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7995 if (rcStrict == VINF_SUCCESS)
7996 {
7997 /*
7998 * Write the VMCS field's value to the location specified in guest-memory.
7999 */
8000 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8001 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8002 else
8003 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8004 if (rcStrict == VINF_SUCCESS)
8005 {
8006 iemVmxVmreadSuccess(pVCpu, cbInstr);
8007 return VINF_SUCCESS;
8008 }
8009
8010 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8011 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8012 return rcStrict;
8013 }
8014
8015 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8016 return rcStrict;
8017}
8018
8019
8020/**
8021 * VMWRITE instruction execution worker.
8022 *
8023 * @returns Strict VBox status code.
8024 * @param pVCpu The cross context virtual CPU structure.
8025 * @param cbInstr The instruction length in bytes.
8026 * @param iEffSeg The effective segment register to use with @a u64Val.
8027 * Pass UINT8_MAX if it is a register access.
8028 * @param u64Val The value to write (or guest linear address to the
8029 * value), @a iEffSeg will indicate if it's a memory
8030 * operand.
8031 * @param u64FieldEnc The VMCS field encoding.
8032 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8033 * NULL.
8034 */
8035IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8036 PCVMXVEXITINFO pExitInfo)
8037{
8038 /* Nested-guest intercept. */
8039 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8040 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8041 {
8042 if (pExitInfo)
8043 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8044 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8045 }
8046
8047 /* CPL. */
8048 if (pVCpu->iem.s.uCpl == 0)
8049 { /* likely */ }
8050 else
8051 {
8052 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8053 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8054 return iemRaiseGeneralProtectionFault0(pVCpu);
8055 }
8056
8057 /* VMCS pointer in root mode. */
8058 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8059 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8060 { /* likely */ }
8061 else
8062 {
8063 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8064 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8065 iemVmxVmFailInvalid(pVCpu);
8066 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8067 return VINF_SUCCESS;
8068 }
8069
8070 /* VMCS-link pointer in non-root mode. */
8071 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8072 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8073 { /* likely */ }
8074 else
8075 {
8076 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8077 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8078 iemVmxVmFailInvalid(pVCpu);
8079 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8080 return VINF_SUCCESS;
8081 }
8082
8083 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8084 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8085 if (!fIsRegOperand)
8086 {
8087 /* Read the value from the specified guest memory location. */
8088 VBOXSTRICTRC rcStrict;
8089 RTGCPTR const GCPtrVal = u64Val;
8090 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8091 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8092 else
8093 {
8094 uint32_t u32Val;
8095 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8096 u64Val = u32Val;
8097 }
8098 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8099 {
8100 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8102 return rcStrict;
8103 }
8104 }
8105 else
8106 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8107
8108 /* Supported VMCS field. */
8109 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8110 { /* likely */ }
8111 else
8112 {
8113 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8114 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8115 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8116 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8117 return VINF_SUCCESS;
8118 }
8119
8120 /* Read-only VMCS field. */
8121 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8122 if ( !fIsFieldReadOnly
8123 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8124 { /* likely */ }
8125 else
8126 {
8127 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8128 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8129 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8130 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8131 return VINF_SUCCESS;
8132 }
8133
8134 /*
8135 * Setup writing to the current or shadow VMCS.
8136 */
8137 uint8_t *pbVmcs;
8138 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8139 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8140 else
8141 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8142 Assert(pbVmcs);
8143
8144 VMXVMCSFIELDENC FieldEnc;
8145 FieldEnc.u = u64FieldEnc;
8146 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8147 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8148 uint8_t const uWidthType = (uWidth << 2) | uType;
8149 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8150 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8151 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8152 Assert(offField < VMX_V_VMCS_SIZE);
8153
8154 /*
8155 * Write the VMCS component based on the field's effective width.
8156 *
8157 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8158 * indicates high bits (little endian).
8159 */
8160 uint8_t *pbField = pbVmcs + offField;
8161 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8162 switch (uEffWidth)
8163 {
8164 case VMX_VMCS_ENC_WIDTH_64BIT:
8165 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8166 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8167 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8168 }
8169
8170 iemVmxVmSucceed(pVCpu);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173}
8174
8175
8176/**
8177 * VMCLEAR instruction execution worker.
8178 *
8179 * @returns Strict VBox status code.
8180 * @param pVCpu The cross context virtual CPU structure.
8181 * @param cbInstr The instruction length in bytes.
8182 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8183 * @param GCPtrVmcs The linear address of the VMCS pointer.
8184 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8185 * NULL.
8186 *
8187 * @remarks Common VMX instruction checks are already expected to by the caller,
8188 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8189 */
8190IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8191 PCVMXVEXITINFO pExitInfo)
8192{
8193 /* Nested-guest intercept. */
8194 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8195 {
8196 if (pExitInfo)
8197 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8198 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8199 }
8200
8201 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8202
8203 /* CPL. */
8204 if (pVCpu->iem.s.uCpl == 0)
8205 { /* likely */ }
8206 else
8207 {
8208 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8209 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8210 return iemRaiseGeneralProtectionFault0(pVCpu);
8211 }
8212
8213 /* Get the VMCS pointer from the location specified by the source memory operand. */
8214 RTGCPHYS GCPhysVmcs;
8215 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8216 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8217 { /* likely */ }
8218 else
8219 {
8220 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8221 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8222 return rcStrict;
8223 }
8224
8225 /* VMCS pointer alignment. */
8226 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8227 { /* likely */ }
8228 else
8229 {
8230 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8231 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8232 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8233 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8234 return VINF_SUCCESS;
8235 }
8236
8237 /* VMCS physical-address width limits. */
8238 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8239 { /* likely */ }
8240 else
8241 {
8242 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8243 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8244 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8246 return VINF_SUCCESS;
8247 }
8248
8249 /* VMCS is not the VMXON region. */
8250 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8251 { /* likely */ }
8252 else
8253 {
8254 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8256 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8257 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8258 return VINF_SUCCESS;
8259 }
8260
8261 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8262 restriction imposed by our implementation. */
8263 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8264 { /* likely */ }
8265 else
8266 {
8267 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8268 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8269 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8270 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8271 return VINF_SUCCESS;
8272 }
8273
8274 /*
8275 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8276 *
8277 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8278 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8279 * to 'clear'.
8280 */
8281 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8282 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8283 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8284 {
8285 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8286 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8287 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8288 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8289 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8290 }
8291 else
8292 {
8293 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8294 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8295 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8296 if (RT_FAILURE(rcStrict))
8297 return rcStrict;
8298 }
8299
8300 iemVmxVmSucceed(pVCpu);
8301 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8302 return VINF_SUCCESS;
8303}
8304
8305
8306/**
8307 * VMPTRST instruction execution worker.
8308 *
8309 * @returns Strict VBox status code.
8310 * @param pVCpu The cross context virtual CPU structure.
8311 * @param cbInstr The instruction length in bytes.
8312 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8313 * @param GCPtrVmcs The linear address of where to store the current VMCS
8314 * pointer.
8315 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8316 * NULL.
8317 *
8318 * @remarks Common VMX instruction checks are already expected to by the caller,
8319 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8320 */
8321IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8322 PCVMXVEXITINFO pExitInfo)
8323{
8324 /* Nested-guest intercept. */
8325 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8326 {
8327 if (pExitInfo)
8328 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8329 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8330 }
8331
8332 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8333
8334 /* CPL. */
8335 if (pVCpu->iem.s.uCpl == 0)
8336 { /* likely */ }
8337 else
8338 {
8339 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8340 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8341 return iemRaiseGeneralProtectionFault0(pVCpu);
8342 }
8343
8344 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8345 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8346 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8347 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8348 {
8349 iemVmxVmSucceed(pVCpu);
8350 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8351 return rcStrict;
8352 }
8353
8354 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8355 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8356 return rcStrict;
8357}
8358
8359
8360/**
8361 * VMPTRLD instruction execution worker.
8362 *
8363 * @returns Strict VBox status code.
8364 * @param pVCpu The cross context virtual CPU structure.
8365 * @param cbInstr The instruction length in bytes.
8366 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8367 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8368 * NULL.
8369 *
8370 * @remarks Common VMX instruction checks are already expected to by the caller,
8371 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8372 */
8373IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8374 PCVMXVEXITINFO pExitInfo)
8375{
8376 /* Nested-guest intercept. */
8377 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8378 {
8379 if (pExitInfo)
8380 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8381 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8382 }
8383
8384 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8385
8386 /* CPL. */
8387 if (pVCpu->iem.s.uCpl == 0)
8388 { /* likely */ }
8389 else
8390 {
8391 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8393 return iemRaiseGeneralProtectionFault0(pVCpu);
8394 }
8395
8396 /* Get the VMCS pointer from the location specified by the source memory operand. */
8397 RTGCPHYS GCPhysVmcs;
8398 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8399 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8400 { /* likely */ }
8401 else
8402 {
8403 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8405 return rcStrict;
8406 }
8407
8408 /* VMCS pointer alignment. */
8409 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8410 { /* likely */ }
8411 else
8412 {
8413 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8416 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8417 return VINF_SUCCESS;
8418 }
8419
8420 /* VMCS physical-address width limits. */
8421 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8427 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8429 return VINF_SUCCESS;
8430 }
8431
8432 /* VMCS is not the VMXON region. */
8433 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8434 { /* likely */ }
8435 else
8436 {
8437 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8438 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8439 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8440 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8441 return VINF_SUCCESS;
8442 }
8443
8444 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8445 restriction imposed by our implementation. */
8446 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8447 { /* likely */ }
8448 else
8449 {
8450 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8451 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8452 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8453 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8454 return VINF_SUCCESS;
8455 }
8456
8457 /* Read just the VMCS revision from the VMCS. */
8458 VMXVMCSREVID VmcsRevId;
8459 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8460 if (RT_SUCCESS(rc))
8461 { /* likely */ }
8462 else
8463 {
8464 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8465 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8466 return rc;
8467 }
8468
8469 /*
8470 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8471 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8472 */
8473 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8474 && ( !VmcsRevId.n.fIsShadowVmcs
8475 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8476 { /* likely */ }
8477 else
8478 {
8479 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8480 {
8481 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8482 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8484 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8485 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8486 return VINF_SUCCESS;
8487 }
8488
8489 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8490 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8491 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8492 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8493 return VINF_SUCCESS;
8494 }
8495
8496 /*
8497 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8498 * the cache of an existing, current VMCS back to guest memory before loading a new,
8499 * different current VMCS.
8500 */
8501 bool fLoadVmcsFromMem;
8502 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8503 {
8504 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8505 {
8506 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8507 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8508 fLoadVmcsFromMem = true;
8509 }
8510 else
8511 fLoadVmcsFromMem = false;
8512 }
8513 else
8514 fLoadVmcsFromMem = true;
8515
8516 if (fLoadVmcsFromMem)
8517 {
8518 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8519 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8520 sizeof(VMXVVMCS));
8521 if (RT_SUCCESS(rc))
8522 { /* likely */ }
8523 else
8524 {
8525 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8526 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8527 return rc;
8528 }
8529 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8530 }
8531
8532 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8533 iemVmxVmSucceed(pVCpu);
8534 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8535 return VINF_SUCCESS;
8536}
8537
8538
8539/**
8540 * INVVPID instruction execution worker.
8541 *
8542 * @returns Strict VBox status code.
8543 * @param pVCpu The cross context virtual CPU structure.
8544 * @param cbInstr The instruction length in bytes.
8545 * @param iEffSeg The segment of the invvpid descriptor.
8546 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8547 * @param u64InvvpidType The invalidation type.
8548 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8549 * NULL.
8550 *
8551 * @remarks Common VMX instruction checks are already expected to by the caller,
8552 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8553 */
8554IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8555 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8556{
8557 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8558 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8559 return iemRaiseUndefinedOpcode(pVCpu);
8560
8561 /* Nested-guest intercept. */
8562 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8563 {
8564 if (pExitInfo)
8565 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8566 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8567 }
8568
8569 /* CPL. */
8570 if (pVCpu->iem.s.uCpl != 0)
8571 {
8572 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8573 return iemRaiseGeneralProtectionFault0(pVCpu);
8574 }
8575
8576 /*
8577 * Validate INVVPID invalidation type.
8578 *
8579 * The instruction specifies exactly ONE of the supported invalidation types.
8580 *
8581 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8582 * supported. In theory, it's possible for a CPU to not support flushing individual
8583 * addresses but all the other types or any other combination. We do not take any
8584 * shortcuts here by assuming the types we currently expose to the guest.
8585 */
8586 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8587 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8588 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8589 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8590 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8591 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8592 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8593 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8594 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8595 { /* likely */ }
8596 else
8597 {
8598 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8599 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8600 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8602 return VINF_SUCCESS;
8603 }
8604
8605 /*
8606 * Fetch the invvpid descriptor from guest memory.
8607 */
8608 RTUINT128U uDesc;
8609 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8610 if (rcStrict == VINF_SUCCESS)
8611 {
8612 /*
8613 * Validate the descriptor.
8614 */
8615 if (uDesc.s.Lo > 0xfff)
8616 {
8617 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8618 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8619 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8620 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8621 return VINF_SUCCESS;
8622 }
8623
8624 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8625 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8626 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8627 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8628 switch (u64InvvpidType)
8629 {
8630 case VMXTLBFLUSHVPID_INDIV_ADDR:
8631 {
8632 if (uVpid != 0)
8633 {
8634 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8635 {
8636 /* Invalidate mappings for the linear address tagged with VPID. */
8637 /** @todo PGM support for VPID? Currently just flush everything. */
8638 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8639 iemVmxVmSucceed(pVCpu);
8640 }
8641 else
8642 {
8643 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8644 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8645 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8646 }
8647 }
8648 else
8649 {
8650 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8652 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8653 }
8654 break;
8655 }
8656
8657 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8658 {
8659 if (uVpid != 0)
8660 {
8661 /* Invalidate all mappings with VPID. */
8662 /** @todo PGM support for VPID? Currently just flush everything. */
8663 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8664 iemVmxVmSucceed(pVCpu);
8665 }
8666 else
8667 {
8668 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8669 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8670 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8671 }
8672 break;
8673 }
8674
8675 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8676 {
8677 /* Invalidate all mappings with non-zero VPIDs. */
8678 /** @todo PGM support for VPID? Currently just flush everything. */
8679 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8680 iemVmxVmSucceed(pVCpu);
8681 break;
8682 }
8683
8684 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8685 {
8686 if (uVpid != 0)
8687 {
8688 /* Invalidate all mappings with VPID except global translations. */
8689 /** @todo PGM support for VPID? Currently just flush everything. */
8690 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8691 iemVmxVmSucceed(pVCpu);
8692 }
8693 else
8694 {
8695 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8696 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8697 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8698 }
8699 break;
8700 }
8701 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8702 }
8703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8704 }
8705 return rcStrict;
8706}
8707
8708
8709/**
8710 * VMXON instruction execution worker.
8711 *
8712 * @returns Strict VBox status code.
8713 * @param pVCpu The cross context virtual CPU structure.
8714 * @param cbInstr The instruction length in bytes.
8715 * @param iEffSeg The effective segment register to use with @a
8716 * GCPtrVmxon.
8717 * @param GCPtrVmxon The linear address of the VMXON pointer.
8718 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8719 * NULL.
8720 *
8721 * @remarks Common VMX instruction checks are already expected to by the caller,
8722 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8723 */
8724IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8725 PCVMXVEXITINFO pExitInfo)
8726{
8727 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8728 {
8729 /* CPL. */
8730 if (pVCpu->iem.s.uCpl == 0)
8731 { /* likely */ }
8732 else
8733 {
8734 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8735 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8736 return iemRaiseGeneralProtectionFault0(pVCpu);
8737 }
8738
8739 /* A20M (A20 Masked) mode. */
8740 if (PGMPhysIsA20Enabled(pVCpu))
8741 { /* likely */ }
8742 else
8743 {
8744 Log(("vmxon: A20M mode -> #GP(0)\n"));
8745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8746 return iemRaiseGeneralProtectionFault0(pVCpu);
8747 }
8748
8749 /* CR0. */
8750 {
8751 /* CR0 MB1 bits. */
8752 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8753 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8754 { /* likely */ }
8755 else
8756 {
8757 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8758 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8759 return iemRaiseGeneralProtectionFault0(pVCpu);
8760 }
8761
8762 /* CR0 MBZ bits. */
8763 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8764 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8765 { /* likely */ }
8766 else
8767 {
8768 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8769 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8770 return iemRaiseGeneralProtectionFault0(pVCpu);
8771 }
8772 }
8773
8774 /* CR4. */
8775 {
8776 /* CR4 MB1 bits. */
8777 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8778 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8779 { /* likely */ }
8780 else
8781 {
8782 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8784 return iemRaiseGeneralProtectionFault0(pVCpu);
8785 }
8786
8787 /* CR4 MBZ bits. */
8788 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8789 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8790 { /* likely */ }
8791 else
8792 {
8793 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8794 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8795 return iemRaiseGeneralProtectionFault0(pVCpu);
8796 }
8797 }
8798
8799 /* Feature control MSR's LOCK and VMXON bits. */
8800 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8801 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8802 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8803 { /* likely */ }
8804 else
8805 {
8806 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8807 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8808 return iemRaiseGeneralProtectionFault0(pVCpu);
8809 }
8810
8811 /* Get the VMXON pointer from the location specified by the source memory operand. */
8812 RTGCPHYS GCPhysVmxon;
8813 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8814 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8815 { /* likely */ }
8816 else
8817 {
8818 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8819 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8820 return rcStrict;
8821 }
8822
8823 /* VMXON region pointer alignment. */
8824 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8825 { /* likely */ }
8826 else
8827 {
8828 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8829 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8830 iemVmxVmFailInvalid(pVCpu);
8831 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8832 return VINF_SUCCESS;
8833 }
8834
8835 /* VMXON physical-address width limits. */
8836 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8837 { /* likely */ }
8838 else
8839 {
8840 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8841 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8842 iemVmxVmFailInvalid(pVCpu);
8843 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8844 return VINF_SUCCESS;
8845 }
8846
8847 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8848 restriction imposed by our implementation. */
8849 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8850 { /* likely */ }
8851 else
8852 {
8853 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8854 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8855 iemVmxVmFailInvalid(pVCpu);
8856 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8857 return VINF_SUCCESS;
8858 }
8859
8860 /* Read the VMCS revision ID from the VMXON region. */
8861 VMXVMCSREVID VmcsRevId;
8862 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8863 if (RT_SUCCESS(rc))
8864 { /* likely */ }
8865 else
8866 {
8867 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8869 return rc;
8870 }
8871
8872 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8873 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8874 { /* likely */ }
8875 else
8876 {
8877 /* Revision ID mismatch. */
8878 if (!VmcsRevId.n.fIsShadowVmcs)
8879 {
8880 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8881 VmcsRevId.n.u31RevisionId));
8882 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8883 iemVmxVmFailInvalid(pVCpu);
8884 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8885 return VINF_SUCCESS;
8886 }
8887
8888 /* Shadow VMCS disallowed. */
8889 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8890 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8891 iemVmxVmFailInvalid(pVCpu);
8892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8893 return VINF_SUCCESS;
8894 }
8895
8896 /*
8897 * Record that we're in VMX operation, block INIT, block and disable A20M.
8898 */
8899 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8900 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8901 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8902
8903 /* Clear address-range monitoring. */
8904 EMMonitorWaitClear(pVCpu);
8905 /** @todo NSTVMX: Intel PT. */
8906
8907 iemVmxVmSucceed(pVCpu);
8908 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8909 return VINF_SUCCESS;
8910 }
8911 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8912 {
8913 /* Nested-guest intercept. */
8914 if (pExitInfo)
8915 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8916 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8917 }
8918
8919 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8920
8921 /* CPL. */
8922 if (pVCpu->iem.s.uCpl > 0)
8923 {
8924 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8925 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8926 return iemRaiseGeneralProtectionFault0(pVCpu);
8927 }
8928
8929 /* VMXON when already in VMX root mode. */
8930 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8931 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8932 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8933 return VINF_SUCCESS;
8934}
8935
8936
8937/**
8938 * Implements 'VMXOFF'.
8939 *
8940 * @remarks Common VMX instruction checks are already expected to by the caller,
8941 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8942 */
8943IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8944{
8945 /* Nested-guest intercept. */
8946 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8947 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8948
8949 /* CPL. */
8950 if (pVCpu->iem.s.uCpl == 0)
8951 { /* likely */ }
8952 else
8953 {
8954 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8956 return iemRaiseGeneralProtectionFault0(pVCpu);
8957 }
8958
8959 /* Dual monitor treatment of SMIs and SMM. */
8960 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8961 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8962 { /* likely */ }
8963 else
8964 {
8965 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8966 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8967 return VINF_SUCCESS;
8968 }
8969
8970 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8971 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8972 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8973
8974 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8975 { /** @todo NSTVMX: Unblock SMI. */ }
8976
8977 EMMonitorWaitClear(pVCpu);
8978 /** @todo NSTVMX: Unblock and enable A20M. */
8979
8980 iemVmxVmSucceed(pVCpu);
8981 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8982 return VINF_SUCCESS;
8983}
8984
8985
8986/**
8987 * Implements 'VMXON'.
8988 */
8989IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8990{
8991 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8992}
8993
8994
8995/**
8996 * Implements 'VMLAUNCH'.
8997 */
8998IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8999{
9000 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9001}
9002
9003
9004/**
9005 * Implements 'VMRESUME'.
9006 */
9007IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9008{
9009 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9010}
9011
9012
9013/**
9014 * Implements 'VMPTRLD'.
9015 */
9016IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9017{
9018 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9019}
9020
9021
9022/**
9023 * Implements 'VMPTRST'.
9024 */
9025IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9026{
9027 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9028}
9029
9030
9031/**
9032 * Implements 'VMCLEAR'.
9033 */
9034IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9035{
9036 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9037}
9038
9039
9040/**
9041 * Implements 'VMWRITE' register.
9042 */
9043IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9044{
9045 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9046}
9047
9048
9049/**
9050 * Implements 'VMWRITE' memory.
9051 */
9052IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9053{
9054 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9055}
9056
9057
9058/**
9059 * Implements 'VMREAD' register (64-bit).
9060 */
9061IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9062{
9063 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9064}
9065
9066
9067/**
9068 * Implements 'VMREAD' register (32-bit).
9069 */
9070IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9071{
9072 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9073}
9074
9075
9076/**
9077 * Implements 'VMREAD' memory, 64-bit register.
9078 */
9079IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9080{
9081 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9082}
9083
9084
9085/**
9086 * Implements 'VMREAD' memory, 32-bit register.
9087 */
9088IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9089{
9090 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9091}
9092
9093
9094/**
9095 * Implements 'INVVPID'.
9096 */
9097IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9098{
9099 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9100}
9101
9102
9103/**
9104 * Implements VMX's implementation of PAUSE.
9105 */
9106IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9107{
9108 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9109 {
9110 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9111 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9112 return rcStrict;
9113 }
9114
9115 /*
9116 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9117 * a VM-exit, the instruction operates normally.
9118 */
9119 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9120 return VINF_SUCCESS;
9121}
9122
9123#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9124
9125
9126/**
9127 * Implements 'VMCALL'.
9128 */
9129IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9130{
9131#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9132 /* Nested-guest intercept. */
9133 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9134 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9135#endif
9136
9137 /* Join forces with vmmcall. */
9138 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9139}
9140
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