VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79073

Last change on this file since 79073 was 79059, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Todo.
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File size: 360.2 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79059 2019-06-10 11:30:19Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELDENC.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64FieldEnc The VMCS field encoding.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64FieldEnc)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the Exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param u64ExitQual The Exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = u64ExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitIntInfo The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
1984 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
1986 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1987 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1988 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1989 CPUMSetGuestCR0(pVCpu, uValidCr0);
1990 }
1991
1992 /* CR4. */
1993 {
1994 /* CR4 MB1 bits are not modified. */
1995 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1996 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1997 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1998 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1999 if (fHostInLongMode)
2000 uValidCr4 |= X86_CR4_PAE;
2001 else
2002 uValidCr4 &= ~X86_CR4_PCIDE;
2003 CPUMSetGuestCR4(pVCpu, uValidCr4);
2004 }
2005
2006 /* CR3 (host value validated while checking host-state during VM-entry). */
2007 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2008
2009 /* DR7. */
2010 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2011
2012 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2013
2014 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2015 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2016 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2017 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2018
2019 /* FS, GS bases are loaded later while we load host segment registers. */
2020
2021 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2022 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2023 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2024 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2025 {
2026 if (fHostInLongMode)
2027 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2028 else
2029 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2030 }
2031
2032 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2033
2034 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2035 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2036 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2037
2038 /* We don't support IA32_BNDCFGS MSR yet. */
2039}
2040
2041
2042/**
2043 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2044 *
2045 * @param pVCpu The cross context virtual CPU structure.
2046 */
2047IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2048{
2049 /*
2050 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2051 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2052 *
2053 * Warning! Be careful to not touch fields that are reserved by VT-x,
2054 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2055 */
2056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2057 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2058
2059 /* CS, SS, ES, DS, FS, GS. */
2060 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2061 {
2062 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2063 bool const fUnusable = RT_BOOL(HostSel == 0);
2064 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2065
2066 /* Selector. */
2067 pSelReg->Sel = HostSel;
2068 pSelReg->ValidSel = HostSel;
2069 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2070
2071 /* Limit. */
2072 pSelReg->u32Limit = 0xffffffff;
2073
2074 /* Base. */
2075 pSelReg->u64Base = 0;
2076
2077 /* Attributes. */
2078 if (iSegReg == X86_SREG_CS)
2079 {
2080 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2081 pSelReg->Attr.n.u1DescType = 1;
2082 pSelReg->Attr.n.u2Dpl = 0;
2083 pSelReg->Attr.n.u1Present = 1;
2084 pSelReg->Attr.n.u1Long = fHostInLongMode;
2085 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2086 pSelReg->Attr.n.u1Granularity = 1;
2087 Assert(!pSelReg->Attr.n.u1Unusable);
2088 Assert(!fUnusable);
2089 }
2090 else
2091 {
2092 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2093 pSelReg->Attr.n.u1DescType = 1;
2094 pSelReg->Attr.n.u2Dpl = 0;
2095 pSelReg->Attr.n.u1Present = 1;
2096 pSelReg->Attr.n.u1DefBig = 1;
2097 pSelReg->Attr.n.u1Granularity = 1;
2098 pSelReg->Attr.n.u1Unusable = fUnusable;
2099 }
2100 }
2101
2102 /* FS base. */
2103 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2104 || fHostInLongMode)
2105 {
2106 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2107 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2108 }
2109
2110 /* GS base. */
2111 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2112 || fHostInLongMode)
2113 {
2114 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2115 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2116 }
2117
2118 /* TR. */
2119 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2120 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2121 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2122 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2123 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2124 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2125 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2126 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2127 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2128 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2132
2133 /* LDTR (Warning! do not touch the base and limits here). */
2134 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2135 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2136 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2137 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2138
2139 /* GDTR. */
2140 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2141 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2142 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2143
2144 /* IDTR.*/
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2146 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2147 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2148}
2149
2150
2151/**
2152 * Checks host PDPTes as part of VM-exit.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param uExitReason The VM-exit reason (for logging purposes).
2156 */
2157IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2158{
2159 /*
2160 * Check host PDPTEs.
2161 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2162 */
2163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2164 const char *const pszFailure = "VMX-abort";
2165 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2166
2167 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2168 && !fHostInLongMode)
2169 {
2170 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2171 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2172 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2173 if (RT_SUCCESS(rc))
2174 {
2175 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2176 {
2177 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2178 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2179 { /* likely */ }
2180 else
2181 {
2182 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2183 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2184 }
2185 }
2186 }
2187 else
2188 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2189 }
2190
2191 NOREF(pszFailure);
2192 NOREF(uExitReason);
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2199 *
2200 * @returns VBox status code.
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param pszInstr The VMX instruction name (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Load host MSRs.
2208 * See Intel spec. 27.6 "Loading MSRs".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212
2213 /*
2214 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2215 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2216 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2217 */
2218 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2219 if (!cMsrs)
2220 return VINF_SUCCESS;
2221
2222 /*
2223 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2224 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2225 * implementation causes a VMX-abort followed by a triple-fault.
2226 */
2227 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2228 if (fIsMsrCountValid)
2229 { /* likely */ }
2230 else
2231 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2232
2233 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2234 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2235 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2236 if (RT_SUCCESS(rc))
2237 {
2238 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2239 Assert(pMsr);
2240 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2241 {
2242 if ( !pMsr->u32Reserved
2243 && pMsr->u32Msr != MSR_K8_FS_BASE
2244 && pMsr->u32Msr != MSR_K8_GS_BASE
2245 && pMsr->u32Msr != MSR_K6_EFER
2246 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2247 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2248 {
2249 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2250 if (rcStrict == VINF_SUCCESS)
2251 continue;
2252
2253 /*
2254 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2255 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2256 * recording the MSR index in the auxiliary info. field and indicated further by our
2257 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2258 * if possible, or come up with a better, generic solution.
2259 */
2260 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2261 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2262 ? kVmxVDiag_Vmexit_MsrLoadRing3
2263 : kVmxVDiag_Vmexit_MsrLoad;
2264 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2265 }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2268 }
2269 }
2270 else
2271 {
2272 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2273 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2274 }
2275
2276 NOREF(uExitReason);
2277 NOREF(pszFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Loads the host state as part of VM-exit.
2284 *
2285 * @returns Strict VBox status code.
2286 * @param pVCpu The cross context virtual CPU structure.
2287 * @param uExitReason The VM-exit reason (for logging purposes).
2288 */
2289IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2290{
2291 /*
2292 * Load host state.
2293 * See Intel spec. 27.5 "Loading Host State".
2294 */
2295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2296 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2297
2298 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2299 if ( CPUMIsGuestInLongMode(pVCpu)
2300 && !fHostInLongMode)
2301 {
2302 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2303 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2304 }
2305
2306 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2307 iemVmxVmexitLoadHostSegRegs(pVCpu);
2308
2309 /*
2310 * Load host RIP, RSP and RFLAGS.
2311 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2312 */
2313 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2314 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2315 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2316
2317 /* Clear address range monitoring. */
2318 EMMonitorWaitClear(pVCpu);
2319
2320 /* Perform the VMX transition (PGM updates). */
2321 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2322 if (rcStrict == VINF_SUCCESS)
2323 {
2324 /* Check host PDPTEs (only when we've fully switched page tables_. */
2325 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2326 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2327 if (RT_FAILURE(rc))
2328 {
2329 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2330 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2331 }
2332 }
2333 else if (RT_SUCCESS(rcStrict))
2334 {
2335 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2336 uExitReason));
2337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2338 }
2339 else
2340 {
2341 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2342 return VBOXSTRICTRC_VAL(rcStrict);
2343 }
2344
2345 Assert(rcStrict == VINF_SUCCESS);
2346
2347 /* Load MSRs from the VM-exit auto-load MSR area. */
2348 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2349 if (RT_FAILURE(rc))
2350 {
2351 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2352 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2353 }
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/**
2359 * Gets VM-exit instruction information along with any displacement for an
2360 * instruction VM-exit.
2361 *
2362 * @returns The VM-exit instruction information.
2363 * @param pVCpu The cross context virtual CPU structure.
2364 * @param uExitReason The VM-exit reason.
2365 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2366 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2367 * NULL.
2368 */
2369IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2370{
2371 RTGCPTR GCPtrDisp;
2372 VMXEXITINSTRINFO ExitInstrInfo;
2373 ExitInstrInfo.u = 0;
2374
2375 /*
2376 * Get and parse the ModR/M byte from our decoded opcodes.
2377 */
2378 uint8_t bRm;
2379 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2380 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2381 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2382 {
2383 /*
2384 * ModR/M indicates register addressing.
2385 *
2386 * The primary/secondary register operands are reported in the iReg1 or iReg2
2387 * fields depending on whether it is a read/write form.
2388 */
2389 uint8_t idxReg1;
2390 uint8_t idxReg2;
2391 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2392 {
2393 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2394 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2395 }
2396 else
2397 {
2398 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2399 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2400 }
2401 ExitInstrInfo.All.u2Scaling = 0;
2402 ExitInstrInfo.All.iReg1 = idxReg1;
2403 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2404 ExitInstrInfo.All.fIsRegOperand = 1;
2405 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2406 ExitInstrInfo.All.iSegReg = 0;
2407 ExitInstrInfo.All.iIdxReg = 0;
2408 ExitInstrInfo.All.fIdxRegInvalid = 1;
2409 ExitInstrInfo.All.iBaseReg = 0;
2410 ExitInstrInfo.All.fBaseRegInvalid = 1;
2411 ExitInstrInfo.All.iReg2 = idxReg2;
2412
2413 /* Displacement not applicable for register addressing. */
2414 GCPtrDisp = 0;
2415 }
2416 else
2417 {
2418 /*
2419 * ModR/M indicates memory addressing.
2420 */
2421 uint8_t uScale = 0;
2422 bool fBaseRegValid = false;
2423 bool fIdxRegValid = false;
2424 uint8_t iBaseReg = 0;
2425 uint8_t iIdxReg = 0;
2426 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2427 {
2428 /*
2429 * Parse the ModR/M, displacement for 16-bit addressing mode.
2430 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2431 */
2432 uint16_t u16Disp = 0;
2433 uint8_t const offDisp = offModRm + sizeof(bRm);
2434 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2435 {
2436 /* Displacement without any registers. */
2437 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2438 }
2439 else
2440 {
2441 /* Register (index and base). */
2442 switch (bRm & X86_MODRM_RM_MASK)
2443 {
2444 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2445 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2446 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2447 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2448 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2449 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2450 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2451 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2452 }
2453
2454 /* Register + displacement. */
2455 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2456 {
2457 case 0: break;
2458 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2459 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2460 default:
2461 {
2462 /* Register addressing, handled at the beginning. */
2463 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2464 break;
2465 }
2466 }
2467 }
2468
2469 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2470 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2471 }
2472 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2473 {
2474 /*
2475 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2476 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2477 */
2478 uint32_t u32Disp = 0;
2479 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2480 {
2481 /* Displacement without any registers. */
2482 uint8_t const offDisp = offModRm + sizeof(bRm);
2483 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2484 }
2485 else
2486 {
2487 /* Register (and perhaps scale, index and base). */
2488 uint8_t offDisp = offModRm + sizeof(bRm);
2489 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2490 if (iBaseReg == 4)
2491 {
2492 /* An SIB byte follows the ModR/M byte, parse it. */
2493 uint8_t bSib;
2494 uint8_t const offSib = offModRm + sizeof(bRm);
2495 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2496
2497 /* A displacement may follow SIB, update its offset. */
2498 offDisp += sizeof(bSib);
2499
2500 /* Get the scale. */
2501 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2502
2503 /* Get the index register. */
2504 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2505 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2506
2507 /* Get the base register. */
2508 iBaseReg = bSib & X86_SIB_BASE_MASK;
2509 fBaseRegValid = true;
2510 if (iBaseReg == 5)
2511 {
2512 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2513 {
2514 /* Mod is 0 implies a 32-bit displacement with no base. */
2515 fBaseRegValid = false;
2516 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2517 }
2518 else
2519 {
2520 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2521 iBaseReg = X86_GREG_xBP;
2522 }
2523 }
2524 }
2525
2526 /* Register + displacement. */
2527 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2528 {
2529 case 0: /* Handled above */ break;
2530 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2531 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2532 default:
2533 {
2534 /* Register addressing, handled at the beginning. */
2535 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2536 break;
2537 }
2538 }
2539 }
2540
2541 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2542 }
2543 else
2544 {
2545 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2546
2547 /*
2548 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2549 * See Intel instruction spec. 2.2 "IA-32e Mode".
2550 */
2551 uint64_t u64Disp = 0;
2552 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2553 if (fRipRelativeAddr)
2554 {
2555 /*
2556 * RIP-relative addressing mode.
2557 *
2558 * The displacement is 32-bit signed implying an offset range of +/-2G.
2559 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2560 */
2561 uint8_t const offDisp = offModRm + sizeof(bRm);
2562 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2563 }
2564 else
2565 {
2566 uint8_t offDisp = offModRm + sizeof(bRm);
2567
2568 /*
2569 * Register (and perhaps scale, index and base).
2570 *
2571 * REX.B extends the most-significant bit of the base register. However, REX.B
2572 * is ignored while determining whether an SIB follows the opcode. Hence, we
2573 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2574 *
2575 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2576 */
2577 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2578 if (iBaseReg == 4)
2579 {
2580 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2581 uint8_t bSib;
2582 uint8_t const offSib = offModRm + sizeof(bRm);
2583 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2584
2585 /* Displacement may follow SIB, update its offset. */
2586 offDisp += sizeof(bSib);
2587
2588 /* Get the scale. */
2589 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2590
2591 /* Get the index. */
2592 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2593 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2594
2595 /* Get the base. */
2596 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2597 fBaseRegValid = true;
2598 if (iBaseReg == 5)
2599 {
2600 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2601 {
2602 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2603 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2604 }
2605 else
2606 {
2607 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2608 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2609 }
2610 }
2611 }
2612 iBaseReg |= pVCpu->iem.s.uRexB;
2613
2614 /* Register + displacement. */
2615 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2616 {
2617 case 0: /* Handled above */ break;
2618 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2619 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2620 default:
2621 {
2622 /* Register addressing, handled at the beginning. */
2623 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2624 break;
2625 }
2626 }
2627 }
2628
2629 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2630 }
2631
2632 /*
2633 * The primary or secondary register operand is reported in iReg2 depending
2634 * on whether the primary operand is in read/write form.
2635 */
2636 uint8_t idxReg2;
2637 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2638 {
2639 idxReg2 = bRm & X86_MODRM_RM_MASK;
2640 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2641 idxReg2 |= pVCpu->iem.s.uRexB;
2642 }
2643 else
2644 {
2645 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2646 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2647 idxReg2 |= pVCpu->iem.s.uRexReg;
2648 }
2649 ExitInstrInfo.All.u2Scaling = uScale;
2650 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2651 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2652 ExitInstrInfo.All.fIsRegOperand = 0;
2653 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2654 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2655 ExitInstrInfo.All.iIdxReg = iIdxReg;
2656 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2657 ExitInstrInfo.All.iBaseReg = iBaseReg;
2658 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2659 ExitInstrInfo.All.iReg2 = idxReg2;
2660 }
2661
2662 /*
2663 * Handle exceptions to the norm for certain instructions.
2664 * (e.g. some instructions convey an instruction identity in place of iReg2).
2665 */
2666 switch (uExitReason)
2667 {
2668 case VMX_EXIT_GDTR_IDTR_ACCESS:
2669 {
2670 Assert(VMXINSTRID_IS_VALID(uInstrId));
2671 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2672 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2673 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2674 break;
2675 }
2676
2677 case VMX_EXIT_LDTR_TR_ACCESS:
2678 {
2679 Assert(VMXINSTRID_IS_VALID(uInstrId));
2680 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2681 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2682 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2683 break;
2684 }
2685
2686 case VMX_EXIT_RDRAND:
2687 case VMX_EXIT_RDSEED:
2688 {
2689 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2690 break;
2691 }
2692 }
2693
2694 /* Update displacement and return the constructed VM-exit instruction information field. */
2695 if (pGCPtrDisp)
2696 *pGCPtrDisp = GCPtrDisp;
2697
2698 return ExitInstrInfo.u;
2699}
2700
2701
2702/**
2703 * VMX VM-exit handler.
2704 *
2705 * @returns Strict VBox status code.
2706 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2707 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2708 * triple-fault.
2709 *
2710 * @param pVCpu The cross context virtual CPU structure.
2711 * @param uExitReason The VM-exit reason.
2712 * @param u64ExitQual The Exit qualification.
2713 */
2714IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2715{
2716# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2717 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2718 return VINF_EM_RAW_EMULATE_INSTR;
2719# else
2720 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2721 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2722 | CPUMCTX_EXTRN_EFER /* MSRs */
2723 | CPUMCTX_EXTRN_SYSENTER_MSRS
2724 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2725 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2726 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2727 | CPUMCTX_EXTRN_TR /* Task register */
2728 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2729 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2730
2731 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2732 Assert(pVmcs);
2733
2734 /* Ensure VM-entry interruption information valid bit isn't set. */
2735 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2736
2737 /*
2738 * Update the VM-exit reason and Exit qualification.
2739 * Other VMCS read-only data fields are expected to be updated by the caller already.
2740 */
2741 pVmcs->u32RoExitReason = uExitReason;
2742 pVmcs->u64RoExitQual.u = u64ExitQual;
2743 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2744 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2745
2746 /*
2747 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2748 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2749 */
2750 {
2751 uint8_t uVector;
2752 uint32_t fFlags;
2753 uint32_t uErrCode;
2754 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2755 if (fInEventDelivery)
2756 {
2757 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2758 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2759 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2760 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2761 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2762 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2763 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2764 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2765 }
2766 }
2767
2768 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2769 Assert(pVmcs->u64RoIoRcx.u == 0);
2770 Assert(pVmcs->u64RoIoRsi.u == 0);
2771 Assert(pVmcs->u64RoIoRdi.u == 0);
2772 Assert(pVmcs->u64RoIoRip.u == 0);
2773
2774 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2775 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2776 {
2777 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2778 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2779 }
2780
2781 /*
2782 * Save the guest state back into the VMCS.
2783 * We only need to save the state when the VM-entry was successful.
2784 */
2785 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2786 if (!fVmentryFailed)
2787 {
2788 /*
2789 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2790 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2791 *
2792 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2793 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2794 * as guest-CPU state would not been modified. Hence for now, we do this only when
2795 * the VM-entry succeeded.
2796 */
2797 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2798 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2799 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2800 {
2801 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2802 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2803 else
2804 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2805 }
2806
2807 /*
2808 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2809 * occurs in enclave mode/SMM which we don't support yet.
2810 *
2811 * If we ever add support for it, we can pass just the lower bits to the functions
2812 * below, till then an assert should suffice.
2813 */
2814 Assert(!RT_HI_U16(uExitReason));
2815
2816 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2817 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2818 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2819 if (RT_SUCCESS(rc))
2820 { /* likely */ }
2821 else
2822 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2823
2824 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2825 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2826 }
2827 else
2828 {
2829 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2830 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2831 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2832 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2833 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2834 }
2835
2836 /*
2837 * Clear any pending VMX nested-guest force-flags.
2838 * These force-flags have no effect on guest execution and will
2839 * be re-evaluated and setup on the next nested-guest VM-entry.
2840 */
2841 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2842 | VMCPU_FF_VMX_MTF
2843 | VMCPU_FF_VMX_APIC_WRITE
2844 | VMCPU_FF_VMX_INT_WINDOW
2845 | VMCPU_FF_VMX_NMI_WINDOW);
2846
2847 /* Restore the host (outer guest) state. */
2848 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2849 if (RT_SUCCESS(rcStrict))
2850 {
2851 Assert(rcStrict == VINF_SUCCESS);
2852 rcStrict = VINF_VMX_VMEXIT;
2853 }
2854 else
2855 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2856
2857 /* Notify HM that we've completed the VM-exit. */
2858 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2859
2860 /* We're no longer in nested-guest execution mode. */
2861 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2862
2863# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2864 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2865 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2866 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2867 if (rcSched != VINF_SUCCESS)
2868 iemSetPassUpStatus(pVCpu, rcSched);
2869# endif
2870 return rcStrict;
2871# endif
2872}
2873
2874
2875/**
2876 * VMX VM-exit handler for VM-exits due to instruction execution.
2877 *
2878 * This is intended for instructions where the caller provides all the relevant
2879 * VM-exit information.
2880 *
2881 * @returns Strict VBox status code.
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param pExitInfo Pointer to the VM-exit information.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2886{
2887 /*
2888 * For instructions where any of the following fields are not applicable:
2889 * - Exit qualification must be cleared.
2890 * - VM-exit instruction info. is undefined.
2891 * - Guest-linear address is undefined.
2892 * - Guest-physical address is undefined.
2893 *
2894 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2895 * instruction execution. For VM-exits that are not due to instruction execution this
2896 * field is undefined.
2897 *
2898 * In our implementation in IEM, all undefined fields are generally cleared. However,
2899 * if the caller supplies information (from say the physical CPU directly) it is
2900 * then possible that the undefined fields are not cleared.
2901 *
2902 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2903 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2904 */
2905 Assert(pExitInfo);
2906 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2907 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2908 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2909
2910 /* Update all the relevant fields from the VM-exit instruction information struct. */
2911 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2912 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2913 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2914 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2915
2916 /* Perform the VM-exit. */
2917 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2918}
2919
2920
2921/**
2922 * VMX VM-exit handler for VM-exits due to instruction execution.
2923 *
2924 * This is intended for instructions that only provide the VM-exit instruction
2925 * length.
2926 *
2927 * @param pVCpu The cross context virtual CPU structure.
2928 * @param uExitReason The VM-exit reason.
2929 * @param cbInstr The instruction length in bytes.
2930 */
2931IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2932{
2933 VMXVEXITINFO ExitInfo;
2934 RT_ZERO(ExitInfo);
2935 ExitInfo.uReason = uExitReason;
2936 ExitInfo.cbInstr = cbInstr;
2937
2938#ifdef VBOX_STRICT
2939 /*
2940 * To prevent us from shooting ourselves in the foot.
2941 * The follow instructions should convey more than just the instruction length.
2942 */
2943 switch (uExitReason)
2944 {
2945 case VMX_EXIT_INVEPT:
2946 case VMX_EXIT_INVPCID:
2947 case VMX_EXIT_LDTR_TR_ACCESS:
2948 case VMX_EXIT_GDTR_IDTR_ACCESS:
2949 case VMX_EXIT_VMCLEAR:
2950 case VMX_EXIT_VMPTRLD:
2951 case VMX_EXIT_VMPTRST:
2952 case VMX_EXIT_VMREAD:
2953 case VMX_EXIT_VMWRITE:
2954 case VMX_EXIT_VMXON:
2955 case VMX_EXIT_XRSTORS:
2956 case VMX_EXIT_XSAVES:
2957 case VMX_EXIT_RDRAND:
2958 case VMX_EXIT_RDSEED:
2959 case VMX_EXIT_IO_INSTR:
2960 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2961 break;
2962 }
2963#endif
2964
2965 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2966}
2967
2968
2969/**
2970 * VMX VM-exit handler for VM-exits due to instruction execution.
2971 *
2972 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2973 * instruction information and Exit qualification fields.
2974 *
2975 * @param pVCpu The cross context virtual CPU structure.
2976 * @param uExitReason The VM-exit reason.
2977 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2978 * @param cbInstr The instruction length in bytes.
2979 *
2980 * @remarks Do not use this for INS/OUTS instruction.
2981 */
2982IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2983{
2984 VMXVEXITINFO ExitInfo;
2985 RT_ZERO(ExitInfo);
2986 ExitInfo.uReason = uExitReason;
2987 ExitInfo.cbInstr = cbInstr;
2988
2989 /*
2990 * Update the Exit qualification field with displacement bytes.
2991 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2992 */
2993 switch (uExitReason)
2994 {
2995 case VMX_EXIT_INVEPT:
2996 case VMX_EXIT_INVPCID:
2997 case VMX_EXIT_INVVPID:
2998 case VMX_EXIT_LDTR_TR_ACCESS:
2999 case VMX_EXIT_GDTR_IDTR_ACCESS:
3000 case VMX_EXIT_VMCLEAR:
3001 case VMX_EXIT_VMPTRLD:
3002 case VMX_EXIT_VMPTRST:
3003 case VMX_EXIT_VMREAD:
3004 case VMX_EXIT_VMWRITE:
3005 case VMX_EXIT_VMXON:
3006 case VMX_EXIT_XRSTORS:
3007 case VMX_EXIT_XSAVES:
3008 case VMX_EXIT_RDRAND:
3009 case VMX_EXIT_RDSEED:
3010 {
3011 /* Construct the VM-exit instruction information. */
3012 RTGCPTR GCPtrDisp;
3013 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3014
3015 /* Update the VM-exit instruction information. */
3016 ExitInfo.InstrInfo.u = uInstrInfo;
3017
3018 /* Update the Exit qualification. */
3019 ExitInfo.u64Qual = GCPtrDisp;
3020 break;
3021 }
3022
3023 default:
3024 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3025 break;
3026 }
3027
3028 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3029}
3030
3031
3032/**
3033 * VMX VM-exit handler for VM-exits due to INVLPG.
3034 *
3035 * @returns Strict VBox status code.
3036 * @param pVCpu The cross context virtual CPU structure.
3037 * @param GCPtrPage The guest-linear address of the page being invalidated.
3038 * @param cbInstr The instruction length in bytes.
3039 */
3040IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3041{
3042 VMXVEXITINFO ExitInfo;
3043 RT_ZERO(ExitInfo);
3044 ExitInfo.uReason = VMX_EXIT_INVLPG;
3045 ExitInfo.cbInstr = cbInstr;
3046 ExitInfo.u64Qual = GCPtrPage;
3047 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3048
3049 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3050}
3051
3052
3053/**
3054 * VMX VM-exit handler for VM-exits due to LMSW.
3055 *
3056 * @returns Strict VBox status code.
3057 * @param pVCpu The cross context virtual CPU structure.
3058 * @param uGuestCr0 The current guest CR0.
3059 * @param pu16NewMsw The machine-status word specified in LMSW's source
3060 * operand. This will be updated depending on the VMX
3061 * guest/host CR0 mask if LMSW is not intercepted.
3062 * @param GCPtrEffDst The guest-linear address of the source operand in case
3063 * of a memory operand. For register operand, pass
3064 * NIL_RTGCPTR.
3065 * @param cbInstr The instruction length in bytes.
3066 */
3067IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3068 uint8_t cbInstr)
3069{
3070 Assert(pu16NewMsw);
3071
3072 uint16_t const uNewMsw = *pu16NewMsw;
3073 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3074 {
3075 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3076
3077 VMXVEXITINFO ExitInfo;
3078 RT_ZERO(ExitInfo);
3079 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3080 ExitInfo.cbInstr = cbInstr;
3081
3082 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3083 if (fMemOperand)
3084 {
3085 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3086 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3087 }
3088
3089 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3090 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3093
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096
3097 /*
3098 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3099 * CR0 guest/host mask must be left unmodified.
3100 *
3101 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3102 */
3103 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3104 Assert(pVmcs);
3105 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3106 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3107 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3108
3109 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3110}
3111
3112
3113/**
3114 * VMX VM-exit handler for VM-exits due to CLTS.
3115 *
3116 * @returns Strict VBox status code.
3117 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3118 * VM-exit but must not modify the guest CR0.TS bit.
3119 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3120 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3121 * CR0 fixed bits in VMX operation).
3122 * @param pVCpu The cross context virtual CPU structure.
3123 * @param cbInstr The instruction length in bytes.
3124 */
3125IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3126{
3127 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3128 Assert(pVmcs);
3129
3130 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3131 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3132
3133 /*
3134 * If CR0.TS is owned by the host:
3135 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3136 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3137 * CLTS instruction completes without clearing CR0.TS.
3138 *
3139 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3140 */
3141 if (fGstHostMask & X86_CR0_TS)
3142 {
3143 if (fReadShadow & X86_CR0_TS)
3144 {
3145 Log2(("clts: Guest intercept -> VM-exit\n"));
3146
3147 VMXVEXITINFO ExitInfo;
3148 RT_ZERO(ExitInfo);
3149 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3150 ExitInfo.cbInstr = cbInstr;
3151 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3152 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3153 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3154 }
3155
3156 return VINF_VMX_MODIFIES_BEHAVIOR;
3157 }
3158
3159 /*
3160 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3161 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3162 */
3163 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3164}
3165
3166
3167/**
3168 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3169 * (CR0/CR4 write).
3170 *
3171 * @returns Strict VBox status code.
3172 * @param pVCpu The cross context virtual CPU structure.
3173 * @param iCrReg The control register (either CR0 or CR4).
3174 * @param uGuestCrX The current guest CR0/CR4.
3175 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3176 * if no VM-exit is caused.
3177 * @param iGReg The general register from which the CR0/CR4 value is
3178 * being loaded.
3179 * @param cbInstr The instruction length in bytes.
3180 */
3181IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3182 uint8_t cbInstr)
3183{
3184 Assert(puNewCrX);
3185 Assert(iCrReg == 0 || iCrReg == 4);
3186 Assert(iGReg < X86_GREG_COUNT);
3187
3188 uint64_t const uNewCrX = *puNewCrX;
3189 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3190 {
3191 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3192
3193 VMXVEXITINFO ExitInfo;
3194 RT_ZERO(ExitInfo);
3195 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3196 ExitInfo.cbInstr = cbInstr;
3197 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3198 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3200 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3201 }
3202
3203 /*
3204 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3205 * must not be modified the instruction.
3206 *
3207 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3208 */
3209 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3210 Assert(pVmcs);
3211 uint64_t uGuestCrX;
3212 uint64_t fGstHostMask;
3213 if (iCrReg == 0)
3214 {
3215 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3216 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3217 fGstHostMask = pVmcs->u64Cr0Mask.u;
3218 }
3219 else
3220 {
3221 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3222 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3223 fGstHostMask = pVmcs->u64Cr4Mask.u;
3224 }
3225
3226 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3227 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3228}
3229
3230
3231/**
3232 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3233 *
3234 * @returns VBox strict status code.
3235 * @param pVCpu The cross context virtual CPU structure.
3236 * @param iGReg The general register to which the CR3 value is being stored.
3237 * @param cbInstr The instruction length in bytes.
3238 */
3239IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3240{
3241 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3242 Assert(pVmcs);
3243 Assert(iGReg < X86_GREG_COUNT);
3244 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3245
3246 /*
3247 * If the CR3-store exiting control is set, we must cause a VM-exit.
3248 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3249 */
3250 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3251 {
3252 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3253
3254 VMXVEXITINFO ExitInfo;
3255 RT_ZERO(ExitInfo);
3256 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3257 ExitInfo.cbInstr = cbInstr;
3258 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3259 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3260 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3261 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3262 }
3263
3264 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3265}
3266
3267
3268/**
3269 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3270 *
3271 * @returns VBox strict status code.
3272 * @param pVCpu The cross context virtual CPU structure.
3273 * @param uNewCr3 The new CR3 value.
3274 * @param iGReg The general register from which the CR3 value is being
3275 * loaded.
3276 * @param cbInstr The instruction length in bytes.
3277 */
3278IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3279{
3280 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3281 Assert(pVmcs);
3282 Assert(iGReg < X86_GREG_COUNT);
3283
3284 /*
3285 * If the CR3-load exiting control is set and the new CR3 value does not
3286 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3287 *
3288 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3289 */
3290 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3291 {
3292 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3293 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3294
3295 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3296 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3297 if (!fIntercept)
3298 {
3299 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3300 {
3301 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3302 if (uNewCr3 != uCr3TargetValue)
3303 {
3304 fIntercept = true;
3305 break;
3306 }
3307 }
3308 }
3309
3310 if (fIntercept)
3311 {
3312 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3313
3314 VMXVEXITINFO ExitInfo;
3315 RT_ZERO(ExitInfo);
3316 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3317 ExitInfo.cbInstr = cbInstr;
3318 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3319 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3321 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3322 }
3323 }
3324
3325 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3326}
3327
3328
3329/**
3330 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3331 *
3332 * @returns VBox strict status code.
3333 * @param pVCpu The cross context virtual CPU structure.
3334 * @param iGReg The general register to which the CR8 value is being stored.
3335 * @param cbInstr The instruction length in bytes.
3336 */
3337IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3338{
3339 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3340 Assert(pVmcs);
3341 Assert(iGReg < X86_GREG_COUNT);
3342
3343 /*
3344 * If the CR8-store exiting control is set, we must cause a VM-exit.
3345 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3346 */
3347 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3348 {
3349 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3350
3351 VMXVEXITINFO ExitInfo;
3352 RT_ZERO(ExitInfo);
3353 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3354 ExitInfo.cbInstr = cbInstr;
3355 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3356 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3357 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3358 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3359 }
3360
3361 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3362}
3363
3364
3365/**
3366 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3367 *
3368 * @returns VBox strict status code.
3369 * @param pVCpu The cross context virtual CPU structure.
3370 * @param iGReg The general register from which the CR8 value is being
3371 * loaded.
3372 * @param cbInstr The instruction length in bytes.
3373 */
3374IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3375{
3376 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3377 Assert(pVmcs);
3378 Assert(iGReg < X86_GREG_COUNT);
3379
3380 /*
3381 * If the CR8-load exiting control is set, we must cause a VM-exit.
3382 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3383 */
3384 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3385 {
3386 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3387
3388 VMXVEXITINFO ExitInfo;
3389 RT_ZERO(ExitInfo);
3390 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3391 ExitInfo.cbInstr = cbInstr;
3392 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3393 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3394 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3395 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3396 }
3397
3398 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3399}
3400
3401
3402/**
3403 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3404 * GReg,DRx' (DRx read).
3405 *
3406 * @returns VBox strict status code.
3407 * @param pVCpu The cross context virtual CPU structure.
3408 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3409 * VMXINSTRID_MOV_FROM_DRX).
3410 * @param iDrReg The debug register being accessed.
3411 * @param iGReg The general register to/from which the DRx value is being
3412 * store/loaded.
3413 * @param cbInstr The instruction length in bytes.
3414 */
3415IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3416 uint8_t cbInstr)
3417{
3418 Assert(iDrReg <= 7);
3419 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3420 Assert(iGReg < X86_GREG_COUNT);
3421
3422 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3423 Assert(pVmcs);
3424
3425 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3426 {
3427 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3428 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3429 VMXVEXITINFO ExitInfo;
3430 RT_ZERO(ExitInfo);
3431 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3432 ExitInfo.cbInstr = cbInstr;
3433 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3434 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3435 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3436 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3437 }
3438
3439 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3440}
3441
3442
3443/**
3444 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3445 *
3446 * @returns VBox strict status code.
3447 * @param pVCpu The cross context virtual CPU structure.
3448 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3449 * VMXINSTRID_IO_OUT).
3450 * @param u16Port The I/O port being accessed.
3451 * @param fImm Whether the I/O port was encoded using an immediate operand
3452 * or the implicit DX register.
3453 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3454 * @param cbInstr The instruction length in bytes.
3455 */
3456IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3457 uint8_t cbInstr)
3458{
3459 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3460 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3461
3462 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3463 if (fIntercept)
3464 {
3465 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3466 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3467 VMXVEXITINFO ExitInfo;
3468 RT_ZERO(ExitInfo);
3469 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3470 ExitInfo.cbInstr = cbInstr;
3471 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3472 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3473 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3474 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3475 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3476 }
3477
3478 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3479}
3480
3481
3482/**
3483 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3484 *
3485 * @returns VBox strict status code.
3486 * @param pVCpu The cross context virtual CPU structure.
3487 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3488 * VMXINSTRID_IO_OUTS).
3489 * @param u16Port The I/O port being accessed.
3490 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3491 * @param fRep Whether the instruction has a REP prefix or not.
3492 * @param ExitInstrInfo The VM-exit instruction info. field.
3493 * @param cbInstr The instruction length in bytes.
3494 */
3495IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3496 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3497{
3498 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3499 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3500 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3501 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3502 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3503
3504 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3505 if (fIntercept)
3506 {
3507 /*
3508 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3509 */
3510 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3511 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3512 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3513 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3514 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3515
3516 uint32_t uDirection;
3517 uint64_t uGuestLinearAddr;
3518 if (uInstrId == VMXINSTRID_IO_INS)
3519 {
3520 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3521 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3522 }
3523 else
3524 {
3525 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3526 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3527 }
3528
3529 /*
3530 * If the segment is unusable, the guest-linear address in undefined.
3531 * We shall clear it for consistency.
3532 *
3533 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3534 */
3535 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3536 uGuestLinearAddr = 0;
3537
3538 VMXVEXITINFO ExitInfo;
3539 RT_ZERO(ExitInfo);
3540 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3541 ExitInfo.cbInstr = cbInstr;
3542 ExitInfo.InstrInfo = ExitInstrInfo;
3543 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3544 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3545 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3546 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3547 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3548 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3549 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3550 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3551 }
3552
3553 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3554}
3555
3556
3557/**
3558 * VMX VM-exit handler for VM-exits due to MWAIT.
3559 *
3560 * @returns VBox strict status code.
3561 * @param pVCpu The cross context virtual CPU structure.
3562 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3563 * @param cbInstr The instruction length in bytes.
3564 */
3565IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3566{
3567 VMXVEXITINFO ExitInfo;
3568 RT_ZERO(ExitInfo);
3569 ExitInfo.uReason = VMX_EXIT_MWAIT;
3570 ExitInfo.cbInstr = cbInstr;
3571 ExitInfo.u64Qual = fMonitorHwArmed;
3572 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3573}
3574
3575
3576/**
3577 * VMX VM-exit handler for VM-exits due to PAUSE.
3578 *
3579 * @returns VBox strict status code.
3580 * @param pVCpu The cross context virtual CPU structure.
3581 * @param cbInstr The instruction length in bytes.
3582 */
3583IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3584{
3585 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3586 Assert(pVmcs);
3587
3588 /*
3589 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3590 * "PAUSE-loop exiting" control.
3591 *
3592 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3593 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3594 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3595 * a VM-exit.
3596 *
3597 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3598 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3599 */
3600 bool fIntercept = false;
3601 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3602 fIntercept = true;
3603 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3604 && pVCpu->iem.s.uCpl == 0)
3605 {
3606 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3607
3608 /*
3609 * A previous-PAUSE-tick value of 0 is used to identify the first time
3610 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3611 * consider this to be the first execution of PAUSE in a loop according
3612 * to the Intel.
3613 *
3614 * All subsequent records for the previous-PAUSE-tick we ensure that it
3615 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3616 */
3617 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3618 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3619 uint64_t const uTick = TMCpuTickGet(pVCpu);
3620 uint32_t const uPleGap = pVmcs->u32PleGap;
3621 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3622 if ( *puPrevPauseTick == 0
3623 || uTick - *puPrevPauseTick > uPleGap)
3624 *puFirstPauseLoopTick = uTick;
3625 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3626 fIntercept = true;
3627
3628 *puPrevPauseTick = uTick | 1;
3629 }
3630
3631 if (fIntercept)
3632 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3633
3634 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3635}
3636
3637
3638/**
3639 * VMX VM-exit handler for VM-exits due to task switches.
3640 *
3641 * @returns VBox strict status code.
3642 * @param pVCpu The cross context virtual CPU structure.
3643 * @param enmTaskSwitch The cause of the task switch.
3644 * @param SelNewTss The selector of the new TSS.
3645 * @param cbInstr The instruction length in bytes.
3646 */
3647IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3648{
3649 /*
3650 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3651 *
3652 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3653 * instruction or delivery of the exception generated by one of these instructions
3654 * lead to a task switch through a task gate in the IDT, we need to provide the
3655 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3656 * leaves the VM-exit instruction length field undefined.
3657 *
3658 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3659 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3660 */
3661 Assert(cbInstr <= 15);
3662
3663 uint8_t uType;
3664 switch (enmTaskSwitch)
3665 {
3666 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3667 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3668 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3669 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3670 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3671 }
3672
3673 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3674 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3675 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3676 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3677}
3678
3679
3680/**
3681 * VMX VM-exit handler for VM-exits due to task switches.
3682 *
3683 * This is intended for task switches where the caller provides all the relevant
3684 * VM-exit information.
3685 *
3686 * @returns VBox strict status code.
3687 * @param pVCpu The cross context virtual CPU structure.
3688 * @param pExitInfo Pointer to the VM-exit information.
3689 * @param pExitEventInfo Pointer to the VM-exit event information.
3690 */
3691IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3692 PCVMXVEXITEVENTINFO pExitEventInfo)
3693{
3694 Assert(pExitInfo);
3695 Assert(pExitEventInfo);
3696
3697 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3698 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3699 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3700
3701 /*
3702 * Figure out if an instruction was the source of the task switch.
3703 *
3704 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3705 * of an event generated by a software interrupt (INT-N), privileged software
3706 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3707 * the instruction length.
3708 */
3709 bool fHasInstrLen;
3710 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3711 {
3712 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3713 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3714 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3715 if (fIdtVectInfoValid)
3716 {
3717 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3718 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3719 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3720
3721 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3722 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3723 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3724 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3725 fHasInstrLen = true;
3726 else
3727 fHasInstrLen = false;
3728 }
3729 else
3730 fHasInstrLen = false;
3731 }
3732 else
3733 {
3734 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3735 fHasInstrLen = true;
3736 }
3737
3738 if (fHasInstrLen)
3739 {
3740 Assert(pExitInfo->cbInstr > 0);
3741 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3742 }
3743 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3744}
3745
3746
3747/**
3748 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3749 *
3750 * @returns VBox strict status code.
3751 * @param pVCpu The cross context virtual CPU structure.
3752 */
3753IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3754{
3755 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3756 Assert(pVmcs);
3757
3758 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3759 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3760 {
3761 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3762 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3763
3764 /*
3765 * Calculate the current VMX-preemption timer value.
3766 * Only if the value has reached zero, we cause the VM-exit.
3767 */
3768 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3769 if (!uPreemptTimer)
3770 {
3771 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3772 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3773 pVmcs->u32PreemptTimer = 0;
3774
3775 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3776 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3777 }
3778 }
3779
3780 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3781}
3782
3783
3784/**
3785 * VMX VM-exit handler for VM-exits due to external interrupts.
3786 *
3787 * @returns VBox strict status code.
3788 * @param pVCpu The cross context virtual CPU structure.
3789 * @param uVector The external interrupt vector (pass 0 if the interrupt
3790 * is still pending since we typically won't know the
3791 * vector).
3792 * @param fIntPending Whether the external interrupt is pending or
3793 * acknowledged in the interrupt controller.
3794 */
3795IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3796{
3797 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3798 Assert(pVmcs);
3799 Assert(fIntPending || uVector == 0);
3800
3801 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3802 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3803 * functions require prior checking of a blanket intercept and which don't.
3804 * It is better for the caller to check a blanket intercept performance wise
3805 * than making a function call. Leaving this as a todo because it is more
3806 * a performance issue. */
3807
3808 /* The VM-exit is subject to "External interrupt exiting" being set. */
3809 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3810 {
3811 if (fIntPending)
3812 {
3813 /*
3814 * If the interrupt is pending and we don't need to acknowledge the
3815 * interrupt on VM-exit, cause the VM-exit immediately.
3816 *
3817 * See Intel spec 25.2 "Other Causes Of VM Exits".
3818 */
3819 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3820 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3821
3822 /*
3823 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3824 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3825 * acknowledged that the interrupt has been consumed.
3826 */
3827 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3828 }
3829
3830 /*
3831 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3832 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3833 * all set, we cause the VM-exit now. We need to record the external interrupt that
3834 * just occurred in the VM-exit interruption information field.
3835 *
3836 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3837 */
3838 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3839 {
3840 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3841 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3842 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3843 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3844 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3845 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3846 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3847 }
3848 }
3849
3850 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3851}
3852
3853
3854/**
3855 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3856 * an event.
3857 *
3858 * @returns VBox strict status code.
3859 * @param pVCpu The cross context virtual CPU structure.
3860 */
3861IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3862{
3863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3864 Assert(pVmcs);
3865
3866 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3867 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3868 {
3869 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3870 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3871 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3872 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3873 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3874 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3875 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3876 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3877 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3878
3879 /*
3880 * A VM-exit is not considered to occur during event delivery when the original
3881 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3882 * using the exception bitmap).
3883 *
3884 * Therefore, we must clear the original event from the IDT-vectoring fields which
3885 * would've been recorded before causing the VM-exit.
3886 *
3887 * 27.2.3 "Information for VM Exits During Event Delivery"
3888 */
3889 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3890 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3891 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3892 }
3893
3894 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3895}
3896
3897
3898/**
3899 * VMX VM-exit handler for VM-exit due to delivery of an events.
3900 *
3901 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3902 * all the relevant VM-exit information.
3903 *
3904 * @returns VBox strict status code.
3905 * @param pVCpu The cross context virtual CPU structure.
3906 * @param pExitInfo Pointer to the VM-exit information.
3907 * @param pExitEventInfo Pointer to the VM-exit event information.
3908 */
3909IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3910{
3911 Assert(pExitInfo);
3912 Assert(pExitEventInfo);
3913 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3914
3915 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3916 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3917 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3918 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3919 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3920 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3921}
3922
3923
3924/**
3925 * VMX VM-exit handler for VM-exits due to delivery of an event.
3926 *
3927 * @returns VBox strict status code.
3928 * @param pVCpu The cross context virtual CPU structure.
3929 * @param uVector The interrupt / exception vector.
3930 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3931 * @param uErrCode The error code associated with the event.
3932 * @param uCr2 The CR2 value in case of a \#PF exception.
3933 * @param cbInstr The instruction length in bytes.
3934 */
3935IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3936 uint8_t cbInstr)
3937{
3938 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3939 Assert(pVmcs);
3940
3941 /*
3942 * If the event is being injected as part of VM-entry, it is -not- subject to event
3943 * intercepts in the nested-guest. However, secondary exceptions that occur during
3944 * injection of any event -are- subject to event interception.
3945 *
3946 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3947 */
3948 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3949 {
3950 /*
3951 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3952 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3953 *
3954 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3955 */
3956 if ( uVector == X86_XCPT_NMI
3957 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3958 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3959 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3960 else
3961 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3962
3963 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3964 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3965 }
3966
3967 /*
3968 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3969 * If not, the caller will continue delivery of the external interrupt as it would
3970 * normally. The interrupt is no longer pending in the interrupt controller at this
3971 * point.
3972 */
3973 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3974 {
3975 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3976 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3977 }
3978
3979 /*
3980 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3981 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3982 * interrupts.
3983 */
3984 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3985 bool fIntercept;
3986 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3987 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3988 {
3989 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3990 }
3991 else
3992 {
3993 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3994 fIntercept = false;
3995 }
3996
3997 /*
3998 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3999 * relevant VM-exit information and cause the VM-exit.
4000 */
4001 if (fIntercept)
4002 {
4003 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4004
4005 /* Construct the rest of the event related information fields and cause the VM-exit. */
4006 uint64_t u64ExitQual;
4007 if (uVector == X86_XCPT_PF)
4008 {
4009 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4010 u64ExitQual = uCr2;
4011 }
4012 else if (uVector == X86_XCPT_DB)
4013 {
4014 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4015 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4016 }
4017 else
4018 u64ExitQual = 0;
4019
4020 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4021 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4022 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4023 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4024 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4025 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4026 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4027 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4028 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4029 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4030
4031 /*
4032 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
4033 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4034 * length.
4035 */
4036 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4037 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4038 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4039 else
4040 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4041
4042 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
4043 }
4044
4045 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4046}
4047
4048
4049/**
4050 * VMX VM-exit handler for VM-exits due to a triple fault.
4051 *
4052 * @returns VBox strict status code.
4053 * @param pVCpu The cross context virtual CPU structure.
4054 */
4055IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4056{
4057 /*
4058 * A VM-exit is not considered to occur during event delivery when the original
4059 * event results in a triple-fault.
4060 *
4061 * Therefore, we must clear the original event from the IDT-vectoring fields which
4062 * would've been recorded before causing the VM-exit.
4063 *
4064 * 27.2.3 "Information for VM Exits During Event Delivery"
4065 */
4066 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4067 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4068
4069 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
4070}
4071
4072
4073/**
4074 * VMX VM-exit handler for APIC accesses.
4075 *
4076 * @param pVCpu The cross context virtual CPU structure.
4077 * @param offAccess The offset of the register being accessed.
4078 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4079 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4080 */
4081IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4082{
4083 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4084
4085 VMXAPICACCESS enmAccess;
4086 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4087 if (fInEventDelivery)
4088 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4089 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4090 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4091 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4092 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4093 else
4094 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4095
4096 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4098 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4099}
4100
4101
4102/**
4103 * VMX VM-exit handler for APIC accesses.
4104 *
4105 * This is intended for APIC accesses where the caller provides all the
4106 * relevant VM-exit information.
4107 *
4108 * @returns VBox strict status code.
4109 * @param pVCpu The cross context virtual CPU structure.
4110 * @param pExitInfo Pointer to the VM-exit information.
4111 * @param pExitEventInfo Pointer to the VM-exit event information.
4112 */
4113IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
4114 PCVMXVEXITEVENTINFO pExitEventInfo)
4115{
4116 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4117 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4118 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4119 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4120 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4121 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4122 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4123}
4124
4125
4126/**
4127 * VMX VM-exit handler for APIC-write VM-exits.
4128 *
4129 * @param pVCpu The cross context virtual CPU structure.
4130 * @param offApic The write to the virtual-APIC page offset that caused this
4131 * VM-exit.
4132 */
4133IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4134{
4135 Assert(offApic < XAPIC_OFF_END + 4);
4136 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4137 offApic &= UINT16_C(0xfff);
4138 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4139}
4140
4141
4142/**
4143 * Sets virtual-APIC write emulation as pending.
4144 *
4145 * @param pVCpu The cross context virtual CPU structure.
4146 * @param offApic The offset in the virtual-APIC page that was written.
4147 */
4148DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4149{
4150 Assert(offApic < XAPIC_OFF_END + 4);
4151
4152 /*
4153 * Record the currently updated APIC offset, as we need this later for figuring
4154 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4155 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4156 */
4157 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4158
4159 /*
4160 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4161 * virtualization or APIC-write emulation).
4162 */
4163 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4164 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4165}
4166
4167
4168/**
4169 * Clears any pending virtual-APIC write emulation.
4170 *
4171 * @returns The virtual-APIC offset that was written before clearing it.
4172 * @param pVCpu The cross context virtual CPU structure.
4173 */
4174DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4175{
4176 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4177 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4178 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4179 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4180 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4181 return offVirtApicWrite;
4182}
4183
4184
4185/**
4186 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4187 *
4188 * @returns The register from the virtual-APIC page.
4189 * @param pVCpu The cross context virtual CPU structure.
4190 * @param offReg The offset of the register being read.
4191 */
4192IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4193{
4194 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4195 Assert(pVmcs);
4196
4197 uint32_t uReg;
4198 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4199 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4200 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4201 if (RT_FAILURE(rc))
4202 {
4203 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4204 GCPhysVirtApic));
4205 uReg = 0;
4206 }
4207 return uReg;
4208}
4209
4210
4211/**
4212 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4213 *
4214 * @returns The register from the virtual-APIC page.
4215 * @param pVCpu The cross context virtual CPU structure.
4216 * @param offReg The offset of the register being read.
4217 */
4218IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4219{
4220 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4221 Assert(pVmcs);
4222
4223 uint64_t uReg;
4224 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4225 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4226 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4227 if (RT_FAILURE(rc))
4228 {
4229 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4230 GCPhysVirtApic));
4231 uReg = 0;
4232 }
4233 return uReg;
4234}
4235
4236
4237/**
4238 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4239 *
4240 * @param pVCpu The cross context virtual CPU structure.
4241 * @param offReg The offset of the register being written.
4242 * @param uReg The register value to write.
4243 */
4244IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4245{
4246 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4247 Assert(pVmcs);
4248 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4249 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4250 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4251 if (RT_FAILURE(rc))
4252 {
4253 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4254 GCPhysVirtApic));
4255 }
4256}
4257
4258
4259/**
4260 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4261 *
4262 * @param pVCpu The cross context virtual CPU structure.
4263 * @param offReg The offset of the register being written.
4264 * @param uReg The register value to write.
4265 */
4266IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4267{
4268 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4269 Assert(pVmcs);
4270 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4271 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4272 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4273 if (RT_FAILURE(rc))
4274 {
4275 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4276 GCPhysVirtApic));
4277 }
4278}
4279
4280
4281/**
4282 * Sets the vector in a virtual-APIC 256-bit sparse register.
4283 *
4284 * @param pVCpu The cross context virtual CPU structure.
4285 * @param offReg The offset of the 256-bit spare register.
4286 * @param uVector The vector to set.
4287 *
4288 * @remarks This is based on our APIC device code.
4289 */
4290IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4291{
4292 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4293 Assert(pVmcs);
4294 uint32_t uReg;
4295 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4296 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4297 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4298 if (RT_SUCCESS(rc))
4299 {
4300 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4301 uReg |= RT_BIT(idxVectorBit);
4302 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4303 if (RT_FAILURE(rc))
4304 {
4305 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4306 uVector, offReg, GCPhysVirtApic));
4307 }
4308 }
4309 else
4310 {
4311 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4312 uVector, offReg, GCPhysVirtApic));
4313 }
4314}
4315
4316
4317/**
4318 * Clears the vector in a virtual-APIC 256-bit sparse register.
4319 *
4320 * @param pVCpu The cross context virtual CPU structure.
4321 * @param offReg The offset of the 256-bit spare register.
4322 * @param uVector The vector to clear.
4323 *
4324 * @remarks This is based on our APIC device code.
4325 */
4326IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4327{
4328 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4329 Assert(pVmcs);
4330 uint32_t uReg;
4331 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4332 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4333 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4334 if (RT_SUCCESS(rc))
4335 {
4336 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4337 uReg &= ~RT_BIT(idxVectorBit);
4338 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4339 if (RT_FAILURE(rc))
4340 {
4341 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4342 uVector, offReg, GCPhysVirtApic));
4343 }
4344 }
4345 else
4346 {
4347 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4348 uVector, offReg, GCPhysVirtApic));
4349 }
4350}
4351
4352
4353/**
4354 * Checks if a memory access to the APIC-access page must causes an APIC-access
4355 * VM-exit.
4356 *
4357 * @param pVCpu The cross context virtual CPU structure.
4358 * @param offAccess The offset of the register being accessed.
4359 * @param cbAccess The size of the access in bytes.
4360 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4361 * IEM_ACCESS_TYPE_WRITE).
4362 *
4363 * @remarks This must not be used for MSR-based APIC-access page accesses!
4364 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4365 */
4366IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4367{
4368 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4369 Assert(pVmcs);
4370 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4371
4372 /*
4373 * We must cause a VM-exit if any of the following are true:
4374 * - TPR shadowing isn't active.
4375 * - The access size exceeds 32-bits.
4376 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4377 *
4378 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4379 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4380 */
4381 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4382 || cbAccess > sizeof(uint32_t)
4383 || ((offAccess + cbAccess - 1) & 0xc)
4384 || offAccess >= XAPIC_OFF_END + 4)
4385 return true;
4386
4387 /*
4388 * If the access is part of an operation where we have already
4389 * virtualized a virtual-APIC write, we must cause a VM-exit.
4390 */
4391 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4392 return true;
4393
4394 /*
4395 * Check write accesses to the APIC-access page that cause VM-exits.
4396 */
4397 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4398 {
4399 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4400 {
4401 /*
4402 * With APIC-register virtualization, a write access to any of the
4403 * following registers are virtualized. Accessing any other register
4404 * causes a VM-exit.
4405 */
4406 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4407 switch (offAlignedAccess)
4408 {
4409 case XAPIC_OFF_ID:
4410 case XAPIC_OFF_TPR:
4411 case XAPIC_OFF_EOI:
4412 case XAPIC_OFF_LDR:
4413 case XAPIC_OFF_DFR:
4414 case XAPIC_OFF_SVR:
4415 case XAPIC_OFF_ESR:
4416 case XAPIC_OFF_ICR_LO:
4417 case XAPIC_OFF_ICR_HI:
4418 case XAPIC_OFF_LVT_TIMER:
4419 case XAPIC_OFF_LVT_THERMAL:
4420 case XAPIC_OFF_LVT_PERF:
4421 case XAPIC_OFF_LVT_LINT0:
4422 case XAPIC_OFF_LVT_LINT1:
4423 case XAPIC_OFF_LVT_ERROR:
4424 case XAPIC_OFF_TIMER_ICR:
4425 case XAPIC_OFF_TIMER_DCR:
4426 break;
4427 default:
4428 return true;
4429 }
4430 }
4431 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4432 {
4433 /*
4434 * With virtual-interrupt delivery, a write access to any of the
4435 * following registers are virtualized. Accessing any other register
4436 * causes a VM-exit.
4437 *
4438 * Note! The specification does not allow writing to offsets in-between
4439 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4440 */
4441 switch (offAccess)
4442 {
4443 case XAPIC_OFF_TPR:
4444 case XAPIC_OFF_EOI:
4445 case XAPIC_OFF_ICR_LO:
4446 break;
4447 default:
4448 return true;
4449 }
4450 }
4451 else
4452 {
4453 /*
4454 * Without APIC-register virtualization or virtual-interrupt delivery,
4455 * only TPR accesses are virtualized.
4456 */
4457 if (offAccess == XAPIC_OFF_TPR)
4458 { /* likely */ }
4459 else
4460 return true;
4461 }
4462 }
4463 else
4464 {
4465 /*
4466 * Check read accesses to the APIC-access page that cause VM-exits.
4467 */
4468 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4469 {
4470 /*
4471 * With APIC-register virtualization, a read access to any of the
4472 * following registers are virtualized. Accessing any other register
4473 * causes a VM-exit.
4474 */
4475 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4476 switch (offAlignedAccess)
4477 {
4478 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4479 case XAPIC_OFF_ID:
4480 case XAPIC_OFF_VERSION:
4481 case XAPIC_OFF_TPR:
4482 case XAPIC_OFF_EOI:
4483 case XAPIC_OFF_LDR:
4484 case XAPIC_OFF_DFR:
4485 case XAPIC_OFF_SVR:
4486 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4487 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4488 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4489 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4490 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4491 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4492 case XAPIC_OFF_ESR:
4493 case XAPIC_OFF_ICR_LO:
4494 case XAPIC_OFF_ICR_HI:
4495 case XAPIC_OFF_LVT_TIMER:
4496 case XAPIC_OFF_LVT_THERMAL:
4497 case XAPIC_OFF_LVT_PERF:
4498 case XAPIC_OFF_LVT_LINT0:
4499 case XAPIC_OFF_LVT_LINT1:
4500 case XAPIC_OFF_LVT_ERROR:
4501 case XAPIC_OFF_TIMER_ICR:
4502 case XAPIC_OFF_TIMER_DCR:
4503 break;
4504 default:
4505 return true;
4506 }
4507 }
4508 else
4509 {
4510 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4511 if (offAccess == XAPIC_OFF_TPR)
4512 { /* likely */ }
4513 else
4514 return true;
4515 }
4516 }
4517
4518 /* The APIC access is virtualized, does not cause a VM-exit. */
4519 return false;
4520}
4521
4522
4523/**
4524 * Virtualizes a memory-based APIC access where the address is not used to access
4525 * memory.
4526 *
4527 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4528 * page-faults but do not use the address to access memory.
4529 *
4530 * @param pVCpu The cross context virtual CPU structure.
4531 * @param pGCPhysAccess Pointer to the guest-physical address used.
4532 */
4533IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4534{
4535 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4536 Assert(pVmcs);
4537 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4538 Assert(pGCPhysAccess);
4539
4540 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4541 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4542 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4543
4544 if (GCPhysAccess == GCPhysApic)
4545 {
4546 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4547 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4548 uint16_t const cbAccess = 1;
4549 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4550 if (fIntercept)
4551 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4552
4553 *pGCPhysAccess = GCPhysApic | offAccess;
4554 return VINF_VMX_MODIFIES_BEHAVIOR;
4555 }
4556
4557 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4558}
4559
4560
4561/**
4562 * Virtualizes a memory-based APIC access.
4563 *
4564 * @returns VBox strict status code.
4565 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4566 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4567 *
4568 * @param pVCpu The cross context virtual CPU structure.
4569 * @param offAccess The offset of the register being accessed (within the
4570 * APIC-access page).
4571 * @param cbAccess The size of the access in bytes.
4572 * @param pvData Pointer to the data being written or where to store the data
4573 * being read.
4574 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4575 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4576 */
4577IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4578 uint32_t fAccess)
4579{
4580 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4581 Assert(pVmcs);
4582 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4583 Assert(pvData);
4584 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4585 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4586 || (fAccess & IEM_ACCESS_INSTRUCTION));
4587
4588 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4589 if (fIntercept)
4590 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4591
4592 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4593 {
4594 /*
4595 * A write access to the APIC-access page that is virtualized (rather than
4596 * causing a VM-exit) writes data to the virtual-APIC page.
4597 */
4598 uint32_t const u32Data = *(uint32_t *)pvData;
4599 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4600
4601 /*
4602 * Record the currently updated APIC offset, as we need this later for figuring
4603 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4604 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4605 *
4606 * After completion of the current operation, we need to perform TPR virtualization,
4607 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4608 *
4609 * The current operation may be a REP-prefixed string instruction, execution of any
4610 * other instruction, or delivery of an event through the IDT.
4611 *
4612 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4613 * performed now but later after completion of the current operation.
4614 *
4615 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4616 */
4617 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4618 }
4619 else
4620 {
4621 /*
4622 * A read access from the APIC-access page that is virtualized (rather than
4623 * causing a VM-exit) returns data from the virtual-APIC page.
4624 *
4625 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4626 */
4627 Assert(cbAccess <= 4);
4628 Assert(offAccess < XAPIC_OFF_END + 4);
4629 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4630
4631 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4632 u32Data &= s_auAccessSizeMasks[cbAccess];
4633 *(uint32_t *)pvData = u32Data;
4634 }
4635
4636 return VINF_VMX_MODIFIES_BEHAVIOR;
4637}
4638
4639
4640/**
4641 * Virtualizes an MSR-based APIC read access.
4642 *
4643 * @returns VBox strict status code.
4644 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4645 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4646 * handled by the x2APIC device.
4647 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4648 * not within the range of valid MSRs, caller must raise \#GP(0).
4649 * @param pVCpu The cross context virtual CPU structure.
4650 * @param idMsr The x2APIC MSR being read.
4651 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4652 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4653 */
4654IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4655{
4656 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4657 Assert(pVmcs);
4658 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4659 Assert(pu64Value);
4660
4661 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4662 {
4663 /*
4664 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4665 * what the end of the valid x2APIC MSR range is. Hence the use of different
4666 * macros here.
4667 *
4668 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4669 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4670 */
4671 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4672 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4673 {
4674 uint16_t const offReg = (idMsr & 0xff) << 4;
4675 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4676 *pu64Value = u64Value;
4677 return VINF_VMX_MODIFIES_BEHAVIOR;
4678 }
4679 return VERR_OUT_OF_RANGE;
4680 }
4681
4682 if (idMsr == MSR_IA32_X2APIC_TPR)
4683 {
4684 uint16_t const offReg = (idMsr & 0xff) << 4;
4685 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4686 *pu64Value = u64Value;
4687 return VINF_VMX_MODIFIES_BEHAVIOR;
4688 }
4689
4690 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4691}
4692
4693
4694/**
4695 * Virtualizes an MSR-based APIC write access.
4696 *
4697 * @returns VBox strict status code.
4698 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4699 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4700 * not within the range of valid MSRs, caller must raise \#GP(0).
4701 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4702 *
4703 * @param pVCpu The cross context virtual CPU structure.
4704 * @param idMsr The x2APIC MSR being written.
4705 * @param u64Value The value of the x2APIC MSR being written.
4706 */
4707IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4708{
4709 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4710 Assert(pVmcs);
4711
4712 /*
4713 * Check if the access is to be virtualized.
4714 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4715 */
4716 if ( idMsr == MSR_IA32_X2APIC_TPR
4717 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4718 && ( idMsr == MSR_IA32_X2APIC_EOI
4719 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4720 {
4721 /* Validate the MSR write depending on the register. */
4722 switch (idMsr)
4723 {
4724 case MSR_IA32_X2APIC_TPR:
4725 case MSR_IA32_X2APIC_SELF_IPI:
4726 {
4727 if (u64Value & UINT64_C(0xffffffffffffff00))
4728 return VERR_OUT_OF_RANGE;
4729 break;
4730 }
4731 case MSR_IA32_X2APIC_EOI:
4732 {
4733 if (u64Value != 0)
4734 return VERR_OUT_OF_RANGE;
4735 break;
4736 }
4737 }
4738
4739 /* Write the MSR to the virtual-APIC page. */
4740 uint16_t const offReg = (idMsr & 0xff) << 4;
4741 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4742
4743 /*
4744 * Record the currently updated APIC offset, as we need this later for figuring
4745 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4746 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4747 */
4748 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4749
4750 return VINF_VMX_MODIFIES_BEHAVIOR;
4751 }
4752
4753 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4754}
4755
4756
4757/**
4758 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4759 *
4760 * @returns VBox status code.
4761 * @retval VINF_SUCCESS when the highest set bit is found.
4762 * @retval VERR_NOT_FOUND when no bit is set.
4763 *
4764 * @param pVCpu The cross context virtual CPU structure.
4765 * @param offReg The offset of the APIC 256-bit sparse register.
4766 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4767 * set in the register. Only valid when VINF_SUCCESS is
4768 * returned.
4769 *
4770 * @remarks The format of the 256-bit sparse register here mirrors that found in
4771 * real APIC hardware.
4772 */
4773static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4774{
4775 Assert(offReg < XAPIC_OFF_END + 4);
4776 Assert(pidxHighestBit);
4777 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4778
4779 /*
4780 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4781 * However, in each fragment only the first 4 bytes are used.
4782 */
4783 uint8_t const cFrags = 8;
4784 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4785 {
4786 uint16_t const offFrag = iFrag * 16;
4787 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4788 if (!u32Frag)
4789 continue;
4790
4791 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4792 Assert(idxHighestBit > 0);
4793 --idxHighestBit;
4794 Assert(idxHighestBit <= UINT8_MAX);
4795 *pidxHighestBit = idxHighestBit;
4796 return VINF_SUCCESS;
4797 }
4798 return VERR_NOT_FOUND;
4799}
4800
4801
4802/**
4803 * Evaluates pending virtual interrupts.
4804 *
4805 * @param pVCpu The cross context virtual CPU structure.
4806 */
4807IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4808{
4809 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4810 Assert(pVmcs);
4811 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4812
4813 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4814 {
4815 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4816 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4817
4818 if ((uRvi >> 4) > (uPpr >> 4))
4819 {
4820 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4821 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4822 }
4823 else
4824 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4825 }
4826}
4827
4828
4829/**
4830 * Performs PPR virtualization.
4831 *
4832 * @returns VBox strict status code.
4833 * @param pVCpu The cross context virtual CPU structure.
4834 */
4835IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4836{
4837 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4838 Assert(pVmcs);
4839 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4840 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4841
4842 /*
4843 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4844 * or EOI-virtualization.
4845 *
4846 * See Intel spec. 29.1.3 "PPR Virtualization".
4847 */
4848 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4849 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4850
4851 uint32_t uPpr;
4852 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4853 uPpr = uTpr & 0xff;
4854 else
4855 uPpr = uSvi & 0xf0;
4856
4857 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4858 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4859}
4860
4861
4862/**
4863 * Performs VMX TPR virtualization.
4864 *
4865 * @returns VBox strict status code.
4866 * @param pVCpu The cross context virtual CPU structure.
4867 */
4868IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4869{
4870 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4871 Assert(pVmcs);
4872 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4873
4874 /*
4875 * We should have already performed the virtual-APIC write to the TPR offset
4876 * in the virtual-APIC page. We now perform TPR virtualization.
4877 *
4878 * See Intel spec. 29.1.2 "TPR Virtualization".
4879 */
4880 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4881 {
4882 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4883 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4884
4885 /*
4886 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4887 * See Intel spec. 29.1.2 "TPR Virtualization".
4888 */
4889 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4890 {
4891 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4892 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4893 }
4894 }
4895 else
4896 {
4897 iemVmxPprVirtualization(pVCpu);
4898 iemVmxEvalPendingVirtIntrs(pVCpu);
4899 }
4900
4901 return VINF_SUCCESS;
4902}
4903
4904
4905/**
4906 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4907 * not.
4908 *
4909 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4910 * @param pVCpu The cross context virtual CPU structure.
4911 * @param uVector The interrupt that was acknowledged using an EOI.
4912 */
4913IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4914{
4915 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4916 Assert(pVmcs);
4917 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4918
4919 if (uVector < 64)
4920 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4921 if (uVector < 128)
4922 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4923 if (uVector < 192)
4924 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4925 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4926}
4927
4928
4929/**
4930 * Performs EOI virtualization.
4931 *
4932 * @returns VBox strict status code.
4933 * @param pVCpu The cross context virtual CPU structure.
4934 */
4935IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4936{
4937 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4938 Assert(pVmcs);
4939 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4940
4941 /*
4942 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4943 * and get the next guest-interrupt that's in-service (if any).
4944 *
4945 * See Intel spec. 29.1.4 "EOI Virtualization".
4946 */
4947 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4948 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4949 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4950
4951 uint8_t uVector = uSvi;
4952 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4953
4954 uVector = 0;
4955 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4956
4957 if (uVector)
4958 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4959 else
4960 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4961
4962 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4963 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4964
4965 iemVmxPprVirtualization(pVCpu);
4966 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4967 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4968 iemVmxEvalPendingVirtIntrs(pVCpu);
4969 return VINF_SUCCESS;
4970}
4971
4972
4973/**
4974 * Performs self-IPI virtualization.
4975 *
4976 * @returns VBox strict status code.
4977 * @param pVCpu The cross context virtual CPU structure.
4978 */
4979IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4980{
4981 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4982 Assert(pVmcs);
4983 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4984
4985 /*
4986 * We should have already performed the virtual-APIC write to the self-IPI offset
4987 * in the virtual-APIC page. We now perform self-IPI virtualization.
4988 *
4989 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4990 */
4991 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4992 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4993 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4994 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4995 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4996 if (uVector > uRvi)
4997 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4998 iemVmxEvalPendingVirtIntrs(pVCpu);
4999 return VINF_SUCCESS;
5000}
5001
5002
5003/**
5004 * Performs VMX APIC-write emulation.
5005 *
5006 * @returns VBox strict status code.
5007 * @param pVCpu The cross context virtual CPU structure.
5008 */
5009IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5010{
5011 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5012 Assert(pVmcs);
5013
5014 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5015 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5016
5017 /*
5018 * Perform APIC-write emulation based on the virtual-APIC register written.
5019 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5020 */
5021 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5022 VBOXSTRICTRC rcStrict;
5023 switch (offApicWrite)
5024 {
5025 case XAPIC_OFF_TPR:
5026 {
5027 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5028 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5029 uTpr &= UINT32_C(0x000000ff);
5030 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5031 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5032 rcStrict = iemVmxTprVirtualization(pVCpu);
5033 break;
5034 }
5035
5036 case XAPIC_OFF_EOI:
5037 {
5038 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5039 {
5040 /* Clear VEOI and perform EOI virtualization. */
5041 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5042 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5043 rcStrict = iemVmxEoiVirtualization(pVCpu);
5044 }
5045 else
5046 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5047 break;
5048 }
5049
5050 case XAPIC_OFF_ICR_LO:
5051 {
5052 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5053 {
5054 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5055 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5056 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5057 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5058 if ( !(uIcrLo & fIcrLoMb0)
5059 && (uIcrLo & fIcrLoMb1))
5060 {
5061 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5062 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5063 }
5064 else
5065 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5066 }
5067 else
5068 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5069 break;
5070 }
5071
5072 case XAPIC_OFF_ICR_HI:
5073 {
5074 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5075 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5076 uIcrHi &= UINT32_C(0xff000000);
5077 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5078 rcStrict = VINF_SUCCESS;
5079 break;
5080 }
5081
5082 default:
5083 {
5084 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5085 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5086 break;
5087 }
5088 }
5089
5090 return rcStrict;
5091}
5092
5093
5094/**
5095 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5096 *
5097 * @param pVCpu The cross context virtual CPU structure.
5098 * @param pszInstr The VMX instruction name (for logging purposes).
5099 */
5100IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5101{
5102 /*
5103 * Guest Control Registers, Debug Registers, and MSRs.
5104 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5105 */
5106 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5107 const char *const pszFailure = "VM-exit";
5108 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5109
5110 /* CR0 reserved bits. */
5111 {
5112 /* CR0 MB1 bits. */
5113 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5114 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5115 if (fUnrestrictedGuest)
5116 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5117 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5118 { /* likely */ }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5121
5122 /* CR0 MBZ bits. */
5123 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5124 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5125 { /* likely */ }
5126 else
5127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5128
5129 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5130 if ( !fUnrestrictedGuest
5131 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5132 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5134 }
5135
5136 /* CR4 reserved bits. */
5137 {
5138 /* CR4 MB1 bits. */
5139 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5140 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5141 { /* likely */ }
5142 else
5143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5144
5145 /* CR4 MBZ bits. */
5146 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5147 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5148 { /* likely */ }
5149 else
5150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5151 }
5152
5153 /* DEBUGCTL MSR. */
5154 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5155 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5156 { /* likely */ }
5157 else
5158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5159
5160 /* 64-bit CPU checks. */
5161 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5162 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5163 {
5164 if (fGstInLongMode)
5165 {
5166 /* PAE must be set. */
5167 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5168 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5169 { /* likely */ }
5170 else
5171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5172 }
5173 else
5174 {
5175 /* PCIDE should not be set. */
5176 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5177 { /* likely */ }
5178 else
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5180 }
5181
5182 /* CR3. */
5183 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5184 { /* likely */ }
5185 else
5186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5187
5188 /* DR7. */
5189 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5190 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5194
5195 /* SYSENTER ESP and SYSENTER EIP. */
5196 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5197 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5201 }
5202
5203 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5204 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5205
5206 /* PAT MSR. */
5207 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5208 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5209 { /* likely */ }
5210 else
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5212
5213 /* EFER MSR. */
5214 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5215 {
5216 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5217 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5218 { /* likely */ }
5219 else
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5221
5222 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5223 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5224 if ( fGstLma == fGstInLongMode
5225 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5226 || fGstLma == fGstLme))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5230 }
5231
5232 /* We don't support IA32_BNDCFGS MSR yet. */
5233 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5234
5235 NOREF(pszInstr);
5236 NOREF(pszFailure);
5237 return VINF_SUCCESS;
5238}
5239
5240
5241/**
5242 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5243 *
5244 * @param pVCpu The cross context virtual CPU structure.
5245 * @param pszInstr The VMX instruction name (for logging purposes).
5246 */
5247IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5248{
5249 /*
5250 * Segment registers.
5251 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5252 */
5253 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5254 const char *const pszFailure = "VM-exit";
5255 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5256 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5257 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5258
5259 /* Selectors. */
5260 if ( !fGstInV86Mode
5261 && !fUnrestrictedGuest
5262 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5264
5265 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5266 {
5267 CPUMSELREG SelReg;
5268 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5269 if (RT_LIKELY(rc == VINF_SUCCESS))
5270 { /* likely */ }
5271 else
5272 return rc;
5273
5274 /*
5275 * Virtual-8086 mode checks.
5276 */
5277 if (fGstInV86Mode)
5278 {
5279 /* Base address. */
5280 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5281 { /* likely */ }
5282 else
5283 {
5284 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5286 }
5287
5288 /* Limit. */
5289 if (SelReg.u32Limit == 0xffff)
5290 { /* likely */ }
5291 else
5292 {
5293 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5295 }
5296
5297 /* Attribute. */
5298 if (SelReg.Attr.u == 0xf3)
5299 { /* likely */ }
5300 else
5301 {
5302 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5304 }
5305
5306 /* We're done; move to checking the next segment. */
5307 continue;
5308 }
5309
5310 /* Checks done by 64-bit CPUs. */
5311 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5312 {
5313 /* Base address. */
5314 if ( iSegReg == X86_SREG_FS
5315 || iSegReg == X86_SREG_GS)
5316 {
5317 if (X86_IS_CANONICAL(SelReg.u64Base))
5318 { /* likely */ }
5319 else
5320 {
5321 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5323 }
5324 }
5325 else if (iSegReg == X86_SREG_CS)
5326 {
5327 if (!RT_HI_U32(SelReg.u64Base))
5328 { /* likely */ }
5329 else
5330 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5331 }
5332 else
5333 {
5334 if ( SelReg.Attr.n.u1Unusable
5335 || !RT_HI_U32(SelReg.u64Base))
5336 { /* likely */ }
5337 else
5338 {
5339 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5341 }
5342 }
5343 }
5344
5345 /*
5346 * Checks outside Virtual-8086 mode.
5347 */
5348 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5349 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5350 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5351 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5352 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5353 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5354 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5355 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5356
5357 /* Code or usable segment. */
5358 if ( iSegReg == X86_SREG_CS
5359 || fUsable)
5360 {
5361 /* Reserved bits (bits 31:17 and bits 11:8). */
5362 if (!(SelReg.Attr.u & 0xfffe0f00))
5363 { /* likely */ }
5364 else
5365 {
5366 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5367 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5368 }
5369
5370 /* Descriptor type. */
5371 if (fCodeDataSeg)
5372 { /* likely */ }
5373 else
5374 {
5375 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5377 }
5378
5379 /* Present. */
5380 if (fPresent)
5381 { /* likely */ }
5382 else
5383 {
5384 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5386 }
5387
5388 /* Granularity. */
5389 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5390 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5391 { /* likely */ }
5392 else
5393 {
5394 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5396 }
5397 }
5398
5399 if (iSegReg == X86_SREG_CS)
5400 {
5401 /* Segment Type and DPL. */
5402 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5403 && fUnrestrictedGuest)
5404 {
5405 if (uDpl == 0)
5406 { /* likely */ }
5407 else
5408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5409 }
5410 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5411 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5412 {
5413 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5414 if (uDpl == AttrSs.n.u2Dpl)
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5418 }
5419 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5420 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5421 {
5422 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5423 if (uDpl <= AttrSs.n.u2Dpl)
5424 { /* likely */ }
5425 else
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5427 }
5428 else
5429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5430
5431 /* Def/Big. */
5432 if ( fGstInLongMode
5433 && fSegLong)
5434 {
5435 if (uDefBig == 0)
5436 { /* likely */ }
5437 else
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5439 }
5440 }
5441 else if (iSegReg == X86_SREG_SS)
5442 {
5443 /* Segment Type. */
5444 if ( !fUsable
5445 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5446 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5447 { /* likely */ }
5448 else
5449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5450
5451 /* DPL. */
5452 if (!fUnrestrictedGuest)
5453 {
5454 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5455 { /* likely */ }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5458 }
5459 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5460 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5461 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5462 {
5463 if (uDpl == 0)
5464 { /* likely */ }
5465 else
5466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5467 }
5468 }
5469 else
5470 {
5471 /* DS, ES, FS, GS. */
5472 if (fUsable)
5473 {
5474 /* Segment type. */
5475 if (uSegType & X86_SEL_TYPE_ACCESSED)
5476 { /* likely */ }
5477 else
5478 {
5479 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5481 }
5482
5483 if ( !(uSegType & X86_SEL_TYPE_CODE)
5484 || (uSegType & X86_SEL_TYPE_READ))
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5488
5489 /* DPL. */
5490 if ( !fUnrestrictedGuest
5491 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5492 {
5493 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5494 { /* likely */ }
5495 else
5496 {
5497 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5498 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5499 }
5500 }
5501 }
5502 }
5503 }
5504
5505 /*
5506 * LDTR.
5507 */
5508 {
5509 CPUMSELREG Ldtr;
5510 Ldtr.Sel = pVmcs->GuestLdtr;
5511 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5512 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5513 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5514
5515 if (!Ldtr.Attr.n.u1Unusable)
5516 {
5517 /* Selector. */
5518 if (!(Ldtr.Sel & X86_SEL_LDT))
5519 { /* likely */ }
5520 else
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5522
5523 /* Base. */
5524 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5525 {
5526 if (X86_IS_CANONICAL(Ldtr.u64Base))
5527 { /* likely */ }
5528 else
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5530 }
5531
5532 /* Attributes. */
5533 /* Reserved bits (bits 31:17 and bits 11:8). */
5534 if (!(Ldtr.Attr.u & 0xfffe0f00))
5535 { /* likely */ }
5536 else
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5538
5539 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5540 { /* likely */ }
5541 else
5542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5543
5544 if (!Ldtr.Attr.n.u1DescType)
5545 { /* likely */ }
5546 else
5547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5548
5549 if (Ldtr.Attr.n.u1Present)
5550 { /* likely */ }
5551 else
5552 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5553
5554 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5555 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5556 { /* likely */ }
5557 else
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5559 }
5560 }
5561
5562 /*
5563 * TR.
5564 */
5565 {
5566 CPUMSELREG Tr;
5567 Tr.Sel = pVmcs->GuestTr;
5568 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5569 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5570 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5571
5572 /* Selector. */
5573 if (!(Tr.Sel & X86_SEL_LDT))
5574 { /* likely */ }
5575 else
5576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5577
5578 /* Base. */
5579 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5580 {
5581 if (X86_IS_CANONICAL(Tr.u64Base))
5582 { /* likely */ }
5583 else
5584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5585 }
5586
5587 /* Attributes. */
5588 /* Reserved bits (bits 31:17 and bits 11:8). */
5589 if (!(Tr.Attr.u & 0xfffe0f00))
5590 { /* likely */ }
5591 else
5592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5593
5594 if (!Tr.Attr.n.u1Unusable)
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5598
5599 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5600 || ( !fGstInLongMode
5601 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5602 { /* likely */ }
5603 else
5604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5605
5606 if (!Tr.Attr.n.u1DescType)
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5610
5611 if (Tr.Attr.n.u1Present)
5612 { /* likely */ }
5613 else
5614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5615
5616 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5617 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5621 }
5622
5623 NOREF(pszInstr);
5624 NOREF(pszFailure);
5625 return VINF_SUCCESS;
5626}
5627
5628
5629/**
5630 * Checks guest GDTR and IDTR as part of VM-entry.
5631 *
5632 * @param pVCpu The cross context virtual CPU structure.
5633 * @param pszInstr The VMX instruction name (for logging purposes).
5634 */
5635IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5636{
5637 /*
5638 * GDTR and IDTR.
5639 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5640 */
5641 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5642 const char *const pszFailure = "VM-exit";
5643
5644 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5645 {
5646 /* Base. */
5647 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5648 { /* likely */ }
5649 else
5650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5651
5652 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5653 { /* likely */ }
5654 else
5655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5656 }
5657
5658 /* Limit. */
5659 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5660 { /* likely */ }
5661 else
5662 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5663
5664 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5665 { /* likely */ }
5666 else
5667 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5668
5669 NOREF(pszInstr);
5670 NOREF(pszFailure);
5671 return VINF_SUCCESS;
5672}
5673
5674
5675/**
5676 * Checks guest RIP and RFLAGS as part of VM-entry.
5677 *
5678 * @param pVCpu The cross context virtual CPU structure.
5679 * @param pszInstr The VMX instruction name (for logging purposes).
5680 */
5681IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5682{
5683 /*
5684 * RIP and RFLAGS.
5685 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5686 */
5687 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5688 const char *const pszFailure = "VM-exit";
5689 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5690
5691 /* RIP. */
5692 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5693 {
5694 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5695 if ( !fGstInLongMode
5696 || !AttrCs.n.u1Long)
5697 {
5698 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5699 { /* likely */ }
5700 else
5701 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5702 }
5703
5704 if ( fGstInLongMode
5705 && AttrCs.n.u1Long)
5706 {
5707 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5708 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5709 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5713 }
5714 }
5715
5716 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5717 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5718 : pVmcs->u64GuestRFlags.s.Lo;
5719 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5720 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5721 { /* likely */ }
5722 else
5723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5724
5725 if ( fGstInLongMode
5726 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5727 {
5728 if (!(uGuestRFlags & X86_EFL_VM))
5729 { /* likely */ }
5730 else
5731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5732 }
5733
5734 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5735 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5736 {
5737 if (uGuestRFlags & X86_EFL_IF)
5738 { /* likely */ }
5739 else
5740 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5741 }
5742
5743 NOREF(pszInstr);
5744 NOREF(pszFailure);
5745 return VINF_SUCCESS;
5746}
5747
5748
5749/**
5750 * Checks guest non-register state as part of VM-entry.
5751 *
5752 * @param pVCpu The cross context virtual CPU structure.
5753 * @param pszInstr The VMX instruction name (for logging purposes).
5754 */
5755IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5756{
5757 /*
5758 * Guest non-register state.
5759 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5760 */
5761 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5762 const char *const pszFailure = "VM-exit";
5763
5764 /*
5765 * Activity state.
5766 */
5767 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5768 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5769 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5770 { /* likely */ }
5771 else
5772 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5773
5774 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5775 if ( !AttrSs.n.u2Dpl
5776 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5777 { /* likely */ }
5778 else
5779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5780
5781 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5782 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5783 {
5784 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5785 { /* likely */ }
5786 else
5787 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5788 }
5789
5790 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5791 {
5792 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5793 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5794 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5795 switch (pVmcs->u32GuestActivityState)
5796 {
5797 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5798 {
5799 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5800 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5801 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5802 && ( uVector == X86_XCPT_DB
5803 || uVector == X86_XCPT_MC))
5804 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5805 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5806 { /* likely */ }
5807 else
5808 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5809 break;
5810 }
5811
5812 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5813 {
5814 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5815 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5816 && uVector == X86_XCPT_MC))
5817 { /* likely */ }
5818 else
5819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5820 break;
5821 }
5822
5823 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5824 default:
5825 break;
5826 }
5827 }
5828
5829 /*
5830 * Interruptibility state.
5831 */
5832 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5833 { /* likely */ }
5834 else
5835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5836
5837 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5838 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5839 { /* likely */ }
5840 else
5841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5842
5843 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5844 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5845 { /* likely */ }
5846 else
5847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5848
5849 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5850 {
5851 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5852 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5853 {
5854 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5855 { /* likely */ }
5856 else
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5858 }
5859 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5860 {
5861 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5862 { /* likely */ }
5863 else
5864 {
5865 /*
5866 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5867 * We update the Exit qualification only when blocking-by-STI is set
5868 * without blocking-by-MovSS being set. Although in practise it does not
5869 * make much difference since the order of checks are implementation defined.
5870 */
5871 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5872 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5874 }
5875
5876 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5877 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5878 { /* likely */ }
5879 else
5880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5881 }
5882 }
5883
5884 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5885 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5886 { /* likely */ }
5887 else
5888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5889
5890 /* We don't support SGX yet. So enclave-interruption must not be set. */
5891 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5892 { /* likely */ }
5893 else
5894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5895
5896 /*
5897 * Pending debug exceptions.
5898 */
5899 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5900 ? pVmcs->u64GuestPendingDbgXcpt.u
5901 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5902 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5903 { /* likely */ }
5904 else
5905 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5906
5907 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5908 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5909 {
5910 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5911 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5912 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5913 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5914
5915 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5916 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5917 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5919 }
5920
5921 /* We don't support RTM (Real-time Transactional Memory) yet. */
5922 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5923 { /* likely */ }
5924 else
5925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5926
5927 /*
5928 * VMCS link pointer.
5929 */
5930 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5931 {
5932 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5933 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5934 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5935 { /* likely */ }
5936 else
5937 {
5938 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5940 }
5941
5942 /* Validate the address. */
5943 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5944 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5945 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5946 { /* likely */ }
5947 else
5948 {
5949 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5950 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5951 }
5952
5953 /* Read the VMCS-link pointer from guest memory. */
5954 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5955 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5956 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5957 if (RT_SUCCESS(rc))
5958 { /* likely */ }
5959 else
5960 {
5961 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5963 }
5964
5965 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5966 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5967 { /* likely */ }
5968 else
5969 {
5970 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5972 }
5973
5974 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5975 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5976 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5977 { /* likely */ }
5978 else
5979 {
5980 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5982 }
5983
5984 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5985 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5986 }
5987
5988 NOREF(pszInstr);
5989 NOREF(pszFailure);
5990 return VINF_SUCCESS;
5991}
5992
5993
5994/**
5995 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5996 * VM-entry.
5997 *
5998 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5999 * @param pVCpu The cross context virtual CPU structure.
6000 * @param pszInstr The VMX instruction name (for logging purposes).
6001 * @param pVmcs Pointer to the virtual VMCS.
6002 */
6003IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6004{
6005 /*
6006 * Check PDPTEs.
6007 * See Intel spec. 4.4.1 "PDPTE Registers".
6008 */
6009 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6010 const char *const pszFailure = "VM-exit";
6011
6012 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6013 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6014 if (RT_SUCCESS(rc))
6015 {
6016 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6017 {
6018 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6019 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6020 { /* likely */ }
6021 else
6022 {
6023 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6024 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6026 }
6027 }
6028 }
6029 else
6030 {
6031 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6033 }
6034
6035 NOREF(pszFailure);
6036 NOREF(pszInstr);
6037 return rc;
6038}
6039
6040
6041/**
6042 * Checks guest PDPTEs as part of VM-entry.
6043 *
6044 * @param pVCpu The cross context virtual CPU structure.
6045 * @param pszInstr The VMX instruction name (for logging purposes).
6046 */
6047IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6048{
6049 /*
6050 * Guest PDPTEs.
6051 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6052 */
6053 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6054 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6055
6056 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6057 int rc;
6058 if ( !fGstInLongMode
6059 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6060 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6061 {
6062 /*
6063 * We don't support nested-paging for nested-guests yet.
6064 *
6065 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6066 * rather we need to check the PDPTEs referenced by the guest CR3.
6067 */
6068 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6069 }
6070 else
6071 rc = VINF_SUCCESS;
6072 return rc;
6073}
6074
6075
6076/**
6077 * Checks guest-state as part of VM-entry.
6078 *
6079 * @returns VBox status code.
6080 * @param pVCpu The cross context virtual CPU structure.
6081 * @param pszInstr The VMX instruction name (for logging purposes).
6082 */
6083IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6084{
6085 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6086 if (RT_SUCCESS(rc))
6087 {
6088 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6089 if (RT_SUCCESS(rc))
6090 {
6091 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6092 if (RT_SUCCESS(rc))
6093 {
6094 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6095 if (RT_SUCCESS(rc))
6096 {
6097 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6098 if (RT_SUCCESS(rc))
6099 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6100 }
6101 }
6102 }
6103 }
6104 return rc;
6105}
6106
6107
6108/**
6109 * Checks host-state as part of VM-entry.
6110 *
6111 * @returns VBox status code.
6112 * @param pVCpu The cross context virtual CPU structure.
6113 * @param pszInstr The VMX instruction name (for logging purposes).
6114 */
6115IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6116{
6117 /*
6118 * Host Control Registers and MSRs.
6119 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6120 */
6121 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6122 const char * const pszFailure = "VMFail";
6123
6124 /* CR0 reserved bits. */
6125 {
6126 /* CR0 MB1 bits. */
6127 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6128 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6129 { /* likely */ }
6130 else
6131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6132
6133 /* CR0 MBZ bits. */
6134 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6135 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6139 }
6140
6141 /* CR4 reserved bits. */
6142 {
6143 /* CR4 MB1 bits. */
6144 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6145 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6149
6150 /* CR4 MBZ bits. */
6151 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6152 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6153 { /* likely */ }
6154 else
6155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6156 }
6157
6158 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6159 {
6160 /* CR3 reserved bits. */
6161 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6165
6166 /* SYSENTER ESP and SYSENTER EIP. */
6167 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6168 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6169 { /* likely */ }
6170 else
6171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6172 }
6173
6174 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6175 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6176
6177 /* PAT MSR. */
6178 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6179 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6180 { /* likely */ }
6181 else
6182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6183
6184 /* EFER MSR. */
6185 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6186 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6187 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6188 { /* likely */ }
6189 else
6190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6191
6192 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6193 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6194 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6195 if ( fHostInLongMode == fHostLma
6196 && fHostInLongMode == fHostLme)
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6200
6201 /*
6202 * Host Segment and Descriptor-Table Registers.
6203 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6204 */
6205 /* Selector RPL and TI. */
6206 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6207 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6208 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6209 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6210 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6211 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6212 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6213 { /* likely */ }
6214 else
6215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6216
6217 /* CS and TR selectors cannot be 0. */
6218 if ( pVmcs->HostCs
6219 && pVmcs->HostTr)
6220 { /* likely */ }
6221 else
6222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6223
6224 /* SS cannot be 0 if 32-bit host. */
6225 if ( fHostInLongMode
6226 || pVmcs->HostSs)
6227 { /* likely */ }
6228 else
6229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6230
6231 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6232 {
6233 /* FS, GS, GDTR, IDTR, TR base address. */
6234 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6235 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6236 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6237 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6238 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6239 { /* likely */ }
6240 else
6241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6242 }
6243
6244 /*
6245 * Host address-space size for 64-bit CPUs.
6246 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6247 */
6248 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6249 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6250 {
6251 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6252
6253 /* Logical processor in IA-32e mode. */
6254 if (fCpuInLongMode)
6255 {
6256 if (fHostInLongMode)
6257 {
6258 /* PAE must be set. */
6259 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6260 { /* likely */ }
6261 else
6262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6263
6264 /* RIP must be canonical. */
6265 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6266 { /* likely */ }
6267 else
6268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6269 }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6272 }
6273 else
6274 {
6275 /* Logical processor is outside IA-32e mode. */
6276 if ( !fGstInLongMode
6277 && !fHostInLongMode)
6278 {
6279 /* PCIDE should not be set. */
6280 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6281 { /* likely */ }
6282 else
6283 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6284
6285 /* The high 32-bits of RIP MBZ. */
6286 if (!pVmcs->u64HostRip.s.Hi)
6287 { /* likely */ }
6288 else
6289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6290 }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6293 }
6294 }
6295 else
6296 {
6297 /* Host address-space size for 32-bit CPUs. */
6298 if ( !fGstInLongMode
6299 && !fHostInLongMode)
6300 { /* likely */ }
6301 else
6302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6303 }
6304
6305 NOREF(pszInstr);
6306 NOREF(pszFailure);
6307 return VINF_SUCCESS;
6308}
6309
6310
6311/**
6312 * Checks VM-entry controls fields as part of VM-entry.
6313 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6314 *
6315 * @returns VBox status code.
6316 * @param pVCpu The cross context virtual CPU structure.
6317 * @param pszInstr The VMX instruction name (for logging purposes).
6318 */
6319IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6320{
6321 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6322 const char * const pszFailure = "VMFail";
6323
6324 /* VM-entry controls. */
6325 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6326 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6327 { /* likely */ }
6328 else
6329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6330
6331 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6332 { /* likely */ }
6333 else
6334 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6335
6336 /* Event injection. */
6337 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6338 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6339 {
6340 /* Type and vector. */
6341 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6342 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6343 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6344 if ( !uRsvd
6345 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6346 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6347 { /* likely */ }
6348 else
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6350
6351 /* Exception error code. */
6352 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6353 {
6354 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6355 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6356 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6360
6361 /* Exceptions that provide an error code. */
6362 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6363 && ( uVector == X86_XCPT_DF
6364 || uVector == X86_XCPT_TS
6365 || uVector == X86_XCPT_NP
6366 || uVector == X86_XCPT_SS
6367 || uVector == X86_XCPT_GP
6368 || uVector == X86_XCPT_PF
6369 || uVector == X86_XCPT_AC))
6370 { /* likely */ }
6371 else
6372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6373
6374 /* Exception error-code reserved bits. */
6375 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6376 { /* likely */ }
6377 else
6378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6379
6380 /* Injecting a software interrupt, software exception or privileged software exception. */
6381 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6382 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6383 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6384 {
6385 /* Instruction length must be in the range 0-15. */
6386 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6387 { /* likely */ }
6388 else
6389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6390
6391 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6392 if ( pVmcs->u32EntryInstrLen == 0
6393 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6395 }
6396 }
6397 }
6398
6399 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6400 if (pVmcs->u32EntryMsrLoadCount)
6401 {
6402 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6403 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6404 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6405 { /* likely */ }
6406 else
6407 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6408 }
6409
6410 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6411 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6412
6413 NOREF(pszInstr);
6414 NOREF(pszFailure);
6415 return VINF_SUCCESS;
6416}
6417
6418
6419/**
6420 * Checks VM-exit controls fields as part of VM-entry.
6421 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6422 *
6423 * @returns VBox status code.
6424 * @param pVCpu The cross context virtual CPU structure.
6425 * @param pszInstr The VMX instruction name (for logging purposes).
6426 */
6427IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6428{
6429 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6430 const char * const pszFailure = "VMFail";
6431
6432 /* VM-exit controls. */
6433 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6434 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6435 { /* likely */ }
6436 else
6437 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6438
6439 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6440 { /* likely */ }
6441 else
6442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6443
6444 /* Save preemption timer without activating it. */
6445 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6446 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6447 { /* likely */ }
6448 else
6449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6450
6451 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6452 if (pVmcs->u32ExitMsrStoreCount)
6453 {
6454 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6455 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6456 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6457 { /* likely */ }
6458 else
6459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6460 }
6461
6462 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6463 if (pVmcs->u32ExitMsrLoadCount)
6464 {
6465 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6466 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6467 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6468 { /* likely */ }
6469 else
6470 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6471 }
6472
6473 NOREF(pszInstr);
6474 NOREF(pszFailure);
6475 return VINF_SUCCESS;
6476}
6477
6478
6479/**
6480 * Checks VM-execution controls fields as part of VM-entry.
6481 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6482 *
6483 * @returns VBox status code.
6484 * @param pVCpu The cross context virtual CPU structure.
6485 * @param pszInstr The VMX instruction name (for logging purposes).
6486 *
6487 * @remarks This may update secondary-processor based VM-execution control fields
6488 * in the current VMCS if necessary.
6489 */
6490IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6491{
6492 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6493 const char * const pszFailure = "VMFail";
6494
6495 /* Pin-based VM-execution controls. */
6496 {
6497 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6498 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6499 { /* likely */ }
6500 else
6501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6502
6503 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6507 }
6508
6509 /* Processor-based VM-execution controls. */
6510 {
6511 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6512 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6513 { /* likely */ }
6514 else
6515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6516
6517 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6518 { /* likely */ }
6519 else
6520 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6521 }
6522
6523 /* Secondary processor-based VM-execution controls. */
6524 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6525 {
6526 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6527 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6528 { /* likely */ }
6529 else
6530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6531
6532 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6533 { /* likely */ }
6534 else
6535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6536 }
6537 else
6538 Assert(!pVmcs->u32ProcCtls2);
6539
6540 /* CR3-target count. */
6541 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6542 { /* likely */ }
6543 else
6544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6545
6546 /* I/O bitmaps physical addresses. */
6547 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6548 {
6549 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6550 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6551 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6552 { /* likely */ }
6553 else
6554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6555
6556 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6557 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6558 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6559 { /* likely */ }
6560 else
6561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6562 }
6563
6564 /* MSR bitmap physical address. */
6565 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6566 {
6567 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6568 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6569 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6570 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6571 { /* likely */ }
6572 else
6573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6574
6575 /* Read the MSR bitmap. */
6576 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6577 * implementing fast path. */
6578 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6579 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6580 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6581 if (RT_SUCCESS(rc))
6582 { /* likely */ }
6583 else
6584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6585 }
6586
6587 /* TPR shadow related controls. */
6588 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6589 {
6590 /* Virtual-APIC page physical address. */
6591 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6592 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6593 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6594 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6595 { /* likely */ }
6596 else
6597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6598
6599 /* TPR threshold without virtual-interrupt delivery. */
6600 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6601 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6603
6604 /* TPR threshold and VTPR. */
6605 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6606 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6607 {
6608 /* Read the VTPR from the virtual-APIC page. */
6609 uint8_t u8VTpr;
6610 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6611 if (RT_SUCCESS(rc))
6612 { /* likely */ }
6613 else
6614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6615
6616 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6617 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6618 { /* likely */ }
6619 else
6620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6621 }
6622 }
6623 else
6624 {
6625 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6626 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6627 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6628 { /* likely */ }
6629 else
6630 {
6631 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6633 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6635 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6636 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6637 }
6638 }
6639
6640 /* NMI exiting and virtual-NMIs. */
6641 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6642 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6643 { /* likely */ }
6644 else
6645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6646
6647 /* Virtual-NMIs and NMI-window exiting. */
6648 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6649 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6650 { /* likely */ }
6651 else
6652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6653
6654 /* Virtualize APIC accesses. */
6655 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6656 {
6657 /* APIC-access physical address. */
6658 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6659 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6660 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6661 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6662 { /* likely */ }
6663 else
6664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6665
6666 /*
6667 * Disallow APIC-access page and virtual-APIC page from being the same address.
6668 * Note! This is not an Intel requirement, but one imposed by our implementation.
6669 */
6670 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6671 * redirecting accesses between the APIC-access page and the virtual-APIC
6672 * page. If any nested hypervisor requires this, we can implement it later. */
6673 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6674 {
6675 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6676 if (GCPhysVirtApic != GCPhysApicAccess)
6677 { /* likely */ }
6678 else
6679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6680 }
6681
6682 /*
6683 * Register the handler for the APIC-access page.
6684 *
6685 * We don't deregister the APIC-access page handler during the VM-exit as a different
6686 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6687 *
6688 * We leave the page registered until the first access that happens outside VMX non-root
6689 * mode. Guest software is allowed to access structures such as the APIC-access page
6690 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6691 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6692 *
6693 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6694 */
6695 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6696 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6697 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6698 if (RT_SUCCESS(rc))
6699 { /* likely */ }
6700 else
6701 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6702 }
6703
6704 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6705 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6706 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6710
6711 /* Virtual-interrupt delivery requires external interrupt exiting. */
6712 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6713 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6717
6718 /* VPID. */
6719 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6720 || pVmcs->u16Vpid != 0)
6721 { /* likely */ }
6722 else
6723 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6724
6725 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6726 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6727 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6728 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6729 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6730 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6731 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6732
6733 /* VMCS shadowing. */
6734 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6735 {
6736 /* VMREAD-bitmap physical address. */
6737 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6738 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6739 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6740 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6741 { /* likely */ }
6742 else
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6744
6745 /* VMWRITE-bitmap physical address. */
6746 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6747 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6748 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6749 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6750 { /* likely */ }
6751 else
6752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6753
6754 /* Read the VMREAD-bitmap. */
6755 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6756 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6757 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6758 if (RT_SUCCESS(rc))
6759 { /* likely */ }
6760 else
6761 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6762
6763 /* Read the VMWRITE-bitmap. */
6764 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6765 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6766 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6767 if (RT_SUCCESS(rc))
6768 { /* likely */ }
6769 else
6770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6771 }
6772
6773 NOREF(pszInstr);
6774 NOREF(pszFailure);
6775 return VINF_SUCCESS;
6776}
6777
6778
6779/**
6780 * Loads the guest control registers, debug register and some MSRs as part of
6781 * VM-entry.
6782 *
6783 * @param pVCpu The cross context virtual CPU structure.
6784 */
6785IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6786{
6787 /*
6788 * Load guest control registers, debug registers and MSRs.
6789 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6790 */
6791 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6792
6793 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6794 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6795 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6796 CPUMSetGuestCR0(pVCpu, uGstCr0);
6797 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6798 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6799
6800 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6801 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6802
6803 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6804 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6805 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6806
6807 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6808 {
6809 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6810
6811 /* EFER MSR. */
6812 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6813 {
6814 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6815 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6816 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6817 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6818 if (fGstInLongMode)
6819 {
6820 /* If the nested-guest is in long mode, LMA and LME are both set. */
6821 Assert(fGstPaging);
6822 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6823 }
6824 else
6825 {
6826 /*
6827 * If the nested-guest is outside long mode:
6828 * - With paging: LMA is cleared, LME is cleared.
6829 * - Without paging: LMA is cleared, LME is left unmodified.
6830 */
6831 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6832 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6833 }
6834 }
6835 /* else: see below. */
6836 }
6837
6838 /* PAT MSR. */
6839 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6840 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6841
6842 /* EFER MSR. */
6843 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6844 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6845
6846 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6847 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6848
6849 /* We don't support IA32_BNDCFGS MSR yet. */
6850 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6851
6852 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6853}
6854
6855
6856/**
6857 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6858 *
6859 * @param pVCpu The cross context virtual CPU structure.
6860 */
6861IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6862{
6863 /*
6864 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6865 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6866 */
6867 /* CS, SS, ES, DS, FS, GS. */
6868 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6869 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6870 {
6871 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6872 CPUMSELREG VmcsSelReg;
6873 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6874 AssertRC(rc); NOREF(rc);
6875 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6876 {
6877 pGstSelReg->Sel = VmcsSelReg.Sel;
6878 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6879 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6880 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6881 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6882 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6883 }
6884 else
6885 {
6886 pGstSelReg->Sel = VmcsSelReg.Sel;
6887 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6888 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6889 switch (iSegReg)
6890 {
6891 case X86_SREG_CS:
6892 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6893 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6894 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6895 break;
6896
6897 case X86_SREG_SS:
6898 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6899 pGstSelReg->u32Limit = 0;
6900 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6901 break;
6902
6903 case X86_SREG_ES:
6904 case X86_SREG_DS:
6905 pGstSelReg->u64Base = 0;
6906 pGstSelReg->u32Limit = 0;
6907 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6908 break;
6909
6910 case X86_SREG_FS:
6911 case X86_SREG_GS:
6912 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6913 pGstSelReg->u32Limit = 0;
6914 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6915 break;
6916 }
6917 Assert(pGstSelReg->Attr.n.u1Unusable);
6918 }
6919 }
6920
6921 /* LDTR. */
6922 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6923 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6924 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6925 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6926 {
6927 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6928 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6929 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6930 }
6931 else
6932 {
6933 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6934 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6935 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6936 }
6937
6938 /* TR. */
6939 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6940 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6941 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6942 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6943 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6944 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6945 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6946
6947 /* GDTR. */
6948 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6949 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6950
6951 /* IDTR. */
6952 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6953 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6954}
6955
6956
6957/**
6958 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6959 *
6960 * @returns VBox status code.
6961 * @param pVCpu The cross context virtual CPU structure.
6962 * @param pszInstr The VMX instruction name (for logging purposes).
6963 */
6964IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6965{
6966 /*
6967 * Load guest MSRs.
6968 * See Intel spec. 26.4 "Loading MSRs".
6969 */
6970 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6971 const char *const pszFailure = "VM-exit";
6972
6973 /*
6974 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6975 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6976 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6977 */
6978 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6979 if (!cMsrs)
6980 return VINF_SUCCESS;
6981
6982 /*
6983 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6984 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6985 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6986 */
6987 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6988 if (fIsMsrCountValid)
6989 { /* likely */ }
6990 else
6991 {
6992 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6993 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6994 }
6995
6996 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6997 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6998 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6999 if (RT_SUCCESS(rc))
7000 {
7001 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7002 Assert(pMsr);
7003 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7004 {
7005 if ( !pMsr->u32Reserved
7006 && pMsr->u32Msr != MSR_K8_FS_BASE
7007 && pMsr->u32Msr != MSR_K8_GS_BASE
7008 && pMsr->u32Msr != MSR_K6_EFER
7009 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7010 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7011 {
7012 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7013 if (rcStrict == VINF_SUCCESS)
7014 continue;
7015
7016 /*
7017 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7018 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7019 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7020 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7021 * MSR in ring-0 if possible, or come up with a better, generic solution.
7022 */
7023 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7024 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7025 ? kVmxVDiag_Vmentry_MsrLoadRing3
7026 : kVmxVDiag_Vmentry_MsrLoad;
7027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7028 }
7029 else
7030 {
7031 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7033 }
7034 }
7035 }
7036 else
7037 {
7038 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7040 }
7041
7042 NOREF(pszInstr);
7043 NOREF(pszFailure);
7044 return VINF_SUCCESS;
7045}
7046
7047
7048/**
7049 * Loads the guest-state non-register state as part of VM-entry.
7050 *
7051 * @returns VBox status code.
7052 * @param pVCpu The cross context virtual CPU structure.
7053 *
7054 * @remarks This must be called only after loading the nested-guest register state
7055 * (especially nested-guest RIP).
7056 */
7057IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7058{
7059 /*
7060 * Load guest non-register state.
7061 * See Intel spec. 26.6 "Special Features of VM Entry"
7062 */
7063 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7064
7065 /*
7066 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7067 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7068 *
7069 * See Intel spec. 26.6.1 "Interruptibility State".
7070 */
7071 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7072 if ( !fEntryVectoring
7073 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7074 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7075 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7076 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7077
7078 /* NMI blocking. */
7079 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7080 {
7081 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7082 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7083 else
7084 {
7085 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7086 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7087 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7088 }
7089 }
7090 else
7091 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7092
7093 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7094
7095 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7096 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7097
7098 /* VPID is irrelevant. We don't support VPID yet. */
7099
7100 /* Clear address-range monitoring. */
7101 EMMonitorWaitClear(pVCpu);
7102}
7103
7104
7105/**
7106 * Loads the guest-state as part of VM-entry.
7107 *
7108 * @returns VBox status code.
7109 * @param pVCpu The cross context virtual CPU structure.
7110 * @param pszInstr The VMX instruction name (for logging purposes).
7111 *
7112 * @remarks This must be done after all the necessary steps prior to loading of
7113 * guest-state (e.g. checking various VMCS state).
7114 */
7115IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7116{
7117 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7118 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7119
7120 /*
7121 * Load guest RIP, RSP and RFLAGS.
7122 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7123 */
7124 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7125 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7126 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7127 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7128
7129 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7130 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7131 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7132
7133 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7134
7135 NOREF(pszInstr);
7136 return VINF_SUCCESS;
7137}
7138
7139
7140/**
7141 * Returns whether there are is a pending debug exception on VM-entry.
7142 *
7143 * @param pVCpu The cross context virtual CPU structure.
7144 * @param pszInstr The VMX instruction name (for logging purposes).
7145 */
7146IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7147{
7148 /*
7149 * Pending debug exceptions.
7150 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7151 */
7152 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7153 Assert(pVmcs);
7154
7155 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7156 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7157 if (fPendingDbgXcpt)
7158 {
7159 uint8_t uEntryIntInfoType;
7160 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7161 if (fEntryVectoring)
7162 {
7163 switch (uEntryIntInfoType)
7164 {
7165 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7166 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7167 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7168 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7169 fPendingDbgXcpt = false;
7170 break;
7171
7172 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7173 {
7174 /*
7175 * Whether the pending debug exception for software exceptions other than
7176 * #BP and #OF is delivered after injecting the exception or is discard
7177 * is CPU implementation specific. We will discard them (easier).
7178 */
7179 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7180 if ( uVector != X86_XCPT_BP
7181 && uVector != X86_XCPT_OF)
7182 fPendingDbgXcpt = false;
7183 RT_FALL_THRU();
7184 }
7185 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7186 {
7187 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7188 fPendingDbgXcpt = false;
7189 break;
7190 }
7191 }
7192 }
7193 else
7194 {
7195 /*
7196 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7197 * pending debug exception is held pending or is discarded is CPU implementation
7198 * specific. We will discard them (easier).
7199 */
7200 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7201 fPendingDbgXcpt = false;
7202
7203 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7204 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7205 fPendingDbgXcpt = false;
7206 }
7207 }
7208
7209 NOREF(pszInstr);
7210 return fPendingDbgXcpt;
7211}
7212
7213
7214/**
7215 * Set up the monitor-trap flag (MTF).
7216 *
7217 * @param pVCpu The cross context virtual CPU structure.
7218 * @param pszInstr The VMX instruction name (for logging purposes).
7219 */
7220IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7221{
7222 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7223 Assert(pVmcs);
7224 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7225 {
7226 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7227 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7228 }
7229 else
7230 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7231 NOREF(pszInstr);
7232}
7233
7234
7235/**
7236 * Sets up NMI-window exiting.
7237 *
7238 * @param pVCpu The cross context virtual CPU structure.
7239 * @param pszInstr The VMX instruction name (for logging purposes).
7240 */
7241IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7242{
7243 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7244 Assert(pVmcs);
7245 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7246 {
7247 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7248 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7249 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7250 }
7251 else
7252 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7253 NOREF(pszInstr);
7254}
7255
7256
7257/**
7258 * Sets up interrupt-window exiting.
7259 *
7260 * @param pVCpu The cross context virtual CPU structure.
7261 * @param pszInstr The VMX instruction name (for logging purposes).
7262 */
7263IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7264{
7265 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7266 Assert(pVmcs);
7267 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7268 {
7269 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7270 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7271 }
7272 else
7273 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7274 NOREF(pszInstr);
7275}
7276
7277
7278/**
7279 * Set up the VMX-preemption timer.
7280 *
7281 * @param pVCpu The cross context virtual CPU structure.
7282 * @param pszInstr The VMX instruction name (for logging purposes).
7283 */
7284IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7285{
7286 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7287 Assert(pVmcs);
7288 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7289 {
7290 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7291 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7292 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7293
7294 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7295 }
7296 else
7297 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7298
7299 NOREF(pszInstr);
7300}
7301
7302
7303/**
7304 * Injects an event using TRPM given a VM-entry interruption info. and related
7305 * fields.
7306 *
7307 * @returns VBox status code.
7308 * @param pVCpu The cross context virtual CPU structure.
7309 * @param uEntryIntInfo The VM-entry interruption info.
7310 * @param uErrCode The error code associated with the event if any.
7311 * @param cbInstr The VM-entry instruction length (for software
7312 * interrupts and software exceptions). Pass 0
7313 * otherwise.
7314 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7315 */
7316IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7317 RTGCUINTPTR GCPtrFaultAddress)
7318{
7319 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7320
7321 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7322 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7323 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7324
7325 TRPMEVENT enmTrapType;
7326 switch (uType)
7327 {
7328 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7329 enmTrapType = TRPM_HARDWARE_INT;
7330 break;
7331
7332 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7333 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7334 enmTrapType = TRPM_TRAP;
7335 break;
7336
7337 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7338 enmTrapType = TRPM_SOFTWARE_INT;
7339 break;
7340
7341 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7342 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7343 enmTrapType = TRPM_SOFTWARE_INT;
7344 break;
7345
7346 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7347 Assert(uVector == X86_XCPT_DB);
7348 enmTrapType = TRPM_SOFTWARE_INT;
7349 break;
7350
7351 default:
7352 /* Shouldn't really happen. */
7353 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7354 break;
7355 }
7356
7357 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7358 AssertRCReturn(rc, rc);
7359
7360 if (fErrCodeValid)
7361 TRPMSetErrorCode(pVCpu, uErrCode);
7362
7363 if ( enmTrapType == TRPM_TRAP
7364 && uVector == X86_XCPT_PF)
7365 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7366 else if (enmTrapType == TRPM_SOFTWARE_INT)
7367 TRPMSetInstrLength(pVCpu, cbInstr);
7368
7369 return VINF_SUCCESS;
7370}
7371
7372
7373/**
7374 * Performs event injection (if any) as part of VM-entry.
7375 *
7376 * @param pVCpu The cross context virtual CPU structure.
7377 * @param pszInstr The VMX instruction name (for logging purposes).
7378 */
7379IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7380{
7381 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7382
7383 /*
7384 * Inject events.
7385 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7386 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7387 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7388 * the actually delivery of this event.
7389 *
7390 * See Intel spec. 26.5 "Event Injection".
7391 */
7392 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7393 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7394
7395 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7396 if (fEntryIntInfoValid)
7397 {
7398 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7399 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7400 {
7401 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7402 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7403 return VINF_SUCCESS;
7404 }
7405
7406 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7407 pVCpu->cpum.GstCtx.cr2);
7408 if (RT_SUCCESS(rc))
7409 {
7410 /*
7411 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7412 *
7413 * However, we do it here on VM-entry because while it continues to not be visible to
7414 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7415 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7416 * information field.
7417 *
7418 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7419 */
7420 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7421 }
7422 return rc;
7423 }
7424
7425 /*
7426 * Inject any pending guest debug exception.
7427 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7428 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7429 */
7430 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7431 if (fPendingDbgXcpt)
7432 {
7433 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7434 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7435 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7436 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7437 0 /* GCPtrFaultAddress */);
7438 }
7439
7440 NOREF(pszInstr);
7441 return VINF_SUCCESS;
7442}
7443
7444
7445/**
7446 * Initializes all read-only VMCS fields as part of VM-entry.
7447 *
7448 * @param pVCpu The cross context virtual CPU structure.
7449 */
7450IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7451{
7452 /*
7453 * Any VMCS field which we do not establish on every VM-exit but may potentially
7454 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7455 * specified to be undefined needs to be initialized here.
7456 *
7457 * Thus, it is especially important to clear the Exit qualification field
7458 * since it must be zero for VM-exits where it is not used. Similarly, the
7459 * VM-exit interruption information field's valid bit needs to be cleared for
7460 * the same reasons.
7461 */
7462 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7463 Assert(pVmcs);
7464
7465 /* 16-bit (none currently). */
7466 /* 32-bit. */
7467 pVmcs->u32RoVmInstrError = 0;
7468 pVmcs->u32RoExitReason = 0;
7469 pVmcs->u32RoExitIntInfo = 0;
7470 pVmcs->u32RoExitIntErrCode = 0;
7471 pVmcs->u32RoIdtVectoringInfo = 0;
7472 pVmcs->u32RoIdtVectoringErrCode = 0;
7473 pVmcs->u32RoExitInstrLen = 0;
7474 pVmcs->u32RoExitInstrInfo = 0;
7475
7476 /* 64-bit. */
7477 pVmcs->u64RoGuestPhysAddr.u = 0;
7478
7479 /* Natural-width. */
7480 pVmcs->u64RoExitQual.u = 0;
7481 pVmcs->u64RoIoRcx.u = 0;
7482 pVmcs->u64RoIoRsi.u = 0;
7483 pVmcs->u64RoIoRdi.u = 0;
7484 pVmcs->u64RoIoRip.u = 0;
7485 pVmcs->u64RoGuestLinearAddr.u = 0;
7486}
7487
7488
7489/**
7490 * VMLAUNCH/VMRESUME instruction execution worker.
7491 *
7492 * @returns Strict VBox status code.
7493 * @param pVCpu The cross context virtual CPU structure.
7494 * @param cbInstr The instruction length in bytes.
7495 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7496 * VMXINSTRID_VMRESUME).
7497 *
7498 * @remarks Common VMX instruction checks are already expected to by the caller,
7499 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7500 */
7501IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7502{
7503# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7504 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7505 return VINF_EM_RAW_EMULATE_INSTR;
7506# else
7507 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7508 || uInstrId == VMXINSTRID_VMRESUME);
7509 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7510
7511 /* Nested-guest intercept. */
7512 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7513 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7514
7515 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7516
7517 /*
7518 * Basic VM-entry checks.
7519 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7520 * The checks following that do not have to follow a specific order.
7521 *
7522 * See Intel spec. 26.1 "Basic VM-entry Checks".
7523 */
7524
7525 /* CPL. */
7526 if (pVCpu->iem.s.uCpl == 0)
7527 { /* likely */ }
7528 else
7529 {
7530 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7531 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7532 return iemRaiseGeneralProtectionFault0(pVCpu);
7533 }
7534
7535 /* Current VMCS valid. */
7536 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7537 { /* likely */ }
7538 else
7539 {
7540 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7541 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7542 iemVmxVmFailInvalid(pVCpu);
7543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7544 return VINF_SUCCESS;
7545 }
7546
7547 /* Current VMCS is not a shadow VMCS. */
7548 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7549 { /* likely */ }
7550 else
7551 {
7552 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7553 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7554 iemVmxVmFailInvalid(pVCpu);
7555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7556 return VINF_SUCCESS;
7557 }
7558
7559 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7560 * use block-by-STI here which is not quite correct. */
7561 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7562 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7563 { /* likely */ }
7564 else
7565 {
7566 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7567 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7568 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7569 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7570 return VINF_SUCCESS;
7571 }
7572
7573 if (uInstrId == VMXINSTRID_VMLAUNCH)
7574 {
7575 /* VMLAUNCH with non-clear VMCS. */
7576 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7577 { /* likely */ }
7578 else
7579 {
7580 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7582 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7583 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7584 return VINF_SUCCESS;
7585 }
7586 }
7587 else
7588 {
7589 /* VMRESUME with non-launched VMCS. */
7590 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7591 { /* likely */ }
7592 else
7593 {
7594 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7595 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7596 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7597 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7598 return VINF_SUCCESS;
7599 }
7600 }
7601
7602 /*
7603 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7604 * while entering VMX non-root mode. We do some of this while checking VM-execution
7605 * controls. The guest hypervisor should not make assumptions and cannot expect
7606 * predictable behavior if changes to these structures are made in guest memory while
7607 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7608 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7609 *
7610 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7611 */
7612 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7613 Assert(pVmcs);
7614 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7615
7616 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7617 if (RT_SUCCESS(rc))
7618 {
7619 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7620 if (RT_SUCCESS(rc))
7621 {
7622 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7623 if (RT_SUCCESS(rc))
7624 {
7625 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7626 if (RT_SUCCESS(rc))
7627 {
7628 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7629 iemVmxVmentryInitReadOnlyFields(pVCpu);
7630
7631 /*
7632 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7633 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7634 * VM-exit when required.
7635 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7636 */
7637 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7638
7639 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7640 if (RT_SUCCESS(rc))
7641 {
7642 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7643 if (RT_SUCCESS(rc))
7644 {
7645 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7646 if (RT_SUCCESS(rc))
7647 {
7648 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7649
7650 /* VMLAUNCH instruction must update the VMCS launch state. */
7651 if (uInstrId == VMXINSTRID_VMLAUNCH)
7652 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7653
7654 /* Perform the VMX transition (PGM updates). */
7655 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7656 if (rcStrict == VINF_SUCCESS)
7657 { /* likely */ }
7658 else if (RT_SUCCESS(rcStrict))
7659 {
7660 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7661 VBOXSTRICTRC_VAL(rcStrict)));
7662 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7663 }
7664 else
7665 {
7666 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7667 return rcStrict;
7668 }
7669
7670 /* We've now entered nested-guest execution. */
7671 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7672
7673 /*
7674 * The priority of potential VM-exits during VM-entry is important.
7675 * The priorities of VM-exits and events are listed from highest
7676 * to lowest as follows:
7677 *
7678 * 1. Event injection.
7679 * 2. Trap on task-switch (T flag set in TSS).
7680 * 3. TPR below threshold / APIC-write.
7681 * 4. SMI, INIT.
7682 * 5. MTF exit.
7683 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7684 * 7. VMX-preemption timer.
7685 * 9. NMI-window exit.
7686 * 10. NMI injection.
7687 * 11. Interrupt-window exit.
7688 * 12. Virtual-interrupt injection.
7689 * 13. Interrupt injection.
7690 * 14. Process next instruction (fetch, decode, execute).
7691 */
7692
7693 /* Setup the VMX-preemption timer. */
7694 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7695
7696 /* Setup monitor-trap flag. */
7697 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7698
7699 /* Setup NMI-window exiting. */
7700 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7701
7702 /* Setup interrupt-window exiting. */
7703 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7704
7705 /* Now that we've switched page tables, we can go ahead and inject any event. */
7706 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7707 if (RT_SUCCESS(rcStrict))
7708 {
7709 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7710# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7711 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7712 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7713 if (rcSched != VINF_SUCCESS)
7714 iemSetPassUpStatus(pVCpu, rcSched);
7715# endif
7716 return VINF_SUCCESS;
7717 }
7718
7719 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7720 return rcStrict;
7721 }
7722 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7723 pVmcs->u64RoExitQual.u);
7724 }
7725 }
7726 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7727 pVmcs->u64RoExitQual.u);
7728 }
7729
7730 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7732 return VINF_SUCCESS;
7733 }
7734 }
7735 }
7736
7737 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7738 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7739 return VINF_SUCCESS;
7740# endif
7741}
7742
7743
7744/**
7745 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7746 * (causes a VM-exit) or not.
7747 *
7748 * @returns @c true if the instruction is intercepted, @c false otherwise.
7749 * @param pVCpu The cross context virtual CPU structure.
7750 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7751 * VMX_EXIT_WRMSR).
7752 * @param idMsr The MSR.
7753 */
7754IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7755{
7756 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7757 Assert( uExitReason == VMX_EXIT_RDMSR
7758 || uExitReason == VMX_EXIT_WRMSR);
7759
7760 /* Consult the MSR bitmap if the feature is supported. */
7761 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7762 Assert(pVmcs);
7763 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7764 {
7765 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7766 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7767 if (uExitReason == VMX_EXIT_RDMSR)
7768 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7769 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7770 }
7771
7772 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7773 return true;
7774}
7775
7776
7777/**
7778 * VMREAD common (memory/register) instruction execution worker
7779 *
7780 * @returns Strict VBox status code.
7781 * @param pVCpu The cross context virtual CPU structure.
7782 * @param cbInstr The instruction length in bytes.
7783 * @param pu64Dst Where to write the VMCS value (only updated when
7784 * VINF_SUCCESS is returned).
7785 * @param u64FieldEnc The VMCS field encoding.
7786 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7787 * NULL.
7788 */
7789IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7790 PCVMXVEXITINFO pExitInfo)
7791{
7792 /* Nested-guest intercept. */
7793 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7794 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7795 {
7796 if (pExitInfo)
7797 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7798 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7799 }
7800
7801 /* CPL. */
7802 if (pVCpu->iem.s.uCpl == 0)
7803 { /* likely */ }
7804 else
7805 {
7806 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7807 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7808 return iemRaiseGeneralProtectionFault0(pVCpu);
7809 }
7810
7811 /* VMCS pointer in root mode. */
7812 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7813 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7814 { /* likely */ }
7815 else
7816 {
7817 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7818 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7819 iemVmxVmFailInvalid(pVCpu);
7820 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7821 return VINF_SUCCESS;
7822 }
7823
7824 /* VMCS-link pointer in non-root mode. */
7825 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7826 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7827 { /* likely */ }
7828 else
7829 {
7830 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7831 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7832 iemVmxVmFailInvalid(pVCpu);
7833 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7834 return VINF_SUCCESS;
7835 }
7836
7837 /* Supported VMCS field. */
7838 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7839 { /* likely */ }
7840 else
7841 {
7842 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7843 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7844 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7845 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7846 return VINF_SUCCESS;
7847 }
7848
7849 /*
7850 * Setup reading from the current or shadow VMCS.
7851 */
7852 uint8_t *pbVmcs;
7853 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7854 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7855 else
7856 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7857 Assert(pbVmcs);
7858
7859 VMXVMCSFIELDENC FieldEnc;
7860 FieldEnc.u = u64FieldEnc;
7861 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7862 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7863 uint8_t const uWidthType = (uWidth << 2) | uType;
7864 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7865 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7866 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7867 Assert(offField < VMX_V_VMCS_SIZE);
7868
7869 /*
7870 * Read the VMCS component based on the field's effective width.
7871 *
7872 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7873 * indicates high bits (little endian).
7874 *
7875 * Note! The caller is responsible to trim the result and update registers
7876 * or memory locations are required. Here we just zero-extend to the largest
7877 * type (i.e. 64-bits).
7878 */
7879 uint8_t *pbField = pbVmcs + offField;
7880 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7881 switch (uEffWidth)
7882 {
7883 case VMX_VMCS_ENC_WIDTH_64BIT:
7884 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7885 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7886 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7887 }
7888 return VINF_SUCCESS;
7889}
7890
7891
7892/**
7893 * VMREAD (64-bit register) instruction execution worker.
7894 *
7895 * @returns Strict VBox status code.
7896 * @param pVCpu The cross context virtual CPU structure.
7897 * @param cbInstr The instruction length in bytes.
7898 * @param pu64Dst Where to store the VMCS field's value.
7899 * @param u64FieldEnc The VMCS field encoding.
7900 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7901 * NULL.
7902 */
7903IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7904 PCVMXVEXITINFO pExitInfo)
7905{
7906 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7907 if (rcStrict == VINF_SUCCESS)
7908 {
7909 iemVmxVmreadSuccess(pVCpu, cbInstr);
7910 return VINF_SUCCESS;
7911 }
7912
7913 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7914 return rcStrict;
7915}
7916
7917
7918/**
7919 * VMREAD (32-bit register) instruction execution worker.
7920 *
7921 * @returns Strict VBox status code.
7922 * @param pVCpu The cross context virtual CPU structure.
7923 * @param cbInstr The instruction length in bytes.
7924 * @param pu32Dst Where to store the VMCS field's value.
7925 * @param u32FieldEnc The VMCS field encoding.
7926 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7927 * NULL.
7928 */
7929IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7930 PCVMXVEXITINFO pExitInfo)
7931{
7932 uint64_t u64Dst;
7933 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7934 if (rcStrict == VINF_SUCCESS)
7935 {
7936 *pu32Dst = u64Dst;
7937 iemVmxVmreadSuccess(pVCpu, cbInstr);
7938 return VINF_SUCCESS;
7939 }
7940
7941 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7942 return rcStrict;
7943}
7944
7945
7946/**
7947 * VMREAD (memory) instruction execution worker.
7948 *
7949 * @returns Strict VBox status code.
7950 * @param pVCpu The cross context virtual CPU structure.
7951 * @param cbInstr The instruction length in bytes.
7952 * @param iEffSeg The effective segment register to use with @a u64Val.
7953 * Pass UINT8_MAX if it is a register access.
7954 * @param GCPtrDst The guest linear address to store the VMCS field's
7955 * value.
7956 * @param u64FieldEnc The VMCS field encoding.
7957 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7958 * NULL.
7959 */
7960IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64FieldEnc,
7961 PCVMXVEXITINFO pExitInfo)
7962{
7963 uint64_t u64Dst;
7964 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7965 if (rcStrict == VINF_SUCCESS)
7966 {
7967 /*
7968 * Write the VMCS field's value to the location specified in guest-memory.
7969 */
7970 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7971 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7972 else
7973 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7974 if (rcStrict == VINF_SUCCESS)
7975 {
7976 iemVmxVmreadSuccess(pVCpu, cbInstr);
7977 return VINF_SUCCESS;
7978 }
7979
7980 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7981 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7982 return rcStrict;
7983 }
7984
7985 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7986 return rcStrict;
7987}
7988
7989
7990/**
7991 * VMWRITE instruction execution worker.
7992 *
7993 * @returns Strict VBox status code.
7994 * @param pVCpu The cross context virtual CPU structure.
7995 * @param cbInstr The instruction length in bytes.
7996 * @param iEffSeg The effective segment register to use with @a u64Val.
7997 * Pass UINT8_MAX if it is a register access.
7998 * @param u64Val The value to write (or guest linear address to the
7999 * value), @a iEffSeg will indicate if it's a memory
8000 * operand.
8001 * @param u64FieldEnc The VMCS field encoding.
8002 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8003 * NULL.
8004 */
8005IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64FieldEnc,
8006 PCVMXVEXITINFO pExitInfo)
8007{
8008 /* Nested-guest intercept. */
8009 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8010 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
8011 {
8012 if (pExitInfo)
8013 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8014 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8015 }
8016
8017 /* CPL. */
8018 if (pVCpu->iem.s.uCpl == 0)
8019 { /* likely */ }
8020 else
8021 {
8022 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8023 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8024 return iemRaiseGeneralProtectionFault0(pVCpu);
8025 }
8026
8027 /* VMCS pointer in root mode. */
8028 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8029 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8030 { /* likely */ }
8031 else
8032 {
8033 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8034 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8035 iemVmxVmFailInvalid(pVCpu);
8036 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8037 return VINF_SUCCESS;
8038 }
8039
8040 /* VMCS-link pointer in non-root mode. */
8041 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8042 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8043 { /* likely */ }
8044 else
8045 {
8046 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8047 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8048 iemVmxVmFailInvalid(pVCpu);
8049 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8050 return VINF_SUCCESS;
8051 }
8052
8053 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8054 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8055 if (!fIsRegOperand)
8056 {
8057 /* Read the value from the specified guest memory location. */
8058 VBOXSTRICTRC rcStrict;
8059 RTGCPTR const GCPtrVal = u64Val;
8060 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8061 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8062 else
8063 {
8064 uint32_t u32Val;
8065 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8066 u64Val = u32Val;
8067 }
8068 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8069 {
8070 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8071 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8072 return rcStrict;
8073 }
8074 }
8075 else
8076 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8077
8078 /* Supported VMCS field. */
8079 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8085 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8086 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8087 return VINF_SUCCESS;
8088 }
8089
8090 /* Read-only VMCS field. */
8091 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8092 if ( !fIsFieldReadOnly
8093 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8094 { /* likely */ }
8095 else
8096 {
8097 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8098 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8099 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8100 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8101 return VINF_SUCCESS;
8102 }
8103
8104 /*
8105 * Setup writing to the current or shadow VMCS.
8106 */
8107 uint8_t *pbVmcs;
8108 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8109 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8110 else
8111 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8112 Assert(pbVmcs);
8113
8114 VMXVMCSFIELDENC FieldEnc;
8115 FieldEnc.u = u64FieldEnc;
8116 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8117 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8118 uint8_t const uWidthType = (uWidth << 2) | uType;
8119 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8120 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8121 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8122 Assert(offField < VMX_V_VMCS_SIZE);
8123
8124 /*
8125 * Write the VMCS component based on the field's effective width.
8126 *
8127 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8128 * indicates high bits (little endian).
8129 */
8130 uint8_t *pbField = pbVmcs + offField;
8131 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8132 switch (uEffWidth)
8133 {
8134 case VMX_VMCS_ENC_WIDTH_64BIT:
8135 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8136 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8137 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8138 }
8139
8140 iemVmxVmSucceed(pVCpu);
8141 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8142 return VINF_SUCCESS;
8143}
8144
8145
8146/**
8147 * VMCLEAR instruction execution worker.
8148 *
8149 * @returns Strict VBox status code.
8150 * @param pVCpu The cross context virtual CPU structure.
8151 * @param cbInstr The instruction length in bytes.
8152 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8153 * @param GCPtrVmcs The linear address of the VMCS pointer.
8154 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8155 * NULL.
8156 *
8157 * @remarks Common VMX instruction checks are already expected to by the caller,
8158 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8159 */
8160IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8161 PCVMXVEXITINFO pExitInfo)
8162{
8163 /* Nested-guest intercept. */
8164 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8165 {
8166 if (pExitInfo)
8167 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8168 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8169 }
8170
8171 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8172
8173 /* CPL. */
8174 if (pVCpu->iem.s.uCpl == 0)
8175 { /* likely */ }
8176 else
8177 {
8178 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8179 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8180 return iemRaiseGeneralProtectionFault0(pVCpu);
8181 }
8182
8183 /* Get the VMCS pointer from the location specified by the source memory operand. */
8184 RTGCPHYS GCPhysVmcs;
8185 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8186 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8187 { /* likely */ }
8188 else
8189 {
8190 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8191 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8192 return rcStrict;
8193 }
8194
8195 /* VMCS pointer alignment. */
8196 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8197 { /* likely */ }
8198 else
8199 {
8200 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8201 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8202 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8203 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8204 return VINF_SUCCESS;
8205 }
8206
8207 /* VMCS physical-address width limits. */
8208 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8209 { /* likely */ }
8210 else
8211 {
8212 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8213 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8214 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8215 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8216 return VINF_SUCCESS;
8217 }
8218
8219 /* VMCS is not the VMXON region. */
8220 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8221 { /* likely */ }
8222 else
8223 {
8224 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8225 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8226 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8227 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8228 return VINF_SUCCESS;
8229 }
8230
8231 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8232 restriction imposed by our implementation. */
8233 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8234 { /* likely */ }
8235 else
8236 {
8237 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8238 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8239 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8240 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8241 return VINF_SUCCESS;
8242 }
8243
8244 /*
8245 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8246 *
8247 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8248 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8249 * to 'clear'.
8250 */
8251 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8252 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8253 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8254 {
8255 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8256 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8257 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8258 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8259 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8260 }
8261 else
8262 {
8263 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8264 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8265 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8266 if (RT_FAILURE(rcStrict))
8267 return rcStrict;
8268 }
8269
8270 iemVmxVmSucceed(pVCpu);
8271 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8272 return VINF_SUCCESS;
8273}
8274
8275
8276/**
8277 * VMPTRST instruction execution worker.
8278 *
8279 * @returns Strict VBox status code.
8280 * @param pVCpu The cross context virtual CPU structure.
8281 * @param cbInstr The instruction length in bytes.
8282 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8283 * @param GCPtrVmcs The linear address of where to store the current VMCS
8284 * pointer.
8285 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8286 * NULL.
8287 *
8288 * @remarks Common VMX instruction checks are already expected to by the caller,
8289 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8290 */
8291IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8292 PCVMXVEXITINFO pExitInfo)
8293{
8294 /* Nested-guest intercept. */
8295 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8296 {
8297 if (pExitInfo)
8298 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8299 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8300 }
8301
8302 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8303
8304 /* CPL. */
8305 if (pVCpu->iem.s.uCpl == 0)
8306 { /* likely */ }
8307 else
8308 {
8309 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8311 return iemRaiseGeneralProtectionFault0(pVCpu);
8312 }
8313
8314 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8315 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8316 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8317 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8318 {
8319 iemVmxVmSucceed(pVCpu);
8320 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8321 return rcStrict;
8322 }
8323
8324 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8325 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8326 return rcStrict;
8327}
8328
8329
8330/**
8331 * VMPTRLD instruction execution worker.
8332 *
8333 * @returns Strict VBox status code.
8334 * @param pVCpu The cross context virtual CPU structure.
8335 * @param cbInstr The instruction length in bytes.
8336 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8337 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8338 * NULL.
8339 *
8340 * @remarks Common VMX instruction checks are already expected to by the caller,
8341 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8342 */
8343IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8344 PCVMXVEXITINFO pExitInfo)
8345{
8346 /* Nested-guest intercept. */
8347 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8348 {
8349 if (pExitInfo)
8350 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8351 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8352 }
8353
8354 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8355
8356 /* CPL. */
8357 if (pVCpu->iem.s.uCpl == 0)
8358 { /* likely */ }
8359 else
8360 {
8361 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8362 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8363 return iemRaiseGeneralProtectionFault0(pVCpu);
8364 }
8365
8366 /* Get the VMCS pointer from the location specified by the source memory operand. */
8367 RTGCPHYS GCPhysVmcs;
8368 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8369 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8370 { /* likely */ }
8371 else
8372 {
8373 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8374 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8375 return rcStrict;
8376 }
8377
8378 /* VMCS pointer alignment. */
8379 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8380 { /* likely */ }
8381 else
8382 {
8383 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8384 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8385 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8386 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8387 return VINF_SUCCESS;
8388 }
8389
8390 /* VMCS physical-address width limits. */
8391 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8392 { /* likely */ }
8393 else
8394 {
8395 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8396 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8397 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8398 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8399 return VINF_SUCCESS;
8400 }
8401
8402 /* VMCS is not the VMXON region. */
8403 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8404 { /* likely */ }
8405 else
8406 {
8407 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8408 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8409 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8410 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8411 return VINF_SUCCESS;
8412 }
8413
8414 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8415 restriction imposed by our implementation. */
8416 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8417 { /* likely */ }
8418 else
8419 {
8420 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8421 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8422 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8423 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8424 return VINF_SUCCESS;
8425 }
8426
8427 /* Read just the VMCS revision from the VMCS. */
8428 VMXVMCSREVID VmcsRevId;
8429 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8430 if (RT_SUCCESS(rc))
8431 { /* likely */ }
8432 else
8433 {
8434 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8436 return rc;
8437 }
8438
8439 /*
8440 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8441 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8442 */
8443 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8444 && ( !VmcsRevId.n.fIsShadowVmcs
8445 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8446 { /* likely */ }
8447 else
8448 {
8449 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8450 {
8451 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8452 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8454 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8455 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8456 return VINF_SUCCESS;
8457 }
8458
8459 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8461 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8462 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8463 return VINF_SUCCESS;
8464 }
8465
8466 /*
8467 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8468 * the cache of an existing, current VMCS back to guest memory before loading a new,
8469 * different current VMCS.
8470 */
8471 bool fLoadVmcsFromMem;
8472 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8473 {
8474 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8475 {
8476 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8477 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8478 fLoadVmcsFromMem = true;
8479 }
8480 else
8481 fLoadVmcsFromMem = false;
8482 }
8483 else
8484 fLoadVmcsFromMem = true;
8485
8486 if (fLoadVmcsFromMem)
8487 {
8488 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8489 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8490 sizeof(VMXVVMCS));
8491 if (RT_SUCCESS(rc))
8492 { /* likely */ }
8493 else
8494 {
8495 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8496 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8497 return rc;
8498 }
8499 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8500 }
8501
8502 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8503 iemVmxVmSucceed(pVCpu);
8504 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8505 return VINF_SUCCESS;
8506}
8507
8508
8509/**
8510 * INVVPID instruction execution worker.
8511 *
8512 * @returns Strict VBox status code.
8513 * @param pVCpu The cross context virtual CPU structure.
8514 * @param cbInstr The instruction length in bytes.
8515 * @param iEffSeg The segment of the invvpid descriptor.
8516 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8517 * @param u64InvvpidType The invalidation type.
8518 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8519 * NULL.
8520 *
8521 * @remarks Common VMX instruction checks are already expected to by the caller,
8522 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8523 */
8524IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8525 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8526{
8527 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8528 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8529 return iemRaiseUndefinedOpcode(pVCpu);
8530
8531 /* Nested-guest intercept. */
8532 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8533 {
8534 if (pExitInfo)
8535 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8536 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8537 }
8538
8539 /* CPL. */
8540 if (pVCpu->iem.s.uCpl != 0)
8541 {
8542 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8543 return iemRaiseGeneralProtectionFault0(pVCpu);
8544 }
8545
8546 /*
8547 * Validate INVVPID invalidation type.
8548 *
8549 * The instruction specifies exactly ONE of the supported invalidation types.
8550 *
8551 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8552 * supported. In theory, it's possible for a CPU to not support flushing individual
8553 * addresses but all the other types or any other combination. We do not take any
8554 * shortcuts here by assuming the types we currently expose to the guest.
8555 */
8556 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8557 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8558 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8559 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8560 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8561 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8562 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8563 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8564 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8565 { /* likely */ }
8566 else
8567 {
8568 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8570 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8571 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8572 return VINF_SUCCESS;
8573 }
8574
8575 /*
8576 * Fetch the invvpid descriptor from guest memory.
8577 */
8578 RTUINT128U uDesc;
8579 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8580 if (rcStrict == VINF_SUCCESS)
8581 {
8582 /*
8583 * Validate the descriptor.
8584 */
8585 if (uDesc.s.Lo > 0xfff)
8586 {
8587 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8588 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8589 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8590 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8591 return VINF_SUCCESS;
8592 }
8593
8594 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8595 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8596 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8597 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8598 switch (u64InvvpidType)
8599 {
8600 case VMXTLBFLUSHVPID_INDIV_ADDR:
8601 {
8602 if (uVpid != 0)
8603 {
8604 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8605 {
8606 /* Invalidate mappings for the linear address tagged with VPID. */
8607 /** @todo PGM support for VPID? Currently just flush everything. */
8608 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8609 iemVmxVmSucceed(pVCpu);
8610 }
8611 else
8612 {
8613 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8614 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8615 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8616 }
8617 }
8618 else
8619 {
8620 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8621 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8622 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8623 }
8624 break;
8625 }
8626
8627 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8628 {
8629 if (uVpid != 0)
8630 {
8631 /* Invalidate all mappings with VPID. */
8632 /** @todo PGM support for VPID? Currently just flush everything. */
8633 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8634 iemVmxVmSucceed(pVCpu);
8635 }
8636 else
8637 {
8638 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8640 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8641 }
8642 break;
8643 }
8644
8645 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8646 {
8647 /* Invalidate all mappings with non-zero VPIDs. */
8648 /** @todo PGM support for VPID? Currently just flush everything. */
8649 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8650 iemVmxVmSucceed(pVCpu);
8651 break;
8652 }
8653
8654 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8655 {
8656 if (uVpid != 0)
8657 {
8658 /* Invalidate all mappings with VPID except global translations. */
8659 /** @todo PGM support for VPID? Currently just flush everything. */
8660 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8661 iemVmxVmSucceed(pVCpu);
8662 }
8663 else
8664 {
8665 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8666 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8667 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8668 }
8669 break;
8670 }
8671 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8672 }
8673 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8674 }
8675 return rcStrict;
8676}
8677
8678
8679/**
8680 * VMXON instruction execution worker.
8681 *
8682 * @returns Strict VBox status code.
8683 * @param pVCpu The cross context virtual CPU structure.
8684 * @param cbInstr The instruction length in bytes.
8685 * @param iEffSeg The effective segment register to use with @a
8686 * GCPtrVmxon.
8687 * @param GCPtrVmxon The linear address of the VMXON pointer.
8688 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8689 * NULL.
8690 *
8691 * @remarks Common VMX instruction checks are already expected to by the caller,
8692 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8693 */
8694IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8695 PCVMXVEXITINFO pExitInfo)
8696{
8697 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8698 {
8699 /* CPL. */
8700 if (pVCpu->iem.s.uCpl == 0)
8701 { /* likely */ }
8702 else
8703 {
8704 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8706 return iemRaiseGeneralProtectionFault0(pVCpu);
8707 }
8708
8709 /* A20M (A20 Masked) mode. */
8710 if (PGMPhysIsA20Enabled(pVCpu))
8711 { /* likely */ }
8712 else
8713 {
8714 Log(("vmxon: A20M mode -> #GP(0)\n"));
8715 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8716 return iemRaiseGeneralProtectionFault0(pVCpu);
8717 }
8718
8719 /* CR0. */
8720 {
8721 /* CR0 MB1 bits. */
8722 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8723 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8724 { /* likely */ }
8725 else
8726 {
8727 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8728 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8729 return iemRaiseGeneralProtectionFault0(pVCpu);
8730 }
8731
8732 /* CR0 MBZ bits. */
8733 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8734 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8735 { /* likely */ }
8736 else
8737 {
8738 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8739 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8740 return iemRaiseGeneralProtectionFault0(pVCpu);
8741 }
8742 }
8743
8744 /* CR4. */
8745 {
8746 /* CR4 MB1 bits. */
8747 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8748 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8749 { /* likely */ }
8750 else
8751 {
8752 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8753 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8754 return iemRaiseGeneralProtectionFault0(pVCpu);
8755 }
8756
8757 /* CR4 MBZ bits. */
8758 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8759 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8760 { /* likely */ }
8761 else
8762 {
8763 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8764 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8765 return iemRaiseGeneralProtectionFault0(pVCpu);
8766 }
8767 }
8768
8769 /* Feature control MSR's LOCK and VMXON bits. */
8770 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8771 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8772 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8773 { /* likely */ }
8774 else
8775 {
8776 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8777 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8778 return iemRaiseGeneralProtectionFault0(pVCpu);
8779 }
8780
8781 /* Get the VMXON pointer from the location specified by the source memory operand. */
8782 RTGCPHYS GCPhysVmxon;
8783 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8784 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8785 { /* likely */ }
8786 else
8787 {
8788 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8789 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8790 return rcStrict;
8791 }
8792
8793 /* VMXON region pointer alignment. */
8794 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8795 { /* likely */ }
8796 else
8797 {
8798 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8799 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8800 iemVmxVmFailInvalid(pVCpu);
8801 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8802 return VINF_SUCCESS;
8803 }
8804
8805 /* VMXON physical-address width limits. */
8806 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8807 { /* likely */ }
8808 else
8809 {
8810 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8811 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8812 iemVmxVmFailInvalid(pVCpu);
8813 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8814 return VINF_SUCCESS;
8815 }
8816
8817 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8818 restriction imposed by our implementation. */
8819 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8820 { /* likely */ }
8821 else
8822 {
8823 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8825 iemVmxVmFailInvalid(pVCpu);
8826 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8827 return VINF_SUCCESS;
8828 }
8829
8830 /* Read the VMCS revision ID from the VMXON region. */
8831 VMXVMCSREVID VmcsRevId;
8832 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8833 if (RT_SUCCESS(rc))
8834 { /* likely */ }
8835 else
8836 {
8837 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8838 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8839 return rc;
8840 }
8841
8842 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8843 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8844 { /* likely */ }
8845 else
8846 {
8847 /* Revision ID mismatch. */
8848 if (!VmcsRevId.n.fIsShadowVmcs)
8849 {
8850 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8851 VmcsRevId.n.u31RevisionId));
8852 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8853 iemVmxVmFailInvalid(pVCpu);
8854 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8855 return VINF_SUCCESS;
8856 }
8857
8858 /* Shadow VMCS disallowed. */
8859 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8860 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8861 iemVmxVmFailInvalid(pVCpu);
8862 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8863 return VINF_SUCCESS;
8864 }
8865
8866 /*
8867 * Record that we're in VMX operation, block INIT, block and disable A20M.
8868 */
8869 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8870 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8871 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8872
8873 /* Clear address-range monitoring. */
8874 EMMonitorWaitClear(pVCpu);
8875 /** @todo NSTVMX: Intel PT. */
8876
8877 iemVmxVmSucceed(pVCpu);
8878 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8879 return VINF_SUCCESS;
8880 }
8881 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8882 {
8883 /* Nested-guest intercept. */
8884 if (pExitInfo)
8885 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8886 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8887 }
8888
8889 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8890
8891 /* CPL. */
8892 if (pVCpu->iem.s.uCpl > 0)
8893 {
8894 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8895 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8896 return iemRaiseGeneralProtectionFault0(pVCpu);
8897 }
8898
8899 /* VMXON when already in VMX root mode. */
8900 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8901 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8902 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8903 return VINF_SUCCESS;
8904}
8905
8906
8907/**
8908 * Implements 'VMXOFF'.
8909 *
8910 * @remarks Common VMX instruction checks are already expected to by the caller,
8911 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8912 */
8913IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8914{
8915 /* Nested-guest intercept. */
8916 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8917 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8918
8919 /* CPL. */
8920 if (pVCpu->iem.s.uCpl == 0)
8921 { /* likely */ }
8922 else
8923 {
8924 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8925 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8926 return iemRaiseGeneralProtectionFault0(pVCpu);
8927 }
8928
8929 /* Dual monitor treatment of SMIs and SMM. */
8930 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8931 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8932 { /* likely */ }
8933 else
8934 {
8935 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8936 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8937 return VINF_SUCCESS;
8938 }
8939
8940 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8941 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8942 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8943
8944 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8945 { /** @todo NSTVMX: Unblock SMI. */ }
8946
8947 EMMonitorWaitClear(pVCpu);
8948 /** @todo NSTVMX: Unblock and enable A20M. */
8949
8950 iemVmxVmSucceed(pVCpu);
8951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8952 return VINF_SUCCESS;
8953}
8954
8955
8956/**
8957 * Implements 'VMXON'.
8958 */
8959IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8960{
8961 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8962}
8963
8964
8965/**
8966 * Implements 'VMLAUNCH'.
8967 */
8968IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8969{
8970 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8971}
8972
8973
8974/**
8975 * Implements 'VMRESUME'.
8976 */
8977IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8978{
8979 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8980}
8981
8982
8983/**
8984 * Implements 'VMPTRLD'.
8985 */
8986IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8987{
8988 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8989}
8990
8991
8992/**
8993 * Implements 'VMPTRST'.
8994 */
8995IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8996{
8997 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8998}
8999
9000
9001/**
9002 * Implements 'VMCLEAR'.
9003 */
9004IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9005{
9006 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9007}
9008
9009
9010/**
9011 * Implements 'VMWRITE' register.
9012 */
9013IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
9014{
9015 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64FieldEnc, NULL /* pExitInfo */);
9016}
9017
9018
9019/**
9020 * Implements 'VMWRITE' memory.
9021 */
9022IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
9023{
9024 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
9025}
9026
9027
9028/**
9029 * Implements 'VMREAD' register (64-bit).
9030 */
9031IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
9032{
9033 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
9034}
9035
9036
9037/**
9038 * Implements 'VMREAD' register (32-bit).
9039 */
9040IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
9041{
9042 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
9043}
9044
9045
9046/**
9047 * Implements 'VMREAD' memory, 64-bit register.
9048 */
9049IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
9050{
9051 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
9052}
9053
9054
9055/**
9056 * Implements 'VMREAD' memory, 32-bit register.
9057 */
9058IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
9059{
9060 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
9061}
9062
9063
9064/**
9065 * Implements 'INVVPID'.
9066 */
9067IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9068{
9069 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9070}
9071
9072
9073/**
9074 * Implements VMX's implementation of PAUSE.
9075 */
9076IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9077{
9078 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9079 {
9080 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9081 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9082 return rcStrict;
9083 }
9084
9085 /*
9086 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9087 * a VM-exit, the instruction operates normally.
9088 */
9089 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9090 return VINF_SUCCESS;
9091}
9092
9093#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9094
9095
9096/**
9097 * Implements 'VMCALL'.
9098 */
9099IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9100{
9101#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9102 /* Nested-guest intercept. */
9103 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9104 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9105#endif
9106
9107 /* Join forces with vmmcall. */
9108 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9109}
9110
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