VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79104

Last change on this file since 79104 was 79104, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Fix typo in iemVmxVmexitApicAccess.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79104 2019-06-12 09:43:24Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64VmcsField The VMCS field.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64VmcsField)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the Exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param u64ExitQual The Exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = u64ExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitIntInfo The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
1984 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
1986 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1987 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1988 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1989 CPUMSetGuestCR0(pVCpu, uValidCr0);
1990 }
1991
1992 /* CR4. */
1993 {
1994 /* CR4 MB1 bits are not modified. */
1995 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1996 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1997 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1998 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1999 if (fHostInLongMode)
2000 uValidCr4 |= X86_CR4_PAE;
2001 else
2002 uValidCr4 &= ~X86_CR4_PCIDE;
2003 CPUMSetGuestCR4(pVCpu, uValidCr4);
2004 }
2005
2006 /* CR3 (host value validated while checking host-state during VM-entry). */
2007 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2008
2009 /* DR7. */
2010 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2011
2012 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2013
2014 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2015 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2016 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2017 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2018
2019 /* FS, GS bases are loaded later while we load host segment registers. */
2020
2021 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2022 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2023 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2024 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2025 {
2026 if (fHostInLongMode)
2027 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2028 else
2029 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2030 }
2031
2032 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2033
2034 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2035 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2036 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2037
2038 /* We don't support IA32_BNDCFGS MSR yet. */
2039}
2040
2041
2042/**
2043 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2044 *
2045 * @param pVCpu The cross context virtual CPU structure.
2046 */
2047IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2048{
2049 /*
2050 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2051 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2052 *
2053 * Warning! Be careful to not touch fields that are reserved by VT-x,
2054 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2055 */
2056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2057 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2058
2059 /* CS, SS, ES, DS, FS, GS. */
2060 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2061 {
2062 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2063 bool const fUnusable = RT_BOOL(HostSel == 0);
2064 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2065
2066 /* Selector. */
2067 pSelReg->Sel = HostSel;
2068 pSelReg->ValidSel = HostSel;
2069 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2070
2071 /* Limit. */
2072 pSelReg->u32Limit = 0xffffffff;
2073
2074 /* Base. */
2075 pSelReg->u64Base = 0;
2076
2077 /* Attributes. */
2078 if (iSegReg == X86_SREG_CS)
2079 {
2080 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2081 pSelReg->Attr.n.u1DescType = 1;
2082 pSelReg->Attr.n.u2Dpl = 0;
2083 pSelReg->Attr.n.u1Present = 1;
2084 pSelReg->Attr.n.u1Long = fHostInLongMode;
2085 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2086 pSelReg->Attr.n.u1Granularity = 1;
2087 Assert(!pSelReg->Attr.n.u1Unusable);
2088 Assert(!fUnusable);
2089 }
2090 else
2091 {
2092 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2093 pSelReg->Attr.n.u1DescType = 1;
2094 pSelReg->Attr.n.u2Dpl = 0;
2095 pSelReg->Attr.n.u1Present = 1;
2096 pSelReg->Attr.n.u1DefBig = 1;
2097 pSelReg->Attr.n.u1Granularity = 1;
2098 pSelReg->Attr.n.u1Unusable = fUnusable;
2099 }
2100 }
2101
2102 /* FS base. */
2103 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2104 || fHostInLongMode)
2105 {
2106 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2107 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2108 }
2109
2110 /* GS base. */
2111 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2112 || fHostInLongMode)
2113 {
2114 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2115 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2116 }
2117
2118 /* TR. */
2119 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2120 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2121 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2122 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2123 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2124 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2125 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2126 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2127 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2128 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2132
2133 /* LDTR (Warning! do not touch the base and limits here). */
2134 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2135 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2136 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2137 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2138
2139 /* GDTR. */
2140 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2141 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2142 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2143
2144 /* IDTR.*/
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2146 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2147 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2148}
2149
2150
2151/**
2152 * Checks host PDPTes as part of VM-exit.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param uExitReason The VM-exit reason (for logging purposes).
2156 */
2157IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2158{
2159 /*
2160 * Check host PDPTEs.
2161 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2162 */
2163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2164 const char *const pszFailure = "VMX-abort";
2165 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2166
2167 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2168 && !fHostInLongMode)
2169 {
2170 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2171 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2172 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2173 if (RT_SUCCESS(rc))
2174 {
2175 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2176 {
2177 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2178 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2179 { /* likely */ }
2180 else
2181 {
2182 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2183 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2184 }
2185 }
2186 }
2187 else
2188 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2189 }
2190
2191 NOREF(pszFailure);
2192 NOREF(uExitReason);
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2199 *
2200 * @returns VBox status code.
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param pszInstr The VMX instruction name (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Load host MSRs.
2208 * See Intel spec. 27.6 "Loading MSRs".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212
2213 /*
2214 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2215 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2216 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2217 */
2218 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2219 if (!cMsrs)
2220 return VINF_SUCCESS;
2221
2222 /*
2223 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2224 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2225 * implementation causes a VMX-abort followed by a triple-fault.
2226 */
2227 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2228 if (fIsMsrCountValid)
2229 { /* likely */ }
2230 else
2231 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2232
2233 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2234 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2235 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2236 if (RT_SUCCESS(rc))
2237 {
2238 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2239 Assert(pMsr);
2240 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2241 {
2242 if ( !pMsr->u32Reserved
2243 && pMsr->u32Msr != MSR_K8_FS_BASE
2244 && pMsr->u32Msr != MSR_K8_GS_BASE
2245 && pMsr->u32Msr != MSR_K6_EFER
2246 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2247 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2248 {
2249 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2250 if (rcStrict == VINF_SUCCESS)
2251 continue;
2252
2253 /*
2254 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2255 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2256 * recording the MSR index in the auxiliary info. field and indicated further by our
2257 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2258 * if possible, or come up with a better, generic solution.
2259 */
2260 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2261 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2262 ? kVmxVDiag_Vmexit_MsrLoadRing3
2263 : kVmxVDiag_Vmexit_MsrLoad;
2264 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2265 }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2268 }
2269 }
2270 else
2271 {
2272 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2273 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2274 }
2275
2276 NOREF(uExitReason);
2277 NOREF(pszFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Loads the host state as part of VM-exit.
2284 *
2285 * @returns Strict VBox status code.
2286 * @param pVCpu The cross context virtual CPU structure.
2287 * @param uExitReason The VM-exit reason (for logging purposes).
2288 */
2289IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2290{
2291 /*
2292 * Load host state.
2293 * See Intel spec. 27.5 "Loading Host State".
2294 */
2295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2296 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2297
2298 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2299 if ( CPUMIsGuestInLongMode(pVCpu)
2300 && !fHostInLongMode)
2301 {
2302 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2303 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2304 }
2305
2306 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2307 iemVmxVmexitLoadHostSegRegs(pVCpu);
2308
2309 /*
2310 * Load host RIP, RSP and RFLAGS.
2311 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2312 */
2313 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2314 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2315 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2316
2317 /* Clear address range monitoring. */
2318 EMMonitorWaitClear(pVCpu);
2319
2320 /* Perform the VMX transition (PGM updates). */
2321 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2322 if (rcStrict == VINF_SUCCESS)
2323 {
2324 /* Check host PDPTEs (only when we've fully switched page tables_. */
2325 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2326 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2327 if (RT_FAILURE(rc))
2328 {
2329 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2330 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2331 }
2332 }
2333 else if (RT_SUCCESS(rcStrict))
2334 {
2335 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2336 uExitReason));
2337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2338 }
2339 else
2340 {
2341 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2342 return VBOXSTRICTRC_VAL(rcStrict);
2343 }
2344
2345 Assert(rcStrict == VINF_SUCCESS);
2346
2347 /* Load MSRs from the VM-exit auto-load MSR area. */
2348 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2349 if (RT_FAILURE(rc))
2350 {
2351 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2352 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2353 }
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/**
2359 * Gets VM-exit instruction information along with any displacement for an
2360 * instruction VM-exit.
2361 *
2362 * @returns The VM-exit instruction information.
2363 * @param pVCpu The cross context virtual CPU structure.
2364 * @param uExitReason The VM-exit reason.
2365 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2366 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2367 * NULL.
2368 */
2369IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2370{
2371 RTGCPTR GCPtrDisp;
2372 VMXEXITINSTRINFO ExitInstrInfo;
2373 ExitInstrInfo.u = 0;
2374
2375 /*
2376 * Get and parse the ModR/M byte from our decoded opcodes.
2377 */
2378 uint8_t bRm;
2379 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2380 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2381 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2382 {
2383 /*
2384 * ModR/M indicates register addressing.
2385 *
2386 * The primary/secondary register operands are reported in the iReg1 or iReg2
2387 * fields depending on whether it is a read/write form.
2388 */
2389 uint8_t idxReg1;
2390 uint8_t idxReg2;
2391 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2392 {
2393 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2394 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2395 }
2396 else
2397 {
2398 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2399 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2400 }
2401 ExitInstrInfo.All.u2Scaling = 0;
2402 ExitInstrInfo.All.iReg1 = idxReg1;
2403 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2404 ExitInstrInfo.All.fIsRegOperand = 1;
2405 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2406 ExitInstrInfo.All.iSegReg = 0;
2407 ExitInstrInfo.All.iIdxReg = 0;
2408 ExitInstrInfo.All.fIdxRegInvalid = 1;
2409 ExitInstrInfo.All.iBaseReg = 0;
2410 ExitInstrInfo.All.fBaseRegInvalid = 1;
2411 ExitInstrInfo.All.iReg2 = idxReg2;
2412
2413 /* Displacement not applicable for register addressing. */
2414 GCPtrDisp = 0;
2415 }
2416 else
2417 {
2418 /*
2419 * ModR/M indicates memory addressing.
2420 */
2421 uint8_t uScale = 0;
2422 bool fBaseRegValid = false;
2423 bool fIdxRegValid = false;
2424 uint8_t iBaseReg = 0;
2425 uint8_t iIdxReg = 0;
2426 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2427 {
2428 /*
2429 * Parse the ModR/M, displacement for 16-bit addressing mode.
2430 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2431 */
2432 uint16_t u16Disp = 0;
2433 uint8_t const offDisp = offModRm + sizeof(bRm);
2434 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2435 {
2436 /* Displacement without any registers. */
2437 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2438 }
2439 else
2440 {
2441 /* Register (index and base). */
2442 switch (bRm & X86_MODRM_RM_MASK)
2443 {
2444 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2445 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2446 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2447 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2448 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2449 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2450 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2451 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2452 }
2453
2454 /* Register + displacement. */
2455 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2456 {
2457 case 0: break;
2458 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2459 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2460 default:
2461 {
2462 /* Register addressing, handled at the beginning. */
2463 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2464 break;
2465 }
2466 }
2467 }
2468
2469 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2470 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2471 }
2472 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2473 {
2474 /*
2475 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2476 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2477 */
2478 uint32_t u32Disp = 0;
2479 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2480 {
2481 /* Displacement without any registers. */
2482 uint8_t const offDisp = offModRm + sizeof(bRm);
2483 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2484 }
2485 else
2486 {
2487 /* Register (and perhaps scale, index and base). */
2488 uint8_t offDisp = offModRm + sizeof(bRm);
2489 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2490 if (iBaseReg == 4)
2491 {
2492 /* An SIB byte follows the ModR/M byte, parse it. */
2493 uint8_t bSib;
2494 uint8_t const offSib = offModRm + sizeof(bRm);
2495 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2496
2497 /* A displacement may follow SIB, update its offset. */
2498 offDisp += sizeof(bSib);
2499
2500 /* Get the scale. */
2501 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2502
2503 /* Get the index register. */
2504 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2505 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2506
2507 /* Get the base register. */
2508 iBaseReg = bSib & X86_SIB_BASE_MASK;
2509 fBaseRegValid = true;
2510 if (iBaseReg == 5)
2511 {
2512 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2513 {
2514 /* Mod is 0 implies a 32-bit displacement with no base. */
2515 fBaseRegValid = false;
2516 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2517 }
2518 else
2519 {
2520 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2521 iBaseReg = X86_GREG_xBP;
2522 }
2523 }
2524 }
2525
2526 /* Register + displacement. */
2527 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2528 {
2529 case 0: /* Handled above */ break;
2530 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2531 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2532 default:
2533 {
2534 /* Register addressing, handled at the beginning. */
2535 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2536 break;
2537 }
2538 }
2539 }
2540
2541 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2542 }
2543 else
2544 {
2545 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2546
2547 /*
2548 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2549 * See Intel instruction spec. 2.2 "IA-32e Mode".
2550 */
2551 uint64_t u64Disp = 0;
2552 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2553 if (fRipRelativeAddr)
2554 {
2555 /*
2556 * RIP-relative addressing mode.
2557 *
2558 * The displacement is 32-bit signed implying an offset range of +/-2G.
2559 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2560 */
2561 uint8_t const offDisp = offModRm + sizeof(bRm);
2562 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2563 }
2564 else
2565 {
2566 uint8_t offDisp = offModRm + sizeof(bRm);
2567
2568 /*
2569 * Register (and perhaps scale, index and base).
2570 *
2571 * REX.B extends the most-significant bit of the base register. However, REX.B
2572 * is ignored while determining whether an SIB follows the opcode. Hence, we
2573 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2574 *
2575 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2576 */
2577 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2578 if (iBaseReg == 4)
2579 {
2580 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2581 uint8_t bSib;
2582 uint8_t const offSib = offModRm + sizeof(bRm);
2583 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2584
2585 /* Displacement may follow SIB, update its offset. */
2586 offDisp += sizeof(bSib);
2587
2588 /* Get the scale. */
2589 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2590
2591 /* Get the index. */
2592 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2593 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2594
2595 /* Get the base. */
2596 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2597 fBaseRegValid = true;
2598 if (iBaseReg == 5)
2599 {
2600 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2601 {
2602 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2603 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2604 }
2605 else
2606 {
2607 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2608 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2609 }
2610 }
2611 }
2612 iBaseReg |= pVCpu->iem.s.uRexB;
2613
2614 /* Register + displacement. */
2615 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2616 {
2617 case 0: /* Handled above */ break;
2618 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2619 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2620 default:
2621 {
2622 /* Register addressing, handled at the beginning. */
2623 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2624 break;
2625 }
2626 }
2627 }
2628
2629 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2630 }
2631
2632 /*
2633 * The primary or secondary register operand is reported in iReg2 depending
2634 * on whether the primary operand is in read/write form.
2635 */
2636 uint8_t idxReg2;
2637 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2638 {
2639 idxReg2 = bRm & X86_MODRM_RM_MASK;
2640 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2641 idxReg2 |= pVCpu->iem.s.uRexB;
2642 }
2643 else
2644 {
2645 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2646 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2647 idxReg2 |= pVCpu->iem.s.uRexReg;
2648 }
2649 ExitInstrInfo.All.u2Scaling = uScale;
2650 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2651 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2652 ExitInstrInfo.All.fIsRegOperand = 0;
2653 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2654 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2655 ExitInstrInfo.All.iIdxReg = iIdxReg;
2656 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2657 ExitInstrInfo.All.iBaseReg = iBaseReg;
2658 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2659 ExitInstrInfo.All.iReg2 = idxReg2;
2660 }
2661
2662 /*
2663 * Handle exceptions to the norm for certain instructions.
2664 * (e.g. some instructions convey an instruction identity in place of iReg2).
2665 */
2666 switch (uExitReason)
2667 {
2668 case VMX_EXIT_GDTR_IDTR_ACCESS:
2669 {
2670 Assert(VMXINSTRID_IS_VALID(uInstrId));
2671 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2672 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2673 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2674 break;
2675 }
2676
2677 case VMX_EXIT_LDTR_TR_ACCESS:
2678 {
2679 Assert(VMXINSTRID_IS_VALID(uInstrId));
2680 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2681 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2682 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2683 break;
2684 }
2685
2686 case VMX_EXIT_RDRAND:
2687 case VMX_EXIT_RDSEED:
2688 {
2689 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2690 break;
2691 }
2692 }
2693
2694 /* Update displacement and return the constructed VM-exit instruction information field. */
2695 if (pGCPtrDisp)
2696 *pGCPtrDisp = GCPtrDisp;
2697
2698 return ExitInstrInfo.u;
2699}
2700
2701
2702/**
2703 * VMX VM-exit handler.
2704 *
2705 * @returns Strict VBox status code.
2706 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2707 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2708 * triple-fault.
2709 *
2710 * @param pVCpu The cross context virtual CPU structure.
2711 * @param uExitReason The VM-exit reason.
2712 * @param u64ExitQual The Exit qualification.
2713 */
2714IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2715{
2716# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2717 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2718 return VINF_EM_RAW_EMULATE_INSTR;
2719# else
2720 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2721 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2722 | CPUMCTX_EXTRN_EFER /* MSRs */
2723 | CPUMCTX_EXTRN_SYSENTER_MSRS
2724 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2725 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2726 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2727 | CPUMCTX_EXTRN_TR /* Task register */
2728 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2729 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2730
2731 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2732 Assert(pVmcs);
2733
2734 /* Ensure VM-entry interruption information valid bit isn't set. */
2735 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2736
2737 /*
2738 * Update the VM-exit reason and Exit qualification.
2739 * Other VMCS read-only data fields are expected to be updated by the caller already.
2740 */
2741 pVmcs->u32RoExitReason = uExitReason;
2742 pVmcs->u64RoExitQual.u = u64ExitQual;
2743 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2744 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2745
2746 /*
2747 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2748 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2749 */
2750 {
2751 uint8_t uVector;
2752 uint32_t fFlags;
2753 uint32_t uErrCode;
2754 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2755 if (fInEventDelivery)
2756 {
2757 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2758 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2759 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2760 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2761 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2762 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2763 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2764 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2765 }
2766 }
2767
2768 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2769 Assert(pVmcs->u64RoIoRcx.u == 0);
2770 Assert(pVmcs->u64RoIoRsi.u == 0);
2771 Assert(pVmcs->u64RoIoRdi.u == 0);
2772 Assert(pVmcs->u64RoIoRip.u == 0);
2773
2774 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2775 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2776 {
2777 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2778 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2779 }
2780
2781 /*
2782 * Save the guest state back into the VMCS.
2783 * We only need to save the state when the VM-entry was successful.
2784 */
2785 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2786 if (!fVmentryFailed)
2787 {
2788 /*
2789 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2790 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2791 *
2792 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2793 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2794 * as guest-CPU state would not been modified. Hence for now, we do this only when
2795 * the VM-entry succeeded.
2796 */
2797 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2798 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2799 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2800 {
2801 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2802 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2803 else
2804 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2805 }
2806
2807 /*
2808 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2809 * occurs in enclave mode/SMM which we don't support yet.
2810 *
2811 * If we ever add support for it, we can pass just the lower bits to the functions
2812 * below, till then an assert should suffice.
2813 */
2814 Assert(!RT_HI_U16(uExitReason));
2815
2816 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2817 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2818 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2819 if (RT_SUCCESS(rc))
2820 { /* likely */ }
2821 else
2822 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2823
2824 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2825 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2826 }
2827 else
2828 {
2829 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2830 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2831 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2832 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2833 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2834 }
2835
2836 /*
2837 * Clear any pending VMX nested-guest force-flags.
2838 * These force-flags have no effect on guest execution and will
2839 * be re-evaluated and setup on the next nested-guest VM-entry.
2840 */
2841 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2842 | VMCPU_FF_VMX_MTF
2843 | VMCPU_FF_VMX_APIC_WRITE
2844 | VMCPU_FF_VMX_INT_WINDOW
2845 | VMCPU_FF_VMX_NMI_WINDOW);
2846
2847 /* Restore the host (outer guest) state. */
2848 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2849 if (RT_SUCCESS(rcStrict))
2850 {
2851 Assert(rcStrict == VINF_SUCCESS);
2852 rcStrict = VINF_VMX_VMEXIT;
2853 }
2854 else
2855 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2856
2857 /* Notify HM that we've completed the VM-exit. */
2858 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2859
2860 /* We're no longer in nested-guest execution mode. */
2861 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2862
2863# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2864 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2865 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2866 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2867 if (rcSched != VINF_SUCCESS)
2868 iemSetPassUpStatus(pVCpu, rcSched);
2869# endif
2870 return rcStrict;
2871# endif
2872}
2873
2874
2875/**
2876 * VMX VM-exit handler for VM-exits due to instruction execution.
2877 *
2878 * This is intended for instructions where the caller provides all the relevant
2879 * VM-exit information.
2880 *
2881 * @returns Strict VBox status code.
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param pExitInfo Pointer to the VM-exit information.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2886{
2887 /*
2888 * For instructions where any of the following fields are not applicable:
2889 * - Exit qualification must be cleared.
2890 * - VM-exit instruction info. is undefined.
2891 * - Guest-linear address is undefined.
2892 * - Guest-physical address is undefined.
2893 *
2894 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2895 * instruction execution. For VM-exits that are not due to instruction execution this
2896 * field is undefined.
2897 *
2898 * In our implementation in IEM, all undefined fields are generally cleared. However,
2899 * if the caller supplies information (from say the physical CPU directly) it is
2900 * then possible that the undefined fields are not cleared.
2901 *
2902 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2903 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2904 */
2905 Assert(pExitInfo);
2906 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2907 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2908 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2909
2910 /* Update all the relevant fields from the VM-exit instruction information struct. */
2911 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2912 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2913 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2914 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2915
2916 /* Perform the VM-exit. */
2917 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2918}
2919
2920
2921/**
2922 * VMX VM-exit handler for VM-exits due to instruction execution.
2923 *
2924 * This is intended for instructions that only provide the VM-exit instruction
2925 * length.
2926 *
2927 * @param pVCpu The cross context virtual CPU structure.
2928 * @param uExitReason The VM-exit reason.
2929 * @param cbInstr The instruction length in bytes.
2930 */
2931IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2932{
2933 VMXVEXITINFO ExitInfo;
2934 RT_ZERO(ExitInfo);
2935 ExitInfo.uReason = uExitReason;
2936 ExitInfo.cbInstr = cbInstr;
2937
2938#ifdef VBOX_STRICT
2939 /*
2940 * To prevent us from shooting ourselves in the foot.
2941 * The follow instructions should convey more than just the instruction length.
2942 */
2943 switch (uExitReason)
2944 {
2945 case VMX_EXIT_INVEPT:
2946 case VMX_EXIT_INVPCID:
2947 case VMX_EXIT_INVVPID:
2948 case VMX_EXIT_LDTR_TR_ACCESS:
2949 case VMX_EXIT_GDTR_IDTR_ACCESS:
2950 case VMX_EXIT_VMCLEAR:
2951 case VMX_EXIT_VMPTRLD:
2952 case VMX_EXIT_VMPTRST:
2953 case VMX_EXIT_VMREAD:
2954 case VMX_EXIT_VMWRITE:
2955 case VMX_EXIT_VMXON:
2956 case VMX_EXIT_XRSTORS:
2957 case VMX_EXIT_XSAVES:
2958 case VMX_EXIT_RDRAND:
2959 case VMX_EXIT_RDSEED:
2960 case VMX_EXIT_IO_INSTR:
2961 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2962 break;
2963 }
2964#endif
2965
2966 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2967}
2968
2969
2970/**
2971 * VMX VM-exit handler for VM-exits due to instruction execution.
2972 *
2973 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2974 * instruction information and Exit qualification fields.
2975 *
2976 * @param pVCpu The cross context virtual CPU structure.
2977 * @param uExitReason The VM-exit reason.
2978 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2979 * @param cbInstr The instruction length in bytes.
2980 *
2981 * @remarks Do not use this for INS/OUTS instruction.
2982 */
2983IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2984{
2985 VMXVEXITINFO ExitInfo;
2986 RT_ZERO(ExitInfo);
2987 ExitInfo.uReason = uExitReason;
2988 ExitInfo.cbInstr = cbInstr;
2989
2990 /*
2991 * Update the Exit qualification field with displacement bytes.
2992 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2993 */
2994 switch (uExitReason)
2995 {
2996 case VMX_EXIT_INVEPT:
2997 case VMX_EXIT_INVPCID:
2998 case VMX_EXIT_INVVPID:
2999 case VMX_EXIT_LDTR_TR_ACCESS:
3000 case VMX_EXIT_GDTR_IDTR_ACCESS:
3001 case VMX_EXIT_VMCLEAR:
3002 case VMX_EXIT_VMPTRLD:
3003 case VMX_EXIT_VMPTRST:
3004 case VMX_EXIT_VMREAD:
3005 case VMX_EXIT_VMWRITE:
3006 case VMX_EXIT_VMXON:
3007 case VMX_EXIT_XRSTORS:
3008 case VMX_EXIT_XSAVES:
3009 case VMX_EXIT_RDRAND:
3010 case VMX_EXIT_RDSEED:
3011 {
3012 /* Construct the VM-exit instruction information. */
3013 RTGCPTR GCPtrDisp;
3014 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3015
3016 /* Update the VM-exit instruction information. */
3017 ExitInfo.InstrInfo.u = uInstrInfo;
3018
3019 /* Update the Exit qualification. */
3020 ExitInfo.u64Qual = GCPtrDisp;
3021 break;
3022 }
3023
3024 default:
3025 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3026 break;
3027 }
3028
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030}
3031
3032
3033/**
3034 * VMX VM-exit handler for VM-exits due to INVLPG.
3035 *
3036 * @returns Strict VBox status code.
3037 * @param pVCpu The cross context virtual CPU structure.
3038 * @param GCPtrPage The guest-linear address of the page being invalidated.
3039 * @param cbInstr The instruction length in bytes.
3040 */
3041IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3042{
3043 VMXVEXITINFO ExitInfo;
3044 RT_ZERO(ExitInfo);
3045 ExitInfo.uReason = VMX_EXIT_INVLPG;
3046 ExitInfo.cbInstr = cbInstr;
3047 ExitInfo.u64Qual = GCPtrPage;
3048 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3049
3050 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3051}
3052
3053
3054/**
3055 * VMX VM-exit handler for VM-exits due to LMSW.
3056 *
3057 * @returns Strict VBox status code.
3058 * @param pVCpu The cross context virtual CPU structure.
3059 * @param uGuestCr0 The current guest CR0.
3060 * @param pu16NewMsw The machine-status word specified in LMSW's source
3061 * operand. This will be updated depending on the VMX
3062 * guest/host CR0 mask if LMSW is not intercepted.
3063 * @param GCPtrEffDst The guest-linear address of the source operand in case
3064 * of a memory operand. For register operand, pass
3065 * NIL_RTGCPTR.
3066 * @param cbInstr The instruction length in bytes.
3067 */
3068IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3069 uint8_t cbInstr)
3070{
3071 Assert(pu16NewMsw);
3072
3073 uint16_t const uNewMsw = *pu16NewMsw;
3074 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3075 {
3076 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3077
3078 VMXVEXITINFO ExitInfo;
3079 RT_ZERO(ExitInfo);
3080 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3081 ExitInfo.cbInstr = cbInstr;
3082
3083 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3084 if (fMemOperand)
3085 {
3086 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3087 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3088 }
3089
3090 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3094
3095 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3096 }
3097
3098 /*
3099 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3100 * CR0 guest/host mask must be left unmodified.
3101 *
3102 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3103 */
3104 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3105 Assert(pVmcs);
3106 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3107 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3108 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3109
3110 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3111}
3112
3113
3114/**
3115 * VMX VM-exit handler for VM-exits due to CLTS.
3116 *
3117 * @returns Strict VBox status code.
3118 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3119 * VM-exit but must not modify the guest CR0.TS bit.
3120 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3121 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3122 * CR0 fixed bits in VMX operation).
3123 * @param pVCpu The cross context virtual CPU structure.
3124 * @param cbInstr The instruction length in bytes.
3125 */
3126IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3127{
3128 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3129 Assert(pVmcs);
3130
3131 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3132 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3133
3134 /*
3135 * If CR0.TS is owned by the host:
3136 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3137 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3138 * CLTS instruction completes without clearing CR0.TS.
3139 *
3140 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3141 */
3142 if (fGstHostMask & X86_CR0_TS)
3143 {
3144 if (fReadShadow & X86_CR0_TS)
3145 {
3146 Log2(("clts: Guest intercept -> VM-exit\n"));
3147
3148 VMXVEXITINFO ExitInfo;
3149 RT_ZERO(ExitInfo);
3150 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3151 ExitInfo.cbInstr = cbInstr;
3152 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3153 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3154 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3155 }
3156
3157 return VINF_VMX_MODIFIES_BEHAVIOR;
3158 }
3159
3160 /*
3161 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3162 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3163 */
3164 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3165}
3166
3167
3168/**
3169 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3170 * (CR0/CR4 write).
3171 *
3172 * @returns Strict VBox status code.
3173 * @param pVCpu The cross context virtual CPU structure.
3174 * @param iCrReg The control register (either CR0 or CR4).
3175 * @param uGuestCrX The current guest CR0/CR4.
3176 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3177 * if no VM-exit is caused.
3178 * @param iGReg The general register from which the CR0/CR4 value is
3179 * being loaded.
3180 * @param cbInstr The instruction length in bytes.
3181 */
3182IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3183 uint8_t cbInstr)
3184{
3185 Assert(puNewCrX);
3186 Assert(iCrReg == 0 || iCrReg == 4);
3187 Assert(iGReg < X86_GREG_COUNT);
3188
3189 uint64_t const uNewCrX = *puNewCrX;
3190 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3191 {
3192 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3193
3194 VMXVEXITINFO ExitInfo;
3195 RT_ZERO(ExitInfo);
3196 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3197 ExitInfo.cbInstr = cbInstr;
3198 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3199 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3201 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3202 }
3203
3204 /*
3205 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3206 * must not be modified the instruction.
3207 *
3208 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3209 */
3210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3211 Assert(pVmcs);
3212 uint64_t uGuestCrX;
3213 uint64_t fGstHostMask;
3214 if (iCrReg == 0)
3215 {
3216 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3217 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3218 fGstHostMask = pVmcs->u64Cr0Mask.u;
3219 }
3220 else
3221 {
3222 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3223 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3224 fGstHostMask = pVmcs->u64Cr4Mask.u;
3225 }
3226
3227 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3228 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3229}
3230
3231
3232/**
3233 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3234 *
3235 * @returns VBox strict status code.
3236 * @param pVCpu The cross context virtual CPU structure.
3237 * @param iGReg The general register to which the CR3 value is being stored.
3238 * @param cbInstr The instruction length in bytes.
3239 */
3240IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3241{
3242 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3243 Assert(pVmcs);
3244 Assert(iGReg < X86_GREG_COUNT);
3245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3246
3247 /*
3248 * If the CR3-store exiting control is set, we must cause a VM-exit.
3249 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3250 */
3251 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3252 {
3253 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3254
3255 VMXVEXITINFO ExitInfo;
3256 RT_ZERO(ExitInfo);
3257 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3258 ExitInfo.cbInstr = cbInstr;
3259 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3260 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3261 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3262 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3263 }
3264
3265 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3266}
3267
3268
3269/**
3270 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3271 *
3272 * @returns VBox strict status code.
3273 * @param pVCpu The cross context virtual CPU structure.
3274 * @param uNewCr3 The new CR3 value.
3275 * @param iGReg The general register from which the CR3 value is being
3276 * loaded.
3277 * @param cbInstr The instruction length in bytes.
3278 */
3279IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3280{
3281 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3282 Assert(pVmcs);
3283 Assert(iGReg < X86_GREG_COUNT);
3284
3285 /*
3286 * If the CR3-load exiting control is set and the new CR3 value does not
3287 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3288 *
3289 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3290 */
3291 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3292 {
3293 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3294 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3295
3296 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3297 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3298 if (!fIntercept)
3299 {
3300 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3301 {
3302 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3303 if (uNewCr3 != uCr3TargetValue)
3304 {
3305 fIntercept = true;
3306 break;
3307 }
3308 }
3309 }
3310
3311 if (fIntercept)
3312 {
3313 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3314
3315 VMXVEXITINFO ExitInfo;
3316 RT_ZERO(ExitInfo);
3317 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3318 ExitInfo.cbInstr = cbInstr;
3319 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3320 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3321 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3322 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3323 }
3324 }
3325
3326 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3327}
3328
3329
3330/**
3331 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3332 *
3333 * @returns VBox strict status code.
3334 * @param pVCpu The cross context virtual CPU structure.
3335 * @param iGReg The general register to which the CR8 value is being stored.
3336 * @param cbInstr The instruction length in bytes.
3337 */
3338IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3339{
3340 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3341 Assert(pVmcs);
3342 Assert(iGReg < X86_GREG_COUNT);
3343
3344 /*
3345 * If the CR8-store exiting control is set, we must cause a VM-exit.
3346 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3347 */
3348 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3349 {
3350 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3351
3352 VMXVEXITINFO ExitInfo;
3353 RT_ZERO(ExitInfo);
3354 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3355 ExitInfo.cbInstr = cbInstr;
3356 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3357 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3358 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3359 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3360 }
3361
3362 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3363}
3364
3365
3366/**
3367 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3368 *
3369 * @returns VBox strict status code.
3370 * @param pVCpu The cross context virtual CPU structure.
3371 * @param iGReg The general register from which the CR8 value is being
3372 * loaded.
3373 * @param cbInstr The instruction length in bytes.
3374 */
3375IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3376{
3377 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3378 Assert(pVmcs);
3379 Assert(iGReg < X86_GREG_COUNT);
3380
3381 /*
3382 * If the CR8-load exiting control is set, we must cause a VM-exit.
3383 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3384 */
3385 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3386 {
3387 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3388
3389 VMXVEXITINFO ExitInfo;
3390 RT_ZERO(ExitInfo);
3391 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3392 ExitInfo.cbInstr = cbInstr;
3393 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3394 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3395 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3396 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3397 }
3398
3399 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3400}
3401
3402
3403/**
3404 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3405 * GReg,DRx' (DRx read).
3406 *
3407 * @returns VBox strict status code.
3408 * @param pVCpu The cross context virtual CPU structure.
3409 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3410 * VMXINSTRID_MOV_FROM_DRX).
3411 * @param iDrReg The debug register being accessed.
3412 * @param iGReg The general register to/from which the DRx value is being
3413 * store/loaded.
3414 * @param cbInstr The instruction length in bytes.
3415 */
3416IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3417 uint8_t cbInstr)
3418{
3419 Assert(iDrReg <= 7);
3420 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3421 Assert(iGReg < X86_GREG_COUNT);
3422
3423 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3424 Assert(pVmcs);
3425
3426 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3427 {
3428 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3429 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3430 VMXVEXITINFO ExitInfo;
3431 RT_ZERO(ExitInfo);
3432 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3433 ExitInfo.cbInstr = cbInstr;
3434 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3435 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3436 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3437 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3438 }
3439
3440 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3441}
3442
3443
3444/**
3445 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3446 *
3447 * @returns VBox strict status code.
3448 * @param pVCpu The cross context virtual CPU structure.
3449 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3450 * VMXINSTRID_IO_OUT).
3451 * @param u16Port The I/O port being accessed.
3452 * @param fImm Whether the I/O port was encoded using an immediate operand
3453 * or the implicit DX register.
3454 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3455 * @param cbInstr The instruction length in bytes.
3456 */
3457IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3458 uint8_t cbInstr)
3459{
3460 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3461 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3462
3463 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3464 if (fIntercept)
3465 {
3466 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3467 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3468 VMXVEXITINFO ExitInfo;
3469 RT_ZERO(ExitInfo);
3470 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3471 ExitInfo.cbInstr = cbInstr;
3472 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3473 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3474 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3476 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3477 }
3478
3479 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480}
3481
3482
3483/**
3484 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3485 *
3486 * @returns VBox strict status code.
3487 * @param pVCpu The cross context virtual CPU structure.
3488 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3489 * VMXINSTRID_IO_OUTS).
3490 * @param u16Port The I/O port being accessed.
3491 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3492 * @param fRep Whether the instruction has a REP prefix or not.
3493 * @param ExitInstrInfo The VM-exit instruction info. field.
3494 * @param cbInstr The instruction length in bytes.
3495 */
3496IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3497 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3498{
3499 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3500 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3501 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3502 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3503 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3504
3505 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3506 if (fIntercept)
3507 {
3508 /*
3509 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3510 */
3511 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3512 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3513 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3514 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3515 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3516
3517 uint32_t uDirection;
3518 uint64_t uGuestLinearAddr;
3519 if (uInstrId == VMXINSTRID_IO_INS)
3520 {
3521 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3522 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3523 }
3524 else
3525 {
3526 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3527 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3528 }
3529
3530 /*
3531 * If the segment is unusable, the guest-linear address in undefined.
3532 * We shall clear it for consistency.
3533 *
3534 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3535 */
3536 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3537 uGuestLinearAddr = 0;
3538
3539 VMXVEXITINFO ExitInfo;
3540 RT_ZERO(ExitInfo);
3541 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3542 ExitInfo.cbInstr = cbInstr;
3543 ExitInfo.InstrInfo = ExitInstrInfo;
3544 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3545 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3546 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3547 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3548 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3549 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3550 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3551 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3552 }
3553
3554 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3555}
3556
3557
3558/**
3559 * VMX VM-exit handler for VM-exits due to MWAIT.
3560 *
3561 * @returns VBox strict status code.
3562 * @param pVCpu The cross context virtual CPU structure.
3563 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3564 * @param cbInstr The instruction length in bytes.
3565 */
3566IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3567{
3568 VMXVEXITINFO ExitInfo;
3569 RT_ZERO(ExitInfo);
3570 ExitInfo.uReason = VMX_EXIT_MWAIT;
3571 ExitInfo.cbInstr = cbInstr;
3572 ExitInfo.u64Qual = fMonitorHwArmed;
3573 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3574}
3575
3576
3577/**
3578 * VMX VM-exit handler for VM-exits due to PAUSE.
3579 *
3580 * @returns VBox strict status code.
3581 * @param pVCpu The cross context virtual CPU structure.
3582 * @param cbInstr The instruction length in bytes.
3583 */
3584IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3585{
3586 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3587 Assert(pVmcs);
3588
3589 /*
3590 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3591 * "PAUSE-loop exiting" control.
3592 *
3593 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3594 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3595 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3596 * a VM-exit.
3597 *
3598 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3599 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3600 */
3601 bool fIntercept = false;
3602 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3603 fIntercept = true;
3604 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3605 && pVCpu->iem.s.uCpl == 0)
3606 {
3607 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3608
3609 /*
3610 * A previous-PAUSE-tick value of 0 is used to identify the first time
3611 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3612 * consider this to be the first execution of PAUSE in a loop according
3613 * to the Intel.
3614 *
3615 * All subsequent records for the previous-PAUSE-tick we ensure that it
3616 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3617 */
3618 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3619 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3620 uint64_t const uTick = TMCpuTickGet(pVCpu);
3621 uint32_t const uPleGap = pVmcs->u32PleGap;
3622 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3623 if ( *puPrevPauseTick == 0
3624 || uTick - *puPrevPauseTick > uPleGap)
3625 *puFirstPauseLoopTick = uTick;
3626 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3627 fIntercept = true;
3628
3629 *puPrevPauseTick = uTick | 1;
3630 }
3631
3632 if (fIntercept)
3633 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3634
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636}
3637
3638
3639/**
3640 * VMX VM-exit handler for VM-exits due to task switches.
3641 *
3642 * @returns VBox strict status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 * @param enmTaskSwitch The cause of the task switch.
3645 * @param SelNewTss The selector of the new TSS.
3646 * @param cbInstr The instruction length in bytes.
3647 */
3648IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3649{
3650 /*
3651 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3652 *
3653 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3654 * instruction or delivery of the exception generated by one of these instructions
3655 * lead to a task switch through a task gate in the IDT, we need to provide the
3656 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3657 * leaves the VM-exit instruction length field undefined.
3658 *
3659 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3660 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3661 */
3662 Assert(cbInstr <= 15);
3663
3664 uint8_t uType;
3665 switch (enmTaskSwitch)
3666 {
3667 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3668 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3669 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3670 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3671 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3672 }
3673
3674 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3675 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3676 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3677 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3678}
3679
3680
3681/**
3682 * VMX VM-exit handler for VM-exits due to task switches.
3683 *
3684 * This is intended for task switches where the caller provides all the relevant
3685 * VM-exit information.
3686 *
3687 * @returns VBox strict status code.
3688 * @param pVCpu The cross context virtual CPU structure.
3689 * @param pExitInfo Pointer to the VM-exit information.
3690 * @param pExitEventInfo Pointer to the VM-exit event information.
3691 */
3692IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3693 PCVMXVEXITEVENTINFO pExitEventInfo)
3694{
3695 Assert(pExitInfo);
3696 Assert(pExitEventInfo);
3697
3698 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3699 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3700 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3701
3702 /*
3703 * Figure out if an instruction was the source of the task switch.
3704 *
3705 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3706 * of an event generated by a software interrupt (INT-N), privileged software
3707 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3708 * the instruction length.
3709 */
3710 bool fHasInstrLen;
3711 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3712 {
3713 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3714 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3715 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3716 if (fIdtVectInfoValid)
3717 {
3718 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3719 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3720 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3721
3722 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3723 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3724 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3725 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3726 fHasInstrLen = true;
3727 else
3728 fHasInstrLen = false;
3729 }
3730 else
3731 fHasInstrLen = false;
3732 }
3733 else
3734 {
3735 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3736 fHasInstrLen = true;
3737 }
3738
3739 if (fHasInstrLen)
3740 {
3741 Assert(pExitInfo->cbInstr > 0);
3742 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3743 }
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3745}
3746
3747
3748/**
3749 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3750 *
3751 * @returns VBox strict status code.
3752 * @param pVCpu The cross context virtual CPU structure.
3753 */
3754IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3755{
3756 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3757 Assert(pVmcs);
3758
3759 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3760 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3761 {
3762 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3763 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3764
3765 /*
3766 * Calculate the current VMX-preemption timer value.
3767 * Only if the value has reached zero, we cause the VM-exit.
3768 */
3769 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3770 if (!uPreemptTimer)
3771 {
3772 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3773 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3774 pVmcs->u32PreemptTimer = 0;
3775
3776 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3777 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3778 }
3779 }
3780
3781 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3782}
3783
3784
3785/**
3786 * VMX VM-exit handler for VM-exits due to external interrupts.
3787 *
3788 * @returns VBox strict status code.
3789 * @param pVCpu The cross context virtual CPU structure.
3790 * @param uVector The external interrupt vector (pass 0 if the interrupt
3791 * is still pending since we typically won't know the
3792 * vector).
3793 * @param fIntPending Whether the external interrupt is pending or
3794 * acknowledged in the interrupt controller.
3795 */
3796IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3797{
3798 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3799 Assert(pVmcs);
3800 Assert(fIntPending || uVector == 0);
3801
3802 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3803 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3804 * functions require prior checking of a blanket intercept and which don't.
3805 * It is better for the caller to check a blanket intercept performance wise
3806 * than making a function call. Leaving this as a todo because it is more
3807 * a performance issue. */
3808
3809 /* The VM-exit is subject to "External interrupt exiting" being set. */
3810 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3811 {
3812 if (fIntPending)
3813 {
3814 /*
3815 * If the interrupt is pending and we don't need to acknowledge the
3816 * interrupt on VM-exit, cause the VM-exit immediately.
3817 *
3818 * See Intel spec 25.2 "Other Causes Of VM Exits".
3819 */
3820 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3821 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3822
3823 /*
3824 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3825 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3826 * acknowledged that the interrupt has been consumed.
3827 */
3828 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3829 }
3830
3831 /*
3832 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3833 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3834 * all set, we cause the VM-exit now. We need to record the external interrupt that
3835 * just occurred in the VM-exit interruption information field.
3836 *
3837 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3838 */
3839 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3840 {
3841 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3842 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3843 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3844 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3845 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3846 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3847 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3848 }
3849 }
3850
3851 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3852}
3853
3854
3855/**
3856 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3857 * an event.
3858 *
3859 * @returns VBox strict status code.
3860 * @param pVCpu The cross context virtual CPU structure.
3861 */
3862IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3863{
3864 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3865 Assert(pVmcs);
3866
3867 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3868 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3869 {
3870 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3871 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3872 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3873 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3874 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3875 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3876 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3877 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3878 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3879
3880 /*
3881 * A VM-exit is not considered to occur during event delivery when the original
3882 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3883 * using the exception bitmap).
3884 *
3885 * Therefore, we must clear the original event from the IDT-vectoring fields which
3886 * would've been recorded before causing the VM-exit.
3887 *
3888 * 27.2.3 "Information for VM Exits During Event Delivery"
3889 */
3890 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3891 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3892 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3893 }
3894
3895 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3896}
3897
3898
3899/**
3900 * VMX VM-exit handler for VM-exit due to delivery of an events.
3901 *
3902 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3903 * all the relevant VM-exit information.
3904 *
3905 * @returns VBox strict status code.
3906 * @param pVCpu The cross context virtual CPU structure.
3907 * @param pExitInfo Pointer to the VM-exit information.
3908 * @param pExitEventInfo Pointer to the VM-exit event information.
3909 */
3910IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3911{
3912 Assert(pExitInfo);
3913 Assert(pExitEventInfo);
3914 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3915
3916 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3917 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3918 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3919 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3920 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3921 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3922}
3923
3924
3925/**
3926 * VMX VM-exit handler for VM-exits due to delivery of an event.
3927 *
3928 * @returns VBox strict status code.
3929 * @param pVCpu The cross context virtual CPU structure.
3930 * @param uVector The interrupt / exception vector.
3931 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3932 * @param uErrCode The error code associated with the event.
3933 * @param uCr2 The CR2 value in case of a \#PF exception.
3934 * @param cbInstr The instruction length in bytes.
3935 */
3936IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3937 uint8_t cbInstr)
3938{
3939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3940 Assert(pVmcs);
3941
3942 /*
3943 * If the event is being injected as part of VM-entry, it is -not- subject to event
3944 * intercepts in the nested-guest. However, secondary exceptions that occur during
3945 * injection of any event -are- subject to event interception.
3946 *
3947 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3948 */
3949 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3950 {
3951 /*
3952 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3953 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3954 *
3955 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3956 */
3957 if ( uVector == X86_XCPT_NMI
3958 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3959 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3960 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3961 else
3962 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3963
3964 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3965 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3966 }
3967
3968 /*
3969 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3970 * If not, the caller will continue delivery of the external interrupt as it would
3971 * normally. The interrupt is no longer pending in the interrupt controller at this
3972 * point.
3973 */
3974 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3975 {
3976 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3977 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3978 }
3979
3980 /*
3981 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3982 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3983 * interrupts.
3984 */
3985 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3986 bool fIntercept;
3987 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3988 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3989 {
3990 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3991 }
3992 else
3993 {
3994 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3995 fIntercept = false;
3996 }
3997
3998 /*
3999 * Now that we've determined whether the event causes a VM-exit, we need to construct the
4000 * relevant VM-exit information and cause the VM-exit.
4001 */
4002 if (fIntercept)
4003 {
4004 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4005
4006 /* Construct the rest of the event related information fields and cause the VM-exit. */
4007 uint64_t u64ExitQual;
4008 if (uVector == X86_XCPT_PF)
4009 {
4010 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4011 u64ExitQual = uCr2;
4012 }
4013 else if (uVector == X86_XCPT_DB)
4014 {
4015 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4016 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4017 }
4018 else
4019 u64ExitQual = 0;
4020
4021 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4022 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4023 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4024 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4025 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4026 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4027 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4028 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4029 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4030 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4031
4032 /*
4033 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
4034 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4035 * length.
4036 */
4037 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4038 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4039 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4040 else
4041 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4042
4043 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
4044 }
4045
4046 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4047}
4048
4049
4050/**
4051 * VMX VM-exit handler for VM-exits due to a triple fault.
4052 *
4053 * @returns VBox strict status code.
4054 * @param pVCpu The cross context virtual CPU structure.
4055 */
4056IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4057{
4058 /*
4059 * A VM-exit is not considered to occur during event delivery when the original
4060 * event results in a triple-fault.
4061 *
4062 * Therefore, we must clear the original event from the IDT-vectoring fields which
4063 * would've been recorded before causing the VM-exit.
4064 *
4065 * 27.2.3 "Information for VM Exits During Event Delivery"
4066 */
4067 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4068 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4069
4070 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
4071}
4072
4073
4074/**
4075 * VMX VM-exit handler for APIC accesses.
4076 *
4077 * @param pVCpu The cross context virtual CPU structure.
4078 * @param offAccess The offset of the register being accessed.
4079 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4080 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4081 */
4082IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4083{
4084 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4085
4086 VMXAPICACCESS enmAccess;
4087 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4088 if (fInEventDelivery)
4089 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4090 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4091 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4092 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4093 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4094 else
4095 enmAccess = VMXAPICACCESS_LINEAR_READ;
4096
4097 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4098 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4099 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4100}
4101
4102
4103/**
4104 * VMX VM-exit handler for APIC accesses.
4105 *
4106 * This is intended for APIC accesses where the caller provides all the
4107 * relevant VM-exit information.
4108 *
4109 * @returns VBox strict status code.
4110 * @param pVCpu The cross context virtual CPU structure.
4111 * @param pExitInfo Pointer to the VM-exit information.
4112 * @param pExitEventInfo Pointer to the VM-exit event information.
4113 */
4114IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
4115 PCVMXVEXITEVENTINFO pExitEventInfo)
4116{
4117 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4118 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4119 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4120 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4121 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4122 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4123 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4124}
4125
4126
4127/**
4128 * VMX VM-exit handler for APIC-write VM-exits.
4129 *
4130 * @param pVCpu The cross context virtual CPU structure.
4131 * @param offApic The write to the virtual-APIC page offset that caused this
4132 * VM-exit.
4133 */
4134IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4135{
4136 Assert(offApic < XAPIC_OFF_END + 4);
4137 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4138 offApic &= UINT16_C(0xfff);
4139 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4140}
4141
4142
4143/**
4144 * Sets virtual-APIC write emulation as pending.
4145 *
4146 * @param pVCpu The cross context virtual CPU structure.
4147 * @param offApic The offset in the virtual-APIC page that was written.
4148 */
4149DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4150{
4151 Assert(offApic < XAPIC_OFF_END + 4);
4152
4153 /*
4154 * Record the currently updated APIC offset, as we need this later for figuring
4155 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4156 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4157 */
4158 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4159
4160 /*
4161 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4162 * virtualization or APIC-write emulation).
4163 */
4164 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4165 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4166}
4167
4168
4169/**
4170 * Clears any pending virtual-APIC write emulation.
4171 *
4172 * @returns The virtual-APIC offset that was written before clearing it.
4173 * @param pVCpu The cross context virtual CPU structure.
4174 */
4175DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4176{
4177 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4178 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4179 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4180 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4181 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4182 return offVirtApicWrite;
4183}
4184
4185
4186/**
4187 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4188 *
4189 * @returns The register from the virtual-APIC page.
4190 * @param pVCpu The cross context virtual CPU structure.
4191 * @param offReg The offset of the register being read.
4192 */
4193IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4194{
4195 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4196 Assert(pVmcs);
4197
4198 uint32_t uReg;
4199 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4200 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4201 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4202 if (RT_FAILURE(rc))
4203 {
4204 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4205 GCPhysVirtApic));
4206 uReg = 0;
4207 }
4208 return uReg;
4209}
4210
4211
4212/**
4213 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4214 *
4215 * @returns The register from the virtual-APIC page.
4216 * @param pVCpu The cross context virtual CPU structure.
4217 * @param offReg The offset of the register being read.
4218 */
4219IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4220{
4221 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4222 Assert(pVmcs);
4223
4224 uint64_t uReg;
4225 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4226 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4227 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4228 if (RT_FAILURE(rc))
4229 {
4230 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4231 GCPhysVirtApic));
4232 uReg = 0;
4233 }
4234 return uReg;
4235}
4236
4237
4238/**
4239 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4240 *
4241 * @param pVCpu The cross context virtual CPU structure.
4242 * @param offReg The offset of the register being written.
4243 * @param uReg The register value to write.
4244 */
4245IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4246{
4247 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4248 Assert(pVmcs);
4249 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4250 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4251 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4252 if (RT_FAILURE(rc))
4253 {
4254 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4255 GCPhysVirtApic));
4256 }
4257}
4258
4259
4260/**
4261 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4262 *
4263 * @param pVCpu The cross context virtual CPU structure.
4264 * @param offReg The offset of the register being written.
4265 * @param uReg The register value to write.
4266 */
4267IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4268{
4269 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4270 Assert(pVmcs);
4271 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4272 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4273 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4274 if (RT_FAILURE(rc))
4275 {
4276 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4277 GCPhysVirtApic));
4278 }
4279}
4280
4281
4282/**
4283 * Sets the vector in a virtual-APIC 256-bit sparse register.
4284 *
4285 * @param pVCpu The cross context virtual CPU structure.
4286 * @param offReg The offset of the 256-bit spare register.
4287 * @param uVector The vector to set.
4288 *
4289 * @remarks This is based on our APIC device code.
4290 */
4291IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4292{
4293 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4294 Assert(pVmcs);
4295 uint32_t uReg;
4296 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4297 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4298 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4299 if (RT_SUCCESS(rc))
4300 {
4301 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4302 uReg |= RT_BIT(idxVectorBit);
4303 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4304 if (RT_FAILURE(rc))
4305 {
4306 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4307 uVector, offReg, GCPhysVirtApic));
4308 }
4309 }
4310 else
4311 {
4312 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4313 uVector, offReg, GCPhysVirtApic));
4314 }
4315}
4316
4317
4318/**
4319 * Clears the vector in a virtual-APIC 256-bit sparse register.
4320 *
4321 * @param pVCpu The cross context virtual CPU structure.
4322 * @param offReg The offset of the 256-bit spare register.
4323 * @param uVector The vector to clear.
4324 *
4325 * @remarks This is based on our APIC device code.
4326 */
4327IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4328{
4329 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4330 Assert(pVmcs);
4331 uint32_t uReg;
4332 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4333 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4334 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4335 if (RT_SUCCESS(rc))
4336 {
4337 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4338 uReg &= ~RT_BIT(idxVectorBit);
4339 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4340 if (RT_FAILURE(rc))
4341 {
4342 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4343 uVector, offReg, GCPhysVirtApic));
4344 }
4345 }
4346 else
4347 {
4348 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4349 uVector, offReg, GCPhysVirtApic));
4350 }
4351}
4352
4353
4354/**
4355 * Checks if a memory access to the APIC-access page must causes an APIC-access
4356 * VM-exit.
4357 *
4358 * @param pVCpu The cross context virtual CPU structure.
4359 * @param offAccess The offset of the register being accessed.
4360 * @param cbAccess The size of the access in bytes.
4361 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4362 * IEM_ACCESS_TYPE_WRITE).
4363 *
4364 * @remarks This must not be used for MSR-based APIC-access page accesses!
4365 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4366 */
4367IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4368{
4369 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4370 Assert(pVmcs);
4371 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4372
4373 /*
4374 * We must cause a VM-exit if any of the following are true:
4375 * - TPR shadowing isn't active.
4376 * - The access size exceeds 32-bits.
4377 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4378 *
4379 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4380 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4381 */
4382 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4383 || cbAccess > sizeof(uint32_t)
4384 || ((offAccess + cbAccess - 1) & 0xc)
4385 || offAccess >= XAPIC_OFF_END + 4)
4386 return true;
4387
4388 /*
4389 * If the access is part of an operation where we have already
4390 * virtualized a virtual-APIC write, we must cause a VM-exit.
4391 */
4392 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4393 return true;
4394
4395 /*
4396 * Check write accesses to the APIC-access page that cause VM-exits.
4397 */
4398 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4399 {
4400 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4401 {
4402 /*
4403 * With APIC-register virtualization, a write access to any of the
4404 * following registers are virtualized. Accessing any other register
4405 * causes a VM-exit.
4406 */
4407 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4408 switch (offAlignedAccess)
4409 {
4410 case XAPIC_OFF_ID:
4411 case XAPIC_OFF_TPR:
4412 case XAPIC_OFF_EOI:
4413 case XAPIC_OFF_LDR:
4414 case XAPIC_OFF_DFR:
4415 case XAPIC_OFF_SVR:
4416 case XAPIC_OFF_ESR:
4417 case XAPIC_OFF_ICR_LO:
4418 case XAPIC_OFF_ICR_HI:
4419 case XAPIC_OFF_LVT_TIMER:
4420 case XAPIC_OFF_LVT_THERMAL:
4421 case XAPIC_OFF_LVT_PERF:
4422 case XAPIC_OFF_LVT_LINT0:
4423 case XAPIC_OFF_LVT_LINT1:
4424 case XAPIC_OFF_LVT_ERROR:
4425 case XAPIC_OFF_TIMER_ICR:
4426 case XAPIC_OFF_TIMER_DCR:
4427 break;
4428 default:
4429 return true;
4430 }
4431 }
4432 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4433 {
4434 /*
4435 * With virtual-interrupt delivery, a write access to any of the
4436 * following registers are virtualized. Accessing any other register
4437 * causes a VM-exit.
4438 *
4439 * Note! The specification does not allow writing to offsets in-between
4440 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4441 */
4442 switch (offAccess)
4443 {
4444 case XAPIC_OFF_TPR:
4445 case XAPIC_OFF_EOI:
4446 case XAPIC_OFF_ICR_LO:
4447 break;
4448 default:
4449 return true;
4450 }
4451 }
4452 else
4453 {
4454 /*
4455 * Without APIC-register virtualization or virtual-interrupt delivery,
4456 * only TPR accesses are virtualized.
4457 */
4458 if (offAccess == XAPIC_OFF_TPR)
4459 { /* likely */ }
4460 else
4461 return true;
4462 }
4463 }
4464 else
4465 {
4466 /*
4467 * Check read accesses to the APIC-access page that cause VM-exits.
4468 */
4469 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4470 {
4471 /*
4472 * With APIC-register virtualization, a read access to any of the
4473 * following registers are virtualized. Accessing any other register
4474 * causes a VM-exit.
4475 */
4476 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4477 switch (offAlignedAccess)
4478 {
4479 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4480 case XAPIC_OFF_ID:
4481 case XAPIC_OFF_VERSION:
4482 case XAPIC_OFF_TPR:
4483 case XAPIC_OFF_EOI:
4484 case XAPIC_OFF_LDR:
4485 case XAPIC_OFF_DFR:
4486 case XAPIC_OFF_SVR:
4487 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4488 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4489 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4490 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4491 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4492 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4493 case XAPIC_OFF_ESR:
4494 case XAPIC_OFF_ICR_LO:
4495 case XAPIC_OFF_ICR_HI:
4496 case XAPIC_OFF_LVT_TIMER:
4497 case XAPIC_OFF_LVT_THERMAL:
4498 case XAPIC_OFF_LVT_PERF:
4499 case XAPIC_OFF_LVT_LINT0:
4500 case XAPIC_OFF_LVT_LINT1:
4501 case XAPIC_OFF_LVT_ERROR:
4502 case XAPIC_OFF_TIMER_ICR:
4503 case XAPIC_OFF_TIMER_DCR:
4504 break;
4505 default:
4506 return true;
4507 }
4508 }
4509 else
4510 {
4511 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4512 if (offAccess == XAPIC_OFF_TPR)
4513 { /* likely */ }
4514 else
4515 return true;
4516 }
4517 }
4518
4519 /* The APIC access is virtualized, does not cause a VM-exit. */
4520 return false;
4521}
4522
4523
4524/**
4525 * Virtualizes a memory-based APIC access where the address is not used to access
4526 * memory.
4527 *
4528 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4529 * page-faults but do not use the address to access memory.
4530 *
4531 * @param pVCpu The cross context virtual CPU structure.
4532 * @param pGCPhysAccess Pointer to the guest-physical address used.
4533 */
4534IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4535{
4536 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4537 Assert(pVmcs);
4538 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4539 Assert(pGCPhysAccess);
4540
4541 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4542 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4543 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4544
4545 if (GCPhysAccess == GCPhysApic)
4546 {
4547 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4548 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4549 uint16_t const cbAccess = 1;
4550 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4551 if (fIntercept)
4552 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4553
4554 *pGCPhysAccess = GCPhysApic | offAccess;
4555 return VINF_VMX_MODIFIES_BEHAVIOR;
4556 }
4557
4558 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4559}
4560
4561
4562/**
4563 * Virtualizes a memory-based APIC access.
4564 *
4565 * @returns VBox strict status code.
4566 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4567 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4568 *
4569 * @param pVCpu The cross context virtual CPU structure.
4570 * @param offAccess The offset of the register being accessed (within the
4571 * APIC-access page).
4572 * @param cbAccess The size of the access in bytes.
4573 * @param pvData Pointer to the data being written or where to store the data
4574 * being read.
4575 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4576 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4577 */
4578IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4579 uint32_t fAccess)
4580{
4581 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4582 Assert(pVmcs);
4583 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4584 Assert(pvData);
4585 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4586 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4587 || (fAccess & IEM_ACCESS_INSTRUCTION));
4588
4589 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4590 if (fIntercept)
4591 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4592
4593 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4594 {
4595 /*
4596 * A write access to the APIC-access page that is virtualized (rather than
4597 * causing a VM-exit) writes data to the virtual-APIC page.
4598 */
4599 uint32_t const u32Data = *(uint32_t *)pvData;
4600 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4601
4602 /*
4603 * Record the currently updated APIC offset, as we need this later for figuring
4604 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4605 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4606 *
4607 * After completion of the current operation, we need to perform TPR virtualization,
4608 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4609 *
4610 * The current operation may be a REP-prefixed string instruction, execution of any
4611 * other instruction, or delivery of an event through the IDT.
4612 *
4613 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4614 * performed now but later after completion of the current operation.
4615 *
4616 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4617 */
4618 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4619 }
4620 else
4621 {
4622 /*
4623 * A read access from the APIC-access page that is virtualized (rather than
4624 * causing a VM-exit) returns data from the virtual-APIC page.
4625 *
4626 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4627 */
4628 Assert(cbAccess <= 4);
4629 Assert(offAccess < XAPIC_OFF_END + 4);
4630 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4631
4632 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4633 u32Data &= s_auAccessSizeMasks[cbAccess];
4634 *(uint32_t *)pvData = u32Data;
4635 }
4636
4637 return VINF_VMX_MODIFIES_BEHAVIOR;
4638}
4639
4640
4641/**
4642 * Virtualizes an MSR-based APIC read access.
4643 *
4644 * @returns VBox strict status code.
4645 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4646 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4647 * handled by the x2APIC device.
4648 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4649 * not within the range of valid MSRs, caller must raise \#GP(0).
4650 * @param pVCpu The cross context virtual CPU structure.
4651 * @param idMsr The x2APIC MSR being read.
4652 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4653 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4654 */
4655IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4656{
4657 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4658 Assert(pVmcs);
4659 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4660 Assert(pu64Value);
4661
4662 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4663 {
4664 /*
4665 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4666 * what the end of the valid x2APIC MSR range is. Hence the use of different
4667 * macros here.
4668 *
4669 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4670 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4671 */
4672 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4673 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4674 {
4675 uint16_t const offReg = (idMsr & 0xff) << 4;
4676 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4677 *pu64Value = u64Value;
4678 return VINF_VMX_MODIFIES_BEHAVIOR;
4679 }
4680 return VERR_OUT_OF_RANGE;
4681 }
4682
4683 if (idMsr == MSR_IA32_X2APIC_TPR)
4684 {
4685 uint16_t const offReg = (idMsr & 0xff) << 4;
4686 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4687 *pu64Value = u64Value;
4688 return VINF_VMX_MODIFIES_BEHAVIOR;
4689 }
4690
4691 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4692}
4693
4694
4695/**
4696 * Virtualizes an MSR-based APIC write access.
4697 *
4698 * @returns VBox strict status code.
4699 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4700 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4701 * not within the range of valid MSRs, caller must raise \#GP(0).
4702 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4703 *
4704 * @param pVCpu The cross context virtual CPU structure.
4705 * @param idMsr The x2APIC MSR being written.
4706 * @param u64Value The value of the x2APIC MSR being written.
4707 */
4708IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4709{
4710 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4711 Assert(pVmcs);
4712
4713 /*
4714 * Check if the access is to be virtualized.
4715 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4716 */
4717 if ( idMsr == MSR_IA32_X2APIC_TPR
4718 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4719 && ( idMsr == MSR_IA32_X2APIC_EOI
4720 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4721 {
4722 /* Validate the MSR write depending on the register. */
4723 switch (idMsr)
4724 {
4725 case MSR_IA32_X2APIC_TPR:
4726 case MSR_IA32_X2APIC_SELF_IPI:
4727 {
4728 if (u64Value & UINT64_C(0xffffffffffffff00))
4729 return VERR_OUT_OF_RANGE;
4730 break;
4731 }
4732 case MSR_IA32_X2APIC_EOI:
4733 {
4734 if (u64Value != 0)
4735 return VERR_OUT_OF_RANGE;
4736 break;
4737 }
4738 }
4739
4740 /* Write the MSR to the virtual-APIC page. */
4741 uint16_t const offReg = (idMsr & 0xff) << 4;
4742 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4743
4744 /*
4745 * Record the currently updated APIC offset, as we need this later for figuring
4746 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4747 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4748 */
4749 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4750
4751 return VINF_VMX_MODIFIES_BEHAVIOR;
4752 }
4753
4754 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4755}
4756
4757
4758/**
4759 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4760 *
4761 * @returns VBox status code.
4762 * @retval VINF_SUCCESS when the highest set bit is found.
4763 * @retval VERR_NOT_FOUND when no bit is set.
4764 *
4765 * @param pVCpu The cross context virtual CPU structure.
4766 * @param offReg The offset of the APIC 256-bit sparse register.
4767 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4768 * set in the register. Only valid when VINF_SUCCESS is
4769 * returned.
4770 *
4771 * @remarks The format of the 256-bit sparse register here mirrors that found in
4772 * real APIC hardware.
4773 */
4774static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4775{
4776 Assert(offReg < XAPIC_OFF_END + 4);
4777 Assert(pidxHighestBit);
4778 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4779
4780 /*
4781 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4782 * However, in each fragment only the first 4 bytes are used.
4783 */
4784 uint8_t const cFrags = 8;
4785 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4786 {
4787 uint16_t const offFrag = iFrag * 16;
4788 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4789 if (!u32Frag)
4790 continue;
4791
4792 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4793 Assert(idxHighestBit > 0);
4794 --idxHighestBit;
4795 Assert(idxHighestBit <= UINT8_MAX);
4796 *pidxHighestBit = idxHighestBit;
4797 return VINF_SUCCESS;
4798 }
4799 return VERR_NOT_FOUND;
4800}
4801
4802
4803/**
4804 * Evaluates pending virtual interrupts.
4805 *
4806 * @param pVCpu The cross context virtual CPU structure.
4807 */
4808IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4809{
4810 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4811 Assert(pVmcs);
4812 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4813
4814 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4815 {
4816 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4817 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4818
4819 if ((uRvi >> 4) > (uPpr >> 4))
4820 {
4821 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4822 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4823 }
4824 else
4825 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4826 }
4827}
4828
4829
4830/**
4831 * Performs PPR virtualization.
4832 *
4833 * @returns VBox strict status code.
4834 * @param pVCpu The cross context virtual CPU structure.
4835 */
4836IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4837{
4838 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4839 Assert(pVmcs);
4840 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4841 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4842
4843 /*
4844 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4845 * or EOI-virtualization.
4846 *
4847 * See Intel spec. 29.1.3 "PPR Virtualization".
4848 */
4849 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4850 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4851
4852 uint32_t uPpr;
4853 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4854 uPpr = uTpr & 0xff;
4855 else
4856 uPpr = uSvi & 0xf0;
4857
4858 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4859 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4860}
4861
4862
4863/**
4864 * Performs VMX TPR virtualization.
4865 *
4866 * @returns VBox strict status code.
4867 * @param pVCpu The cross context virtual CPU structure.
4868 */
4869IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4870{
4871 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4872 Assert(pVmcs);
4873 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4874
4875 /*
4876 * We should have already performed the virtual-APIC write to the TPR offset
4877 * in the virtual-APIC page. We now perform TPR virtualization.
4878 *
4879 * See Intel spec. 29.1.2 "TPR Virtualization".
4880 */
4881 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4882 {
4883 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4884 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4885
4886 /*
4887 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4888 * See Intel spec. 29.1.2 "TPR Virtualization".
4889 */
4890 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4891 {
4892 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4893 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4894 }
4895 }
4896 else
4897 {
4898 iemVmxPprVirtualization(pVCpu);
4899 iemVmxEvalPendingVirtIntrs(pVCpu);
4900 }
4901
4902 return VINF_SUCCESS;
4903}
4904
4905
4906/**
4907 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4908 * not.
4909 *
4910 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4911 * @param pVCpu The cross context virtual CPU structure.
4912 * @param uVector The interrupt that was acknowledged using an EOI.
4913 */
4914IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4915{
4916 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4917 Assert(pVmcs);
4918 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4919
4920 if (uVector < 64)
4921 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4922 if (uVector < 128)
4923 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4924 if (uVector < 192)
4925 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4926 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4927}
4928
4929
4930/**
4931 * Performs EOI virtualization.
4932 *
4933 * @returns VBox strict status code.
4934 * @param pVCpu The cross context virtual CPU structure.
4935 */
4936IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4937{
4938 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4939 Assert(pVmcs);
4940 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4941
4942 /*
4943 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4944 * and get the next guest-interrupt that's in-service (if any).
4945 *
4946 * See Intel spec. 29.1.4 "EOI Virtualization".
4947 */
4948 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4949 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4950 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4951
4952 uint8_t uVector = uSvi;
4953 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4954
4955 uVector = 0;
4956 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4957
4958 if (uVector)
4959 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4960 else
4961 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4962
4963 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4964 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4965
4966 iemVmxPprVirtualization(pVCpu);
4967 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4968 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4969 iemVmxEvalPendingVirtIntrs(pVCpu);
4970 return VINF_SUCCESS;
4971}
4972
4973
4974/**
4975 * Performs self-IPI virtualization.
4976 *
4977 * @returns VBox strict status code.
4978 * @param pVCpu The cross context virtual CPU structure.
4979 */
4980IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4981{
4982 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4983 Assert(pVmcs);
4984 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4985
4986 /*
4987 * We should have already performed the virtual-APIC write to the self-IPI offset
4988 * in the virtual-APIC page. We now perform self-IPI virtualization.
4989 *
4990 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4991 */
4992 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4993 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4994 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4995 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4996 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4997 if (uVector > uRvi)
4998 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4999 iemVmxEvalPendingVirtIntrs(pVCpu);
5000 return VINF_SUCCESS;
5001}
5002
5003
5004/**
5005 * Performs VMX APIC-write emulation.
5006 *
5007 * @returns VBox strict status code.
5008 * @param pVCpu The cross context virtual CPU structure.
5009 */
5010IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5011{
5012 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5013 Assert(pVmcs);
5014
5015 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5016 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5017
5018 /*
5019 * Perform APIC-write emulation based on the virtual-APIC register written.
5020 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5021 */
5022 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5023 VBOXSTRICTRC rcStrict;
5024 switch (offApicWrite)
5025 {
5026 case XAPIC_OFF_TPR:
5027 {
5028 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5029 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5030 uTpr &= UINT32_C(0x000000ff);
5031 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5032 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5033 rcStrict = iemVmxTprVirtualization(pVCpu);
5034 break;
5035 }
5036
5037 case XAPIC_OFF_EOI:
5038 {
5039 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5040 {
5041 /* Clear VEOI and perform EOI virtualization. */
5042 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5043 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5044 rcStrict = iemVmxEoiVirtualization(pVCpu);
5045 }
5046 else
5047 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5048 break;
5049 }
5050
5051 case XAPIC_OFF_ICR_LO:
5052 {
5053 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5054 {
5055 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5056 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5057 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5058 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5059 if ( !(uIcrLo & fIcrLoMb0)
5060 && (uIcrLo & fIcrLoMb1))
5061 {
5062 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5063 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5064 }
5065 else
5066 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5067 }
5068 else
5069 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5070 break;
5071 }
5072
5073 case XAPIC_OFF_ICR_HI:
5074 {
5075 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5076 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5077 uIcrHi &= UINT32_C(0xff000000);
5078 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5079 rcStrict = VINF_SUCCESS;
5080 break;
5081 }
5082
5083 default:
5084 {
5085 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5086 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5087 break;
5088 }
5089 }
5090
5091 return rcStrict;
5092}
5093
5094
5095/**
5096 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5097 *
5098 * @param pVCpu The cross context virtual CPU structure.
5099 * @param pszInstr The VMX instruction name (for logging purposes).
5100 */
5101IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5102{
5103 /*
5104 * Guest Control Registers, Debug Registers, and MSRs.
5105 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5106 */
5107 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5108 const char *const pszFailure = "VM-exit";
5109 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5110
5111 /* CR0 reserved bits. */
5112 {
5113 /* CR0 MB1 bits. */
5114 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5115 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5116 if (fUnrestrictedGuest)
5117 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5118 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5122
5123 /* CR0 MBZ bits. */
5124 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5125 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5126 { /* likely */ }
5127 else
5128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5129
5130 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5131 if ( !fUnrestrictedGuest
5132 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5133 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5134 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5135 }
5136
5137 /* CR4 reserved bits. */
5138 {
5139 /* CR4 MB1 bits. */
5140 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5141 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5142 { /* likely */ }
5143 else
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5145
5146 /* CR4 MBZ bits. */
5147 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5148 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5152 }
5153
5154 /* DEBUGCTL MSR. */
5155 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5156 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5157 { /* likely */ }
5158 else
5159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5160
5161 /* 64-bit CPU checks. */
5162 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5163 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5164 {
5165 if (fGstInLongMode)
5166 {
5167 /* PAE must be set. */
5168 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5169 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5173 }
5174 else
5175 {
5176 /* PCIDE should not be set. */
5177 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5178 { /* likely */ }
5179 else
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5181 }
5182
5183 /* CR3. */
5184 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5185 { /* likely */ }
5186 else
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5188
5189 /* DR7. */
5190 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5191 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5192 { /* likely */ }
5193 else
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5195
5196 /* SYSENTER ESP and SYSENTER EIP. */
5197 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5198 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5199 { /* likely */ }
5200 else
5201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5202 }
5203
5204 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5205 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5206
5207 /* PAT MSR. */
5208 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5209 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5210 { /* likely */ }
5211 else
5212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5213
5214 /* EFER MSR. */
5215 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5216 {
5217 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5218 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5222
5223 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5224 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5225 if ( fGstLma == fGstInLongMode
5226 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5227 || fGstLma == fGstLme))
5228 { /* likely */ }
5229 else
5230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5231 }
5232
5233 /* We don't support IA32_BNDCFGS MSR yet. */
5234 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5235
5236 NOREF(pszInstr);
5237 NOREF(pszFailure);
5238 return VINF_SUCCESS;
5239}
5240
5241
5242/**
5243 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5244 *
5245 * @param pVCpu The cross context virtual CPU structure.
5246 * @param pszInstr The VMX instruction name (for logging purposes).
5247 */
5248IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5249{
5250 /*
5251 * Segment registers.
5252 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5253 */
5254 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5255 const char *const pszFailure = "VM-exit";
5256 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5257 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5258 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5259
5260 /* Selectors. */
5261 if ( !fGstInV86Mode
5262 && !fUnrestrictedGuest
5263 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5265
5266 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5267 {
5268 CPUMSELREG SelReg;
5269 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5270 if (RT_LIKELY(rc == VINF_SUCCESS))
5271 { /* likely */ }
5272 else
5273 return rc;
5274
5275 /*
5276 * Virtual-8086 mode checks.
5277 */
5278 if (fGstInV86Mode)
5279 {
5280 /* Base address. */
5281 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5282 { /* likely */ }
5283 else
5284 {
5285 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5287 }
5288
5289 /* Limit. */
5290 if (SelReg.u32Limit == 0xffff)
5291 { /* likely */ }
5292 else
5293 {
5294 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5296 }
5297
5298 /* Attribute. */
5299 if (SelReg.Attr.u == 0xf3)
5300 { /* likely */ }
5301 else
5302 {
5303 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5305 }
5306
5307 /* We're done; move to checking the next segment. */
5308 continue;
5309 }
5310
5311 /* Checks done by 64-bit CPUs. */
5312 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5313 {
5314 /* Base address. */
5315 if ( iSegReg == X86_SREG_FS
5316 || iSegReg == X86_SREG_GS)
5317 {
5318 if (X86_IS_CANONICAL(SelReg.u64Base))
5319 { /* likely */ }
5320 else
5321 {
5322 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5324 }
5325 }
5326 else if (iSegReg == X86_SREG_CS)
5327 {
5328 if (!RT_HI_U32(SelReg.u64Base))
5329 { /* likely */ }
5330 else
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5332 }
5333 else
5334 {
5335 if ( SelReg.Attr.n.u1Unusable
5336 || !RT_HI_U32(SelReg.u64Base))
5337 { /* likely */ }
5338 else
5339 {
5340 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5342 }
5343 }
5344 }
5345
5346 /*
5347 * Checks outside Virtual-8086 mode.
5348 */
5349 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5350 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5351 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5352 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5353 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5354 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5355 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5356 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5357
5358 /* Code or usable segment. */
5359 if ( iSegReg == X86_SREG_CS
5360 || fUsable)
5361 {
5362 /* Reserved bits (bits 31:17 and bits 11:8). */
5363 if (!(SelReg.Attr.u & 0xfffe0f00))
5364 { /* likely */ }
5365 else
5366 {
5367 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5369 }
5370
5371 /* Descriptor type. */
5372 if (fCodeDataSeg)
5373 { /* likely */ }
5374 else
5375 {
5376 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5378 }
5379
5380 /* Present. */
5381 if (fPresent)
5382 { /* likely */ }
5383 else
5384 {
5385 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5387 }
5388
5389 /* Granularity. */
5390 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5391 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5392 { /* likely */ }
5393 else
5394 {
5395 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5397 }
5398 }
5399
5400 if (iSegReg == X86_SREG_CS)
5401 {
5402 /* Segment Type and DPL. */
5403 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5404 && fUnrestrictedGuest)
5405 {
5406 if (uDpl == 0)
5407 { /* likely */ }
5408 else
5409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5410 }
5411 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5412 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5413 {
5414 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5415 if (uDpl == AttrSs.n.u2Dpl)
5416 { /* likely */ }
5417 else
5418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5419 }
5420 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5421 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5422 {
5423 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5424 if (uDpl <= AttrSs.n.u2Dpl)
5425 { /* likely */ }
5426 else
5427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5428 }
5429 else
5430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5431
5432 /* Def/Big. */
5433 if ( fGstInLongMode
5434 && fSegLong)
5435 {
5436 if (uDefBig == 0)
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5440 }
5441 }
5442 else if (iSegReg == X86_SREG_SS)
5443 {
5444 /* Segment Type. */
5445 if ( !fUsable
5446 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5447 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5448 { /* likely */ }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5451
5452 /* DPL. */
5453 if (!fUnrestrictedGuest)
5454 {
5455 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5459 }
5460 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5461 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5462 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5463 {
5464 if (uDpl == 0)
5465 { /* likely */ }
5466 else
5467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5468 }
5469 }
5470 else
5471 {
5472 /* DS, ES, FS, GS. */
5473 if (fUsable)
5474 {
5475 /* Segment type. */
5476 if (uSegType & X86_SEL_TYPE_ACCESSED)
5477 { /* likely */ }
5478 else
5479 {
5480 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5482 }
5483
5484 if ( !(uSegType & X86_SEL_TYPE_CODE)
5485 || (uSegType & X86_SEL_TYPE_READ))
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5489
5490 /* DPL. */
5491 if ( !fUnrestrictedGuest
5492 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5493 {
5494 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5495 { /* likely */ }
5496 else
5497 {
5498 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5500 }
5501 }
5502 }
5503 }
5504 }
5505
5506 /*
5507 * LDTR.
5508 */
5509 {
5510 CPUMSELREG Ldtr;
5511 Ldtr.Sel = pVmcs->GuestLdtr;
5512 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5513 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5514 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5515
5516 if (!Ldtr.Attr.n.u1Unusable)
5517 {
5518 /* Selector. */
5519 if (!(Ldtr.Sel & X86_SEL_LDT))
5520 { /* likely */ }
5521 else
5522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5523
5524 /* Base. */
5525 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5526 {
5527 if (X86_IS_CANONICAL(Ldtr.u64Base))
5528 { /* likely */ }
5529 else
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5531 }
5532
5533 /* Attributes. */
5534 /* Reserved bits (bits 31:17 and bits 11:8). */
5535 if (!(Ldtr.Attr.u & 0xfffe0f00))
5536 { /* likely */ }
5537 else
5538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5539
5540 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5541 { /* likely */ }
5542 else
5543 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5544
5545 if (!Ldtr.Attr.n.u1DescType)
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5549
5550 if (Ldtr.Attr.n.u1Present)
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5554
5555 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5556 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5557 { /* likely */ }
5558 else
5559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5560 }
5561 }
5562
5563 /*
5564 * TR.
5565 */
5566 {
5567 CPUMSELREG Tr;
5568 Tr.Sel = pVmcs->GuestTr;
5569 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5570 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5571 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5572
5573 /* Selector. */
5574 if (!(Tr.Sel & X86_SEL_LDT))
5575 { /* likely */ }
5576 else
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5578
5579 /* Base. */
5580 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5581 {
5582 if (X86_IS_CANONICAL(Tr.u64Base))
5583 { /* likely */ }
5584 else
5585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5586 }
5587
5588 /* Attributes. */
5589 /* Reserved bits (bits 31:17 and bits 11:8). */
5590 if (!(Tr.Attr.u & 0xfffe0f00))
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5594
5595 if (!Tr.Attr.n.u1Unusable)
5596 { /* likely */ }
5597 else
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5599
5600 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5601 || ( !fGstInLongMode
5602 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5603 { /* likely */ }
5604 else
5605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5606
5607 if (!Tr.Attr.n.u1DescType)
5608 { /* likely */ }
5609 else
5610 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5611
5612 if (Tr.Attr.n.u1Present)
5613 { /* likely */ }
5614 else
5615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5616
5617 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5618 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5619 { /* likely */ }
5620 else
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5622 }
5623
5624 NOREF(pszInstr);
5625 NOREF(pszFailure);
5626 return VINF_SUCCESS;
5627}
5628
5629
5630/**
5631 * Checks guest GDTR and IDTR as part of VM-entry.
5632 *
5633 * @param pVCpu The cross context virtual CPU structure.
5634 * @param pszInstr The VMX instruction name (for logging purposes).
5635 */
5636IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5637{
5638 /*
5639 * GDTR and IDTR.
5640 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5641 */
5642 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5643 const char *const pszFailure = "VM-exit";
5644
5645 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5646 {
5647 /* Base. */
5648 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5649 { /* likely */ }
5650 else
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5652
5653 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5654 { /* likely */ }
5655 else
5656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5657 }
5658
5659 /* Limit. */
5660 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5661 { /* likely */ }
5662 else
5663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5664
5665 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5666 { /* likely */ }
5667 else
5668 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5669
5670 NOREF(pszInstr);
5671 NOREF(pszFailure);
5672 return VINF_SUCCESS;
5673}
5674
5675
5676/**
5677 * Checks guest RIP and RFLAGS as part of VM-entry.
5678 *
5679 * @param pVCpu The cross context virtual CPU structure.
5680 * @param pszInstr The VMX instruction name (for logging purposes).
5681 */
5682IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5683{
5684 /*
5685 * RIP and RFLAGS.
5686 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5687 */
5688 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5689 const char *const pszFailure = "VM-exit";
5690 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5691
5692 /* RIP. */
5693 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5694 {
5695 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5696 if ( !fGstInLongMode
5697 || !AttrCs.n.u1Long)
5698 {
5699 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5700 { /* likely */ }
5701 else
5702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5703 }
5704
5705 if ( fGstInLongMode
5706 && AttrCs.n.u1Long)
5707 {
5708 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5709 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5710 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5711 { /* likely */ }
5712 else
5713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5714 }
5715 }
5716
5717 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5718 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5719 : pVmcs->u64GuestRFlags.s.Lo;
5720 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5721 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5722 { /* likely */ }
5723 else
5724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5725
5726 if ( fGstInLongMode
5727 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5728 {
5729 if (!(uGuestRFlags & X86_EFL_VM))
5730 { /* likely */ }
5731 else
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5733 }
5734
5735 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5736 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5737 {
5738 if (uGuestRFlags & X86_EFL_IF)
5739 { /* likely */ }
5740 else
5741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5742 }
5743
5744 NOREF(pszInstr);
5745 NOREF(pszFailure);
5746 return VINF_SUCCESS;
5747}
5748
5749
5750/**
5751 * Checks guest non-register state as part of VM-entry.
5752 *
5753 * @param pVCpu The cross context virtual CPU structure.
5754 * @param pszInstr The VMX instruction name (for logging purposes).
5755 */
5756IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5757{
5758 /*
5759 * Guest non-register state.
5760 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5761 */
5762 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5763 const char *const pszFailure = "VM-exit";
5764
5765 /*
5766 * Activity state.
5767 */
5768 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5769 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5770 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5771 { /* likely */ }
5772 else
5773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5774
5775 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5776 if ( !AttrSs.n.u2Dpl
5777 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5778 { /* likely */ }
5779 else
5780 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5781
5782 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5783 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5784 {
5785 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5789 }
5790
5791 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5792 {
5793 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5794 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5795 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5796 switch (pVmcs->u32GuestActivityState)
5797 {
5798 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5799 {
5800 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5801 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5802 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5803 && ( uVector == X86_XCPT_DB
5804 || uVector == X86_XCPT_MC))
5805 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5806 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5807 { /* likely */ }
5808 else
5809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5810 break;
5811 }
5812
5813 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5814 {
5815 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5816 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5817 && uVector == X86_XCPT_MC))
5818 { /* likely */ }
5819 else
5820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5821 break;
5822 }
5823
5824 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5825 default:
5826 break;
5827 }
5828 }
5829
5830 /*
5831 * Interruptibility state.
5832 */
5833 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5834 { /* likely */ }
5835 else
5836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5837
5838 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5839 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5840 { /* likely */ }
5841 else
5842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5843
5844 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5845 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5846 { /* likely */ }
5847 else
5848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5849
5850 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5851 {
5852 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5853 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5854 {
5855 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5856 { /* likely */ }
5857 else
5858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5859 }
5860 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5861 {
5862 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5863 { /* likely */ }
5864 else
5865 {
5866 /*
5867 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5868 * We update the Exit qualification only when blocking-by-STI is set
5869 * without blocking-by-MovSS being set. Although in practise it does not
5870 * make much difference since the order of checks are implementation defined.
5871 */
5872 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5873 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5874 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5875 }
5876
5877 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5878 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5882 }
5883 }
5884
5885 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5886 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5887 { /* likely */ }
5888 else
5889 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5890
5891 /* We don't support SGX yet. So enclave-interruption must not be set. */
5892 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5893 { /* likely */ }
5894 else
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5896
5897 /*
5898 * Pending debug exceptions.
5899 */
5900 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5901 ? pVmcs->u64GuestPendingDbgXcpt.u
5902 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5903 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5904 { /* likely */ }
5905 else
5906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5907
5908 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5909 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5910 {
5911 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5912 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5913 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5915
5916 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5917 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5918 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5920 }
5921
5922 /* We don't support RTM (Real-time Transactional Memory) yet. */
5923 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5924 { /* likely */ }
5925 else
5926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5927
5928 /*
5929 * VMCS link pointer.
5930 */
5931 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5932 {
5933 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5934 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5935 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5936 { /* likely */ }
5937 else
5938 {
5939 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5941 }
5942
5943 /* Validate the address. */
5944 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5945 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5946 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5947 { /* likely */ }
5948 else
5949 {
5950 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5952 }
5953
5954 /* Read the VMCS-link pointer from guest memory. */
5955 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5956 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5957 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5958 if (RT_SUCCESS(rc))
5959 { /* likely */ }
5960 else
5961 {
5962 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5964 }
5965
5966 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5967 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5968 { /* likely */ }
5969 else
5970 {
5971 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5972 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5973 }
5974
5975 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5976 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5977 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5978 { /* likely */ }
5979 else
5980 {
5981 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5982 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5983 }
5984
5985 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5986 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5987 }
5988
5989 NOREF(pszInstr);
5990 NOREF(pszFailure);
5991 return VINF_SUCCESS;
5992}
5993
5994
5995/**
5996 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5997 * VM-entry.
5998 *
5999 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6000 * @param pVCpu The cross context virtual CPU structure.
6001 * @param pszInstr The VMX instruction name (for logging purposes).
6002 * @param pVmcs Pointer to the virtual VMCS.
6003 */
6004IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6005{
6006 /*
6007 * Check PDPTEs.
6008 * See Intel spec. 4.4.1 "PDPTE Registers".
6009 */
6010 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6011 const char *const pszFailure = "VM-exit";
6012
6013 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6014 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6015 if (RT_SUCCESS(rc))
6016 {
6017 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6018 {
6019 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6020 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6021 { /* likely */ }
6022 else
6023 {
6024 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6025 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6027 }
6028 }
6029 }
6030 else
6031 {
6032 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6034 }
6035
6036 NOREF(pszFailure);
6037 NOREF(pszInstr);
6038 return rc;
6039}
6040
6041
6042/**
6043 * Checks guest PDPTEs as part of VM-entry.
6044 *
6045 * @param pVCpu The cross context virtual CPU structure.
6046 * @param pszInstr The VMX instruction name (for logging purposes).
6047 */
6048IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6049{
6050 /*
6051 * Guest PDPTEs.
6052 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6053 */
6054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6055 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6056
6057 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6058 int rc;
6059 if ( !fGstInLongMode
6060 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6061 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6062 {
6063 /*
6064 * We don't support nested-paging for nested-guests yet.
6065 *
6066 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6067 * rather we need to check the PDPTEs referenced by the guest CR3.
6068 */
6069 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6070 }
6071 else
6072 rc = VINF_SUCCESS;
6073 return rc;
6074}
6075
6076
6077/**
6078 * Checks guest-state as part of VM-entry.
6079 *
6080 * @returns VBox status code.
6081 * @param pVCpu The cross context virtual CPU structure.
6082 * @param pszInstr The VMX instruction name (for logging purposes).
6083 */
6084IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6085{
6086 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6087 if (RT_SUCCESS(rc))
6088 {
6089 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6090 if (RT_SUCCESS(rc))
6091 {
6092 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6093 if (RT_SUCCESS(rc))
6094 {
6095 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6096 if (RT_SUCCESS(rc))
6097 {
6098 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6099 if (RT_SUCCESS(rc))
6100 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6101 }
6102 }
6103 }
6104 }
6105 return rc;
6106}
6107
6108
6109/**
6110 * Checks host-state as part of VM-entry.
6111 *
6112 * @returns VBox status code.
6113 * @param pVCpu The cross context virtual CPU structure.
6114 * @param pszInstr The VMX instruction name (for logging purposes).
6115 */
6116IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6117{
6118 /*
6119 * Host Control Registers and MSRs.
6120 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6121 */
6122 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6123 const char * const pszFailure = "VMFail";
6124
6125 /* CR0 reserved bits. */
6126 {
6127 /* CR0 MB1 bits. */
6128 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6129 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6133
6134 /* CR0 MBZ bits. */
6135 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6136 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6140 }
6141
6142 /* CR4 reserved bits. */
6143 {
6144 /* CR4 MB1 bits. */
6145 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6146 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6147 { /* likely */ }
6148 else
6149 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6150
6151 /* CR4 MBZ bits. */
6152 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6153 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6154 { /* likely */ }
6155 else
6156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6157 }
6158
6159 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6160 {
6161 /* CR3 reserved bits. */
6162 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6163 { /* likely */ }
6164 else
6165 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6166
6167 /* SYSENTER ESP and SYSENTER EIP. */
6168 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6169 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6173 }
6174
6175 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6176 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6177
6178 /* PAT MSR. */
6179 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6180 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6181 { /* likely */ }
6182 else
6183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6184
6185 /* EFER MSR. */
6186 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6187 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6188 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6189 { /* likely */ }
6190 else
6191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6192
6193 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6194 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6195 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6196 if ( fHostInLongMode == fHostLma
6197 && fHostInLongMode == fHostLme)
6198 { /* likely */ }
6199 else
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6201
6202 /*
6203 * Host Segment and Descriptor-Table Registers.
6204 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6205 */
6206 /* Selector RPL and TI. */
6207 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6208 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6209 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6210 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6211 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6212 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6213 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6214 { /* likely */ }
6215 else
6216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6217
6218 /* CS and TR selectors cannot be 0. */
6219 if ( pVmcs->HostCs
6220 && pVmcs->HostTr)
6221 { /* likely */ }
6222 else
6223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6224
6225 /* SS cannot be 0 if 32-bit host. */
6226 if ( fHostInLongMode
6227 || pVmcs->HostSs)
6228 { /* likely */ }
6229 else
6230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6231
6232 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6233 {
6234 /* FS, GS, GDTR, IDTR, TR base address. */
6235 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6236 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6237 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6238 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6239 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6243 }
6244
6245 /*
6246 * Host address-space size for 64-bit CPUs.
6247 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6248 */
6249 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6250 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6251 {
6252 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6253
6254 /* Logical processor in IA-32e mode. */
6255 if (fCpuInLongMode)
6256 {
6257 if (fHostInLongMode)
6258 {
6259 /* PAE must be set. */
6260 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6261 { /* likely */ }
6262 else
6263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6264
6265 /* RIP must be canonical. */
6266 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6267 { /* likely */ }
6268 else
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6270 }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6273 }
6274 else
6275 {
6276 /* Logical processor is outside IA-32e mode. */
6277 if ( !fGstInLongMode
6278 && !fHostInLongMode)
6279 {
6280 /* PCIDE should not be set. */
6281 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6282 { /* likely */ }
6283 else
6284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6285
6286 /* The high 32-bits of RIP MBZ. */
6287 if (!pVmcs->u64HostRip.s.Hi)
6288 { /* likely */ }
6289 else
6290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6291 }
6292 else
6293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6294 }
6295 }
6296 else
6297 {
6298 /* Host address-space size for 32-bit CPUs. */
6299 if ( !fGstInLongMode
6300 && !fHostInLongMode)
6301 { /* likely */ }
6302 else
6303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6304 }
6305
6306 NOREF(pszInstr);
6307 NOREF(pszFailure);
6308 return VINF_SUCCESS;
6309}
6310
6311
6312/**
6313 * Checks VM-entry controls fields as part of VM-entry.
6314 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6315 *
6316 * @returns VBox status code.
6317 * @param pVCpu The cross context virtual CPU structure.
6318 * @param pszInstr The VMX instruction name (for logging purposes).
6319 */
6320IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6321{
6322 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6323 const char * const pszFailure = "VMFail";
6324
6325 /* VM-entry controls. */
6326 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6327 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6328 { /* likely */ }
6329 else
6330 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6331
6332 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6333 { /* likely */ }
6334 else
6335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6336
6337 /* Event injection. */
6338 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6339 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6340 {
6341 /* Type and vector. */
6342 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6343 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6344 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6345 if ( !uRsvd
6346 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6347 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6348 { /* likely */ }
6349 else
6350 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6351
6352 /* Exception error code. */
6353 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6354 {
6355 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6356 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6357 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6361
6362 /* Exceptions that provide an error code. */
6363 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6364 && ( uVector == X86_XCPT_DF
6365 || uVector == X86_XCPT_TS
6366 || uVector == X86_XCPT_NP
6367 || uVector == X86_XCPT_SS
6368 || uVector == X86_XCPT_GP
6369 || uVector == X86_XCPT_PF
6370 || uVector == X86_XCPT_AC))
6371 { /* likely */ }
6372 else
6373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6374
6375 /* Exception error-code reserved bits. */
6376 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6377 { /* likely */ }
6378 else
6379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6380
6381 /* Injecting a software interrupt, software exception or privileged software exception. */
6382 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6383 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6384 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6385 {
6386 /* Instruction length must be in the range 0-15. */
6387 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6391
6392 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6393 if ( pVmcs->u32EntryInstrLen == 0
6394 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6396 }
6397 }
6398 }
6399
6400 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6401 if (pVmcs->u32EntryMsrLoadCount)
6402 {
6403 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6404 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6405 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6406 { /* likely */ }
6407 else
6408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6409 }
6410
6411 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6412 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6413
6414 NOREF(pszInstr);
6415 NOREF(pszFailure);
6416 return VINF_SUCCESS;
6417}
6418
6419
6420/**
6421 * Checks VM-exit controls fields as part of VM-entry.
6422 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6423 *
6424 * @returns VBox status code.
6425 * @param pVCpu The cross context virtual CPU structure.
6426 * @param pszInstr The VMX instruction name (for logging purposes).
6427 */
6428IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6429{
6430 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6431 const char * const pszFailure = "VMFail";
6432
6433 /* VM-exit controls. */
6434 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6435 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6436 { /* likely */ }
6437 else
6438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6439
6440 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6441 { /* likely */ }
6442 else
6443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6444
6445 /* Save preemption timer without activating it. */
6446 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6447 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6448 { /* likely */ }
6449 else
6450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6451
6452 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6453 if (pVmcs->u32ExitMsrStoreCount)
6454 {
6455 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6456 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6457 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6458 { /* likely */ }
6459 else
6460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6461 }
6462
6463 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6464 if (pVmcs->u32ExitMsrLoadCount)
6465 {
6466 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6467 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6468 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6469 { /* likely */ }
6470 else
6471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6472 }
6473
6474 NOREF(pszInstr);
6475 NOREF(pszFailure);
6476 return VINF_SUCCESS;
6477}
6478
6479
6480/**
6481 * Checks VM-execution controls fields as part of VM-entry.
6482 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6483 *
6484 * @returns VBox status code.
6485 * @param pVCpu The cross context virtual CPU structure.
6486 * @param pszInstr The VMX instruction name (for logging purposes).
6487 *
6488 * @remarks This may update secondary-processor based VM-execution control fields
6489 * in the current VMCS if necessary.
6490 */
6491IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6492{
6493 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6494 const char * const pszFailure = "VMFail";
6495
6496 /* Pin-based VM-execution controls. */
6497 {
6498 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6499 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6500 { /* likely */ }
6501 else
6502 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6503
6504 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6505 { /* likely */ }
6506 else
6507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6508 }
6509
6510 /* Processor-based VM-execution controls. */
6511 {
6512 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6513 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6514 { /* likely */ }
6515 else
6516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6517
6518 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6519 { /* likely */ }
6520 else
6521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6522 }
6523
6524 /* Secondary processor-based VM-execution controls. */
6525 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6526 {
6527 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6528 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6529 { /* likely */ }
6530 else
6531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6532
6533 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6534 { /* likely */ }
6535 else
6536 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6537 }
6538 else
6539 Assert(!pVmcs->u32ProcCtls2);
6540
6541 /* CR3-target count. */
6542 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6543 { /* likely */ }
6544 else
6545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6546
6547 /* I/O bitmaps physical addresses. */
6548 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6549 {
6550 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6551 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6552 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6553 { /* likely */ }
6554 else
6555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6556
6557 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6558 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6559 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6560 { /* likely */ }
6561 else
6562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6563 }
6564
6565 /* MSR bitmap physical address. */
6566 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6567 {
6568 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6569 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6570 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6571 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6572 { /* likely */ }
6573 else
6574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6575
6576 /* Read the MSR bitmap. */
6577 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6578 * implementing fast path. */
6579 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6580 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6581 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6582 if (RT_SUCCESS(rc))
6583 { /* likely */ }
6584 else
6585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6586 }
6587
6588 /* TPR shadow related controls. */
6589 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6590 {
6591 /* Virtual-APIC page physical address. */
6592 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6593 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6594 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6595 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6596 { /* likely */ }
6597 else
6598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6599
6600 /* TPR threshold without virtual-interrupt delivery. */
6601 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6602 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6604
6605 /* TPR threshold and VTPR. */
6606 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6607 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6608 {
6609 /* Read the VTPR from the virtual-APIC page. */
6610 uint8_t u8VTpr;
6611 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6612 if (RT_SUCCESS(rc))
6613 { /* likely */ }
6614 else
6615 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6616
6617 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6618 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6619 { /* likely */ }
6620 else
6621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6622 }
6623 }
6624 else
6625 {
6626 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6627 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6628 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6629 { /* likely */ }
6630 else
6631 {
6632 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6634 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6636 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6638 }
6639 }
6640
6641 /* NMI exiting and virtual-NMIs. */
6642 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6643 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6644 { /* likely */ }
6645 else
6646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6647
6648 /* Virtual-NMIs and NMI-window exiting. */
6649 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6650 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6651 { /* likely */ }
6652 else
6653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6654
6655 /* Virtualize APIC accesses. */
6656 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6657 {
6658 /* APIC-access physical address. */
6659 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6660 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6661 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6662 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6663 { /* likely */ }
6664 else
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6666
6667 /*
6668 * Disallow APIC-access page and virtual-APIC page from being the same address.
6669 * Note! This is not an Intel requirement, but one imposed by our implementation.
6670 */
6671 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6672 * redirecting accesses between the APIC-access page and the virtual-APIC
6673 * page. If any nested hypervisor requires this, we can implement it later. */
6674 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6675 {
6676 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6677 if (GCPhysVirtApic != GCPhysApicAccess)
6678 { /* likely */ }
6679 else
6680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6681 }
6682
6683 /*
6684 * Register the handler for the APIC-access page.
6685 *
6686 * We don't deregister the APIC-access page handler during the VM-exit as a different
6687 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6688 *
6689 * We leave the page registered until the first access that happens outside VMX non-root
6690 * mode. Guest software is allowed to access structures such as the APIC-access page
6691 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6692 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6693 *
6694 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6695 */
6696 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6697 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6698 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6699 if (RT_SUCCESS(rc))
6700 { /* likely */ }
6701 else
6702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6703 }
6704
6705 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6706 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6707 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6708 { /* likely */ }
6709 else
6710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6711
6712 /* Virtual-interrupt delivery requires external interrupt exiting. */
6713 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6714 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6715 { /* likely */ }
6716 else
6717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6718
6719 /* VPID. */
6720 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6721 || pVmcs->u16Vpid != 0)
6722 { /* likely */ }
6723 else
6724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6725
6726 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6727 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6728 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6729 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6730 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6731 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6732 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6733
6734 /* VMCS shadowing. */
6735 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6736 {
6737 /* VMREAD-bitmap physical address. */
6738 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6739 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6740 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6741 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6742 { /* likely */ }
6743 else
6744 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6745
6746 /* VMWRITE-bitmap physical address. */
6747 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6748 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6749 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6750 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6751 { /* likely */ }
6752 else
6753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6754
6755 /* Read the VMREAD-bitmap. */
6756 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6757 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6758 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6759 if (RT_SUCCESS(rc))
6760 { /* likely */ }
6761 else
6762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6763
6764 /* Read the VMWRITE-bitmap. */
6765 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6766 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6767 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6768 if (RT_SUCCESS(rc))
6769 { /* likely */ }
6770 else
6771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6772 }
6773
6774 NOREF(pszInstr);
6775 NOREF(pszFailure);
6776 return VINF_SUCCESS;
6777}
6778
6779
6780/**
6781 * Loads the guest control registers, debug register and some MSRs as part of
6782 * VM-entry.
6783 *
6784 * @param pVCpu The cross context virtual CPU structure.
6785 */
6786IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6787{
6788 /*
6789 * Load guest control registers, debug registers and MSRs.
6790 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6791 */
6792 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6793
6794 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6795 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6796 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6797 CPUMSetGuestCR0(pVCpu, uGstCr0);
6798 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6799 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6800
6801 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6802 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6803
6804 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6805 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6806 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6807
6808 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6809 {
6810 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6811
6812 /* EFER MSR. */
6813 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6814 {
6815 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6816 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6817 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6818 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6819 if (fGstInLongMode)
6820 {
6821 /* If the nested-guest is in long mode, LMA and LME are both set. */
6822 Assert(fGstPaging);
6823 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6824 }
6825 else
6826 {
6827 /*
6828 * If the nested-guest is outside long mode:
6829 * - With paging: LMA is cleared, LME is cleared.
6830 * - Without paging: LMA is cleared, LME is left unmodified.
6831 */
6832 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6833 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6834 }
6835 }
6836 /* else: see below. */
6837 }
6838
6839 /* PAT MSR. */
6840 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6841 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6842
6843 /* EFER MSR. */
6844 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6845 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6846
6847 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6848 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6849
6850 /* We don't support IA32_BNDCFGS MSR yet. */
6851 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6852
6853 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6854}
6855
6856
6857/**
6858 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6859 *
6860 * @param pVCpu The cross context virtual CPU structure.
6861 */
6862IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6863{
6864 /*
6865 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6866 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6867 */
6868 /* CS, SS, ES, DS, FS, GS. */
6869 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6870 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6871 {
6872 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6873 CPUMSELREG VmcsSelReg;
6874 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6875 AssertRC(rc); NOREF(rc);
6876 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6877 {
6878 pGstSelReg->Sel = VmcsSelReg.Sel;
6879 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6880 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6881 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6882 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6883 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6884 }
6885 else
6886 {
6887 pGstSelReg->Sel = VmcsSelReg.Sel;
6888 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6889 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6890 switch (iSegReg)
6891 {
6892 case X86_SREG_CS:
6893 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6894 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6895 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6896 break;
6897
6898 case X86_SREG_SS:
6899 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6900 pGstSelReg->u32Limit = 0;
6901 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6902 break;
6903
6904 case X86_SREG_ES:
6905 case X86_SREG_DS:
6906 pGstSelReg->u64Base = 0;
6907 pGstSelReg->u32Limit = 0;
6908 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6909 break;
6910
6911 case X86_SREG_FS:
6912 case X86_SREG_GS:
6913 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6914 pGstSelReg->u32Limit = 0;
6915 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6916 break;
6917 }
6918 Assert(pGstSelReg->Attr.n.u1Unusable);
6919 }
6920 }
6921
6922 /* LDTR. */
6923 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6924 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6925 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6926 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6927 {
6928 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6929 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6930 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6931 }
6932 else
6933 {
6934 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6935 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6936 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6937 }
6938
6939 /* TR. */
6940 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6941 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6942 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6943 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6944 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6945 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6946 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6947
6948 /* GDTR. */
6949 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6950 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6951
6952 /* IDTR. */
6953 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6954 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6955}
6956
6957
6958/**
6959 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6960 *
6961 * @returns VBox status code.
6962 * @param pVCpu The cross context virtual CPU structure.
6963 * @param pszInstr The VMX instruction name (for logging purposes).
6964 */
6965IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6966{
6967 /*
6968 * Load guest MSRs.
6969 * See Intel spec. 26.4 "Loading MSRs".
6970 */
6971 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6972 const char *const pszFailure = "VM-exit";
6973
6974 /*
6975 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6976 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6977 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6978 */
6979 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6980 if (!cMsrs)
6981 return VINF_SUCCESS;
6982
6983 /*
6984 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6985 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6986 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6987 */
6988 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6989 if (fIsMsrCountValid)
6990 { /* likely */ }
6991 else
6992 {
6993 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6995 }
6996
6997 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6998 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6999 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7000 if (RT_SUCCESS(rc))
7001 {
7002 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
7003 Assert(pMsr);
7004 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7005 {
7006 if ( !pMsr->u32Reserved
7007 && pMsr->u32Msr != MSR_K8_FS_BASE
7008 && pMsr->u32Msr != MSR_K8_GS_BASE
7009 && pMsr->u32Msr != MSR_K6_EFER
7010 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7011 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7012 {
7013 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7014 if (rcStrict == VINF_SUCCESS)
7015 continue;
7016
7017 /*
7018 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7019 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7020 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7021 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7022 * MSR in ring-0 if possible, or come up with a better, generic solution.
7023 */
7024 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7025 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7026 ? kVmxVDiag_Vmentry_MsrLoadRing3
7027 : kVmxVDiag_Vmentry_MsrLoad;
7028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7029 }
7030 else
7031 {
7032 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7034 }
7035 }
7036 }
7037 else
7038 {
7039 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7041 }
7042
7043 NOREF(pszInstr);
7044 NOREF(pszFailure);
7045 return VINF_SUCCESS;
7046}
7047
7048
7049/**
7050 * Loads the guest-state non-register state as part of VM-entry.
7051 *
7052 * @returns VBox status code.
7053 * @param pVCpu The cross context virtual CPU structure.
7054 *
7055 * @remarks This must be called only after loading the nested-guest register state
7056 * (especially nested-guest RIP).
7057 */
7058IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7059{
7060 /*
7061 * Load guest non-register state.
7062 * See Intel spec. 26.6 "Special Features of VM Entry"
7063 */
7064 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7065
7066 /*
7067 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7068 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7069 *
7070 * See Intel spec. 26.6.1 "Interruptibility State".
7071 */
7072 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7073 if ( !fEntryVectoring
7074 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7075 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7076 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7077 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7078
7079 /* NMI blocking. */
7080 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7081 {
7082 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7083 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7084 else
7085 {
7086 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7087 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7088 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7089 }
7090 }
7091 else
7092 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7093
7094 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7095
7096 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7097 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7098
7099 /* VPID is irrelevant. We don't support VPID yet. */
7100
7101 /* Clear address-range monitoring. */
7102 EMMonitorWaitClear(pVCpu);
7103}
7104
7105
7106/**
7107 * Loads the guest-state as part of VM-entry.
7108 *
7109 * @returns VBox status code.
7110 * @param pVCpu The cross context virtual CPU structure.
7111 * @param pszInstr The VMX instruction name (for logging purposes).
7112 *
7113 * @remarks This must be done after all the necessary steps prior to loading of
7114 * guest-state (e.g. checking various VMCS state).
7115 */
7116IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7117{
7118 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7119 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7120
7121 /*
7122 * Load guest RIP, RSP and RFLAGS.
7123 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7124 */
7125 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7126 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7127 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7128 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7129
7130 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7131 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7132 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7133
7134 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7135
7136 NOREF(pszInstr);
7137 return VINF_SUCCESS;
7138}
7139
7140
7141/**
7142 * Returns whether there are is a pending debug exception on VM-entry.
7143 *
7144 * @param pVCpu The cross context virtual CPU structure.
7145 * @param pszInstr The VMX instruction name (for logging purposes).
7146 */
7147IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7148{
7149 /*
7150 * Pending debug exceptions.
7151 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7152 */
7153 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7154 Assert(pVmcs);
7155
7156 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7157 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7158 if (fPendingDbgXcpt)
7159 {
7160 uint8_t uEntryIntInfoType;
7161 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7162 if (fEntryVectoring)
7163 {
7164 switch (uEntryIntInfoType)
7165 {
7166 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7167 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7168 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7169 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7170 fPendingDbgXcpt = false;
7171 break;
7172
7173 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7174 {
7175 /*
7176 * Whether the pending debug exception for software exceptions other than
7177 * #BP and #OF is delivered after injecting the exception or is discard
7178 * is CPU implementation specific. We will discard them (easier).
7179 */
7180 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7181 if ( uVector != X86_XCPT_BP
7182 && uVector != X86_XCPT_OF)
7183 fPendingDbgXcpt = false;
7184 RT_FALL_THRU();
7185 }
7186 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7187 {
7188 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7189 fPendingDbgXcpt = false;
7190 break;
7191 }
7192 }
7193 }
7194 else
7195 {
7196 /*
7197 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7198 * pending debug exception is held pending or is discarded is CPU implementation
7199 * specific. We will discard them (easier).
7200 */
7201 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7202 fPendingDbgXcpt = false;
7203
7204 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7205 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7206 fPendingDbgXcpt = false;
7207 }
7208 }
7209
7210 NOREF(pszInstr);
7211 return fPendingDbgXcpt;
7212}
7213
7214
7215/**
7216 * Set up the monitor-trap flag (MTF).
7217 *
7218 * @param pVCpu The cross context virtual CPU structure.
7219 * @param pszInstr The VMX instruction name (for logging purposes).
7220 */
7221IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7222{
7223 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7224 Assert(pVmcs);
7225 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7226 {
7227 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7228 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7229 }
7230 else
7231 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7232 NOREF(pszInstr);
7233}
7234
7235
7236/**
7237 * Sets up NMI-window exiting.
7238 *
7239 * @param pVCpu The cross context virtual CPU structure.
7240 * @param pszInstr The VMX instruction name (for logging purposes).
7241 */
7242IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7243{
7244 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7245 Assert(pVmcs);
7246 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7247 {
7248 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7249 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7250 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7251 }
7252 else
7253 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7254 NOREF(pszInstr);
7255}
7256
7257
7258/**
7259 * Sets up interrupt-window exiting.
7260 *
7261 * @param pVCpu The cross context virtual CPU structure.
7262 * @param pszInstr The VMX instruction name (for logging purposes).
7263 */
7264IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7265{
7266 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7267 Assert(pVmcs);
7268 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7269 {
7270 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7271 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7272 }
7273 else
7274 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7275 NOREF(pszInstr);
7276}
7277
7278
7279/**
7280 * Set up the VMX-preemption timer.
7281 *
7282 * @param pVCpu The cross context virtual CPU structure.
7283 * @param pszInstr The VMX instruction name (for logging purposes).
7284 */
7285IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7286{
7287 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7288 Assert(pVmcs);
7289 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7290 {
7291 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7292 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7293 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7294
7295 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7296 }
7297 else
7298 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7299
7300 NOREF(pszInstr);
7301}
7302
7303
7304/**
7305 * Injects an event using TRPM given a VM-entry interruption info. and related
7306 * fields.
7307 *
7308 * @returns VBox status code.
7309 * @param pVCpu The cross context virtual CPU structure.
7310 * @param uEntryIntInfo The VM-entry interruption info.
7311 * @param uErrCode The error code associated with the event if any.
7312 * @param cbInstr The VM-entry instruction length (for software
7313 * interrupts and software exceptions). Pass 0
7314 * otherwise.
7315 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7316 */
7317IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7318 RTGCUINTPTR GCPtrFaultAddress)
7319{
7320 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7321
7322 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7323 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7324 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7325
7326 TRPMEVENT enmTrapType;
7327 switch (uType)
7328 {
7329 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7330 enmTrapType = TRPM_HARDWARE_INT;
7331 break;
7332
7333 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7334 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7335 enmTrapType = TRPM_TRAP;
7336 break;
7337
7338 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7339 enmTrapType = TRPM_SOFTWARE_INT;
7340 break;
7341
7342 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7343 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7344 enmTrapType = TRPM_SOFTWARE_INT;
7345 break;
7346
7347 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7348 Assert(uVector == X86_XCPT_DB);
7349 enmTrapType = TRPM_SOFTWARE_INT;
7350 break;
7351
7352 default:
7353 /* Shouldn't really happen. */
7354 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7355 break;
7356 }
7357
7358 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7359 AssertRCReturn(rc, rc);
7360
7361 if (fErrCodeValid)
7362 TRPMSetErrorCode(pVCpu, uErrCode);
7363
7364 if ( enmTrapType == TRPM_TRAP
7365 && uVector == X86_XCPT_PF)
7366 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7367 else if (enmTrapType == TRPM_SOFTWARE_INT)
7368 TRPMSetInstrLength(pVCpu, cbInstr);
7369
7370 return VINF_SUCCESS;
7371}
7372
7373
7374/**
7375 * Performs event injection (if any) as part of VM-entry.
7376 *
7377 * @param pVCpu The cross context virtual CPU structure.
7378 * @param pszInstr The VMX instruction name (for logging purposes).
7379 */
7380IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7381{
7382 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7383
7384 /*
7385 * Inject events.
7386 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7387 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7388 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7389 * the actually delivery of this event.
7390 *
7391 * See Intel spec. 26.5 "Event Injection".
7392 */
7393 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7394 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7395
7396 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7397 if (fEntryIntInfoValid)
7398 {
7399 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7400 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7401 {
7402 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7403 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7404 return VINF_SUCCESS;
7405 }
7406
7407 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7408 pVCpu->cpum.GstCtx.cr2);
7409 if (RT_SUCCESS(rc))
7410 {
7411 /*
7412 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7413 *
7414 * However, we do it here on VM-entry because while it continues to not be visible to
7415 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7416 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7417 * information field.
7418 *
7419 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7420 */
7421 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7422 }
7423 return rc;
7424 }
7425
7426 /*
7427 * Inject any pending guest debug exception.
7428 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7429 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7430 */
7431 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7432 if (fPendingDbgXcpt)
7433 {
7434 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7435 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7436 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7437 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7438 0 /* GCPtrFaultAddress */);
7439 }
7440
7441 NOREF(pszInstr);
7442 return VINF_SUCCESS;
7443}
7444
7445
7446/**
7447 * Initializes all read-only VMCS fields as part of VM-entry.
7448 *
7449 * @param pVCpu The cross context virtual CPU structure.
7450 */
7451IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7452{
7453 /*
7454 * Any VMCS field which we do not establish on every VM-exit but may potentially
7455 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7456 * specified to be undefined needs to be initialized here.
7457 *
7458 * Thus, it is especially important to clear the Exit qualification field
7459 * since it must be zero for VM-exits where it is not used. Similarly, the
7460 * VM-exit interruption information field's valid bit needs to be cleared for
7461 * the same reasons.
7462 */
7463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7464 Assert(pVmcs);
7465
7466 /* 16-bit (none currently). */
7467 /* 32-bit. */
7468 pVmcs->u32RoVmInstrError = 0;
7469 pVmcs->u32RoExitReason = 0;
7470 pVmcs->u32RoExitIntInfo = 0;
7471 pVmcs->u32RoExitIntErrCode = 0;
7472 pVmcs->u32RoIdtVectoringInfo = 0;
7473 pVmcs->u32RoIdtVectoringErrCode = 0;
7474 pVmcs->u32RoExitInstrLen = 0;
7475 pVmcs->u32RoExitInstrInfo = 0;
7476
7477 /* 64-bit. */
7478 pVmcs->u64RoGuestPhysAddr.u = 0;
7479
7480 /* Natural-width. */
7481 pVmcs->u64RoExitQual.u = 0;
7482 pVmcs->u64RoIoRcx.u = 0;
7483 pVmcs->u64RoIoRsi.u = 0;
7484 pVmcs->u64RoIoRdi.u = 0;
7485 pVmcs->u64RoIoRip.u = 0;
7486 pVmcs->u64RoGuestLinearAddr.u = 0;
7487}
7488
7489
7490/**
7491 * VMLAUNCH/VMRESUME instruction execution worker.
7492 *
7493 * @returns Strict VBox status code.
7494 * @param pVCpu The cross context virtual CPU structure.
7495 * @param cbInstr The instruction length in bytes.
7496 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7497 * VMXINSTRID_VMRESUME).
7498 *
7499 * @remarks Common VMX instruction checks are already expected to by the caller,
7500 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7501 */
7502IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7503{
7504# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7505 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7506 return VINF_EM_RAW_EMULATE_INSTR;
7507# else
7508 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7509 || uInstrId == VMXINSTRID_VMRESUME);
7510 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7511
7512 /* Nested-guest intercept. */
7513 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7514 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7515
7516 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7517
7518 /*
7519 * Basic VM-entry checks.
7520 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7521 * The checks following that do not have to follow a specific order.
7522 *
7523 * See Intel spec. 26.1 "Basic VM-entry Checks".
7524 */
7525
7526 /* CPL. */
7527 if (pVCpu->iem.s.uCpl == 0)
7528 { /* likely */ }
7529 else
7530 {
7531 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7532 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7533 return iemRaiseGeneralProtectionFault0(pVCpu);
7534 }
7535
7536 /* Current VMCS valid. */
7537 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7538 { /* likely */ }
7539 else
7540 {
7541 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7542 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7543 iemVmxVmFailInvalid(pVCpu);
7544 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7545 return VINF_SUCCESS;
7546 }
7547
7548 /* Current VMCS is not a shadow VMCS. */
7549 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7550 { /* likely */ }
7551 else
7552 {
7553 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7554 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7555 iemVmxVmFailInvalid(pVCpu);
7556 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7557 return VINF_SUCCESS;
7558 }
7559
7560 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7561 * use block-by-STI here which is not quite correct. */
7562 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7563 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7564 { /* likely */ }
7565 else
7566 {
7567 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7569 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7570 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7571 return VINF_SUCCESS;
7572 }
7573
7574 if (uInstrId == VMXINSTRID_VMLAUNCH)
7575 {
7576 /* VMLAUNCH with non-clear VMCS. */
7577 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7578 { /* likely */ }
7579 else
7580 {
7581 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7582 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7583 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7584 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7585 return VINF_SUCCESS;
7586 }
7587 }
7588 else
7589 {
7590 /* VMRESUME with non-launched VMCS. */
7591 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7592 { /* likely */ }
7593 else
7594 {
7595 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7596 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7597 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7599 return VINF_SUCCESS;
7600 }
7601 }
7602
7603 /*
7604 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7605 * while entering VMX non-root mode. We do some of this while checking VM-execution
7606 * controls. The guest hypervisor should not make assumptions and cannot expect
7607 * predictable behavior if changes to these structures are made in guest memory while
7608 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7609 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7610 *
7611 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7612 */
7613 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7614 Assert(pVmcs);
7615 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7616
7617 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7618 if (RT_SUCCESS(rc))
7619 {
7620 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7621 if (RT_SUCCESS(rc))
7622 {
7623 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7624 if (RT_SUCCESS(rc))
7625 {
7626 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7627 if (RT_SUCCESS(rc))
7628 {
7629 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7630 iemVmxVmentryInitReadOnlyFields(pVCpu);
7631
7632 /*
7633 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7634 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7635 * VM-exit when required.
7636 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7637 */
7638 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7639
7640 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7641 if (RT_SUCCESS(rc))
7642 {
7643 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7644 if (RT_SUCCESS(rc))
7645 {
7646 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7647 if (RT_SUCCESS(rc))
7648 {
7649 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7650
7651 /* VMLAUNCH instruction must update the VMCS launch state. */
7652 if (uInstrId == VMXINSTRID_VMLAUNCH)
7653 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7654
7655 /* Perform the VMX transition (PGM updates). */
7656 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7657 if (rcStrict == VINF_SUCCESS)
7658 { /* likely */ }
7659 else if (RT_SUCCESS(rcStrict))
7660 {
7661 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7662 VBOXSTRICTRC_VAL(rcStrict)));
7663 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7664 }
7665 else
7666 {
7667 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7668 return rcStrict;
7669 }
7670
7671 /* We've now entered nested-guest execution. */
7672 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7673
7674 /*
7675 * The priority of potential VM-exits during VM-entry is important.
7676 * The priorities of VM-exits and events are listed from highest
7677 * to lowest as follows:
7678 *
7679 * 1. Event injection.
7680 * 2. Trap on task-switch (T flag set in TSS).
7681 * 3. TPR below threshold / APIC-write.
7682 * 4. SMI, INIT.
7683 * 5. MTF exit.
7684 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7685 * 7. VMX-preemption timer.
7686 * 9. NMI-window exit.
7687 * 10. NMI injection.
7688 * 11. Interrupt-window exit.
7689 * 12. Virtual-interrupt injection.
7690 * 13. Interrupt injection.
7691 * 14. Process next instruction (fetch, decode, execute).
7692 */
7693
7694 /* Setup the VMX-preemption timer. */
7695 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7696
7697 /* Setup monitor-trap flag. */
7698 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7699
7700 /* Setup NMI-window exiting. */
7701 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7702
7703 /* Setup interrupt-window exiting. */
7704 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7705
7706 /* Now that we've switched page tables, we can go ahead and inject any event. */
7707 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7708 if (RT_SUCCESS(rcStrict))
7709 {
7710 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7711# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7712 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7713 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7714 if (rcSched != VINF_SUCCESS)
7715 iemSetPassUpStatus(pVCpu, rcSched);
7716# endif
7717 return VINF_SUCCESS;
7718 }
7719
7720 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7721 return rcStrict;
7722 }
7723 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7724 pVmcs->u64RoExitQual.u);
7725 }
7726 }
7727 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7728 pVmcs->u64RoExitQual.u);
7729 }
7730
7731 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7732 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7733 return VINF_SUCCESS;
7734 }
7735 }
7736 }
7737
7738 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7739 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7740 return VINF_SUCCESS;
7741# endif
7742}
7743
7744
7745/**
7746 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7747 * (causes a VM-exit) or not.
7748 *
7749 * @returns @c true if the instruction is intercepted, @c false otherwise.
7750 * @param pVCpu The cross context virtual CPU structure.
7751 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7752 * VMX_EXIT_WRMSR).
7753 * @param idMsr The MSR.
7754 */
7755IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7756{
7757 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7758 Assert( uExitReason == VMX_EXIT_RDMSR
7759 || uExitReason == VMX_EXIT_WRMSR);
7760
7761 /* Consult the MSR bitmap if the feature is supported. */
7762 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7763 Assert(pVmcs);
7764 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7765 {
7766 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7767 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7768 if (uExitReason == VMX_EXIT_RDMSR)
7769 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7770 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7771 }
7772
7773 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7774 return true;
7775}
7776
7777
7778/**
7779 * VMREAD common (memory/register) instruction execution worker
7780 *
7781 * @returns Strict VBox status code.
7782 * @param pVCpu The cross context virtual CPU structure.
7783 * @param cbInstr The instruction length in bytes.
7784 * @param pu64Dst Where to write the VMCS value (only updated when
7785 * VINF_SUCCESS is returned).
7786 * @param u64VmcsField The VMCS field.
7787 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7788 * NULL.
7789 */
7790IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7791 PCVMXVEXITINFO pExitInfo)
7792{
7793 /* Nested-guest intercept. */
7794 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7795 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7796 {
7797 if (pExitInfo)
7798 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7799 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7800 }
7801
7802 /* CPL. */
7803 if (pVCpu->iem.s.uCpl == 0)
7804 { /* likely */ }
7805 else
7806 {
7807 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7808 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7809 return iemRaiseGeneralProtectionFault0(pVCpu);
7810 }
7811
7812 /* VMCS pointer in root mode. */
7813 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7814 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7815 { /* likely */ }
7816 else
7817 {
7818 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7819 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7820 iemVmxVmFailInvalid(pVCpu);
7821 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7822 return VINF_SUCCESS;
7823 }
7824
7825 /* VMCS-link pointer in non-root mode. */
7826 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7827 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7828 { /* likely */ }
7829 else
7830 {
7831 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7832 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7833 iemVmxVmFailInvalid(pVCpu);
7834 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7835 return VINF_SUCCESS;
7836 }
7837
7838 /* Supported VMCS field. */
7839 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
7840 { /* likely */ }
7841 else
7842 {
7843 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7845 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7846 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7847 return VINF_SUCCESS;
7848 }
7849
7850 /*
7851 * Setup reading from the current or shadow VMCS.
7852 */
7853 uint8_t *pbVmcs;
7854 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7855 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7856 else
7857 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7858 Assert(pbVmcs);
7859
7860 VMXVMCSFIELD VmcsField;
7861 VmcsField.u = u64VmcsField;
7862 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
7863 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
7864 uint8_t const uWidthType = (uWidth << 2) | uType;
7865 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
7866 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7867 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7868 Assert(offField < VMX_V_VMCS_SIZE);
7869
7870 /*
7871 * Read the VMCS component based on the field's effective width.
7872 *
7873 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7874 * indicates high bits (little endian).
7875 *
7876 * Note! The caller is responsible to trim the result and update registers
7877 * or memory locations are required. Here we just zero-extend to the largest
7878 * type (i.e. 64-bits).
7879 */
7880 uint8_t *pbField = pbVmcs + offField;
7881 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7882 switch (uEffWidth)
7883 {
7884 case VMX_VMCS_ENC_WIDTH_64BIT:
7885 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7886 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7887 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7888 }
7889 return VINF_SUCCESS;
7890}
7891
7892
7893/**
7894 * VMREAD (64-bit register) instruction execution worker.
7895 *
7896 * @returns Strict VBox status code.
7897 * @param pVCpu The cross context virtual CPU structure.
7898 * @param cbInstr The instruction length in bytes.
7899 * @param pu64Dst Where to store the VMCS field's value.
7900 * @param u64VmcsField The VMCS field.
7901 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7902 * NULL.
7903 */
7904IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7905 PCVMXVEXITINFO pExitInfo)
7906{
7907 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7908 if (rcStrict == VINF_SUCCESS)
7909 {
7910 iemVmxVmreadSuccess(pVCpu, cbInstr);
7911 return VINF_SUCCESS;
7912 }
7913
7914 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7915 return rcStrict;
7916}
7917
7918
7919/**
7920 * VMREAD (32-bit register) instruction execution worker.
7921 *
7922 * @returns Strict VBox status code.
7923 * @param pVCpu The cross context virtual CPU structure.
7924 * @param cbInstr The instruction length in bytes.
7925 * @param pu32Dst Where to store the VMCS field's value.
7926 * @param u32VmcsField The VMCS field.
7927 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7928 * NULL.
7929 */
7930IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7931 PCVMXVEXITINFO pExitInfo)
7932{
7933 uint64_t u64Dst;
7934 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7935 if (rcStrict == VINF_SUCCESS)
7936 {
7937 *pu32Dst = u64Dst;
7938 iemVmxVmreadSuccess(pVCpu, cbInstr);
7939 return VINF_SUCCESS;
7940 }
7941
7942 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7943 return rcStrict;
7944}
7945
7946
7947/**
7948 * VMREAD (memory) instruction execution worker.
7949 *
7950 * @returns Strict VBox status code.
7951 * @param pVCpu The cross context virtual CPU structure.
7952 * @param cbInstr The instruction length in bytes.
7953 * @param iEffSeg The effective segment register to use with @a u64Val.
7954 * Pass UINT8_MAX if it is a register access.
7955 * @param GCPtrDst The guest linear address to store the VMCS field's
7956 * value.
7957 * @param u64VmcsField The VMCS field.
7958 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7959 * NULL.
7960 */
7961IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7962 PCVMXVEXITINFO pExitInfo)
7963{
7964 uint64_t u64Dst;
7965 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7966 if (rcStrict == VINF_SUCCESS)
7967 {
7968 /*
7969 * Write the VMCS field's value to the location specified in guest-memory.
7970 */
7971 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7972 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7973 else
7974 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7975 if (rcStrict == VINF_SUCCESS)
7976 {
7977 iemVmxVmreadSuccess(pVCpu, cbInstr);
7978 return VINF_SUCCESS;
7979 }
7980
7981 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7982 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7983 return rcStrict;
7984 }
7985
7986 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7987 return rcStrict;
7988}
7989
7990
7991/**
7992 * VMWRITE instruction execution worker.
7993 *
7994 * @returns Strict VBox status code.
7995 * @param pVCpu The cross context virtual CPU structure.
7996 * @param cbInstr The instruction length in bytes.
7997 * @param iEffSeg The effective segment register to use with @a u64Val.
7998 * Pass UINT8_MAX if it is a register access.
7999 * @param u64Val The value to write (or guest linear address to the
8000 * value), @a iEffSeg will indicate if it's a memory
8001 * operand.
8002 * @param u64VmcsField The VMCS field.
8003 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8004 * NULL.
8005 */
8006IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
8007 PCVMXVEXITINFO pExitInfo)
8008{
8009 /* Nested-guest intercept. */
8010 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8011 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8012 {
8013 if (pExitInfo)
8014 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8015 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8016 }
8017
8018 /* CPL. */
8019 if (pVCpu->iem.s.uCpl == 0)
8020 { /* likely */ }
8021 else
8022 {
8023 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8024 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8025 return iemRaiseGeneralProtectionFault0(pVCpu);
8026 }
8027
8028 /* VMCS pointer in root mode. */
8029 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8030 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8031 { /* likely */ }
8032 else
8033 {
8034 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8035 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8036 iemVmxVmFailInvalid(pVCpu);
8037 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8038 return VINF_SUCCESS;
8039 }
8040
8041 /* VMCS-link pointer in non-root mode. */
8042 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8043 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8044 { /* likely */ }
8045 else
8046 {
8047 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8048 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8049 iemVmxVmFailInvalid(pVCpu);
8050 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8051 return VINF_SUCCESS;
8052 }
8053
8054 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8055 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8056 if (!fIsRegOperand)
8057 {
8058 /* Read the value from the specified guest memory location. */
8059 VBOXSTRICTRC rcStrict;
8060 RTGCPTR const GCPtrVal = u64Val;
8061 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8062 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8063 else
8064 {
8065 uint32_t u32Val;
8066 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8067 u64Val = u32Val;
8068 }
8069 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8070 {
8071 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8072 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8073 return rcStrict;
8074 }
8075 }
8076 else
8077 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8078
8079 /* Supported VMCS field. */
8080 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
8081 { /* likely */ }
8082 else
8083 {
8084 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8085 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8086 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8088 return VINF_SUCCESS;
8089 }
8090
8091 /* Read-only VMCS field. */
8092 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
8093 if ( !fIsFieldReadOnly
8094 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8095 { /* likely */ }
8096 else
8097 {
8098 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8099 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8100 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8101 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8102 return VINF_SUCCESS;
8103 }
8104
8105 /*
8106 * Setup writing to the current or shadow VMCS.
8107 */
8108 uint8_t *pbVmcs;
8109 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8110 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8111 else
8112 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8113 Assert(pbVmcs);
8114
8115 VMXVMCSFIELD VmcsField;
8116 VmcsField.u = u64VmcsField;
8117 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
8118 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
8119 uint8_t const uWidthType = (uWidth << 2) | uType;
8120 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
8121 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8122 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8123 Assert(offField < VMX_V_VMCS_SIZE);
8124
8125 /*
8126 * Write the VMCS component based on the field's effective width.
8127 *
8128 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8129 * indicates high bits (little endian).
8130 */
8131 uint8_t *pbField = pbVmcs + offField;
8132 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
8133 switch (uEffWidth)
8134 {
8135 case VMX_VMCS_ENC_WIDTH_64BIT:
8136 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8137 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8138 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8139 }
8140
8141 iemVmxVmSucceed(pVCpu);
8142 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8143 return VINF_SUCCESS;
8144}
8145
8146
8147/**
8148 * VMCLEAR instruction execution worker.
8149 *
8150 * @returns Strict VBox status code.
8151 * @param pVCpu The cross context virtual CPU structure.
8152 * @param cbInstr The instruction length in bytes.
8153 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8154 * @param GCPtrVmcs The linear address of the VMCS pointer.
8155 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8156 * NULL.
8157 *
8158 * @remarks Common VMX instruction checks are already expected to by the caller,
8159 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8160 */
8161IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8162 PCVMXVEXITINFO pExitInfo)
8163{
8164 /* Nested-guest intercept. */
8165 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8166 {
8167 if (pExitInfo)
8168 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8169 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8170 }
8171
8172 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8173
8174 /* CPL. */
8175 if (pVCpu->iem.s.uCpl == 0)
8176 { /* likely */ }
8177 else
8178 {
8179 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8180 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8181 return iemRaiseGeneralProtectionFault0(pVCpu);
8182 }
8183
8184 /* Get the VMCS pointer from the location specified by the source memory operand. */
8185 RTGCPHYS GCPhysVmcs;
8186 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8187 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8188 { /* likely */ }
8189 else
8190 {
8191 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8192 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8193 return rcStrict;
8194 }
8195
8196 /* VMCS pointer alignment. */
8197 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8198 { /* likely */ }
8199 else
8200 {
8201 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8202 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8203 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8204 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8205 return VINF_SUCCESS;
8206 }
8207
8208 /* VMCS physical-address width limits. */
8209 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8210 { /* likely */ }
8211 else
8212 {
8213 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8214 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8215 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8216 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8217 return VINF_SUCCESS;
8218 }
8219
8220 /* VMCS is not the VMXON region. */
8221 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8222 { /* likely */ }
8223 else
8224 {
8225 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8226 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8227 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8228 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8229 return VINF_SUCCESS;
8230 }
8231
8232 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8233 restriction imposed by our implementation. */
8234 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8235 { /* likely */ }
8236 else
8237 {
8238 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8239 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8240 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8241 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8242 return VINF_SUCCESS;
8243 }
8244
8245 /*
8246 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8247 *
8248 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8249 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8250 * to 'clear'.
8251 */
8252 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8253 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8254 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8255 {
8256 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8257 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8258 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8259 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8260 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8261 }
8262 else
8263 {
8264 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8265 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8266 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8267 if (RT_FAILURE(rcStrict))
8268 return rcStrict;
8269 }
8270
8271 iemVmxVmSucceed(pVCpu);
8272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8273 return VINF_SUCCESS;
8274}
8275
8276
8277/**
8278 * VMPTRST instruction execution worker.
8279 *
8280 * @returns Strict VBox status code.
8281 * @param pVCpu The cross context virtual CPU structure.
8282 * @param cbInstr The instruction length in bytes.
8283 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8284 * @param GCPtrVmcs The linear address of where to store the current VMCS
8285 * pointer.
8286 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8287 * NULL.
8288 *
8289 * @remarks Common VMX instruction checks are already expected to by the caller,
8290 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8291 */
8292IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8293 PCVMXVEXITINFO pExitInfo)
8294{
8295 /* Nested-guest intercept. */
8296 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8297 {
8298 if (pExitInfo)
8299 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8300 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8301 }
8302
8303 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8304
8305 /* CPL. */
8306 if (pVCpu->iem.s.uCpl == 0)
8307 { /* likely */ }
8308 else
8309 {
8310 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8311 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8312 return iemRaiseGeneralProtectionFault0(pVCpu);
8313 }
8314
8315 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8316 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8317 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8318 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8319 {
8320 iemVmxVmSucceed(pVCpu);
8321 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8322 return rcStrict;
8323 }
8324
8325 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8326 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8327 return rcStrict;
8328}
8329
8330
8331/**
8332 * VMPTRLD instruction execution worker.
8333 *
8334 * @returns Strict VBox status code.
8335 * @param pVCpu The cross context virtual CPU structure.
8336 * @param cbInstr The instruction length in bytes.
8337 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8338 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8339 * NULL.
8340 *
8341 * @remarks Common VMX instruction checks are already expected to by the caller,
8342 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8343 */
8344IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8345 PCVMXVEXITINFO pExitInfo)
8346{
8347 /* Nested-guest intercept. */
8348 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8349 {
8350 if (pExitInfo)
8351 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8352 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8353 }
8354
8355 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8356
8357 /* CPL. */
8358 if (pVCpu->iem.s.uCpl == 0)
8359 { /* likely */ }
8360 else
8361 {
8362 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8363 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8364 return iemRaiseGeneralProtectionFault0(pVCpu);
8365 }
8366
8367 /* Get the VMCS pointer from the location specified by the source memory operand. */
8368 RTGCPHYS GCPhysVmcs;
8369 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8370 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8371 { /* likely */ }
8372 else
8373 {
8374 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8375 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8376 return rcStrict;
8377 }
8378
8379 /* VMCS pointer alignment. */
8380 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8381 { /* likely */ }
8382 else
8383 {
8384 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8385 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8386 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8387 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8388 return VINF_SUCCESS;
8389 }
8390
8391 /* VMCS physical-address width limits. */
8392 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8393 { /* likely */ }
8394 else
8395 {
8396 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8397 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8398 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8399 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8400 return VINF_SUCCESS;
8401 }
8402
8403 /* VMCS is not the VMXON region. */
8404 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8405 { /* likely */ }
8406 else
8407 {
8408 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8409 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8410 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8411 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8412 return VINF_SUCCESS;
8413 }
8414
8415 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8416 restriction imposed by our implementation. */
8417 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8418 { /* likely */ }
8419 else
8420 {
8421 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8422 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8423 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8424 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8425 return VINF_SUCCESS;
8426 }
8427
8428 /* Read just the VMCS revision from the VMCS. */
8429 VMXVMCSREVID VmcsRevId;
8430 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8431 if (RT_SUCCESS(rc))
8432 { /* likely */ }
8433 else
8434 {
8435 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8436 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8437 return rc;
8438 }
8439
8440 /*
8441 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8442 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8443 */
8444 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8445 && ( !VmcsRevId.n.fIsShadowVmcs
8446 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8447 { /* likely */ }
8448 else
8449 {
8450 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8451 {
8452 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8453 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8454 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8455 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8456 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8457 return VINF_SUCCESS;
8458 }
8459
8460 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8461 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8462 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8463 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8464 return VINF_SUCCESS;
8465 }
8466
8467 /*
8468 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8469 * the cache of an existing, current VMCS back to guest memory before loading a new,
8470 * different current VMCS.
8471 */
8472 bool fLoadVmcsFromMem;
8473 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8474 {
8475 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8476 {
8477 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8478 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8479 fLoadVmcsFromMem = true;
8480 }
8481 else
8482 fLoadVmcsFromMem = false;
8483 }
8484 else
8485 fLoadVmcsFromMem = true;
8486
8487 if (fLoadVmcsFromMem)
8488 {
8489 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8490 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8491 sizeof(VMXVVMCS));
8492 if (RT_SUCCESS(rc))
8493 { /* likely */ }
8494 else
8495 {
8496 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8497 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8498 return rc;
8499 }
8500 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8501 }
8502
8503 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8504 iemVmxVmSucceed(pVCpu);
8505 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8506 return VINF_SUCCESS;
8507}
8508
8509
8510/**
8511 * INVVPID instruction execution worker.
8512 *
8513 * @returns Strict VBox status code.
8514 * @param pVCpu The cross context virtual CPU structure.
8515 * @param cbInstr The instruction length in bytes.
8516 * @param iEffSeg The segment of the invvpid descriptor.
8517 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8518 * @param u64InvvpidType The invalidation type.
8519 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8520 * NULL.
8521 *
8522 * @remarks Common VMX instruction checks are already expected to by the caller,
8523 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8524 */
8525IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8526 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8527{
8528 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8529 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8530 return iemRaiseUndefinedOpcode(pVCpu);
8531
8532 /* Nested-guest intercept. */
8533 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8534 {
8535 if (pExitInfo)
8536 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8537 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8538 }
8539
8540 /* CPL. */
8541 if (pVCpu->iem.s.uCpl != 0)
8542 {
8543 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8544 return iemRaiseGeneralProtectionFault0(pVCpu);
8545 }
8546
8547 /*
8548 * Validate INVVPID invalidation type.
8549 *
8550 * The instruction specifies exactly ONE of the supported invalidation types.
8551 *
8552 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8553 * supported. In theory, it's possible for a CPU to not support flushing individual
8554 * addresses but all the other types or any other combination. We do not take any
8555 * shortcuts here by assuming the types we currently expose to the guest.
8556 */
8557 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8558 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8559 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8560 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8561 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8562 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8563 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8564 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8565 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8566 { /* likely */ }
8567 else
8568 {
8569 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8570 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8571 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8572 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8573 return VINF_SUCCESS;
8574 }
8575
8576 /*
8577 * Fetch the invvpid descriptor from guest memory.
8578 */
8579 RTUINT128U uDesc;
8580 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8581 if (rcStrict == VINF_SUCCESS)
8582 {
8583 /*
8584 * Validate the descriptor.
8585 */
8586 if (uDesc.s.Lo > 0xfff)
8587 {
8588 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8589 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8590 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8591 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8592 return VINF_SUCCESS;
8593 }
8594
8595 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8596 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8597 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8598 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8599 switch (u64InvvpidType)
8600 {
8601 case VMXTLBFLUSHVPID_INDIV_ADDR:
8602 {
8603 if (uVpid != 0)
8604 {
8605 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8606 {
8607 /* Invalidate mappings for the linear address tagged with VPID. */
8608 /** @todo PGM support for VPID? Currently just flush everything. */
8609 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8610 iemVmxVmSucceed(pVCpu);
8611 }
8612 else
8613 {
8614 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8616 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8617 }
8618 }
8619 else
8620 {
8621 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8622 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8623 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8624 }
8625 break;
8626 }
8627
8628 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8629 {
8630 if (uVpid != 0)
8631 {
8632 /* Invalidate all mappings with VPID. */
8633 /** @todo PGM support for VPID? Currently just flush everything. */
8634 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8635 iemVmxVmSucceed(pVCpu);
8636 }
8637 else
8638 {
8639 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8640 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8641 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8642 }
8643 break;
8644 }
8645
8646 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8647 {
8648 /* Invalidate all mappings with non-zero VPIDs. */
8649 /** @todo PGM support for VPID? Currently just flush everything. */
8650 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8651 iemVmxVmSucceed(pVCpu);
8652 break;
8653 }
8654
8655 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8656 {
8657 if (uVpid != 0)
8658 {
8659 /* Invalidate all mappings with VPID except global translations. */
8660 /** @todo PGM support for VPID? Currently just flush everything. */
8661 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8662 iemVmxVmSucceed(pVCpu);
8663 }
8664 else
8665 {
8666 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8667 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8668 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8669 }
8670 break;
8671 }
8672 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8673 }
8674 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8675 }
8676 return rcStrict;
8677}
8678
8679
8680/**
8681 * VMXON instruction execution worker.
8682 *
8683 * @returns Strict VBox status code.
8684 * @param pVCpu The cross context virtual CPU structure.
8685 * @param cbInstr The instruction length in bytes.
8686 * @param iEffSeg The effective segment register to use with @a
8687 * GCPtrVmxon.
8688 * @param GCPtrVmxon The linear address of the VMXON pointer.
8689 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8690 * NULL.
8691 *
8692 * @remarks Common VMX instruction checks are already expected to by the caller,
8693 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8694 */
8695IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8696 PCVMXVEXITINFO pExitInfo)
8697{
8698 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8699 {
8700 /* CPL. */
8701 if (pVCpu->iem.s.uCpl == 0)
8702 { /* likely */ }
8703 else
8704 {
8705 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8706 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8707 return iemRaiseGeneralProtectionFault0(pVCpu);
8708 }
8709
8710 /* A20M (A20 Masked) mode. */
8711 if (PGMPhysIsA20Enabled(pVCpu))
8712 { /* likely */ }
8713 else
8714 {
8715 Log(("vmxon: A20M mode -> #GP(0)\n"));
8716 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8717 return iemRaiseGeneralProtectionFault0(pVCpu);
8718 }
8719
8720 /* CR0. */
8721 {
8722 /* CR0 MB1 bits. */
8723 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8724 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8725 { /* likely */ }
8726 else
8727 {
8728 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8729 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8730 return iemRaiseGeneralProtectionFault0(pVCpu);
8731 }
8732
8733 /* CR0 MBZ bits. */
8734 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8735 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8736 { /* likely */ }
8737 else
8738 {
8739 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8740 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8741 return iemRaiseGeneralProtectionFault0(pVCpu);
8742 }
8743 }
8744
8745 /* CR4. */
8746 {
8747 /* CR4 MB1 bits. */
8748 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8749 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8750 { /* likely */ }
8751 else
8752 {
8753 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8755 return iemRaiseGeneralProtectionFault0(pVCpu);
8756 }
8757
8758 /* CR4 MBZ bits. */
8759 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8760 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8761 { /* likely */ }
8762 else
8763 {
8764 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8766 return iemRaiseGeneralProtectionFault0(pVCpu);
8767 }
8768 }
8769
8770 /* Feature control MSR's LOCK and VMXON bits. */
8771 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8772 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8773 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8774 { /* likely */ }
8775 else
8776 {
8777 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8778 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8779 return iemRaiseGeneralProtectionFault0(pVCpu);
8780 }
8781
8782 /* Get the VMXON pointer from the location specified by the source memory operand. */
8783 RTGCPHYS GCPhysVmxon;
8784 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8785 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8786 { /* likely */ }
8787 else
8788 {
8789 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8790 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8791 return rcStrict;
8792 }
8793
8794 /* VMXON region pointer alignment. */
8795 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8796 { /* likely */ }
8797 else
8798 {
8799 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8801 iemVmxVmFailInvalid(pVCpu);
8802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8803 return VINF_SUCCESS;
8804 }
8805
8806 /* VMXON physical-address width limits. */
8807 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8808 { /* likely */ }
8809 else
8810 {
8811 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8813 iemVmxVmFailInvalid(pVCpu);
8814 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8815 return VINF_SUCCESS;
8816 }
8817
8818 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8819 restriction imposed by our implementation. */
8820 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8821 { /* likely */ }
8822 else
8823 {
8824 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8825 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8826 iemVmxVmFailInvalid(pVCpu);
8827 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8828 return VINF_SUCCESS;
8829 }
8830
8831 /* Read the VMCS revision ID from the VMXON region. */
8832 VMXVMCSREVID VmcsRevId;
8833 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8834 if (RT_SUCCESS(rc))
8835 { /* likely */ }
8836 else
8837 {
8838 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8839 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8840 return rc;
8841 }
8842
8843 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8844 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8845 { /* likely */ }
8846 else
8847 {
8848 /* Revision ID mismatch. */
8849 if (!VmcsRevId.n.fIsShadowVmcs)
8850 {
8851 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8852 VmcsRevId.n.u31RevisionId));
8853 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8854 iemVmxVmFailInvalid(pVCpu);
8855 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8856 return VINF_SUCCESS;
8857 }
8858
8859 /* Shadow VMCS disallowed. */
8860 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8862 iemVmxVmFailInvalid(pVCpu);
8863 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8864 return VINF_SUCCESS;
8865 }
8866
8867 /*
8868 * Record that we're in VMX operation, block INIT, block and disable A20M.
8869 */
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8871 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8872 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8873
8874 /* Clear address-range monitoring. */
8875 EMMonitorWaitClear(pVCpu);
8876 /** @todo NSTVMX: Intel PT. */
8877
8878 iemVmxVmSucceed(pVCpu);
8879 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8880 return VINF_SUCCESS;
8881 }
8882 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8883 {
8884 /* Nested-guest intercept. */
8885 if (pExitInfo)
8886 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8887 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8888 }
8889
8890 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8891
8892 /* CPL. */
8893 if (pVCpu->iem.s.uCpl > 0)
8894 {
8895 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8896 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8897 return iemRaiseGeneralProtectionFault0(pVCpu);
8898 }
8899
8900 /* VMXON when already in VMX root mode. */
8901 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8902 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8903 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8904 return VINF_SUCCESS;
8905}
8906
8907
8908/**
8909 * Implements 'VMXOFF'.
8910 *
8911 * @remarks Common VMX instruction checks are already expected to by the caller,
8912 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8913 */
8914IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8915{
8916 /* Nested-guest intercept. */
8917 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8918 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8919
8920 /* CPL. */
8921 if (pVCpu->iem.s.uCpl == 0)
8922 { /* likely */ }
8923 else
8924 {
8925 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8926 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8927 return iemRaiseGeneralProtectionFault0(pVCpu);
8928 }
8929
8930 /* Dual monitor treatment of SMIs and SMM. */
8931 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8932 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8933 { /* likely */ }
8934 else
8935 {
8936 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8937 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8938 return VINF_SUCCESS;
8939 }
8940
8941 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8942 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8943 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8944
8945 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8946 { /** @todo NSTVMX: Unblock SMI. */ }
8947
8948 EMMonitorWaitClear(pVCpu);
8949 /** @todo NSTVMX: Unblock and enable A20M. */
8950
8951 iemVmxVmSucceed(pVCpu);
8952 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8953 return VINF_SUCCESS;
8954}
8955
8956
8957/**
8958 * Implements 'VMXON'.
8959 */
8960IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8961{
8962 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8963}
8964
8965
8966/**
8967 * Implements 'VMLAUNCH'.
8968 */
8969IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8970{
8971 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8972}
8973
8974
8975/**
8976 * Implements 'VMRESUME'.
8977 */
8978IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8979{
8980 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8981}
8982
8983
8984/**
8985 * Implements 'VMPTRLD'.
8986 */
8987IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8988{
8989 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8990}
8991
8992
8993/**
8994 * Implements 'VMPTRST'.
8995 */
8996IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8997{
8998 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8999}
9000
9001
9002/**
9003 * Implements 'VMCLEAR'.
9004 */
9005IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9006{
9007 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9008}
9009
9010
9011/**
9012 * Implements 'VMWRITE' register.
9013 */
9014IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9015{
9016 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9017}
9018
9019
9020/**
9021 * Implements 'VMWRITE' memory.
9022 */
9023IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9024{
9025 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9026}
9027
9028
9029/**
9030 * Implements 'VMREAD' register (64-bit).
9031 */
9032IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9033{
9034 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9035}
9036
9037
9038/**
9039 * Implements 'VMREAD' register (32-bit).
9040 */
9041IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9042{
9043 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9044}
9045
9046
9047/**
9048 * Implements 'VMREAD' memory, 64-bit register.
9049 */
9050IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9051{
9052 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9053}
9054
9055
9056/**
9057 * Implements 'VMREAD' memory, 32-bit register.
9058 */
9059IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9060{
9061 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9062}
9063
9064
9065/**
9066 * Implements 'INVVPID'.
9067 */
9068IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9069{
9070 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9071}
9072
9073
9074/**
9075 * Implements VMX's implementation of PAUSE.
9076 */
9077IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9078{
9079 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9080 {
9081 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9082 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9083 return rcStrict;
9084 }
9085
9086 /*
9087 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9088 * a VM-exit, the instruction operates normally.
9089 */
9090 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9091 return VINF_SUCCESS;
9092}
9093
9094#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9095
9096
9097/**
9098 * Implements 'VMCALL'.
9099 */
9100IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9101{
9102#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9103 /* Nested-guest intercept. */
9104 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9105 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9106#endif
9107
9108 /* Join forces with vmmcall. */
9109 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9110}
9111
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