VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79142

Last change on this file since 79142 was 79116, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Use IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79116 2019-06-13 05:22:14Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Returns whether the given VMCS field is valid and supported by our emulation.
445 *
446 * @param pVCpu The cross context virtual CPU structure.
447 * @param u64VmcsField The VMCS field.
448 *
449 * @remarks This takes into account the CPU features exposed to the guest.
450 */
451IEM_STATIC bool iemVmxIsVmcsFieldValid(PCVMCPU pVCpu, uint64_t u64VmcsField)
452{
453 uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
454 uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
455 if (!uFieldEncHi)
456 { /* likely */ }
457 else
458 return false;
459
460 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
461 switch (uFieldEncLo)
462 {
463 /*
464 * 16-bit fields.
465 */
466 /* Control fields. */
467 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
468 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
469 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
470
471 /* Guest-state fields. */
472 case VMX_VMCS16_GUEST_ES_SEL:
473 case VMX_VMCS16_GUEST_CS_SEL:
474 case VMX_VMCS16_GUEST_SS_SEL:
475 case VMX_VMCS16_GUEST_DS_SEL:
476 case VMX_VMCS16_GUEST_FS_SEL:
477 case VMX_VMCS16_GUEST_GS_SEL:
478 case VMX_VMCS16_GUEST_LDTR_SEL:
479 case VMX_VMCS16_GUEST_TR_SEL: return true;
480 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
481 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
482
483 /* Host-state fields. */
484 case VMX_VMCS16_HOST_ES_SEL:
485 case VMX_VMCS16_HOST_CS_SEL:
486 case VMX_VMCS16_HOST_SS_SEL:
487 case VMX_VMCS16_HOST_DS_SEL:
488 case VMX_VMCS16_HOST_FS_SEL:
489 case VMX_VMCS16_HOST_GS_SEL:
490 case VMX_VMCS16_HOST_TR_SEL: return true;
491
492 /*
493 * 64-bit fields.
494 */
495 /* Control fields. */
496 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
497 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
498 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
499 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
500 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
501 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
502 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
503 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
504 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
505 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
506 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
507 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
508 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
509 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
510 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
511 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
512 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
513 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
514 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
515 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
516 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
517 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
518 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
519 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
520 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
521 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
522 case VMX_VMCS64_CTRL_EPTP_FULL:
523 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
524 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
525 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
526 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
527 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
528 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
529 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
530 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
531 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
533 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
534 {
535 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
536 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
537 }
538 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
539 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
540 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
541 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
542 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
543 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
544 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
545 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
546 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
547 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
548 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
549 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
550
551 /* Read-only data fields. */
552 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
553 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
554
555 /* Guest-state fields. */
556 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
557 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
558 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
559 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
560 case VMX_VMCS64_GUEST_PAT_FULL:
561 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
562 case VMX_VMCS64_GUEST_EFER_FULL:
563 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
564 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
565 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
566 case VMX_VMCS64_GUEST_PDPTE0_FULL:
567 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
568 case VMX_VMCS64_GUEST_PDPTE1_FULL:
569 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
570 case VMX_VMCS64_GUEST_PDPTE2_FULL:
571 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
572 case VMX_VMCS64_GUEST_PDPTE3_FULL:
573 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
574 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
575 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
576
577 /* Host-state fields. */
578 case VMX_VMCS64_HOST_PAT_FULL:
579 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
580 case VMX_VMCS64_HOST_EFER_FULL:
581 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
582 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
584
585 /*
586 * 32-bit fields.
587 */
588 /* Control fields. */
589 case VMX_VMCS32_CTRL_PIN_EXEC:
590 case VMX_VMCS32_CTRL_PROC_EXEC:
591 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
592 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
593 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
594 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
595 case VMX_VMCS32_CTRL_EXIT:
596 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
597 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
598 case VMX_VMCS32_CTRL_ENTRY:
599 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
600 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
601 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
602 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
603 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
604 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
605 case VMX_VMCS32_CTRL_PLE_GAP:
606 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
607
608 /* Read-only data fields. */
609 case VMX_VMCS32_RO_VM_INSTR_ERROR:
610 case VMX_VMCS32_RO_EXIT_REASON:
611 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
612 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
613 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
614 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
615 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
616 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
617
618 /* Guest-state fields. */
619 case VMX_VMCS32_GUEST_ES_LIMIT:
620 case VMX_VMCS32_GUEST_CS_LIMIT:
621 case VMX_VMCS32_GUEST_SS_LIMIT:
622 case VMX_VMCS32_GUEST_DS_LIMIT:
623 case VMX_VMCS32_GUEST_FS_LIMIT:
624 case VMX_VMCS32_GUEST_GS_LIMIT:
625 case VMX_VMCS32_GUEST_LDTR_LIMIT:
626 case VMX_VMCS32_GUEST_TR_LIMIT:
627 case VMX_VMCS32_GUEST_GDTR_LIMIT:
628 case VMX_VMCS32_GUEST_IDTR_LIMIT:
629 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
630 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
631 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
632 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
633 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
634 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
635 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
636 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
637 case VMX_VMCS32_GUEST_INT_STATE:
638 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
639 case VMX_VMCS32_GUEST_SMBASE:
640 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
641 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
642
643 /* Host-state fields. */
644 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
645
646 /*
647 * Natural-width fields.
648 */
649 /* Control fields. */
650 case VMX_VMCS_CTRL_CR0_MASK:
651 case VMX_VMCS_CTRL_CR4_MASK:
652 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
653 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
654 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
655 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
656 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
657 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
658
659 /* Read-only data fields. */
660 case VMX_VMCS_RO_EXIT_QUALIFICATION:
661 case VMX_VMCS_RO_IO_RCX:
662 case VMX_VMCS_RO_IO_RSI:
663 case VMX_VMCS_RO_IO_RDI:
664 case VMX_VMCS_RO_IO_RIP:
665 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
666
667 /* Guest-state fields. */
668 case VMX_VMCS_GUEST_CR0:
669 case VMX_VMCS_GUEST_CR3:
670 case VMX_VMCS_GUEST_CR4:
671 case VMX_VMCS_GUEST_ES_BASE:
672 case VMX_VMCS_GUEST_CS_BASE:
673 case VMX_VMCS_GUEST_SS_BASE:
674 case VMX_VMCS_GUEST_DS_BASE:
675 case VMX_VMCS_GUEST_FS_BASE:
676 case VMX_VMCS_GUEST_GS_BASE:
677 case VMX_VMCS_GUEST_LDTR_BASE:
678 case VMX_VMCS_GUEST_TR_BASE:
679 case VMX_VMCS_GUEST_GDTR_BASE:
680 case VMX_VMCS_GUEST_IDTR_BASE:
681 case VMX_VMCS_GUEST_DR7:
682 case VMX_VMCS_GUEST_RSP:
683 case VMX_VMCS_GUEST_RIP:
684 case VMX_VMCS_GUEST_RFLAGS:
685 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
686 case VMX_VMCS_GUEST_SYSENTER_ESP:
687 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
688
689 /* Host-state fields. */
690 case VMX_VMCS_HOST_CR0:
691 case VMX_VMCS_HOST_CR3:
692 case VMX_VMCS_HOST_CR4:
693 case VMX_VMCS_HOST_FS_BASE:
694 case VMX_VMCS_HOST_GS_BASE:
695 case VMX_VMCS_HOST_TR_BASE:
696 case VMX_VMCS_HOST_GDTR_BASE:
697 case VMX_VMCS_HOST_IDTR_BASE:
698 case VMX_VMCS_HOST_SYSENTER_ESP:
699 case VMX_VMCS_HOST_SYSENTER_EIP:
700 case VMX_VMCS_HOST_RSP:
701 case VMX_VMCS_HOST_RIP: return true;
702 }
703
704 return false;
705}
706
707
708/**
709 * Gets a host selector from the VMCS.
710 *
711 * @param pVmcs Pointer to the virtual VMCS.
712 * @param iSelReg The index of the segment register (X86_SREG_XXX).
713 */
714DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
715{
716 Assert(iSegReg < X86_SREG_COUNT);
717 RTSEL HostSel;
718 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
719 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
720 uint8_t const uWidthType = (uWidth << 2) | uType;
721 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
722 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
723 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
724 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
725 uint8_t const *pbField = pbVmcs + offField;
726 HostSel = *(uint16_t *)pbField;
727 return HostSel;
728}
729
730
731/**
732 * Sets a guest segment register in the VMCS.
733 *
734 * @param pVmcs Pointer to the virtual VMCS.
735 * @param iSegReg The index of the segment register (X86_SREG_XXX).
736 * @param pSelReg Pointer to the segment register.
737 */
738IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
739{
740 Assert(pSelReg);
741 Assert(iSegReg < X86_SREG_COUNT);
742
743 /* Selector. */
744 {
745 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
746 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
747 uint8_t const uWidthType = (uWidth << 2) | uType;
748 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
749 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
750 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
751 uint8_t *pbVmcs = (uint8_t *)pVmcs;
752 uint8_t *pbField = pbVmcs + offField;
753 *(uint16_t *)pbField = pSelReg->Sel;
754 }
755
756 /* Limit. */
757 {
758 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
759 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
760 uint8_t const uWidthType = (uWidth << 2) | uType;
761 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
762 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
763 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
764 uint8_t *pbVmcs = (uint8_t *)pVmcs;
765 uint8_t *pbField = pbVmcs + offField;
766 *(uint32_t *)pbField = pSelReg->u32Limit;
767 }
768
769 /* Base. */
770 {
771 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
772 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
773 uint8_t const uWidthType = (uWidth << 2) | uType;
774 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
775 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
776 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
777 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
778 uint8_t const *pbField = pbVmcs + offField;
779 *(uint64_t *)pbField = pSelReg->u64Base;
780 }
781
782 /* Attributes. */
783 {
784 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
785 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
786 | X86DESCATTR_UNUSABLE;
787 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
788 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
789 uint8_t const uWidthType = (uWidth << 2) | uType;
790 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
791 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
792 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
793 uint8_t *pbVmcs = (uint8_t *)pVmcs;
794 uint8_t *pbField = pbVmcs + offField;
795 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
796 }
797}
798
799
800/**
801 * Gets a guest segment register from the VMCS.
802 *
803 * @returns VBox status code.
804 * @param pVmcs Pointer to the virtual VMCS.
805 * @param iSegReg The index of the segment register (X86_SREG_XXX).
806 * @param pSelReg Where to store the segment register (only updated when
807 * VINF_SUCCESS is returned).
808 *
809 * @remarks Warning! This does not validate the contents of the retrieved segment
810 * register.
811 */
812IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
813{
814 Assert(pSelReg);
815 Assert(iSegReg < X86_SREG_COUNT);
816
817 /* Selector. */
818 uint16_t u16Sel;
819 {
820 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
821 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
822 uint8_t const uWidthType = (uWidth << 2) | uType;
823 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
824 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
825 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
826 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
827 uint8_t const *pbField = pbVmcs + offField;
828 u16Sel = *(uint16_t *)pbField;
829 }
830
831 /* Limit. */
832 uint32_t u32Limit;
833 {
834 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
835 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
836 uint8_t const uWidthType = (uWidth << 2) | uType;
837 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
838 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
839 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
840 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
841 uint8_t const *pbField = pbVmcs + offField;
842 u32Limit = *(uint32_t *)pbField;
843 }
844
845 /* Base. */
846 uint64_t u64Base;
847 {
848 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
849 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
850 uint8_t const uWidthType = (uWidth << 2) | uType;
851 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
852 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
853 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
854 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
855 uint8_t const *pbField = pbVmcs + offField;
856 u64Base = *(uint64_t *)pbField;
857 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
858 }
859
860 /* Attributes. */
861 uint32_t u32Attr;
862 {
863 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
864 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
865 uint8_t const uWidthType = (uWidth << 2) | uType;
866 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
867 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
868 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
869 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
870 uint8_t const *pbField = pbVmcs + offField;
871 u32Attr = *(uint32_t *)pbField;
872 }
873
874 pSelReg->Sel = u16Sel;
875 pSelReg->ValidSel = u16Sel;
876 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
877 pSelReg->u32Limit = u32Limit;
878 pSelReg->u64Base = u64Base;
879 pSelReg->Attr.u = u32Attr;
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Gets a CR3 target value from the VMCS.
886 *
887 * @returns VBox status code.
888 * @param pVmcs Pointer to the virtual VMCS.
889 * @param idxCr3Target The index of the CR3-target value to retrieve.
890 * @param puValue Where to store the CR3-target value.
891 */
892IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
893{
894 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
895 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
896 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
897 uint8_t const uWidthType = (uWidth << 2) | uType;
898 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
899 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
900 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
901 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
902 uint8_t const *pbField = pbVmcs + offField;
903 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
904 return uCr3TargetValue;
905}
906
907
908/**
909 * Converts an IEM exception event type to a VMX event type.
910 *
911 * @returns The VMX event type.
912 * @param uVector The interrupt / exception vector.
913 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
914 */
915DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
916{
917 /* Paranoia (callers may use these interchangeably). */
918 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
919 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
920 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
921 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
922 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
923 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
924 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
925 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
926 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
927 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
928 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
929 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
930
931 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
932 {
933 if (uVector == X86_XCPT_NMI)
934 return VMX_EXIT_INT_INFO_TYPE_NMI;
935 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
936 }
937
938 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
939 {
940 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
941 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
942 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
943 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
944 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
945 }
946
947 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
948 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
949}
950
951
952/**
953 * Sets the Exit qualification VMCS field.
954 *
955 * @param pVCpu The cross context virtual CPU structure.
956 * @param u64ExitQual The Exit qualification.
957 */
958DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
959{
960 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
961 pVmcs->u64RoExitQual.u = u64ExitQual;
962}
963
964
965/**
966 * Sets the VM-exit interruption information field.
967 *
968 * @param pVCpu The cross context virtual CPU structure.
969 * @param uExitIntInfo The VM-exit interruption information.
970 */
971DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
972{
973 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
974 pVmcs->u32RoExitIntInfo = uExitIntInfo;
975}
976
977
978/**
979 * Sets the VM-exit interruption error code.
980 *
981 * @param pVCpu The cross context virtual CPU structure.
982 * @param uErrCode The error code.
983 */
984DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
985{
986 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
987 pVmcs->u32RoExitIntErrCode = uErrCode;
988}
989
990
991/**
992 * Sets the IDT-vectoring information field.
993 *
994 * @param pVCpu The cross context virtual CPU structure.
995 * @param uIdtVectorInfo The IDT-vectoring information.
996 */
997DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
998{
999 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1001}
1002
1003
1004/**
1005 * Sets the IDT-vectoring error code field.
1006 *
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param uErrCode The error code.
1009 */
1010DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1011{
1012 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1013 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1014}
1015
1016
1017/**
1018 * Sets the VM-exit guest-linear address VMCS field.
1019 *
1020 * @param pVCpu The cross context virtual CPU structure.
1021 * @param uGuestLinearAddr The VM-exit guest-linear address.
1022 */
1023DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1024{
1025 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1026 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1027}
1028
1029
1030/**
1031 * Sets the VM-exit guest-physical address VMCS field.
1032 *
1033 * @param pVCpu The cross context virtual CPU structure.
1034 * @param uGuestPhysAddr The VM-exit guest-physical address.
1035 */
1036DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1037{
1038 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1039 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1040}
1041
1042
1043/**
1044 * Sets the VM-exit instruction length VMCS field.
1045 *
1046 * @param pVCpu The cross context virtual CPU structure.
1047 * @param cbInstr The VM-exit instruction length in bytes.
1048 *
1049 * @remarks Callers may clear this field to 0. Hence, this function does not check
1050 * the validity of the instruction length.
1051 */
1052DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1053{
1054 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1055 pVmcs->u32RoExitInstrLen = cbInstr;
1056}
1057
1058
1059/**
1060 * Sets the VM-exit instruction info. VMCS field.
1061 *
1062 * @param pVCpu The cross context virtual CPU structure.
1063 * @param uExitInstrInfo The VM-exit instruction information.
1064 */
1065DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1066{
1067 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1068 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1069}
1070
1071
1072/**
1073 * Implements VMSucceed for VMX instruction success.
1074 *
1075 * @param pVCpu The cross context virtual CPU structure.
1076 */
1077DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1078{
1079 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
1080}
1081
1082
1083/**
1084 * Implements VMFailInvalid for VMX instruction failure.
1085 *
1086 * @param pVCpu The cross context virtual CPU structure.
1087 */
1088DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1089{
1090 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
1091}
1092
1093
1094/**
1095 * Implements VMFail for VMX instruction failure.
1096 *
1097 * @param pVCpu The cross context virtual CPU structure.
1098 * @param enmInsErr The VM instruction error.
1099 */
1100DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1101{
1102 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
1103}
1104
1105
1106/**
1107 * Checks if the given auto-load/store MSR area count is valid for the
1108 * implementation.
1109 *
1110 * @returns @c true if it's within the valid limit, @c false otherwise.
1111 * @param pVCpu The cross context virtual CPU structure.
1112 * @param uMsrCount The MSR area count to check.
1113 */
1114DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
1115{
1116 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1117 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1118 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1119 if (uMsrCount <= cMaxSupportedMsrs)
1120 return true;
1121 return false;
1122}
1123
1124
1125/**
1126 * Flushes the current VMCS contents back to guest memory.
1127 *
1128 * @returns VBox status code.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1132{
1133 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1134 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1135 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1136 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1137 return rc;
1138}
1139
1140
1141/**
1142 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1143 *
1144 * @param pVCpu The cross context virtual CPU structure.
1145 */
1146DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1147{
1148 iemVmxVmSucceed(pVCpu);
1149 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1150}
1151
1152
1153/**
1154 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1155 * nested-guest.
1156 *
1157 * @param iSegReg The segment index (X86_SREG_XXX).
1158 */
1159IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1160{
1161 switch (iSegReg)
1162 {
1163 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1164 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1165 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1166 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1167 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1168 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1169 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1170 }
1171}
1172
1173
1174/**
1175 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1176 * nested-guest that is in Virtual-8086 mode.
1177 *
1178 * @param iSegReg The segment index (X86_SREG_XXX).
1179 */
1180IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1181{
1182 switch (iSegReg)
1183 {
1184 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1185 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1186 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1187 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1188 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1189 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1190 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1191 }
1192}
1193
1194
1195/**
1196 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1197 * nested-guest that is in Virtual-8086 mode.
1198 *
1199 * @param iSegReg The segment index (X86_SREG_XXX).
1200 */
1201IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1202{
1203 switch (iSegReg)
1204 {
1205 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1206 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1207 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1208 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1209 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1210 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1211 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1212 }
1213}
1214
1215
1216/**
1217 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1218 * nested-guest that is in Virtual-8086 mode.
1219 *
1220 * @param iSegReg The segment index (X86_SREG_XXX).
1221 */
1222IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1223{
1224 switch (iSegReg)
1225 {
1226 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1227 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1228 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1229 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1230 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1231 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1232 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1233 }
1234}
1235
1236
1237/**
1238 * Gets the instruction diagnostic for segment attributes reserved bits failure
1239 * during VM-entry of a nested-guest.
1240 *
1241 * @param iSegReg The segment index (X86_SREG_XXX).
1242 */
1243IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1244{
1245 switch (iSegReg)
1246 {
1247 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1248 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1249 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1250 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1251 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1252 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1253 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1254 }
1255}
1256
1257
1258/**
1259 * Gets the instruction diagnostic for segment attributes descriptor-type
1260 * (code/segment or system) failure during VM-entry of a nested-guest.
1261 *
1262 * @param iSegReg The segment index (X86_SREG_XXX).
1263 */
1264IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1265{
1266 switch (iSegReg)
1267 {
1268 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1269 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1270 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1271 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1272 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1273 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1274 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1275 }
1276}
1277
1278
1279/**
1280 * Gets the instruction diagnostic for segment attributes descriptor-type
1281 * (code/segment or system) failure during VM-entry of a nested-guest.
1282 *
1283 * @param iSegReg The segment index (X86_SREG_XXX).
1284 */
1285IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1286{
1287 switch (iSegReg)
1288 {
1289 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1290 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1291 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1292 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1293 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1294 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1295 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1296 }
1297}
1298
1299
1300/**
1301 * Gets the instruction diagnostic for segment attribute granularity failure during
1302 * VM-entry of a nested-guest.
1303 *
1304 * @param iSegReg The segment index (X86_SREG_XXX).
1305 */
1306IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1307{
1308 switch (iSegReg)
1309 {
1310 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1311 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1312 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1313 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1314 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1315 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1316 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1317 }
1318}
1319
1320/**
1321 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1322 * VM-entry of a nested-guest.
1323 *
1324 * @param iSegReg The segment index (X86_SREG_XXX).
1325 */
1326IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1327{
1328 switch (iSegReg)
1329 {
1330 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1331 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1332 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1333 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1334 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1335 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1336 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1337 }
1338}
1339
1340
1341/**
1342 * Gets the instruction diagnostic for segment attribute type accessed failure
1343 * during VM-entry of a nested-guest.
1344 *
1345 * @param iSegReg The segment index (X86_SREG_XXX).
1346 */
1347IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1348{
1349 switch (iSegReg)
1350 {
1351 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1352 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1353 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1354 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1355 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1356 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1357 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1358 }
1359}
1360
1361
1362/**
1363 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1364 * failure during VM-entry of a nested-guest.
1365 *
1366 * @param iSegReg The PDPTE entry index.
1367 */
1368IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1369{
1370 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1371 switch (iPdpte)
1372 {
1373 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1374 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1375 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1376 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1377 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1378 }
1379}
1380
1381
1382/**
1383 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1384 * failure during VM-exit of a nested-guest.
1385 *
1386 * @param iSegReg The PDPTE entry index.
1387 */
1388IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1389{
1390 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1391 switch (iPdpte)
1392 {
1393 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1394 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1395 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1396 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1397 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1398 }
1399}
1400
1401
1402/**
1403 * Saves the guest control registers, debug registers and some MSRs are part of
1404 * VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1409{
1410 /*
1411 * Saves the guest control registers, debug registers and some MSRs.
1412 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1413 */
1414 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1415
1416 /* Save control registers. */
1417 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1418 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1419 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1420
1421 /* Save SYSENTER CS, ESP, EIP. */
1422 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1423 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1424 {
1425 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1426 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1427 }
1428 else
1429 {
1430 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1431 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1432 }
1433
1434 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1435 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1436 {
1437 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1438 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1439 }
1440
1441 /* Save PAT MSR. */
1442 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1443 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1444
1445 /* Save EFER MSR. */
1446 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1447 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1448
1449 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1450 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1451
1452 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1453}
1454
1455
1456/**
1457 * Saves the guest force-flags in preparation of entering the nested-guest.
1458 *
1459 * @param pVCpu The cross context virtual CPU structure.
1460 */
1461IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1462{
1463 /* We shouldn't be called multiple times during VM-entry. */
1464 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1465
1466 /* MTF should not be set outside VMX non-root mode. */
1467 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1468
1469 /*
1470 * Preserve the required force-flags.
1471 *
1472 * We cache and clear force-flags that would affect the execution of the
1473 * nested-guest. Cached flags are then restored while returning to the guest
1474 * if necessary.
1475 *
1476 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1477 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1478 * instruction. Interrupt inhibition for any nested-guest instruction
1479 * is supplied by the guest-interruptibility state VMCS field and will
1480 * be set up as part of loading the guest state.
1481 *
1482 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1483 * successful VM-entry (due to invalid guest-state) need to continue
1484 * blocking NMIs if it was in effect before VM-entry.
1485 *
1486 * - MTF need not be preserved as it's used only in VMX non-root mode and
1487 * is supplied through the VM-execution controls.
1488 *
1489 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1490 * we will be able to generate interrupts that may cause VM-exits for
1491 * the nested-guest.
1492 */
1493 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1494}
1495
1496
1497/**
1498 * Restores the guest force-flags in preparation of exiting the nested-guest.
1499 *
1500 * @param pVCpu The cross context virtual CPU structure.
1501 */
1502IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1503{
1504 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1505 {
1506 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1507 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1508 }
1509}
1510
1511
1512/**
1513 * Perform a VMX transition updated PGM, IEM and CPUM.
1514 *
1515 * @param pVCpu The cross context virtual CPU structure.
1516 */
1517IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1518{
1519 /*
1520 * Inform PGM about paging mode changes.
1521 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1522 * see comment in iemMemPageTranslateAndCheckAccess().
1523 */
1524 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1525# ifdef IN_RING3
1526 Assert(rc != VINF_PGM_CHANGE_MODE);
1527# endif
1528 AssertRCReturn(rc, rc);
1529
1530 /* Inform CPUM (recompiler), can later be removed. */
1531 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1532
1533 /*
1534 * Flush the TLB with new CR3. This is required in case the PGM mode change
1535 * above doesn't actually change anything.
1536 */
1537 if (rc == VINF_SUCCESS)
1538 {
1539 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1540 AssertRCReturn(rc, rc);
1541 }
1542
1543 /* Re-initialize IEM cache/state after the drastic mode switch. */
1544 iemReInitExec(pVCpu);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Calculates the current VMX-preemption timer value.
1551 *
1552 * @param pVCpu The cross context virtual CPU structure.
1553 */
1554IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1555{
1556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1557 Assert(pVmcs);
1558
1559 /*
1560 * Assume the following:
1561 * PreemptTimerShift = 5
1562 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1563 * EntryTick = 50000 (TSC at time of VM-entry)
1564 *
1565 * CurTick Delta PreemptTimerVal
1566 * ----------------------------------
1567 * 60000 10000 2
1568 * 80000 30000 1
1569 * 90000 40000 0 -> VM-exit.
1570 *
1571 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1572 * The saved VMX-preemption timer value is calculated as follows:
1573 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1574 * E.g.:
1575 * Delta = 10000
1576 * Tmp = 10000 / (2 * 10000) = 0.5
1577 * NewPt = 2 - 0.5 = 2
1578 * Delta = 30000
1579 * Tmp = 30000 / (2 * 10000) = 1.5
1580 * NewPt = 2 - 1.5 = 1
1581 * Delta = 40000
1582 * Tmp = 40000 / 20000 = 2
1583 * NewPt = 2 - 2 = 0
1584 */
1585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1586 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1587 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1588 uint64_t const uDelta = uCurTick - uEntryTick;
1589 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1590 uint32_t const uPreemptTimer = uVmcsPreemptVal
1591 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1592 return uPreemptTimer;
1593}
1594
1595
1596/**
1597 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1598 *
1599 * @param pVCpu The cross context virtual CPU structure.
1600 */
1601IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1602{
1603 /*
1604 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1605 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1606 */
1607 /* CS, SS, ES, DS, FS, GS. */
1608 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1610 {
1611 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1612 if (!pSelReg->Attr.n.u1Unusable)
1613 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1614 else
1615 {
1616 /*
1617 * For unusable segments the attributes are undefined except for CS and SS.
1618 * For the rest we don't bother preserving anything but the unusable bit.
1619 */
1620 switch (iSegReg)
1621 {
1622 case X86_SREG_CS:
1623 pVmcs->GuestCs = pSelReg->Sel;
1624 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1625 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1626 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1627 | X86DESCATTR_UNUSABLE);
1628 break;
1629
1630 case X86_SREG_SS:
1631 pVmcs->GuestSs = pSelReg->Sel;
1632 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1633 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1634 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1635 break;
1636
1637 case X86_SREG_DS:
1638 pVmcs->GuestDs = pSelReg->Sel;
1639 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1640 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1641 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1642 break;
1643
1644 case X86_SREG_ES:
1645 pVmcs->GuestEs = pSelReg->Sel;
1646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1647 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1648 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1649 break;
1650
1651 case X86_SREG_FS:
1652 pVmcs->GuestFs = pSelReg->Sel;
1653 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1654 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1655 break;
1656
1657 case X86_SREG_GS:
1658 pVmcs->GuestGs = pSelReg->Sel;
1659 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1660 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1661 break;
1662 }
1663 }
1664 }
1665
1666 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1667 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1668 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1669 | X86DESCATTR_UNUSABLE;
1670 /* LDTR. */
1671 {
1672 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1673 pVmcs->GuestLdtr = pSelReg->Sel;
1674 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1675 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1676 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1677 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1678 }
1679
1680 /* TR. */
1681 {
1682 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1683 pVmcs->GuestTr = pSelReg->Sel;
1684 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1685 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1686 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1687 }
1688
1689 /* GDTR. */
1690 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1691 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1692
1693 /* IDTR. */
1694 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1695 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1696}
1697
1698
1699/**
1700 * Saves guest non-register state as part of VM-exit.
1701 *
1702 * @param pVCpu The cross context virtual CPU structure.
1703 * @param uExitReason The VM-exit reason.
1704 */
1705IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1706{
1707 /*
1708 * Save guest non-register state.
1709 * See Intel spec. 27.3.4 "Saving Non-Register State".
1710 */
1711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1712
1713 /*
1714 * Activity state.
1715 * Most VM-exits will occur in the active state. However, if the first instruction
1716 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1717 * the VM-exit will be from the HLT activity state.
1718 *
1719 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1720 */
1721 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1722 * not? */
1723 EMSTATE const enmActivityState = EMGetState(pVCpu);
1724 switch (enmActivityState)
1725 {
1726 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1727 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1728 }
1729
1730 /*
1731 * Interruptibility-state.
1732 */
1733 /* NMI. */
1734 pVmcs->u32GuestIntrState = 0;
1735 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1736 {
1737 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1738 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1739 }
1740 else
1741 {
1742 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1743 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1744 }
1745
1746 /* Blocking-by-STI. */
1747 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1748 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1749 {
1750 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1751 * currently. */
1752 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1753 }
1754 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1755
1756 /*
1757 * Pending debug exceptions.
1758 */
1759 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1760 && uExitReason != VMX_EXIT_SMI
1761 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1762 && !HMVmxIsVmexitTrapLike(uExitReason))
1763 {
1764 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1765 * block-by-MovSS is in effect. */
1766 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1767 }
1768 else
1769 {
1770 /*
1771 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1772 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1773 *
1774 * See Intel spec. 24.4.2 "Guest Non-Register State".
1775 */
1776 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1777 * DR6. */
1778 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1779 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1780 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1781 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1782 if (fPendingDbgMask & fBpHitMask)
1783 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1784 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1785 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1786 }
1787
1788 /*
1789 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1790 *
1791 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1792 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1793 */
1794 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1795 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1796 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1797
1798 /* PDPTEs. */
1799 /* We don't support EPT yet. */
1800 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1801 pVmcs->u64GuestPdpte0.u = 0;
1802 pVmcs->u64GuestPdpte1.u = 0;
1803 pVmcs->u64GuestPdpte2.u = 0;
1804 pVmcs->u64GuestPdpte3.u = 0;
1805}
1806
1807
1808/**
1809 * Saves the guest-state as part of VM-exit.
1810 *
1811 * @returns VBox status code.
1812 * @param pVCpu The cross context virtual CPU structure.
1813 * @param uExitReason The VM-exit reason.
1814 */
1815IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1816{
1817 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1818 Assert(pVmcs);
1819
1820 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1821 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1822
1823 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1824 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1825 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1826
1827 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1828}
1829
1830
1831/**
1832 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1833 *
1834 * @returns VBox status code.
1835 * @param pVCpu The cross context virtual CPU structure.
1836 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1837 */
1838IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1839{
1840 /*
1841 * Save guest MSRs.
1842 * See Intel spec. 27.4 "Saving MSRs".
1843 */
1844 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1845 const char *const pszFailure = "VMX-abort";
1846
1847 /*
1848 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1849 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1850 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1851 */
1852 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1853 if (!cMsrs)
1854 return VINF_SUCCESS;
1855
1856 /*
1857 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1858 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1859 * implementation causes a VMX-abort followed by a triple-fault.
1860 */
1861 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1862 if (fIsMsrCountValid)
1863 { /* likely */ }
1864 else
1865 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1866
1867 /*
1868 * Optimization if the guest hypervisor is using the same guest-physical page for both
1869 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1870 */
1871 PVMXAUTOMSR pMsrArea;
1872 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1873 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1874 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1875 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1876 else
1877 {
1878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1879 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1880 if (RT_SUCCESS(rc))
1881 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1882 else
1883 {
1884 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1885 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1886 }
1887 }
1888
1889 /*
1890 * Update VM-exit MSR store area.
1891 */
1892 PVMXAUTOMSR pMsr = pMsrArea;
1893 Assert(pMsr);
1894 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1895 {
1896 if ( !pMsr->u32Reserved
1897 && pMsr->u32Msr != MSR_IA32_SMBASE
1898 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1899 {
1900 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1901 if (rcStrict == VINF_SUCCESS)
1902 continue;
1903
1904 /*
1905 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1906 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1907 * recording the MSR index in the auxiliary info. field and indicated further by our
1908 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1909 * if possible, or come up with a better, generic solution.
1910 */
1911 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1912 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1913 ? kVmxVDiag_Vmexit_MsrStoreRing3
1914 : kVmxVDiag_Vmexit_MsrStore;
1915 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1916 }
1917 else
1918 {
1919 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1921 }
1922 }
1923
1924 /*
1925 * Commit the VM-exit MSR store are to guest memory.
1926 */
1927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1928 if (RT_SUCCESS(rc))
1929 return VINF_SUCCESS;
1930
1931 NOREF(uExitReason);
1932 NOREF(pszFailure);
1933
1934 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1935 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1936}
1937
1938
1939/**
1940 * Performs a VMX abort (due to an fatal error during VM-exit).
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pVCpu The cross context virtual CPU structure.
1944 * @param enmAbort The VMX abort reason.
1945 */
1946IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1947{
1948 /*
1949 * Perform the VMX abort.
1950 * See Intel spec. 27.7 "VMX Aborts".
1951 */
1952 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1953
1954 /* We don't support SMX yet. */
1955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1956 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1957 {
1958 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1959 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1960 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1961 }
1962
1963 return VINF_EM_TRIPLE_FAULT;
1964}
1965
1966
1967/**
1968 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1969 *
1970 * @param pVCpu The cross context virtual CPU structure.
1971 */
1972IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1973{
1974 /*
1975 * Load host control registers, debug registers and MSRs.
1976 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1977 */
1978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1979 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1980
1981 /* CR0. */
1982 {
1983 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
1984 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1985 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
1986 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1987 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1988 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1989 CPUMSetGuestCR0(pVCpu, uValidCr0);
1990 }
1991
1992 /* CR4. */
1993 {
1994 /* CR4 MB1 bits are not modified. */
1995 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1996 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1997 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1998 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1999 if (fHostInLongMode)
2000 uValidCr4 |= X86_CR4_PAE;
2001 else
2002 uValidCr4 &= ~X86_CR4_PCIDE;
2003 CPUMSetGuestCR4(pVCpu, uValidCr4);
2004 }
2005
2006 /* CR3 (host value validated while checking host-state during VM-entry). */
2007 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2008
2009 /* DR7. */
2010 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2011
2012 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2013
2014 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2015 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2016 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2017 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2018
2019 /* FS, GS bases are loaded later while we load host segment registers. */
2020
2021 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2022 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2023 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2024 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2025 {
2026 if (fHostInLongMode)
2027 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2028 else
2029 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2030 }
2031
2032 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2033
2034 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2035 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2036 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2037
2038 /* We don't support IA32_BNDCFGS MSR yet. */
2039}
2040
2041
2042/**
2043 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2044 *
2045 * @param pVCpu The cross context virtual CPU structure.
2046 */
2047IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2048{
2049 /*
2050 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2051 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2052 *
2053 * Warning! Be careful to not touch fields that are reserved by VT-x,
2054 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2055 */
2056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2057 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2058
2059 /* CS, SS, ES, DS, FS, GS. */
2060 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2061 {
2062 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2063 bool const fUnusable = RT_BOOL(HostSel == 0);
2064 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2065
2066 /* Selector. */
2067 pSelReg->Sel = HostSel;
2068 pSelReg->ValidSel = HostSel;
2069 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2070
2071 /* Limit. */
2072 pSelReg->u32Limit = 0xffffffff;
2073
2074 /* Base. */
2075 pSelReg->u64Base = 0;
2076
2077 /* Attributes. */
2078 if (iSegReg == X86_SREG_CS)
2079 {
2080 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2081 pSelReg->Attr.n.u1DescType = 1;
2082 pSelReg->Attr.n.u2Dpl = 0;
2083 pSelReg->Attr.n.u1Present = 1;
2084 pSelReg->Attr.n.u1Long = fHostInLongMode;
2085 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2086 pSelReg->Attr.n.u1Granularity = 1;
2087 Assert(!pSelReg->Attr.n.u1Unusable);
2088 Assert(!fUnusable);
2089 }
2090 else
2091 {
2092 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2093 pSelReg->Attr.n.u1DescType = 1;
2094 pSelReg->Attr.n.u2Dpl = 0;
2095 pSelReg->Attr.n.u1Present = 1;
2096 pSelReg->Attr.n.u1DefBig = 1;
2097 pSelReg->Attr.n.u1Granularity = 1;
2098 pSelReg->Attr.n.u1Unusable = fUnusable;
2099 }
2100 }
2101
2102 /* FS base. */
2103 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2104 || fHostInLongMode)
2105 {
2106 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2107 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2108 }
2109
2110 /* GS base. */
2111 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2112 || fHostInLongMode)
2113 {
2114 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2115 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2116 }
2117
2118 /* TR. */
2119 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2120 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2121 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2122 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2123 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2124 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2125 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2126 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2127 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2128 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2129 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2130 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2131 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2132
2133 /* LDTR (Warning! do not touch the base and limits here). */
2134 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2135 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2136 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2137 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2138
2139 /* GDTR. */
2140 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2141 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2142 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2143
2144 /* IDTR.*/
2145 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2146 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2147 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2148}
2149
2150
2151/**
2152 * Checks host PDPTes as part of VM-exit.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param uExitReason The VM-exit reason (for logging purposes).
2156 */
2157IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2158{
2159 /*
2160 * Check host PDPTEs.
2161 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2162 */
2163 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2164 const char *const pszFailure = "VMX-abort";
2165 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2166
2167 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2168 && !fHostInLongMode)
2169 {
2170 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2171 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2172 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2173 if (RT_SUCCESS(rc))
2174 {
2175 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2176 {
2177 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2178 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2179 { /* likely */ }
2180 else
2181 {
2182 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2183 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2184 }
2185 }
2186 }
2187 else
2188 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2189 }
2190
2191 NOREF(pszFailure);
2192 NOREF(uExitReason);
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
2199 *
2200 * @returns VBox status code.
2201 * @param pVCpu The cross context virtual CPU structure.
2202 * @param pszInstr The VMX instruction name (for logging purposes).
2203 */
2204IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2205{
2206 /*
2207 * Load host MSRs.
2208 * See Intel spec. 27.6 "Loading MSRs".
2209 */
2210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2211 const char *const pszFailure = "VMX-abort";
2212
2213 /*
2214 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2215 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2216 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2217 */
2218 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2219 if (!cMsrs)
2220 return VINF_SUCCESS;
2221
2222 /*
2223 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2224 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2225 * implementation causes a VMX-abort followed by a triple-fault.
2226 */
2227 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2228 if (fIsMsrCountValid)
2229 { /* likely */ }
2230 else
2231 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2232
2233 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
2234 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
2235 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
2236 if (RT_SUCCESS(rc))
2237 {
2238 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
2239 Assert(pMsr);
2240 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2241 {
2242 if ( !pMsr->u32Reserved
2243 && pMsr->u32Msr != MSR_K8_FS_BASE
2244 && pMsr->u32Msr != MSR_K8_GS_BASE
2245 && pMsr->u32Msr != MSR_K6_EFER
2246 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2247 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2248 {
2249 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2250 if (rcStrict == VINF_SUCCESS)
2251 continue;
2252
2253 /*
2254 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2255 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2256 * recording the MSR index in the auxiliary info. field and indicated further by our
2257 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2258 * if possible, or come up with a better, generic solution.
2259 */
2260 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2261 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2262 ? kVmxVDiag_Vmexit_MsrLoadRing3
2263 : kVmxVDiag_Vmexit_MsrLoad;
2264 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2265 }
2266 else
2267 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2268 }
2269 }
2270 else
2271 {
2272 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2273 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2274 }
2275
2276 NOREF(uExitReason);
2277 NOREF(pszFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Loads the host state as part of VM-exit.
2284 *
2285 * @returns Strict VBox status code.
2286 * @param pVCpu The cross context virtual CPU structure.
2287 * @param uExitReason The VM-exit reason (for logging purposes).
2288 */
2289IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2290{
2291 /*
2292 * Load host state.
2293 * See Intel spec. 27.5 "Loading Host State".
2294 */
2295 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2296 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2297
2298 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2299 if ( CPUMIsGuestInLongMode(pVCpu)
2300 && !fHostInLongMode)
2301 {
2302 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2303 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2304 }
2305
2306 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2307 iemVmxVmexitLoadHostSegRegs(pVCpu);
2308
2309 /*
2310 * Load host RIP, RSP and RFLAGS.
2311 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2312 */
2313 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2314 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2315 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2316
2317 /* Clear address range monitoring. */
2318 EMMonitorWaitClear(pVCpu);
2319
2320 /* Perform the VMX transition (PGM updates). */
2321 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2322 if (rcStrict == VINF_SUCCESS)
2323 {
2324 /* Check host PDPTEs (only when we've fully switched page tables_. */
2325 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2326 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2327 if (RT_FAILURE(rc))
2328 {
2329 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2330 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2331 }
2332 }
2333 else if (RT_SUCCESS(rcStrict))
2334 {
2335 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2336 uExitReason));
2337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2338 }
2339 else
2340 {
2341 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2342 return VBOXSTRICTRC_VAL(rcStrict);
2343 }
2344
2345 Assert(rcStrict == VINF_SUCCESS);
2346
2347 /* Load MSRs from the VM-exit auto-load MSR area. */
2348 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2349 if (RT_FAILURE(rc))
2350 {
2351 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2352 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2353 }
2354 return VINF_SUCCESS;
2355}
2356
2357
2358/**
2359 * Gets VM-exit instruction information along with any displacement for an
2360 * instruction VM-exit.
2361 *
2362 * @returns The VM-exit instruction information.
2363 * @param pVCpu The cross context virtual CPU structure.
2364 * @param uExitReason The VM-exit reason.
2365 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2366 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2367 * NULL.
2368 */
2369IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2370{
2371 RTGCPTR GCPtrDisp;
2372 VMXEXITINSTRINFO ExitInstrInfo;
2373 ExitInstrInfo.u = 0;
2374
2375 /*
2376 * Get and parse the ModR/M byte from our decoded opcodes.
2377 */
2378 uint8_t bRm;
2379 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2380 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2381 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2382 {
2383 /*
2384 * ModR/M indicates register addressing.
2385 *
2386 * The primary/secondary register operands are reported in the iReg1 or iReg2
2387 * fields depending on whether it is a read/write form.
2388 */
2389 uint8_t idxReg1;
2390 uint8_t idxReg2;
2391 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2392 {
2393 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2394 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2395 }
2396 else
2397 {
2398 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2399 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2400 }
2401 ExitInstrInfo.All.u2Scaling = 0;
2402 ExitInstrInfo.All.iReg1 = idxReg1;
2403 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2404 ExitInstrInfo.All.fIsRegOperand = 1;
2405 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2406 ExitInstrInfo.All.iSegReg = 0;
2407 ExitInstrInfo.All.iIdxReg = 0;
2408 ExitInstrInfo.All.fIdxRegInvalid = 1;
2409 ExitInstrInfo.All.iBaseReg = 0;
2410 ExitInstrInfo.All.fBaseRegInvalid = 1;
2411 ExitInstrInfo.All.iReg2 = idxReg2;
2412
2413 /* Displacement not applicable for register addressing. */
2414 GCPtrDisp = 0;
2415 }
2416 else
2417 {
2418 /*
2419 * ModR/M indicates memory addressing.
2420 */
2421 uint8_t uScale = 0;
2422 bool fBaseRegValid = false;
2423 bool fIdxRegValid = false;
2424 uint8_t iBaseReg = 0;
2425 uint8_t iIdxReg = 0;
2426 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2427 {
2428 /*
2429 * Parse the ModR/M, displacement for 16-bit addressing mode.
2430 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2431 */
2432 uint16_t u16Disp = 0;
2433 uint8_t const offDisp = offModRm + sizeof(bRm);
2434 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2435 {
2436 /* Displacement without any registers. */
2437 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2438 }
2439 else
2440 {
2441 /* Register (index and base). */
2442 switch (bRm & X86_MODRM_RM_MASK)
2443 {
2444 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2445 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2446 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2447 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2448 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2449 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2450 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2451 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2452 }
2453
2454 /* Register + displacement. */
2455 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2456 {
2457 case 0: break;
2458 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2459 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2460 default:
2461 {
2462 /* Register addressing, handled at the beginning. */
2463 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2464 break;
2465 }
2466 }
2467 }
2468
2469 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2470 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2471 }
2472 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2473 {
2474 /*
2475 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2476 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2477 */
2478 uint32_t u32Disp = 0;
2479 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2480 {
2481 /* Displacement without any registers. */
2482 uint8_t const offDisp = offModRm + sizeof(bRm);
2483 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2484 }
2485 else
2486 {
2487 /* Register (and perhaps scale, index and base). */
2488 uint8_t offDisp = offModRm + sizeof(bRm);
2489 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2490 if (iBaseReg == 4)
2491 {
2492 /* An SIB byte follows the ModR/M byte, parse it. */
2493 uint8_t bSib;
2494 uint8_t const offSib = offModRm + sizeof(bRm);
2495 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2496
2497 /* A displacement may follow SIB, update its offset. */
2498 offDisp += sizeof(bSib);
2499
2500 /* Get the scale. */
2501 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2502
2503 /* Get the index register. */
2504 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2505 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2506
2507 /* Get the base register. */
2508 iBaseReg = bSib & X86_SIB_BASE_MASK;
2509 fBaseRegValid = true;
2510 if (iBaseReg == 5)
2511 {
2512 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2513 {
2514 /* Mod is 0 implies a 32-bit displacement with no base. */
2515 fBaseRegValid = false;
2516 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2517 }
2518 else
2519 {
2520 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2521 iBaseReg = X86_GREG_xBP;
2522 }
2523 }
2524 }
2525
2526 /* Register + displacement. */
2527 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2528 {
2529 case 0: /* Handled above */ break;
2530 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2531 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2532 default:
2533 {
2534 /* Register addressing, handled at the beginning. */
2535 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2536 break;
2537 }
2538 }
2539 }
2540
2541 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2542 }
2543 else
2544 {
2545 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2546
2547 /*
2548 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2549 * See Intel instruction spec. 2.2 "IA-32e Mode".
2550 */
2551 uint64_t u64Disp = 0;
2552 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2553 if (fRipRelativeAddr)
2554 {
2555 /*
2556 * RIP-relative addressing mode.
2557 *
2558 * The displacement is 32-bit signed implying an offset range of +/-2G.
2559 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2560 */
2561 uint8_t const offDisp = offModRm + sizeof(bRm);
2562 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2563 }
2564 else
2565 {
2566 uint8_t offDisp = offModRm + sizeof(bRm);
2567
2568 /*
2569 * Register (and perhaps scale, index and base).
2570 *
2571 * REX.B extends the most-significant bit of the base register. However, REX.B
2572 * is ignored while determining whether an SIB follows the opcode. Hence, we
2573 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2574 *
2575 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2576 */
2577 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2578 if (iBaseReg == 4)
2579 {
2580 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2581 uint8_t bSib;
2582 uint8_t const offSib = offModRm + sizeof(bRm);
2583 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2584
2585 /* Displacement may follow SIB, update its offset. */
2586 offDisp += sizeof(bSib);
2587
2588 /* Get the scale. */
2589 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2590
2591 /* Get the index. */
2592 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2593 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2594
2595 /* Get the base. */
2596 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2597 fBaseRegValid = true;
2598 if (iBaseReg == 5)
2599 {
2600 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2601 {
2602 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2603 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2604 }
2605 else
2606 {
2607 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2608 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2609 }
2610 }
2611 }
2612 iBaseReg |= pVCpu->iem.s.uRexB;
2613
2614 /* Register + displacement. */
2615 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2616 {
2617 case 0: /* Handled above */ break;
2618 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2619 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2620 default:
2621 {
2622 /* Register addressing, handled at the beginning. */
2623 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2624 break;
2625 }
2626 }
2627 }
2628
2629 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2630 }
2631
2632 /*
2633 * The primary or secondary register operand is reported in iReg2 depending
2634 * on whether the primary operand is in read/write form.
2635 */
2636 uint8_t idxReg2;
2637 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2638 {
2639 idxReg2 = bRm & X86_MODRM_RM_MASK;
2640 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2641 idxReg2 |= pVCpu->iem.s.uRexB;
2642 }
2643 else
2644 {
2645 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2646 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2647 idxReg2 |= pVCpu->iem.s.uRexReg;
2648 }
2649 ExitInstrInfo.All.u2Scaling = uScale;
2650 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2651 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2652 ExitInstrInfo.All.fIsRegOperand = 0;
2653 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2654 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2655 ExitInstrInfo.All.iIdxReg = iIdxReg;
2656 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2657 ExitInstrInfo.All.iBaseReg = iBaseReg;
2658 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2659 ExitInstrInfo.All.iReg2 = idxReg2;
2660 }
2661
2662 /*
2663 * Handle exceptions to the norm for certain instructions.
2664 * (e.g. some instructions convey an instruction identity in place of iReg2).
2665 */
2666 switch (uExitReason)
2667 {
2668 case VMX_EXIT_GDTR_IDTR_ACCESS:
2669 {
2670 Assert(VMXINSTRID_IS_VALID(uInstrId));
2671 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2672 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2673 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2674 break;
2675 }
2676
2677 case VMX_EXIT_LDTR_TR_ACCESS:
2678 {
2679 Assert(VMXINSTRID_IS_VALID(uInstrId));
2680 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2681 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2682 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2683 break;
2684 }
2685
2686 case VMX_EXIT_RDRAND:
2687 case VMX_EXIT_RDSEED:
2688 {
2689 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2690 break;
2691 }
2692 }
2693
2694 /* Update displacement and return the constructed VM-exit instruction information field. */
2695 if (pGCPtrDisp)
2696 *pGCPtrDisp = GCPtrDisp;
2697
2698 return ExitInstrInfo.u;
2699}
2700
2701
2702/**
2703 * VMX VM-exit handler.
2704 *
2705 * @returns Strict VBox status code.
2706 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2707 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2708 * triple-fault.
2709 *
2710 * @param pVCpu The cross context virtual CPU structure.
2711 * @param uExitReason The VM-exit reason.
2712 * @param u64ExitQual The Exit qualification.
2713 */
2714IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2715{
2716# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2717 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2718 return VINF_EM_RAW_EMULATE_INSTR;
2719# else
2720 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2721 Assert(pVmcs);
2722
2723 /* Import all the guest-CPU state required for the VM-exit. */
2724 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
2725
2726 /* Ensure VM-entry interruption information valid bit isn't set. */
2727 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2728
2729 /*
2730 * Update the VM-exit reason and Exit qualification.
2731 * Other VMCS read-only data fields are expected to be updated by the caller already.
2732 */
2733 pVmcs->u32RoExitReason = uExitReason;
2734 pVmcs->u64RoExitQual.u = u64ExitQual;
2735 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2736 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2737
2738 /*
2739 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2740 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2741 */
2742 {
2743 uint8_t uVector;
2744 uint32_t fFlags;
2745 uint32_t uErrCode;
2746 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2747 if (fInEventDelivery)
2748 {
2749 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2750 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2751 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2752 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2753 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2754 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2755 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2756 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2757 }
2758 }
2759
2760 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2761 Assert(pVmcs->u64RoIoRcx.u == 0);
2762 Assert(pVmcs->u64RoIoRsi.u == 0);
2763 Assert(pVmcs->u64RoIoRdi.u == 0);
2764 Assert(pVmcs->u64RoIoRip.u == 0);
2765
2766 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2767 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2768 {
2769 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2770 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2771 }
2772
2773 /*
2774 * Save the guest state back into the VMCS.
2775 * We only need to save the state when the VM-entry was successful.
2776 */
2777 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2778 if (!fVmentryFailed)
2779 {
2780 /*
2781 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2782 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2783 *
2784 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2785 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2786 * as guest-CPU state would not been modified. Hence for now, we do this only when
2787 * the VM-entry succeeded.
2788 */
2789 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2790 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2791 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2792 {
2793 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2794 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2795 else
2796 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2797 }
2798
2799 /*
2800 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2801 * occurs in enclave mode/SMM which we don't support yet.
2802 *
2803 * If we ever add support for it, we can pass just the lower bits to the functions
2804 * below, till then an assert should suffice.
2805 */
2806 Assert(!RT_HI_U16(uExitReason));
2807
2808 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2809 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2810 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2811 if (RT_SUCCESS(rc))
2812 { /* likely */ }
2813 else
2814 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2815
2816 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2817 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2818 }
2819 else
2820 {
2821 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2822 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2823 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2824 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2825 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2826 }
2827
2828 /*
2829 * Clear any pending VMX nested-guest force-flags.
2830 * These force-flags have no effect on guest execution and will
2831 * be re-evaluated and setup on the next nested-guest VM-entry.
2832 */
2833 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2834 | VMCPU_FF_VMX_MTF
2835 | VMCPU_FF_VMX_APIC_WRITE
2836 | VMCPU_FF_VMX_INT_WINDOW
2837 | VMCPU_FF_VMX_NMI_WINDOW);
2838
2839 /* Restore the host (outer guest) state. */
2840 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2841 if (RT_SUCCESS(rcStrict))
2842 {
2843 Assert(rcStrict == VINF_SUCCESS);
2844 rcStrict = VINF_VMX_VMEXIT;
2845 }
2846 else
2847 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2848
2849 /* Notify HM that we've completed the VM-exit. */
2850 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2851
2852 /* We're no longer in nested-guest execution mode. */
2853 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2854
2855# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2856 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2857 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2858 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2859 if (rcSched != VINF_SUCCESS)
2860 iemSetPassUpStatus(pVCpu, rcSched);
2861# endif
2862 return rcStrict;
2863# endif
2864}
2865
2866
2867/**
2868 * VMX VM-exit handler for VM-exits due to instruction execution.
2869 *
2870 * This is intended for instructions where the caller provides all the relevant
2871 * VM-exit information.
2872 *
2873 * @returns Strict VBox status code.
2874 * @param pVCpu The cross context virtual CPU structure.
2875 * @param pExitInfo Pointer to the VM-exit information.
2876 */
2877IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2878{
2879 /*
2880 * For instructions where any of the following fields are not applicable:
2881 * - Exit qualification must be cleared.
2882 * - VM-exit instruction info. is undefined.
2883 * - Guest-linear address is undefined.
2884 * - Guest-physical address is undefined.
2885 *
2886 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2887 * instruction execution. For VM-exits that are not due to instruction execution this
2888 * field is undefined.
2889 *
2890 * In our implementation in IEM, all undefined fields are generally cleared. However,
2891 * if the caller supplies information (from say the physical CPU directly) it is
2892 * then possible that the undefined fields are not cleared.
2893 *
2894 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2895 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2896 */
2897 Assert(pExitInfo);
2898 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2899 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2900 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2901
2902 /* Update all the relevant fields from the VM-exit instruction information struct. */
2903 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2904 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2905 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2906 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2907
2908 /* Perform the VM-exit. */
2909 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2910}
2911
2912
2913/**
2914 * VMX VM-exit handler for VM-exits due to instruction execution.
2915 *
2916 * This is intended for instructions that only provide the VM-exit instruction
2917 * length.
2918 *
2919 * @param pVCpu The cross context virtual CPU structure.
2920 * @param uExitReason The VM-exit reason.
2921 * @param cbInstr The instruction length in bytes.
2922 */
2923IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2924{
2925 VMXVEXITINFO ExitInfo;
2926 RT_ZERO(ExitInfo);
2927 ExitInfo.uReason = uExitReason;
2928 ExitInfo.cbInstr = cbInstr;
2929
2930#ifdef VBOX_STRICT
2931 /*
2932 * To prevent us from shooting ourselves in the foot.
2933 * The follow instructions should convey more than just the instruction length.
2934 */
2935 switch (uExitReason)
2936 {
2937 case VMX_EXIT_INVEPT:
2938 case VMX_EXIT_INVPCID:
2939 case VMX_EXIT_INVVPID:
2940 case VMX_EXIT_LDTR_TR_ACCESS:
2941 case VMX_EXIT_GDTR_IDTR_ACCESS:
2942 case VMX_EXIT_VMCLEAR:
2943 case VMX_EXIT_VMPTRLD:
2944 case VMX_EXIT_VMPTRST:
2945 case VMX_EXIT_VMREAD:
2946 case VMX_EXIT_VMWRITE:
2947 case VMX_EXIT_VMXON:
2948 case VMX_EXIT_XRSTORS:
2949 case VMX_EXIT_XSAVES:
2950 case VMX_EXIT_RDRAND:
2951 case VMX_EXIT_RDSEED:
2952 case VMX_EXIT_IO_INSTR:
2953 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2954 break;
2955 }
2956#endif
2957
2958 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2959}
2960
2961
2962/**
2963 * VMX VM-exit handler for VM-exits due to instruction execution.
2964 *
2965 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2966 * instruction information and Exit qualification fields.
2967 *
2968 * @param pVCpu The cross context virtual CPU structure.
2969 * @param uExitReason The VM-exit reason.
2970 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2971 * @param cbInstr The instruction length in bytes.
2972 *
2973 * @remarks Do not use this for INS/OUTS instruction.
2974 */
2975IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2976{
2977 VMXVEXITINFO ExitInfo;
2978 RT_ZERO(ExitInfo);
2979 ExitInfo.uReason = uExitReason;
2980 ExitInfo.cbInstr = cbInstr;
2981
2982 /*
2983 * Update the Exit qualification field with displacement bytes.
2984 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2985 */
2986 switch (uExitReason)
2987 {
2988 case VMX_EXIT_INVEPT:
2989 case VMX_EXIT_INVPCID:
2990 case VMX_EXIT_INVVPID:
2991 case VMX_EXIT_LDTR_TR_ACCESS:
2992 case VMX_EXIT_GDTR_IDTR_ACCESS:
2993 case VMX_EXIT_VMCLEAR:
2994 case VMX_EXIT_VMPTRLD:
2995 case VMX_EXIT_VMPTRST:
2996 case VMX_EXIT_VMREAD:
2997 case VMX_EXIT_VMWRITE:
2998 case VMX_EXIT_VMXON:
2999 case VMX_EXIT_XRSTORS:
3000 case VMX_EXIT_XSAVES:
3001 case VMX_EXIT_RDRAND:
3002 case VMX_EXIT_RDSEED:
3003 {
3004 /* Construct the VM-exit instruction information. */
3005 RTGCPTR GCPtrDisp;
3006 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3007
3008 /* Update the VM-exit instruction information. */
3009 ExitInfo.InstrInfo.u = uInstrInfo;
3010
3011 /* Update the Exit qualification. */
3012 ExitInfo.u64Qual = GCPtrDisp;
3013 break;
3014 }
3015
3016 default:
3017 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3018 break;
3019 }
3020
3021 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3022}
3023
3024
3025/**
3026 * VMX VM-exit handler for VM-exits due to INVLPG.
3027 *
3028 * @returns Strict VBox status code.
3029 * @param pVCpu The cross context virtual CPU structure.
3030 * @param GCPtrPage The guest-linear address of the page being invalidated.
3031 * @param cbInstr The instruction length in bytes.
3032 */
3033IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3034{
3035 VMXVEXITINFO ExitInfo;
3036 RT_ZERO(ExitInfo);
3037 ExitInfo.uReason = VMX_EXIT_INVLPG;
3038 ExitInfo.cbInstr = cbInstr;
3039 ExitInfo.u64Qual = GCPtrPage;
3040 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3041
3042 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3043}
3044
3045
3046/**
3047 * VMX VM-exit handler for VM-exits due to LMSW.
3048 *
3049 * @returns Strict VBox status code.
3050 * @param pVCpu The cross context virtual CPU structure.
3051 * @param uGuestCr0 The current guest CR0.
3052 * @param pu16NewMsw The machine-status word specified in LMSW's source
3053 * operand. This will be updated depending on the VMX
3054 * guest/host CR0 mask if LMSW is not intercepted.
3055 * @param GCPtrEffDst The guest-linear address of the source operand in case
3056 * of a memory operand. For register operand, pass
3057 * NIL_RTGCPTR.
3058 * @param cbInstr The instruction length in bytes.
3059 */
3060IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3061 uint8_t cbInstr)
3062{
3063 Assert(pu16NewMsw);
3064
3065 uint16_t const uNewMsw = *pu16NewMsw;
3066 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
3067 {
3068 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3069
3070 VMXVEXITINFO ExitInfo;
3071 RT_ZERO(ExitInfo);
3072 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3073 ExitInfo.cbInstr = cbInstr;
3074
3075 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3076 if (fMemOperand)
3077 {
3078 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3079 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3080 }
3081
3082 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3083 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3084 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3085 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
3086
3087 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3088 }
3089
3090 /*
3091 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3092 * CR0 guest/host mask must be left unmodified.
3093 *
3094 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3095 */
3096 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3097 Assert(pVmcs);
3098 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3099 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3100 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
3101
3102 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3103}
3104
3105
3106/**
3107 * VMX VM-exit handler for VM-exits due to CLTS.
3108 *
3109 * @returns Strict VBox status code.
3110 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3111 * VM-exit but must not modify the guest CR0.TS bit.
3112 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3113 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3114 * CR0 fixed bits in VMX operation).
3115 * @param pVCpu The cross context virtual CPU structure.
3116 * @param cbInstr The instruction length in bytes.
3117 */
3118IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3119{
3120 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3121 Assert(pVmcs);
3122
3123 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3124 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3125
3126 /*
3127 * If CR0.TS is owned by the host:
3128 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3129 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3130 * CLTS instruction completes without clearing CR0.TS.
3131 *
3132 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3133 */
3134 if (fGstHostMask & X86_CR0_TS)
3135 {
3136 if (fReadShadow & X86_CR0_TS)
3137 {
3138 Log2(("clts: Guest intercept -> VM-exit\n"));
3139
3140 VMXVEXITINFO ExitInfo;
3141 RT_ZERO(ExitInfo);
3142 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3143 ExitInfo.cbInstr = cbInstr;
3144 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3145 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3146 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3147 }
3148
3149 return VINF_VMX_MODIFIES_BEHAVIOR;
3150 }
3151
3152 /*
3153 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3154 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3155 */
3156 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3157}
3158
3159
3160/**
3161 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3162 * (CR0/CR4 write).
3163 *
3164 * @returns Strict VBox status code.
3165 * @param pVCpu The cross context virtual CPU structure.
3166 * @param iCrReg The control register (either CR0 or CR4).
3167 * @param uGuestCrX The current guest CR0/CR4.
3168 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3169 * if no VM-exit is caused.
3170 * @param iGReg The general register from which the CR0/CR4 value is
3171 * being loaded.
3172 * @param cbInstr The instruction length in bytes.
3173 */
3174IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3175 uint8_t cbInstr)
3176{
3177 Assert(puNewCrX);
3178 Assert(iCrReg == 0 || iCrReg == 4);
3179 Assert(iGReg < X86_GREG_COUNT);
3180
3181 uint64_t const uNewCrX = *puNewCrX;
3182 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3183 {
3184 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3185
3186 VMXVEXITINFO ExitInfo;
3187 RT_ZERO(ExitInfo);
3188 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3189 ExitInfo.cbInstr = cbInstr;
3190 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3191 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3192 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3193 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3194 }
3195
3196 /*
3197 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3198 * must not be modified the instruction.
3199 *
3200 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3201 */
3202 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3203 Assert(pVmcs);
3204 uint64_t uGuestCrX;
3205 uint64_t fGstHostMask;
3206 if (iCrReg == 0)
3207 {
3208 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3209 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3210 fGstHostMask = pVmcs->u64Cr0Mask.u;
3211 }
3212 else
3213 {
3214 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3215 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3216 fGstHostMask = pVmcs->u64Cr4Mask.u;
3217 }
3218
3219 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3220 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3221}
3222
3223
3224/**
3225 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3226 *
3227 * @returns VBox strict status code.
3228 * @param pVCpu The cross context virtual CPU structure.
3229 * @param iGReg The general register to which the CR3 value is being stored.
3230 * @param cbInstr The instruction length in bytes.
3231 */
3232IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3233{
3234 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3235 Assert(pVmcs);
3236 Assert(iGReg < X86_GREG_COUNT);
3237 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3238
3239 /*
3240 * If the CR3-store exiting control is set, we must cause a VM-exit.
3241 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3242 */
3243 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3244 {
3245 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3246
3247 VMXVEXITINFO ExitInfo;
3248 RT_ZERO(ExitInfo);
3249 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3250 ExitInfo.cbInstr = cbInstr;
3251 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3252 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3254 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3255 }
3256
3257 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3258}
3259
3260
3261/**
3262 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3263 *
3264 * @returns VBox strict status code.
3265 * @param pVCpu The cross context virtual CPU structure.
3266 * @param uNewCr3 The new CR3 value.
3267 * @param iGReg The general register from which the CR3 value is being
3268 * loaded.
3269 * @param cbInstr The instruction length in bytes.
3270 */
3271IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3272{
3273 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3274 Assert(pVmcs);
3275 Assert(iGReg < X86_GREG_COUNT);
3276
3277 /*
3278 * If the CR3-load exiting control is set and the new CR3 value does not
3279 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3280 *
3281 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3282 */
3283 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3284 {
3285 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3286 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3287
3288 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3289 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3290 if (!fIntercept)
3291 {
3292 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3293 {
3294 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3295 if (uNewCr3 != uCr3TargetValue)
3296 {
3297 fIntercept = true;
3298 break;
3299 }
3300 }
3301 }
3302
3303 if (fIntercept)
3304 {
3305 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3306
3307 VMXVEXITINFO ExitInfo;
3308 RT_ZERO(ExitInfo);
3309 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3310 ExitInfo.cbInstr = cbInstr;
3311 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3312 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3313 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3314 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3315 }
3316 }
3317
3318 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3319}
3320
3321
3322/**
3323 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3324 *
3325 * @returns VBox strict status code.
3326 * @param pVCpu The cross context virtual CPU structure.
3327 * @param iGReg The general register to which the CR8 value is being stored.
3328 * @param cbInstr The instruction length in bytes.
3329 */
3330IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3331{
3332 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3333 Assert(pVmcs);
3334 Assert(iGReg < X86_GREG_COUNT);
3335
3336 /*
3337 * If the CR8-store exiting control is set, we must cause a VM-exit.
3338 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3339 */
3340 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3341 {
3342 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3343
3344 VMXVEXITINFO ExitInfo;
3345 RT_ZERO(ExitInfo);
3346 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3347 ExitInfo.cbInstr = cbInstr;
3348 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3349 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3350 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3351 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3352 }
3353
3354 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3355}
3356
3357
3358/**
3359 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3360 *
3361 * @returns VBox strict status code.
3362 * @param pVCpu The cross context virtual CPU structure.
3363 * @param iGReg The general register from which the CR8 value is being
3364 * loaded.
3365 * @param cbInstr The instruction length in bytes.
3366 */
3367IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3368{
3369 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3370 Assert(pVmcs);
3371 Assert(iGReg < X86_GREG_COUNT);
3372
3373 /*
3374 * If the CR8-load exiting control is set, we must cause a VM-exit.
3375 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3376 */
3377 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3378 {
3379 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3380
3381 VMXVEXITINFO ExitInfo;
3382 RT_ZERO(ExitInfo);
3383 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3384 ExitInfo.cbInstr = cbInstr;
3385 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3386 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3387 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3388 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3389 }
3390
3391 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3392}
3393
3394
3395/**
3396 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3397 * GReg,DRx' (DRx read).
3398 *
3399 * @returns VBox strict status code.
3400 * @param pVCpu The cross context virtual CPU structure.
3401 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3402 * VMXINSTRID_MOV_FROM_DRX).
3403 * @param iDrReg The debug register being accessed.
3404 * @param iGReg The general register to/from which the DRx value is being
3405 * store/loaded.
3406 * @param cbInstr The instruction length in bytes.
3407 */
3408IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3409 uint8_t cbInstr)
3410{
3411 Assert(iDrReg <= 7);
3412 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3413 Assert(iGReg < X86_GREG_COUNT);
3414
3415 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3416 Assert(pVmcs);
3417
3418 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3419 {
3420 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3421 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3422 VMXVEXITINFO ExitInfo;
3423 RT_ZERO(ExitInfo);
3424 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3425 ExitInfo.cbInstr = cbInstr;
3426 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3427 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3428 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3429 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3430 }
3431
3432 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3433}
3434
3435
3436/**
3437 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3438 *
3439 * @returns VBox strict status code.
3440 * @param pVCpu The cross context virtual CPU structure.
3441 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3442 * VMXINSTRID_IO_OUT).
3443 * @param u16Port The I/O port being accessed.
3444 * @param fImm Whether the I/O port was encoded using an immediate operand
3445 * or the implicit DX register.
3446 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3447 * @param cbInstr The instruction length in bytes.
3448 */
3449IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3450 uint8_t cbInstr)
3451{
3452 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3453 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3454
3455 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3456 if (fIntercept)
3457 {
3458 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3459 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3460 VMXVEXITINFO ExitInfo;
3461 RT_ZERO(ExitInfo);
3462 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3463 ExitInfo.cbInstr = cbInstr;
3464 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3465 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3466 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3467 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3468 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3469 }
3470
3471 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3472}
3473
3474
3475/**
3476 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3477 *
3478 * @returns VBox strict status code.
3479 * @param pVCpu The cross context virtual CPU structure.
3480 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3481 * VMXINSTRID_IO_OUTS).
3482 * @param u16Port The I/O port being accessed.
3483 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3484 * @param fRep Whether the instruction has a REP prefix or not.
3485 * @param ExitInstrInfo The VM-exit instruction info. field.
3486 * @param cbInstr The instruction length in bytes.
3487 */
3488IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3489 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3490{
3491 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3492 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3493 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3494 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3495 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3496
3497 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3498 if (fIntercept)
3499 {
3500 /*
3501 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3502 */
3503 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3504 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3505 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3506 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3507 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3508
3509 uint32_t uDirection;
3510 uint64_t uGuestLinearAddr;
3511 if (uInstrId == VMXINSTRID_IO_INS)
3512 {
3513 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3514 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3515 }
3516 else
3517 {
3518 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3519 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3520 }
3521
3522 /*
3523 * If the segment is unusable, the guest-linear address in undefined.
3524 * We shall clear it for consistency.
3525 *
3526 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3527 */
3528 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3529 uGuestLinearAddr = 0;
3530
3531 VMXVEXITINFO ExitInfo;
3532 RT_ZERO(ExitInfo);
3533 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3534 ExitInfo.cbInstr = cbInstr;
3535 ExitInfo.InstrInfo = ExitInstrInfo;
3536 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3537 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3538 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3539 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3540 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3541 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3542 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3543 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3544 }
3545
3546 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3547}
3548
3549
3550/**
3551 * VMX VM-exit handler for VM-exits due to MWAIT.
3552 *
3553 * @returns VBox strict status code.
3554 * @param pVCpu The cross context virtual CPU structure.
3555 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3556 * @param cbInstr The instruction length in bytes.
3557 */
3558IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3559{
3560 VMXVEXITINFO ExitInfo;
3561 RT_ZERO(ExitInfo);
3562 ExitInfo.uReason = VMX_EXIT_MWAIT;
3563 ExitInfo.cbInstr = cbInstr;
3564 ExitInfo.u64Qual = fMonitorHwArmed;
3565 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3566}
3567
3568
3569/**
3570 * VMX VM-exit handler for VM-exits due to PAUSE.
3571 *
3572 * @returns VBox strict status code.
3573 * @param pVCpu The cross context virtual CPU structure.
3574 * @param cbInstr The instruction length in bytes.
3575 */
3576IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3577{
3578 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3579 Assert(pVmcs);
3580
3581 /*
3582 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3583 * "PAUSE-loop exiting" control.
3584 *
3585 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3586 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3587 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3588 * a VM-exit.
3589 *
3590 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3591 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3592 */
3593 bool fIntercept = false;
3594 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3595 fIntercept = true;
3596 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3597 && pVCpu->iem.s.uCpl == 0)
3598 {
3599 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3600
3601 /*
3602 * A previous-PAUSE-tick value of 0 is used to identify the first time
3603 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3604 * consider this to be the first execution of PAUSE in a loop according
3605 * to the Intel.
3606 *
3607 * All subsequent records for the previous-PAUSE-tick we ensure that it
3608 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3609 */
3610 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3611 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3612 uint64_t const uTick = TMCpuTickGet(pVCpu);
3613 uint32_t const uPleGap = pVmcs->u32PleGap;
3614 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3615 if ( *puPrevPauseTick == 0
3616 || uTick - *puPrevPauseTick > uPleGap)
3617 *puFirstPauseLoopTick = uTick;
3618 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3619 fIntercept = true;
3620
3621 *puPrevPauseTick = uTick | 1;
3622 }
3623
3624 if (fIntercept)
3625 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3626
3627 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3628}
3629
3630
3631/**
3632 * VMX VM-exit handler for VM-exits due to task switches.
3633 *
3634 * @returns VBox strict status code.
3635 * @param pVCpu The cross context virtual CPU structure.
3636 * @param enmTaskSwitch The cause of the task switch.
3637 * @param SelNewTss The selector of the new TSS.
3638 * @param cbInstr The instruction length in bytes.
3639 */
3640IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3641{
3642 /*
3643 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3644 *
3645 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3646 * instruction or delivery of the exception generated by one of these instructions
3647 * lead to a task switch through a task gate in the IDT, we need to provide the
3648 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3649 * leaves the VM-exit instruction length field undefined.
3650 *
3651 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3652 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3653 */
3654 Assert(cbInstr <= 15);
3655
3656 uint8_t uType;
3657 switch (enmTaskSwitch)
3658 {
3659 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3660 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3661 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3662 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3663 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3664 }
3665
3666 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3667 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3668 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3669 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3670}
3671
3672
3673/**
3674 * VMX VM-exit handler for VM-exits due to task switches.
3675 *
3676 * This is intended for task switches where the caller provides all the relevant
3677 * VM-exit information.
3678 *
3679 * @returns VBox strict status code.
3680 * @param pVCpu The cross context virtual CPU structure.
3681 * @param pExitInfo Pointer to the VM-exit information.
3682 * @param pExitEventInfo Pointer to the VM-exit event information.
3683 */
3684IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3685 PCVMXVEXITEVENTINFO pExitEventInfo)
3686{
3687 Assert(pExitInfo);
3688 Assert(pExitEventInfo);
3689
3690 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3691 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3692 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3693
3694 /*
3695 * Figure out if an instruction was the source of the task switch.
3696 *
3697 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3698 * of an event generated by a software interrupt (INT-N), privileged software
3699 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3700 * the instruction length.
3701 */
3702 bool fHasInstrLen;
3703 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3704 {
3705 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3706 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3707 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3708 if (fIdtVectInfoValid)
3709 {
3710 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3711 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3712 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3713
3714 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3715 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3716 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3717 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3718 fHasInstrLen = true;
3719 else
3720 fHasInstrLen = false;
3721 }
3722 else
3723 fHasInstrLen = false;
3724 }
3725 else
3726 {
3727 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3728 fHasInstrLen = true;
3729 }
3730
3731 if (fHasInstrLen)
3732 {
3733 Assert(pExitInfo->cbInstr > 0);
3734 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3735 }
3736 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3737}
3738
3739
3740/**
3741 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3742 *
3743 * @returns VBox strict status code.
3744 * @param pVCpu The cross context virtual CPU structure.
3745 */
3746IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3747{
3748 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3749 Assert(pVmcs);
3750
3751 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3752 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3753 {
3754 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3755 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3756
3757 /*
3758 * Calculate the current VMX-preemption timer value.
3759 * Only if the value has reached zero, we cause the VM-exit.
3760 */
3761 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3762 if (!uPreemptTimer)
3763 {
3764 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3765 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3766 pVmcs->u32PreemptTimer = 0;
3767
3768 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3769 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3770 }
3771 }
3772
3773 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3774}
3775
3776
3777/**
3778 * VMX VM-exit handler for VM-exits due to external interrupts.
3779 *
3780 * @returns VBox strict status code.
3781 * @param pVCpu The cross context virtual CPU structure.
3782 * @param uVector The external interrupt vector (pass 0 if the interrupt
3783 * is still pending since we typically won't know the
3784 * vector).
3785 * @param fIntPending Whether the external interrupt is pending or
3786 * acknowledged in the interrupt controller.
3787 */
3788IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3789{
3790 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3791 Assert(pVmcs);
3792 Assert(fIntPending || uVector == 0);
3793
3794 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3795 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3796 * functions require prior checking of a blanket intercept and which don't.
3797 * It is better for the caller to check a blanket intercept performance wise
3798 * than making a function call. Leaving this as a todo because it is more
3799 * a performance issue. */
3800
3801 /* The VM-exit is subject to "External interrupt exiting" being set. */
3802 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3803 {
3804 if (fIntPending)
3805 {
3806 /*
3807 * If the interrupt is pending and we don't need to acknowledge the
3808 * interrupt on VM-exit, cause the VM-exit immediately.
3809 *
3810 * See Intel spec 25.2 "Other Causes Of VM Exits".
3811 */
3812 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3813 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3814
3815 /*
3816 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3817 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3818 * acknowledged that the interrupt has been consumed.
3819 */
3820 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3821 }
3822
3823 /*
3824 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3825 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3826 * all set, we cause the VM-exit now. We need to record the external interrupt that
3827 * just occurred in the VM-exit interruption information field.
3828 *
3829 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3830 */
3831 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3832 {
3833 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3834 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3835 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3836 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3837 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3838 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3839 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3840 }
3841 }
3842
3843 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3844}
3845
3846
3847/**
3848 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3849 * an event.
3850 *
3851 * @returns VBox strict status code.
3852 * @param pVCpu The cross context virtual CPU structure.
3853 */
3854IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3855{
3856 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3857 Assert(pVmcs);
3858
3859 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3860 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3861 {
3862 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3863 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3864 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3865 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3866 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3867 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3868 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3869 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3870 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3871
3872 /*
3873 * A VM-exit is not considered to occur during event delivery when the original
3874 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3875 * using the exception bitmap).
3876 *
3877 * Therefore, we must clear the original event from the IDT-vectoring fields which
3878 * would've been recorded before causing the VM-exit.
3879 *
3880 * 27.2.3 "Information for VM Exits During Event Delivery"
3881 */
3882 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3883 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3884 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3885 }
3886
3887 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3888}
3889
3890
3891/**
3892 * VMX VM-exit handler for VM-exit due to delivery of an events.
3893 *
3894 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3895 * all the relevant VM-exit information.
3896 *
3897 * @returns VBox strict status code.
3898 * @param pVCpu The cross context virtual CPU structure.
3899 * @param pExitInfo Pointer to the VM-exit information.
3900 * @param pExitEventInfo Pointer to the VM-exit event information.
3901 */
3902IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3903{
3904 Assert(pExitInfo);
3905 Assert(pExitEventInfo);
3906 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3907
3908 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3909 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3910 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3911 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3912 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3913 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3914}
3915
3916
3917/**
3918 * VMX VM-exit handler for VM-exits due to delivery of an event.
3919 *
3920 * @returns VBox strict status code.
3921 * @param pVCpu The cross context virtual CPU structure.
3922 * @param uVector The interrupt / exception vector.
3923 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3924 * @param uErrCode The error code associated with the event.
3925 * @param uCr2 The CR2 value in case of a \#PF exception.
3926 * @param cbInstr The instruction length in bytes.
3927 */
3928IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3929 uint8_t cbInstr)
3930{
3931 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3932 Assert(pVmcs);
3933
3934 /*
3935 * If the event is being injected as part of VM-entry, it is -not- subject to event
3936 * intercepts in the nested-guest. However, secondary exceptions that occur during
3937 * injection of any event -are- subject to event interception.
3938 *
3939 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3940 */
3941 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3942 {
3943 /*
3944 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3945 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3946 *
3947 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3948 */
3949 if ( uVector == X86_XCPT_NMI
3950 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3951 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3952 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3953 else
3954 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3955
3956 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3957 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3958 }
3959
3960 /*
3961 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3962 * If not, the caller will continue delivery of the external interrupt as it would
3963 * normally. The interrupt is no longer pending in the interrupt controller at this
3964 * point.
3965 */
3966 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3967 {
3968 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3969 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3970 }
3971
3972 /*
3973 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3974 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3975 * interrupts.
3976 */
3977 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3978 bool fIntercept;
3979 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3980 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3981 {
3982 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3983 }
3984 else
3985 {
3986 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3987 fIntercept = false;
3988 }
3989
3990 /*
3991 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3992 * relevant VM-exit information and cause the VM-exit.
3993 */
3994 if (fIntercept)
3995 {
3996 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3997
3998 /* Construct the rest of the event related information fields and cause the VM-exit. */
3999 uint64_t u64ExitQual;
4000 if (uVector == X86_XCPT_PF)
4001 {
4002 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4003 u64ExitQual = uCr2;
4004 }
4005 else if (uVector == X86_XCPT_DB)
4006 {
4007 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4008 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4009 }
4010 else
4011 u64ExitQual = 0;
4012
4013 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4014 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4015 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4016 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4017 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4018 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4019 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4020 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4021 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4022 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4023
4024 /*
4025 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
4026 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4027 * length.
4028 */
4029 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4030 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4031 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4032 else
4033 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4034
4035 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
4036 }
4037
4038 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4039}
4040
4041
4042/**
4043 * VMX VM-exit handler for VM-exits due to a triple fault.
4044 *
4045 * @returns VBox strict status code.
4046 * @param pVCpu The cross context virtual CPU structure.
4047 */
4048IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4049{
4050 /*
4051 * A VM-exit is not considered to occur during event delivery when the original
4052 * event results in a triple-fault.
4053 *
4054 * Therefore, we must clear the original event from the IDT-vectoring fields which
4055 * would've been recorded before causing the VM-exit.
4056 *
4057 * 27.2.3 "Information for VM Exits During Event Delivery"
4058 */
4059 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4060 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4061
4062 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
4063}
4064
4065
4066/**
4067 * VMX VM-exit handler for APIC accesses.
4068 *
4069 * @param pVCpu The cross context virtual CPU structure.
4070 * @param offAccess The offset of the register being accessed.
4071 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4072 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4073 */
4074IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4075{
4076 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4077
4078 VMXAPICACCESS enmAccess;
4079 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4080 if (fInEventDelivery)
4081 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4082 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4083 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4084 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4085 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4086 else
4087 enmAccess = VMXAPICACCESS_LINEAR_READ;
4088
4089 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4090 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4091 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4092}
4093
4094
4095/**
4096 * VMX VM-exit handler for APIC accesses.
4097 *
4098 * This is intended for APIC accesses where the caller provides all the
4099 * relevant VM-exit information.
4100 *
4101 * @returns VBox strict status code.
4102 * @param pVCpu The cross context virtual CPU structure.
4103 * @param pExitInfo Pointer to the VM-exit information.
4104 * @param pExitEventInfo Pointer to the VM-exit event information.
4105 */
4106IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
4107 PCVMXVEXITEVENTINFO pExitEventInfo)
4108{
4109 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4110 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4111 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4112 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4113 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4114 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4115 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4116}
4117
4118
4119/**
4120 * VMX VM-exit handler for APIC-write VM-exits.
4121 *
4122 * @param pVCpu The cross context virtual CPU structure.
4123 * @param offApic The write to the virtual-APIC page offset that caused this
4124 * VM-exit.
4125 */
4126IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4127{
4128 Assert(offApic < XAPIC_OFF_END + 4);
4129 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4130 offApic &= UINT16_C(0xfff);
4131 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4132}
4133
4134
4135/**
4136 * Sets virtual-APIC write emulation as pending.
4137 *
4138 * @param pVCpu The cross context virtual CPU structure.
4139 * @param offApic The offset in the virtual-APIC page that was written.
4140 */
4141DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4142{
4143 Assert(offApic < XAPIC_OFF_END + 4);
4144
4145 /*
4146 * Record the currently updated APIC offset, as we need this later for figuring
4147 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4148 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4149 */
4150 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4151
4152 /*
4153 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4154 * virtualization or APIC-write emulation).
4155 */
4156 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4157 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4158}
4159
4160
4161/**
4162 * Clears any pending virtual-APIC write emulation.
4163 *
4164 * @returns The virtual-APIC offset that was written before clearing it.
4165 * @param pVCpu The cross context virtual CPU structure.
4166 */
4167DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4168{
4169 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4170 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4171 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4172 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4173 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4174 return offVirtApicWrite;
4175}
4176
4177
4178/**
4179 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4180 *
4181 * @returns The register from the virtual-APIC page.
4182 * @param pVCpu The cross context virtual CPU structure.
4183 * @param offReg The offset of the register being read.
4184 */
4185IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4186{
4187 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4188 Assert(pVmcs);
4189
4190 uint32_t uReg;
4191 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4192 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4193 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4194 if (RT_FAILURE(rc))
4195 {
4196 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4197 GCPhysVirtApic));
4198 uReg = 0;
4199 }
4200 return uReg;
4201}
4202
4203
4204/**
4205 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4206 *
4207 * @returns The register from the virtual-APIC page.
4208 * @param pVCpu The cross context virtual CPU structure.
4209 * @param offReg The offset of the register being read.
4210 */
4211IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4212{
4213 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4214 Assert(pVmcs);
4215
4216 uint64_t uReg;
4217 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4218 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4219 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4220 if (RT_FAILURE(rc))
4221 {
4222 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4223 GCPhysVirtApic));
4224 uReg = 0;
4225 }
4226 return uReg;
4227}
4228
4229
4230/**
4231 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4232 *
4233 * @param pVCpu The cross context virtual CPU structure.
4234 * @param offReg The offset of the register being written.
4235 * @param uReg The register value to write.
4236 */
4237IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4238{
4239 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4240 Assert(pVmcs);
4241 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4242 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4243 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4244 if (RT_FAILURE(rc))
4245 {
4246 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4247 GCPhysVirtApic));
4248 }
4249}
4250
4251
4252/**
4253 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4254 *
4255 * @param pVCpu The cross context virtual CPU structure.
4256 * @param offReg The offset of the register being written.
4257 * @param uReg The register value to write.
4258 */
4259IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4260{
4261 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4262 Assert(pVmcs);
4263 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4264 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4265 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4266 if (RT_FAILURE(rc))
4267 {
4268 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4269 GCPhysVirtApic));
4270 }
4271}
4272
4273
4274/**
4275 * Sets the vector in a virtual-APIC 256-bit sparse register.
4276 *
4277 * @param pVCpu The cross context virtual CPU structure.
4278 * @param offReg The offset of the 256-bit spare register.
4279 * @param uVector The vector to set.
4280 *
4281 * @remarks This is based on our APIC device code.
4282 */
4283IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4284{
4285 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4286 Assert(pVmcs);
4287 uint32_t uReg;
4288 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4289 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4290 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4291 if (RT_SUCCESS(rc))
4292 {
4293 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4294 uReg |= RT_BIT(idxVectorBit);
4295 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4296 if (RT_FAILURE(rc))
4297 {
4298 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4299 uVector, offReg, GCPhysVirtApic));
4300 }
4301 }
4302 else
4303 {
4304 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4305 uVector, offReg, GCPhysVirtApic));
4306 }
4307}
4308
4309
4310/**
4311 * Clears the vector in a virtual-APIC 256-bit sparse register.
4312 *
4313 * @param pVCpu The cross context virtual CPU structure.
4314 * @param offReg The offset of the 256-bit spare register.
4315 * @param uVector The vector to clear.
4316 *
4317 * @remarks This is based on our APIC device code.
4318 */
4319IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4320{
4321 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4322 Assert(pVmcs);
4323 uint32_t uReg;
4324 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4325 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4326 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4327 if (RT_SUCCESS(rc))
4328 {
4329 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4330 uReg &= ~RT_BIT(idxVectorBit);
4331 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4332 if (RT_FAILURE(rc))
4333 {
4334 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4335 uVector, offReg, GCPhysVirtApic));
4336 }
4337 }
4338 else
4339 {
4340 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4341 uVector, offReg, GCPhysVirtApic));
4342 }
4343}
4344
4345
4346/**
4347 * Checks if a memory access to the APIC-access page must causes an APIC-access
4348 * VM-exit.
4349 *
4350 * @param pVCpu The cross context virtual CPU structure.
4351 * @param offAccess The offset of the register being accessed.
4352 * @param cbAccess The size of the access in bytes.
4353 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4354 * IEM_ACCESS_TYPE_WRITE).
4355 *
4356 * @remarks This must not be used for MSR-based APIC-access page accesses!
4357 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4358 */
4359IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4360{
4361 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4362 Assert(pVmcs);
4363 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4364
4365 /*
4366 * We must cause a VM-exit if any of the following are true:
4367 * - TPR shadowing isn't active.
4368 * - The access size exceeds 32-bits.
4369 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4370 *
4371 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4372 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4373 */
4374 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4375 || cbAccess > sizeof(uint32_t)
4376 || ((offAccess + cbAccess - 1) & 0xc)
4377 || offAccess >= XAPIC_OFF_END + 4)
4378 return true;
4379
4380 /*
4381 * If the access is part of an operation where we have already
4382 * virtualized a virtual-APIC write, we must cause a VM-exit.
4383 */
4384 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4385 return true;
4386
4387 /*
4388 * Check write accesses to the APIC-access page that cause VM-exits.
4389 */
4390 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4391 {
4392 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4393 {
4394 /*
4395 * With APIC-register virtualization, a write access to any of the
4396 * following registers are virtualized. Accessing any other register
4397 * causes a VM-exit.
4398 */
4399 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4400 switch (offAlignedAccess)
4401 {
4402 case XAPIC_OFF_ID:
4403 case XAPIC_OFF_TPR:
4404 case XAPIC_OFF_EOI:
4405 case XAPIC_OFF_LDR:
4406 case XAPIC_OFF_DFR:
4407 case XAPIC_OFF_SVR:
4408 case XAPIC_OFF_ESR:
4409 case XAPIC_OFF_ICR_LO:
4410 case XAPIC_OFF_ICR_HI:
4411 case XAPIC_OFF_LVT_TIMER:
4412 case XAPIC_OFF_LVT_THERMAL:
4413 case XAPIC_OFF_LVT_PERF:
4414 case XAPIC_OFF_LVT_LINT0:
4415 case XAPIC_OFF_LVT_LINT1:
4416 case XAPIC_OFF_LVT_ERROR:
4417 case XAPIC_OFF_TIMER_ICR:
4418 case XAPIC_OFF_TIMER_DCR:
4419 break;
4420 default:
4421 return true;
4422 }
4423 }
4424 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4425 {
4426 /*
4427 * With virtual-interrupt delivery, a write access to any of the
4428 * following registers are virtualized. Accessing any other register
4429 * causes a VM-exit.
4430 *
4431 * Note! The specification does not allow writing to offsets in-between
4432 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4433 */
4434 switch (offAccess)
4435 {
4436 case XAPIC_OFF_TPR:
4437 case XAPIC_OFF_EOI:
4438 case XAPIC_OFF_ICR_LO:
4439 break;
4440 default:
4441 return true;
4442 }
4443 }
4444 else
4445 {
4446 /*
4447 * Without APIC-register virtualization or virtual-interrupt delivery,
4448 * only TPR accesses are virtualized.
4449 */
4450 if (offAccess == XAPIC_OFF_TPR)
4451 { /* likely */ }
4452 else
4453 return true;
4454 }
4455 }
4456 else
4457 {
4458 /*
4459 * Check read accesses to the APIC-access page that cause VM-exits.
4460 */
4461 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4462 {
4463 /*
4464 * With APIC-register virtualization, a read access to any of the
4465 * following registers are virtualized. Accessing any other register
4466 * causes a VM-exit.
4467 */
4468 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4469 switch (offAlignedAccess)
4470 {
4471 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4472 case XAPIC_OFF_ID:
4473 case XAPIC_OFF_VERSION:
4474 case XAPIC_OFF_TPR:
4475 case XAPIC_OFF_EOI:
4476 case XAPIC_OFF_LDR:
4477 case XAPIC_OFF_DFR:
4478 case XAPIC_OFF_SVR:
4479 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4480 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4481 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4482 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4483 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4484 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4485 case XAPIC_OFF_ESR:
4486 case XAPIC_OFF_ICR_LO:
4487 case XAPIC_OFF_ICR_HI:
4488 case XAPIC_OFF_LVT_TIMER:
4489 case XAPIC_OFF_LVT_THERMAL:
4490 case XAPIC_OFF_LVT_PERF:
4491 case XAPIC_OFF_LVT_LINT0:
4492 case XAPIC_OFF_LVT_LINT1:
4493 case XAPIC_OFF_LVT_ERROR:
4494 case XAPIC_OFF_TIMER_ICR:
4495 case XAPIC_OFF_TIMER_DCR:
4496 break;
4497 default:
4498 return true;
4499 }
4500 }
4501 else
4502 {
4503 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4504 if (offAccess == XAPIC_OFF_TPR)
4505 { /* likely */ }
4506 else
4507 return true;
4508 }
4509 }
4510
4511 /* The APIC access is virtualized, does not cause a VM-exit. */
4512 return false;
4513}
4514
4515
4516/**
4517 * Virtualizes a memory-based APIC access where the address is not used to access
4518 * memory.
4519 *
4520 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4521 * page-faults but do not use the address to access memory.
4522 *
4523 * @param pVCpu The cross context virtual CPU structure.
4524 * @param pGCPhysAccess Pointer to the guest-physical address used.
4525 */
4526IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4527{
4528 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4529 Assert(pVmcs);
4530 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4531 Assert(pGCPhysAccess);
4532
4533 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4534 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4535 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4536
4537 if (GCPhysAccess == GCPhysApic)
4538 {
4539 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4540 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4541 uint16_t const cbAccess = 1;
4542 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4543 if (fIntercept)
4544 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4545
4546 *pGCPhysAccess = GCPhysApic | offAccess;
4547 return VINF_VMX_MODIFIES_BEHAVIOR;
4548 }
4549
4550 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4551}
4552
4553
4554/**
4555 * Virtualizes a memory-based APIC access.
4556 *
4557 * @returns VBox strict status code.
4558 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4559 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4560 *
4561 * @param pVCpu The cross context virtual CPU structure.
4562 * @param offAccess The offset of the register being accessed (within the
4563 * APIC-access page).
4564 * @param cbAccess The size of the access in bytes.
4565 * @param pvData Pointer to the data being written or where to store the data
4566 * being read.
4567 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4568 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4569 */
4570IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4571 uint32_t fAccess)
4572{
4573 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4574 Assert(pVmcs);
4575 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4576 Assert(pvData);
4577 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4578 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4579 || (fAccess & IEM_ACCESS_INSTRUCTION));
4580
4581 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4582 if (fIntercept)
4583 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4584
4585 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4586 {
4587 /*
4588 * A write access to the APIC-access page that is virtualized (rather than
4589 * causing a VM-exit) writes data to the virtual-APIC page.
4590 */
4591 uint32_t const u32Data = *(uint32_t *)pvData;
4592 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4593
4594 /*
4595 * Record the currently updated APIC offset, as we need this later for figuring
4596 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4597 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4598 *
4599 * After completion of the current operation, we need to perform TPR virtualization,
4600 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4601 *
4602 * The current operation may be a REP-prefixed string instruction, execution of any
4603 * other instruction, or delivery of an event through the IDT.
4604 *
4605 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4606 * performed now but later after completion of the current operation.
4607 *
4608 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4609 */
4610 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4611 }
4612 else
4613 {
4614 /*
4615 * A read access from the APIC-access page that is virtualized (rather than
4616 * causing a VM-exit) returns data from the virtual-APIC page.
4617 *
4618 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4619 */
4620 Assert(cbAccess <= 4);
4621 Assert(offAccess < XAPIC_OFF_END + 4);
4622 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4623
4624 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4625 u32Data &= s_auAccessSizeMasks[cbAccess];
4626 *(uint32_t *)pvData = u32Data;
4627 }
4628
4629 return VINF_VMX_MODIFIES_BEHAVIOR;
4630}
4631
4632
4633/**
4634 * Virtualizes an MSR-based APIC read access.
4635 *
4636 * @returns VBox strict status code.
4637 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4638 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4639 * handled by the x2APIC device.
4640 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4641 * not within the range of valid MSRs, caller must raise \#GP(0).
4642 * @param pVCpu The cross context virtual CPU structure.
4643 * @param idMsr The x2APIC MSR being read.
4644 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4645 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4646 */
4647IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4648{
4649 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4650 Assert(pVmcs);
4651 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4652 Assert(pu64Value);
4653
4654 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4655 {
4656 /*
4657 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4658 * what the end of the valid x2APIC MSR range is. Hence the use of different
4659 * macros here.
4660 *
4661 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4662 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4663 */
4664 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4665 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4666 {
4667 uint16_t const offReg = (idMsr & 0xff) << 4;
4668 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4669 *pu64Value = u64Value;
4670 return VINF_VMX_MODIFIES_BEHAVIOR;
4671 }
4672 return VERR_OUT_OF_RANGE;
4673 }
4674
4675 if (idMsr == MSR_IA32_X2APIC_TPR)
4676 {
4677 uint16_t const offReg = (idMsr & 0xff) << 4;
4678 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4679 *pu64Value = u64Value;
4680 return VINF_VMX_MODIFIES_BEHAVIOR;
4681 }
4682
4683 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4684}
4685
4686
4687/**
4688 * Virtualizes an MSR-based APIC write access.
4689 *
4690 * @returns VBox strict status code.
4691 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4692 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4693 * not within the range of valid MSRs, caller must raise \#GP(0).
4694 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4695 *
4696 * @param pVCpu The cross context virtual CPU structure.
4697 * @param idMsr The x2APIC MSR being written.
4698 * @param u64Value The value of the x2APIC MSR being written.
4699 */
4700IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4701{
4702 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4703 Assert(pVmcs);
4704
4705 /*
4706 * Check if the access is to be virtualized.
4707 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4708 */
4709 if ( idMsr == MSR_IA32_X2APIC_TPR
4710 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4711 && ( idMsr == MSR_IA32_X2APIC_EOI
4712 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4713 {
4714 /* Validate the MSR write depending on the register. */
4715 switch (idMsr)
4716 {
4717 case MSR_IA32_X2APIC_TPR:
4718 case MSR_IA32_X2APIC_SELF_IPI:
4719 {
4720 if (u64Value & UINT64_C(0xffffffffffffff00))
4721 return VERR_OUT_OF_RANGE;
4722 break;
4723 }
4724 case MSR_IA32_X2APIC_EOI:
4725 {
4726 if (u64Value != 0)
4727 return VERR_OUT_OF_RANGE;
4728 break;
4729 }
4730 }
4731
4732 /* Write the MSR to the virtual-APIC page. */
4733 uint16_t const offReg = (idMsr & 0xff) << 4;
4734 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4735
4736 /*
4737 * Record the currently updated APIC offset, as we need this later for figuring
4738 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4739 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4740 */
4741 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4742
4743 return VINF_VMX_MODIFIES_BEHAVIOR;
4744 }
4745
4746 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4747}
4748
4749
4750/**
4751 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4752 *
4753 * @returns VBox status code.
4754 * @retval VINF_SUCCESS when the highest set bit is found.
4755 * @retval VERR_NOT_FOUND when no bit is set.
4756 *
4757 * @param pVCpu The cross context virtual CPU structure.
4758 * @param offReg The offset of the APIC 256-bit sparse register.
4759 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4760 * set in the register. Only valid when VINF_SUCCESS is
4761 * returned.
4762 *
4763 * @remarks The format of the 256-bit sparse register here mirrors that found in
4764 * real APIC hardware.
4765 */
4766static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4767{
4768 Assert(offReg < XAPIC_OFF_END + 4);
4769 Assert(pidxHighestBit);
4770 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4771
4772 /*
4773 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4774 * However, in each fragment only the first 4 bytes are used.
4775 */
4776 uint8_t const cFrags = 8;
4777 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4778 {
4779 uint16_t const offFrag = iFrag * 16;
4780 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4781 if (!u32Frag)
4782 continue;
4783
4784 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4785 Assert(idxHighestBit > 0);
4786 --idxHighestBit;
4787 Assert(idxHighestBit <= UINT8_MAX);
4788 *pidxHighestBit = idxHighestBit;
4789 return VINF_SUCCESS;
4790 }
4791 return VERR_NOT_FOUND;
4792}
4793
4794
4795/**
4796 * Evaluates pending virtual interrupts.
4797 *
4798 * @param pVCpu The cross context virtual CPU structure.
4799 */
4800IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4801{
4802 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4803 Assert(pVmcs);
4804 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4805
4806 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4807 {
4808 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4809 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4810
4811 if ((uRvi >> 4) > (uPpr >> 4))
4812 {
4813 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4814 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4815 }
4816 else
4817 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4818 }
4819}
4820
4821
4822/**
4823 * Performs PPR virtualization.
4824 *
4825 * @returns VBox strict status code.
4826 * @param pVCpu The cross context virtual CPU structure.
4827 */
4828IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4829{
4830 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4831 Assert(pVmcs);
4832 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4833 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4834
4835 /*
4836 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4837 * or EOI-virtualization.
4838 *
4839 * See Intel spec. 29.1.3 "PPR Virtualization".
4840 */
4841 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4842 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4843
4844 uint32_t uPpr;
4845 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4846 uPpr = uTpr & 0xff;
4847 else
4848 uPpr = uSvi & 0xf0;
4849
4850 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4851 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4852}
4853
4854
4855/**
4856 * Performs VMX TPR virtualization.
4857 *
4858 * @returns VBox strict status code.
4859 * @param pVCpu The cross context virtual CPU structure.
4860 */
4861IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4862{
4863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4864 Assert(pVmcs);
4865 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4866
4867 /*
4868 * We should have already performed the virtual-APIC write to the TPR offset
4869 * in the virtual-APIC page. We now perform TPR virtualization.
4870 *
4871 * See Intel spec. 29.1.2 "TPR Virtualization".
4872 */
4873 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4874 {
4875 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4876 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4877
4878 /*
4879 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4880 * See Intel spec. 29.1.2 "TPR Virtualization".
4881 */
4882 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4883 {
4884 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4885 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4886 }
4887 }
4888 else
4889 {
4890 iemVmxPprVirtualization(pVCpu);
4891 iemVmxEvalPendingVirtIntrs(pVCpu);
4892 }
4893
4894 return VINF_SUCCESS;
4895}
4896
4897
4898/**
4899 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4900 * not.
4901 *
4902 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4903 * @param pVCpu The cross context virtual CPU structure.
4904 * @param uVector The interrupt that was acknowledged using an EOI.
4905 */
4906IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4907{
4908 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4909 Assert(pVmcs);
4910 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4911
4912 if (uVector < 64)
4913 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4914 if (uVector < 128)
4915 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4916 if (uVector < 192)
4917 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4918 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4919}
4920
4921
4922/**
4923 * Performs EOI virtualization.
4924 *
4925 * @returns VBox strict status code.
4926 * @param pVCpu The cross context virtual CPU structure.
4927 */
4928IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4929{
4930 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4931 Assert(pVmcs);
4932 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4933
4934 /*
4935 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4936 * and get the next guest-interrupt that's in-service (if any).
4937 *
4938 * See Intel spec. 29.1.4 "EOI Virtualization".
4939 */
4940 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4941 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4942 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4943
4944 uint8_t uVector = uSvi;
4945 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4946
4947 uVector = 0;
4948 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4949
4950 if (uVector)
4951 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4952 else
4953 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4954
4955 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4956 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4957
4958 iemVmxPprVirtualization(pVCpu);
4959 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4960 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4961 iemVmxEvalPendingVirtIntrs(pVCpu);
4962 return VINF_SUCCESS;
4963}
4964
4965
4966/**
4967 * Performs self-IPI virtualization.
4968 *
4969 * @returns VBox strict status code.
4970 * @param pVCpu The cross context virtual CPU structure.
4971 */
4972IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4973{
4974 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4975 Assert(pVmcs);
4976 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4977
4978 /*
4979 * We should have already performed the virtual-APIC write to the self-IPI offset
4980 * in the virtual-APIC page. We now perform self-IPI virtualization.
4981 *
4982 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4983 */
4984 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4985 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4986 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4987 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4988 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4989 if (uVector > uRvi)
4990 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4991 iemVmxEvalPendingVirtIntrs(pVCpu);
4992 return VINF_SUCCESS;
4993}
4994
4995
4996/**
4997 * Performs VMX APIC-write emulation.
4998 *
4999 * @returns VBox strict status code.
5000 * @param pVCpu The cross context virtual CPU structure.
5001 */
5002IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5003{
5004 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5005 Assert(pVmcs);
5006
5007 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5008 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5009
5010 /*
5011 * Perform APIC-write emulation based on the virtual-APIC register written.
5012 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5013 */
5014 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5015 VBOXSTRICTRC rcStrict;
5016 switch (offApicWrite)
5017 {
5018 case XAPIC_OFF_TPR:
5019 {
5020 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5021 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5022 uTpr &= UINT32_C(0x000000ff);
5023 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5024 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5025 rcStrict = iemVmxTprVirtualization(pVCpu);
5026 break;
5027 }
5028
5029 case XAPIC_OFF_EOI:
5030 {
5031 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5032 {
5033 /* Clear VEOI and perform EOI virtualization. */
5034 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5035 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5036 rcStrict = iemVmxEoiVirtualization(pVCpu);
5037 }
5038 else
5039 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5040 break;
5041 }
5042
5043 case XAPIC_OFF_ICR_LO:
5044 {
5045 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5046 {
5047 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5048 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5049 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5050 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5051 if ( !(uIcrLo & fIcrLoMb0)
5052 && (uIcrLo & fIcrLoMb1))
5053 {
5054 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5055 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5056 }
5057 else
5058 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5059 }
5060 else
5061 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5062 break;
5063 }
5064
5065 case XAPIC_OFF_ICR_HI:
5066 {
5067 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5068 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5069 uIcrHi &= UINT32_C(0xff000000);
5070 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5071 rcStrict = VINF_SUCCESS;
5072 break;
5073 }
5074
5075 default:
5076 {
5077 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5078 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5079 break;
5080 }
5081 }
5082
5083 return rcStrict;
5084}
5085
5086
5087/**
5088 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5089 *
5090 * @param pVCpu The cross context virtual CPU structure.
5091 * @param pszInstr The VMX instruction name (for logging purposes).
5092 */
5093IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5094{
5095 /*
5096 * Guest Control Registers, Debug Registers, and MSRs.
5097 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5098 */
5099 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5100 const char *const pszFailure = "VM-exit";
5101 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5102
5103 /* CR0 reserved bits. */
5104 {
5105 /* CR0 MB1 bits. */
5106 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5107 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5108 if (fUnrestrictedGuest)
5109 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5110 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5111 { /* likely */ }
5112 else
5113 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5114
5115 /* CR0 MBZ bits. */
5116 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5117 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5118 { /* likely */ }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5121
5122 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5123 if ( !fUnrestrictedGuest
5124 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5125 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5127 }
5128
5129 /* CR4 reserved bits. */
5130 {
5131 /* CR4 MB1 bits. */
5132 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5133 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5134 { /* likely */ }
5135 else
5136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5137
5138 /* CR4 MBZ bits. */
5139 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5140 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5141 { /* likely */ }
5142 else
5143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5144 }
5145
5146 /* DEBUGCTL MSR. */
5147 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5148 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5152
5153 /* 64-bit CPU checks. */
5154 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5155 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5156 {
5157 if (fGstInLongMode)
5158 {
5159 /* PAE must be set. */
5160 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5161 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5165 }
5166 else
5167 {
5168 /* PCIDE should not be set. */
5169 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5173 }
5174
5175 /* CR3. */
5176 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5177 { /* likely */ }
5178 else
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5180
5181 /* DR7. */
5182 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5183 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5184 { /* likely */ }
5185 else
5186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5187
5188 /* SYSENTER ESP and SYSENTER EIP. */
5189 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5190 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5194 }
5195
5196 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5197 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5198
5199 /* PAT MSR. */
5200 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5201 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5205
5206 /* EFER MSR. */
5207 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5208 {
5209 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5210 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5211 { /* likely */ }
5212 else
5213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5214
5215 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5216 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5217 if ( fGstLma == fGstInLongMode
5218 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5219 || fGstLma == fGstLme))
5220 { /* likely */ }
5221 else
5222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5223 }
5224
5225 /* We don't support IA32_BNDCFGS MSR yet. */
5226 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5227
5228 NOREF(pszInstr);
5229 NOREF(pszFailure);
5230 return VINF_SUCCESS;
5231}
5232
5233
5234/**
5235 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5236 *
5237 * @param pVCpu The cross context virtual CPU structure.
5238 * @param pszInstr The VMX instruction name (for logging purposes).
5239 */
5240IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5241{
5242 /*
5243 * Segment registers.
5244 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5245 */
5246 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5247 const char *const pszFailure = "VM-exit";
5248 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5249 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5250 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5251
5252 /* Selectors. */
5253 if ( !fGstInV86Mode
5254 && !fUnrestrictedGuest
5255 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5257
5258 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5259 {
5260 CPUMSELREG SelReg;
5261 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5262 if (RT_LIKELY(rc == VINF_SUCCESS))
5263 { /* likely */ }
5264 else
5265 return rc;
5266
5267 /*
5268 * Virtual-8086 mode checks.
5269 */
5270 if (fGstInV86Mode)
5271 {
5272 /* Base address. */
5273 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5274 { /* likely */ }
5275 else
5276 {
5277 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5279 }
5280
5281 /* Limit. */
5282 if (SelReg.u32Limit == 0xffff)
5283 { /* likely */ }
5284 else
5285 {
5286 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5288 }
5289
5290 /* Attribute. */
5291 if (SelReg.Attr.u == 0xf3)
5292 { /* likely */ }
5293 else
5294 {
5295 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5297 }
5298
5299 /* We're done; move to checking the next segment. */
5300 continue;
5301 }
5302
5303 /* Checks done by 64-bit CPUs. */
5304 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5305 {
5306 /* Base address. */
5307 if ( iSegReg == X86_SREG_FS
5308 || iSegReg == X86_SREG_GS)
5309 {
5310 if (X86_IS_CANONICAL(SelReg.u64Base))
5311 { /* likely */ }
5312 else
5313 {
5314 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5316 }
5317 }
5318 else if (iSegReg == X86_SREG_CS)
5319 {
5320 if (!RT_HI_U32(SelReg.u64Base))
5321 { /* likely */ }
5322 else
5323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5324 }
5325 else
5326 {
5327 if ( SelReg.Attr.n.u1Unusable
5328 || !RT_HI_U32(SelReg.u64Base))
5329 { /* likely */ }
5330 else
5331 {
5332 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5334 }
5335 }
5336 }
5337
5338 /*
5339 * Checks outside Virtual-8086 mode.
5340 */
5341 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5342 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5343 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5344 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5345 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5346 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5347 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5348 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5349
5350 /* Code or usable segment. */
5351 if ( iSegReg == X86_SREG_CS
5352 || fUsable)
5353 {
5354 /* Reserved bits (bits 31:17 and bits 11:8). */
5355 if (!(SelReg.Attr.u & 0xfffe0f00))
5356 { /* likely */ }
5357 else
5358 {
5359 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5361 }
5362
5363 /* Descriptor type. */
5364 if (fCodeDataSeg)
5365 { /* likely */ }
5366 else
5367 {
5368 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5370 }
5371
5372 /* Present. */
5373 if (fPresent)
5374 { /* likely */ }
5375 else
5376 {
5377 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5379 }
5380
5381 /* Granularity. */
5382 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5383 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5384 { /* likely */ }
5385 else
5386 {
5387 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5389 }
5390 }
5391
5392 if (iSegReg == X86_SREG_CS)
5393 {
5394 /* Segment Type and DPL. */
5395 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5396 && fUnrestrictedGuest)
5397 {
5398 if (uDpl == 0)
5399 { /* likely */ }
5400 else
5401 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5402 }
5403 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5404 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5405 {
5406 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5407 if (uDpl == AttrSs.n.u2Dpl)
5408 { /* likely */ }
5409 else
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5411 }
5412 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5413 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5414 {
5415 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5416 if (uDpl <= AttrSs.n.u2Dpl)
5417 { /* likely */ }
5418 else
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5420 }
5421 else
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5423
5424 /* Def/Big. */
5425 if ( fGstInLongMode
5426 && fSegLong)
5427 {
5428 if (uDefBig == 0)
5429 { /* likely */ }
5430 else
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5432 }
5433 }
5434 else if (iSegReg == X86_SREG_SS)
5435 {
5436 /* Segment Type. */
5437 if ( !fUsable
5438 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5439 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5440 { /* likely */ }
5441 else
5442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5443
5444 /* DPL. */
5445 if (!fUnrestrictedGuest)
5446 {
5447 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5448 { /* likely */ }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5451 }
5452 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5453 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5454 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5455 {
5456 if (uDpl == 0)
5457 { /* likely */ }
5458 else
5459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5460 }
5461 }
5462 else
5463 {
5464 /* DS, ES, FS, GS. */
5465 if (fUsable)
5466 {
5467 /* Segment type. */
5468 if (uSegType & X86_SEL_TYPE_ACCESSED)
5469 { /* likely */ }
5470 else
5471 {
5472 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5474 }
5475
5476 if ( !(uSegType & X86_SEL_TYPE_CODE)
5477 || (uSegType & X86_SEL_TYPE_READ))
5478 { /* likely */ }
5479 else
5480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5481
5482 /* DPL. */
5483 if ( !fUnrestrictedGuest
5484 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5485 {
5486 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5487 { /* likely */ }
5488 else
5489 {
5490 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5492 }
5493 }
5494 }
5495 }
5496 }
5497
5498 /*
5499 * LDTR.
5500 */
5501 {
5502 CPUMSELREG Ldtr;
5503 Ldtr.Sel = pVmcs->GuestLdtr;
5504 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5505 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5506 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5507
5508 if (!Ldtr.Attr.n.u1Unusable)
5509 {
5510 /* Selector. */
5511 if (!(Ldtr.Sel & X86_SEL_LDT))
5512 { /* likely */ }
5513 else
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5515
5516 /* Base. */
5517 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5518 {
5519 if (X86_IS_CANONICAL(Ldtr.u64Base))
5520 { /* likely */ }
5521 else
5522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5523 }
5524
5525 /* Attributes. */
5526 /* Reserved bits (bits 31:17 and bits 11:8). */
5527 if (!(Ldtr.Attr.u & 0xfffe0f00))
5528 { /* likely */ }
5529 else
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5531
5532 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5533 { /* likely */ }
5534 else
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5536
5537 if (!Ldtr.Attr.n.u1DescType)
5538 { /* likely */ }
5539 else
5540 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5541
5542 if (Ldtr.Attr.n.u1Present)
5543 { /* likely */ }
5544 else
5545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5546
5547 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5548 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5549 { /* likely */ }
5550 else
5551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5552 }
5553 }
5554
5555 /*
5556 * TR.
5557 */
5558 {
5559 CPUMSELREG Tr;
5560 Tr.Sel = pVmcs->GuestTr;
5561 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5562 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5563 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5564
5565 /* Selector. */
5566 if (!(Tr.Sel & X86_SEL_LDT))
5567 { /* likely */ }
5568 else
5569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5570
5571 /* Base. */
5572 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5573 {
5574 if (X86_IS_CANONICAL(Tr.u64Base))
5575 { /* likely */ }
5576 else
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5578 }
5579
5580 /* Attributes. */
5581 /* Reserved bits (bits 31:17 and bits 11:8). */
5582 if (!(Tr.Attr.u & 0xfffe0f00))
5583 { /* likely */ }
5584 else
5585 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5586
5587 if (!Tr.Attr.n.u1Unusable)
5588 { /* likely */ }
5589 else
5590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5591
5592 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5593 || ( !fGstInLongMode
5594 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5598
5599 if (!Tr.Attr.n.u1DescType)
5600 { /* likely */ }
5601 else
5602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5603
5604 if (Tr.Attr.n.u1Present)
5605 { /* likely */ }
5606 else
5607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5608
5609 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5610 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5611 { /* likely */ }
5612 else
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5614 }
5615
5616 NOREF(pszInstr);
5617 NOREF(pszFailure);
5618 return VINF_SUCCESS;
5619}
5620
5621
5622/**
5623 * Checks guest GDTR and IDTR as part of VM-entry.
5624 *
5625 * @param pVCpu The cross context virtual CPU structure.
5626 * @param pszInstr The VMX instruction name (for logging purposes).
5627 */
5628IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5629{
5630 /*
5631 * GDTR and IDTR.
5632 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5633 */
5634 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5635 const char *const pszFailure = "VM-exit";
5636
5637 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5638 {
5639 /* Base. */
5640 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5641 { /* likely */ }
5642 else
5643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5644
5645 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5646 { /* likely */ }
5647 else
5648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5649 }
5650
5651 /* Limit. */
5652 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5653 { /* likely */ }
5654 else
5655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5656
5657 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5658 { /* likely */ }
5659 else
5660 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5661
5662 NOREF(pszInstr);
5663 NOREF(pszFailure);
5664 return VINF_SUCCESS;
5665}
5666
5667
5668/**
5669 * Checks guest RIP and RFLAGS as part of VM-entry.
5670 *
5671 * @param pVCpu The cross context virtual CPU structure.
5672 * @param pszInstr The VMX instruction name (for logging purposes).
5673 */
5674IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5675{
5676 /*
5677 * RIP and RFLAGS.
5678 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5679 */
5680 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5681 const char *const pszFailure = "VM-exit";
5682 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5683
5684 /* RIP. */
5685 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5686 {
5687 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5688 if ( !fGstInLongMode
5689 || !AttrCs.n.u1Long)
5690 {
5691 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5692 { /* likely */ }
5693 else
5694 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5695 }
5696
5697 if ( fGstInLongMode
5698 && AttrCs.n.u1Long)
5699 {
5700 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5701 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5702 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5703 { /* likely */ }
5704 else
5705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5706 }
5707 }
5708
5709 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5710 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5711 : pVmcs->u64GuestRFlags.s.Lo;
5712 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5713 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5714 { /* likely */ }
5715 else
5716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5717
5718 if ( fGstInLongMode
5719 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5720 {
5721 if (!(uGuestRFlags & X86_EFL_VM))
5722 { /* likely */ }
5723 else
5724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5725 }
5726
5727 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5728 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5729 {
5730 if (uGuestRFlags & X86_EFL_IF)
5731 { /* likely */ }
5732 else
5733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5734 }
5735
5736 NOREF(pszInstr);
5737 NOREF(pszFailure);
5738 return VINF_SUCCESS;
5739}
5740
5741
5742/**
5743 * Checks guest non-register state as part of VM-entry.
5744 *
5745 * @param pVCpu The cross context virtual CPU structure.
5746 * @param pszInstr The VMX instruction name (for logging purposes).
5747 */
5748IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5749{
5750 /*
5751 * Guest non-register state.
5752 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5753 */
5754 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5755 const char *const pszFailure = "VM-exit";
5756
5757 /*
5758 * Activity state.
5759 */
5760 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5761 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5762 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5763 { /* likely */ }
5764 else
5765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5766
5767 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5768 if ( !AttrSs.n.u2Dpl
5769 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5770 { /* likely */ }
5771 else
5772 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5773
5774 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5775 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5776 {
5777 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5778 { /* likely */ }
5779 else
5780 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5781 }
5782
5783 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5784 {
5785 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5786 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5787 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5788 switch (pVmcs->u32GuestActivityState)
5789 {
5790 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5791 {
5792 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5793 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5794 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5795 && ( uVector == X86_XCPT_DB
5796 || uVector == X86_XCPT_MC))
5797 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5798 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5799 { /* likely */ }
5800 else
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5802 break;
5803 }
5804
5805 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5806 {
5807 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5808 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5809 && uVector == X86_XCPT_MC))
5810 { /* likely */ }
5811 else
5812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5813 break;
5814 }
5815
5816 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5817 default:
5818 break;
5819 }
5820 }
5821
5822 /*
5823 * Interruptibility state.
5824 */
5825 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5826 { /* likely */ }
5827 else
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5829
5830 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5831 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5835
5836 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5837 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5838 { /* likely */ }
5839 else
5840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5841
5842 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5843 {
5844 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5845 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5846 {
5847 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5851 }
5852 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5853 {
5854 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5855 { /* likely */ }
5856 else
5857 {
5858 /*
5859 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5860 * We update the Exit qualification only when blocking-by-STI is set
5861 * without blocking-by-MovSS being set. Although in practise it does not
5862 * make much difference since the order of checks are implementation defined.
5863 */
5864 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5865 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5867 }
5868
5869 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5870 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5871 { /* likely */ }
5872 else
5873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5874 }
5875 }
5876
5877 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5878 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5882
5883 /* We don't support SGX yet. So enclave-interruption must not be set. */
5884 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5885 { /* likely */ }
5886 else
5887 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5888
5889 /*
5890 * Pending debug exceptions.
5891 */
5892 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5893 ? pVmcs->u64GuestPendingDbgXcpt.u
5894 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5895 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5896 { /* likely */ }
5897 else
5898 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5899
5900 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5901 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5902 {
5903 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5904 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5905 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5907
5908 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5909 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5910 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5912 }
5913
5914 /* We don't support RTM (Real-time Transactional Memory) yet. */
5915 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5916 { /* likely */ }
5917 else
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5919
5920 /*
5921 * VMCS link pointer.
5922 */
5923 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5924 {
5925 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5926 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5927 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5928 { /* likely */ }
5929 else
5930 {
5931 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5933 }
5934
5935 /* Validate the address. */
5936 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5937 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5938 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5939 { /* likely */ }
5940 else
5941 {
5942 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5943 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5944 }
5945
5946 /* Read the VMCS-link pointer from guest memory. */
5947 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5948 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5949 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5950 if (RT_SUCCESS(rc))
5951 { /* likely */ }
5952 else
5953 {
5954 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5956 }
5957
5958 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5959 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5960 { /* likely */ }
5961 else
5962 {
5963 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5965 }
5966
5967 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5968 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5969 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5970 { /* likely */ }
5971 else
5972 {
5973 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5975 }
5976
5977 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5978 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5979 }
5980
5981 NOREF(pszInstr);
5982 NOREF(pszFailure);
5983 return VINF_SUCCESS;
5984}
5985
5986
5987/**
5988 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5989 * VM-entry.
5990 *
5991 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5992 * @param pVCpu The cross context virtual CPU structure.
5993 * @param pszInstr The VMX instruction name (for logging purposes).
5994 * @param pVmcs Pointer to the virtual VMCS.
5995 */
5996IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5997{
5998 /*
5999 * Check PDPTEs.
6000 * See Intel spec. 4.4.1 "PDPTE Registers".
6001 */
6002 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6003 const char *const pszFailure = "VM-exit";
6004
6005 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6006 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6007 if (RT_SUCCESS(rc))
6008 {
6009 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6010 {
6011 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6012 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6013 { /* likely */ }
6014 else
6015 {
6016 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6017 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6019 }
6020 }
6021 }
6022 else
6023 {
6024 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6026 }
6027
6028 NOREF(pszFailure);
6029 NOREF(pszInstr);
6030 return rc;
6031}
6032
6033
6034/**
6035 * Checks guest PDPTEs as part of VM-entry.
6036 *
6037 * @param pVCpu The cross context virtual CPU structure.
6038 * @param pszInstr The VMX instruction name (for logging purposes).
6039 */
6040IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6041{
6042 /*
6043 * Guest PDPTEs.
6044 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6045 */
6046 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6047 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6048
6049 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6050 int rc;
6051 if ( !fGstInLongMode
6052 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6053 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6054 {
6055 /*
6056 * We don't support nested-paging for nested-guests yet.
6057 *
6058 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6059 * rather we need to check the PDPTEs referenced by the guest CR3.
6060 */
6061 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6062 }
6063 else
6064 rc = VINF_SUCCESS;
6065 return rc;
6066}
6067
6068
6069/**
6070 * Checks guest-state as part of VM-entry.
6071 *
6072 * @returns VBox status code.
6073 * @param pVCpu The cross context virtual CPU structure.
6074 * @param pszInstr The VMX instruction name (for logging purposes).
6075 */
6076IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6077{
6078 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6079 if (RT_SUCCESS(rc))
6080 {
6081 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6082 if (RT_SUCCESS(rc))
6083 {
6084 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6085 if (RT_SUCCESS(rc))
6086 {
6087 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6088 if (RT_SUCCESS(rc))
6089 {
6090 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6091 if (RT_SUCCESS(rc))
6092 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6093 }
6094 }
6095 }
6096 }
6097 return rc;
6098}
6099
6100
6101/**
6102 * Checks host-state as part of VM-entry.
6103 *
6104 * @returns VBox status code.
6105 * @param pVCpu The cross context virtual CPU structure.
6106 * @param pszInstr The VMX instruction name (for logging purposes).
6107 */
6108IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6109{
6110 /*
6111 * Host Control Registers and MSRs.
6112 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6113 */
6114 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6115 const char * const pszFailure = "VMFail";
6116
6117 /* CR0 reserved bits. */
6118 {
6119 /* CR0 MB1 bits. */
6120 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6121 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6122 { /* likely */ }
6123 else
6124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6125
6126 /* CR0 MBZ bits. */
6127 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6128 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6129 { /* likely */ }
6130 else
6131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6132 }
6133
6134 /* CR4 reserved bits. */
6135 {
6136 /* CR4 MB1 bits. */
6137 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6138 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6142
6143 /* CR4 MBZ bits. */
6144 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6145 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6149 }
6150
6151 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6152 {
6153 /* CR3 reserved bits. */
6154 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6158
6159 /* SYSENTER ESP and SYSENTER EIP. */
6160 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6161 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6165 }
6166
6167 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6168 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6169
6170 /* PAT MSR. */
6171 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6172 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6176
6177 /* EFER MSR. */
6178 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6179 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6180 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6181 { /* likely */ }
6182 else
6183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6184
6185 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6186 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6187 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6188 if ( fHostInLongMode == fHostLma
6189 && fHostInLongMode == fHostLme)
6190 { /* likely */ }
6191 else
6192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6193
6194 /*
6195 * Host Segment and Descriptor-Table Registers.
6196 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6197 */
6198 /* Selector RPL and TI. */
6199 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6200 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6201 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6202 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6203 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6204 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6205 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6209
6210 /* CS and TR selectors cannot be 0. */
6211 if ( pVmcs->HostCs
6212 && pVmcs->HostTr)
6213 { /* likely */ }
6214 else
6215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6216
6217 /* SS cannot be 0 if 32-bit host. */
6218 if ( fHostInLongMode
6219 || pVmcs->HostSs)
6220 { /* likely */ }
6221 else
6222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6223
6224 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6225 {
6226 /* FS, GS, GDTR, IDTR, TR base address. */
6227 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6228 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6229 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6230 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6231 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6232 { /* likely */ }
6233 else
6234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6235 }
6236
6237 /*
6238 * Host address-space size for 64-bit CPUs.
6239 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6240 */
6241 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6242 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6243 {
6244 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6245
6246 /* Logical processor in IA-32e mode. */
6247 if (fCpuInLongMode)
6248 {
6249 if (fHostInLongMode)
6250 {
6251 /* PAE must be set. */
6252 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6256
6257 /* RIP must be canonical. */
6258 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6259 { /* likely */ }
6260 else
6261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6262 }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6265 }
6266 else
6267 {
6268 /* Logical processor is outside IA-32e mode. */
6269 if ( !fGstInLongMode
6270 && !fHostInLongMode)
6271 {
6272 /* PCIDE should not be set. */
6273 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6274 { /* likely */ }
6275 else
6276 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6277
6278 /* The high 32-bits of RIP MBZ. */
6279 if (!pVmcs->u64HostRip.s.Hi)
6280 { /* likely */ }
6281 else
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6283 }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6286 }
6287 }
6288 else
6289 {
6290 /* Host address-space size for 32-bit CPUs. */
6291 if ( !fGstInLongMode
6292 && !fHostInLongMode)
6293 { /* likely */ }
6294 else
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6296 }
6297
6298 NOREF(pszInstr);
6299 NOREF(pszFailure);
6300 return VINF_SUCCESS;
6301}
6302
6303
6304/**
6305 * Checks VM-entry controls fields as part of VM-entry.
6306 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6307 *
6308 * @returns VBox status code.
6309 * @param pVCpu The cross context virtual CPU structure.
6310 * @param pszInstr The VMX instruction name (for logging purposes).
6311 */
6312IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6313{
6314 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6315 const char * const pszFailure = "VMFail";
6316
6317 /* VM-entry controls. */
6318 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6319 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6323
6324 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6328
6329 /* Event injection. */
6330 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6331 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6332 {
6333 /* Type and vector. */
6334 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6335 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6336 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6337 if ( !uRsvd
6338 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6339 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6340 { /* likely */ }
6341 else
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6343
6344 /* Exception error code. */
6345 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6346 {
6347 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6348 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6349 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6353
6354 /* Exceptions that provide an error code. */
6355 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6356 && ( uVector == X86_XCPT_DF
6357 || uVector == X86_XCPT_TS
6358 || uVector == X86_XCPT_NP
6359 || uVector == X86_XCPT_SS
6360 || uVector == X86_XCPT_GP
6361 || uVector == X86_XCPT_PF
6362 || uVector == X86_XCPT_AC))
6363 { /* likely */ }
6364 else
6365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6366
6367 /* Exception error-code reserved bits. */
6368 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6369 { /* likely */ }
6370 else
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6372
6373 /* Injecting a software interrupt, software exception or privileged software exception. */
6374 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6375 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6376 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6377 {
6378 /* Instruction length must be in the range 0-15. */
6379 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6380 { /* likely */ }
6381 else
6382 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6383
6384 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6385 if ( pVmcs->u32EntryInstrLen == 0
6386 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6388 }
6389 }
6390 }
6391
6392 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6393 if (pVmcs->u32EntryMsrLoadCount)
6394 {
6395 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6396 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6397 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6398 { /* likely */ }
6399 else
6400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6401 }
6402
6403 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6404 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6405
6406 NOREF(pszInstr);
6407 NOREF(pszFailure);
6408 return VINF_SUCCESS;
6409}
6410
6411
6412/**
6413 * Checks VM-exit controls fields as part of VM-entry.
6414 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6415 *
6416 * @returns VBox status code.
6417 * @param pVCpu The cross context virtual CPU structure.
6418 * @param pszInstr The VMX instruction name (for logging purposes).
6419 */
6420IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6421{
6422 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6423 const char * const pszFailure = "VMFail";
6424
6425 /* VM-exit controls. */
6426 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6427 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6428 { /* likely */ }
6429 else
6430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6431
6432 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6433 { /* likely */ }
6434 else
6435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6436
6437 /* Save preemption timer without activating it. */
6438 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6439 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6440 { /* likely */ }
6441 else
6442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6443
6444 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6445 if (pVmcs->u32ExitMsrStoreCount)
6446 {
6447 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6448 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6449 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6450 { /* likely */ }
6451 else
6452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6453 }
6454
6455 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6456 if (pVmcs->u32ExitMsrLoadCount)
6457 {
6458 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6459 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6460 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6461 { /* likely */ }
6462 else
6463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6464 }
6465
6466 NOREF(pszInstr);
6467 NOREF(pszFailure);
6468 return VINF_SUCCESS;
6469}
6470
6471
6472/**
6473 * Checks VM-execution controls fields as part of VM-entry.
6474 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6475 *
6476 * @returns VBox status code.
6477 * @param pVCpu The cross context virtual CPU structure.
6478 * @param pszInstr The VMX instruction name (for logging purposes).
6479 *
6480 * @remarks This may update secondary-processor based VM-execution control fields
6481 * in the current VMCS if necessary.
6482 */
6483IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6484{
6485 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6486 const char * const pszFailure = "VMFail";
6487
6488 /* Pin-based VM-execution controls. */
6489 {
6490 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6491 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6492 { /* likely */ }
6493 else
6494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6495
6496 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6497 { /* likely */ }
6498 else
6499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6500 }
6501
6502 /* Processor-based VM-execution controls. */
6503 {
6504 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6505 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6506 { /* likely */ }
6507 else
6508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6509
6510 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6511 { /* likely */ }
6512 else
6513 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6514 }
6515
6516 /* Secondary processor-based VM-execution controls. */
6517 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6518 {
6519 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6520 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6521 { /* likely */ }
6522 else
6523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6524
6525 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6526 { /* likely */ }
6527 else
6528 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6529 }
6530 else
6531 Assert(!pVmcs->u32ProcCtls2);
6532
6533 /* CR3-target count. */
6534 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6538
6539 /* I/O bitmaps physical addresses. */
6540 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6541 {
6542 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6543 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6544 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6545 { /* likely */ }
6546 else
6547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6548
6549 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6550 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6551 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6552 { /* likely */ }
6553 else
6554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6555 }
6556
6557 /* MSR bitmap physical address. */
6558 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6559 {
6560 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6561 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6562 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6563 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6564 { /* likely */ }
6565 else
6566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6567
6568 /* Read the MSR bitmap. */
6569 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6570 * implementing fast path. */
6571 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6572 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6573 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6574 if (RT_SUCCESS(rc))
6575 { /* likely */ }
6576 else
6577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6578 }
6579
6580 /* TPR shadow related controls. */
6581 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6582 {
6583 /* Virtual-APIC page physical address. */
6584 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6585 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6586 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6587 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6588 { /* likely */ }
6589 else
6590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6591
6592 /* TPR threshold without virtual-interrupt delivery. */
6593 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6594 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6596
6597 /* TPR threshold and VTPR. */
6598 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6599 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6600 {
6601 /* Read the VTPR from the virtual-APIC page. */
6602 uint8_t u8VTpr;
6603 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6604 if (RT_SUCCESS(rc))
6605 { /* likely */ }
6606 else
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6608
6609 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6610 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6611 { /* likely */ }
6612 else
6613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6614 }
6615 }
6616 else
6617 {
6618 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6619 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6620 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6621 { /* likely */ }
6622 else
6623 {
6624 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6626 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6628 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6630 }
6631 }
6632
6633 /* NMI exiting and virtual-NMIs. */
6634 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6635 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6636 { /* likely */ }
6637 else
6638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6639
6640 /* Virtual-NMIs and NMI-window exiting. */
6641 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6642 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6643 { /* likely */ }
6644 else
6645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6646
6647 /* Virtualize APIC accesses. */
6648 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6649 {
6650 /* APIC-access physical address. */
6651 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6652 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6653 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6654 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6655 { /* likely */ }
6656 else
6657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6658
6659 /*
6660 * Disallow APIC-access page and virtual-APIC page from being the same address.
6661 * Note! This is not an Intel requirement, but one imposed by our implementation.
6662 */
6663 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6664 * redirecting accesses between the APIC-access page and the virtual-APIC
6665 * page. If any nested hypervisor requires this, we can implement it later. */
6666 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6667 {
6668 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6669 if (GCPhysVirtApic != GCPhysApicAccess)
6670 { /* likely */ }
6671 else
6672 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6673 }
6674
6675 /*
6676 * Register the handler for the APIC-access page.
6677 *
6678 * We don't deregister the APIC-access page handler during the VM-exit as a different
6679 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6680 *
6681 * We leave the page registered until the first access that happens outside VMX non-root
6682 * mode. Guest software is allowed to access structures such as the APIC-access page
6683 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6684 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6685 *
6686 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6687 */
6688 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6689 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6690 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6691 if (RT_SUCCESS(rc))
6692 { /* likely */ }
6693 else
6694 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6695 }
6696
6697 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6698 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6699 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6700 { /* likely */ }
6701 else
6702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6703
6704 /* Virtual-interrupt delivery requires external interrupt exiting. */
6705 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6706 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6710
6711 /* VPID. */
6712 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6713 || pVmcs->u16Vpid != 0)
6714 { /* likely */ }
6715 else
6716 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6717
6718 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6719 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6720 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6721 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6722 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6723 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6724 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6725
6726 /* VMCS shadowing. */
6727 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6728 {
6729 /* VMREAD-bitmap physical address. */
6730 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6731 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6732 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6733 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6734 { /* likely */ }
6735 else
6736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6737
6738 /* VMWRITE-bitmap physical address. */
6739 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6740 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6741 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6742 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6743 { /* likely */ }
6744 else
6745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6746
6747 /* Read the VMREAD-bitmap. */
6748 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6749 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6750 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6751 if (RT_SUCCESS(rc))
6752 { /* likely */ }
6753 else
6754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6755
6756 /* Read the VMWRITE-bitmap. */
6757 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6758 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6759 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6760 if (RT_SUCCESS(rc))
6761 { /* likely */ }
6762 else
6763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6764 }
6765
6766 NOREF(pszInstr);
6767 NOREF(pszFailure);
6768 return VINF_SUCCESS;
6769}
6770
6771
6772/**
6773 * Loads the guest control registers, debug register and some MSRs as part of
6774 * VM-entry.
6775 *
6776 * @param pVCpu The cross context virtual CPU structure.
6777 */
6778IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6779{
6780 /*
6781 * Load guest control registers, debug registers and MSRs.
6782 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6783 */
6784 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6785
6786 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6787 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6788 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6789 CPUMSetGuestCR0(pVCpu, uGstCr0);
6790 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6791 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6792
6793 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6794 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6795
6796 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6797 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6798 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6799
6800 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6801 {
6802 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6803
6804 /* EFER MSR. */
6805 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6806 {
6807 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6808 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6809 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6810 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6811 if (fGstInLongMode)
6812 {
6813 /* If the nested-guest is in long mode, LMA and LME are both set. */
6814 Assert(fGstPaging);
6815 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6816 }
6817 else
6818 {
6819 /*
6820 * If the nested-guest is outside long mode:
6821 * - With paging: LMA is cleared, LME is cleared.
6822 * - Without paging: LMA is cleared, LME is left unmodified.
6823 */
6824 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6825 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6826 }
6827 }
6828 /* else: see below. */
6829 }
6830
6831 /* PAT MSR. */
6832 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6833 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6834
6835 /* EFER MSR. */
6836 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6837 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6838
6839 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6840 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6841
6842 /* We don't support IA32_BNDCFGS MSR yet. */
6843 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6844
6845 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6846}
6847
6848
6849/**
6850 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6851 *
6852 * @param pVCpu The cross context virtual CPU structure.
6853 */
6854IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6855{
6856 /*
6857 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6858 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6859 */
6860 /* CS, SS, ES, DS, FS, GS. */
6861 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6862 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6863 {
6864 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6865 CPUMSELREG VmcsSelReg;
6866 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6867 AssertRC(rc); NOREF(rc);
6868 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6869 {
6870 pGstSelReg->Sel = VmcsSelReg.Sel;
6871 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6872 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6873 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6874 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6875 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6876 }
6877 else
6878 {
6879 pGstSelReg->Sel = VmcsSelReg.Sel;
6880 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6881 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6882 switch (iSegReg)
6883 {
6884 case X86_SREG_CS:
6885 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6886 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6887 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6888 break;
6889
6890 case X86_SREG_SS:
6891 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6892 pGstSelReg->u32Limit = 0;
6893 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6894 break;
6895
6896 case X86_SREG_ES:
6897 case X86_SREG_DS:
6898 pGstSelReg->u64Base = 0;
6899 pGstSelReg->u32Limit = 0;
6900 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6901 break;
6902
6903 case X86_SREG_FS:
6904 case X86_SREG_GS:
6905 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6906 pGstSelReg->u32Limit = 0;
6907 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6908 break;
6909 }
6910 Assert(pGstSelReg->Attr.n.u1Unusable);
6911 }
6912 }
6913
6914 /* LDTR. */
6915 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6916 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6917 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6918 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6919 {
6920 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6921 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6922 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6923 }
6924 else
6925 {
6926 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6927 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6928 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6929 }
6930
6931 /* TR. */
6932 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6933 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6934 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6935 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6936 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6937 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6938 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6939
6940 /* GDTR. */
6941 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6942 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6943
6944 /* IDTR. */
6945 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6946 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6947}
6948
6949
6950/**
6951 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6952 *
6953 * @returns VBox status code.
6954 * @param pVCpu The cross context virtual CPU structure.
6955 * @param pszInstr The VMX instruction name (for logging purposes).
6956 */
6957IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6958{
6959 /*
6960 * Load guest MSRs.
6961 * See Intel spec. 26.4 "Loading MSRs".
6962 */
6963 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6964 const char *const pszFailure = "VM-exit";
6965
6966 /*
6967 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6968 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6969 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6970 */
6971 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6972 if (!cMsrs)
6973 return VINF_SUCCESS;
6974
6975 /*
6976 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6977 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6978 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6979 */
6980 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6981 if (fIsMsrCountValid)
6982 { /* likely */ }
6983 else
6984 {
6985 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6987 }
6988
6989 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6990 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6991 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6992 if (RT_SUCCESS(rc))
6993 {
6994 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6995 Assert(pMsr);
6996 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6997 {
6998 if ( !pMsr->u32Reserved
6999 && pMsr->u32Msr != MSR_K8_FS_BASE
7000 && pMsr->u32Msr != MSR_K8_GS_BASE
7001 && pMsr->u32Msr != MSR_K6_EFER
7002 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7003 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7004 {
7005 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7006 if (rcStrict == VINF_SUCCESS)
7007 continue;
7008
7009 /*
7010 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7011 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7012 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7013 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7014 * MSR in ring-0 if possible, or come up with a better, generic solution.
7015 */
7016 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7017 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7018 ? kVmxVDiag_Vmentry_MsrLoadRing3
7019 : kVmxVDiag_Vmentry_MsrLoad;
7020 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7021 }
7022 else
7023 {
7024 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7026 }
7027 }
7028 }
7029 else
7030 {
7031 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7033 }
7034
7035 NOREF(pszInstr);
7036 NOREF(pszFailure);
7037 return VINF_SUCCESS;
7038}
7039
7040
7041/**
7042 * Loads the guest-state non-register state as part of VM-entry.
7043 *
7044 * @returns VBox status code.
7045 * @param pVCpu The cross context virtual CPU structure.
7046 *
7047 * @remarks This must be called only after loading the nested-guest register state
7048 * (especially nested-guest RIP).
7049 */
7050IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7051{
7052 /*
7053 * Load guest non-register state.
7054 * See Intel spec. 26.6 "Special Features of VM Entry"
7055 */
7056 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7057
7058 /*
7059 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7060 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7061 *
7062 * See Intel spec. 26.6.1 "Interruptibility State".
7063 */
7064 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7065 if ( !fEntryVectoring
7066 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7067 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7068 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7069 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7070
7071 /* NMI blocking. */
7072 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7073 {
7074 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7075 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7076 else
7077 {
7078 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7079 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7080 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7081 }
7082 }
7083 else
7084 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7085
7086 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7087
7088 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7089 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7090
7091 /* VPID is irrelevant. We don't support VPID yet. */
7092
7093 /* Clear address-range monitoring. */
7094 EMMonitorWaitClear(pVCpu);
7095}
7096
7097
7098/**
7099 * Loads the guest-state as part of VM-entry.
7100 *
7101 * @returns VBox status code.
7102 * @param pVCpu The cross context virtual CPU structure.
7103 * @param pszInstr The VMX instruction name (for logging purposes).
7104 *
7105 * @remarks This must be done after all the necessary steps prior to loading of
7106 * guest-state (e.g. checking various VMCS state).
7107 */
7108IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7109{
7110 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7111 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7112
7113 /*
7114 * Load guest RIP, RSP and RFLAGS.
7115 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7116 */
7117 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7118 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7119 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7120 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7121
7122 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7123 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7124 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7125
7126 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7127
7128 NOREF(pszInstr);
7129 return VINF_SUCCESS;
7130}
7131
7132
7133/**
7134 * Returns whether there are is a pending debug exception on VM-entry.
7135 *
7136 * @param pVCpu The cross context virtual CPU structure.
7137 * @param pszInstr The VMX instruction name (for logging purposes).
7138 */
7139IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7140{
7141 /*
7142 * Pending debug exceptions.
7143 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7144 */
7145 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7146 Assert(pVmcs);
7147
7148 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7149 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7150 if (fPendingDbgXcpt)
7151 {
7152 uint8_t uEntryIntInfoType;
7153 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7154 if (fEntryVectoring)
7155 {
7156 switch (uEntryIntInfoType)
7157 {
7158 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7159 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7160 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7161 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7162 fPendingDbgXcpt = false;
7163 break;
7164
7165 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7166 {
7167 /*
7168 * Whether the pending debug exception for software exceptions other than
7169 * #BP and #OF is delivered after injecting the exception or is discard
7170 * is CPU implementation specific. We will discard them (easier).
7171 */
7172 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7173 if ( uVector != X86_XCPT_BP
7174 && uVector != X86_XCPT_OF)
7175 fPendingDbgXcpt = false;
7176 RT_FALL_THRU();
7177 }
7178 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7179 {
7180 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7181 fPendingDbgXcpt = false;
7182 break;
7183 }
7184 }
7185 }
7186 else
7187 {
7188 /*
7189 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7190 * pending debug exception is held pending or is discarded is CPU implementation
7191 * specific. We will discard them (easier).
7192 */
7193 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7194 fPendingDbgXcpt = false;
7195
7196 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7197 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7198 fPendingDbgXcpt = false;
7199 }
7200 }
7201
7202 NOREF(pszInstr);
7203 return fPendingDbgXcpt;
7204}
7205
7206
7207/**
7208 * Set up the monitor-trap flag (MTF).
7209 *
7210 * @param pVCpu The cross context virtual CPU structure.
7211 * @param pszInstr The VMX instruction name (for logging purposes).
7212 */
7213IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7214{
7215 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7216 Assert(pVmcs);
7217 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7218 {
7219 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7220 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7221 }
7222 else
7223 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7224 NOREF(pszInstr);
7225}
7226
7227
7228/**
7229 * Sets up NMI-window exiting.
7230 *
7231 * @param pVCpu The cross context virtual CPU structure.
7232 * @param pszInstr The VMX instruction name (for logging purposes).
7233 */
7234IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
7235{
7236 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7237 Assert(pVmcs);
7238 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7239 {
7240 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7241 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7242 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7243 }
7244 else
7245 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7246 NOREF(pszInstr);
7247}
7248
7249
7250/**
7251 * Sets up interrupt-window exiting.
7252 *
7253 * @param pVCpu The cross context virtual CPU structure.
7254 * @param pszInstr The VMX instruction name (for logging purposes).
7255 */
7256IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7257{
7258 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7259 Assert(pVmcs);
7260 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7261 {
7262 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7263 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7264 }
7265 else
7266 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7267 NOREF(pszInstr);
7268}
7269
7270
7271/**
7272 * Set up the VMX-preemption timer.
7273 *
7274 * @param pVCpu The cross context virtual CPU structure.
7275 * @param pszInstr The VMX instruction name (for logging purposes).
7276 */
7277IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7278{
7279 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7280 Assert(pVmcs);
7281 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7282 {
7283 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7284 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7285 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7286
7287 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7288 }
7289 else
7290 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7291
7292 NOREF(pszInstr);
7293}
7294
7295
7296/**
7297 * Injects an event using TRPM given a VM-entry interruption info. and related
7298 * fields.
7299 *
7300 * @returns VBox status code.
7301 * @param pVCpu The cross context virtual CPU structure.
7302 * @param uEntryIntInfo The VM-entry interruption info.
7303 * @param uErrCode The error code associated with the event if any.
7304 * @param cbInstr The VM-entry instruction length (for software
7305 * interrupts and software exceptions). Pass 0
7306 * otherwise.
7307 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7308 */
7309IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7310 RTGCUINTPTR GCPtrFaultAddress)
7311{
7312 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7313
7314 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7315 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7316 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7317
7318 TRPMEVENT enmTrapType;
7319 switch (uType)
7320 {
7321 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7322 enmTrapType = TRPM_HARDWARE_INT;
7323 break;
7324
7325 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7326 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7327 enmTrapType = TRPM_TRAP;
7328 break;
7329
7330 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7331 enmTrapType = TRPM_SOFTWARE_INT;
7332 break;
7333
7334 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7335 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7336 enmTrapType = TRPM_SOFTWARE_INT;
7337 break;
7338
7339 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7340 Assert(uVector == X86_XCPT_DB);
7341 enmTrapType = TRPM_SOFTWARE_INT;
7342 break;
7343
7344 default:
7345 /* Shouldn't really happen. */
7346 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7347 break;
7348 }
7349
7350 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7351 AssertRCReturn(rc, rc);
7352
7353 if (fErrCodeValid)
7354 TRPMSetErrorCode(pVCpu, uErrCode);
7355
7356 if ( enmTrapType == TRPM_TRAP
7357 && uVector == X86_XCPT_PF)
7358 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7359 else if (enmTrapType == TRPM_SOFTWARE_INT)
7360 TRPMSetInstrLength(pVCpu, cbInstr);
7361
7362 return VINF_SUCCESS;
7363}
7364
7365
7366/**
7367 * Performs event injection (if any) as part of VM-entry.
7368 *
7369 * @param pVCpu The cross context virtual CPU structure.
7370 * @param pszInstr The VMX instruction name (for logging purposes).
7371 */
7372IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7373{
7374 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7375
7376 /*
7377 * Inject events.
7378 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7379 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7380 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7381 * the actually delivery of this event.
7382 *
7383 * See Intel spec. 26.5 "Event Injection".
7384 */
7385 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7386 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7387
7388 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7389 if (fEntryIntInfoValid)
7390 {
7391 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7392 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7393 {
7394 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7395 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7396 return VINF_SUCCESS;
7397 }
7398
7399 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7400 pVCpu->cpum.GstCtx.cr2);
7401 if (RT_SUCCESS(rc))
7402 {
7403 /*
7404 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7405 *
7406 * However, we do it here on VM-entry because while it continues to not be visible to
7407 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7408 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7409 * information field.
7410 *
7411 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7412 */
7413 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7414 }
7415 return rc;
7416 }
7417
7418 /*
7419 * Inject any pending guest debug exception.
7420 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7421 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7422 */
7423 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7424 if (fPendingDbgXcpt)
7425 {
7426 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7427 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7428 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7429 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7430 0 /* GCPtrFaultAddress */);
7431 }
7432
7433 NOREF(pszInstr);
7434 return VINF_SUCCESS;
7435}
7436
7437
7438/**
7439 * Initializes all read-only VMCS fields as part of VM-entry.
7440 *
7441 * @param pVCpu The cross context virtual CPU structure.
7442 */
7443IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7444{
7445 /*
7446 * Any VMCS field which we do not establish on every VM-exit but may potentially
7447 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7448 * specified to be undefined needs to be initialized here.
7449 *
7450 * Thus, it is especially important to clear the Exit qualification field
7451 * since it must be zero for VM-exits where it is not used. Similarly, the
7452 * VM-exit interruption information field's valid bit needs to be cleared for
7453 * the same reasons.
7454 */
7455 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7456 Assert(pVmcs);
7457
7458 /* 16-bit (none currently). */
7459 /* 32-bit. */
7460 pVmcs->u32RoVmInstrError = 0;
7461 pVmcs->u32RoExitReason = 0;
7462 pVmcs->u32RoExitIntInfo = 0;
7463 pVmcs->u32RoExitIntErrCode = 0;
7464 pVmcs->u32RoIdtVectoringInfo = 0;
7465 pVmcs->u32RoIdtVectoringErrCode = 0;
7466 pVmcs->u32RoExitInstrLen = 0;
7467 pVmcs->u32RoExitInstrInfo = 0;
7468
7469 /* 64-bit. */
7470 pVmcs->u64RoGuestPhysAddr.u = 0;
7471
7472 /* Natural-width. */
7473 pVmcs->u64RoExitQual.u = 0;
7474 pVmcs->u64RoIoRcx.u = 0;
7475 pVmcs->u64RoIoRsi.u = 0;
7476 pVmcs->u64RoIoRdi.u = 0;
7477 pVmcs->u64RoIoRip.u = 0;
7478 pVmcs->u64RoGuestLinearAddr.u = 0;
7479}
7480
7481
7482/**
7483 * VMLAUNCH/VMRESUME instruction execution worker.
7484 *
7485 * @returns Strict VBox status code.
7486 * @param pVCpu The cross context virtual CPU structure.
7487 * @param cbInstr The instruction length in bytes.
7488 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7489 * VMXINSTRID_VMRESUME).
7490 *
7491 * @remarks Common VMX instruction checks are already expected to by the caller,
7492 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7493 */
7494IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7495{
7496# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7497 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7498 return VINF_EM_RAW_EMULATE_INSTR;
7499# else
7500 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7501 || uInstrId == VMXINSTRID_VMRESUME);
7502 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7503
7504 /* Nested-guest intercept. */
7505 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7506 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7507
7508 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7509
7510 /*
7511 * Basic VM-entry checks.
7512 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7513 * The checks following that do not have to follow a specific order.
7514 *
7515 * See Intel spec. 26.1 "Basic VM-entry Checks".
7516 */
7517
7518 /* CPL. */
7519 if (pVCpu->iem.s.uCpl == 0)
7520 { /* likely */ }
7521 else
7522 {
7523 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7525 return iemRaiseGeneralProtectionFault0(pVCpu);
7526 }
7527
7528 /* Current VMCS valid. */
7529 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7530 { /* likely */ }
7531 else
7532 {
7533 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7534 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7535 iemVmxVmFailInvalid(pVCpu);
7536 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7537 return VINF_SUCCESS;
7538 }
7539
7540 /* Current VMCS is not a shadow VMCS. */
7541 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7542 { /* likely */ }
7543 else
7544 {
7545 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7547 iemVmxVmFailInvalid(pVCpu);
7548 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7549 return VINF_SUCCESS;
7550 }
7551
7552 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7553 * use block-by-STI here which is not quite correct. */
7554 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7555 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7556 { /* likely */ }
7557 else
7558 {
7559 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7560 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7561 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7562 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7563 return VINF_SUCCESS;
7564 }
7565
7566 if (uInstrId == VMXINSTRID_VMLAUNCH)
7567 {
7568 /* VMLAUNCH with non-clear VMCS. */
7569 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7570 { /* likely */ }
7571 else
7572 {
7573 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7574 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7575 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7576 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7577 return VINF_SUCCESS;
7578 }
7579 }
7580 else
7581 {
7582 /* VMRESUME with non-launched VMCS. */
7583 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7584 { /* likely */ }
7585 else
7586 {
7587 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7588 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7589 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7590 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7591 return VINF_SUCCESS;
7592 }
7593 }
7594
7595 /*
7596 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7597 * while entering VMX non-root mode. We do some of this while checking VM-execution
7598 * controls. The guest hypervisor should not make assumptions and cannot expect
7599 * predictable behavior if changes to these structures are made in guest memory while
7600 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7601 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7602 *
7603 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7604 */
7605 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7606 Assert(pVmcs);
7607 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7608
7609 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7610 if (RT_SUCCESS(rc))
7611 {
7612 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7613 if (RT_SUCCESS(rc))
7614 {
7615 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7616 if (RT_SUCCESS(rc))
7617 {
7618 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7619 if (RT_SUCCESS(rc))
7620 {
7621 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7622 iemVmxVmentryInitReadOnlyFields(pVCpu);
7623
7624 /*
7625 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7626 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7627 * VM-exit when required.
7628 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7629 */
7630 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7631
7632 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7633 if (RT_SUCCESS(rc))
7634 {
7635 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7636 if (RT_SUCCESS(rc))
7637 {
7638 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7639 if (RT_SUCCESS(rc))
7640 {
7641 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7642
7643 /* VMLAUNCH instruction must update the VMCS launch state. */
7644 if (uInstrId == VMXINSTRID_VMLAUNCH)
7645 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7646
7647 /* Perform the VMX transition (PGM updates). */
7648 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7649 if (rcStrict == VINF_SUCCESS)
7650 { /* likely */ }
7651 else if (RT_SUCCESS(rcStrict))
7652 {
7653 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7654 VBOXSTRICTRC_VAL(rcStrict)));
7655 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7656 }
7657 else
7658 {
7659 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7660 return rcStrict;
7661 }
7662
7663 /* We've now entered nested-guest execution. */
7664 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7665
7666 /*
7667 * The priority of potential VM-exits during VM-entry is important.
7668 * The priorities of VM-exits and events are listed from highest
7669 * to lowest as follows:
7670 *
7671 * 1. Event injection.
7672 * 2. Trap on task-switch (T flag set in TSS).
7673 * 3. TPR below threshold / APIC-write.
7674 * 4. SMI, INIT.
7675 * 5. MTF exit.
7676 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7677 * 7. VMX-preemption timer.
7678 * 9. NMI-window exit.
7679 * 10. NMI injection.
7680 * 11. Interrupt-window exit.
7681 * 12. Virtual-interrupt injection.
7682 * 13. Interrupt injection.
7683 * 14. Process next instruction (fetch, decode, execute).
7684 */
7685
7686 /* Setup the VMX-preemption timer. */
7687 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7688
7689 /* Setup monitor-trap flag. */
7690 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7691
7692 /* Setup NMI-window exiting. */
7693 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7694
7695 /* Setup interrupt-window exiting. */
7696 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7697
7698 /* Now that we've switched page tables, we can go ahead and inject any event. */
7699 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7700 if (RT_SUCCESS(rcStrict))
7701 {
7702 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7703# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7704 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7705 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7706 if (rcSched != VINF_SUCCESS)
7707 iemSetPassUpStatus(pVCpu, rcSched);
7708# endif
7709 return VINF_SUCCESS;
7710 }
7711
7712 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7713 return rcStrict;
7714 }
7715 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7716 pVmcs->u64RoExitQual.u);
7717 }
7718 }
7719 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7720 pVmcs->u64RoExitQual.u);
7721 }
7722
7723 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7724 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7725 return VINF_SUCCESS;
7726 }
7727 }
7728 }
7729
7730 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7732 return VINF_SUCCESS;
7733# endif
7734}
7735
7736
7737/**
7738 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7739 * (causes a VM-exit) or not.
7740 *
7741 * @returns @c true if the instruction is intercepted, @c false otherwise.
7742 * @param pVCpu The cross context virtual CPU structure.
7743 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7744 * VMX_EXIT_WRMSR).
7745 * @param idMsr The MSR.
7746 */
7747IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7748{
7749 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7750 Assert( uExitReason == VMX_EXIT_RDMSR
7751 || uExitReason == VMX_EXIT_WRMSR);
7752
7753 /* Consult the MSR bitmap if the feature is supported. */
7754 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7755 Assert(pVmcs);
7756 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7757 {
7758 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7759 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7760 if (uExitReason == VMX_EXIT_RDMSR)
7761 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7762 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7763 }
7764
7765 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7766 return true;
7767}
7768
7769
7770/**
7771 * VMREAD common (memory/register) instruction execution worker
7772 *
7773 * @returns Strict VBox status code.
7774 * @param pVCpu The cross context virtual CPU structure.
7775 * @param cbInstr The instruction length in bytes.
7776 * @param pu64Dst Where to write the VMCS value (only updated when
7777 * VINF_SUCCESS is returned).
7778 * @param u64VmcsField The VMCS field.
7779 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7780 * NULL.
7781 */
7782IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7783 PCVMXVEXITINFO pExitInfo)
7784{
7785 /* Nested-guest intercept. */
7786 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7787 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7788 {
7789 if (pExitInfo)
7790 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7791 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7792 }
7793
7794 /* CPL. */
7795 if (pVCpu->iem.s.uCpl == 0)
7796 { /* likely */ }
7797 else
7798 {
7799 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7801 return iemRaiseGeneralProtectionFault0(pVCpu);
7802 }
7803
7804 /* VMCS pointer in root mode. */
7805 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7806 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7807 { /* likely */ }
7808 else
7809 {
7810 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7811 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7812 iemVmxVmFailInvalid(pVCpu);
7813 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7814 return VINF_SUCCESS;
7815 }
7816
7817 /* VMCS-link pointer in non-root mode. */
7818 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7819 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7820 { /* likely */ }
7821 else
7822 {
7823 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7825 iemVmxVmFailInvalid(pVCpu);
7826 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7827 return VINF_SUCCESS;
7828 }
7829
7830 /* Supported VMCS field. */
7831 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
7832 { /* likely */ }
7833 else
7834 {
7835 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7836 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7837 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7838 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7839 return VINF_SUCCESS;
7840 }
7841
7842 /*
7843 * Setup reading from the current or shadow VMCS.
7844 */
7845 uint8_t *pbVmcs;
7846 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7847 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7848 else
7849 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7850 Assert(pbVmcs);
7851
7852 VMXVMCSFIELD VmcsField;
7853 VmcsField.u = u64VmcsField;
7854 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
7855 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
7856 uint8_t const uWidthType = (uWidth << 2) | uType;
7857 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
7858 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7859 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7860 Assert(offField < VMX_V_VMCS_SIZE);
7861
7862 /*
7863 * Read the VMCS component based on the field's effective width.
7864 *
7865 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7866 * indicates high bits (little endian).
7867 *
7868 * Note! The caller is responsible to trim the result and update registers
7869 * or memory locations are required. Here we just zero-extend to the largest
7870 * type (i.e. 64-bits).
7871 */
7872 uint8_t *pbField = pbVmcs + offField;
7873 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7874 switch (uEffWidth)
7875 {
7876 case VMX_VMCS_ENC_WIDTH_64BIT:
7877 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7878 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7879 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7880 }
7881 return VINF_SUCCESS;
7882}
7883
7884
7885/**
7886 * VMREAD (64-bit register) instruction execution worker.
7887 *
7888 * @returns Strict VBox status code.
7889 * @param pVCpu The cross context virtual CPU structure.
7890 * @param cbInstr The instruction length in bytes.
7891 * @param pu64Dst Where to store the VMCS field's value.
7892 * @param u64VmcsField The VMCS field.
7893 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7894 * NULL.
7895 */
7896IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7897 PCVMXVEXITINFO pExitInfo)
7898{
7899 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7900 if (rcStrict == VINF_SUCCESS)
7901 {
7902 iemVmxVmreadSuccess(pVCpu, cbInstr);
7903 return VINF_SUCCESS;
7904 }
7905
7906 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7907 return rcStrict;
7908}
7909
7910
7911/**
7912 * VMREAD (32-bit register) instruction execution worker.
7913 *
7914 * @returns Strict VBox status code.
7915 * @param pVCpu The cross context virtual CPU structure.
7916 * @param cbInstr The instruction length in bytes.
7917 * @param pu32Dst Where to store the VMCS field's value.
7918 * @param u32VmcsField The VMCS field.
7919 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7920 * NULL.
7921 */
7922IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7923 PCVMXVEXITINFO pExitInfo)
7924{
7925 uint64_t u64Dst;
7926 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7927 if (rcStrict == VINF_SUCCESS)
7928 {
7929 *pu32Dst = u64Dst;
7930 iemVmxVmreadSuccess(pVCpu, cbInstr);
7931 return VINF_SUCCESS;
7932 }
7933
7934 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7935 return rcStrict;
7936}
7937
7938
7939/**
7940 * VMREAD (memory) instruction execution worker.
7941 *
7942 * @returns Strict VBox status code.
7943 * @param pVCpu The cross context virtual CPU structure.
7944 * @param cbInstr The instruction length in bytes.
7945 * @param iEffSeg The effective segment register to use with @a u64Val.
7946 * Pass UINT8_MAX if it is a register access.
7947 * @param GCPtrDst The guest linear address to store the VMCS field's
7948 * value.
7949 * @param u64VmcsField The VMCS field.
7950 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7951 * NULL.
7952 */
7953IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7954 PCVMXVEXITINFO pExitInfo)
7955{
7956 uint64_t u64Dst;
7957 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7958 if (rcStrict == VINF_SUCCESS)
7959 {
7960 /*
7961 * Write the VMCS field's value to the location specified in guest-memory.
7962 */
7963 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7964 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7965 else
7966 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7967 if (rcStrict == VINF_SUCCESS)
7968 {
7969 iemVmxVmreadSuccess(pVCpu, cbInstr);
7970 return VINF_SUCCESS;
7971 }
7972
7973 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7974 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7975 return rcStrict;
7976 }
7977
7978 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7979 return rcStrict;
7980}
7981
7982
7983/**
7984 * VMWRITE instruction execution worker.
7985 *
7986 * @returns Strict VBox status code.
7987 * @param pVCpu The cross context virtual CPU structure.
7988 * @param cbInstr The instruction length in bytes.
7989 * @param iEffSeg The effective segment register to use with @a u64Val.
7990 * Pass UINT8_MAX if it is a register access.
7991 * @param u64Val The value to write (or guest linear address to the
7992 * value), @a iEffSeg will indicate if it's a memory
7993 * operand.
7994 * @param u64VmcsField The VMCS field.
7995 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7996 * NULL.
7997 */
7998IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7999 PCVMXVEXITINFO pExitInfo)
8000{
8001 /* Nested-guest intercept. */
8002 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8003 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8004 {
8005 if (pExitInfo)
8006 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8007 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8008 }
8009
8010 /* CPL. */
8011 if (pVCpu->iem.s.uCpl == 0)
8012 { /* likely */ }
8013 else
8014 {
8015 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8016 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8017 return iemRaiseGeneralProtectionFault0(pVCpu);
8018 }
8019
8020 /* VMCS pointer in root mode. */
8021 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8022 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8023 { /* likely */ }
8024 else
8025 {
8026 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8028 iemVmxVmFailInvalid(pVCpu);
8029 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8030 return VINF_SUCCESS;
8031 }
8032
8033 /* VMCS-link pointer in non-root mode. */
8034 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8035 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8036 { /* likely */ }
8037 else
8038 {
8039 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8040 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8041 iemVmxVmFailInvalid(pVCpu);
8042 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8043 return VINF_SUCCESS;
8044 }
8045
8046 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8047 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8048 if (!fIsRegOperand)
8049 {
8050 /* Read the value from the specified guest memory location. */
8051 VBOXSTRICTRC rcStrict;
8052 RTGCPTR const GCPtrVal = u64Val;
8053 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8054 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8055 else
8056 {
8057 uint32_t u32Val;
8058 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8059 u64Val = u32Val;
8060 }
8061 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8062 {
8063 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8064 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8065 return rcStrict;
8066 }
8067 }
8068 else
8069 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8070
8071 /* Supported VMCS field. */
8072 if (iemVmxIsVmcsFieldValid(pVCpu, u64VmcsField))
8073 { /* likely */ }
8074 else
8075 {
8076 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8077 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8078 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8079 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8080 return VINF_SUCCESS;
8081 }
8082
8083 /* Read-only VMCS field. */
8084 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
8085 if ( !fIsFieldReadOnly
8086 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8087 { /* likely */ }
8088 else
8089 {
8090 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8091 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8092 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8093 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8094 return VINF_SUCCESS;
8095 }
8096
8097 /*
8098 * Setup writing to the current or shadow VMCS.
8099 */
8100 uint8_t *pbVmcs;
8101 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8102 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8103 else
8104 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8105 Assert(pbVmcs);
8106
8107 VMXVMCSFIELD VmcsField;
8108 VmcsField.u = u64VmcsField;
8109 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_WIDTH);
8110 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_TYPE);
8111 uint8_t const uWidthType = (uWidth << 2) | uType;
8112 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCS_ENC_INDEX);
8113 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8114 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8115 Assert(offField < VMX_V_VMCS_SIZE);
8116
8117 /*
8118 * Write the VMCS component based on the field's effective width.
8119 *
8120 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8121 * indicates high bits (little endian).
8122 */
8123 uint8_t *pbField = pbVmcs + offField;
8124 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
8125 switch (uEffWidth)
8126 {
8127 case VMX_VMCS_ENC_WIDTH_64BIT:
8128 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8129 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8130 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8131 }
8132
8133 iemVmxVmSucceed(pVCpu);
8134 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8135 return VINF_SUCCESS;
8136}
8137
8138
8139/**
8140 * VMCLEAR instruction execution worker.
8141 *
8142 * @returns Strict VBox status code.
8143 * @param pVCpu The cross context virtual CPU structure.
8144 * @param cbInstr The instruction length in bytes.
8145 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8146 * @param GCPtrVmcs The linear address of the VMCS pointer.
8147 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8148 * NULL.
8149 *
8150 * @remarks Common VMX instruction checks are already expected to by the caller,
8151 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8152 */
8153IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8154 PCVMXVEXITINFO pExitInfo)
8155{
8156 /* Nested-guest intercept. */
8157 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8158 {
8159 if (pExitInfo)
8160 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8161 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8162 }
8163
8164 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8165
8166 /* CPL. */
8167 if (pVCpu->iem.s.uCpl == 0)
8168 { /* likely */ }
8169 else
8170 {
8171 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8172 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8173 return iemRaiseGeneralProtectionFault0(pVCpu);
8174 }
8175
8176 /* Get the VMCS pointer from the location specified by the source memory operand. */
8177 RTGCPHYS GCPhysVmcs;
8178 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8179 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8180 { /* likely */ }
8181 else
8182 {
8183 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8185 return rcStrict;
8186 }
8187
8188 /* VMCS pointer alignment. */
8189 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8190 { /* likely */ }
8191 else
8192 {
8193 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8194 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8195 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8196 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8197 return VINF_SUCCESS;
8198 }
8199
8200 /* VMCS physical-address width limits. */
8201 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8202 { /* likely */ }
8203 else
8204 {
8205 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8206 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8207 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8208 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8209 return VINF_SUCCESS;
8210 }
8211
8212 /* VMCS is not the VMXON region. */
8213 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8214 { /* likely */ }
8215 else
8216 {
8217 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8218 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8219 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8220 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8221 return VINF_SUCCESS;
8222 }
8223
8224 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8225 restriction imposed by our implementation. */
8226 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8227 { /* likely */ }
8228 else
8229 {
8230 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8231 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8232 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8233 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8234 return VINF_SUCCESS;
8235 }
8236
8237 /*
8238 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8239 *
8240 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8241 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8242 * to 'clear'.
8243 */
8244 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8245 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8246 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8247 {
8248 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8249 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8250 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8251 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8252 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8253 }
8254 else
8255 {
8256 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8257 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8258 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8259 if (RT_FAILURE(rcStrict))
8260 return rcStrict;
8261 }
8262
8263 iemVmxVmSucceed(pVCpu);
8264 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8265 return VINF_SUCCESS;
8266}
8267
8268
8269/**
8270 * VMPTRST instruction execution worker.
8271 *
8272 * @returns Strict VBox status code.
8273 * @param pVCpu The cross context virtual CPU structure.
8274 * @param cbInstr The instruction length in bytes.
8275 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8276 * @param GCPtrVmcs The linear address of where to store the current VMCS
8277 * pointer.
8278 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8279 * NULL.
8280 *
8281 * @remarks Common VMX instruction checks are already expected to by the caller,
8282 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8283 */
8284IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8285 PCVMXVEXITINFO pExitInfo)
8286{
8287 /* Nested-guest intercept. */
8288 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8289 {
8290 if (pExitInfo)
8291 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8292 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8293 }
8294
8295 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8296
8297 /* CPL. */
8298 if (pVCpu->iem.s.uCpl == 0)
8299 { /* likely */ }
8300 else
8301 {
8302 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8303 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8304 return iemRaiseGeneralProtectionFault0(pVCpu);
8305 }
8306
8307 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8308 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8309 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8310 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8311 {
8312 iemVmxVmSucceed(pVCpu);
8313 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8314 return rcStrict;
8315 }
8316
8317 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8318 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8319 return rcStrict;
8320}
8321
8322
8323/**
8324 * VMPTRLD instruction execution worker.
8325 *
8326 * @returns Strict VBox status code.
8327 * @param pVCpu The cross context virtual CPU structure.
8328 * @param cbInstr The instruction length in bytes.
8329 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8330 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8331 * NULL.
8332 *
8333 * @remarks Common VMX instruction checks are already expected to by the caller,
8334 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8335 */
8336IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8337 PCVMXVEXITINFO pExitInfo)
8338{
8339 /* Nested-guest intercept. */
8340 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8341 {
8342 if (pExitInfo)
8343 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8344 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8345 }
8346
8347 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8348
8349 /* CPL. */
8350 if (pVCpu->iem.s.uCpl == 0)
8351 { /* likely */ }
8352 else
8353 {
8354 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8355 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8356 return iemRaiseGeneralProtectionFault0(pVCpu);
8357 }
8358
8359 /* Get the VMCS pointer from the location specified by the source memory operand. */
8360 RTGCPHYS GCPhysVmcs;
8361 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8362 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8363 { /* likely */ }
8364 else
8365 {
8366 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8368 return rcStrict;
8369 }
8370
8371 /* VMCS pointer alignment. */
8372 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8373 { /* likely */ }
8374 else
8375 {
8376 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8377 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8378 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8379 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8380 return VINF_SUCCESS;
8381 }
8382
8383 /* VMCS physical-address width limits. */
8384 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8385 { /* likely */ }
8386 else
8387 {
8388 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8389 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8390 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8391 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8392 return VINF_SUCCESS;
8393 }
8394
8395 /* VMCS is not the VMXON region. */
8396 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8397 { /* likely */ }
8398 else
8399 {
8400 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8401 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8402 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8403 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8404 return VINF_SUCCESS;
8405 }
8406
8407 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8408 restriction imposed by our implementation. */
8409 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8410 { /* likely */ }
8411 else
8412 {
8413 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8416 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8417 return VINF_SUCCESS;
8418 }
8419
8420 /* Read just the VMCS revision from the VMCS. */
8421 VMXVMCSREVID VmcsRevId;
8422 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8423 if (RT_SUCCESS(rc))
8424 { /* likely */ }
8425 else
8426 {
8427 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8428 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8429 return rc;
8430 }
8431
8432 /*
8433 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8434 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8435 */
8436 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8437 && ( !VmcsRevId.n.fIsShadowVmcs
8438 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8439 { /* likely */ }
8440 else
8441 {
8442 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8443 {
8444 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8445 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8446 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8447 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8448 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8449 return VINF_SUCCESS;
8450 }
8451
8452 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8454 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8455 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8456 return VINF_SUCCESS;
8457 }
8458
8459 /*
8460 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8461 * the cache of an existing, current VMCS back to guest memory before loading a new,
8462 * different current VMCS.
8463 */
8464 bool fLoadVmcsFromMem;
8465 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8466 {
8467 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8468 {
8469 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8470 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8471 fLoadVmcsFromMem = true;
8472 }
8473 else
8474 fLoadVmcsFromMem = false;
8475 }
8476 else
8477 fLoadVmcsFromMem = true;
8478
8479 if (fLoadVmcsFromMem)
8480 {
8481 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8482 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8483 sizeof(VMXVVMCS));
8484 if (RT_SUCCESS(rc))
8485 { /* likely */ }
8486 else
8487 {
8488 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8489 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8490 return rc;
8491 }
8492 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8493 }
8494
8495 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8496 iemVmxVmSucceed(pVCpu);
8497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8498 return VINF_SUCCESS;
8499}
8500
8501
8502/**
8503 * INVVPID instruction execution worker.
8504 *
8505 * @returns Strict VBox status code.
8506 * @param pVCpu The cross context virtual CPU structure.
8507 * @param cbInstr The instruction length in bytes.
8508 * @param iEffSeg The segment of the invvpid descriptor.
8509 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8510 * @param u64InvvpidType The invalidation type.
8511 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8512 * NULL.
8513 *
8514 * @remarks Common VMX instruction checks are already expected to by the caller,
8515 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8516 */
8517IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8518 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8519{
8520 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8521 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8522 return iemRaiseUndefinedOpcode(pVCpu);
8523
8524 /* Nested-guest intercept. */
8525 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8526 {
8527 if (pExitInfo)
8528 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8529 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8530 }
8531
8532 /* CPL. */
8533 if (pVCpu->iem.s.uCpl != 0)
8534 {
8535 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8536 return iemRaiseGeneralProtectionFault0(pVCpu);
8537 }
8538
8539 /*
8540 * Validate INVVPID invalidation type.
8541 *
8542 * The instruction specifies exactly ONE of the supported invalidation types.
8543 *
8544 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8545 * supported. In theory, it's possible for a CPU to not support flushing individual
8546 * addresses but all the other types or any other combination. We do not take any
8547 * shortcuts here by assuming the types we currently expose to the guest.
8548 */
8549 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8550 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8551 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8552 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8553 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8554 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8555 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8556 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8557 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8558 { /* likely */ }
8559 else
8560 {
8561 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8563 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8565 return VINF_SUCCESS;
8566 }
8567
8568 /*
8569 * Fetch the invvpid descriptor from guest memory.
8570 */
8571 RTUINT128U uDesc;
8572 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8573 if (rcStrict == VINF_SUCCESS)
8574 {
8575 /*
8576 * Validate the descriptor.
8577 */
8578 if (uDesc.s.Lo > 0xfff)
8579 {
8580 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8582 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8583 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8584 return VINF_SUCCESS;
8585 }
8586
8587 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8588 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8589 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8590 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8591 switch (u64InvvpidType)
8592 {
8593 case VMXTLBFLUSHVPID_INDIV_ADDR:
8594 {
8595 if (uVpid != 0)
8596 {
8597 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8598 {
8599 /* Invalidate mappings for the linear address tagged with VPID. */
8600 /** @todo PGM support for VPID? Currently just flush everything. */
8601 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8602 iemVmxVmSucceed(pVCpu);
8603 }
8604 else
8605 {
8606 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8607 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8608 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8609 }
8610 }
8611 else
8612 {
8613 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8614 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8615 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8616 }
8617 break;
8618 }
8619
8620 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8621 {
8622 if (uVpid != 0)
8623 {
8624 /* Invalidate all mappings with VPID. */
8625 /** @todo PGM support for VPID? Currently just flush everything. */
8626 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8627 iemVmxVmSucceed(pVCpu);
8628 }
8629 else
8630 {
8631 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8632 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8633 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8634 }
8635 break;
8636 }
8637
8638 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8639 {
8640 /* Invalidate all mappings with non-zero VPIDs. */
8641 /** @todo PGM support for VPID? Currently just flush everything. */
8642 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8643 iemVmxVmSucceed(pVCpu);
8644 break;
8645 }
8646
8647 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8648 {
8649 if (uVpid != 0)
8650 {
8651 /* Invalidate all mappings with VPID except global translations. */
8652 /** @todo PGM support for VPID? Currently just flush everything. */
8653 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8654 iemVmxVmSucceed(pVCpu);
8655 }
8656 else
8657 {
8658 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8659 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8660 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8661 }
8662 break;
8663 }
8664 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8665 }
8666 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8667 }
8668 return rcStrict;
8669}
8670
8671
8672/**
8673 * VMXON instruction execution worker.
8674 *
8675 * @returns Strict VBox status code.
8676 * @param pVCpu The cross context virtual CPU structure.
8677 * @param cbInstr The instruction length in bytes.
8678 * @param iEffSeg The effective segment register to use with @a
8679 * GCPtrVmxon.
8680 * @param GCPtrVmxon The linear address of the VMXON pointer.
8681 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8682 * NULL.
8683 *
8684 * @remarks Common VMX instruction checks are already expected to by the caller,
8685 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8686 */
8687IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8688 PCVMXVEXITINFO pExitInfo)
8689{
8690 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8691 {
8692 /* CPL. */
8693 if (pVCpu->iem.s.uCpl == 0)
8694 { /* likely */ }
8695 else
8696 {
8697 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8698 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8699 return iemRaiseGeneralProtectionFault0(pVCpu);
8700 }
8701
8702 /* A20M (A20 Masked) mode. */
8703 if (PGMPhysIsA20Enabled(pVCpu))
8704 { /* likely */ }
8705 else
8706 {
8707 Log(("vmxon: A20M mode -> #GP(0)\n"));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8709 return iemRaiseGeneralProtectionFault0(pVCpu);
8710 }
8711
8712 /* CR0. */
8713 {
8714 /* CR0 MB1 bits. */
8715 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8716 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8717 { /* likely */ }
8718 else
8719 {
8720 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8721 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8722 return iemRaiseGeneralProtectionFault0(pVCpu);
8723 }
8724
8725 /* CR0 MBZ bits. */
8726 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8727 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8728 { /* likely */ }
8729 else
8730 {
8731 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8732 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8733 return iemRaiseGeneralProtectionFault0(pVCpu);
8734 }
8735 }
8736
8737 /* CR4. */
8738 {
8739 /* CR4 MB1 bits. */
8740 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8741 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8742 { /* likely */ }
8743 else
8744 {
8745 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8746 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8747 return iemRaiseGeneralProtectionFault0(pVCpu);
8748 }
8749
8750 /* CR4 MBZ bits. */
8751 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8752 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8753 { /* likely */ }
8754 else
8755 {
8756 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8757 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8758 return iemRaiseGeneralProtectionFault0(pVCpu);
8759 }
8760 }
8761
8762 /* Feature control MSR's LOCK and VMXON bits. */
8763 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8764 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8765 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8766 { /* likely */ }
8767 else
8768 {
8769 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8770 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8771 return iemRaiseGeneralProtectionFault0(pVCpu);
8772 }
8773
8774 /* Get the VMXON pointer from the location specified by the source memory operand. */
8775 RTGCPHYS GCPhysVmxon;
8776 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8777 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8778 { /* likely */ }
8779 else
8780 {
8781 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8783 return rcStrict;
8784 }
8785
8786 /* VMXON region pointer alignment. */
8787 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8788 { /* likely */ }
8789 else
8790 {
8791 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8792 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8793 iemVmxVmFailInvalid(pVCpu);
8794 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8795 return VINF_SUCCESS;
8796 }
8797
8798 /* VMXON physical-address width limits. */
8799 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8800 { /* likely */ }
8801 else
8802 {
8803 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8805 iemVmxVmFailInvalid(pVCpu);
8806 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8807 return VINF_SUCCESS;
8808 }
8809
8810 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8811 restriction imposed by our implementation. */
8812 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8813 { /* likely */ }
8814 else
8815 {
8816 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8817 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8818 iemVmxVmFailInvalid(pVCpu);
8819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8820 return VINF_SUCCESS;
8821 }
8822
8823 /* Read the VMCS revision ID from the VMXON region. */
8824 VMXVMCSREVID VmcsRevId;
8825 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8826 if (RT_SUCCESS(rc))
8827 { /* likely */ }
8828 else
8829 {
8830 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8831 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8832 return rc;
8833 }
8834
8835 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8836 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8837 { /* likely */ }
8838 else
8839 {
8840 /* Revision ID mismatch. */
8841 if (!VmcsRevId.n.fIsShadowVmcs)
8842 {
8843 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8844 VmcsRevId.n.u31RevisionId));
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8846 iemVmxVmFailInvalid(pVCpu);
8847 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8848 return VINF_SUCCESS;
8849 }
8850
8851 /* Shadow VMCS disallowed. */
8852 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8853 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8854 iemVmxVmFailInvalid(pVCpu);
8855 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8856 return VINF_SUCCESS;
8857 }
8858
8859 /*
8860 * Record that we're in VMX operation, block INIT, block and disable A20M.
8861 */
8862 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8863 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8864 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8865
8866 /* Clear address-range monitoring. */
8867 EMMonitorWaitClear(pVCpu);
8868 /** @todo NSTVMX: Intel PT. */
8869
8870 iemVmxVmSucceed(pVCpu);
8871 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8872 return VINF_SUCCESS;
8873 }
8874 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8875 {
8876 /* Nested-guest intercept. */
8877 if (pExitInfo)
8878 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8879 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8880 }
8881
8882 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8883
8884 /* CPL. */
8885 if (pVCpu->iem.s.uCpl > 0)
8886 {
8887 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8888 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8889 return iemRaiseGeneralProtectionFault0(pVCpu);
8890 }
8891
8892 /* VMXON when already in VMX root mode. */
8893 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8894 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8895 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8896 return VINF_SUCCESS;
8897}
8898
8899
8900/**
8901 * Implements 'VMXOFF'.
8902 *
8903 * @remarks Common VMX instruction checks are already expected to by the caller,
8904 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8905 */
8906IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8907{
8908 /* Nested-guest intercept. */
8909 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8910 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8911
8912 /* CPL. */
8913 if (pVCpu->iem.s.uCpl == 0)
8914 { /* likely */ }
8915 else
8916 {
8917 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8918 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8919 return iemRaiseGeneralProtectionFault0(pVCpu);
8920 }
8921
8922 /* Dual monitor treatment of SMIs and SMM. */
8923 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8924 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8925 { /* likely */ }
8926 else
8927 {
8928 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8929 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8930 return VINF_SUCCESS;
8931 }
8932
8933 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8934 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8935 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8936
8937 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8938 { /** @todo NSTVMX: Unblock SMI. */ }
8939
8940 EMMonitorWaitClear(pVCpu);
8941 /** @todo NSTVMX: Unblock and enable A20M. */
8942
8943 iemVmxVmSucceed(pVCpu);
8944 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8945 return VINF_SUCCESS;
8946}
8947
8948
8949/**
8950 * Implements 'VMXON'.
8951 */
8952IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8953{
8954 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8955}
8956
8957
8958/**
8959 * Implements 'VMLAUNCH'.
8960 */
8961IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8962{
8963 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8964}
8965
8966
8967/**
8968 * Implements 'VMRESUME'.
8969 */
8970IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8971{
8972 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8973}
8974
8975
8976/**
8977 * Implements 'VMPTRLD'.
8978 */
8979IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8980{
8981 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8982}
8983
8984
8985/**
8986 * Implements 'VMPTRST'.
8987 */
8988IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8989{
8990 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8991}
8992
8993
8994/**
8995 * Implements 'VMCLEAR'.
8996 */
8997IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8998{
8999 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9000}
9001
9002
9003/**
9004 * Implements 'VMWRITE' register.
9005 */
9006IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9007{
9008 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9009}
9010
9011
9012/**
9013 * Implements 'VMWRITE' memory.
9014 */
9015IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9016{
9017 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9018}
9019
9020
9021/**
9022 * Implements 'VMREAD' register (64-bit).
9023 */
9024IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9025{
9026 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9027}
9028
9029
9030/**
9031 * Implements 'VMREAD' register (32-bit).
9032 */
9033IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9034{
9035 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9036}
9037
9038
9039/**
9040 * Implements 'VMREAD' memory, 64-bit register.
9041 */
9042IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9043{
9044 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9045}
9046
9047
9048/**
9049 * Implements 'VMREAD' memory, 32-bit register.
9050 */
9051IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9052{
9053 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9054}
9055
9056
9057/**
9058 * Implements 'INVVPID'.
9059 */
9060IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9061{
9062 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9063}
9064
9065
9066/**
9067 * Implements VMX's implementation of PAUSE.
9068 */
9069IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9070{
9071 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9072 {
9073 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9074 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9075 return rcStrict;
9076 }
9077
9078 /*
9079 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9080 * a VM-exit, the instruction operates normally.
9081 */
9082 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9083 return VINF_SUCCESS;
9084}
9085
9086#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9087
9088
9089/**
9090 * Implements 'VMCALL'.
9091 */
9092IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9093{
9094#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9095 /* Nested-guest intercept. */
9096 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9097 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9098#endif
9099
9100 /* Join forces with vmmcall. */
9101 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9102}
9103
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