VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79233

Last change on this file since 79233 was 79233, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Doxygen spaces.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79233 2019-06-19 08:25:43Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Gets a CR3 target value from the VMCS.
621 *
622 * @returns VBox status code.
623 * @param pVmcs Pointer to the virtual VMCS.
624 * @param idxCr3Target The index of the CR3-target value to retrieve.
625 * @param puValue Where to store the CR3-target value.
626 */
627IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
628{
629 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
630 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
631 uint8_t const uType = VMX_VMCSFIELD_TYPE_CONTROL;
632 uint8_t const uWidthType = (uWidth << 2) | uType;
633 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCSFIELD_INDEX);
634 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
635 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
636 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
637 uint8_t const *pbField = pbVmcs + offField;
638 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
639 return uCr3TargetValue;
640}
641
642
643/**
644 * Converts an IEM exception event type to a VMX event type.
645 *
646 * @returns The VMX event type.
647 * @param uVector The interrupt / exception vector.
648 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
649 */
650DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
651{
652 /* Paranoia (callers may use these interchangeably). */
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
662 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
663 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
664 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
665
666 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
667 {
668 if (uVector == X86_XCPT_NMI)
669 return VMX_EXIT_INT_INFO_TYPE_NMI;
670 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
671 }
672
673 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
674 {
675 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
676 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
677 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
678 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
679 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
680 }
681
682 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
683 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
684}
685
686
687/**
688 * Sets the Exit qualification VMCS field.
689 *
690 * @param pVCpu The cross context virtual CPU structure.
691 * @param u64ExitQual The Exit qualification.
692 */
693DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
694{
695 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
696 pVmcs->u64RoExitQual.u = u64ExitQual;
697}
698
699
700/**
701 * Sets the VM-exit interruption information field.
702 *
703 * @param pVCpu The cross context virtual CPU structure.
704 * @param uExitIntInfo The VM-exit interruption information.
705 */
706DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
707{
708 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
709 pVmcs->u32RoExitIntInfo = uExitIntInfo;
710}
711
712
713/**
714 * Sets the VM-exit interruption error code.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uErrCode The error code.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
720{
721 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
722 pVmcs->u32RoExitIntErrCode = uErrCode;
723}
724
725
726/**
727 * Sets the IDT-vectoring information field.
728 *
729 * @param pVCpu The cross context virtual CPU structure.
730 * @param uIdtVectorInfo The IDT-vectoring information.
731 */
732DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
733{
734 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
735 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
736}
737
738
739/**
740 * Sets the IDT-vectoring error code field.
741 *
742 * @param pVCpu The cross context virtual CPU structure.
743 * @param uErrCode The error code.
744 */
745DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
746{
747 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
748 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
749}
750
751
752/**
753 * Sets the VM-exit guest-linear address VMCS field.
754 *
755 * @param pVCpu The cross context virtual CPU structure.
756 * @param uGuestLinearAddr The VM-exit guest-linear address.
757 */
758DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
759{
760 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
761 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
762}
763
764
765/**
766 * Sets the VM-exit guest-physical address VMCS field.
767 *
768 * @param pVCpu The cross context virtual CPU structure.
769 * @param uGuestPhysAddr The VM-exit guest-physical address.
770 */
771DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
772{
773 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
774 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
775}
776
777
778/**
779 * Sets the VM-exit instruction length VMCS field.
780 *
781 * @param pVCpu The cross context virtual CPU structure.
782 * @param cbInstr The VM-exit instruction length in bytes.
783 *
784 * @remarks Callers may clear this field to 0. Hence, this function does not check
785 * the validity of the instruction length.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
788{
789 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
790 pVmcs->u32RoExitInstrLen = cbInstr;
791}
792
793
794/**
795 * Sets the VM-exit instruction info. VMCS field.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 * @param uExitInstrInfo The VM-exit instruction information.
799 */
800DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
801{
802 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
803 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
804}
805
806
807/**
808 * Implements VMSucceed for VMX instruction success.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 */
812DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
813{
814 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
815}
816
817
818/**
819 * Implements VMFailInvalid for VMX instruction failure.
820 *
821 * @param pVCpu The cross context virtual CPU structure.
822 */
823DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
824{
825 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
826}
827
828
829/**
830 * Implements VMFail for VMX instruction failure.
831 *
832 * @param pVCpu The cross context virtual CPU structure.
833 * @param enmInsErr The VM instruction error.
834 */
835DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
836{
837 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
838}
839
840
841/**
842 * Checks if the given auto-load/store MSR area count is valid for the
843 * implementation.
844 *
845 * @returns @c true if it's within the valid limit, @c false otherwise.
846 * @param pVCpu The cross context virtual CPU structure.
847 * @param uMsrCount The MSR area count to check.
848 */
849DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
850{
851 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
852 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
853 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
854 if (uMsrCount <= cMaxSupportedMsrs)
855 return true;
856 return false;
857}
858
859
860/**
861 * Flushes the current VMCS contents back to guest memory.
862 *
863 * @returns VBox status code.
864 * @param pVCpu The cross context virtual CPU structure.
865 */
866DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
867{
868 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
869 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
870 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
871 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
872 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
873 return rc;
874}
875
876
877/**
878 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
879 *
880 * @param pVCpu The cross context virtual CPU structure.
881 */
882DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
883{
884 iemVmxVmSucceed(pVCpu);
885 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
886}
887
888
889/**
890 * Gets the instruction diagnostic for segment base checks during VM-entry of a
891 * nested-guest.
892 *
893 * @param iSegReg The segment index (X86_SREG_XXX).
894 */
895IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
896{
897 switch (iSegReg)
898 {
899 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
900 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
901 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
902 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
903 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
904 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
905 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
906 }
907}
908
909
910/**
911 * Gets the instruction diagnostic for segment base checks during VM-entry of a
912 * nested-guest that is in Virtual-8086 mode.
913 *
914 * @param iSegReg The segment index (X86_SREG_XXX).
915 */
916IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
917{
918 switch (iSegReg)
919 {
920 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
921 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
922 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
923 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
924 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
925 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
926 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
927 }
928}
929
930
931/**
932 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
933 * nested-guest that is in Virtual-8086 mode.
934 *
935 * @param iSegReg The segment index (X86_SREG_XXX).
936 */
937IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
938{
939 switch (iSegReg)
940 {
941 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
942 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
943 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
944 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
945 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
946 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
947 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
948 }
949}
950
951
952/**
953 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
954 * nested-guest that is in Virtual-8086 mode.
955 *
956 * @param iSegReg The segment index (X86_SREG_XXX).
957 */
958IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
959{
960 switch (iSegReg)
961 {
962 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
963 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
964 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
965 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
966 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
967 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
968 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
969 }
970}
971
972
973/**
974 * Gets the instruction diagnostic for segment attributes reserved bits failure
975 * during VM-entry of a nested-guest.
976 *
977 * @param iSegReg The segment index (X86_SREG_XXX).
978 */
979IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
980{
981 switch (iSegReg)
982 {
983 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
984 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
985 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
986 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
987 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
988 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
989 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
990 }
991}
992
993
994/**
995 * Gets the instruction diagnostic for segment attributes descriptor-type
996 * (code/segment or system) failure during VM-entry of a nested-guest.
997 *
998 * @param iSegReg The segment index (X86_SREG_XXX).
999 */
1000IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1001{
1002 switch (iSegReg)
1003 {
1004 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1005 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1006 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1007 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1008 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1009 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1010 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1011 }
1012}
1013
1014
1015/**
1016 * Gets the instruction diagnostic for segment attributes descriptor-type
1017 * (code/segment or system) failure during VM-entry of a nested-guest.
1018 *
1019 * @param iSegReg The segment index (X86_SREG_XXX).
1020 */
1021IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1022{
1023 switch (iSegReg)
1024 {
1025 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1026 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1027 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1028 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1029 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1030 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1031 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1032 }
1033}
1034
1035
1036/**
1037 * Gets the instruction diagnostic for segment attribute granularity failure during
1038 * VM-entry of a nested-guest.
1039 *
1040 * @param iSegReg The segment index (X86_SREG_XXX).
1041 */
1042IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1043{
1044 switch (iSegReg)
1045 {
1046 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1047 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1048 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1049 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1050 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1051 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1052 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1053 }
1054}
1055
1056/**
1057 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1058 * VM-entry of a nested-guest.
1059 *
1060 * @param iSegReg The segment index (X86_SREG_XXX).
1061 */
1062IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1063{
1064 switch (iSegReg)
1065 {
1066 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1067 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1068 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1069 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1070 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1071 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1072 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1073 }
1074}
1075
1076
1077/**
1078 * Gets the instruction diagnostic for segment attribute type accessed failure
1079 * during VM-entry of a nested-guest.
1080 *
1081 * @param iSegReg The segment index (X86_SREG_XXX).
1082 */
1083IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1084{
1085 switch (iSegReg)
1086 {
1087 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1088 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1089 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1090 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1091 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1092 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1093 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1094 }
1095}
1096
1097
1098/**
1099 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1100 * failure during VM-entry of a nested-guest.
1101 *
1102 * @param iSegReg The PDPTE entry index.
1103 */
1104IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1105{
1106 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1107 switch (iPdpte)
1108 {
1109 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1110 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1111 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1112 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1113 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1114 }
1115}
1116
1117
1118/**
1119 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1120 * failure during VM-exit of a nested-guest.
1121 *
1122 * @param iSegReg The PDPTE entry index.
1123 */
1124IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1125{
1126 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1127 switch (iPdpte)
1128 {
1129 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1130 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1131 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1132 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1133 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1134 }
1135}
1136
1137
1138/**
1139 * Saves the guest control registers, debug registers and some MSRs are part of
1140 * VM-exit.
1141 *
1142 * @param pVCpu The cross context virtual CPU structure.
1143 */
1144IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1145{
1146 /*
1147 * Saves the guest control registers, debug registers and some MSRs.
1148 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1149 */
1150 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1151
1152 /* Save control registers. */
1153 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1154 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1155 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1156
1157 /* Save SYSENTER CS, ESP, EIP. */
1158 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1159 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1160 {
1161 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1162 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1163 }
1164 else
1165 {
1166 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1167 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1168 }
1169
1170 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1171 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1172 {
1173 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1174 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1175 }
1176
1177 /* Save PAT MSR. */
1178 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1179 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1180
1181 /* Save EFER MSR. */
1182 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1183 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1184
1185 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1186 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1187
1188 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1189}
1190
1191
1192/**
1193 * Saves the guest force-flags in preparation of entering the nested-guest.
1194 *
1195 * @param pVCpu The cross context virtual CPU structure.
1196 */
1197IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1198{
1199 /* We shouldn't be called multiple times during VM-entry. */
1200 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1201
1202 /* MTF should not be set outside VMX non-root mode. */
1203 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1204
1205 /*
1206 * Preserve the required force-flags.
1207 *
1208 * We cache and clear force-flags that would affect the execution of the
1209 * nested-guest. Cached flags are then restored while returning to the guest
1210 * if necessary.
1211 *
1212 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1213 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1214 * instruction. Interrupt inhibition for any nested-guest instruction
1215 * is supplied by the guest-interruptibility state VMCS field and will
1216 * be set up as part of loading the guest state.
1217 *
1218 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1219 * successful VM-entry (due to invalid guest-state) need to continue
1220 * blocking NMIs if it was in effect before VM-entry.
1221 *
1222 * - MTF need not be preserved as it's used only in VMX non-root mode and
1223 * is supplied through the VM-execution controls.
1224 *
1225 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1226 * we will be able to generate interrupts that may cause VM-exits for
1227 * the nested-guest.
1228 */
1229 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1230}
1231
1232
1233/**
1234 * Restores the guest force-flags in preparation of exiting the nested-guest.
1235 *
1236 * @param pVCpu The cross context virtual CPU structure.
1237 */
1238IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1239{
1240 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1241 {
1242 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1243 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1244 }
1245}
1246
1247
1248/**
1249 * Perform a VMX transition updated PGM, IEM and CPUM.
1250 *
1251 * @param pVCpu The cross context virtual CPU structure.
1252 */
1253IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1254{
1255 /*
1256 * Inform PGM about paging mode changes.
1257 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1258 * see comment in iemMemPageTranslateAndCheckAccess().
1259 */
1260 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1261# ifdef IN_RING3
1262 Assert(rc != VINF_PGM_CHANGE_MODE);
1263# endif
1264 AssertRCReturn(rc, rc);
1265
1266 /* Inform CPUM (recompiler), can later be removed. */
1267 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1268
1269 /*
1270 * Flush the TLB with new CR3. This is required in case the PGM mode change
1271 * above doesn't actually change anything.
1272 */
1273 if (rc == VINF_SUCCESS)
1274 {
1275 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1276 AssertRCReturn(rc, rc);
1277 }
1278
1279 /* Re-initialize IEM cache/state after the drastic mode switch. */
1280 iemReInitExec(pVCpu);
1281 return rc;
1282}
1283
1284
1285/**
1286 * Calculates the current VMX-preemption timer value.
1287 *
1288 * @returns The current VMX-preemption timer value.
1289 * @param pVCpu The cross context virtual CPU structure.
1290 */
1291IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1292{
1293 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1294 Assert(pVmcs);
1295
1296 /*
1297 * Assume the following:
1298 * PreemptTimerShift = 5
1299 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1300 * EntryTick = 50000 (TSC at time of VM-entry)
1301 *
1302 * CurTick Delta PreemptTimerVal
1303 * ----------------------------------
1304 * 60000 10000 2
1305 * 80000 30000 1
1306 * 90000 40000 0 -> VM-exit.
1307 *
1308 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1309 * The saved VMX-preemption timer value is calculated as follows:
1310 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1311 * E.g.:
1312 * Delta = 10000
1313 * Tmp = 10000 / (2 * 10000) = 0.5
1314 * NewPt = 2 - 0.5 = 2
1315 * Delta = 30000
1316 * Tmp = 30000 / (2 * 10000) = 1.5
1317 * NewPt = 2 - 1.5 = 1
1318 * Delta = 40000
1319 * Tmp = 40000 / 20000 = 2
1320 * NewPt = 2 - 2 = 0
1321 */
1322 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1323 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1324 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1325 uint64_t const uDelta = uCurTick - uEntryTick;
1326 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1327 uint32_t const uPreemptTimer = uVmcsPreemptVal
1328 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1329 return uPreemptTimer;
1330}
1331
1332
1333/**
1334 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1335 *
1336 * @param pVCpu The cross context virtual CPU structure.
1337 */
1338IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1339{
1340 /*
1341 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1342 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1343 */
1344 /* CS, SS, ES, DS, FS, GS. */
1345 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1346 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1347 {
1348 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1349 if (!pSelReg->Attr.n.u1Unusable)
1350 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1351 else
1352 {
1353 /*
1354 * For unusable segments the attributes are undefined except for CS and SS.
1355 * For the rest we don't bother preserving anything but the unusable bit.
1356 */
1357 switch (iSegReg)
1358 {
1359 case X86_SREG_CS:
1360 pVmcs->GuestCs = pSelReg->Sel;
1361 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1362 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1363 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1364 | X86DESCATTR_UNUSABLE);
1365 break;
1366
1367 case X86_SREG_SS:
1368 pVmcs->GuestSs = pSelReg->Sel;
1369 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1370 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1371 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1372 break;
1373
1374 case X86_SREG_DS:
1375 pVmcs->GuestDs = pSelReg->Sel;
1376 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1377 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1378 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1379 break;
1380
1381 case X86_SREG_ES:
1382 pVmcs->GuestEs = pSelReg->Sel;
1383 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1384 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1385 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1386 break;
1387
1388 case X86_SREG_FS:
1389 pVmcs->GuestFs = pSelReg->Sel;
1390 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1391 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1392 break;
1393
1394 case X86_SREG_GS:
1395 pVmcs->GuestGs = pSelReg->Sel;
1396 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1397 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399 }
1400 }
1401 }
1402
1403 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1404 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1405 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1406 | X86DESCATTR_UNUSABLE;
1407 /* LDTR. */
1408 {
1409 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1410 pVmcs->GuestLdtr = pSelReg->Sel;
1411 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1412 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1413 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1414 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1415 }
1416
1417 /* TR. */
1418 {
1419 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1420 pVmcs->GuestTr = pSelReg->Sel;
1421 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1422 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1423 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1424 }
1425
1426 /* GDTR. */
1427 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1428 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1429
1430 /* IDTR. */
1431 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1432 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1433}
1434
1435
1436/**
1437 * Saves guest non-register state as part of VM-exit.
1438 *
1439 * @param pVCpu The cross context virtual CPU structure.
1440 * @param uExitReason The VM-exit reason.
1441 */
1442IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1443{
1444 /*
1445 * Save guest non-register state.
1446 * See Intel spec. 27.3.4 "Saving Non-Register State".
1447 */
1448 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1449
1450 /*
1451 * Activity state.
1452 * Most VM-exits will occur in the active state. However, if the first instruction
1453 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1454 * the VM-exit will be from the HLT activity state.
1455 *
1456 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1457 */
1458 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1459 * not? */
1460 EMSTATE const enmActivityState = EMGetState(pVCpu);
1461 switch (enmActivityState)
1462 {
1463 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1464 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1465 }
1466
1467 /*
1468 * Interruptibility-state.
1469 */
1470 /* NMI. */
1471 pVmcs->u32GuestIntrState = 0;
1472 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1473 {
1474 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1475 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1476 }
1477 else
1478 {
1479 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1481 }
1482
1483 /* Blocking-by-STI. */
1484 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1485 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1486 {
1487 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1488 * currently. */
1489 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1490 }
1491 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1492
1493 /*
1494 * Pending debug exceptions.
1495 */
1496 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1497 && uExitReason != VMX_EXIT_SMI
1498 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1499 && !HMVmxIsVmexitTrapLike(uExitReason))
1500 {
1501 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1502 * block-by-MovSS is in effect. */
1503 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1504 }
1505 else
1506 {
1507 /*
1508 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1509 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1510 *
1511 * See Intel spec. 24.4.2 "Guest Non-Register State".
1512 */
1513 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1514 * DR6. */
1515 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1516 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1517 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1518 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1519 if (fPendingDbgMask & fBpHitMask)
1520 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1521 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1522 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1523 }
1524
1525 /*
1526 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1527 *
1528 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1529 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1530 */
1531 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1532 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1533 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1534
1535 /* PDPTEs. */
1536 /* We don't support EPT yet. */
1537 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1538 pVmcs->u64GuestPdpte0.u = 0;
1539 pVmcs->u64GuestPdpte1.u = 0;
1540 pVmcs->u64GuestPdpte2.u = 0;
1541 pVmcs->u64GuestPdpte3.u = 0;
1542}
1543
1544
1545/**
1546 * Saves the guest-state as part of VM-exit.
1547 *
1548 * @returns VBox status code.
1549 * @param pVCpu The cross context virtual CPU structure.
1550 * @param uExitReason The VM-exit reason.
1551 */
1552IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1553{
1554 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1555 Assert(pVmcs);
1556
1557 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1558 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1559
1560 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1561 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1562 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1563
1564 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1565}
1566
1567
1568/**
1569 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1570 *
1571 * @returns VBox status code.
1572 * @param pVCpu The cross context virtual CPU structure.
1573 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1574 */
1575IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1576{
1577 /*
1578 * Save guest MSRs.
1579 * See Intel spec. 27.4 "Saving MSRs".
1580 */
1581 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1582 const char *const pszFailure = "VMX-abort";
1583
1584 /*
1585 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1586 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1587 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1588 */
1589 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1590 if (!cMsrs)
1591 return VINF_SUCCESS;
1592
1593 /*
1594 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1595 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1596 * implementation causes a VMX-abort followed by a triple-fault.
1597 */
1598 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1599 if (fIsMsrCountValid)
1600 { /* likely */ }
1601 else
1602 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1603
1604 /*
1605 * Optimization if the guest hypervisor is using the same guest-physical page for both
1606 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1607 */
1608 PVMXAUTOMSR pMsrArea;
1609 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1610 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1611 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1612 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1613 else
1614 {
1615 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1616 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1617 if (RT_SUCCESS(rc))
1618 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1619 else
1620 {
1621 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1622 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1623 }
1624 }
1625
1626 /*
1627 * Update VM-exit MSR store area.
1628 */
1629 PVMXAUTOMSR pMsr = pMsrArea;
1630 Assert(pMsr);
1631 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1632 {
1633 if ( !pMsr->u32Reserved
1634 && pMsr->u32Msr != MSR_IA32_SMBASE
1635 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1636 {
1637 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1638 if (rcStrict == VINF_SUCCESS)
1639 continue;
1640
1641 /*
1642 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1643 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1644 * recording the MSR index in the auxiliary info. field and indicated further by our
1645 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1646 * if possible, or come up with a better, generic solution.
1647 */
1648 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1649 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1650 ? kVmxVDiag_Vmexit_MsrStoreRing3
1651 : kVmxVDiag_Vmexit_MsrStore;
1652 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1653 }
1654 else
1655 {
1656 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1657 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1658 }
1659 }
1660
1661 /*
1662 * Commit the VM-exit MSR store are to guest memory.
1663 */
1664 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1665 if (RT_SUCCESS(rc))
1666 return VINF_SUCCESS;
1667
1668 NOREF(uExitReason);
1669 NOREF(pszFailure);
1670
1671 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1672 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1673}
1674
1675
1676/**
1677 * Performs a VMX abort (due to an fatal error during VM-exit).
1678 *
1679 * @returns Strict VBox status code.
1680 * @param pVCpu The cross context virtual CPU structure.
1681 * @param enmAbort The VMX abort reason.
1682 */
1683IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1684{
1685 /*
1686 * Perform the VMX abort.
1687 * See Intel spec. 27.7 "VMX Aborts".
1688 */
1689 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1690
1691 /* We don't support SMX yet. */
1692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1693 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1694 {
1695 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1696 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1697 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1698 }
1699
1700 return VINF_EM_TRIPLE_FAULT;
1701}
1702
1703
1704/**
1705 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1706 *
1707 * @param pVCpu The cross context virtual CPU structure.
1708 */
1709IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1710{
1711 /*
1712 * Load host control registers, debug registers and MSRs.
1713 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1714 */
1715 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1716 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1717
1718 /* CR0. */
1719 {
1720 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1721 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1722 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1723 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1724 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1725 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1726 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1727 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1728 }
1729
1730 /* CR4. */
1731 {
1732 /* Fixed CR4 bits are not modified. */
1733 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1734 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1735 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1736 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1737 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1738 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1739 if (fHostInLongMode)
1740 uValidHostCr4 |= X86_CR4_PAE;
1741 else
1742 uValidHostCr4 &= ~X86_CR4_PCIDE;
1743 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1744 }
1745
1746 /* CR3 (host value validated while checking host-state during VM-entry). */
1747 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1748
1749 /* DR7. */
1750 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1751
1752 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1753
1754 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1755 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1756 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1757 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1758
1759 /* FS, GS bases are loaded later while we load host segment registers. */
1760
1761 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1762 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1763 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1764 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1765 {
1766 if (fHostInLongMode)
1767 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1768 else
1769 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1770 }
1771
1772 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1773
1774 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1775 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1776 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1777
1778 /* We don't support IA32_BNDCFGS MSR yet. */
1779}
1780
1781
1782/**
1783 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1784 *
1785 * @param pVCpu The cross context virtual CPU structure.
1786 */
1787IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
1788{
1789 /*
1790 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1791 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1792 *
1793 * Warning! Be careful to not touch fields that are reserved by VT-x,
1794 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1795 */
1796 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1797 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1798
1799 /* CS, SS, ES, DS, FS, GS. */
1800 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1801 {
1802 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1803 bool const fUnusable = RT_BOOL(HostSel == 0);
1804 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1805
1806 /* Selector. */
1807 pSelReg->Sel = HostSel;
1808 pSelReg->ValidSel = HostSel;
1809 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1810
1811 /* Limit. */
1812 pSelReg->u32Limit = 0xffffffff;
1813
1814 /* Base. */
1815 pSelReg->u64Base = 0;
1816
1817 /* Attributes. */
1818 if (iSegReg == X86_SREG_CS)
1819 {
1820 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1821 pSelReg->Attr.n.u1DescType = 1;
1822 pSelReg->Attr.n.u2Dpl = 0;
1823 pSelReg->Attr.n.u1Present = 1;
1824 pSelReg->Attr.n.u1Long = fHostInLongMode;
1825 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1826 pSelReg->Attr.n.u1Granularity = 1;
1827 Assert(!pSelReg->Attr.n.u1Unusable);
1828 Assert(!fUnusable);
1829 }
1830 else
1831 {
1832 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1833 pSelReg->Attr.n.u1DescType = 1;
1834 pSelReg->Attr.n.u2Dpl = 0;
1835 pSelReg->Attr.n.u1Present = 1;
1836 pSelReg->Attr.n.u1DefBig = 1;
1837 pSelReg->Attr.n.u1Granularity = 1;
1838 pSelReg->Attr.n.u1Unusable = fUnusable;
1839 }
1840 }
1841
1842 /* FS base. */
1843 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1844 || fHostInLongMode)
1845 {
1846 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1847 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1848 }
1849
1850 /* GS base. */
1851 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1852 || fHostInLongMode)
1853 {
1854 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1855 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1856 }
1857
1858 /* TR. */
1859 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1860 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1861 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1862 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1863 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1864 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1865 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1869 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1870 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1871 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1872
1873 /* LDTR (Warning! do not touch the base and limits here). */
1874 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1875 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1876 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1877 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1878
1879 /* GDTR. */
1880 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1881 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1882 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1883
1884 /* IDTR.*/
1885 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1886 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1887 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1888}
1889
1890
1891/**
1892 * Checks host PDPTes as part of VM-exit.
1893 *
1894 * @param pVCpu The cross context virtual CPU structure.
1895 * @param uExitReason The VM-exit reason (for logging purposes).
1896 */
1897IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
1898{
1899 /*
1900 * Check host PDPTEs.
1901 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1902 */
1903 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1904 const char *const pszFailure = "VMX-abort";
1905 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1906
1907 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1908 && !fHostInLongMode)
1909 {
1910 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1911 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1912 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1913 if (RT_SUCCESS(rc))
1914 {
1915 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1916 {
1917 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1918 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1919 { /* likely */ }
1920 else
1921 {
1922 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1923 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1924 }
1925 }
1926 }
1927 else
1928 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1929 }
1930
1931 NOREF(pszFailure);
1932 NOREF(uExitReason);
1933 return VINF_SUCCESS;
1934}
1935
1936
1937/**
1938 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1939 *
1940 * @returns VBox status code.
1941 * @param pVCpu The cross context virtual CPU structure.
1942 * @param pszInstr The VMX instruction name (for logging purposes).
1943 */
1944IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1945{
1946 /*
1947 * Load host MSRs.
1948 * See Intel spec. 27.6 "Loading MSRs".
1949 */
1950 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1951 const char *const pszFailure = "VMX-abort";
1952
1953 /*
1954 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1955 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1956 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1957 */
1958 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1959 if (!cMsrs)
1960 return VINF_SUCCESS;
1961
1962 /*
1963 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1964 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1965 * implementation causes a VMX-abort followed by a triple-fault.
1966 */
1967 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1968 if (fIsMsrCountValid)
1969 { /* likely */ }
1970 else
1971 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1972
1973 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1974 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1975 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1976 if (RT_SUCCESS(rc))
1977 {
1978 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1979 Assert(pMsr);
1980 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1981 {
1982 if ( !pMsr->u32Reserved
1983 && pMsr->u32Msr != MSR_K8_FS_BASE
1984 && pMsr->u32Msr != MSR_K8_GS_BASE
1985 && pMsr->u32Msr != MSR_K6_EFER
1986 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1987 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1988 {
1989 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1990 if (rcStrict == VINF_SUCCESS)
1991 continue;
1992
1993 /*
1994 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1995 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1996 * recording the MSR index in the auxiliary info. field and indicated further by our
1997 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1998 * if possible, or come up with a better, generic solution.
1999 */
2000 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2001 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2002 ? kVmxVDiag_Vmexit_MsrLoadRing3
2003 : kVmxVDiag_Vmexit_MsrLoad;
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2005 }
2006 else
2007 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2008 }
2009 }
2010 else
2011 {
2012 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2013 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2014 }
2015
2016 NOREF(uExitReason);
2017 NOREF(pszFailure);
2018 return VINF_SUCCESS;
2019}
2020
2021
2022/**
2023 * Loads the host state as part of VM-exit.
2024 *
2025 * @returns Strict VBox status code.
2026 * @param pVCpu The cross context virtual CPU structure.
2027 * @param uExitReason The VM-exit reason (for logging purposes).
2028 */
2029IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2030{
2031 /*
2032 * Load host state.
2033 * See Intel spec. 27.5 "Loading Host State".
2034 */
2035 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2036 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2037
2038 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2039 if ( CPUMIsGuestInLongMode(pVCpu)
2040 && !fHostInLongMode)
2041 {
2042 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2043 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2044 }
2045
2046 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2047 iemVmxVmexitLoadHostSegRegs(pVCpu);
2048
2049 /*
2050 * Load host RIP, RSP and RFLAGS.
2051 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2052 */
2053 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2054 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2055 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2056
2057 /* Clear address range monitoring. */
2058 EMMonitorWaitClear(pVCpu);
2059
2060 /* Perform the VMX transition (PGM updates). */
2061 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2062 if (rcStrict == VINF_SUCCESS)
2063 {
2064 /* Check host PDPTEs (only when we've fully switched page tables_. */
2065 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2066 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2067 if (RT_FAILURE(rc))
2068 {
2069 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2070 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2071 }
2072 }
2073 else if (RT_SUCCESS(rcStrict))
2074 {
2075 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2076 uExitReason));
2077 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2078 }
2079 else
2080 {
2081 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2082 return VBOXSTRICTRC_VAL(rcStrict);
2083 }
2084
2085 Assert(rcStrict == VINF_SUCCESS);
2086
2087 /* Load MSRs from the VM-exit auto-load MSR area. */
2088 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2089 if (RT_FAILURE(rc))
2090 {
2091 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2092 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2093 }
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * Gets VM-exit instruction information along with any displacement for an
2100 * instruction VM-exit.
2101 *
2102 * @returns The VM-exit instruction information.
2103 * @param pVCpu The cross context virtual CPU structure.
2104 * @param uExitReason The VM-exit reason.
2105 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2106 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2107 * NULL.
2108 */
2109IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2110{
2111 RTGCPTR GCPtrDisp;
2112 VMXEXITINSTRINFO ExitInstrInfo;
2113 ExitInstrInfo.u = 0;
2114
2115 /*
2116 * Get and parse the ModR/M byte from our decoded opcodes.
2117 */
2118 uint8_t bRm;
2119 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2120 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2121 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2122 {
2123 /*
2124 * ModR/M indicates register addressing.
2125 *
2126 * The primary/secondary register operands are reported in the iReg1 or iReg2
2127 * fields depending on whether it is a read/write form.
2128 */
2129 uint8_t idxReg1;
2130 uint8_t idxReg2;
2131 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2132 {
2133 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2134 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2135 }
2136 else
2137 {
2138 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2139 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2140 }
2141 ExitInstrInfo.All.u2Scaling = 0;
2142 ExitInstrInfo.All.iReg1 = idxReg1;
2143 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2144 ExitInstrInfo.All.fIsRegOperand = 1;
2145 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2146 ExitInstrInfo.All.iSegReg = 0;
2147 ExitInstrInfo.All.iIdxReg = 0;
2148 ExitInstrInfo.All.fIdxRegInvalid = 1;
2149 ExitInstrInfo.All.iBaseReg = 0;
2150 ExitInstrInfo.All.fBaseRegInvalid = 1;
2151 ExitInstrInfo.All.iReg2 = idxReg2;
2152
2153 /* Displacement not applicable for register addressing. */
2154 GCPtrDisp = 0;
2155 }
2156 else
2157 {
2158 /*
2159 * ModR/M indicates memory addressing.
2160 */
2161 uint8_t uScale = 0;
2162 bool fBaseRegValid = false;
2163 bool fIdxRegValid = false;
2164 uint8_t iBaseReg = 0;
2165 uint8_t iIdxReg = 0;
2166 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2167 {
2168 /*
2169 * Parse the ModR/M, displacement for 16-bit addressing mode.
2170 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2171 */
2172 uint16_t u16Disp = 0;
2173 uint8_t const offDisp = offModRm + sizeof(bRm);
2174 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2175 {
2176 /* Displacement without any registers. */
2177 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2178 }
2179 else
2180 {
2181 /* Register (index and base). */
2182 switch (bRm & X86_MODRM_RM_MASK)
2183 {
2184 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2185 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2186 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2187 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2188 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2189 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2190 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2191 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2192 }
2193
2194 /* Register + displacement. */
2195 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2196 {
2197 case 0: break;
2198 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2199 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2200 default:
2201 {
2202 /* Register addressing, handled at the beginning. */
2203 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2204 break;
2205 }
2206 }
2207 }
2208
2209 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2210 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2211 }
2212 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2213 {
2214 /*
2215 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2216 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2217 */
2218 uint32_t u32Disp = 0;
2219 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2220 {
2221 /* Displacement without any registers. */
2222 uint8_t const offDisp = offModRm + sizeof(bRm);
2223 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2224 }
2225 else
2226 {
2227 /* Register (and perhaps scale, index and base). */
2228 uint8_t offDisp = offModRm + sizeof(bRm);
2229 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2230 if (iBaseReg == 4)
2231 {
2232 /* An SIB byte follows the ModR/M byte, parse it. */
2233 uint8_t bSib;
2234 uint8_t const offSib = offModRm + sizeof(bRm);
2235 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2236
2237 /* A displacement may follow SIB, update its offset. */
2238 offDisp += sizeof(bSib);
2239
2240 /* Get the scale. */
2241 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2242
2243 /* Get the index register. */
2244 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2245 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2246
2247 /* Get the base register. */
2248 iBaseReg = bSib & X86_SIB_BASE_MASK;
2249 fBaseRegValid = true;
2250 if (iBaseReg == 5)
2251 {
2252 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2253 {
2254 /* Mod is 0 implies a 32-bit displacement with no base. */
2255 fBaseRegValid = false;
2256 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2257 }
2258 else
2259 {
2260 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2261 iBaseReg = X86_GREG_xBP;
2262 }
2263 }
2264 }
2265
2266 /* Register + displacement. */
2267 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2268 {
2269 case 0: /* Handled above */ break;
2270 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2271 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2272 default:
2273 {
2274 /* Register addressing, handled at the beginning. */
2275 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2276 break;
2277 }
2278 }
2279 }
2280
2281 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2282 }
2283 else
2284 {
2285 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2286
2287 /*
2288 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2289 * See Intel instruction spec. 2.2 "IA-32e Mode".
2290 */
2291 uint64_t u64Disp = 0;
2292 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2293 if (fRipRelativeAddr)
2294 {
2295 /*
2296 * RIP-relative addressing mode.
2297 *
2298 * The displacement is 32-bit signed implying an offset range of +/-2G.
2299 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2300 */
2301 uint8_t const offDisp = offModRm + sizeof(bRm);
2302 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2303 }
2304 else
2305 {
2306 uint8_t offDisp = offModRm + sizeof(bRm);
2307
2308 /*
2309 * Register (and perhaps scale, index and base).
2310 *
2311 * REX.B extends the most-significant bit of the base register. However, REX.B
2312 * is ignored while determining whether an SIB follows the opcode. Hence, we
2313 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2314 *
2315 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2316 */
2317 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2318 if (iBaseReg == 4)
2319 {
2320 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2321 uint8_t bSib;
2322 uint8_t const offSib = offModRm + sizeof(bRm);
2323 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2324
2325 /* Displacement may follow SIB, update its offset. */
2326 offDisp += sizeof(bSib);
2327
2328 /* Get the scale. */
2329 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2330
2331 /* Get the index. */
2332 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2333 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2334
2335 /* Get the base. */
2336 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2337 fBaseRegValid = true;
2338 if (iBaseReg == 5)
2339 {
2340 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2341 {
2342 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2343 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2344 }
2345 else
2346 {
2347 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2348 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2349 }
2350 }
2351 }
2352 iBaseReg |= pVCpu->iem.s.uRexB;
2353
2354 /* Register + displacement. */
2355 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2356 {
2357 case 0: /* Handled above */ break;
2358 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2359 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2360 default:
2361 {
2362 /* Register addressing, handled at the beginning. */
2363 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2364 break;
2365 }
2366 }
2367 }
2368
2369 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2370 }
2371
2372 /*
2373 * The primary or secondary register operand is reported in iReg2 depending
2374 * on whether the primary operand is in read/write form.
2375 */
2376 uint8_t idxReg2;
2377 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2378 {
2379 idxReg2 = bRm & X86_MODRM_RM_MASK;
2380 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2381 idxReg2 |= pVCpu->iem.s.uRexB;
2382 }
2383 else
2384 {
2385 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2386 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2387 idxReg2 |= pVCpu->iem.s.uRexReg;
2388 }
2389 ExitInstrInfo.All.u2Scaling = uScale;
2390 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2391 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2392 ExitInstrInfo.All.fIsRegOperand = 0;
2393 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2394 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2395 ExitInstrInfo.All.iIdxReg = iIdxReg;
2396 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2397 ExitInstrInfo.All.iBaseReg = iBaseReg;
2398 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2399 ExitInstrInfo.All.iReg2 = idxReg2;
2400 }
2401
2402 /*
2403 * Handle exceptions to the norm for certain instructions.
2404 * (e.g. some instructions convey an instruction identity in place of iReg2).
2405 */
2406 switch (uExitReason)
2407 {
2408 case VMX_EXIT_GDTR_IDTR_ACCESS:
2409 {
2410 Assert(VMXINSTRID_IS_VALID(uInstrId));
2411 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2412 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2413 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2414 break;
2415 }
2416
2417 case VMX_EXIT_LDTR_TR_ACCESS:
2418 {
2419 Assert(VMXINSTRID_IS_VALID(uInstrId));
2420 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2421 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2422 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2423 break;
2424 }
2425
2426 case VMX_EXIT_RDRAND:
2427 case VMX_EXIT_RDSEED:
2428 {
2429 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2430 break;
2431 }
2432 }
2433
2434 /* Update displacement and return the constructed VM-exit instruction information field. */
2435 if (pGCPtrDisp)
2436 *pGCPtrDisp = GCPtrDisp;
2437
2438 return ExitInstrInfo.u;
2439}
2440
2441
2442/**
2443 * VMX VM-exit handler.
2444 *
2445 * @returns Strict VBox status code.
2446 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2447 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2448 * triple-fault.
2449 *
2450 * @param pVCpu The cross context virtual CPU structure.
2451 * @param uExitReason The VM-exit reason.
2452 * @param u64ExitQual The Exit qualification.
2453 */
2454IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2455{
2456# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2457 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2458 return VINF_EM_RAW_EMULATE_INSTR;
2459# else
2460 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2461 Assert(pVmcs);
2462
2463 /*
2464 * Import all the guest-CPU state.
2465 *
2466 * HM on returning to guest execution would have to reset up a whole lot of state
2467 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2468 * the state and flag reloading the entire state on re-entry. So import the entire
2469 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2470 */
2471 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2472
2473 /* Ensure VM-entry interruption information valid bit isn't set. */
2474 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2475
2476 /*
2477 * Update the VM-exit reason and Exit qualification.
2478 * Other VMCS read-only data fields are expected to be updated by the caller already.
2479 */
2480 pVmcs->u32RoExitReason = uExitReason;
2481 pVmcs->u64RoExitQual.u = u64ExitQual;
2482 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2483 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2484
2485 /*
2486 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2487 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2488 */
2489 {
2490 uint8_t uVector;
2491 uint32_t fFlags;
2492 uint32_t uErrCode;
2493 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2494 if (fInEventDelivery)
2495 {
2496 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2497 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2498 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2499 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2500 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2501 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2502 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2503 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2504 }
2505 }
2506
2507 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2508 Assert(pVmcs->u64RoIoRcx.u == 0);
2509 Assert(pVmcs->u64RoIoRsi.u == 0);
2510 Assert(pVmcs->u64RoIoRdi.u == 0);
2511 Assert(pVmcs->u64RoIoRip.u == 0);
2512
2513 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2514 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2515 {
2516 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2517 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2518 }
2519
2520 /*
2521 * Save the guest state back into the VMCS.
2522 * We only need to save the state when the VM-entry was successful.
2523 */
2524 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2525 if (!fVmentryFailed)
2526 {
2527 /*
2528 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2529 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2530 *
2531 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2532 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2533 * as guest-CPU state would not been modified. Hence for now, we do this only when
2534 * the VM-entry succeeded.
2535 */
2536 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2537 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2538 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2539 {
2540 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2541 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2542 else
2543 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2544 }
2545
2546 /*
2547 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2548 * occurs in enclave mode/SMM which we don't support yet.
2549 *
2550 * If we ever add support for it, we can pass just the lower bits to the functions
2551 * below, till then an assert should suffice.
2552 */
2553 Assert(!RT_HI_U16(uExitReason));
2554
2555 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2556 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2557 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2558 if (RT_SUCCESS(rc))
2559 { /* likely */ }
2560 else
2561 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2562
2563 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2564 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2565 }
2566 else
2567 {
2568 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2569 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2570 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2571 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2572 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2573 }
2574
2575 /*
2576 * Clear any pending VMX nested-guest force-flags.
2577 * These force-flags have no effect on guest execution and will
2578 * be re-evaluated and setup on the next nested-guest VM-entry.
2579 */
2580 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2581 | VMCPU_FF_VMX_MTF
2582 | VMCPU_FF_VMX_APIC_WRITE
2583 | VMCPU_FF_VMX_INT_WINDOW
2584 | VMCPU_FF_VMX_NMI_WINDOW);
2585
2586 /* Restore the host (outer guest) state. */
2587 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2588 if (RT_SUCCESS(rcStrict))
2589 {
2590 Assert(rcStrict == VINF_SUCCESS);
2591 rcStrict = VINF_VMX_VMEXIT;
2592 }
2593 else
2594 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2595
2596 /* Notify HM that we've completed the VM-exit. */
2597 HMNotifyVmxNstGstVmexit(pVCpu, &pVCpu->cpum.GstCtx);
2598
2599 /* We're no longer in nested-guest execution mode. */
2600 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2601
2602# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2603 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2604 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2605 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2606 if (rcSched != VINF_SUCCESS)
2607 iemSetPassUpStatus(pVCpu, rcSched);
2608# endif
2609 return rcStrict;
2610# endif
2611}
2612
2613
2614/**
2615 * VMX VM-exit handler for VM-exits due to instruction execution.
2616 *
2617 * This is intended for instructions where the caller provides all the relevant
2618 * VM-exit information.
2619 *
2620 * @returns Strict VBox status code.
2621 * @param pVCpu The cross context virtual CPU structure.
2622 * @param pExitInfo Pointer to the VM-exit information.
2623 */
2624IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2625{
2626 /*
2627 * For instructions where any of the following fields are not applicable:
2628 * - Exit qualification must be cleared.
2629 * - VM-exit instruction info. is undefined.
2630 * - Guest-linear address is undefined.
2631 * - Guest-physical address is undefined.
2632 *
2633 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2634 * instruction execution. For VM-exits that are not due to instruction execution this
2635 * field is undefined.
2636 *
2637 * In our implementation in IEM, all undefined fields are generally cleared. However,
2638 * if the caller supplies information (from say the physical CPU directly) it is
2639 * then possible that the undefined fields are not cleared.
2640 *
2641 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2642 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2643 */
2644 Assert(pExitInfo);
2645 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2646 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2647 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2648
2649 /* Update all the relevant fields from the VM-exit instruction information struct. */
2650 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2651 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2652 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2653 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2654
2655 /* Perform the VM-exit. */
2656 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2657}
2658
2659
2660/**
2661 * VMX VM-exit handler for VM-exits due to instruction execution.
2662 *
2663 * This is intended for instructions that only provide the VM-exit instruction
2664 * length.
2665 *
2666 * @param pVCpu The cross context virtual CPU structure.
2667 * @param uExitReason The VM-exit reason.
2668 * @param cbInstr The instruction length in bytes.
2669 */
2670IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2671{
2672 VMXVEXITINFO ExitInfo;
2673 RT_ZERO(ExitInfo);
2674 ExitInfo.uReason = uExitReason;
2675 ExitInfo.cbInstr = cbInstr;
2676
2677#ifdef VBOX_STRICT
2678 /*
2679 * To prevent us from shooting ourselves in the foot.
2680 * The follow instructions should convey more than just the instruction length.
2681 */
2682 switch (uExitReason)
2683 {
2684 case VMX_EXIT_INVEPT:
2685 case VMX_EXIT_INVPCID:
2686 case VMX_EXIT_INVVPID:
2687 case VMX_EXIT_LDTR_TR_ACCESS:
2688 case VMX_EXIT_GDTR_IDTR_ACCESS:
2689 case VMX_EXIT_VMCLEAR:
2690 case VMX_EXIT_VMPTRLD:
2691 case VMX_EXIT_VMPTRST:
2692 case VMX_EXIT_VMREAD:
2693 case VMX_EXIT_VMWRITE:
2694 case VMX_EXIT_VMXON:
2695 case VMX_EXIT_XRSTORS:
2696 case VMX_EXIT_XSAVES:
2697 case VMX_EXIT_RDRAND:
2698 case VMX_EXIT_RDSEED:
2699 case VMX_EXIT_IO_INSTR:
2700 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2701 break;
2702 }
2703#endif
2704
2705 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2706}
2707
2708
2709/**
2710 * VMX VM-exit handler for VM-exits due to instruction execution.
2711 *
2712 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2713 * instruction information and Exit qualification fields.
2714 *
2715 * @param pVCpu The cross context virtual CPU structure.
2716 * @param uExitReason The VM-exit reason.
2717 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2718 * @param cbInstr The instruction length in bytes.
2719 *
2720 * @remarks Do not use this for INS/OUTS instruction.
2721 */
2722IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2723{
2724 VMXVEXITINFO ExitInfo;
2725 RT_ZERO(ExitInfo);
2726 ExitInfo.uReason = uExitReason;
2727 ExitInfo.cbInstr = cbInstr;
2728
2729 /*
2730 * Update the Exit qualification field with displacement bytes.
2731 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2732 */
2733 switch (uExitReason)
2734 {
2735 case VMX_EXIT_INVEPT:
2736 case VMX_EXIT_INVPCID:
2737 case VMX_EXIT_INVVPID:
2738 case VMX_EXIT_LDTR_TR_ACCESS:
2739 case VMX_EXIT_GDTR_IDTR_ACCESS:
2740 case VMX_EXIT_VMCLEAR:
2741 case VMX_EXIT_VMPTRLD:
2742 case VMX_EXIT_VMPTRST:
2743 case VMX_EXIT_VMREAD:
2744 case VMX_EXIT_VMWRITE:
2745 case VMX_EXIT_VMXON:
2746 case VMX_EXIT_XRSTORS:
2747 case VMX_EXIT_XSAVES:
2748 case VMX_EXIT_RDRAND:
2749 case VMX_EXIT_RDSEED:
2750 {
2751 /* Construct the VM-exit instruction information. */
2752 RTGCPTR GCPtrDisp;
2753 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2754
2755 /* Update the VM-exit instruction information. */
2756 ExitInfo.InstrInfo.u = uInstrInfo;
2757
2758 /* Update the Exit qualification. */
2759 ExitInfo.u64Qual = GCPtrDisp;
2760 break;
2761 }
2762
2763 default:
2764 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2765 break;
2766 }
2767
2768 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2769}
2770
2771
2772/**
2773 * VMX VM-exit handler for VM-exits due to INVLPG.
2774 *
2775 * @returns Strict VBox status code.
2776 * @param pVCpu The cross context virtual CPU structure.
2777 * @param GCPtrPage The guest-linear address of the page being invalidated.
2778 * @param cbInstr The instruction length in bytes.
2779 */
2780IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2781{
2782 VMXVEXITINFO ExitInfo;
2783 RT_ZERO(ExitInfo);
2784 ExitInfo.uReason = VMX_EXIT_INVLPG;
2785 ExitInfo.cbInstr = cbInstr;
2786 ExitInfo.u64Qual = GCPtrPage;
2787 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2788
2789 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2790}
2791
2792
2793/**
2794 * VMX VM-exit handler for VM-exits due to LMSW.
2795 *
2796 * @returns Strict VBox status code.
2797 * @param pVCpu The cross context virtual CPU structure.
2798 * @param uGuestCr0 The current guest CR0.
2799 * @param pu16NewMsw The machine-status word specified in LMSW's source
2800 * operand. This will be updated depending on the VMX
2801 * guest/host CR0 mask if LMSW is not intercepted.
2802 * @param GCPtrEffDst The guest-linear address of the source operand in case
2803 * of a memory operand. For register operand, pass
2804 * NIL_RTGCPTR.
2805 * @param cbInstr The instruction length in bytes.
2806 */
2807IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2808 uint8_t cbInstr)
2809{
2810 Assert(pu16NewMsw);
2811
2812 uint16_t const uNewMsw = *pu16NewMsw;
2813 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2814 {
2815 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2816
2817 VMXVEXITINFO ExitInfo;
2818 RT_ZERO(ExitInfo);
2819 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2820 ExitInfo.cbInstr = cbInstr;
2821
2822 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2823 if (fMemOperand)
2824 {
2825 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2826 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2827 }
2828
2829 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2830 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2831 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2832 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2833
2834 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2835 }
2836
2837 /*
2838 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2839 * CR0 guest/host mask must be left unmodified.
2840 *
2841 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2842 */
2843 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2844 Assert(pVmcs);
2845 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2846 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2847 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2848
2849 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2850}
2851
2852
2853/**
2854 * VMX VM-exit handler for VM-exits due to CLTS.
2855 *
2856 * @returns Strict VBox status code.
2857 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2858 * VM-exit but must not modify the guest CR0.TS bit.
2859 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2860 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2861 * CR0 fixed bits in VMX operation).
2862 * @param pVCpu The cross context virtual CPU structure.
2863 * @param cbInstr The instruction length in bytes.
2864 */
2865IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
2866{
2867 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2868 Assert(pVmcs);
2869
2870 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2871 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2872
2873 /*
2874 * If CR0.TS is owned by the host:
2875 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2876 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2877 * CLTS instruction completes without clearing CR0.TS.
2878 *
2879 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2880 */
2881 if (fGstHostMask & X86_CR0_TS)
2882 {
2883 if (fReadShadow & X86_CR0_TS)
2884 {
2885 Log2(("clts: Guest intercept -> VM-exit\n"));
2886
2887 VMXVEXITINFO ExitInfo;
2888 RT_ZERO(ExitInfo);
2889 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2890 ExitInfo.cbInstr = cbInstr;
2891 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2892 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2893 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2894 }
2895
2896 return VINF_VMX_MODIFIES_BEHAVIOR;
2897 }
2898
2899 /*
2900 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2901 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2902 */
2903 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2904}
2905
2906
2907/**
2908 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2909 * (CR0/CR4 write).
2910 *
2911 * @returns Strict VBox status code.
2912 * @param pVCpu The cross context virtual CPU structure.
2913 * @param iCrReg The control register (either CR0 or CR4).
2914 * @param uGuestCrX The current guest CR0/CR4.
2915 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2916 * VM-exit is caused.
2917 * @param iGReg The general register from which the CR0/CR4 value is being
2918 * loaded.
2919 * @param cbInstr The instruction length in bytes.
2920 */
2921IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2922 uint8_t cbInstr)
2923{
2924 Assert(puNewCrX);
2925 Assert(iCrReg == 0 || iCrReg == 4);
2926 Assert(iGReg < X86_GREG_COUNT);
2927
2928 uint64_t const uNewCrX = *puNewCrX;
2929 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2930 {
2931 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2932
2933 VMXVEXITINFO ExitInfo;
2934 RT_ZERO(ExitInfo);
2935 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2936 ExitInfo.cbInstr = cbInstr;
2937 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2938 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2939 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2940 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2941 }
2942
2943 /*
2944 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2945 * must not be modified the instruction.
2946 *
2947 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2948 */
2949 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2950 Assert(pVmcs);
2951 uint64_t uGuestCrX;
2952 uint64_t fGstHostMask;
2953 if (iCrReg == 0)
2954 {
2955 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2956 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2957 fGstHostMask = pVmcs->u64Cr0Mask.u;
2958 }
2959 else
2960 {
2961 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2962 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2963 fGstHostMask = pVmcs->u64Cr4Mask.u;
2964 }
2965
2966 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2967 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2968}
2969
2970
2971/**
2972 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2973 *
2974 * @returns VBox strict status code.
2975 * @param pVCpu The cross context virtual CPU structure.
2976 * @param iGReg The general register to which the CR3 value is being stored.
2977 * @param cbInstr The instruction length in bytes.
2978 */
2979IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
2980{
2981 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2982 Assert(pVmcs);
2983 Assert(iGReg < X86_GREG_COUNT);
2984 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2985
2986 /*
2987 * If the CR3-store exiting control is set, we must cause a VM-exit.
2988 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2989 */
2990 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2991 {
2992 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2993
2994 VMXVEXITINFO ExitInfo;
2995 RT_ZERO(ExitInfo);
2996 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2997 ExitInfo.cbInstr = cbInstr;
2998 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2999 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3000 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3001 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3002 }
3003
3004 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3005}
3006
3007
3008/**
3009 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3010 *
3011 * @returns VBox strict status code.
3012 * @param pVCpu The cross context virtual CPU structure.
3013 * @param uNewCr3 The new CR3 value.
3014 * @param iGReg The general register from which the CR3 value is being
3015 * loaded.
3016 * @param cbInstr The instruction length in bytes.
3017 */
3018IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3019{
3020 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3021 Assert(pVmcs);
3022 Assert(iGReg < X86_GREG_COUNT);
3023
3024 /*
3025 * If the CR3-load exiting control is set and the new CR3 value does not
3026 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3027 *
3028 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3029 */
3030 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3031 {
3032 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3033 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3034
3035 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3036 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3037 if (!fIntercept)
3038 {
3039 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3040 {
3041 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3042 if (uNewCr3 != uCr3TargetValue)
3043 {
3044 fIntercept = true;
3045 break;
3046 }
3047 }
3048 }
3049
3050 if (fIntercept)
3051 {
3052 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3053
3054 VMXVEXITINFO ExitInfo;
3055 RT_ZERO(ExitInfo);
3056 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3057 ExitInfo.cbInstr = cbInstr;
3058 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3059 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3060 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3061 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3062 }
3063 }
3064
3065 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3066}
3067
3068
3069/**
3070 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3071 *
3072 * @returns VBox strict status code.
3073 * @param pVCpu The cross context virtual CPU structure.
3074 * @param iGReg The general register to which the CR8 value is being stored.
3075 * @param cbInstr The instruction length in bytes.
3076 */
3077IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3078{
3079 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3080 Assert(pVmcs);
3081 Assert(iGReg < X86_GREG_COUNT);
3082
3083 /*
3084 * If the CR8-store exiting control is set, we must cause a VM-exit.
3085 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3086 */
3087 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3088 {
3089 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3090
3091 VMXVEXITINFO ExitInfo;
3092 RT_ZERO(ExitInfo);
3093 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3094 ExitInfo.cbInstr = cbInstr;
3095 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3096 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3098 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3099 }
3100
3101 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3102}
3103
3104
3105/**
3106 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3107 *
3108 * @returns VBox strict status code.
3109 * @param pVCpu The cross context virtual CPU structure.
3110 * @param iGReg The general register from which the CR8 value is being
3111 * loaded.
3112 * @param cbInstr The instruction length in bytes.
3113 */
3114IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3115{
3116 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3117 Assert(pVmcs);
3118 Assert(iGReg < X86_GREG_COUNT);
3119
3120 /*
3121 * If the CR8-load exiting control is set, we must cause a VM-exit.
3122 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3123 */
3124 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3125 {
3126 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3127
3128 VMXVEXITINFO ExitInfo;
3129 RT_ZERO(ExitInfo);
3130 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3131 ExitInfo.cbInstr = cbInstr;
3132 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3133 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3134 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3135 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3136 }
3137
3138 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3139}
3140
3141
3142/**
3143 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3144 * GReg,DRx' (DRx read).
3145 *
3146 * @returns VBox strict status code.
3147 * @param pVCpu The cross context virtual CPU structure.
3148 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3149 * VMXINSTRID_MOV_FROM_DRX).
3150 * @param iDrReg The debug register being accessed.
3151 * @param iGReg The general register to/from which the DRx value is being
3152 * store/loaded.
3153 * @param cbInstr The instruction length in bytes.
3154 */
3155IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3156 uint8_t cbInstr)
3157{
3158 Assert(iDrReg <= 7);
3159 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3160 Assert(iGReg < X86_GREG_COUNT);
3161
3162 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3163 Assert(pVmcs);
3164
3165 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3166 {
3167 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3168 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3169 VMXVEXITINFO ExitInfo;
3170 RT_ZERO(ExitInfo);
3171 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3172 ExitInfo.cbInstr = cbInstr;
3173 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3175 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3176 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3177 }
3178
3179 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3180}
3181
3182
3183/**
3184 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3185 *
3186 * @returns VBox strict status code.
3187 * @param pVCpu The cross context virtual CPU structure.
3188 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3189 * VMXINSTRID_IO_OUT).
3190 * @param u16Port The I/O port being accessed.
3191 * @param fImm Whether the I/O port was encoded using an immediate operand
3192 * or the implicit DX register.
3193 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3194 * @param cbInstr The instruction length in bytes.
3195 */
3196IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3197 uint8_t cbInstr)
3198{
3199 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3200 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3201
3202 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3203 if (fIntercept)
3204 {
3205 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3206 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3207 VMXVEXITINFO ExitInfo;
3208 RT_ZERO(ExitInfo);
3209 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3210 ExitInfo.cbInstr = cbInstr;
3211 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3212 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3213 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3214 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3215 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3216 }
3217
3218 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3219}
3220
3221
3222/**
3223 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3224 *
3225 * @returns VBox strict status code.
3226 * @param pVCpu The cross context virtual CPU structure.
3227 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3228 * VMXINSTRID_IO_OUTS).
3229 * @param u16Port The I/O port being accessed.
3230 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3231 * @param fRep Whether the instruction has a REP prefix or not.
3232 * @param ExitInstrInfo The VM-exit instruction info. field.
3233 * @param cbInstr The instruction length in bytes.
3234 */
3235IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3236 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3237{
3238 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3239 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3240 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3241 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3242 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3243
3244 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3245 if (fIntercept)
3246 {
3247 /*
3248 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3249 */
3250 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3251 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3252 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3253 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3254 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3255
3256 uint32_t uDirection;
3257 uint64_t uGuestLinearAddr;
3258 if (uInstrId == VMXINSTRID_IO_INS)
3259 {
3260 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3261 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3262 }
3263 else
3264 {
3265 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3266 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3267 }
3268
3269 /*
3270 * If the segment is unusable, the guest-linear address in undefined.
3271 * We shall clear it for consistency.
3272 *
3273 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3274 */
3275 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3276 uGuestLinearAddr = 0;
3277
3278 VMXVEXITINFO ExitInfo;
3279 RT_ZERO(ExitInfo);
3280 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3281 ExitInfo.cbInstr = cbInstr;
3282 ExitInfo.InstrInfo = ExitInstrInfo;
3283 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3284 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3285 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3286 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3287 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3288 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3289 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3290 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3291 }
3292
3293 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3294}
3295
3296
3297/**
3298 * VMX VM-exit handler for VM-exits due to MWAIT.
3299 *
3300 * @returns VBox strict status code.
3301 * @param pVCpu The cross context virtual CPU structure.
3302 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3303 * @param cbInstr The instruction length in bytes.
3304 */
3305IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3306{
3307 VMXVEXITINFO ExitInfo;
3308 RT_ZERO(ExitInfo);
3309 ExitInfo.uReason = VMX_EXIT_MWAIT;
3310 ExitInfo.cbInstr = cbInstr;
3311 ExitInfo.u64Qual = fMonitorHwArmed;
3312 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3313}
3314
3315
3316/**
3317 * VMX VM-exit handler for VM-exits due to PAUSE.
3318 *
3319 * @returns VBox strict status code.
3320 * @param pVCpu The cross context virtual CPU structure.
3321 * @param cbInstr The instruction length in bytes.
3322 */
3323IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3324{
3325 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3326 Assert(pVmcs);
3327
3328 /*
3329 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3330 * "PAUSE-loop exiting" control.
3331 *
3332 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3333 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3334 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3335 * a VM-exit.
3336 *
3337 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3338 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3339 */
3340 bool fIntercept = false;
3341 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3342 fIntercept = true;
3343 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3344 && pVCpu->iem.s.uCpl == 0)
3345 {
3346 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3347
3348 /*
3349 * A previous-PAUSE-tick value of 0 is used to identify the first time
3350 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3351 * consider this to be the first execution of PAUSE in a loop according
3352 * to the Intel.
3353 *
3354 * All subsequent records for the previous-PAUSE-tick we ensure that it
3355 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3356 */
3357 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3358 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3359 uint64_t const uTick = TMCpuTickGet(pVCpu);
3360 uint32_t const uPleGap = pVmcs->u32PleGap;
3361 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3362 if ( *puPrevPauseTick == 0
3363 || uTick - *puPrevPauseTick > uPleGap)
3364 *puFirstPauseLoopTick = uTick;
3365 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3366 fIntercept = true;
3367
3368 *puPrevPauseTick = uTick | 1;
3369 }
3370
3371 if (fIntercept)
3372 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3373
3374 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3375}
3376
3377
3378/**
3379 * VMX VM-exit handler for VM-exits due to task switches.
3380 *
3381 * @returns VBox strict status code.
3382 * @param pVCpu The cross context virtual CPU structure.
3383 * @param enmTaskSwitch The cause of the task switch.
3384 * @param SelNewTss The selector of the new TSS.
3385 * @param cbInstr The instruction length in bytes.
3386 */
3387IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3388{
3389 /*
3390 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3391 *
3392 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3393 * instruction or delivery of the exception generated by one of these instructions
3394 * lead to a task switch through a task gate in the IDT, we need to provide the
3395 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3396 * leaves the VM-exit instruction length field undefined.
3397 *
3398 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3399 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3400 */
3401 Assert(cbInstr <= 15);
3402
3403 uint8_t uType;
3404 switch (enmTaskSwitch)
3405 {
3406 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3407 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3408 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3409 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3410 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3411 }
3412
3413 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3414 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3415 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3416 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3417}
3418
3419
3420/**
3421 * VMX VM-exit handler for VM-exits due to task switches.
3422 *
3423 * This is intended for task switches where the caller provides all the relevant
3424 * VM-exit information.
3425 *
3426 * @returns VBox strict status code.
3427 * @param pVCpu The cross context virtual CPU structure.
3428 * @param pExitInfo Pointer to the VM-exit information.
3429 * @param pExitEventInfo Pointer to the VM-exit event information.
3430 */
3431IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3432 PCVMXVEXITEVENTINFO pExitEventInfo)
3433{
3434 Assert(pExitInfo);
3435 Assert(pExitEventInfo);
3436
3437 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3438 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3439 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3440
3441 /*
3442 * Figure out if an instruction was the source of the task switch.
3443 *
3444 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3445 * of an event generated by a software interrupt (INT-N), privileged software
3446 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3447 * the instruction length.
3448 */
3449 bool fHasInstrLen;
3450 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3451 {
3452 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3453 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3454 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3455 if (fIdtVectInfoValid)
3456 {
3457 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3458 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3459 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3460
3461 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3462 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3463 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3464 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3465 fHasInstrLen = true;
3466 else
3467 fHasInstrLen = false;
3468 }
3469 else
3470 fHasInstrLen = false;
3471 }
3472 else
3473 {
3474 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3475 fHasInstrLen = true;
3476 }
3477
3478 if (fHasInstrLen)
3479 {
3480 Assert(pExitInfo->cbInstr > 0);
3481 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3482 }
3483 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3484}
3485
3486
3487/**
3488 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3489 *
3490 * @returns VBox strict status code.
3491 * @param pVCpu The cross context virtual CPU structure.
3492 */
3493IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3494{
3495 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3496 Assert(pVmcs);
3497
3498 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3499 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3500 {
3501 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3502 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3503
3504 /*
3505 * Calculate the current VMX-preemption timer value.
3506 * Only if the value has reached zero, we cause the VM-exit.
3507 */
3508 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3509 if (!uPreemptTimer)
3510 {
3511 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3512 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3513 pVmcs->u32PreemptTimer = 0;
3514
3515 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3516 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3517 }
3518 }
3519
3520 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3521}
3522
3523
3524/**
3525 * VMX VM-exit handler for VM-exits due to external interrupts.
3526 *
3527 * @returns VBox strict status code.
3528 * @param pVCpu The cross context virtual CPU structure.
3529 * @param uVector The external interrupt vector (pass 0 if the interrupt
3530 * is still pending since we typically won't know the
3531 * vector).
3532 * @param fIntPending Whether the external interrupt is pending or
3533 * acknowledged in the interrupt controller.
3534 */
3535IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3536{
3537 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3538 Assert(pVmcs);
3539 Assert(fIntPending || uVector == 0);
3540
3541 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3542 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3543 * functions require prior checking of a blanket intercept and which don't.
3544 * It is better for the caller to check a blanket intercept performance wise
3545 * than making a function call. Leaving this as a todo because it is more
3546 * a performance issue. */
3547
3548 /* The VM-exit is subject to "External interrupt exiting" being set. */
3549 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3550 {
3551 if (fIntPending)
3552 {
3553 /*
3554 * If the interrupt is pending and we don't need to acknowledge the
3555 * interrupt on VM-exit, cause the VM-exit immediately.
3556 *
3557 * See Intel spec 25.2 "Other Causes Of VM Exits".
3558 */
3559 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3560 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3561
3562 /*
3563 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3564 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3565 * acknowledged that the interrupt has been consumed.
3566 */
3567 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3568 }
3569
3570 /*
3571 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3572 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3573 * all set, we cause the VM-exit now. We need to record the external interrupt that
3574 * just occurred in the VM-exit interruption information field.
3575 *
3576 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3577 */
3578 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3579 {
3580 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3581 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3582 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3583 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3584 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3585 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3586 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3587 }
3588 }
3589
3590 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3591}
3592
3593
3594/**
3595 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3596 * an event.
3597 *
3598 * @returns VBox strict status code.
3599 * @param pVCpu The cross context virtual CPU structure.
3600 */
3601IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3602{
3603 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3604 Assert(pVmcs);
3605
3606 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3607 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3608 {
3609 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3610 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3611 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3612 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3613 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3614 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3615 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3616 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3617 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3618
3619 /*
3620 * A VM-exit is not considered to occur during event delivery when the original
3621 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3622 * using the exception bitmap).
3623 *
3624 * Therefore, we must clear the original event from the IDT-vectoring fields which
3625 * would've been recorded before causing the VM-exit.
3626 *
3627 * 27.2.3 "Information for VM Exits During Event Delivery"
3628 */
3629 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3630 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3631 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3632 }
3633
3634 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3635}
3636
3637
3638/**
3639 * VMX VM-exit handler for VM-exit due to delivery of an events.
3640 *
3641 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3642 * all the relevant VM-exit information.
3643 *
3644 * @returns VBox strict status code.
3645 * @param pVCpu The cross context virtual CPU structure.
3646 * @param pExitInfo Pointer to the VM-exit information.
3647 * @param pExitEventInfo Pointer to the VM-exit event information.
3648 */
3649IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3650{
3651 Assert(pExitInfo);
3652 Assert(pExitEventInfo);
3653 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3654
3655 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3656 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3657 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3658 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3659 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3660 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3661}
3662
3663
3664/**
3665 * VMX VM-exit handler for VM-exits due to delivery of an event.
3666 *
3667 * @returns VBox strict status code.
3668 * @param pVCpu The cross context virtual CPU structure.
3669 * @param uVector The interrupt / exception vector.
3670 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3671 * @param uErrCode The error code associated with the event.
3672 * @param uCr2 The CR2 value in case of a \#PF exception.
3673 * @param cbInstr The instruction length in bytes.
3674 */
3675IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3676 uint8_t cbInstr)
3677{
3678 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3679 Assert(pVmcs);
3680
3681 /*
3682 * If the event is being injected as part of VM-entry, it is -not- subject to event
3683 * intercepts in the nested-guest. However, secondary exceptions that occur during
3684 * injection of any event -are- subject to event interception.
3685 *
3686 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3687 */
3688 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3689 {
3690 /*
3691 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3692 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3693 *
3694 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3695 */
3696 if ( uVector == X86_XCPT_NMI
3697 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3698 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3699 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3700 else
3701 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3702
3703 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3704 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3705 }
3706
3707 /*
3708 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3709 * If not, the caller will continue delivery of the external interrupt as it would
3710 * normally. The interrupt is no longer pending in the interrupt controller at this
3711 * point.
3712 */
3713 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3714 {
3715 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3716 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3717 }
3718
3719 /*
3720 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3721 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3722 * interrupts.
3723 */
3724 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3725 bool fIntercept;
3726 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3727 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3728 {
3729 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3730 }
3731 else
3732 {
3733 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3734 fIntercept = false;
3735 }
3736
3737 /*
3738 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3739 * relevant VM-exit information and cause the VM-exit.
3740 */
3741 if (fIntercept)
3742 {
3743 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3744
3745 /* Construct the rest of the event related information fields and cause the VM-exit. */
3746 uint64_t u64ExitQual;
3747 if (uVector == X86_XCPT_PF)
3748 {
3749 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3750 u64ExitQual = uCr2;
3751 }
3752 else if (uVector == X86_XCPT_DB)
3753 {
3754 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3755 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3756 }
3757 else
3758 u64ExitQual = 0;
3759
3760 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3761 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3762 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3763 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3764 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3765 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3766 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3767 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3768 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3769 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3770
3771 /*
3772 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3773 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3774 * length.
3775 */
3776 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3777 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3778 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3779 else
3780 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3781
3782 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3783 }
3784
3785 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3786}
3787
3788
3789/**
3790 * VMX VM-exit handler for VM-exits due to a triple fault.
3791 *
3792 * @returns VBox strict status code.
3793 * @param pVCpu The cross context virtual CPU structure.
3794 */
3795IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3796{
3797 /*
3798 * A VM-exit is not considered to occur during event delivery when the original
3799 * event results in a triple-fault.
3800 *
3801 * Therefore, we must clear the original event from the IDT-vectoring fields which
3802 * would've been recorded before causing the VM-exit.
3803 *
3804 * 27.2.3 "Information for VM Exits During Event Delivery"
3805 */
3806 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3807 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3808
3809 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
3810}
3811
3812
3813/**
3814 * VMX VM-exit handler for APIC accesses.
3815 *
3816 * @param pVCpu The cross context virtual CPU structure.
3817 * @param offAccess The offset of the register being accessed.
3818 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3819 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3820 */
3821IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
3822{
3823 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3824
3825 VMXAPICACCESS enmAccess;
3826 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3827 if (fInEventDelivery)
3828 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3829 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3830 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3831 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3832 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3833 else
3834 enmAccess = VMXAPICACCESS_LINEAR_READ;
3835
3836 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3837 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3838 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3839}
3840
3841
3842/**
3843 * VMX VM-exit handler for APIC accesses.
3844 *
3845 * This is intended for APIC accesses where the caller provides all the
3846 * relevant VM-exit information.
3847 *
3848 * @returns VBox strict status code.
3849 * @param pVCpu The cross context virtual CPU structure.
3850 * @param pExitInfo Pointer to the VM-exit information.
3851 * @param pExitEventInfo Pointer to the VM-exit event information.
3852 */
3853IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3854 PCVMXVEXITEVENTINFO pExitEventInfo)
3855{
3856 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3857 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3858 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3859 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3860 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3861 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3862 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3863}
3864
3865
3866/**
3867 * VMX VM-exit handler for APIC-write VM-exits.
3868 *
3869 * @param pVCpu The cross context virtual CPU structure.
3870 * @param offApic The write to the virtual-APIC page offset that caused this
3871 * VM-exit.
3872 */
3873IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
3874{
3875 Assert(offApic < XAPIC_OFF_END + 4);
3876 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3877 offApic &= UINT16_C(0xfff);
3878 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3879}
3880
3881
3882/**
3883 * Sets virtual-APIC write emulation as pending.
3884 *
3885 * @param pVCpu The cross context virtual CPU structure.
3886 * @param offApic The offset in the virtual-APIC page that was written.
3887 */
3888DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
3889{
3890 Assert(offApic < XAPIC_OFF_END + 4);
3891
3892 /*
3893 * Record the currently updated APIC offset, as we need this later for figuring
3894 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3895 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3896 */
3897 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3898
3899 /*
3900 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3901 * virtualization or APIC-write emulation).
3902 */
3903 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3904 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3905}
3906
3907
3908/**
3909 * Clears any pending virtual-APIC write emulation.
3910 *
3911 * @returns The virtual-APIC offset that was written before clearing it.
3912 * @param pVCpu The cross context virtual CPU structure.
3913 */
3914DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
3915{
3916 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3917 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3918 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3919 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3920 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3921 return offVirtApicWrite;
3922}
3923
3924
3925/**
3926 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3927 *
3928 * @returns The register from the virtual-APIC page.
3929 * @param pVCpu The cross context virtual CPU structure.
3930 * @param offReg The offset of the register being read.
3931 */
3932IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
3933{
3934 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3935 Assert(pVmcs);
3936
3937 uint32_t uReg;
3938 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3939 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3940 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3941 if (RT_FAILURE(rc))
3942 {
3943 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3944 GCPhysVirtApic));
3945 uReg = 0;
3946 }
3947 return uReg;
3948}
3949
3950
3951/**
3952 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3953 *
3954 * @returns The register from the virtual-APIC page.
3955 * @param pVCpu The cross context virtual CPU structure.
3956 * @param offReg The offset of the register being read.
3957 */
3958IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
3959{
3960 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3961 Assert(pVmcs);
3962
3963 uint64_t uReg;
3964 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3965 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3966 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3967 if (RT_FAILURE(rc))
3968 {
3969 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3970 GCPhysVirtApic));
3971 uReg = 0;
3972 }
3973 return uReg;
3974}
3975
3976
3977/**
3978 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3979 *
3980 * @param pVCpu The cross context virtual CPU structure.
3981 * @param offReg The offset of the register being written.
3982 * @param uReg The register value to write.
3983 */
3984IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
3985{
3986 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3987 Assert(pVmcs);
3988 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3989 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3990 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3991 if (RT_FAILURE(rc))
3992 {
3993 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3994 GCPhysVirtApic));
3995 }
3996}
3997
3998
3999/**
4000 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4001 *
4002 * @param pVCpu The cross context virtual CPU structure.
4003 * @param offReg The offset of the register being written.
4004 * @param uReg The register value to write.
4005 */
4006IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4007{
4008 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4009 Assert(pVmcs);
4010 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
4011 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4012 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4013 if (RT_FAILURE(rc))
4014 {
4015 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
4016 GCPhysVirtApic));
4017 }
4018}
4019
4020
4021/**
4022 * Sets the vector in a virtual-APIC 256-bit sparse register.
4023 *
4024 * @param pVCpu The cross context virtual CPU structure.
4025 * @param offReg The offset of the 256-bit spare register.
4026 * @param uVector The vector to set.
4027 *
4028 * @remarks This is based on our APIC device code.
4029 */
4030IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4031{
4032 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4033 Assert(pVmcs);
4034 uint32_t uReg;
4035 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4036 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4037 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4038 if (RT_SUCCESS(rc))
4039 {
4040 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4041 uReg |= RT_BIT(idxVectorBit);
4042 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4043 if (RT_FAILURE(rc))
4044 {
4045 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4046 uVector, offReg, GCPhysVirtApic));
4047 }
4048 }
4049 else
4050 {
4051 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4052 uVector, offReg, GCPhysVirtApic));
4053 }
4054}
4055
4056
4057/**
4058 * Clears the vector in a virtual-APIC 256-bit sparse register.
4059 *
4060 * @param pVCpu The cross context virtual CPU structure.
4061 * @param offReg The offset of the 256-bit spare register.
4062 * @param uVector The vector to clear.
4063 *
4064 * @remarks This is based on our APIC device code.
4065 */
4066IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4067{
4068 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4069 Assert(pVmcs);
4070 uint32_t uReg;
4071 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4072 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4073 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4074 if (RT_SUCCESS(rc))
4075 {
4076 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4077 uReg &= ~RT_BIT(idxVectorBit);
4078 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4079 if (RT_FAILURE(rc))
4080 {
4081 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4082 uVector, offReg, GCPhysVirtApic));
4083 }
4084 }
4085 else
4086 {
4087 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4088 uVector, offReg, GCPhysVirtApic));
4089 }
4090}
4091
4092
4093/**
4094 * Checks if a memory access to the APIC-access page must causes an APIC-access
4095 * VM-exit.
4096 *
4097 * @param pVCpu The cross context virtual CPU structure.
4098 * @param offAccess The offset of the register being accessed.
4099 * @param cbAccess The size of the access in bytes.
4100 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4101 * IEM_ACCESS_TYPE_WRITE).
4102 *
4103 * @remarks This must not be used for MSR-based APIC-access page accesses!
4104 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4105 */
4106IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4107{
4108 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4109 Assert(pVmcs);
4110 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4111
4112 /*
4113 * We must cause a VM-exit if any of the following are true:
4114 * - TPR shadowing isn't active.
4115 * - The access size exceeds 32-bits.
4116 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4117 *
4118 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4119 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4120 */
4121 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4122 || cbAccess > sizeof(uint32_t)
4123 || ((offAccess + cbAccess - 1) & 0xc)
4124 || offAccess >= XAPIC_OFF_END + 4)
4125 return true;
4126
4127 /*
4128 * If the access is part of an operation where we have already
4129 * virtualized a virtual-APIC write, we must cause a VM-exit.
4130 */
4131 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4132 return true;
4133
4134 /*
4135 * Check write accesses to the APIC-access page that cause VM-exits.
4136 */
4137 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4138 {
4139 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4140 {
4141 /*
4142 * With APIC-register virtualization, a write access to any of the
4143 * following registers are virtualized. Accessing any other register
4144 * causes a VM-exit.
4145 */
4146 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4147 switch (offAlignedAccess)
4148 {
4149 case XAPIC_OFF_ID:
4150 case XAPIC_OFF_TPR:
4151 case XAPIC_OFF_EOI:
4152 case XAPIC_OFF_LDR:
4153 case XAPIC_OFF_DFR:
4154 case XAPIC_OFF_SVR:
4155 case XAPIC_OFF_ESR:
4156 case XAPIC_OFF_ICR_LO:
4157 case XAPIC_OFF_ICR_HI:
4158 case XAPIC_OFF_LVT_TIMER:
4159 case XAPIC_OFF_LVT_THERMAL:
4160 case XAPIC_OFF_LVT_PERF:
4161 case XAPIC_OFF_LVT_LINT0:
4162 case XAPIC_OFF_LVT_LINT1:
4163 case XAPIC_OFF_LVT_ERROR:
4164 case XAPIC_OFF_TIMER_ICR:
4165 case XAPIC_OFF_TIMER_DCR:
4166 break;
4167 default:
4168 return true;
4169 }
4170 }
4171 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4172 {
4173 /*
4174 * With virtual-interrupt delivery, a write access to any of the
4175 * following registers are virtualized. Accessing any other register
4176 * causes a VM-exit.
4177 *
4178 * Note! The specification does not allow writing to offsets in-between
4179 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4180 */
4181 switch (offAccess)
4182 {
4183 case XAPIC_OFF_TPR:
4184 case XAPIC_OFF_EOI:
4185 case XAPIC_OFF_ICR_LO:
4186 break;
4187 default:
4188 return true;
4189 }
4190 }
4191 else
4192 {
4193 /*
4194 * Without APIC-register virtualization or virtual-interrupt delivery,
4195 * only TPR accesses are virtualized.
4196 */
4197 if (offAccess == XAPIC_OFF_TPR)
4198 { /* likely */ }
4199 else
4200 return true;
4201 }
4202 }
4203 else
4204 {
4205 /*
4206 * Check read accesses to the APIC-access page that cause VM-exits.
4207 */
4208 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4209 {
4210 /*
4211 * With APIC-register virtualization, a read access to any of the
4212 * following registers are virtualized. Accessing any other register
4213 * causes a VM-exit.
4214 */
4215 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4216 switch (offAlignedAccess)
4217 {
4218 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4219 case XAPIC_OFF_ID:
4220 case XAPIC_OFF_VERSION:
4221 case XAPIC_OFF_TPR:
4222 case XAPIC_OFF_EOI:
4223 case XAPIC_OFF_LDR:
4224 case XAPIC_OFF_DFR:
4225 case XAPIC_OFF_SVR:
4226 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4227 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4228 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4229 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4230 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4231 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4232 case XAPIC_OFF_ESR:
4233 case XAPIC_OFF_ICR_LO:
4234 case XAPIC_OFF_ICR_HI:
4235 case XAPIC_OFF_LVT_TIMER:
4236 case XAPIC_OFF_LVT_THERMAL:
4237 case XAPIC_OFF_LVT_PERF:
4238 case XAPIC_OFF_LVT_LINT0:
4239 case XAPIC_OFF_LVT_LINT1:
4240 case XAPIC_OFF_LVT_ERROR:
4241 case XAPIC_OFF_TIMER_ICR:
4242 case XAPIC_OFF_TIMER_DCR:
4243 break;
4244 default:
4245 return true;
4246 }
4247 }
4248 else
4249 {
4250 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4251 if (offAccess == XAPIC_OFF_TPR)
4252 { /* likely */ }
4253 else
4254 return true;
4255 }
4256 }
4257
4258 /* The APIC access is virtualized, does not cause a VM-exit. */
4259 return false;
4260}
4261
4262
4263/**
4264 * Virtualizes a memory-based APIC access where the address is not used to access
4265 * memory.
4266 *
4267 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4268 * page-faults but do not use the address to access memory.
4269 *
4270 * @param pVCpu The cross context virtual CPU structure.
4271 * @param pGCPhysAccess Pointer to the guest-physical address used.
4272 */
4273IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4274{
4275 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4276 Assert(pVmcs);
4277 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4278 Assert(pGCPhysAccess);
4279
4280 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4281 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4282 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4283
4284 if (GCPhysAccess == GCPhysApic)
4285 {
4286 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4287 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4288 uint16_t const cbAccess = 1;
4289 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4290 if (fIntercept)
4291 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4292
4293 *pGCPhysAccess = GCPhysApic | offAccess;
4294 return VINF_VMX_MODIFIES_BEHAVIOR;
4295 }
4296
4297 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4298}
4299
4300
4301/**
4302 * Virtualizes a memory-based APIC access.
4303 *
4304 * @returns VBox strict status code.
4305 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4306 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4307 *
4308 * @param pVCpu The cross context virtual CPU structure.
4309 * @param offAccess The offset of the register being accessed (within the
4310 * APIC-access page).
4311 * @param cbAccess The size of the access in bytes.
4312 * @param pvData Pointer to the data being written or where to store the data
4313 * being read.
4314 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4315 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4316 */
4317IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4318 uint32_t fAccess)
4319{
4320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4321 Assert(pVmcs);
4322 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4323 Assert(pvData);
4324 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4325 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4326 || (fAccess & IEM_ACCESS_INSTRUCTION));
4327
4328 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4329 if (fIntercept)
4330 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4331
4332 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4333 {
4334 /*
4335 * A write access to the APIC-access page that is virtualized (rather than
4336 * causing a VM-exit) writes data to the virtual-APIC page.
4337 */
4338 uint32_t const u32Data = *(uint32_t *)pvData;
4339 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4340
4341 /*
4342 * Record the currently updated APIC offset, as we need this later for figuring
4343 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4344 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4345 *
4346 * After completion of the current operation, we need to perform TPR virtualization,
4347 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4348 *
4349 * The current operation may be a REP-prefixed string instruction, execution of any
4350 * other instruction, or delivery of an event through the IDT.
4351 *
4352 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4353 * performed now but later after completion of the current operation.
4354 *
4355 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4356 */
4357 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4358 }
4359 else
4360 {
4361 /*
4362 * A read access from the APIC-access page that is virtualized (rather than
4363 * causing a VM-exit) returns data from the virtual-APIC page.
4364 *
4365 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4366 */
4367 Assert(cbAccess <= 4);
4368 Assert(offAccess < XAPIC_OFF_END + 4);
4369 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4370
4371 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4372 u32Data &= s_auAccessSizeMasks[cbAccess];
4373 *(uint32_t *)pvData = u32Data;
4374 }
4375
4376 return VINF_VMX_MODIFIES_BEHAVIOR;
4377}
4378
4379
4380/**
4381 * Virtualizes an MSR-based APIC read access.
4382 *
4383 * @returns VBox strict status code.
4384 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4385 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4386 * handled by the x2APIC device.
4387 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4388 * not within the range of valid MSRs, caller must raise \#GP(0).
4389 * @param pVCpu The cross context virtual CPU structure.
4390 * @param idMsr The x2APIC MSR being read.
4391 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4392 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4393 */
4394IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4395{
4396 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4397 Assert(pVmcs);
4398 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4399 Assert(pu64Value);
4400
4401 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4402 {
4403 /*
4404 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4405 * what the end of the valid x2APIC MSR range is. Hence the use of different
4406 * macros here.
4407 *
4408 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4409 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4410 */
4411 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4412 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4413 {
4414 uint16_t const offReg = (idMsr & 0xff) << 4;
4415 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4416 *pu64Value = u64Value;
4417 return VINF_VMX_MODIFIES_BEHAVIOR;
4418 }
4419 return VERR_OUT_OF_RANGE;
4420 }
4421
4422 if (idMsr == MSR_IA32_X2APIC_TPR)
4423 {
4424 uint16_t const offReg = (idMsr & 0xff) << 4;
4425 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4426 *pu64Value = u64Value;
4427 return VINF_VMX_MODIFIES_BEHAVIOR;
4428 }
4429
4430 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4431}
4432
4433
4434/**
4435 * Virtualizes an MSR-based APIC write access.
4436 *
4437 * @returns VBox strict status code.
4438 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4439 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4440 * not within the range of valid MSRs, caller must raise \#GP(0).
4441 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4442 *
4443 * @param pVCpu The cross context virtual CPU structure.
4444 * @param idMsr The x2APIC MSR being written.
4445 * @param u64Value The value of the x2APIC MSR being written.
4446 */
4447IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4448{
4449 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4450 Assert(pVmcs);
4451
4452 /*
4453 * Check if the access is to be virtualized.
4454 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4455 */
4456 if ( idMsr == MSR_IA32_X2APIC_TPR
4457 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4458 && ( idMsr == MSR_IA32_X2APIC_EOI
4459 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4460 {
4461 /* Validate the MSR write depending on the register. */
4462 switch (idMsr)
4463 {
4464 case MSR_IA32_X2APIC_TPR:
4465 case MSR_IA32_X2APIC_SELF_IPI:
4466 {
4467 if (u64Value & UINT64_C(0xffffffffffffff00))
4468 return VERR_OUT_OF_RANGE;
4469 break;
4470 }
4471 case MSR_IA32_X2APIC_EOI:
4472 {
4473 if (u64Value != 0)
4474 return VERR_OUT_OF_RANGE;
4475 break;
4476 }
4477 }
4478
4479 /* Write the MSR to the virtual-APIC page. */
4480 uint16_t const offReg = (idMsr & 0xff) << 4;
4481 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4482
4483 /*
4484 * Record the currently updated APIC offset, as we need this later for figuring
4485 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4486 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4487 */
4488 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4489
4490 return VINF_VMX_MODIFIES_BEHAVIOR;
4491 }
4492
4493 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4494}
4495
4496
4497/**
4498 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4499 *
4500 * @returns VBox status code.
4501 * @retval VINF_SUCCESS when the highest set bit is found.
4502 * @retval VERR_NOT_FOUND when no bit is set.
4503 *
4504 * @param pVCpu The cross context virtual CPU structure.
4505 * @param offReg The offset of the APIC 256-bit sparse register.
4506 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4507 * set in the register. Only valid when VINF_SUCCESS is
4508 * returned.
4509 *
4510 * @remarks The format of the 256-bit sparse register here mirrors that found in
4511 * real APIC hardware.
4512 */
4513static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4514{
4515 Assert(offReg < XAPIC_OFF_END + 4);
4516 Assert(pidxHighestBit);
4517 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4518
4519 /*
4520 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4521 * However, in each fragment only the first 4 bytes are used.
4522 */
4523 uint8_t const cFrags = 8;
4524 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4525 {
4526 uint16_t const offFrag = iFrag * 16;
4527 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4528 if (!u32Frag)
4529 continue;
4530
4531 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4532 Assert(idxHighestBit > 0);
4533 --idxHighestBit;
4534 Assert(idxHighestBit <= UINT8_MAX);
4535 *pidxHighestBit = idxHighestBit;
4536 return VINF_SUCCESS;
4537 }
4538 return VERR_NOT_FOUND;
4539}
4540
4541
4542/**
4543 * Evaluates pending virtual interrupts.
4544 *
4545 * @param pVCpu The cross context virtual CPU structure.
4546 */
4547IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4548{
4549 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4550 Assert(pVmcs);
4551 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4552
4553 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4554 {
4555 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4556 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4557
4558 if ((uRvi >> 4) > (uPpr >> 4))
4559 {
4560 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4561 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4562 }
4563 else
4564 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4565 }
4566}
4567
4568
4569/**
4570 * Performs PPR virtualization.
4571 *
4572 * @returns VBox strict status code.
4573 * @param pVCpu The cross context virtual CPU structure.
4574 */
4575IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4576{
4577 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4578 Assert(pVmcs);
4579 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4580 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4581
4582 /*
4583 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4584 * or EOI-virtualization.
4585 *
4586 * See Intel spec. 29.1.3 "PPR Virtualization".
4587 */
4588 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4589 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4590
4591 uint32_t uPpr;
4592 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4593 uPpr = uTpr & 0xff;
4594 else
4595 uPpr = uSvi & 0xf0;
4596
4597 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4598 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4599}
4600
4601
4602/**
4603 * Performs VMX TPR virtualization.
4604 *
4605 * @returns VBox strict status code.
4606 * @param pVCpu The cross context virtual CPU structure.
4607 */
4608IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4609{
4610 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4611 Assert(pVmcs);
4612 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4613
4614 /*
4615 * We should have already performed the virtual-APIC write to the TPR offset
4616 * in the virtual-APIC page. We now perform TPR virtualization.
4617 *
4618 * See Intel spec. 29.1.2 "TPR Virtualization".
4619 */
4620 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4621 {
4622 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4623 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4624
4625 /*
4626 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4627 * See Intel spec. 29.1.2 "TPR Virtualization".
4628 */
4629 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4630 {
4631 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4632 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4633 }
4634 }
4635 else
4636 {
4637 iemVmxPprVirtualization(pVCpu);
4638 iemVmxEvalPendingVirtIntrs(pVCpu);
4639 }
4640
4641 return VINF_SUCCESS;
4642}
4643
4644
4645/**
4646 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4647 * not.
4648 *
4649 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4650 * @param pVCpu The cross context virtual CPU structure.
4651 * @param uVector The interrupt that was acknowledged using an EOI.
4652 */
4653IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4654{
4655 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4656 Assert(pVmcs);
4657 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4658
4659 if (uVector < 64)
4660 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4661 if (uVector < 128)
4662 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4663 if (uVector < 192)
4664 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4665 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4666}
4667
4668
4669/**
4670 * Performs EOI virtualization.
4671 *
4672 * @returns VBox strict status code.
4673 * @param pVCpu The cross context virtual CPU structure.
4674 */
4675IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4676{
4677 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4678 Assert(pVmcs);
4679 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4680
4681 /*
4682 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4683 * and get the next guest-interrupt that's in-service (if any).
4684 *
4685 * See Intel spec. 29.1.4 "EOI Virtualization".
4686 */
4687 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4688 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4689 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4690
4691 uint8_t uVector = uSvi;
4692 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4693
4694 uVector = 0;
4695 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4696
4697 if (uVector)
4698 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4699 else
4700 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4701
4702 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4703 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4704
4705 iemVmxPprVirtualization(pVCpu);
4706 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4707 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4708 iemVmxEvalPendingVirtIntrs(pVCpu);
4709 return VINF_SUCCESS;
4710}
4711
4712
4713/**
4714 * Performs self-IPI virtualization.
4715 *
4716 * @returns VBox strict status code.
4717 * @param pVCpu The cross context virtual CPU structure.
4718 */
4719IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4720{
4721 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4722 Assert(pVmcs);
4723 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4724
4725 /*
4726 * We should have already performed the virtual-APIC write to the self-IPI offset
4727 * in the virtual-APIC page. We now perform self-IPI virtualization.
4728 *
4729 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4730 */
4731 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4732 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4733 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4734 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4735 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4736 if (uVector > uRvi)
4737 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4738 iemVmxEvalPendingVirtIntrs(pVCpu);
4739 return VINF_SUCCESS;
4740}
4741
4742
4743/**
4744 * Performs VMX APIC-write emulation.
4745 *
4746 * @returns VBox strict status code.
4747 * @param pVCpu The cross context virtual CPU structure.
4748 */
4749IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4750{
4751 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4752 Assert(pVmcs);
4753
4754 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4755 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4756
4757 /*
4758 * Perform APIC-write emulation based on the virtual-APIC register written.
4759 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4760 */
4761 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4762 VBOXSTRICTRC rcStrict;
4763 switch (offApicWrite)
4764 {
4765 case XAPIC_OFF_TPR:
4766 {
4767 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4768 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4769 uTpr &= UINT32_C(0x000000ff);
4770 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4771 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4772 rcStrict = iemVmxTprVirtualization(pVCpu);
4773 break;
4774 }
4775
4776 case XAPIC_OFF_EOI:
4777 {
4778 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4779 {
4780 /* Clear VEOI and perform EOI virtualization. */
4781 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4782 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4783 rcStrict = iemVmxEoiVirtualization(pVCpu);
4784 }
4785 else
4786 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4787 break;
4788 }
4789
4790 case XAPIC_OFF_ICR_LO:
4791 {
4792 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4793 {
4794 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4795 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4796 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4797 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4798 if ( !(uIcrLo & fIcrLoMb0)
4799 && (uIcrLo & fIcrLoMb1))
4800 {
4801 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4802 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4803 }
4804 else
4805 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4806 }
4807 else
4808 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4809 break;
4810 }
4811
4812 case XAPIC_OFF_ICR_HI:
4813 {
4814 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4815 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4816 uIcrHi &= UINT32_C(0xff000000);
4817 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4818 rcStrict = VINF_SUCCESS;
4819 break;
4820 }
4821
4822 default:
4823 {
4824 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4825 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4826 break;
4827 }
4828 }
4829
4830 return rcStrict;
4831}
4832
4833
4834/**
4835 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4836 *
4837 * @param pVCpu The cross context virtual CPU structure.
4838 * @param pszInstr The VMX instruction name (for logging purposes).
4839 */
4840IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
4841{
4842 /*
4843 * Guest Control Registers, Debug Registers, and MSRs.
4844 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4845 */
4846 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4847 const char *const pszFailure = "VM-exit";
4848 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4849
4850 /* CR0 reserved bits. */
4851 {
4852 /* CR0 MB1 bits. */
4853 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4854 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4855 if (fUnrestrictedGuest)
4856 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4857 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4858 { /* likely */ }
4859 else
4860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4861
4862 /* CR0 MBZ bits. */
4863 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4864 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4865 { /* likely */ }
4866 else
4867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4868
4869 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4870 if ( !fUnrestrictedGuest
4871 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4872 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4874 }
4875
4876 /* CR4 reserved bits. */
4877 {
4878 /* CR4 MB1 bits. */
4879 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4880 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4881 { /* likely */ }
4882 else
4883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4884
4885 /* CR4 MBZ bits. */
4886 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4887 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4888 { /* likely */ }
4889 else
4890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4891 }
4892
4893 /* DEBUGCTL MSR. */
4894 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4895 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4896 { /* likely */ }
4897 else
4898 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4899
4900 /* 64-bit CPU checks. */
4901 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4902 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4903 {
4904 if (fGstInLongMode)
4905 {
4906 /* PAE must be set. */
4907 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4908 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4909 { /* likely */ }
4910 else
4911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4912 }
4913 else
4914 {
4915 /* PCIDE should not be set. */
4916 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4917 { /* likely */ }
4918 else
4919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4920 }
4921
4922 /* CR3. */
4923 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4924 { /* likely */ }
4925 else
4926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4927
4928 /* DR7. */
4929 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4930 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4931 { /* likely */ }
4932 else
4933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4934
4935 /* SYSENTER ESP and SYSENTER EIP. */
4936 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4937 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4938 { /* likely */ }
4939 else
4940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4941 }
4942
4943 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4944 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4945
4946 /* PAT MSR. */
4947 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4948 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4949 { /* likely */ }
4950 else
4951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4952
4953 /* EFER MSR. */
4954 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4955 {
4956 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4957 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4958 { /* likely */ }
4959 else
4960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4961
4962 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4963 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4964 if ( fGstLma == fGstInLongMode
4965 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4966 || fGstLma == fGstLme))
4967 { /* likely */ }
4968 else
4969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4970 }
4971
4972 /* We don't support IA32_BNDCFGS MSR yet. */
4973 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4974
4975 NOREF(pszInstr);
4976 NOREF(pszFailure);
4977 return VINF_SUCCESS;
4978}
4979
4980
4981/**
4982 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4983 *
4984 * @param pVCpu The cross context virtual CPU structure.
4985 * @param pszInstr The VMX instruction name (for logging purposes).
4986 */
4987IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4988{
4989 /*
4990 * Segment registers.
4991 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4992 */
4993 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4994 const char *const pszFailure = "VM-exit";
4995 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4996 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4997 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4998
4999 /* Selectors. */
5000 if ( !fGstInV86Mode
5001 && !fUnrestrictedGuest
5002 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5003 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5004
5005 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5006 {
5007 CPUMSELREG SelReg;
5008 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5009 if (RT_LIKELY(rc == VINF_SUCCESS))
5010 { /* likely */ }
5011 else
5012 return rc;
5013
5014 /*
5015 * Virtual-8086 mode checks.
5016 */
5017 if (fGstInV86Mode)
5018 {
5019 /* Base address. */
5020 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5021 { /* likely */ }
5022 else
5023 {
5024 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5026 }
5027
5028 /* Limit. */
5029 if (SelReg.u32Limit == 0xffff)
5030 { /* likely */ }
5031 else
5032 {
5033 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5035 }
5036
5037 /* Attribute. */
5038 if (SelReg.Attr.u == 0xf3)
5039 { /* likely */ }
5040 else
5041 {
5042 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5044 }
5045
5046 /* We're done; move to checking the next segment. */
5047 continue;
5048 }
5049
5050 /* Checks done by 64-bit CPUs. */
5051 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5052 {
5053 /* Base address. */
5054 if ( iSegReg == X86_SREG_FS
5055 || iSegReg == X86_SREG_GS)
5056 {
5057 if (X86_IS_CANONICAL(SelReg.u64Base))
5058 { /* likely */ }
5059 else
5060 {
5061 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5063 }
5064 }
5065 else if (iSegReg == X86_SREG_CS)
5066 {
5067 if (!RT_HI_U32(SelReg.u64Base))
5068 { /* likely */ }
5069 else
5070 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5071 }
5072 else
5073 {
5074 if ( SelReg.Attr.n.u1Unusable
5075 || !RT_HI_U32(SelReg.u64Base))
5076 { /* likely */ }
5077 else
5078 {
5079 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5081 }
5082 }
5083 }
5084
5085 /*
5086 * Checks outside Virtual-8086 mode.
5087 */
5088 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5089 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5090 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5091 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5092 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5093 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5094 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5095 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5096
5097 /* Code or usable segment. */
5098 if ( iSegReg == X86_SREG_CS
5099 || fUsable)
5100 {
5101 /* Reserved bits (bits 31:17 and bits 11:8). */
5102 if (!(SelReg.Attr.u & 0xfffe0f00))
5103 { /* likely */ }
5104 else
5105 {
5106 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5108 }
5109
5110 /* Descriptor type. */
5111 if (fCodeDataSeg)
5112 { /* likely */ }
5113 else
5114 {
5115 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5116 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5117 }
5118
5119 /* Present. */
5120 if (fPresent)
5121 { /* likely */ }
5122 else
5123 {
5124 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5126 }
5127
5128 /* Granularity. */
5129 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5130 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5131 { /* likely */ }
5132 else
5133 {
5134 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5136 }
5137 }
5138
5139 if (iSegReg == X86_SREG_CS)
5140 {
5141 /* Segment Type and DPL. */
5142 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5143 && fUnrestrictedGuest)
5144 {
5145 if (uDpl == 0)
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5149 }
5150 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5151 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5152 {
5153 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5154 if (uDpl == AttrSs.n.u2Dpl)
5155 { /* likely */ }
5156 else
5157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5158 }
5159 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5160 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5161 {
5162 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5163 if (uDpl <= AttrSs.n.u2Dpl)
5164 { /* likely */ }
5165 else
5166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5167 }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5170
5171 /* Def/Big. */
5172 if ( fGstInLongMode
5173 && fSegLong)
5174 {
5175 if (uDefBig == 0)
5176 { /* likely */ }
5177 else
5178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5179 }
5180 }
5181 else if (iSegReg == X86_SREG_SS)
5182 {
5183 /* Segment Type. */
5184 if ( !fUsable
5185 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5186 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5190
5191 /* DPL. */
5192 if (!fUnrestrictedGuest)
5193 {
5194 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5195 { /* likely */ }
5196 else
5197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5198 }
5199 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5200 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5201 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5202 {
5203 if (uDpl == 0)
5204 { /* likely */ }
5205 else
5206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5207 }
5208 }
5209 else
5210 {
5211 /* DS, ES, FS, GS. */
5212 if (fUsable)
5213 {
5214 /* Segment type. */
5215 if (uSegType & X86_SEL_TYPE_ACCESSED)
5216 { /* likely */ }
5217 else
5218 {
5219 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5221 }
5222
5223 if ( !(uSegType & X86_SEL_TYPE_CODE)
5224 || (uSegType & X86_SEL_TYPE_READ))
5225 { /* likely */ }
5226 else
5227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5228
5229 /* DPL. */
5230 if ( !fUnrestrictedGuest
5231 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5232 {
5233 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5234 { /* likely */ }
5235 else
5236 {
5237 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5239 }
5240 }
5241 }
5242 }
5243 }
5244
5245 /*
5246 * LDTR.
5247 */
5248 {
5249 CPUMSELREG Ldtr;
5250 Ldtr.Sel = pVmcs->GuestLdtr;
5251 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5252 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5253 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5254
5255 if (!Ldtr.Attr.n.u1Unusable)
5256 {
5257 /* Selector. */
5258 if (!(Ldtr.Sel & X86_SEL_LDT))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5262
5263 /* Base. */
5264 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5265 {
5266 if (X86_IS_CANONICAL(Ldtr.u64Base))
5267 { /* likely */ }
5268 else
5269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5270 }
5271
5272 /* Attributes. */
5273 /* Reserved bits (bits 31:17 and bits 11:8). */
5274 if (!(Ldtr.Attr.u & 0xfffe0f00))
5275 { /* likely */ }
5276 else
5277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5278
5279 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5280 { /* likely */ }
5281 else
5282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5283
5284 if (!Ldtr.Attr.n.u1DescType)
5285 { /* likely */ }
5286 else
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5288
5289 if (Ldtr.Attr.n.u1Present)
5290 { /* likely */ }
5291 else
5292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5293
5294 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5295 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5296 { /* likely */ }
5297 else
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5299 }
5300 }
5301
5302 /*
5303 * TR.
5304 */
5305 {
5306 CPUMSELREG Tr;
5307 Tr.Sel = pVmcs->GuestTr;
5308 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5309 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5310 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5311
5312 /* Selector. */
5313 if (!(Tr.Sel & X86_SEL_LDT))
5314 { /* likely */ }
5315 else
5316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5317
5318 /* Base. */
5319 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5320 {
5321 if (X86_IS_CANONICAL(Tr.u64Base))
5322 { /* likely */ }
5323 else
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5325 }
5326
5327 /* Attributes. */
5328 /* Reserved bits (bits 31:17 and bits 11:8). */
5329 if (!(Tr.Attr.u & 0xfffe0f00))
5330 { /* likely */ }
5331 else
5332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5333
5334 if (!Tr.Attr.n.u1Unusable)
5335 { /* likely */ }
5336 else
5337 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5338
5339 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5340 || ( !fGstInLongMode
5341 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5342 { /* likely */ }
5343 else
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5345
5346 if (!Tr.Attr.n.u1DescType)
5347 { /* likely */ }
5348 else
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5350
5351 if (Tr.Attr.n.u1Present)
5352 { /* likely */ }
5353 else
5354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5355
5356 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5357 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5358 { /* likely */ }
5359 else
5360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5361 }
5362
5363 NOREF(pszInstr);
5364 NOREF(pszFailure);
5365 return VINF_SUCCESS;
5366}
5367
5368
5369/**
5370 * Checks guest GDTR and IDTR as part of VM-entry.
5371 *
5372 * @param pVCpu The cross context virtual CPU structure.
5373 * @param pszInstr The VMX instruction name (for logging purposes).
5374 */
5375IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5376{
5377 /*
5378 * GDTR and IDTR.
5379 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5380 */
5381 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5382 const char *const pszFailure = "VM-exit";
5383
5384 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5385 {
5386 /* Base. */
5387 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5388 { /* likely */ }
5389 else
5390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5391
5392 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5393 { /* likely */ }
5394 else
5395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5396 }
5397
5398 /* Limit. */
5399 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5400 { /* likely */ }
5401 else
5402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5403
5404 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5405 { /* likely */ }
5406 else
5407 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5408
5409 NOREF(pszInstr);
5410 NOREF(pszFailure);
5411 return VINF_SUCCESS;
5412}
5413
5414
5415/**
5416 * Checks guest RIP and RFLAGS as part of VM-entry.
5417 *
5418 * @param pVCpu The cross context virtual CPU structure.
5419 * @param pszInstr The VMX instruction name (for logging purposes).
5420 */
5421IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5422{
5423 /*
5424 * RIP and RFLAGS.
5425 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5426 */
5427 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5428 const char *const pszFailure = "VM-exit";
5429 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5430
5431 /* RIP. */
5432 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5433 {
5434 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5435 if ( !fGstInLongMode
5436 || !AttrCs.n.u1Long)
5437 {
5438 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5439 { /* likely */ }
5440 else
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5442 }
5443
5444 if ( fGstInLongMode
5445 && AttrCs.n.u1Long)
5446 {
5447 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5448 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5449 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5450 { /* likely */ }
5451 else
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5453 }
5454 }
5455
5456 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5457 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5458 : pVmcs->u64GuestRFlags.s.Lo;
5459 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5460 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5461 { /* likely */ }
5462 else
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5464
5465 if ( fGstInLongMode
5466 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5467 {
5468 if (!(uGuestRFlags & X86_EFL_VM))
5469 { /* likely */ }
5470 else
5471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5472 }
5473
5474 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5475 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5476 {
5477 if (uGuestRFlags & X86_EFL_IF)
5478 { /* likely */ }
5479 else
5480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5481 }
5482
5483 NOREF(pszInstr);
5484 NOREF(pszFailure);
5485 return VINF_SUCCESS;
5486}
5487
5488
5489/**
5490 * Checks guest non-register state as part of VM-entry.
5491 *
5492 * @param pVCpu The cross context virtual CPU structure.
5493 * @param pszInstr The VMX instruction name (for logging purposes).
5494 */
5495IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5496{
5497 /*
5498 * Guest non-register state.
5499 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5500 */
5501 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5502 const char *const pszFailure = "VM-exit";
5503
5504 /*
5505 * Activity state.
5506 */
5507 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5508 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5509 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5510 { /* likely */ }
5511 else
5512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5513
5514 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5515 if ( !AttrSs.n.u2Dpl
5516 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5517 { /* likely */ }
5518 else
5519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5520
5521 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5522 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5523 {
5524 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5525 { /* likely */ }
5526 else
5527 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5528 }
5529
5530 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5531 {
5532 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5533 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5534 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5535 switch (pVmcs->u32GuestActivityState)
5536 {
5537 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5538 {
5539 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5540 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5541 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5542 && ( uVector == X86_XCPT_DB
5543 || uVector == X86_XCPT_MC))
5544 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5545 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5549 break;
5550 }
5551
5552 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5553 {
5554 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5555 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5556 && uVector == X86_XCPT_MC))
5557 { /* likely */ }
5558 else
5559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5560 break;
5561 }
5562
5563 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5564 default:
5565 break;
5566 }
5567 }
5568
5569 /*
5570 * Interruptibility state.
5571 */
5572 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5573 { /* likely */ }
5574 else
5575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5576
5577 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5578 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5579 { /* likely */ }
5580 else
5581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5582
5583 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5584 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5588
5589 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5590 {
5591 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5592 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5593 {
5594 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5598 }
5599 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5600 {
5601 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5602 { /* likely */ }
5603 else
5604 {
5605 /*
5606 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5607 * We update the Exit qualification only when blocking-by-STI is set
5608 * without blocking-by-MovSS being set. Although in practise it does not
5609 * make much difference since the order of checks are implementation defined.
5610 */
5611 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5612 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5614 }
5615
5616 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5617 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5621 }
5622 }
5623
5624 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5625 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5629
5630 /* We don't support SGX yet. So enclave-interruption must not be set. */
5631 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5635
5636 /*
5637 * Pending debug exceptions.
5638 */
5639 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5640 ? pVmcs->u64GuestPendingDbgXcpt.u
5641 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5642 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5643 { /* likely */ }
5644 else
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5646
5647 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5648 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5649 {
5650 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5651 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5652 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5654
5655 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5656 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5657 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5658 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5659 }
5660
5661 /* We don't support RTM (Real-time Transactional Memory) yet. */
5662 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5663 { /* likely */ }
5664 else
5665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5666
5667 /*
5668 * VMCS link pointer.
5669 */
5670 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5671 {
5672 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5673 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5674 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5675 { /* likely */ }
5676 else
5677 {
5678 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5680 }
5681
5682 /* Validate the address. */
5683 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5684 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5685 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5686 { /* likely */ }
5687 else
5688 {
5689 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5691 }
5692
5693 /* Read the VMCS-link pointer from guest memory. */
5694 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5695 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5696 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5697 if (RT_SUCCESS(rc))
5698 { /* likely */ }
5699 else
5700 {
5701 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5703 }
5704
5705 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5706 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5707 { /* likely */ }
5708 else
5709 {
5710 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5711 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5712 }
5713
5714 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5715 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5716 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5717 { /* likely */ }
5718 else
5719 {
5720 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5722 }
5723
5724 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5725 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5726 }
5727
5728 NOREF(pszInstr);
5729 NOREF(pszFailure);
5730 return VINF_SUCCESS;
5731}
5732
5733
5734/**
5735 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5736 * VM-entry.
5737 *
5738 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5739 * @param pVCpu The cross context virtual CPU structure.
5740 * @param pszInstr The VMX instruction name (for logging purposes).
5741 * @param pVmcs Pointer to the virtual VMCS.
5742 */
5743IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5744{
5745 /*
5746 * Check PDPTEs.
5747 * See Intel spec. 4.4.1 "PDPTE Registers".
5748 */
5749 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5750 const char *const pszFailure = "VM-exit";
5751
5752 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5753 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5754 if (RT_SUCCESS(rc))
5755 {
5756 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5757 {
5758 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5759 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5760 { /* likely */ }
5761 else
5762 {
5763 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5764 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5766 }
5767 }
5768 }
5769 else
5770 {
5771 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5772 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5773 }
5774
5775 NOREF(pszFailure);
5776 NOREF(pszInstr);
5777 return rc;
5778}
5779
5780
5781/**
5782 * Checks guest PDPTEs as part of VM-entry.
5783 *
5784 * @param pVCpu The cross context virtual CPU structure.
5785 * @param pszInstr The VMX instruction name (for logging purposes).
5786 */
5787IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5788{
5789 /*
5790 * Guest PDPTEs.
5791 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5792 */
5793 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5794 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5795
5796 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5797 int rc;
5798 if ( !fGstInLongMode
5799 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5800 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5801 {
5802 /*
5803 * We don't support nested-paging for nested-guests yet.
5804 *
5805 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5806 * rather we need to check the PDPTEs referenced by the guest CR3.
5807 */
5808 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5809 }
5810 else
5811 rc = VINF_SUCCESS;
5812 return rc;
5813}
5814
5815
5816/**
5817 * Checks guest-state as part of VM-entry.
5818 *
5819 * @returns VBox status code.
5820 * @param pVCpu The cross context virtual CPU structure.
5821 * @param pszInstr The VMX instruction name (for logging purposes).
5822 */
5823IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5824{
5825 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5826 if (RT_SUCCESS(rc))
5827 {
5828 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5829 if (RT_SUCCESS(rc))
5830 {
5831 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5832 if (RT_SUCCESS(rc))
5833 {
5834 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5835 if (RT_SUCCESS(rc))
5836 {
5837 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5838 if (RT_SUCCESS(rc))
5839 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5840 }
5841 }
5842 }
5843 }
5844 return rc;
5845}
5846
5847
5848/**
5849 * Checks host-state as part of VM-entry.
5850 *
5851 * @returns VBox status code.
5852 * @param pVCpu The cross context virtual CPU structure.
5853 * @param pszInstr The VMX instruction name (for logging purposes).
5854 */
5855IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
5856{
5857 /*
5858 * Host Control Registers and MSRs.
5859 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5860 */
5861 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5862 const char * const pszFailure = "VMFail";
5863
5864 /* CR0 reserved bits. */
5865 {
5866 /* CR0 MB1 bits. */
5867 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5868 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5872
5873 /* CR0 MBZ bits. */
5874 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5875 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5879 }
5880
5881 /* CR4 reserved bits. */
5882 {
5883 /* CR4 MB1 bits. */
5884 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5885 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5886 { /* likely */ }
5887 else
5888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5889
5890 /* CR4 MBZ bits. */
5891 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5892 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5893 { /* likely */ }
5894 else
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5896 }
5897
5898 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5899 {
5900 /* CR3 reserved bits. */
5901 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5902 { /* likely */ }
5903 else
5904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5905
5906 /* SYSENTER ESP and SYSENTER EIP. */
5907 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5908 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5909 { /* likely */ }
5910 else
5911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5912 }
5913
5914 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5915 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5916
5917 /* PAT MSR. */
5918 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5919 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5923
5924 /* EFER MSR. */
5925 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5926 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5927 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5931
5932 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5933 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5934 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5935 if ( fHostInLongMode == fHostLma
5936 && fHostInLongMode == fHostLme)
5937 { /* likely */ }
5938 else
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5940
5941 /*
5942 * Host Segment and Descriptor-Table Registers.
5943 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5944 */
5945 /* Selector RPL and TI. */
5946 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5947 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5948 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5949 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5950 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5951 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5952 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5956
5957 /* CS and TR selectors cannot be 0. */
5958 if ( pVmcs->HostCs
5959 && pVmcs->HostTr)
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5963
5964 /* SS cannot be 0 if 32-bit host. */
5965 if ( fHostInLongMode
5966 || pVmcs->HostSs)
5967 { /* likely */ }
5968 else
5969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5970
5971 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5972 {
5973 /* FS, GS, GDTR, IDTR, TR base address. */
5974 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5975 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5976 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5977 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5978 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5979 { /* likely */ }
5980 else
5981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5982 }
5983
5984 /*
5985 * Host address-space size for 64-bit CPUs.
5986 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5987 */
5988 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5989 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5990 {
5991 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5992
5993 /* Logical processor in IA-32e mode. */
5994 if (fCpuInLongMode)
5995 {
5996 if (fHostInLongMode)
5997 {
5998 /* PAE must be set. */
5999 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6003
6004 /* RIP must be canonical. */
6005 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6006 { /* likely */ }
6007 else
6008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6009 }
6010 else
6011 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6012 }
6013 else
6014 {
6015 /* Logical processor is outside IA-32e mode. */
6016 if ( !fGstInLongMode
6017 && !fHostInLongMode)
6018 {
6019 /* PCIDE should not be set. */
6020 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6021 { /* likely */ }
6022 else
6023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6024
6025 /* The high 32-bits of RIP MBZ. */
6026 if (!pVmcs->u64HostRip.s.Hi)
6027 { /* likely */ }
6028 else
6029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6030 }
6031 else
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6033 }
6034 }
6035 else
6036 {
6037 /* Host address-space size for 32-bit CPUs. */
6038 if ( !fGstInLongMode
6039 && !fHostInLongMode)
6040 { /* likely */ }
6041 else
6042 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6043 }
6044
6045 NOREF(pszInstr);
6046 NOREF(pszFailure);
6047 return VINF_SUCCESS;
6048}
6049
6050
6051/**
6052 * Checks VM-entry controls fields as part of VM-entry.
6053 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6054 *
6055 * @returns VBox status code.
6056 * @param pVCpu The cross context virtual CPU structure.
6057 * @param pszInstr The VMX instruction name (for logging purposes).
6058 */
6059IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6060{
6061 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6062 const char * const pszFailure = "VMFail";
6063
6064 /* VM-entry controls. */
6065 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6066 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6067 { /* likely */ }
6068 else
6069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6070
6071 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6072 { /* likely */ }
6073 else
6074 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6075
6076 /* Event injection. */
6077 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6078 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6079 {
6080 /* Type and vector. */
6081 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6082 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6083 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6084 if ( !uRsvd
6085 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6086 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6087 { /* likely */ }
6088 else
6089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6090
6091 /* Exception error code. */
6092 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6093 {
6094 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6095 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6096 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6100
6101 /* Exceptions that provide an error code. */
6102 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6103 && ( uVector == X86_XCPT_DF
6104 || uVector == X86_XCPT_TS
6105 || uVector == X86_XCPT_NP
6106 || uVector == X86_XCPT_SS
6107 || uVector == X86_XCPT_GP
6108 || uVector == X86_XCPT_PF
6109 || uVector == X86_XCPT_AC))
6110 { /* likely */ }
6111 else
6112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6113
6114 /* Exception error-code reserved bits. */
6115 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6116 { /* likely */ }
6117 else
6118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6119
6120 /* Injecting a software interrupt, software exception or privileged software exception. */
6121 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6122 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6123 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6124 {
6125 /* Instruction length must be in the range 0-15. */
6126 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6127 { /* likely */ }
6128 else
6129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6130
6131 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6132 if ( pVmcs->u32EntryInstrLen == 0
6133 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6134 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6135 }
6136 }
6137 }
6138
6139 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6140 if (pVmcs->u32EntryMsrLoadCount)
6141 {
6142 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6143 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6144 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6148 }
6149
6150 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6151 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6152
6153 NOREF(pszInstr);
6154 NOREF(pszFailure);
6155 return VINF_SUCCESS;
6156}
6157
6158
6159/**
6160 * Checks VM-exit controls fields as part of VM-entry.
6161 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6162 *
6163 * @returns VBox status code.
6164 * @param pVCpu The cross context virtual CPU structure.
6165 * @param pszInstr The VMX instruction name (for logging purposes).
6166 */
6167IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6168{
6169 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6170 const char * const pszFailure = "VMFail";
6171
6172 /* VM-exit controls. */
6173 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6174 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6175 { /* likely */ }
6176 else
6177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6178
6179 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6180 { /* likely */ }
6181 else
6182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6183
6184 /* Save preemption timer without activating it. */
6185 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6186 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6190
6191 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6192 if (pVmcs->u32ExitMsrStoreCount)
6193 {
6194 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6195 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6196 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6200 }
6201
6202 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6203 if (pVmcs->u32ExitMsrLoadCount)
6204 {
6205 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6206 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6207 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6208 { /* likely */ }
6209 else
6210 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6211 }
6212
6213 NOREF(pszInstr);
6214 NOREF(pszFailure);
6215 return VINF_SUCCESS;
6216}
6217
6218
6219/**
6220 * Checks VM-execution controls fields as part of VM-entry.
6221 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6222 *
6223 * @returns VBox status code.
6224 * @param pVCpu The cross context virtual CPU structure.
6225 * @param pszInstr The VMX instruction name (for logging purposes).
6226 *
6227 * @remarks This may update secondary-processor based VM-execution control fields
6228 * in the current VMCS if necessary.
6229 */
6230IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6231{
6232 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6233 const char * const pszFailure = "VMFail";
6234
6235 /* Pin-based VM-execution controls. */
6236 {
6237 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6238 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6239 { /* likely */ }
6240 else
6241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6242
6243 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6247 }
6248
6249 /* Processor-based VM-execution controls. */
6250 {
6251 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6252 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6256
6257 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6261 }
6262
6263 /* Secondary processor-based VM-execution controls. */
6264 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6265 {
6266 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6267 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6268 { /* likely */ }
6269 else
6270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6271
6272 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6273 { /* likely */ }
6274 else
6275 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6276 }
6277 else
6278 Assert(!pVmcs->u32ProcCtls2);
6279
6280 /* CR3-target count. */
6281 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6282 { /* likely */ }
6283 else
6284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6285
6286 /* I/O bitmaps physical addresses. */
6287 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6288 {
6289 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6290 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6291 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6292 { /* likely */ }
6293 else
6294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6295
6296 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6297 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6298 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6299 { /* likely */ }
6300 else
6301 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6302 }
6303
6304 /* MSR bitmap physical address. */
6305 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6306 {
6307 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6308 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6309 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6310 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6311 { /* likely */ }
6312 else
6313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6314
6315 /* Read the MSR bitmap. */
6316 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6317 * implementing fast path. */
6318 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6319 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6320 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6321 if (RT_SUCCESS(rc))
6322 { /* likely */ }
6323 else
6324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6325 }
6326
6327 /* TPR shadow related controls. */
6328 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6329 {
6330 /* Virtual-APIC page physical address. */
6331 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6332 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6333 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6334 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6335 { /* likely */ }
6336 else
6337 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6338
6339 /* TPR threshold without virtual-interrupt delivery. */
6340 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6341 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6343
6344 /* TPR threshold and VTPR. */
6345 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6346 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6347 {
6348 /* Read the VTPR from the virtual-APIC page. */
6349 uint8_t u8VTpr;
6350 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6351 if (RT_SUCCESS(rc))
6352 { /* likely */ }
6353 else
6354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6355
6356 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6357 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6361 }
6362 }
6363 else
6364 {
6365 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6366 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6367 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6368 { /* likely */ }
6369 else
6370 {
6371 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6373 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6375 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6377 }
6378 }
6379
6380 /* NMI exiting and virtual-NMIs. */
6381 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6382 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6383 { /* likely */ }
6384 else
6385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6386
6387 /* Virtual-NMIs and NMI-window exiting. */
6388 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6389 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6390 { /* likely */ }
6391 else
6392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6393
6394 /* Virtualize APIC accesses. */
6395 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6396 {
6397 /* APIC-access physical address. */
6398 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6399 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6400 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6401 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6402 { /* likely */ }
6403 else
6404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6405
6406 /*
6407 * Disallow APIC-access page and virtual-APIC page from being the same address.
6408 * Note! This is not an Intel requirement, but one imposed by our implementation.
6409 */
6410 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6411 * redirecting accesses between the APIC-access page and the virtual-APIC
6412 * page. If any guest hypervisor requires this, we can implement it later. */
6413 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6414 {
6415 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6416 if (GCPhysVirtApic != GCPhysApicAccess)
6417 { /* likely */ }
6418 else
6419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6420 }
6421
6422 /*
6423 * Register the handler for the APIC-access page.
6424 *
6425 * We don't deregister the APIC-access page handler during the VM-exit as a different
6426 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6427 *
6428 * We leave the page registered until the first access that happens outside VMX non-root
6429 * mode. Guest software is allowed to access structures such as the APIC-access page
6430 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6431 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6432 *
6433 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6434 */
6435 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6436 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6437 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6438 if (RT_SUCCESS(rc))
6439 { /* likely */ }
6440 else
6441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6442 }
6443
6444 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6445 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6446 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6447 { /* likely */ }
6448 else
6449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6450
6451 /* Virtual-interrupt delivery requires external interrupt exiting. */
6452 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6453 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6454 { /* likely */ }
6455 else
6456 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6457
6458 /* VPID. */
6459 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6460 || pVmcs->u16Vpid != 0)
6461 { /* likely */ }
6462 else
6463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6464
6465 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6466 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6467 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6468 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6469 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6470 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6471 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6472
6473 /* VMCS shadowing. */
6474 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6475 {
6476 /* VMREAD-bitmap physical address. */
6477 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6478 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6479 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6480 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6481 { /* likely */ }
6482 else
6483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6484
6485 /* VMWRITE-bitmap physical address. */
6486 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6487 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6488 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6489 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6490 { /* likely */ }
6491 else
6492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6493
6494 /* Read the VMREAD-bitmap. */
6495 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6496 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6497 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6498 if (RT_SUCCESS(rc))
6499 { /* likely */ }
6500 else
6501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6502
6503 /* Read the VMWRITE-bitmap. */
6504 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6505 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6506 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6507 if (RT_SUCCESS(rc))
6508 { /* likely */ }
6509 else
6510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6511 }
6512
6513 NOREF(pszInstr);
6514 NOREF(pszFailure);
6515 return VINF_SUCCESS;
6516}
6517
6518
6519/**
6520 * Loads the guest control registers, debug register and some MSRs as part of
6521 * VM-entry.
6522 *
6523 * @param pVCpu The cross context virtual CPU structure.
6524 */
6525IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6526{
6527 /*
6528 * Load guest control registers, debug registers and MSRs.
6529 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6530 */
6531 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6532
6533 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6534 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6535 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6536 CPUMSetGuestCR0(pVCpu, uGstCr0);
6537 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6538 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6539
6540 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6541 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6542
6543 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6544 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6545 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6546
6547 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6548 {
6549 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6550
6551 /* EFER MSR. */
6552 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6553 {
6554 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6555 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6556 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6557 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6558 if (fGstInLongMode)
6559 {
6560 /* If the nested-guest is in long mode, LMA and LME are both set. */
6561 Assert(fGstPaging);
6562 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6563 }
6564 else
6565 {
6566 /*
6567 * If the nested-guest is outside long mode:
6568 * - With paging: LMA is cleared, LME is cleared.
6569 * - Without paging: LMA is cleared, LME is left unmodified.
6570 */
6571 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6572 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6573 }
6574 }
6575 /* else: see below. */
6576 }
6577
6578 /* PAT MSR. */
6579 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6580 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6581
6582 /* EFER MSR. */
6583 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6584 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6585
6586 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6587 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6588
6589 /* We don't support IA32_BNDCFGS MSR yet. */
6590 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6591
6592 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6593}
6594
6595
6596/**
6597 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6598 *
6599 * @param pVCpu The cross context virtual CPU structure.
6600 */
6601IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6602{
6603 /*
6604 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6605 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6606 */
6607 /* CS, SS, ES, DS, FS, GS. */
6608 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6609 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6610 {
6611 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6612 CPUMSELREG VmcsSelReg;
6613 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6614 AssertRC(rc); NOREF(rc);
6615 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6616 {
6617 pGstSelReg->Sel = VmcsSelReg.Sel;
6618 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6619 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6620 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6621 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6622 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6623 }
6624 else
6625 {
6626 pGstSelReg->Sel = VmcsSelReg.Sel;
6627 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6628 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6629 switch (iSegReg)
6630 {
6631 case X86_SREG_CS:
6632 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6633 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6634 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6635 break;
6636
6637 case X86_SREG_SS:
6638 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6639 pGstSelReg->u32Limit = 0;
6640 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6641 break;
6642
6643 case X86_SREG_ES:
6644 case X86_SREG_DS:
6645 pGstSelReg->u64Base = 0;
6646 pGstSelReg->u32Limit = 0;
6647 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6648 break;
6649
6650 case X86_SREG_FS:
6651 case X86_SREG_GS:
6652 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6653 pGstSelReg->u32Limit = 0;
6654 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6655 break;
6656 }
6657 Assert(pGstSelReg->Attr.n.u1Unusable);
6658 }
6659 }
6660
6661 /* LDTR. */
6662 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6663 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6664 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6665 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6666 {
6667 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6668 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6669 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6670 }
6671 else
6672 {
6673 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6674 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6675 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6676 }
6677
6678 /* TR. */
6679 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6680 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6681 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6682 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6683 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6684 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6685 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6686
6687 /* GDTR. */
6688 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6689 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6690
6691 /* IDTR. */
6692 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6693 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6694}
6695
6696
6697/**
6698 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6699 *
6700 * @returns VBox status code.
6701 * @param pVCpu The cross context virtual CPU structure.
6702 * @param pszInstr The VMX instruction name (for logging purposes).
6703 */
6704IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6705{
6706 /*
6707 * Load guest MSRs.
6708 * See Intel spec. 26.4 "Loading MSRs".
6709 */
6710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6711 const char *const pszFailure = "VM-exit";
6712
6713 /*
6714 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6715 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6716 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6717 */
6718 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6719 if (!cMsrs)
6720 return VINF_SUCCESS;
6721
6722 /*
6723 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6724 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6725 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6726 */
6727 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6728 if (fIsMsrCountValid)
6729 { /* likely */ }
6730 else
6731 {
6732 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6734 }
6735
6736 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6737 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6738 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6739 if (RT_SUCCESS(rc))
6740 {
6741 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6742 Assert(pMsr);
6743 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6744 {
6745 if ( !pMsr->u32Reserved
6746 && pMsr->u32Msr != MSR_K8_FS_BASE
6747 && pMsr->u32Msr != MSR_K8_GS_BASE
6748 && pMsr->u32Msr != MSR_K6_EFER
6749 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6750 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6751 {
6752 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6753 if (rcStrict == VINF_SUCCESS)
6754 continue;
6755
6756 /*
6757 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6758 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6759 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6760 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6761 * MSR in ring-0 if possible, or come up with a better, generic solution.
6762 */
6763 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6764 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6765 ? kVmxVDiag_Vmentry_MsrLoadRing3
6766 : kVmxVDiag_Vmentry_MsrLoad;
6767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6768 }
6769 else
6770 {
6771 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6772 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6773 }
6774 }
6775 }
6776 else
6777 {
6778 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6780 }
6781
6782 NOREF(pszInstr);
6783 NOREF(pszFailure);
6784 return VINF_SUCCESS;
6785}
6786
6787
6788/**
6789 * Loads the guest-state non-register state as part of VM-entry.
6790 *
6791 * @returns VBox status code.
6792 * @param pVCpu The cross context virtual CPU structure.
6793 *
6794 * @remarks This must be called only after loading the nested-guest register state
6795 * (especially nested-guest RIP).
6796 */
6797IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6798{
6799 /*
6800 * Load guest non-register state.
6801 * See Intel spec. 26.6 "Special Features of VM Entry"
6802 */
6803 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6804
6805 /*
6806 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6807 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6808 *
6809 * See Intel spec. 26.6.1 "Interruptibility State".
6810 */
6811 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6812 if ( !fEntryVectoring
6813 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6814 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6815 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6816 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6817
6818 /* NMI blocking. */
6819 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6820 {
6821 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6822 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6823 else
6824 {
6825 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6826 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6827 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6828 }
6829 }
6830 else
6831 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6832
6833 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6834
6835 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6836 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6837
6838 /* VPID is irrelevant. We don't support VPID yet. */
6839
6840 /* Clear address-range monitoring. */
6841 EMMonitorWaitClear(pVCpu);
6842}
6843
6844
6845/**
6846 * Loads the guest-state as part of VM-entry.
6847 *
6848 * @returns VBox status code.
6849 * @param pVCpu The cross context virtual CPU structure.
6850 * @param pszInstr The VMX instruction name (for logging purposes).
6851 *
6852 * @remarks This must be done after all the necessary steps prior to loading of
6853 * guest-state (e.g. checking various VMCS state).
6854 */
6855IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6856{
6857 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6858 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6859
6860 /*
6861 * Load guest RIP, RSP and RFLAGS.
6862 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6863 */
6864 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6865 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6866 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6867 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6868
6869 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6870 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6871 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6872
6873 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6874
6875 NOREF(pszInstr);
6876 return VINF_SUCCESS;
6877}
6878
6879
6880/**
6881 * Returns whether there are is a pending debug exception on VM-entry.
6882 *
6883 * @param pVCpu The cross context virtual CPU structure.
6884 * @param pszInstr The VMX instruction name (for logging purposes).
6885 */
6886IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6887{
6888 /*
6889 * Pending debug exceptions.
6890 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6891 */
6892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6893 Assert(pVmcs);
6894
6895 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6896 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6897 if (fPendingDbgXcpt)
6898 {
6899 uint8_t uEntryIntInfoType;
6900 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6901 if (fEntryVectoring)
6902 {
6903 switch (uEntryIntInfoType)
6904 {
6905 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6906 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6907 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6908 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6909 fPendingDbgXcpt = false;
6910 break;
6911
6912 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6913 {
6914 /*
6915 * Whether the pending debug exception for software exceptions other than
6916 * #BP and #OF is delivered after injecting the exception or is discard
6917 * is CPU implementation specific. We will discard them (easier).
6918 */
6919 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6920 if ( uVector != X86_XCPT_BP
6921 && uVector != X86_XCPT_OF)
6922 fPendingDbgXcpt = false;
6923 RT_FALL_THRU();
6924 }
6925 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6926 {
6927 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6928 fPendingDbgXcpt = false;
6929 break;
6930 }
6931 }
6932 }
6933 else
6934 {
6935 /*
6936 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6937 * pending debug exception is held pending or is discarded is CPU implementation
6938 * specific. We will discard them (easier).
6939 */
6940 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6941 fPendingDbgXcpt = false;
6942
6943 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6944 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6945 fPendingDbgXcpt = false;
6946 }
6947 }
6948
6949 NOREF(pszInstr);
6950 return fPendingDbgXcpt;
6951}
6952
6953
6954/**
6955 * Set up the monitor-trap flag (MTF).
6956 *
6957 * @param pVCpu The cross context virtual CPU structure.
6958 * @param pszInstr The VMX instruction name (for logging purposes).
6959 */
6960IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
6961{
6962 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6963 Assert(pVmcs);
6964 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6965 {
6966 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6967 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6968 }
6969 else
6970 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6971 NOREF(pszInstr);
6972}
6973
6974
6975/**
6976 * Sets up NMI-window exiting.
6977 *
6978 * @param pVCpu The cross context virtual CPU structure.
6979 * @param pszInstr The VMX instruction name (for logging purposes).
6980 */
6981IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
6982{
6983 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6984 Assert(pVmcs);
6985 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6986 {
6987 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6988 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6989 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6990 }
6991 else
6992 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6993 NOREF(pszInstr);
6994}
6995
6996
6997/**
6998 * Sets up interrupt-window exiting.
6999 *
7000 * @param pVCpu The cross context virtual CPU structure.
7001 * @param pszInstr The VMX instruction name (for logging purposes).
7002 */
7003IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
7004{
7005 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7006 Assert(pVmcs);
7007 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7008 {
7009 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7010 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7011 }
7012 else
7013 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7014 NOREF(pszInstr);
7015}
7016
7017
7018/**
7019 * Set up the VMX-preemption timer.
7020 *
7021 * @param pVCpu The cross context virtual CPU structure.
7022 * @param pszInstr The VMX instruction name (for logging purposes).
7023 */
7024IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7025{
7026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7027 Assert(pVmcs);
7028 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7029 {
7030 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7031 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7032 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7033
7034 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7035 }
7036 else
7037 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7038
7039 NOREF(pszInstr);
7040}
7041
7042
7043/**
7044 * Injects an event using TRPM given a VM-entry interruption info. and related
7045 * fields.
7046 *
7047 * @returns VBox status code.
7048 * @param pVCpu The cross context virtual CPU structure.
7049 * @param uEntryIntInfo The VM-entry interruption info.
7050 * @param uErrCode The error code associated with the event if any.
7051 * @param cbInstr The VM-entry instruction length (for software
7052 * interrupts and software exceptions). Pass 0
7053 * otherwise.
7054 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7055 */
7056IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7057 RTGCUINTPTR GCPtrFaultAddress)
7058{
7059 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7060
7061 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7062 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7063 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7064
7065 TRPMEVENT enmTrapType;
7066 switch (uType)
7067 {
7068 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7069 enmTrapType = TRPM_HARDWARE_INT;
7070 break;
7071
7072 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7073 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7074 enmTrapType = TRPM_TRAP;
7075 break;
7076
7077 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7078 enmTrapType = TRPM_SOFTWARE_INT;
7079 break;
7080
7081 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7082 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7083 enmTrapType = TRPM_SOFTWARE_INT;
7084 break;
7085
7086 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7087 Assert(uVector == X86_XCPT_DB);
7088 enmTrapType = TRPM_SOFTWARE_INT;
7089 break;
7090
7091 default:
7092 /* Shouldn't really happen. */
7093 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7094 break;
7095 }
7096
7097 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7098 AssertRCReturn(rc, rc);
7099
7100 if (fErrCodeValid)
7101 TRPMSetErrorCode(pVCpu, uErrCode);
7102
7103 if ( enmTrapType == TRPM_TRAP
7104 && uVector == X86_XCPT_PF)
7105 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7106 else if (enmTrapType == TRPM_SOFTWARE_INT)
7107 TRPMSetInstrLength(pVCpu, cbInstr);
7108
7109 return VINF_SUCCESS;
7110}
7111
7112
7113/**
7114 * Performs event injection (if any) as part of VM-entry.
7115 *
7116 * @param pVCpu The cross context virtual CPU structure.
7117 * @param pszInstr The VMX instruction name (for logging purposes).
7118 */
7119IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7120{
7121 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7122
7123 /*
7124 * Inject events.
7125 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7126 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7127 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7128 * the actually delivery of this event.
7129 *
7130 * See Intel spec. 26.5 "Event Injection".
7131 */
7132 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7133 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7134
7135 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7136 if (fEntryIntInfoValid)
7137 {
7138 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7139 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7140 {
7141 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7142 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7143 return VINF_SUCCESS;
7144 }
7145
7146 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7147 pVCpu->cpum.GstCtx.cr2);
7148 if (RT_SUCCESS(rc))
7149 {
7150 /*
7151 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7152 *
7153 * However, we do it here on VM-entry because while it continues to not be visible to
7154 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7155 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7156 * information field.
7157 *
7158 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7159 */
7160 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7161 }
7162 return rc;
7163 }
7164
7165 /*
7166 * Inject any pending guest debug exception.
7167 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7168 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7169 */
7170 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7171 if (fPendingDbgXcpt)
7172 {
7173 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7174 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7175 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7176 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7177 0 /* GCPtrFaultAddress */);
7178 }
7179
7180 NOREF(pszInstr);
7181 return VINF_SUCCESS;
7182}
7183
7184
7185/**
7186 * Initializes all read-only VMCS fields as part of VM-entry.
7187 *
7188 * @param pVCpu The cross context virtual CPU structure.
7189 */
7190IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7191{
7192 /*
7193 * Any VMCS field which we do not establish on every VM-exit but may potentially
7194 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7195 * specified to be undefined needs to be initialized here.
7196 *
7197 * Thus, it is especially important to clear the Exit qualification field
7198 * since it must be zero for VM-exits where it is not used. Similarly, the
7199 * VM-exit interruption information field's valid bit needs to be cleared for
7200 * the same reasons.
7201 */
7202 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7203 Assert(pVmcs);
7204
7205 /* 16-bit (none currently). */
7206 /* 32-bit. */
7207 pVmcs->u32RoVmInstrError = 0;
7208 pVmcs->u32RoExitReason = 0;
7209 pVmcs->u32RoExitIntInfo = 0;
7210 pVmcs->u32RoExitIntErrCode = 0;
7211 pVmcs->u32RoIdtVectoringInfo = 0;
7212 pVmcs->u32RoIdtVectoringErrCode = 0;
7213 pVmcs->u32RoExitInstrLen = 0;
7214 pVmcs->u32RoExitInstrInfo = 0;
7215
7216 /* 64-bit. */
7217 pVmcs->u64RoGuestPhysAddr.u = 0;
7218
7219 /* Natural-width. */
7220 pVmcs->u64RoExitQual.u = 0;
7221 pVmcs->u64RoIoRcx.u = 0;
7222 pVmcs->u64RoIoRsi.u = 0;
7223 pVmcs->u64RoIoRdi.u = 0;
7224 pVmcs->u64RoIoRip.u = 0;
7225 pVmcs->u64RoGuestLinearAddr.u = 0;
7226}
7227
7228
7229/**
7230 * VMLAUNCH/VMRESUME instruction execution worker.
7231 *
7232 * @returns Strict VBox status code.
7233 * @param pVCpu The cross context virtual CPU structure.
7234 * @param cbInstr The instruction length in bytes.
7235 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7236 * VMXINSTRID_VMRESUME).
7237 *
7238 * @remarks Common VMX instruction checks are already expected to by the caller,
7239 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7240 */
7241IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7242{
7243# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7244 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7245 return VINF_EM_RAW_EMULATE_INSTR;
7246# else
7247 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7248 || uInstrId == VMXINSTRID_VMRESUME);
7249 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7250
7251 /* Nested-guest intercept. */
7252 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7253 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7254
7255 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7256
7257 /*
7258 * Basic VM-entry checks.
7259 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7260 * The checks following that do not have to follow a specific order.
7261 *
7262 * See Intel spec. 26.1 "Basic VM-entry Checks".
7263 */
7264
7265 /* CPL. */
7266 if (pVCpu->iem.s.uCpl == 0)
7267 { /* likely */ }
7268 else
7269 {
7270 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7271 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7272 return iemRaiseGeneralProtectionFault0(pVCpu);
7273 }
7274
7275 /* Current VMCS valid. */
7276 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7277 { /* likely */ }
7278 else
7279 {
7280 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7281 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7282 iemVmxVmFailInvalid(pVCpu);
7283 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7284 return VINF_SUCCESS;
7285 }
7286
7287 /* Current VMCS is not a shadow VMCS. */
7288 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7289 { /* likely */ }
7290 else
7291 {
7292 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7293 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7294 iemVmxVmFailInvalid(pVCpu);
7295 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7296 return VINF_SUCCESS;
7297 }
7298
7299 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7300 * use block-by-STI here which is not quite correct. */
7301 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7302 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7303 { /* likely */ }
7304 else
7305 {
7306 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7307 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7308 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7309 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7310 return VINF_SUCCESS;
7311 }
7312
7313 if (uInstrId == VMXINSTRID_VMLAUNCH)
7314 {
7315 /* VMLAUNCH with non-clear VMCS. */
7316 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7317 { /* likely */ }
7318 else
7319 {
7320 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7321 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7322 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7323 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7324 return VINF_SUCCESS;
7325 }
7326 }
7327 else
7328 {
7329 /* VMRESUME with non-launched VMCS. */
7330 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7331 { /* likely */ }
7332 else
7333 {
7334 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7335 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7336 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7337 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7338 return VINF_SUCCESS;
7339 }
7340 }
7341
7342 /*
7343 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7344 * while entering VMX non-root mode. We do some of this while checking VM-execution
7345 * controls. The guest hypervisor should not make assumptions and cannot expect
7346 * predictable behavior if changes to these structures are made in guest memory while
7347 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7348 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7349 *
7350 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7351 */
7352 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7353 Assert(pVmcs);
7354 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7355
7356 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7357 if (RT_SUCCESS(rc))
7358 {
7359 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7360 if (RT_SUCCESS(rc))
7361 {
7362 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7363 if (RT_SUCCESS(rc))
7364 {
7365 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7366 if (RT_SUCCESS(rc))
7367 {
7368 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7369 iemVmxVmentryInitReadOnlyFields(pVCpu);
7370
7371 /*
7372 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7373 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7374 * VM-exit when required.
7375 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7376 */
7377 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7378
7379 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7380 if (RT_SUCCESS(rc))
7381 {
7382 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7383 if (RT_SUCCESS(rc))
7384 {
7385 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7386 if (RT_SUCCESS(rc))
7387 {
7388 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7389
7390 /* VMLAUNCH instruction must update the VMCS launch state. */
7391 if (uInstrId == VMXINSTRID_VMLAUNCH)
7392 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7393
7394 /* Perform the VMX transition (PGM updates). */
7395 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7396 if (rcStrict == VINF_SUCCESS)
7397 { /* likely */ }
7398 else if (RT_SUCCESS(rcStrict))
7399 {
7400 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7401 VBOXSTRICTRC_VAL(rcStrict)));
7402 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7403 }
7404 else
7405 {
7406 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7407 return rcStrict;
7408 }
7409
7410 /* We've now entered nested-guest execution. */
7411 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7412
7413 /*
7414 * The priority of potential VM-exits during VM-entry is important.
7415 * The priorities of VM-exits and events are listed from highest
7416 * to lowest as follows:
7417 *
7418 * 1. Event injection.
7419 * 2. Trap on task-switch (T flag set in TSS).
7420 * 3. TPR below threshold / APIC-write.
7421 * 4. SMI, INIT.
7422 * 5. MTF exit.
7423 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7424 * 7. VMX-preemption timer.
7425 * 9. NMI-window exit.
7426 * 10. NMI injection.
7427 * 11. Interrupt-window exit.
7428 * 12. Virtual-interrupt injection.
7429 * 13. Interrupt injection.
7430 * 14. Process next instruction (fetch, decode, execute).
7431 */
7432
7433 /* Setup the VMX-preemption timer. */
7434 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7435
7436 /* Setup monitor-trap flag. */
7437 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7438
7439 /* Setup NMI-window exiting. */
7440 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7441
7442 /* Setup interrupt-window exiting. */
7443 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7444
7445 /* Now that we've switched page tables, we can go ahead and inject any event. */
7446 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7447 if (RT_SUCCESS(rcStrict))
7448 {
7449 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7450# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7451 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7452 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7453 if (rcSched != VINF_SUCCESS)
7454 iemSetPassUpStatus(pVCpu, rcSched);
7455# endif
7456 return VINF_SUCCESS;
7457 }
7458
7459 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7460 return rcStrict;
7461 }
7462 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7463 pVmcs->u64RoExitQual.u);
7464 }
7465 }
7466 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7467 pVmcs->u64RoExitQual.u);
7468 }
7469
7470 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7471 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7472 return VINF_SUCCESS;
7473 }
7474 }
7475 }
7476
7477 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7478 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7479 return VINF_SUCCESS;
7480# endif
7481}
7482
7483
7484/**
7485 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7486 * (causes a VM-exit) or not.
7487 *
7488 * @returns @c true if the instruction is intercepted, @c false otherwise.
7489 * @param pVCpu The cross context virtual CPU structure.
7490 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7491 * VMX_EXIT_WRMSR).
7492 * @param idMsr The MSR.
7493 */
7494IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7495{
7496 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7497 Assert( uExitReason == VMX_EXIT_RDMSR
7498 || uExitReason == VMX_EXIT_WRMSR);
7499
7500 /* Consult the MSR bitmap if the feature is supported. */
7501 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7502 Assert(pVmcs);
7503 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7504 {
7505 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7506 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7507 if (uExitReason == VMX_EXIT_RDMSR)
7508 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7509 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7510 }
7511
7512 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7513 return true;
7514}
7515
7516
7517/**
7518 * VMREAD common (memory/register) instruction execution worker
7519 *
7520 * @returns Strict VBox status code.
7521 * @param pVCpu The cross context virtual CPU structure.
7522 * @param cbInstr The instruction length in bytes.
7523 * @param pu64Dst Where to write the VMCS value (only updated when
7524 * VINF_SUCCESS is returned).
7525 * @param u64VmcsField The VMCS field.
7526 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7527 * NULL.
7528 */
7529IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7530 PCVMXVEXITINFO pExitInfo)
7531{
7532 /* Nested-guest intercept. */
7533 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7534 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7535 {
7536 if (pExitInfo)
7537 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7538 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7539 }
7540
7541 /* CPL. */
7542 if (pVCpu->iem.s.uCpl == 0)
7543 { /* likely */ }
7544 else
7545 {
7546 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7547 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7548 return iemRaiseGeneralProtectionFault0(pVCpu);
7549 }
7550
7551 /* VMCS pointer in root mode. */
7552 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7553 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7554 { /* likely */ }
7555 else
7556 {
7557 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7559 iemVmxVmFailInvalid(pVCpu);
7560 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7561 return VINF_SUCCESS;
7562 }
7563
7564 /* VMCS-link pointer in non-root mode. */
7565 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7566 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7567 { /* likely */ }
7568 else
7569 {
7570 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7572 iemVmxVmFailInvalid(pVCpu);
7573 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7574 return VINF_SUCCESS;
7575 }
7576
7577 /* Supported VMCS field. */
7578 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7579 { /* likely */ }
7580 else
7581 {
7582 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7583 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7584 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7586 return VINF_SUCCESS;
7587 }
7588
7589 /*
7590 * Setup reading from the current or shadow VMCS.
7591 */
7592 uint8_t *pbVmcs;
7593 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7594 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7595 else
7596 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7597 Assert(pbVmcs);
7598
7599 VMXVMCSFIELD VmcsField;
7600 VmcsField.u = u64VmcsField;
7601 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7602 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7603 uint8_t const uWidthType = (uWidth << 2) | uType;
7604 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7605 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7606 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7607 Assert(offField < VMX_V_VMCS_SIZE);
7608
7609 /*
7610 * Read the VMCS component based on the field's effective width.
7611 *
7612 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7613 * indicates high bits (little endian).
7614 *
7615 * Note! The caller is responsible to trim the result and update registers
7616 * or memory locations are required. Here we just zero-extend to the largest
7617 * type (i.e. 64-bits).
7618 */
7619 uint8_t *pbField = pbVmcs + offField;
7620 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7621 switch (uEffWidth)
7622 {
7623 case VMX_VMCSFIELD_WIDTH_64BIT:
7624 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7625 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7626 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7627 }
7628 return VINF_SUCCESS;
7629}
7630
7631
7632/**
7633 * VMREAD (64-bit register) instruction execution worker.
7634 *
7635 * @returns Strict VBox status code.
7636 * @param pVCpu The cross context virtual CPU structure.
7637 * @param cbInstr The instruction length in bytes.
7638 * @param pu64Dst Where to store the VMCS field's value.
7639 * @param u64VmcsField The VMCS field.
7640 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7641 * NULL.
7642 */
7643IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7644 PCVMXVEXITINFO pExitInfo)
7645{
7646 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7647 if (rcStrict == VINF_SUCCESS)
7648 {
7649 iemVmxVmreadSuccess(pVCpu, cbInstr);
7650 return VINF_SUCCESS;
7651 }
7652
7653 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7654 return rcStrict;
7655}
7656
7657
7658/**
7659 * VMREAD (32-bit register) instruction execution worker.
7660 *
7661 * @returns Strict VBox status code.
7662 * @param pVCpu The cross context virtual CPU structure.
7663 * @param cbInstr The instruction length in bytes.
7664 * @param pu32Dst Where to store the VMCS field's value.
7665 * @param u32VmcsField The VMCS field.
7666 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7667 * NULL.
7668 */
7669IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7670 PCVMXVEXITINFO pExitInfo)
7671{
7672 uint64_t u64Dst;
7673 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7674 if (rcStrict == VINF_SUCCESS)
7675 {
7676 *pu32Dst = u64Dst;
7677 iemVmxVmreadSuccess(pVCpu, cbInstr);
7678 return VINF_SUCCESS;
7679 }
7680
7681 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7682 return rcStrict;
7683}
7684
7685
7686/**
7687 * VMREAD (memory) instruction execution worker.
7688 *
7689 * @returns Strict VBox status code.
7690 * @param pVCpu The cross context virtual CPU structure.
7691 * @param cbInstr The instruction length in bytes.
7692 * @param iEffSeg The effective segment register to use with @a u64Val.
7693 * Pass UINT8_MAX if it is a register access.
7694 * @param GCPtrDst The guest linear address to store the VMCS field's
7695 * value.
7696 * @param u64VmcsField The VMCS field.
7697 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7698 * NULL.
7699 */
7700IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7701 PCVMXVEXITINFO pExitInfo)
7702{
7703 uint64_t u64Dst;
7704 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7705 if (rcStrict == VINF_SUCCESS)
7706 {
7707 /*
7708 * Write the VMCS field's value to the location specified in guest-memory.
7709 */
7710 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7711 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7712 else
7713 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7714 if (rcStrict == VINF_SUCCESS)
7715 {
7716 iemVmxVmreadSuccess(pVCpu, cbInstr);
7717 return VINF_SUCCESS;
7718 }
7719
7720 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7721 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7722 return rcStrict;
7723 }
7724
7725 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7726 return rcStrict;
7727}
7728
7729
7730/**
7731 * VMWRITE instruction execution worker.
7732 *
7733 * @returns Strict VBox status code.
7734 * @param pVCpu The cross context virtual CPU structure.
7735 * @param cbInstr The instruction length in bytes.
7736 * @param iEffSeg The effective segment register to use with @a u64Val.
7737 * Pass UINT8_MAX if it is a register access.
7738 * @param u64Val The value to write (or guest linear address to the
7739 * value), @a iEffSeg will indicate if it's a memory
7740 * operand.
7741 * @param u64VmcsField The VMCS field.
7742 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7743 * NULL.
7744 */
7745IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7746 PCVMXVEXITINFO pExitInfo)
7747{
7748 /* Nested-guest intercept. */
7749 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7750 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7751 {
7752 if (pExitInfo)
7753 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7754 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7755 }
7756
7757 /* CPL. */
7758 if (pVCpu->iem.s.uCpl == 0)
7759 { /* likely */ }
7760 else
7761 {
7762 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7763 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7764 return iemRaiseGeneralProtectionFault0(pVCpu);
7765 }
7766
7767 /* VMCS pointer in root mode. */
7768 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7769 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7770 { /* likely */ }
7771 else
7772 {
7773 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7774 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7775 iemVmxVmFailInvalid(pVCpu);
7776 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7777 return VINF_SUCCESS;
7778 }
7779
7780 /* VMCS-link pointer in non-root mode. */
7781 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7782 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7783 { /* likely */ }
7784 else
7785 {
7786 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7788 iemVmxVmFailInvalid(pVCpu);
7789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7790 return VINF_SUCCESS;
7791 }
7792
7793 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7794 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7795 if (!fIsRegOperand)
7796 {
7797 /* Read the value from the specified guest memory location. */
7798 VBOXSTRICTRC rcStrict;
7799 RTGCPTR const GCPtrVal = u64Val;
7800 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7801 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7802 else
7803 {
7804 uint32_t u32Val;
7805 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7806 u64Val = u32Val;
7807 }
7808 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7809 {
7810 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7811 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7812 return rcStrict;
7813 }
7814 }
7815 else
7816 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7817
7818 /* Supported VMCS field. */
7819 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7820 { /* likely */ }
7821 else
7822 {
7823 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7825 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7826 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7827 return VINF_SUCCESS;
7828 }
7829
7830 /* Read-only VMCS field. */
7831 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
7832 if ( !fIsFieldReadOnly
7833 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7834 { /* likely */ }
7835 else
7836 {
7837 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7838 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7839 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7840 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7841 return VINF_SUCCESS;
7842 }
7843
7844 /*
7845 * Setup writing to the current or shadow VMCS.
7846 */
7847 uint8_t *pbVmcs;
7848 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7849 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7850 else
7851 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7852 Assert(pbVmcs);
7853
7854 VMXVMCSFIELD VmcsField;
7855 VmcsField.u = u64VmcsField;
7856 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7857 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7858 uint8_t const uWidthType = (uWidth << 2) | uType;
7859 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7860 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7861 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7862 Assert(offField < VMX_V_VMCS_SIZE);
7863
7864 /*
7865 * Write the VMCS component based on the field's effective width.
7866 *
7867 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7868 * indicates high bits (little endian).
7869 */
7870 uint8_t *pbField = pbVmcs + offField;
7871 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7872 switch (uEffWidth)
7873 {
7874 case VMX_VMCSFIELD_WIDTH_64BIT:
7875 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7876 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7877 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7878 }
7879
7880 iemVmxVmSucceed(pVCpu);
7881 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7882 return VINF_SUCCESS;
7883}
7884
7885
7886/**
7887 * VMCLEAR instruction execution worker.
7888 *
7889 * @returns Strict VBox status code.
7890 * @param pVCpu The cross context virtual CPU structure.
7891 * @param cbInstr The instruction length in bytes.
7892 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7893 * @param GCPtrVmcs The linear address of the VMCS pointer.
7894 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7895 *
7896 * @remarks Common VMX instruction checks are already expected to by the caller,
7897 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7898 */
7899IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7900 PCVMXVEXITINFO pExitInfo)
7901{
7902 /* Nested-guest intercept. */
7903 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7904 {
7905 if (pExitInfo)
7906 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7907 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7908 }
7909
7910 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7911
7912 /* CPL. */
7913 if (pVCpu->iem.s.uCpl == 0)
7914 { /* likely */ }
7915 else
7916 {
7917 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7918 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7919 return iemRaiseGeneralProtectionFault0(pVCpu);
7920 }
7921
7922 /* Get the VMCS pointer from the location specified by the source memory operand. */
7923 RTGCPHYS GCPhysVmcs;
7924 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7925 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7926 { /* likely */ }
7927 else
7928 {
7929 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7930 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7931 return rcStrict;
7932 }
7933
7934 /* VMCS pointer alignment. */
7935 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7936 { /* likely */ }
7937 else
7938 {
7939 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7940 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7941 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7942 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7943 return VINF_SUCCESS;
7944 }
7945
7946 /* VMCS physical-address width limits. */
7947 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7948 { /* likely */ }
7949 else
7950 {
7951 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7952 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7953 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7954 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7955 return VINF_SUCCESS;
7956 }
7957
7958 /* VMCS is not the VMXON region. */
7959 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7960 { /* likely */ }
7961 else
7962 {
7963 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7964 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7965 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7966 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7967 return VINF_SUCCESS;
7968 }
7969
7970 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7971 restriction imposed by our implementation. */
7972 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7973 { /* likely */ }
7974 else
7975 {
7976 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7978 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7979 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7980 return VINF_SUCCESS;
7981 }
7982
7983 /*
7984 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7985 *
7986 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7987 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7988 * to 'clear'.
7989 */
7990 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7991 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7992 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7993 {
7994 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
7995 iemVmxCommitCurrentVmcsToMemory(pVCpu);
7996 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7997 }
7998 else
7999 {
8000 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8001 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8002 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8003 if (RT_FAILURE(rcStrict))
8004 return rcStrict;
8005 }
8006
8007 iemVmxVmSucceed(pVCpu);
8008 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8009 return VINF_SUCCESS;
8010}
8011
8012
8013/**
8014 * VMPTRST instruction execution worker.
8015 *
8016 * @returns Strict VBox status code.
8017 * @param pVCpu The cross context virtual CPU structure.
8018 * @param cbInstr The instruction length in bytes.
8019 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8020 * @param GCPtrVmcs The linear address of where to store the current VMCS
8021 * pointer.
8022 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8023 *
8024 * @remarks Common VMX instruction checks are already expected to by the caller,
8025 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8026 */
8027IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8028 PCVMXVEXITINFO pExitInfo)
8029{
8030 /* Nested-guest intercept. */
8031 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8032 {
8033 if (pExitInfo)
8034 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8035 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8036 }
8037
8038 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8039
8040 /* CPL. */
8041 if (pVCpu->iem.s.uCpl == 0)
8042 { /* likely */ }
8043 else
8044 {
8045 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8046 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8047 return iemRaiseGeneralProtectionFault0(pVCpu);
8048 }
8049
8050 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8051 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8052 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8053 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8054 {
8055 iemVmxVmSucceed(pVCpu);
8056 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8057 return rcStrict;
8058 }
8059
8060 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8061 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8062 return rcStrict;
8063}
8064
8065
8066/**
8067 * VMPTRLD instruction execution worker.
8068 *
8069 * @returns Strict VBox status code.
8070 * @param pVCpu The cross context virtual CPU structure.
8071 * @param cbInstr The instruction length in bytes.
8072 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8073 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8074 *
8075 * @remarks Common VMX instruction checks are already expected to by the caller,
8076 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8077 */
8078IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8079 PCVMXVEXITINFO pExitInfo)
8080{
8081 /* Nested-guest intercept. */
8082 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8083 {
8084 if (pExitInfo)
8085 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8086 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8087 }
8088
8089 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8090
8091 /* CPL. */
8092 if (pVCpu->iem.s.uCpl == 0)
8093 { /* likely */ }
8094 else
8095 {
8096 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8097 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8098 return iemRaiseGeneralProtectionFault0(pVCpu);
8099 }
8100
8101 /* Get the VMCS pointer from the location specified by the source memory operand. */
8102 RTGCPHYS GCPhysVmcs;
8103 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8104 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8105 { /* likely */ }
8106 else
8107 {
8108 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8109 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8110 return rcStrict;
8111 }
8112
8113 /* VMCS pointer alignment. */
8114 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8115 { /* likely */ }
8116 else
8117 {
8118 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8119 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8120 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8121 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8122 return VINF_SUCCESS;
8123 }
8124
8125 /* VMCS physical-address width limits. */
8126 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8127 { /* likely */ }
8128 else
8129 {
8130 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8131 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8132 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8133 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8134 return VINF_SUCCESS;
8135 }
8136
8137 /* VMCS is not the VMXON region. */
8138 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8139 { /* likely */ }
8140 else
8141 {
8142 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8143 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8144 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8145 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8146 return VINF_SUCCESS;
8147 }
8148
8149 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8150 restriction imposed by our implementation. */
8151 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8152 { /* likely */ }
8153 else
8154 {
8155 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8157 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8158 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8159 return VINF_SUCCESS;
8160 }
8161
8162 /* Read just the VMCS revision from the VMCS. */
8163 VMXVMCSREVID VmcsRevId;
8164 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8165 if (RT_SUCCESS(rc))
8166 { /* likely */ }
8167 else
8168 {
8169 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8170 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8171 return rc;
8172 }
8173
8174 /*
8175 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8176 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8177 */
8178 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8179 && ( !VmcsRevId.n.fIsShadowVmcs
8180 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8181 { /* likely */ }
8182 else
8183 {
8184 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8185 {
8186 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8187 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8188 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8189 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8190 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8191 return VINF_SUCCESS;
8192 }
8193
8194 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8195 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8196 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8197 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8198 return VINF_SUCCESS;
8199 }
8200
8201 /*
8202 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8203 * the cache of an existing, current VMCS back to guest memory before loading a new,
8204 * different current VMCS.
8205 */
8206 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8207 {
8208 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8209 {
8210 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8211 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8212 }
8213
8214 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8215 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8216 sizeof(VMXVVMCS));
8217 if (RT_SUCCESS(rc))
8218 { /* likely */ }
8219 else
8220 {
8221 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8222 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8223 return rc;
8224 }
8225 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8226 }
8227
8228 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8229 iemVmxVmSucceed(pVCpu);
8230 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8231 return VINF_SUCCESS;
8232}
8233
8234
8235/**
8236 * INVVPID instruction execution worker.
8237 *
8238 * @returns Strict VBox status code.
8239 * @param pVCpu The cross context virtual CPU structure.
8240 * @param cbInstr The instruction length in bytes.
8241 * @param iEffSeg The segment of the invvpid descriptor.
8242 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8243 * @param u64InvvpidType The invalidation type.
8244 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8245 * NULL.
8246 *
8247 * @remarks Common VMX instruction checks are already expected to by the caller,
8248 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8249 */
8250IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8251 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8252{
8253 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8254 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8255 return iemRaiseUndefinedOpcode(pVCpu);
8256
8257 /* Nested-guest intercept. */
8258 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8259 {
8260 if (pExitInfo)
8261 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8262 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8263 }
8264
8265 /* CPL. */
8266 if (pVCpu->iem.s.uCpl != 0)
8267 {
8268 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8269 return iemRaiseGeneralProtectionFault0(pVCpu);
8270 }
8271
8272 /*
8273 * Validate INVVPID invalidation type.
8274 *
8275 * The instruction specifies exactly ONE of the supported invalidation types.
8276 *
8277 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8278 * supported. In theory, it's possible for a CPU to not support flushing individual
8279 * addresses but all the other types or any other combination. We do not take any
8280 * shortcuts here by assuming the types we currently expose to the guest.
8281 */
8282 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8283 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8284 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8285 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8286 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8287 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8288 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8289 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8290 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8291 { /* likely */ }
8292 else
8293 {
8294 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8295 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8296 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8297 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8298 return VINF_SUCCESS;
8299 }
8300
8301 /*
8302 * Fetch the invvpid descriptor from guest memory.
8303 */
8304 RTUINT128U uDesc;
8305 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8306 if (rcStrict == VINF_SUCCESS)
8307 {
8308 /*
8309 * Validate the descriptor.
8310 */
8311 if (uDesc.s.Lo > 0xfff)
8312 {
8313 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8314 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8315 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8316 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8317 return VINF_SUCCESS;
8318 }
8319
8320 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8321 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8322 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8323 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8324 switch (u64InvvpidType)
8325 {
8326 case VMXTLBFLUSHVPID_INDIV_ADDR:
8327 {
8328 if (uVpid != 0)
8329 {
8330 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8331 {
8332 /* Invalidate mappings for the linear address tagged with VPID. */
8333 /** @todo PGM support for VPID? Currently just flush everything. */
8334 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8335 iemVmxVmSucceed(pVCpu);
8336 }
8337 else
8338 {
8339 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8340 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8341 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8342 }
8343 }
8344 else
8345 {
8346 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8347 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8348 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8349 }
8350 break;
8351 }
8352
8353 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8354 {
8355 if (uVpid != 0)
8356 {
8357 /* Invalidate all mappings with VPID. */
8358 /** @todo PGM support for VPID? Currently just flush everything. */
8359 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8360 iemVmxVmSucceed(pVCpu);
8361 }
8362 else
8363 {
8364 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8365 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8366 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8367 }
8368 break;
8369 }
8370
8371 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8372 {
8373 /* Invalidate all mappings with non-zero VPIDs. */
8374 /** @todo PGM support for VPID? Currently just flush everything. */
8375 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8376 iemVmxVmSucceed(pVCpu);
8377 break;
8378 }
8379
8380 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8381 {
8382 if (uVpid != 0)
8383 {
8384 /* Invalidate all mappings with VPID except global translations. */
8385 /** @todo PGM support for VPID? Currently just flush everything. */
8386 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8387 iemVmxVmSucceed(pVCpu);
8388 }
8389 else
8390 {
8391 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8393 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8394 }
8395 break;
8396 }
8397 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8398 }
8399 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8400 }
8401 return rcStrict;
8402}
8403
8404
8405/**
8406 * VMXON instruction execution worker.
8407 *
8408 * @returns Strict VBox status code.
8409 * @param pVCpu The cross context virtual CPU structure.
8410 * @param cbInstr The instruction length in bytes.
8411 * @param iEffSeg The effective segment register to use with @a
8412 * GCPtrVmxon.
8413 * @param GCPtrVmxon The linear address of the VMXON pointer.
8414 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8415 *
8416 * @remarks Common VMX instruction checks are already expected to by the caller,
8417 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8418 */
8419IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8420 PCVMXVEXITINFO pExitInfo)
8421{
8422 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8423 {
8424 /* CPL. */
8425 if (pVCpu->iem.s.uCpl == 0)
8426 { /* likely */ }
8427 else
8428 {
8429 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8431 return iemRaiseGeneralProtectionFault0(pVCpu);
8432 }
8433
8434 /* A20M (A20 Masked) mode. */
8435 if (PGMPhysIsA20Enabled(pVCpu))
8436 { /* likely */ }
8437 else
8438 {
8439 Log(("vmxon: A20M mode -> #GP(0)\n"));
8440 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8441 return iemRaiseGeneralProtectionFault0(pVCpu);
8442 }
8443
8444 /* CR0. */
8445 {
8446 /* CR0 MB1 bits. */
8447 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8448 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8449 { /* likely */ }
8450 else
8451 {
8452 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8454 return iemRaiseGeneralProtectionFault0(pVCpu);
8455 }
8456
8457 /* CR0 MBZ bits. */
8458 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8459 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8460 { /* likely */ }
8461 else
8462 {
8463 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8464 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8465 return iemRaiseGeneralProtectionFault0(pVCpu);
8466 }
8467 }
8468
8469 /* CR4. */
8470 {
8471 /* CR4 MB1 bits. */
8472 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8473 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8474 { /* likely */ }
8475 else
8476 {
8477 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8478 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8479 return iemRaiseGeneralProtectionFault0(pVCpu);
8480 }
8481
8482 /* CR4 MBZ bits. */
8483 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8484 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8485 { /* likely */ }
8486 else
8487 {
8488 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8489 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8490 return iemRaiseGeneralProtectionFault0(pVCpu);
8491 }
8492 }
8493
8494 /* Feature control MSR's LOCK and VMXON bits. */
8495 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8496 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8497 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8498 { /* likely */ }
8499 else
8500 {
8501 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8502 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8503 return iemRaiseGeneralProtectionFault0(pVCpu);
8504 }
8505
8506 /* Get the VMXON pointer from the location specified by the source memory operand. */
8507 RTGCPHYS GCPhysVmxon;
8508 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8509 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8510 { /* likely */ }
8511 else
8512 {
8513 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8514 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8515 return rcStrict;
8516 }
8517
8518 /* VMXON region pointer alignment. */
8519 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8520 { /* likely */ }
8521 else
8522 {
8523 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8525 iemVmxVmFailInvalid(pVCpu);
8526 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8527 return VINF_SUCCESS;
8528 }
8529
8530 /* VMXON physical-address width limits. */
8531 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8532 { /* likely */ }
8533 else
8534 {
8535 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8536 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8537 iemVmxVmFailInvalid(pVCpu);
8538 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8539 return VINF_SUCCESS;
8540 }
8541
8542 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8543 restriction imposed by our implementation. */
8544 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8545 { /* likely */ }
8546 else
8547 {
8548 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8550 iemVmxVmFailInvalid(pVCpu);
8551 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8552 return VINF_SUCCESS;
8553 }
8554
8555 /* Read the VMCS revision ID from the VMXON region. */
8556 VMXVMCSREVID VmcsRevId;
8557 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8558 if (RT_SUCCESS(rc))
8559 { /* likely */ }
8560 else
8561 {
8562 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8564 return rc;
8565 }
8566
8567 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8568 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8569 { /* likely */ }
8570 else
8571 {
8572 /* Revision ID mismatch. */
8573 if (!VmcsRevId.n.fIsShadowVmcs)
8574 {
8575 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8576 VmcsRevId.n.u31RevisionId));
8577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8578 iemVmxVmFailInvalid(pVCpu);
8579 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8580 return VINF_SUCCESS;
8581 }
8582
8583 /* Shadow VMCS disallowed. */
8584 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8585 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8586 iemVmxVmFailInvalid(pVCpu);
8587 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8588 return VINF_SUCCESS;
8589 }
8590
8591 /*
8592 * Record that we're in VMX operation, block INIT, block and disable A20M.
8593 */
8594 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8595 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8596 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8597
8598 /* Clear address-range monitoring. */
8599 EMMonitorWaitClear(pVCpu);
8600 /** @todo NSTVMX: Intel PT. */
8601
8602 iemVmxVmSucceed(pVCpu);
8603 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8604 return VINF_SUCCESS;
8605 }
8606 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8607 {
8608 /* Nested-guest intercept. */
8609 if (pExitInfo)
8610 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8611 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8612 }
8613
8614 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8615
8616 /* CPL. */
8617 if (pVCpu->iem.s.uCpl > 0)
8618 {
8619 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8621 return iemRaiseGeneralProtectionFault0(pVCpu);
8622 }
8623
8624 /* VMXON when already in VMX root mode. */
8625 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8627 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8628 return VINF_SUCCESS;
8629}
8630
8631
8632/**
8633 * Implements 'VMXOFF'.
8634 *
8635 * @remarks Common VMX instruction checks are already expected to by the caller,
8636 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8637 */
8638IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8639{
8640 /* Nested-guest intercept. */
8641 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8642 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8643
8644 /* CPL. */
8645 if (pVCpu->iem.s.uCpl == 0)
8646 { /* likely */ }
8647 else
8648 {
8649 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8650 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8651 return iemRaiseGeneralProtectionFault0(pVCpu);
8652 }
8653
8654 /* Dual monitor treatment of SMIs and SMM. */
8655 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8656 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8657 { /* likely */ }
8658 else
8659 {
8660 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8661 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8662 return VINF_SUCCESS;
8663 }
8664
8665 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8666 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8667 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8668
8669 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8670 { /** @todo NSTVMX: Unblock SMI. */ }
8671
8672 EMMonitorWaitClear(pVCpu);
8673 /** @todo NSTVMX: Unblock and enable A20M. */
8674
8675 iemVmxVmSucceed(pVCpu);
8676 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8677 return VINF_SUCCESS;
8678}
8679
8680
8681/**
8682 * Implements 'VMXON'.
8683 */
8684IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8685{
8686 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8687}
8688
8689
8690/**
8691 * Implements 'VMLAUNCH'.
8692 */
8693IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8694{
8695 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8696}
8697
8698
8699/**
8700 * Implements 'VMRESUME'.
8701 */
8702IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8703{
8704 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8705}
8706
8707
8708/**
8709 * Implements 'VMPTRLD'.
8710 */
8711IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8712{
8713 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8714}
8715
8716
8717/**
8718 * Implements 'VMPTRST'.
8719 */
8720IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8721{
8722 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8723}
8724
8725
8726/**
8727 * Implements 'VMCLEAR'.
8728 */
8729IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8730{
8731 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8732}
8733
8734
8735/**
8736 * Implements 'VMWRITE' register.
8737 */
8738IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8739{
8740 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8741}
8742
8743
8744/**
8745 * Implements 'VMWRITE' memory.
8746 */
8747IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8748{
8749 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8750}
8751
8752
8753/**
8754 * Implements 'VMREAD' register (64-bit).
8755 */
8756IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8757{
8758 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8759}
8760
8761
8762/**
8763 * Implements 'VMREAD' register (32-bit).
8764 */
8765IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8766{
8767 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8768}
8769
8770
8771/**
8772 * Implements 'VMREAD' memory, 64-bit register.
8773 */
8774IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8775{
8776 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8777}
8778
8779
8780/**
8781 * Implements 'VMREAD' memory, 32-bit register.
8782 */
8783IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8784{
8785 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8786}
8787
8788
8789/**
8790 * Implements 'INVVPID'.
8791 */
8792IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8793{
8794 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8795}
8796
8797
8798/**
8799 * Implements VMX's implementation of PAUSE.
8800 */
8801IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8802{
8803 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8804 {
8805 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8806 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8807 return rcStrict;
8808 }
8809
8810 /*
8811 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8812 * a VM-exit, the instruction operates normally.
8813 */
8814 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8815 return VINF_SUCCESS;
8816}
8817
8818#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8819
8820
8821/**
8822 * Implements 'VMCALL'.
8823 */
8824IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8825{
8826#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8827 /* Nested-guest intercept. */
8828 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8829 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8830#endif
8831
8832 /* Join forces with vmmcall. */
8833 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8834}
8835
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