VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79377

Last change on this file since 79377 was 79377, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Use CPUMIsGuestVmxMovToCr3InterceptSet.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79377 2019-06-27 08:05:04Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Implements VMSucceed for VMX instruction success.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 */
788DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
789{
790 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
791}
792
793
794/**
795 * Implements VMFailInvalid for VMX instruction failure.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
800{
801 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
802}
803
804
805/**
806 * Implements VMFail for VMX instruction failure.
807 *
808 * @param pVCpu The cross context virtual CPU structure.
809 * @param enmInsErr The VM instruction error.
810 */
811DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
812{
813 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
814}
815
816
817/**
818 * Checks if the given auto-load/store MSR area count is valid for the
819 * implementation.
820 *
821 * @returns @c true if it's within the valid limit, @c false otherwise.
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param uMsrCount The MSR area count to check.
824 */
825DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
826{
827 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
828 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
829 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
830 if (uMsrCount <= cMaxSupportedMsrs)
831 return true;
832 return false;
833}
834
835
836/**
837 * Flushes the current VMCS contents back to guest memory.
838 *
839 * @returns VBox status code.
840 * @param pVCpu The cross context virtual CPU structure.
841 */
842DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPU pVCpu)
843{
844 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
845 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
846 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
847 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
848 return rc;
849}
850
851
852/**
853 * Populates the current VMCS contents from guest memory.
854 *
855 * @returns VBox status code.
856 * @param pVCpu The cross context virtual CPU structure.
857 */
858DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPU pVCpu)
859{
860 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
861 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
862 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
863 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
864 return rc;
865}
866
867
868/**
869 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
870 *
871 * @param pVCpu The cross context virtual CPU structure.
872 */
873DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
874{
875 iemVmxVmSucceed(pVCpu);
876 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
877}
878
879
880/**
881 * Gets the instruction diagnostic for segment base checks during VM-entry of a
882 * nested-guest.
883 *
884 * @param iSegReg The segment index (X86_SREG_XXX).
885 */
886IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
887{
888 switch (iSegReg)
889 {
890 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
891 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
892 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
893 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
894 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
895 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
896 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
897 }
898}
899
900
901/**
902 * Gets the instruction diagnostic for segment base checks during VM-entry of a
903 * nested-guest that is in Virtual-8086 mode.
904 *
905 * @param iSegReg The segment index (X86_SREG_XXX).
906 */
907IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
908{
909 switch (iSegReg)
910 {
911 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
912 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
913 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
914 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
915 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
916 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
917 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
918 }
919}
920
921
922/**
923 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
924 * nested-guest that is in Virtual-8086 mode.
925 *
926 * @param iSegReg The segment index (X86_SREG_XXX).
927 */
928IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
929{
930 switch (iSegReg)
931 {
932 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
933 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
934 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
935 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
936 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
937 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
938 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
939 }
940}
941
942
943/**
944 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
945 * nested-guest that is in Virtual-8086 mode.
946 *
947 * @param iSegReg The segment index (X86_SREG_XXX).
948 */
949IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
950{
951 switch (iSegReg)
952 {
953 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
954 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
955 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
956 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
957 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
958 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
959 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
960 }
961}
962
963
964/**
965 * Gets the instruction diagnostic for segment attributes reserved bits failure
966 * during VM-entry of a nested-guest.
967 *
968 * @param iSegReg The segment index (X86_SREG_XXX).
969 */
970IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
971{
972 switch (iSegReg)
973 {
974 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
975 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
976 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
977 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
978 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
979 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
980 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
981 }
982}
983
984
985/**
986 * Gets the instruction diagnostic for segment attributes descriptor-type
987 * (code/segment or system) failure during VM-entry of a nested-guest.
988 *
989 * @param iSegReg The segment index (X86_SREG_XXX).
990 */
991IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
992{
993 switch (iSegReg)
994 {
995 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
996 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
997 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
998 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
999 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1000 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1001 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1002 }
1003}
1004
1005
1006/**
1007 * Gets the instruction diagnostic for segment attributes descriptor-type
1008 * (code/segment or system) failure during VM-entry of a nested-guest.
1009 *
1010 * @param iSegReg The segment index (X86_SREG_XXX).
1011 */
1012IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1013{
1014 switch (iSegReg)
1015 {
1016 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1017 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1018 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1019 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1020 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1021 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1022 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1023 }
1024}
1025
1026
1027/**
1028 * Gets the instruction diagnostic for segment attribute granularity failure during
1029 * VM-entry of a nested-guest.
1030 *
1031 * @param iSegReg The segment index (X86_SREG_XXX).
1032 */
1033IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1034{
1035 switch (iSegReg)
1036 {
1037 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1038 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1039 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1040 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1041 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1042 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1043 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1044 }
1045}
1046
1047/**
1048 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1049 * VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attribute type accessed failure
1070 * during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1091 * failure during VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The PDPTE entry index.
1094 */
1095IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1096{
1097 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1098 switch (iPdpte)
1099 {
1100 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1101 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1102 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1103 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1104 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1105 }
1106}
1107
1108
1109/**
1110 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1111 * failure during VM-exit of a nested-guest.
1112 *
1113 * @param iSegReg The PDPTE entry index.
1114 */
1115IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1116{
1117 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1118 switch (iPdpte)
1119 {
1120 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1121 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1122 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1123 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1124 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1125 }
1126}
1127
1128
1129/**
1130 * Saves the guest control registers, debug registers and some MSRs are part of
1131 * VM-exit.
1132 *
1133 * @param pVCpu The cross context virtual CPU structure.
1134 */
1135IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1136{
1137 /*
1138 * Saves the guest control registers, debug registers and some MSRs.
1139 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1140 */
1141 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1142
1143 /* Save control registers. */
1144 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1145 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1146 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1147
1148 /* Save SYSENTER CS, ESP, EIP. */
1149 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1150 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1151 {
1152 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1153 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1154 }
1155 else
1156 {
1157 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1158 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1159 }
1160
1161 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1162 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1163 {
1164 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1165 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1166 }
1167
1168 /* Save PAT MSR. */
1169 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1170 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1171
1172 /* Save EFER MSR. */
1173 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1174 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1175
1176 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1177 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1178
1179 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1180}
1181
1182
1183/**
1184 * Saves the guest force-flags in preparation of entering the nested-guest.
1185 *
1186 * @param pVCpu The cross context virtual CPU structure.
1187 */
1188IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1189{
1190 /* We shouldn't be called multiple times during VM-entry. */
1191 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1192
1193 /* MTF should not be set outside VMX non-root mode. */
1194 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1195
1196 /*
1197 * Preserve the required force-flags.
1198 *
1199 * We cache and clear force-flags that would affect the execution of the
1200 * nested-guest. Cached flags are then restored while returning to the guest
1201 * if necessary.
1202 *
1203 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1204 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1205 * instruction. Interrupt inhibition for any nested-guest instruction
1206 * is supplied by the guest-interruptibility state VMCS field and will
1207 * be set up as part of loading the guest state.
1208 *
1209 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1210 * successful VM-entry (due to invalid guest-state) need to continue
1211 * blocking NMIs if it was in effect before VM-entry.
1212 *
1213 * - MTF need not be preserved as it's used only in VMX non-root mode and
1214 * is supplied through the VM-execution controls.
1215 *
1216 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1217 * we will be able to generate interrupts that may cause VM-exits for
1218 * the nested-guest.
1219 */
1220 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1221}
1222
1223
1224/**
1225 * Restores the guest force-flags in preparation of exiting the nested-guest.
1226 *
1227 * @param pVCpu The cross context virtual CPU structure.
1228 */
1229IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1230{
1231 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1232 {
1233 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1235 }
1236}
1237
1238
1239/**
1240 * Perform a VMX transition updated PGM, IEM and CPUM.
1241 *
1242 * @param pVCpu The cross context virtual CPU structure.
1243 */
1244IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1245{
1246 /*
1247 * Inform PGM about paging mode changes.
1248 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1249 * see comment in iemMemPageTranslateAndCheckAccess().
1250 */
1251 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1252# ifdef IN_RING3
1253 Assert(rc != VINF_PGM_CHANGE_MODE);
1254# endif
1255 AssertRCReturn(rc, rc);
1256
1257 /* Inform CPUM (recompiler), can later be removed. */
1258 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1259
1260 /*
1261 * Flush the TLB with new CR3. This is required in case the PGM mode change
1262 * above doesn't actually change anything.
1263 */
1264 if (rc == VINF_SUCCESS)
1265 {
1266 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1267 AssertRCReturn(rc, rc);
1268 }
1269
1270 /* Re-initialize IEM cache/state after the drastic mode switch. */
1271 iemReInitExec(pVCpu);
1272 return rc;
1273}
1274
1275
1276/**
1277 * Calculates the current VMX-preemption timer value.
1278 *
1279 * @returns The current VMX-preemption timer value.
1280 * @param pVCpu The cross context virtual CPU structure.
1281 */
1282IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1283{
1284 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1285 Assert(pVmcs);
1286
1287 /*
1288 * Assume the following:
1289 * PreemptTimerShift = 5
1290 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1291 * EntryTick = 50000 (TSC at time of VM-entry)
1292 *
1293 * CurTick Delta PreemptTimerVal
1294 * ----------------------------------
1295 * 60000 10000 2
1296 * 80000 30000 1
1297 * 90000 40000 0 -> VM-exit.
1298 *
1299 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1300 * The saved VMX-preemption timer value is calculated as follows:
1301 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1302 * E.g.:
1303 * Delta = 10000
1304 * Tmp = 10000 / (2 * 10000) = 0.5
1305 * NewPt = 2 - 0.5 = 2
1306 * Delta = 30000
1307 * Tmp = 30000 / (2 * 10000) = 1.5
1308 * NewPt = 2 - 1.5 = 1
1309 * Delta = 40000
1310 * Tmp = 40000 / 20000 = 2
1311 * NewPt = 2 - 2 = 0
1312 */
1313 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1314 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1315 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1316 uint64_t const uDelta = uCurTick - uEntryTick;
1317 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1318 uint32_t const uPreemptTimer = uVmcsPreemptVal
1319 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1320 return uPreemptTimer;
1321}
1322
1323
1324/**
1325 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1326 *
1327 * @param pVCpu The cross context virtual CPU structure.
1328 */
1329IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1330{
1331 /*
1332 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1333 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1334 */
1335 /* CS, SS, ES, DS, FS, GS. */
1336 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1337 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1338 {
1339 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1340 if (!pSelReg->Attr.n.u1Unusable)
1341 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1342 else
1343 {
1344 /*
1345 * For unusable segments the attributes are undefined except for CS and SS.
1346 * For the rest we don't bother preserving anything but the unusable bit.
1347 */
1348 switch (iSegReg)
1349 {
1350 case X86_SREG_CS:
1351 pVmcs->GuestCs = pSelReg->Sel;
1352 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1353 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1354 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1355 | X86DESCATTR_UNUSABLE);
1356 break;
1357
1358 case X86_SREG_SS:
1359 pVmcs->GuestSs = pSelReg->Sel;
1360 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1361 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1362 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1363 break;
1364
1365 case X86_SREG_DS:
1366 pVmcs->GuestDs = pSelReg->Sel;
1367 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1368 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1369 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1370 break;
1371
1372 case X86_SREG_ES:
1373 pVmcs->GuestEs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1377 break;
1378
1379 case X86_SREG_FS:
1380 pVmcs->GuestFs = pSelReg->Sel;
1381 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1382 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1383 break;
1384
1385 case X86_SREG_GS:
1386 pVmcs->GuestGs = pSelReg->Sel;
1387 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1388 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1389 break;
1390 }
1391 }
1392 }
1393
1394 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1395 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1396 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1397 | X86DESCATTR_UNUSABLE;
1398 /* LDTR. */
1399 {
1400 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1401 pVmcs->GuestLdtr = pSelReg->Sel;
1402 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1403 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1404 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1405 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1406 }
1407
1408 /* TR. */
1409 {
1410 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1411 pVmcs->GuestTr = pSelReg->Sel;
1412 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1413 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1414 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1415 }
1416
1417 /* GDTR. */
1418 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1419 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1420
1421 /* IDTR. */
1422 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1423 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1424}
1425
1426
1427/**
1428 * Saves guest non-register state as part of VM-exit.
1429 *
1430 * @param pVCpu The cross context virtual CPU structure.
1431 * @param uExitReason The VM-exit reason.
1432 */
1433IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1434{
1435 /*
1436 * Save guest non-register state.
1437 * See Intel spec. 27.3.4 "Saving Non-Register State".
1438 */
1439 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1440
1441 /*
1442 * Activity state.
1443 * Most VM-exits will occur in the active state. However, if the first instruction
1444 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1445 * the VM-exit will be from the HLT activity state.
1446 *
1447 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1448 */
1449 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1450 * not? */
1451 EMSTATE const enmActivityState = EMGetState(pVCpu);
1452 switch (enmActivityState)
1453 {
1454 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1455 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1456 }
1457
1458 /*
1459 * Interruptibility-state.
1460 */
1461 /* NMI. */
1462 pVmcs->u32GuestIntrState = 0;
1463 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1464 {
1465 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1466 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1467 }
1468 else
1469 {
1470 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1471 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1472 }
1473
1474 /* Blocking-by-STI. */
1475 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1476 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1477 {
1478 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1479 * currently. */
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1481 }
1482 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1483
1484 /*
1485 * Pending debug exceptions.
1486 */
1487 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1488 && uExitReason != VMX_EXIT_SMI
1489 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1490 && !HMVmxIsVmexitTrapLike(uExitReason))
1491 {
1492 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1493 * block-by-MovSS is in effect. */
1494 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1495 }
1496 else
1497 {
1498 /*
1499 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1500 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1501 *
1502 * See Intel spec. 24.4.2 "Guest Non-Register State".
1503 */
1504 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1505 * DR6. */
1506 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1507 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1508 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1509 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1510 if (fPendingDbgMask & fBpHitMask)
1511 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1512 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1513 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1514 }
1515
1516 /*
1517 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1518 *
1519 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1520 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1521 */
1522 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1523 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1524 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1525
1526 /* PDPTEs. */
1527 /* We don't support EPT yet. */
1528 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1529 pVmcs->u64GuestPdpte0.u = 0;
1530 pVmcs->u64GuestPdpte1.u = 0;
1531 pVmcs->u64GuestPdpte2.u = 0;
1532 pVmcs->u64GuestPdpte3.u = 0;
1533}
1534
1535
1536/**
1537 * Saves the guest-state as part of VM-exit.
1538 *
1539 * @returns VBox status code.
1540 * @param pVCpu The cross context virtual CPU structure.
1541 * @param uExitReason The VM-exit reason.
1542 */
1543IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1544{
1545 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1546 Assert(pVmcs);
1547
1548 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1549 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1550
1551 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1552 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1553 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1554
1555 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1556}
1557
1558
1559/**
1560 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1561 *
1562 * @returns VBox status code.
1563 * @param pVCpu The cross context virtual CPU structure.
1564 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1565 */
1566IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1567{
1568 /*
1569 * Save guest MSRs.
1570 * See Intel spec. 27.4 "Saving MSRs".
1571 */
1572 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1573 const char *const pszFailure = "VMX-abort";
1574
1575 /*
1576 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1577 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1578 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1579 */
1580 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1581 if (!cMsrs)
1582 return VINF_SUCCESS;
1583
1584 /*
1585 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1586 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1587 * implementation causes a VMX-abort followed by a triple-fault.
1588 */
1589 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1590 if (fIsMsrCountValid)
1591 { /* likely */ }
1592 else
1593 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1594
1595 /*
1596 * Optimization if the guest hypervisor is using the same guest-physical page for both
1597 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1598 */
1599 PVMXAUTOMSR pMsrArea;
1600 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1601 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1602 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1603 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1604 else
1605 {
1606 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1607 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1608 if (RT_SUCCESS(rc))
1609 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1610 else
1611 {
1612 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1613 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1614 }
1615 }
1616
1617 /*
1618 * Update VM-exit MSR store area.
1619 */
1620 PVMXAUTOMSR pMsr = pMsrArea;
1621 Assert(pMsr);
1622 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1623 {
1624 if ( !pMsr->u32Reserved
1625 && pMsr->u32Msr != MSR_IA32_SMBASE
1626 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1627 {
1628 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1629 if (rcStrict == VINF_SUCCESS)
1630 continue;
1631
1632 /*
1633 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1634 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1635 * recording the MSR index in the auxiliary info. field and indicated further by our
1636 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1637 * if possible, or come up with a better, generic solution.
1638 */
1639 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1640 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1641 ? kVmxVDiag_Vmexit_MsrStoreRing3
1642 : kVmxVDiag_Vmexit_MsrStore;
1643 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1644 }
1645 else
1646 {
1647 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1649 }
1650 }
1651
1652 /*
1653 * Commit the VM-exit MSR store are to guest memory.
1654 */
1655 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1656 if (RT_SUCCESS(rc))
1657 return VINF_SUCCESS;
1658
1659 NOREF(uExitReason);
1660 NOREF(pszFailure);
1661
1662 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1663 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1664}
1665
1666
1667/**
1668 * Performs a VMX abort (due to an fatal error during VM-exit).
1669 *
1670 * @returns Strict VBox status code.
1671 * @param pVCpu The cross context virtual CPU structure.
1672 * @param enmAbort The VMX abort reason.
1673 */
1674IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1675{
1676 /*
1677 * Perform the VMX abort.
1678 * See Intel spec. 27.7 "VMX Aborts".
1679 */
1680 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1681
1682 /* We don't support SMX yet. */
1683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1684 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1685 {
1686 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1687 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1688 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1689 }
1690
1691 return VINF_EM_TRIPLE_FAULT;
1692}
1693
1694
1695/**
1696 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1697 *
1698 * @param pVCpu The cross context virtual CPU structure.
1699 */
1700IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1701{
1702 /*
1703 * Load host control registers, debug registers and MSRs.
1704 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1705 */
1706 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1707 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1708
1709 /* CR0. */
1710 {
1711 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1712 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1713 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1714 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1715 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1716 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1717 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1718 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1719 }
1720
1721 /* CR4. */
1722 {
1723 /* Fixed CR4 bits are not modified. */
1724 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1725 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1726 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1727 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1728 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1729 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1730 if (fHostInLongMode)
1731 uValidHostCr4 |= X86_CR4_PAE;
1732 else
1733 uValidHostCr4 &= ~X86_CR4_PCIDE;
1734 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1735 }
1736
1737 /* CR3 (host value validated while checking host-state during VM-entry). */
1738 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1739
1740 /* DR7. */
1741 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1742
1743 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1744
1745 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1746 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1747 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1748 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1749
1750 /* FS, GS bases are loaded later while we load host segment registers. */
1751
1752 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1753 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1754 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1755 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1756 {
1757 if (fHostInLongMode)
1758 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 else
1760 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1761 }
1762
1763 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1764
1765 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1766 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1767 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1768
1769 /* We don't support IA32_BNDCFGS MSR yet. */
1770}
1771
1772
1773/**
1774 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1775 *
1776 * @param pVCpu The cross context virtual CPU structure.
1777 */
1778IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
1779{
1780 /*
1781 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1782 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1783 *
1784 * Warning! Be careful to not touch fields that are reserved by VT-x,
1785 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1786 */
1787 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1788 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1789
1790 /* CS, SS, ES, DS, FS, GS. */
1791 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1792 {
1793 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1794 bool const fUnusable = RT_BOOL(HostSel == 0);
1795 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1796
1797 /* Selector. */
1798 pSelReg->Sel = HostSel;
1799 pSelReg->ValidSel = HostSel;
1800 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1801
1802 /* Limit. */
1803 pSelReg->u32Limit = 0xffffffff;
1804
1805 /* Base. */
1806 pSelReg->u64Base = 0;
1807
1808 /* Attributes. */
1809 if (iSegReg == X86_SREG_CS)
1810 {
1811 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1812 pSelReg->Attr.n.u1DescType = 1;
1813 pSelReg->Attr.n.u2Dpl = 0;
1814 pSelReg->Attr.n.u1Present = 1;
1815 pSelReg->Attr.n.u1Long = fHostInLongMode;
1816 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1817 pSelReg->Attr.n.u1Granularity = 1;
1818 Assert(!pSelReg->Attr.n.u1Unusable);
1819 Assert(!fUnusable);
1820 }
1821 else
1822 {
1823 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1824 pSelReg->Attr.n.u1DescType = 1;
1825 pSelReg->Attr.n.u2Dpl = 0;
1826 pSelReg->Attr.n.u1Present = 1;
1827 pSelReg->Attr.n.u1DefBig = 1;
1828 pSelReg->Attr.n.u1Granularity = 1;
1829 pSelReg->Attr.n.u1Unusable = fUnusable;
1830 }
1831 }
1832
1833 /* FS base. */
1834 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1835 || fHostInLongMode)
1836 {
1837 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1838 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1839 }
1840
1841 /* GS base. */
1842 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1843 || fHostInLongMode)
1844 {
1845 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1846 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1847 }
1848
1849 /* TR. */
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1851 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1852 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1853 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1854 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1855 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1856 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1861 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1862 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1863
1864 /* LDTR (Warning! do not touch the base and limits here). */
1865 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1866 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1867 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1868 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1869
1870 /* GDTR. */
1871 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1872 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1873 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1874
1875 /* IDTR.*/
1876 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1877 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1878 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1879}
1880
1881
1882/**
1883 * Checks host PDPTes as part of VM-exit.
1884 *
1885 * @param pVCpu The cross context virtual CPU structure.
1886 * @param uExitReason The VM-exit reason (for logging purposes).
1887 */
1888IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
1889{
1890 /*
1891 * Check host PDPTEs.
1892 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1893 */
1894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1895 const char *const pszFailure = "VMX-abort";
1896 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1897
1898 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1899 && !fHostInLongMode)
1900 {
1901 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1902 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1903 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1904 if (RT_SUCCESS(rc))
1905 {
1906 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1907 {
1908 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1909 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1910 { /* likely */ }
1911 else
1912 {
1913 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1914 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1915 }
1916 }
1917 }
1918 else
1919 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1920 }
1921
1922 NOREF(pszFailure);
1923 NOREF(uExitReason);
1924 return VINF_SUCCESS;
1925}
1926
1927
1928/**
1929 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1930 *
1931 * @returns VBox status code.
1932 * @param pVCpu The cross context virtual CPU structure.
1933 * @param pszInstr The VMX instruction name (for logging purposes).
1934 */
1935IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1936{
1937 /*
1938 * Load host MSRs.
1939 * See Intel spec. 27.6 "Loading MSRs".
1940 */
1941 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1942 const char *const pszFailure = "VMX-abort";
1943
1944 /*
1945 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1946 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1947 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1948 */
1949 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1950 if (!cMsrs)
1951 return VINF_SUCCESS;
1952
1953 /*
1954 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1955 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1956 * implementation causes a VMX-abort followed by a triple-fault.
1957 */
1958 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1959 if (fIsMsrCountValid)
1960 { /* likely */ }
1961 else
1962 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1963
1964 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1965 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1966 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1967 if (RT_SUCCESS(rc))
1968 {
1969 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1970 Assert(pMsr);
1971 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1972 {
1973 if ( !pMsr->u32Reserved
1974 && pMsr->u32Msr != MSR_K8_FS_BASE
1975 && pMsr->u32Msr != MSR_K8_GS_BASE
1976 && pMsr->u32Msr != MSR_K6_EFER
1977 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1978 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1979 {
1980 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1981 if (rcStrict == VINF_SUCCESS)
1982 continue;
1983
1984 /*
1985 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1986 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1987 * recording the MSR index in the auxiliary info. field and indicated further by our
1988 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1989 * if possible, or come up with a better, generic solution.
1990 */
1991 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1992 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1993 ? kVmxVDiag_Vmexit_MsrLoadRing3
1994 : kVmxVDiag_Vmexit_MsrLoad;
1995 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1996 }
1997 else
1998 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1999 }
2000 }
2001 else
2002 {
2003 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2005 }
2006
2007 NOREF(uExitReason);
2008 NOREF(pszFailure);
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/**
2014 * Loads the host state as part of VM-exit.
2015 *
2016 * @returns Strict VBox status code.
2017 * @param pVCpu The cross context virtual CPU structure.
2018 * @param uExitReason The VM-exit reason (for logging purposes).
2019 */
2020IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2021{
2022 /*
2023 * Load host state.
2024 * See Intel spec. 27.5 "Loading Host State".
2025 */
2026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2027 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2028
2029 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2030 if ( CPUMIsGuestInLongMode(pVCpu)
2031 && !fHostInLongMode)
2032 {
2033 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2034 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2035 }
2036
2037 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2038 iemVmxVmexitLoadHostSegRegs(pVCpu);
2039
2040 /*
2041 * Load host RIP, RSP and RFLAGS.
2042 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2043 */
2044 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2045 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2046 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2047
2048 /* Clear address range monitoring. */
2049 EMMonitorWaitClear(pVCpu);
2050
2051 /* Perform the VMX transition (PGM updates). */
2052 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2053 if (rcStrict == VINF_SUCCESS)
2054 {
2055 /* Check host PDPTEs (only when we've fully switched page tables_. */
2056 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2057 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2058 if (RT_FAILURE(rc))
2059 {
2060 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2061 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2062 }
2063 }
2064 else if (RT_SUCCESS(rcStrict))
2065 {
2066 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2067 uExitReason));
2068 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2069 }
2070 else
2071 {
2072 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2073 return VBOXSTRICTRC_VAL(rcStrict);
2074 }
2075
2076 Assert(rcStrict == VINF_SUCCESS);
2077
2078 /* Load MSRs from the VM-exit auto-load MSR area. */
2079 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2080 if (RT_FAILURE(rc))
2081 {
2082 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2083 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2084 }
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/**
2090 * Gets VM-exit instruction information along with any displacement for an
2091 * instruction VM-exit.
2092 *
2093 * @returns The VM-exit instruction information.
2094 * @param pVCpu The cross context virtual CPU structure.
2095 * @param uExitReason The VM-exit reason.
2096 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2097 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2098 * NULL.
2099 */
2100IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2101{
2102 RTGCPTR GCPtrDisp;
2103 VMXEXITINSTRINFO ExitInstrInfo;
2104 ExitInstrInfo.u = 0;
2105
2106 /*
2107 * Get and parse the ModR/M byte from our decoded opcodes.
2108 */
2109 uint8_t bRm;
2110 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2111 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2112 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2113 {
2114 /*
2115 * ModR/M indicates register addressing.
2116 *
2117 * The primary/secondary register operands are reported in the iReg1 or iReg2
2118 * fields depending on whether it is a read/write form.
2119 */
2120 uint8_t idxReg1;
2121 uint8_t idxReg2;
2122 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2123 {
2124 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2125 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2126 }
2127 else
2128 {
2129 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2130 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 }
2132 ExitInstrInfo.All.u2Scaling = 0;
2133 ExitInstrInfo.All.iReg1 = idxReg1;
2134 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2135 ExitInstrInfo.All.fIsRegOperand = 1;
2136 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2137 ExitInstrInfo.All.iSegReg = 0;
2138 ExitInstrInfo.All.iIdxReg = 0;
2139 ExitInstrInfo.All.fIdxRegInvalid = 1;
2140 ExitInstrInfo.All.iBaseReg = 0;
2141 ExitInstrInfo.All.fBaseRegInvalid = 1;
2142 ExitInstrInfo.All.iReg2 = idxReg2;
2143
2144 /* Displacement not applicable for register addressing. */
2145 GCPtrDisp = 0;
2146 }
2147 else
2148 {
2149 /*
2150 * ModR/M indicates memory addressing.
2151 */
2152 uint8_t uScale = 0;
2153 bool fBaseRegValid = false;
2154 bool fIdxRegValid = false;
2155 uint8_t iBaseReg = 0;
2156 uint8_t iIdxReg = 0;
2157 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2158 {
2159 /*
2160 * Parse the ModR/M, displacement for 16-bit addressing mode.
2161 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2162 */
2163 uint16_t u16Disp = 0;
2164 uint8_t const offDisp = offModRm + sizeof(bRm);
2165 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2166 {
2167 /* Displacement without any registers. */
2168 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2169 }
2170 else
2171 {
2172 /* Register (index and base). */
2173 switch (bRm & X86_MODRM_RM_MASK)
2174 {
2175 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2180 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2181 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2182 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2183 }
2184
2185 /* Register + displacement. */
2186 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2187 {
2188 case 0: break;
2189 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2190 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2191 default:
2192 {
2193 /* Register addressing, handled at the beginning. */
2194 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2195 break;
2196 }
2197 }
2198 }
2199
2200 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2201 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2202 }
2203 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2204 {
2205 /*
2206 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2207 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2208 */
2209 uint32_t u32Disp = 0;
2210 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2211 {
2212 /* Displacement without any registers. */
2213 uint8_t const offDisp = offModRm + sizeof(bRm);
2214 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2215 }
2216 else
2217 {
2218 /* Register (and perhaps scale, index and base). */
2219 uint8_t offDisp = offModRm + sizeof(bRm);
2220 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2221 if (iBaseReg == 4)
2222 {
2223 /* An SIB byte follows the ModR/M byte, parse it. */
2224 uint8_t bSib;
2225 uint8_t const offSib = offModRm + sizeof(bRm);
2226 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2227
2228 /* A displacement may follow SIB, update its offset. */
2229 offDisp += sizeof(bSib);
2230
2231 /* Get the scale. */
2232 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2233
2234 /* Get the index register. */
2235 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2236 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2237
2238 /* Get the base register. */
2239 iBaseReg = bSib & X86_SIB_BASE_MASK;
2240 fBaseRegValid = true;
2241 if (iBaseReg == 5)
2242 {
2243 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2244 {
2245 /* Mod is 0 implies a 32-bit displacement with no base. */
2246 fBaseRegValid = false;
2247 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2248 }
2249 else
2250 {
2251 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2252 iBaseReg = X86_GREG_xBP;
2253 }
2254 }
2255 }
2256
2257 /* Register + displacement. */
2258 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2259 {
2260 case 0: /* Handled above */ break;
2261 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2262 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2263 default:
2264 {
2265 /* Register addressing, handled at the beginning. */
2266 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2267 break;
2268 }
2269 }
2270 }
2271
2272 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2273 }
2274 else
2275 {
2276 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2277
2278 /*
2279 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2280 * See Intel instruction spec. 2.2 "IA-32e Mode".
2281 */
2282 uint64_t u64Disp = 0;
2283 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2284 if (fRipRelativeAddr)
2285 {
2286 /*
2287 * RIP-relative addressing mode.
2288 *
2289 * The displacement is 32-bit signed implying an offset range of +/-2G.
2290 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2291 */
2292 uint8_t const offDisp = offModRm + sizeof(bRm);
2293 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2294 }
2295 else
2296 {
2297 uint8_t offDisp = offModRm + sizeof(bRm);
2298
2299 /*
2300 * Register (and perhaps scale, index and base).
2301 *
2302 * REX.B extends the most-significant bit of the base register. However, REX.B
2303 * is ignored while determining whether an SIB follows the opcode. Hence, we
2304 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2305 *
2306 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2307 */
2308 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2309 if (iBaseReg == 4)
2310 {
2311 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2312 uint8_t bSib;
2313 uint8_t const offSib = offModRm + sizeof(bRm);
2314 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2315
2316 /* Displacement may follow SIB, update its offset. */
2317 offDisp += sizeof(bSib);
2318
2319 /* Get the scale. */
2320 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2321
2322 /* Get the index. */
2323 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2324 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2325
2326 /* Get the base. */
2327 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2328 fBaseRegValid = true;
2329 if (iBaseReg == 5)
2330 {
2331 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2332 {
2333 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2334 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2335 }
2336 else
2337 {
2338 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2339 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2340 }
2341 }
2342 }
2343 iBaseReg |= pVCpu->iem.s.uRexB;
2344
2345 /* Register + displacement. */
2346 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2347 {
2348 case 0: /* Handled above */ break;
2349 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2350 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2351 default:
2352 {
2353 /* Register addressing, handled at the beginning. */
2354 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2355 break;
2356 }
2357 }
2358 }
2359
2360 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2361 }
2362
2363 /*
2364 * The primary or secondary register operand is reported in iReg2 depending
2365 * on whether the primary operand is in read/write form.
2366 */
2367 uint8_t idxReg2;
2368 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2369 {
2370 idxReg2 = bRm & X86_MODRM_RM_MASK;
2371 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2372 idxReg2 |= pVCpu->iem.s.uRexB;
2373 }
2374 else
2375 {
2376 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexReg;
2379 }
2380 ExitInstrInfo.All.u2Scaling = uScale;
2381 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2382 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2383 ExitInstrInfo.All.fIsRegOperand = 0;
2384 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2385 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2386 ExitInstrInfo.All.iIdxReg = iIdxReg;
2387 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2388 ExitInstrInfo.All.iBaseReg = iBaseReg;
2389 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2390 ExitInstrInfo.All.iReg2 = idxReg2;
2391 }
2392
2393 /*
2394 * Handle exceptions to the norm for certain instructions.
2395 * (e.g. some instructions convey an instruction identity in place of iReg2).
2396 */
2397 switch (uExitReason)
2398 {
2399 case VMX_EXIT_GDTR_IDTR_ACCESS:
2400 {
2401 Assert(VMXINSTRID_IS_VALID(uInstrId));
2402 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2403 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2404 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2405 break;
2406 }
2407
2408 case VMX_EXIT_LDTR_TR_ACCESS:
2409 {
2410 Assert(VMXINSTRID_IS_VALID(uInstrId));
2411 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2412 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2413 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2414 break;
2415 }
2416
2417 case VMX_EXIT_RDRAND:
2418 case VMX_EXIT_RDSEED:
2419 {
2420 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2421 break;
2422 }
2423 }
2424
2425 /* Update displacement and return the constructed VM-exit instruction information field. */
2426 if (pGCPtrDisp)
2427 *pGCPtrDisp = GCPtrDisp;
2428
2429 return ExitInstrInfo.u;
2430}
2431
2432
2433/**
2434 * VMX VM-exit handler.
2435 *
2436 * @returns Strict VBox status code.
2437 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2438 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2439 * triple-fault.
2440 *
2441 * @param pVCpu The cross context virtual CPU structure.
2442 * @param uExitReason The VM-exit reason.
2443 * @param u64ExitQual The Exit qualification.
2444 */
2445IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2446{
2447# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2448 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2449 return VINF_EM_RAW_EMULATE_INSTR;
2450# else
2451 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2452 Assert(pVmcs);
2453
2454 /*
2455 * Import all the guest-CPU state.
2456 *
2457 * HM on returning to guest execution would have to reset up a whole lot of state
2458 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2459 * the state and flag reloading the entire state on re-entry. So import the entire
2460 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2461 */
2462 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2463
2464 /* Ensure VM-entry interruption information valid bit isn't set. */
2465 Assert(!VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo));
2466
2467 /*
2468 * Update the VM-exit reason and Exit qualification.
2469 * Other VMCS read-only data fields are expected to be updated by the caller already.
2470 */
2471 pVmcs->u32RoExitReason = uExitReason;
2472 pVmcs->u64RoExitQual.u = u64ExitQual;
2473 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2474 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2475
2476 /*
2477 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2478 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2479 */
2480 {
2481 uint8_t uVector;
2482 uint32_t fFlags;
2483 uint32_t uErrCode;
2484 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2485 if (fInEventDelivery)
2486 {
2487 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2488 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2489 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2490 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2491 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2492 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2493 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2494 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2495 }
2496 }
2497
2498 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2499 Assert(pVmcs->u64RoIoRcx.u == 0);
2500 Assert(pVmcs->u64RoIoRsi.u == 0);
2501 Assert(pVmcs->u64RoIoRdi.u == 0);
2502 Assert(pVmcs->u64RoIoRip.u == 0);
2503
2504 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2505 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2506 {
2507 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2508 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2509 }
2510
2511 /*
2512 * Save the guest state back into the VMCS.
2513 * We only need to save the state when the VM-entry was successful.
2514 */
2515 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2516 if (!fVmentryFailed)
2517 {
2518 /*
2519 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2520 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2521 *
2522 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2523 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2524 * as guest-CPU state would not been modified. Hence for now, we do this only when
2525 * the VM-entry succeeded.
2526 */
2527 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2528 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2529 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2530 {
2531 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2532 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2533 else
2534 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2535 }
2536
2537 /*
2538 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2539 * occurs in enclave mode/SMM which we don't support yet.
2540 *
2541 * If we ever add support for it, we can pass just the lower bits to the functions
2542 * below, till then an assert should suffice.
2543 */
2544 Assert(!RT_HI_U16(uExitReason));
2545
2546 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2547 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2548 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2549 if (RT_SUCCESS(rc))
2550 { /* likely */ }
2551 else
2552 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2553
2554 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2555 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2556 }
2557 else
2558 {
2559 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2560 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2561 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2562 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2563 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2564 }
2565
2566 /*
2567 * Clear any pending VMX nested-guest force-flags.
2568 * These force-flags have no effect on guest execution and will
2569 * be re-evaluated and setup on the next nested-guest VM-entry.
2570 */
2571 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2572 | VMCPU_FF_VMX_MTF
2573 | VMCPU_FF_VMX_APIC_WRITE
2574 | VMCPU_FF_VMX_INT_WINDOW
2575 | VMCPU_FF_VMX_NMI_WINDOW);
2576
2577 /* Restore the host (outer guest) state. */
2578 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2579 if (RT_SUCCESS(rcStrict))
2580 {
2581 Assert(rcStrict == VINF_SUCCESS);
2582 rcStrict = VINF_VMX_VMEXIT;
2583 }
2584 else
2585 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2586
2587 /* Notify HM that the current VMCS fields have been modified. */
2588 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2589
2590 /* Notify HM that we've completed the VM-exit. */
2591 HMNotifyVmxNstGstVmexit(pVCpu);
2592
2593 /* We're no longer in nested-guest execution mode. */
2594 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2595
2596# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2597 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2598 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2599 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2600 if (rcSched != VINF_SUCCESS)
2601 iemSetPassUpStatus(pVCpu, rcSched);
2602# endif
2603 return rcStrict;
2604# endif
2605}
2606
2607
2608/**
2609 * VMX VM-exit handler for VM-exits due to instruction execution.
2610 *
2611 * This is intended for instructions where the caller provides all the relevant
2612 * VM-exit information.
2613 *
2614 * @returns Strict VBox status code.
2615 * @param pVCpu The cross context virtual CPU structure.
2616 * @param pExitInfo Pointer to the VM-exit information.
2617 */
2618IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2619{
2620 /*
2621 * For instructions where any of the following fields are not applicable:
2622 * - Exit qualification must be cleared.
2623 * - VM-exit instruction info. is undefined.
2624 * - Guest-linear address is undefined.
2625 * - Guest-physical address is undefined.
2626 *
2627 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2628 * instruction execution. For VM-exits that are not due to instruction execution this
2629 * field is undefined.
2630 *
2631 * In our implementation in IEM, all undefined fields are generally cleared. However,
2632 * if the caller supplies information (from say the physical CPU directly) it is
2633 * then possible that the undefined fields are not cleared.
2634 *
2635 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2636 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2637 */
2638 Assert(pExitInfo);
2639 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2640 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2641 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2642
2643 /* Update all the relevant fields from the VM-exit instruction information struct. */
2644 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2645 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2646 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2647 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2648
2649 /* Perform the VM-exit. */
2650 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2651}
2652
2653
2654/**
2655 * VMX VM-exit handler for VM-exits due to instruction execution.
2656 *
2657 * This is intended for instructions that only provide the VM-exit instruction
2658 * length.
2659 *
2660 * @param pVCpu The cross context virtual CPU structure.
2661 * @param uExitReason The VM-exit reason.
2662 * @param cbInstr The instruction length in bytes.
2663 */
2664IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2665{
2666 VMXVEXITINFO ExitInfo;
2667 RT_ZERO(ExitInfo);
2668 ExitInfo.uReason = uExitReason;
2669 ExitInfo.cbInstr = cbInstr;
2670
2671#ifdef VBOX_STRICT
2672 /*
2673 * To prevent us from shooting ourselves in the foot.
2674 * The follow instructions should convey more than just the instruction length.
2675 */
2676 switch (uExitReason)
2677 {
2678 case VMX_EXIT_INVEPT:
2679 case VMX_EXIT_INVPCID:
2680 case VMX_EXIT_INVVPID:
2681 case VMX_EXIT_LDTR_TR_ACCESS:
2682 case VMX_EXIT_GDTR_IDTR_ACCESS:
2683 case VMX_EXIT_VMCLEAR:
2684 case VMX_EXIT_VMPTRLD:
2685 case VMX_EXIT_VMPTRST:
2686 case VMX_EXIT_VMREAD:
2687 case VMX_EXIT_VMWRITE:
2688 case VMX_EXIT_VMXON:
2689 case VMX_EXIT_XRSTORS:
2690 case VMX_EXIT_XSAVES:
2691 case VMX_EXIT_RDRAND:
2692 case VMX_EXIT_RDSEED:
2693 case VMX_EXIT_IO_INSTR:
2694 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2695 break;
2696 }
2697#endif
2698
2699 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2700}
2701
2702
2703/**
2704 * VMX VM-exit handler for VM-exits due to instruction execution.
2705 *
2706 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2707 * instruction information and Exit qualification fields.
2708 *
2709 * @param pVCpu The cross context virtual CPU structure.
2710 * @param uExitReason The VM-exit reason.
2711 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2712 * @param cbInstr The instruction length in bytes.
2713 *
2714 * @remarks Do not use this for INS/OUTS instruction.
2715 */
2716IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2717{
2718 VMXVEXITINFO ExitInfo;
2719 RT_ZERO(ExitInfo);
2720 ExitInfo.uReason = uExitReason;
2721 ExitInfo.cbInstr = cbInstr;
2722
2723 /*
2724 * Update the Exit qualification field with displacement bytes.
2725 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2726 */
2727 switch (uExitReason)
2728 {
2729 case VMX_EXIT_INVEPT:
2730 case VMX_EXIT_INVPCID:
2731 case VMX_EXIT_INVVPID:
2732 case VMX_EXIT_LDTR_TR_ACCESS:
2733 case VMX_EXIT_GDTR_IDTR_ACCESS:
2734 case VMX_EXIT_VMCLEAR:
2735 case VMX_EXIT_VMPTRLD:
2736 case VMX_EXIT_VMPTRST:
2737 case VMX_EXIT_VMREAD:
2738 case VMX_EXIT_VMWRITE:
2739 case VMX_EXIT_VMXON:
2740 case VMX_EXIT_XRSTORS:
2741 case VMX_EXIT_XSAVES:
2742 case VMX_EXIT_RDRAND:
2743 case VMX_EXIT_RDSEED:
2744 {
2745 /* Construct the VM-exit instruction information. */
2746 RTGCPTR GCPtrDisp;
2747 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2748
2749 /* Update the VM-exit instruction information. */
2750 ExitInfo.InstrInfo.u = uInstrInfo;
2751
2752 /* Update the Exit qualification. */
2753 ExitInfo.u64Qual = GCPtrDisp;
2754 break;
2755 }
2756
2757 default:
2758 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2759 break;
2760 }
2761
2762 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2763}
2764
2765
2766/**
2767 * VMX VM-exit handler for VM-exits due to INVLPG.
2768 *
2769 * @returns Strict VBox status code.
2770 * @param pVCpu The cross context virtual CPU structure.
2771 * @param GCPtrPage The guest-linear address of the page being invalidated.
2772 * @param cbInstr The instruction length in bytes.
2773 */
2774IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2775{
2776 VMXVEXITINFO ExitInfo;
2777 RT_ZERO(ExitInfo);
2778 ExitInfo.uReason = VMX_EXIT_INVLPG;
2779 ExitInfo.cbInstr = cbInstr;
2780 ExitInfo.u64Qual = GCPtrPage;
2781 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2782
2783 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2784}
2785
2786
2787/**
2788 * VMX VM-exit handler for VM-exits due to LMSW.
2789 *
2790 * @returns Strict VBox status code.
2791 * @param pVCpu The cross context virtual CPU structure.
2792 * @param uGuestCr0 The current guest CR0.
2793 * @param pu16NewMsw The machine-status word specified in LMSW's source
2794 * operand. This will be updated depending on the VMX
2795 * guest/host CR0 mask if LMSW is not intercepted.
2796 * @param GCPtrEffDst The guest-linear address of the source operand in case
2797 * of a memory operand. For register operand, pass
2798 * NIL_RTGCPTR.
2799 * @param cbInstr The instruction length in bytes.
2800 */
2801IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2802 uint8_t cbInstr)
2803{
2804 Assert(pu16NewMsw);
2805
2806 uint16_t const uNewMsw = *pu16NewMsw;
2807 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2808 {
2809 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2810
2811 VMXVEXITINFO ExitInfo;
2812 RT_ZERO(ExitInfo);
2813 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2814 ExitInfo.cbInstr = cbInstr;
2815
2816 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2817 if (fMemOperand)
2818 {
2819 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2820 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2821 }
2822
2823 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2824 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2825 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2826 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2827
2828 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2829 }
2830
2831 /*
2832 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2833 * CR0 guest/host mask must be left unmodified.
2834 *
2835 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2836 */
2837 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2838 Assert(pVmcs);
2839 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2840 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2841 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2842
2843 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2844}
2845
2846
2847/**
2848 * VMX VM-exit handler for VM-exits due to CLTS.
2849 *
2850 * @returns Strict VBox status code.
2851 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2852 * VM-exit but must not modify the guest CR0.TS bit.
2853 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2854 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2855 * CR0 fixed bits in VMX operation).
2856 * @param pVCpu The cross context virtual CPU structure.
2857 * @param cbInstr The instruction length in bytes.
2858 */
2859IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
2860{
2861 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2862 Assert(pVmcs);
2863
2864 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2865 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2866
2867 /*
2868 * If CR0.TS is owned by the host:
2869 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2870 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2871 * CLTS instruction completes without clearing CR0.TS.
2872 *
2873 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2874 */
2875 if (fGstHostMask & X86_CR0_TS)
2876 {
2877 if (fReadShadow & X86_CR0_TS)
2878 {
2879 Log2(("clts: Guest intercept -> VM-exit\n"));
2880
2881 VMXVEXITINFO ExitInfo;
2882 RT_ZERO(ExitInfo);
2883 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2884 ExitInfo.cbInstr = cbInstr;
2885 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2886 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2887 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2888 }
2889
2890 return VINF_VMX_MODIFIES_BEHAVIOR;
2891 }
2892
2893 /*
2894 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2895 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2896 */
2897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2898}
2899
2900
2901/**
2902 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2903 * (CR0/CR4 write).
2904 *
2905 * @returns Strict VBox status code.
2906 * @param pVCpu The cross context virtual CPU structure.
2907 * @param iCrReg The control register (either CR0 or CR4).
2908 * @param uGuestCrX The current guest CR0/CR4.
2909 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2910 * VM-exit is caused.
2911 * @param iGReg The general register from which the CR0/CR4 value is being
2912 * loaded.
2913 * @param cbInstr The instruction length in bytes.
2914 */
2915IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2916 uint8_t cbInstr)
2917{
2918 Assert(puNewCrX);
2919 Assert(iCrReg == 0 || iCrReg == 4);
2920 Assert(iGReg < X86_GREG_COUNT);
2921
2922 uint64_t const uNewCrX = *puNewCrX;
2923 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2924 {
2925 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2926
2927 VMXVEXITINFO ExitInfo;
2928 RT_ZERO(ExitInfo);
2929 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2930 ExitInfo.cbInstr = cbInstr;
2931 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2932 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2933 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2934 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2935 }
2936
2937 /*
2938 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2939 * must not be modified the instruction.
2940 *
2941 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2942 */
2943 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2944 Assert(pVmcs);
2945 uint64_t uGuestCrX;
2946 uint64_t fGstHostMask;
2947 if (iCrReg == 0)
2948 {
2949 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2950 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2951 fGstHostMask = pVmcs->u64Cr0Mask.u;
2952 }
2953 else
2954 {
2955 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2956 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2957 fGstHostMask = pVmcs->u64Cr4Mask.u;
2958 }
2959
2960 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2961 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2962}
2963
2964
2965/**
2966 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2967 *
2968 * @returns VBox strict status code.
2969 * @param pVCpu The cross context virtual CPU structure.
2970 * @param iGReg The general register to which the CR3 value is being stored.
2971 * @param cbInstr The instruction length in bytes.
2972 */
2973IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
2974{
2975 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2976 Assert(pVmcs);
2977 Assert(iGReg < X86_GREG_COUNT);
2978 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2979
2980 /*
2981 * If the CR3-store exiting control is set, we must cause a VM-exit.
2982 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2983 */
2984 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2985 {
2986 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2987
2988 VMXVEXITINFO ExitInfo;
2989 RT_ZERO(ExitInfo);
2990 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2991 ExitInfo.cbInstr = cbInstr;
2992 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2993 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2994 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2995 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2996 }
2997
2998 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2999}
3000
3001
3002/**
3003 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3004 *
3005 * @returns VBox strict status code.
3006 * @param pVCpu The cross context virtual CPU structure.
3007 * @param uNewCr3 The new CR3 value.
3008 * @param iGReg The general register from which the CR3 value is being
3009 * loaded.
3010 * @param cbInstr The instruction length in bytes.
3011 */
3012IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3013{
3014 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3015 Assert(pVmcs);
3016 Assert(iGReg < X86_GREG_COUNT);
3017
3018 /*
3019 * If the CR3-load exiting control is set and the new CR3 value does not
3020 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3021 *
3022 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3023 */
3024 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3025 {
3026 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3027
3028 VMXVEXITINFO ExitInfo;
3029 RT_ZERO(ExitInfo);
3030 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3031 ExitInfo.cbInstr = cbInstr;
3032 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3033 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3034 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3035 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3036 }
3037
3038 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3039}
3040
3041
3042/**
3043 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3044 *
3045 * @returns VBox strict status code.
3046 * @param pVCpu The cross context virtual CPU structure.
3047 * @param iGReg The general register to which the CR8 value is being stored.
3048 * @param cbInstr The instruction length in bytes.
3049 */
3050IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3051{
3052 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3053 Assert(pVmcs);
3054 Assert(iGReg < X86_GREG_COUNT);
3055
3056 /*
3057 * If the CR8-store exiting control is set, we must cause a VM-exit.
3058 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3059 */
3060 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3061 {
3062 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3063
3064 VMXVEXITINFO ExitInfo;
3065 RT_ZERO(ExitInfo);
3066 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3067 ExitInfo.cbInstr = cbInstr;
3068 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3069 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3070 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3071 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3072 }
3073
3074 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3075}
3076
3077
3078/**
3079 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3080 *
3081 * @returns VBox strict status code.
3082 * @param pVCpu The cross context virtual CPU structure.
3083 * @param iGReg The general register from which the CR8 value is being
3084 * loaded.
3085 * @param cbInstr The instruction length in bytes.
3086 */
3087IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3088{
3089 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3090 Assert(pVmcs);
3091 Assert(iGReg < X86_GREG_COUNT);
3092
3093 /*
3094 * If the CR8-load exiting control is set, we must cause a VM-exit.
3095 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3096 */
3097 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3098 {
3099 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3100
3101 VMXVEXITINFO ExitInfo;
3102 RT_ZERO(ExitInfo);
3103 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3104 ExitInfo.cbInstr = cbInstr;
3105 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3106 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3107 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3108 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3109 }
3110
3111 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3112}
3113
3114
3115/**
3116 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3117 * GReg,DRx' (DRx read).
3118 *
3119 * @returns VBox strict status code.
3120 * @param pVCpu The cross context virtual CPU structure.
3121 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3122 * VMXINSTRID_MOV_FROM_DRX).
3123 * @param iDrReg The debug register being accessed.
3124 * @param iGReg The general register to/from which the DRx value is being
3125 * store/loaded.
3126 * @param cbInstr The instruction length in bytes.
3127 */
3128IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3129 uint8_t cbInstr)
3130{
3131 Assert(iDrReg <= 7);
3132 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3133 Assert(iGReg < X86_GREG_COUNT);
3134
3135 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3136 Assert(pVmcs);
3137
3138 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3139 {
3140 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3141 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3142 VMXVEXITINFO ExitInfo;
3143 RT_ZERO(ExitInfo);
3144 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3145 ExitInfo.cbInstr = cbInstr;
3146 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3147 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3148 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3149 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3150 }
3151
3152 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3153}
3154
3155
3156/**
3157 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3158 *
3159 * @returns VBox strict status code.
3160 * @param pVCpu The cross context virtual CPU structure.
3161 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3162 * VMXINSTRID_IO_OUT).
3163 * @param u16Port The I/O port being accessed.
3164 * @param fImm Whether the I/O port was encoded using an immediate operand
3165 * or the implicit DX register.
3166 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3167 * @param cbInstr The instruction length in bytes.
3168 */
3169IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3170 uint8_t cbInstr)
3171{
3172 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3173 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3174
3175 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3176 if (fIntercept)
3177 {
3178 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3179 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3180 VMXVEXITINFO ExitInfo;
3181 RT_ZERO(ExitInfo);
3182 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3183 ExitInfo.cbInstr = cbInstr;
3184 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3185 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3186 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3187 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3188 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3189 }
3190
3191 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3192}
3193
3194
3195/**
3196 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3197 *
3198 * @returns VBox strict status code.
3199 * @param pVCpu The cross context virtual CPU structure.
3200 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3201 * VMXINSTRID_IO_OUTS).
3202 * @param u16Port The I/O port being accessed.
3203 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3204 * @param fRep Whether the instruction has a REP prefix or not.
3205 * @param ExitInstrInfo The VM-exit instruction info. field.
3206 * @param cbInstr The instruction length in bytes.
3207 */
3208IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3209 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3210{
3211 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3212 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3213 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3214 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3215 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3216
3217 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3218 if (fIntercept)
3219 {
3220 /*
3221 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3222 */
3223 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3224 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3225 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3226 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3227 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3228
3229 uint32_t uDirection;
3230 uint64_t uGuestLinearAddr;
3231 if (uInstrId == VMXINSTRID_IO_INS)
3232 {
3233 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3234 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3235 }
3236 else
3237 {
3238 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3239 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3240 }
3241
3242 /*
3243 * If the segment is unusable, the guest-linear address in undefined.
3244 * We shall clear it for consistency.
3245 *
3246 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3247 */
3248 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3249 uGuestLinearAddr = 0;
3250
3251 VMXVEXITINFO ExitInfo;
3252 RT_ZERO(ExitInfo);
3253 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3254 ExitInfo.cbInstr = cbInstr;
3255 ExitInfo.InstrInfo = ExitInstrInfo;
3256 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3257 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3258 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3259 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3260 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3261 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3262 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3263 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3264 }
3265
3266 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3267}
3268
3269
3270/**
3271 * VMX VM-exit handler for VM-exits due to MWAIT.
3272 *
3273 * @returns VBox strict status code.
3274 * @param pVCpu The cross context virtual CPU structure.
3275 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3276 * @param cbInstr The instruction length in bytes.
3277 */
3278IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3279{
3280 VMXVEXITINFO ExitInfo;
3281 RT_ZERO(ExitInfo);
3282 ExitInfo.uReason = VMX_EXIT_MWAIT;
3283 ExitInfo.cbInstr = cbInstr;
3284 ExitInfo.u64Qual = fMonitorHwArmed;
3285 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3286}
3287
3288
3289/**
3290 * VMX VM-exit handler for VM-exits due to PAUSE.
3291 *
3292 * @returns VBox strict status code.
3293 * @param pVCpu The cross context virtual CPU structure.
3294 * @param cbInstr The instruction length in bytes.
3295 */
3296IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3297{
3298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3299 Assert(pVmcs);
3300
3301 /*
3302 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3303 * "PAUSE-loop exiting" control.
3304 *
3305 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3306 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3307 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3308 * a VM-exit.
3309 *
3310 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3311 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3312 */
3313 bool fIntercept = false;
3314 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3315 fIntercept = true;
3316 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3317 && pVCpu->iem.s.uCpl == 0)
3318 {
3319 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3320
3321 /*
3322 * A previous-PAUSE-tick value of 0 is used to identify the first time
3323 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3324 * consider this to be the first execution of PAUSE in a loop according
3325 * to the Intel.
3326 *
3327 * All subsequent records for the previous-PAUSE-tick we ensure that it
3328 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3329 */
3330 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3331 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3332 uint64_t const uTick = TMCpuTickGet(pVCpu);
3333 uint32_t const uPleGap = pVmcs->u32PleGap;
3334 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3335 if ( *puPrevPauseTick == 0
3336 || uTick - *puPrevPauseTick > uPleGap)
3337 *puFirstPauseLoopTick = uTick;
3338 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3339 fIntercept = true;
3340
3341 *puPrevPauseTick = uTick | 1;
3342 }
3343
3344 if (fIntercept)
3345 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3346
3347 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3348}
3349
3350
3351/**
3352 * VMX VM-exit handler for VM-exits due to task switches.
3353 *
3354 * @returns VBox strict status code.
3355 * @param pVCpu The cross context virtual CPU structure.
3356 * @param enmTaskSwitch The cause of the task switch.
3357 * @param SelNewTss The selector of the new TSS.
3358 * @param cbInstr The instruction length in bytes.
3359 */
3360IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3361{
3362 /*
3363 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3364 *
3365 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3366 * instruction or delivery of the exception generated by one of these instructions
3367 * lead to a task switch through a task gate in the IDT, we need to provide the
3368 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3369 * leaves the VM-exit instruction length field undefined.
3370 *
3371 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3372 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3373 */
3374 Assert(cbInstr <= 15);
3375
3376 uint8_t uType;
3377 switch (enmTaskSwitch)
3378 {
3379 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3380 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3381 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3382 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3383 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3384 }
3385
3386 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3387 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3388 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3389 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3390}
3391
3392
3393/**
3394 * VMX VM-exit handler for VM-exits due to task switches.
3395 *
3396 * This is intended for task switches where the caller provides all the relevant
3397 * VM-exit information.
3398 *
3399 * @returns VBox strict status code.
3400 * @param pVCpu The cross context virtual CPU structure.
3401 * @param pExitInfo Pointer to the VM-exit information.
3402 * @param pExitEventInfo Pointer to the VM-exit event information.
3403 */
3404IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3405 PCVMXVEXITEVENTINFO pExitEventInfo)
3406{
3407 Assert(pExitInfo);
3408 Assert(pExitEventInfo);
3409
3410 /* The Exit qualification is mandatory for all task-switch VM-exits. */
3411 uint64_t const u64ExitQual = pExitInfo->u64Qual;
3412 iemVmxVmcsSetExitQual(pVCpu, u64ExitQual);
3413
3414 /*
3415 * Figure out if an instruction was the source of the task switch.
3416 *
3417 * If the task-switch was due to CALL/IRET/JMP instruction or due to the delivery
3418 * of an event generated by a software interrupt (INT-N), privileged software
3419 * interrupt (INT1/ICEBP) or software exception (INT3/INTO) then the CPU provides
3420 * the instruction length.
3421 */
3422 bool fHasInstrLen;
3423 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(u64ExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
3424 {
3425 /* Check if an event delivery through IDT caused a task switch VM-exit. */
3426 uint32_t const uIdtVectInfo = pExitEventInfo->uIdtVectoringInfo;
3427 bool const fIdtVectInfoValid = VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectInfo);
3428 if (fIdtVectInfoValid)
3429 {
3430 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectInfo);
3431 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectInfo))
3432 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3433
3434 uint8_t const fIdtVectType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectInfo);
3435 if ( fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
3436 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT
3437 || fIdtVectType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT)
3438 fHasInstrLen = true;
3439 else
3440 fHasInstrLen = false;
3441 }
3442 else
3443 fHasInstrLen = false;
3444 }
3445 else
3446 {
3447 /* CALL, IRET or JMP instruction caused the task switch VM-exit. */
3448 fHasInstrLen = true;
3449 }
3450
3451 if (fHasInstrLen)
3452 {
3453 Assert(pExitInfo->cbInstr > 0);
3454 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3455 }
3456 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3457}
3458
3459
3460/**
3461 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3462 *
3463 * @returns VBox strict status code.
3464 * @param pVCpu The cross context virtual CPU structure.
3465 */
3466IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3467{
3468 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3469 Assert(pVmcs);
3470
3471 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3472 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3473 {
3474 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3475 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3476
3477 /*
3478 * Calculate the current VMX-preemption timer value.
3479 * Only if the value has reached zero, we cause the VM-exit.
3480 */
3481 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3482 if (!uPreemptTimer)
3483 {
3484 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3485 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3486 pVmcs->u32PreemptTimer = 0;
3487
3488 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3489 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3490 }
3491 }
3492
3493 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3494}
3495
3496
3497/**
3498 * VMX VM-exit handler for VM-exits due to external interrupts.
3499 *
3500 * @returns VBox strict status code.
3501 * @param pVCpu The cross context virtual CPU structure.
3502 * @param uVector The external interrupt vector (pass 0 if the interrupt
3503 * is still pending since we typically won't know the
3504 * vector).
3505 * @param fIntPending Whether the external interrupt is pending or
3506 * acknowledged in the interrupt controller.
3507 */
3508IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3509{
3510 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3511 Assert(pVmcs);
3512 Assert(fIntPending || uVector == 0);
3513
3514 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3515 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3516 * functions require prior checking of a blanket intercept and which don't.
3517 * It is better for the caller to check a blanket intercept performance wise
3518 * than making a function call. Leaving this as a todo because it is more
3519 * a performance issue. */
3520
3521 /* The VM-exit is subject to "External interrupt exiting" being set. */
3522 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3523 {
3524 if (fIntPending)
3525 {
3526 /*
3527 * If the interrupt is pending and we don't need to acknowledge the
3528 * interrupt on VM-exit, cause the VM-exit immediately.
3529 *
3530 * See Intel spec 25.2 "Other Causes Of VM Exits".
3531 */
3532 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3533 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3534
3535 /*
3536 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3537 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3538 * acknowledged that the interrupt has been consumed.
3539 */
3540 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3541 }
3542
3543 /*
3544 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3545 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3546 * all set, we cause the VM-exit now. We need to record the external interrupt that
3547 * just occurred in the VM-exit interruption information field.
3548 *
3549 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3550 */
3551 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3552 {
3553 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3554 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3555 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3556 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3557 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3558 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3559 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3560 }
3561 }
3562
3563 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3564}
3565
3566
3567/**
3568 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3569 * an event.
3570 *
3571 * @returns VBox strict status code.
3572 * @param pVCpu The cross context virtual CPU structure.
3573 */
3574IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3575{
3576 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3577 Assert(pVmcs);
3578
3579 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3580 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3581 {
3582 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3583 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3584 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3585 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3586 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3587 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3588 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3589 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3590 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3591
3592 /*
3593 * A VM-exit is not considered to occur during event delivery when the original
3594 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3595 * using the exception bitmap).
3596 *
3597 * Therefore, we must clear the original event from the IDT-vectoring fields which
3598 * would've been recorded before causing the VM-exit.
3599 *
3600 * 27.2.3 "Information for VM Exits During Event Delivery"
3601 */
3602 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3603 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3604 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3605 }
3606
3607 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3608}
3609
3610
3611/**
3612 * VMX VM-exit handler for VM-exit due to delivery of an events.
3613 *
3614 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3615 * all the relevant VM-exit information.
3616 *
3617 * @returns VBox strict status code.
3618 * @param pVCpu The cross context virtual CPU structure.
3619 * @param pExitInfo Pointer to the VM-exit information.
3620 * @param pExitEventInfo Pointer to the VM-exit event information.
3621 */
3622IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3623{
3624 Assert(pExitInfo);
3625 Assert(pExitEventInfo);
3626 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3627
3628 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3629 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3630 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3631 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3632 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3633 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3634}
3635
3636
3637/**
3638 * VMX VM-exit handler for VM-exits due to delivery of an event.
3639 *
3640 * @returns VBox strict status code.
3641 * @param pVCpu The cross context virtual CPU structure.
3642 * @param uVector The interrupt / exception vector.
3643 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3644 * @param uErrCode The error code associated with the event.
3645 * @param uCr2 The CR2 value in case of a \#PF exception.
3646 * @param cbInstr The instruction length in bytes.
3647 */
3648IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3649 uint8_t cbInstr)
3650{
3651 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3652 Assert(pVmcs);
3653
3654 /*
3655 * If the event is being injected as part of VM-entry, it is -not- subject to event
3656 * intercepts in the nested-guest. However, secondary exceptions that occur during
3657 * injection of any event -are- subject to event interception.
3658 *
3659 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3660 */
3661 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3662 {
3663 /*
3664 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3665 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3666 *
3667 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3668 */
3669 if ( uVector == X86_XCPT_NMI
3670 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3671 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3672 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3673 else
3674 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3675
3676 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3677 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3678 }
3679
3680 /*
3681 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3682 * If not, the caller will continue delivery of the external interrupt as it would
3683 * normally. The interrupt is no longer pending in the interrupt controller at this
3684 * point.
3685 */
3686 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3687 {
3688 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3689 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3690 }
3691
3692 /*
3693 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3694 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3695 * interrupts.
3696 */
3697 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3698 bool fIntercept;
3699 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3700 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3701 {
3702 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3703 }
3704 else
3705 {
3706 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3707 fIntercept = false;
3708 }
3709
3710 /*
3711 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3712 * relevant VM-exit information and cause the VM-exit.
3713 */
3714 if (fIntercept)
3715 {
3716 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3717
3718 /* Construct the rest of the event related information fields and cause the VM-exit. */
3719 uint64_t u64ExitQual;
3720 if (uVector == X86_XCPT_PF)
3721 {
3722 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3723 u64ExitQual = uCr2;
3724 }
3725 else if (uVector == X86_XCPT_DB)
3726 {
3727 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3728 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3729 }
3730 else
3731 u64ExitQual = 0;
3732
3733 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3734 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3735 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3736 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3737 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3738 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3739 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3740 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3741 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3742 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3743
3744 /*
3745 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3746 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3747 * length.
3748 */
3749 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3750 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3751 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3752 else
3753 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3754
3755 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3756 }
3757
3758 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3759}
3760
3761
3762/**
3763 * VMX VM-exit handler for VM-exits due to a triple fault.
3764 *
3765 * @returns VBox strict status code.
3766 * @param pVCpu The cross context virtual CPU structure.
3767 */
3768IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3769{
3770 /*
3771 * A VM-exit is not considered to occur during event delivery when the original
3772 * event results in a triple-fault.
3773 *
3774 * Therefore, we must clear the original event from the IDT-vectoring fields which
3775 * would've been recorded before causing the VM-exit.
3776 *
3777 * 27.2.3 "Information for VM Exits During Event Delivery"
3778 */
3779 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3780 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3781
3782 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
3783}
3784
3785
3786/**
3787 * VMX VM-exit handler for APIC accesses.
3788 *
3789 * @param pVCpu The cross context virtual CPU structure.
3790 * @param offAccess The offset of the register being accessed.
3791 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3792 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3793 */
3794IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
3795{
3796 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3797
3798 VMXAPICACCESS enmAccess;
3799 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3800 if (fInEventDelivery)
3801 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3802 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3803 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3804 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3805 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3806 else
3807 enmAccess = VMXAPICACCESS_LINEAR_READ;
3808
3809 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3810 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3811 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3812}
3813
3814
3815/**
3816 * VMX VM-exit handler for APIC accesses.
3817 *
3818 * This is intended for APIC accesses where the caller provides all the
3819 * relevant VM-exit information.
3820 *
3821 * @returns VBox strict status code.
3822 * @param pVCpu The cross context virtual CPU structure.
3823 * @param pExitInfo Pointer to the VM-exit information.
3824 * @param pExitEventInfo Pointer to the VM-exit event information.
3825 */
3826IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3827 PCVMXVEXITEVENTINFO pExitEventInfo)
3828{
3829 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3830 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3831 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3832 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3833 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3834 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3835 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3836}
3837
3838
3839/**
3840 * VMX VM-exit handler for APIC-write VM-exits.
3841 *
3842 * @param pVCpu The cross context virtual CPU structure.
3843 * @param offApic The write to the virtual-APIC page offset that caused this
3844 * VM-exit.
3845 */
3846IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
3847{
3848 Assert(offApic < XAPIC_OFF_END + 4);
3849 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3850 offApic &= UINT16_C(0xfff);
3851 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3852}
3853
3854
3855/**
3856 * Sets virtual-APIC write emulation as pending.
3857 *
3858 * @param pVCpu The cross context virtual CPU structure.
3859 * @param offApic The offset in the virtual-APIC page that was written.
3860 */
3861DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
3862{
3863 Assert(offApic < XAPIC_OFF_END + 4);
3864
3865 /*
3866 * Record the currently updated APIC offset, as we need this later for figuring
3867 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3868 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3869 */
3870 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3871
3872 /*
3873 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3874 * virtualization or APIC-write emulation).
3875 */
3876 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3877 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3878}
3879
3880
3881/**
3882 * Clears any pending virtual-APIC write emulation.
3883 *
3884 * @returns The virtual-APIC offset that was written before clearing it.
3885 * @param pVCpu The cross context virtual CPU structure.
3886 */
3887DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
3888{
3889 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3890 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3891 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3892 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3893 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3894 return offVirtApicWrite;
3895}
3896
3897
3898/**
3899 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3900 *
3901 * @returns The register from the virtual-APIC page.
3902 * @param pVCpu The cross context virtual CPU structure.
3903 * @param offReg The offset of the register being read.
3904 */
3905IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
3906{
3907 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3908 Assert(pVmcs);
3909
3910 uint32_t uReg;
3911 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3912 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3913 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3914 if (RT_FAILURE(rc))
3915 {
3916 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3917 GCPhysVirtApic));
3918 uReg = 0;
3919 }
3920 return uReg;
3921}
3922
3923
3924/**
3925 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3926 *
3927 * @returns The register from the virtual-APIC page.
3928 * @param pVCpu The cross context virtual CPU structure.
3929 * @param offReg The offset of the register being read.
3930 */
3931IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
3932{
3933 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3934 Assert(pVmcs);
3935
3936 uint64_t uReg;
3937 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3938 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3939 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3940 if (RT_FAILURE(rc))
3941 {
3942 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3943 GCPhysVirtApic));
3944 uReg = 0;
3945 }
3946 return uReg;
3947}
3948
3949
3950/**
3951 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3952 *
3953 * @param pVCpu The cross context virtual CPU structure.
3954 * @param offReg The offset of the register being written.
3955 * @param uReg The register value to write.
3956 */
3957IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
3958{
3959 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3960 Assert(pVmcs);
3961 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3962 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3963 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3964 if (RT_FAILURE(rc))
3965 {
3966 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3967 GCPhysVirtApic));
3968 }
3969}
3970
3971
3972/**
3973 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3974 *
3975 * @param pVCpu The cross context virtual CPU structure.
3976 * @param offReg The offset of the register being written.
3977 * @param uReg The register value to write.
3978 */
3979IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
3980{
3981 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3982 Assert(pVmcs);
3983 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uReg));
3984 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3985 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3986 if (RT_FAILURE(rc))
3987 {
3988 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3989 GCPhysVirtApic));
3990 }
3991}
3992
3993
3994/**
3995 * Sets the vector in a virtual-APIC 256-bit sparse register.
3996 *
3997 * @param pVCpu The cross context virtual CPU structure.
3998 * @param offReg The offset of the 256-bit spare register.
3999 * @param uVector The vector to set.
4000 *
4001 * @remarks This is based on our APIC device code.
4002 */
4003IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4004{
4005 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4006 Assert(pVmcs);
4007 uint32_t uReg;
4008 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4009 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4010 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4011 if (RT_SUCCESS(rc))
4012 {
4013 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4014 uReg |= RT_BIT(idxVectorBit);
4015 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4016 if (RT_FAILURE(rc))
4017 {
4018 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4019 uVector, offReg, GCPhysVirtApic));
4020 }
4021 }
4022 else
4023 {
4024 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4025 uVector, offReg, GCPhysVirtApic));
4026 }
4027}
4028
4029
4030/**
4031 * Clears the vector in a virtual-APIC 256-bit sparse register.
4032 *
4033 * @param pVCpu The cross context virtual CPU structure.
4034 * @param offReg The offset of the 256-bit spare register.
4035 * @param uVector The vector to clear.
4036 *
4037 * @remarks This is based on our APIC device code.
4038 */
4039IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4040{
4041 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4042 Assert(pVmcs);
4043 uint32_t uReg;
4044 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4045 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4046 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4047 if (RT_SUCCESS(rc))
4048 {
4049 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4050 uReg &= ~RT_BIT(idxVectorBit);
4051 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4052 if (RT_FAILURE(rc))
4053 {
4054 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4055 uVector, offReg, GCPhysVirtApic));
4056 }
4057 }
4058 else
4059 {
4060 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4061 uVector, offReg, GCPhysVirtApic));
4062 }
4063}
4064
4065
4066/**
4067 * Checks if a memory access to the APIC-access page must causes an APIC-access
4068 * VM-exit.
4069 *
4070 * @param pVCpu The cross context virtual CPU structure.
4071 * @param offAccess The offset of the register being accessed.
4072 * @param cbAccess The size of the access in bytes.
4073 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4074 * IEM_ACCESS_TYPE_WRITE).
4075 *
4076 * @remarks This must not be used for MSR-based APIC-access page accesses!
4077 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4078 */
4079IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4080{
4081 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4082 Assert(pVmcs);
4083 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4084
4085 /*
4086 * We must cause a VM-exit if any of the following are true:
4087 * - TPR shadowing isn't active.
4088 * - The access size exceeds 32-bits.
4089 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4090 *
4091 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4092 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4093 */
4094 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4095 || cbAccess > sizeof(uint32_t)
4096 || ((offAccess + cbAccess - 1) & 0xc)
4097 || offAccess >= XAPIC_OFF_END + 4)
4098 return true;
4099
4100 /*
4101 * If the access is part of an operation where we have already
4102 * virtualized a virtual-APIC write, we must cause a VM-exit.
4103 */
4104 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4105 return true;
4106
4107 /*
4108 * Check write accesses to the APIC-access page that cause VM-exits.
4109 */
4110 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4111 {
4112 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4113 {
4114 /*
4115 * With APIC-register virtualization, a write access to any of the
4116 * following registers are virtualized. Accessing any other register
4117 * causes a VM-exit.
4118 */
4119 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4120 switch (offAlignedAccess)
4121 {
4122 case XAPIC_OFF_ID:
4123 case XAPIC_OFF_TPR:
4124 case XAPIC_OFF_EOI:
4125 case XAPIC_OFF_LDR:
4126 case XAPIC_OFF_DFR:
4127 case XAPIC_OFF_SVR:
4128 case XAPIC_OFF_ESR:
4129 case XAPIC_OFF_ICR_LO:
4130 case XAPIC_OFF_ICR_HI:
4131 case XAPIC_OFF_LVT_TIMER:
4132 case XAPIC_OFF_LVT_THERMAL:
4133 case XAPIC_OFF_LVT_PERF:
4134 case XAPIC_OFF_LVT_LINT0:
4135 case XAPIC_OFF_LVT_LINT1:
4136 case XAPIC_OFF_LVT_ERROR:
4137 case XAPIC_OFF_TIMER_ICR:
4138 case XAPIC_OFF_TIMER_DCR:
4139 break;
4140 default:
4141 return true;
4142 }
4143 }
4144 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4145 {
4146 /*
4147 * With virtual-interrupt delivery, a write access to any of the
4148 * following registers are virtualized. Accessing any other register
4149 * causes a VM-exit.
4150 *
4151 * Note! The specification does not allow writing to offsets in-between
4152 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4153 */
4154 switch (offAccess)
4155 {
4156 case XAPIC_OFF_TPR:
4157 case XAPIC_OFF_EOI:
4158 case XAPIC_OFF_ICR_LO:
4159 break;
4160 default:
4161 return true;
4162 }
4163 }
4164 else
4165 {
4166 /*
4167 * Without APIC-register virtualization or virtual-interrupt delivery,
4168 * only TPR accesses are virtualized.
4169 */
4170 if (offAccess == XAPIC_OFF_TPR)
4171 { /* likely */ }
4172 else
4173 return true;
4174 }
4175 }
4176 else
4177 {
4178 /*
4179 * Check read accesses to the APIC-access page that cause VM-exits.
4180 */
4181 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4182 {
4183 /*
4184 * With APIC-register virtualization, a read access to any of the
4185 * following registers are virtualized. Accessing any other register
4186 * causes a VM-exit.
4187 */
4188 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4189 switch (offAlignedAccess)
4190 {
4191 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4192 case XAPIC_OFF_ID:
4193 case XAPIC_OFF_VERSION:
4194 case XAPIC_OFF_TPR:
4195 case XAPIC_OFF_EOI:
4196 case XAPIC_OFF_LDR:
4197 case XAPIC_OFF_DFR:
4198 case XAPIC_OFF_SVR:
4199 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4200 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4201 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4202 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4203 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4204 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4205 case XAPIC_OFF_ESR:
4206 case XAPIC_OFF_ICR_LO:
4207 case XAPIC_OFF_ICR_HI:
4208 case XAPIC_OFF_LVT_TIMER:
4209 case XAPIC_OFF_LVT_THERMAL:
4210 case XAPIC_OFF_LVT_PERF:
4211 case XAPIC_OFF_LVT_LINT0:
4212 case XAPIC_OFF_LVT_LINT1:
4213 case XAPIC_OFF_LVT_ERROR:
4214 case XAPIC_OFF_TIMER_ICR:
4215 case XAPIC_OFF_TIMER_DCR:
4216 break;
4217 default:
4218 return true;
4219 }
4220 }
4221 else
4222 {
4223 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4224 if (offAccess == XAPIC_OFF_TPR)
4225 { /* likely */ }
4226 else
4227 return true;
4228 }
4229 }
4230
4231 /* The APIC access is virtualized, does not cause a VM-exit. */
4232 return false;
4233}
4234
4235
4236/**
4237 * Virtualizes a memory-based APIC access where the address is not used to access
4238 * memory.
4239 *
4240 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4241 * page-faults but do not use the address to access memory.
4242 *
4243 * @param pVCpu The cross context virtual CPU structure.
4244 * @param pGCPhysAccess Pointer to the guest-physical address used.
4245 */
4246IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4247{
4248 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4249 Assert(pVmcs);
4250 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4251 Assert(pGCPhysAccess);
4252
4253 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4254 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4255 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4256
4257 if (GCPhysAccess == GCPhysApic)
4258 {
4259 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4260 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4261 uint16_t const cbAccess = 1;
4262 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4263 if (fIntercept)
4264 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4265
4266 *pGCPhysAccess = GCPhysApic | offAccess;
4267 return VINF_VMX_MODIFIES_BEHAVIOR;
4268 }
4269
4270 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4271}
4272
4273
4274/**
4275 * Virtualizes a memory-based APIC access.
4276 *
4277 * @returns VBox strict status code.
4278 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4279 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4280 *
4281 * @param pVCpu The cross context virtual CPU structure.
4282 * @param offAccess The offset of the register being accessed (within the
4283 * APIC-access page).
4284 * @param cbAccess The size of the access in bytes.
4285 * @param pvData Pointer to the data being written or where to store the data
4286 * being read.
4287 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4288 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4289 */
4290IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4291 uint32_t fAccess)
4292{
4293 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4294 Assert(pVmcs);
4295 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4296 Assert(pvData);
4297 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4298 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4299 || (fAccess & IEM_ACCESS_INSTRUCTION));
4300
4301 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4302 if (fIntercept)
4303 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4304
4305 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4306 {
4307 /*
4308 * A write access to the APIC-access page that is virtualized (rather than
4309 * causing a VM-exit) writes data to the virtual-APIC page.
4310 */
4311 uint32_t const u32Data = *(uint32_t *)pvData;
4312 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4313
4314 /*
4315 * Record the currently updated APIC offset, as we need this later for figuring
4316 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4317 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4318 *
4319 * After completion of the current operation, we need to perform TPR virtualization,
4320 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4321 *
4322 * The current operation may be a REP-prefixed string instruction, execution of any
4323 * other instruction, or delivery of an event through the IDT.
4324 *
4325 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4326 * performed now but later after completion of the current operation.
4327 *
4328 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4329 */
4330 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4331 }
4332 else
4333 {
4334 /*
4335 * A read access from the APIC-access page that is virtualized (rather than
4336 * causing a VM-exit) returns data from the virtual-APIC page.
4337 *
4338 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4339 */
4340 Assert(cbAccess <= 4);
4341 Assert(offAccess < XAPIC_OFF_END + 4);
4342 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4343
4344 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4345 u32Data &= s_auAccessSizeMasks[cbAccess];
4346 *(uint32_t *)pvData = u32Data;
4347 }
4348
4349 return VINF_VMX_MODIFIES_BEHAVIOR;
4350}
4351
4352
4353/**
4354 * Virtualizes an MSR-based APIC read access.
4355 *
4356 * @returns VBox strict status code.
4357 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4358 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4359 * handled by the x2APIC device.
4360 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4361 * not within the range of valid MSRs, caller must raise \#GP(0).
4362 * @param pVCpu The cross context virtual CPU structure.
4363 * @param idMsr The x2APIC MSR being read.
4364 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4365 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4366 */
4367IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4368{
4369 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4370 Assert(pVmcs);
4371 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4372 Assert(pu64Value);
4373
4374 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4375 {
4376 /*
4377 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4378 * what the end of the valid x2APIC MSR range is. Hence the use of different
4379 * macros here.
4380 *
4381 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4382 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4383 */
4384 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4385 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4386 {
4387 uint16_t const offReg = (idMsr & 0xff) << 4;
4388 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4389 *pu64Value = u64Value;
4390 return VINF_VMX_MODIFIES_BEHAVIOR;
4391 }
4392 return VERR_OUT_OF_RANGE;
4393 }
4394
4395 if (idMsr == MSR_IA32_X2APIC_TPR)
4396 {
4397 uint16_t const offReg = (idMsr & 0xff) << 4;
4398 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4399 *pu64Value = u64Value;
4400 return VINF_VMX_MODIFIES_BEHAVIOR;
4401 }
4402
4403 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4404}
4405
4406
4407/**
4408 * Virtualizes an MSR-based APIC write access.
4409 *
4410 * @returns VBox strict status code.
4411 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4412 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4413 * not within the range of valid MSRs, caller must raise \#GP(0).
4414 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4415 *
4416 * @param pVCpu The cross context virtual CPU structure.
4417 * @param idMsr The x2APIC MSR being written.
4418 * @param u64Value The value of the x2APIC MSR being written.
4419 */
4420IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4421{
4422 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4423 Assert(pVmcs);
4424
4425 /*
4426 * Check if the access is to be virtualized.
4427 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4428 */
4429 if ( idMsr == MSR_IA32_X2APIC_TPR
4430 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4431 && ( idMsr == MSR_IA32_X2APIC_EOI
4432 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4433 {
4434 /* Validate the MSR write depending on the register. */
4435 switch (idMsr)
4436 {
4437 case MSR_IA32_X2APIC_TPR:
4438 case MSR_IA32_X2APIC_SELF_IPI:
4439 {
4440 if (u64Value & UINT64_C(0xffffffffffffff00))
4441 return VERR_OUT_OF_RANGE;
4442 break;
4443 }
4444 case MSR_IA32_X2APIC_EOI:
4445 {
4446 if (u64Value != 0)
4447 return VERR_OUT_OF_RANGE;
4448 break;
4449 }
4450 }
4451
4452 /* Write the MSR to the virtual-APIC page. */
4453 uint16_t const offReg = (idMsr & 0xff) << 4;
4454 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4455
4456 /*
4457 * Record the currently updated APIC offset, as we need this later for figuring
4458 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4459 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4460 */
4461 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4462
4463 return VINF_VMX_MODIFIES_BEHAVIOR;
4464 }
4465
4466 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4467}
4468
4469
4470/**
4471 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4472 *
4473 * @returns VBox status code.
4474 * @retval VINF_SUCCESS when the highest set bit is found.
4475 * @retval VERR_NOT_FOUND when no bit is set.
4476 *
4477 * @param pVCpu The cross context virtual CPU structure.
4478 * @param offReg The offset of the APIC 256-bit sparse register.
4479 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4480 * set in the register. Only valid when VINF_SUCCESS is
4481 * returned.
4482 *
4483 * @remarks The format of the 256-bit sparse register here mirrors that found in
4484 * real APIC hardware.
4485 */
4486static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4487{
4488 Assert(offReg < XAPIC_OFF_END + 4);
4489 Assert(pidxHighestBit);
4490 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4491
4492 /*
4493 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4494 * However, in each fragment only the first 4 bytes are used.
4495 */
4496 uint8_t const cFrags = 8;
4497 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4498 {
4499 uint16_t const offFrag = iFrag * 16;
4500 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4501 if (!u32Frag)
4502 continue;
4503
4504 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4505 Assert(idxHighestBit > 0);
4506 --idxHighestBit;
4507 Assert(idxHighestBit <= UINT8_MAX);
4508 *pidxHighestBit = idxHighestBit;
4509 return VINF_SUCCESS;
4510 }
4511 return VERR_NOT_FOUND;
4512}
4513
4514
4515/**
4516 * Evaluates pending virtual interrupts.
4517 *
4518 * @param pVCpu The cross context virtual CPU structure.
4519 */
4520IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4521{
4522 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4523 Assert(pVmcs);
4524 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4525
4526 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4527 {
4528 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4529 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4530
4531 if ((uRvi >> 4) > (uPpr >> 4))
4532 {
4533 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4534 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4535 }
4536 else
4537 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4538 }
4539}
4540
4541
4542/**
4543 * Performs PPR virtualization.
4544 *
4545 * @returns VBox strict status code.
4546 * @param pVCpu The cross context virtual CPU structure.
4547 */
4548IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4549{
4550 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4551 Assert(pVmcs);
4552 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4553 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4554
4555 /*
4556 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4557 * or EOI-virtualization.
4558 *
4559 * See Intel spec. 29.1.3 "PPR Virtualization".
4560 */
4561 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4562 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4563
4564 uint32_t uPpr;
4565 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4566 uPpr = uTpr & 0xff;
4567 else
4568 uPpr = uSvi & 0xf0;
4569
4570 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4571 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4572}
4573
4574
4575/**
4576 * Performs VMX TPR virtualization.
4577 *
4578 * @returns VBox strict status code.
4579 * @param pVCpu The cross context virtual CPU structure.
4580 */
4581IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4582{
4583 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4584 Assert(pVmcs);
4585 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4586
4587 /*
4588 * We should have already performed the virtual-APIC write to the TPR offset
4589 * in the virtual-APIC page. We now perform TPR virtualization.
4590 *
4591 * See Intel spec. 29.1.2 "TPR Virtualization".
4592 */
4593 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4594 {
4595 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4596 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4597
4598 /*
4599 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4600 * See Intel spec. 29.1.2 "TPR Virtualization".
4601 */
4602 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4603 {
4604 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4605 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4606 }
4607 }
4608 else
4609 {
4610 iemVmxPprVirtualization(pVCpu);
4611 iemVmxEvalPendingVirtIntrs(pVCpu);
4612 }
4613
4614 return VINF_SUCCESS;
4615}
4616
4617
4618/**
4619 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4620 * not.
4621 *
4622 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4623 * @param pVCpu The cross context virtual CPU structure.
4624 * @param uVector The interrupt that was acknowledged using an EOI.
4625 */
4626IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4627{
4628 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4629 Assert(pVmcs);
4630 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4631
4632 if (uVector < 64)
4633 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4634 if (uVector < 128)
4635 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4636 if (uVector < 192)
4637 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4638 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4639}
4640
4641
4642/**
4643 * Performs EOI virtualization.
4644 *
4645 * @returns VBox strict status code.
4646 * @param pVCpu The cross context virtual CPU structure.
4647 */
4648IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4649{
4650 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4651 Assert(pVmcs);
4652 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4653
4654 /*
4655 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4656 * and get the next guest-interrupt that's in-service (if any).
4657 *
4658 * See Intel spec. 29.1.4 "EOI Virtualization".
4659 */
4660 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4661 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4662 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4663
4664 uint8_t uVector = uSvi;
4665 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4666
4667 uVector = 0;
4668 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4669
4670 if (uVector)
4671 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4672 else
4673 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4674
4675 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4676 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4677
4678 iemVmxPprVirtualization(pVCpu);
4679 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4680 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4681 iemVmxEvalPendingVirtIntrs(pVCpu);
4682 return VINF_SUCCESS;
4683}
4684
4685
4686/**
4687 * Performs self-IPI virtualization.
4688 *
4689 * @returns VBox strict status code.
4690 * @param pVCpu The cross context virtual CPU structure.
4691 */
4692IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4693{
4694 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4695 Assert(pVmcs);
4696 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4697
4698 /*
4699 * We should have already performed the virtual-APIC write to the self-IPI offset
4700 * in the virtual-APIC page. We now perform self-IPI virtualization.
4701 *
4702 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4703 */
4704 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4705 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4706 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4707 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4708 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4709 if (uVector > uRvi)
4710 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4711 iemVmxEvalPendingVirtIntrs(pVCpu);
4712 return VINF_SUCCESS;
4713}
4714
4715
4716/**
4717 * Performs VMX APIC-write emulation.
4718 *
4719 * @returns VBox strict status code.
4720 * @param pVCpu The cross context virtual CPU structure.
4721 */
4722IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4723{
4724 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4725 Assert(pVmcs);
4726
4727 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4728 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4729
4730 /*
4731 * Perform APIC-write emulation based on the virtual-APIC register written.
4732 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4733 */
4734 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4735 VBOXSTRICTRC rcStrict;
4736 switch (offApicWrite)
4737 {
4738 case XAPIC_OFF_TPR:
4739 {
4740 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4741 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4742 uTpr &= UINT32_C(0x000000ff);
4743 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4744 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4745 rcStrict = iemVmxTprVirtualization(pVCpu);
4746 break;
4747 }
4748
4749 case XAPIC_OFF_EOI:
4750 {
4751 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4752 {
4753 /* Clear VEOI and perform EOI virtualization. */
4754 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4755 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4756 rcStrict = iemVmxEoiVirtualization(pVCpu);
4757 }
4758 else
4759 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4760 break;
4761 }
4762
4763 case XAPIC_OFF_ICR_LO:
4764 {
4765 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4766 {
4767 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4768 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4769 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4770 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4771 if ( !(uIcrLo & fIcrLoMb0)
4772 && (uIcrLo & fIcrLoMb1))
4773 {
4774 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4775 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4776 }
4777 else
4778 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4779 }
4780 else
4781 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4782 break;
4783 }
4784
4785 case XAPIC_OFF_ICR_HI:
4786 {
4787 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4788 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4789 uIcrHi &= UINT32_C(0xff000000);
4790 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4791 rcStrict = VINF_SUCCESS;
4792 break;
4793 }
4794
4795 default:
4796 {
4797 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4798 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4799 break;
4800 }
4801 }
4802
4803 return rcStrict;
4804}
4805
4806
4807/**
4808 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4809 *
4810 * @param pVCpu The cross context virtual CPU structure.
4811 * @param pszInstr The VMX instruction name (for logging purposes).
4812 */
4813IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
4814{
4815 /*
4816 * Guest Control Registers, Debug Registers, and MSRs.
4817 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4818 */
4819 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4820 const char *const pszFailure = "VM-exit";
4821 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4822
4823 /* CR0 reserved bits. */
4824 {
4825 /* CR0 MB1 bits. */
4826 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4827 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4828 if (fUnrestrictedGuest)
4829 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4830 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4831 { /* likely */ }
4832 else
4833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4834
4835 /* CR0 MBZ bits. */
4836 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4837 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4838 { /* likely */ }
4839 else
4840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4841
4842 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4843 if ( !fUnrestrictedGuest
4844 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4845 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4846 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4847 }
4848
4849 /* CR4 reserved bits. */
4850 {
4851 /* CR4 MB1 bits. */
4852 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4853 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4854 { /* likely */ }
4855 else
4856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4857
4858 /* CR4 MBZ bits. */
4859 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4860 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4861 { /* likely */ }
4862 else
4863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4864 }
4865
4866 /* DEBUGCTL MSR. */
4867 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4868 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4869 { /* likely */ }
4870 else
4871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4872
4873 /* 64-bit CPU checks. */
4874 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4875 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4876 {
4877 if (fGstInLongMode)
4878 {
4879 /* PAE must be set. */
4880 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4881 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4882 { /* likely */ }
4883 else
4884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4885 }
4886 else
4887 {
4888 /* PCIDE should not be set. */
4889 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4890 { /* likely */ }
4891 else
4892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4893 }
4894
4895 /* CR3. */
4896 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4897 { /* likely */ }
4898 else
4899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4900
4901 /* DR7. */
4902 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4903 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4904 { /* likely */ }
4905 else
4906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4907
4908 /* SYSENTER ESP and SYSENTER EIP. */
4909 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4910 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4911 { /* likely */ }
4912 else
4913 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4914 }
4915
4916 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4917 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4918
4919 /* PAT MSR. */
4920 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4921 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4922 { /* likely */ }
4923 else
4924 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4925
4926 /* EFER MSR. */
4927 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4928 {
4929 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4930 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4931 { /* likely */ }
4932 else
4933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4934
4935 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4936 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4937 if ( fGstLma == fGstInLongMode
4938 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4939 || fGstLma == fGstLme))
4940 { /* likely */ }
4941 else
4942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4943 }
4944
4945 /* We don't support IA32_BNDCFGS MSR yet. */
4946 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4947
4948 NOREF(pszInstr);
4949 NOREF(pszFailure);
4950 return VINF_SUCCESS;
4951}
4952
4953
4954/**
4955 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4956 *
4957 * @param pVCpu The cross context virtual CPU structure.
4958 * @param pszInstr The VMX instruction name (for logging purposes).
4959 */
4960IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4961{
4962 /*
4963 * Segment registers.
4964 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4965 */
4966 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4967 const char *const pszFailure = "VM-exit";
4968 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4969 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4970 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4971
4972 /* Selectors. */
4973 if ( !fGstInV86Mode
4974 && !fUnrestrictedGuest
4975 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4977
4978 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4979 {
4980 CPUMSELREG SelReg;
4981 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4982 if (RT_LIKELY(rc == VINF_SUCCESS))
4983 { /* likely */ }
4984 else
4985 return rc;
4986
4987 /*
4988 * Virtual-8086 mode checks.
4989 */
4990 if (fGstInV86Mode)
4991 {
4992 /* Base address. */
4993 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4994 { /* likely */ }
4995 else
4996 {
4997 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4998 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4999 }
5000
5001 /* Limit. */
5002 if (SelReg.u32Limit == 0xffff)
5003 { /* likely */ }
5004 else
5005 {
5006 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5008 }
5009
5010 /* Attribute. */
5011 if (SelReg.Attr.u == 0xf3)
5012 { /* likely */ }
5013 else
5014 {
5015 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5017 }
5018
5019 /* We're done; move to checking the next segment. */
5020 continue;
5021 }
5022
5023 /* Checks done by 64-bit CPUs. */
5024 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5025 {
5026 /* Base address. */
5027 if ( iSegReg == X86_SREG_FS
5028 || iSegReg == X86_SREG_GS)
5029 {
5030 if (X86_IS_CANONICAL(SelReg.u64Base))
5031 { /* likely */ }
5032 else
5033 {
5034 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5036 }
5037 }
5038 else if (iSegReg == X86_SREG_CS)
5039 {
5040 if (!RT_HI_U32(SelReg.u64Base))
5041 { /* likely */ }
5042 else
5043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5044 }
5045 else
5046 {
5047 if ( SelReg.Attr.n.u1Unusable
5048 || !RT_HI_U32(SelReg.u64Base))
5049 { /* likely */ }
5050 else
5051 {
5052 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5054 }
5055 }
5056 }
5057
5058 /*
5059 * Checks outside Virtual-8086 mode.
5060 */
5061 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5062 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5063 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5064 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5065 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5066 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5067 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5068 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5069
5070 /* Code or usable segment. */
5071 if ( iSegReg == X86_SREG_CS
5072 || fUsable)
5073 {
5074 /* Reserved bits (bits 31:17 and bits 11:8). */
5075 if (!(SelReg.Attr.u & 0xfffe0f00))
5076 { /* likely */ }
5077 else
5078 {
5079 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5081 }
5082
5083 /* Descriptor type. */
5084 if (fCodeDataSeg)
5085 { /* likely */ }
5086 else
5087 {
5088 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5090 }
5091
5092 /* Present. */
5093 if (fPresent)
5094 { /* likely */ }
5095 else
5096 {
5097 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5099 }
5100
5101 /* Granularity. */
5102 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5103 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5104 { /* likely */ }
5105 else
5106 {
5107 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5109 }
5110 }
5111
5112 if (iSegReg == X86_SREG_CS)
5113 {
5114 /* Segment Type and DPL. */
5115 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5116 && fUnrestrictedGuest)
5117 {
5118 if (uDpl == 0)
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5122 }
5123 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5124 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5125 {
5126 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5127 if (uDpl == AttrSs.n.u2Dpl)
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5131 }
5132 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5133 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5134 {
5135 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5136 if (uDpl <= AttrSs.n.u2Dpl)
5137 { /* likely */ }
5138 else
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5140 }
5141 else
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5143
5144 /* Def/Big. */
5145 if ( fGstInLongMode
5146 && fSegLong)
5147 {
5148 if (uDefBig == 0)
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5152 }
5153 }
5154 else if (iSegReg == X86_SREG_SS)
5155 {
5156 /* Segment Type. */
5157 if ( !fUsable
5158 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5159 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5160 { /* likely */ }
5161 else
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5163
5164 /* DPL. */
5165 if (!fUnrestrictedGuest)
5166 {
5167 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5171 }
5172 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5173 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5174 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5175 {
5176 if (uDpl == 0)
5177 { /* likely */ }
5178 else
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5180 }
5181 }
5182 else
5183 {
5184 /* DS, ES, FS, GS. */
5185 if (fUsable)
5186 {
5187 /* Segment type. */
5188 if (uSegType & X86_SEL_TYPE_ACCESSED)
5189 { /* likely */ }
5190 else
5191 {
5192 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5194 }
5195
5196 if ( !(uSegType & X86_SEL_TYPE_CODE)
5197 || (uSegType & X86_SEL_TYPE_READ))
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5201
5202 /* DPL. */
5203 if ( !fUnrestrictedGuest
5204 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5205 {
5206 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5207 { /* likely */ }
5208 else
5209 {
5210 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5212 }
5213 }
5214 }
5215 }
5216 }
5217
5218 /*
5219 * LDTR.
5220 */
5221 {
5222 CPUMSELREG Ldtr;
5223 Ldtr.Sel = pVmcs->GuestLdtr;
5224 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5225 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5226 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5227
5228 if (!Ldtr.Attr.n.u1Unusable)
5229 {
5230 /* Selector. */
5231 if (!(Ldtr.Sel & X86_SEL_LDT))
5232 { /* likely */ }
5233 else
5234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5235
5236 /* Base. */
5237 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5238 {
5239 if (X86_IS_CANONICAL(Ldtr.u64Base))
5240 { /* likely */ }
5241 else
5242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5243 }
5244
5245 /* Attributes. */
5246 /* Reserved bits (bits 31:17 and bits 11:8). */
5247 if (!(Ldtr.Attr.u & 0xfffe0f00))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5251
5252 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5256
5257 if (!Ldtr.Attr.n.u1DescType)
5258 { /* likely */ }
5259 else
5260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5261
5262 if (Ldtr.Attr.n.u1Present)
5263 { /* likely */ }
5264 else
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5266
5267 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5268 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5269 { /* likely */ }
5270 else
5271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5272 }
5273 }
5274
5275 /*
5276 * TR.
5277 */
5278 {
5279 CPUMSELREG Tr;
5280 Tr.Sel = pVmcs->GuestTr;
5281 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5282 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5283 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5284
5285 /* Selector. */
5286 if (!(Tr.Sel & X86_SEL_LDT))
5287 { /* likely */ }
5288 else
5289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5290
5291 /* Base. */
5292 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5293 {
5294 if (X86_IS_CANONICAL(Tr.u64Base))
5295 { /* likely */ }
5296 else
5297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5298 }
5299
5300 /* Attributes. */
5301 /* Reserved bits (bits 31:17 and bits 11:8). */
5302 if (!(Tr.Attr.u & 0xfffe0f00))
5303 { /* likely */ }
5304 else
5305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5306
5307 if (!Tr.Attr.n.u1Unusable)
5308 { /* likely */ }
5309 else
5310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5311
5312 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5313 || ( !fGstInLongMode
5314 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5315 { /* likely */ }
5316 else
5317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5318
5319 if (!Tr.Attr.n.u1DescType)
5320 { /* likely */ }
5321 else
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5323
5324 if (Tr.Attr.n.u1Present)
5325 { /* likely */ }
5326 else
5327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5328
5329 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5330 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5331 { /* likely */ }
5332 else
5333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5334 }
5335
5336 NOREF(pszInstr);
5337 NOREF(pszFailure);
5338 return VINF_SUCCESS;
5339}
5340
5341
5342/**
5343 * Checks guest GDTR and IDTR as part of VM-entry.
5344 *
5345 * @param pVCpu The cross context virtual CPU structure.
5346 * @param pszInstr The VMX instruction name (for logging purposes).
5347 */
5348IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5349{
5350 /*
5351 * GDTR and IDTR.
5352 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5353 */
5354 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5355 const char *const pszFailure = "VM-exit";
5356
5357 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5358 {
5359 /* Base. */
5360 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5361 { /* likely */ }
5362 else
5363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5364
5365 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5366 { /* likely */ }
5367 else
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5369 }
5370
5371 /* Limit. */
5372 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5373 { /* likely */ }
5374 else
5375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5376
5377 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5378 { /* likely */ }
5379 else
5380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5381
5382 NOREF(pszInstr);
5383 NOREF(pszFailure);
5384 return VINF_SUCCESS;
5385}
5386
5387
5388/**
5389 * Checks guest RIP and RFLAGS as part of VM-entry.
5390 *
5391 * @param pVCpu The cross context virtual CPU structure.
5392 * @param pszInstr The VMX instruction name (for logging purposes).
5393 */
5394IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5395{
5396 /*
5397 * RIP and RFLAGS.
5398 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5399 */
5400 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5401 const char *const pszFailure = "VM-exit";
5402 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5403
5404 /* RIP. */
5405 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5406 {
5407 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5408 if ( !fGstInLongMode
5409 || !AttrCs.n.u1Long)
5410 {
5411 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5412 { /* likely */ }
5413 else
5414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5415 }
5416
5417 if ( fGstInLongMode
5418 && AttrCs.n.u1Long)
5419 {
5420 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5421 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5422 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5423 { /* likely */ }
5424 else
5425 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5426 }
5427 }
5428
5429 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5430 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5431 : pVmcs->u64GuestRFlags.s.Lo;
5432 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5433 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5434 { /* likely */ }
5435 else
5436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5437
5438 if ( fGstInLongMode
5439 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5440 {
5441 if (!(uGuestRFlags & X86_EFL_VM))
5442 { /* likely */ }
5443 else
5444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5445 }
5446
5447 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5448 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5449 {
5450 if (uGuestRFlags & X86_EFL_IF)
5451 { /* likely */ }
5452 else
5453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5454 }
5455
5456 NOREF(pszInstr);
5457 NOREF(pszFailure);
5458 return VINF_SUCCESS;
5459}
5460
5461
5462/**
5463 * Checks guest non-register state as part of VM-entry.
5464 *
5465 * @param pVCpu The cross context virtual CPU structure.
5466 * @param pszInstr The VMX instruction name (for logging purposes).
5467 */
5468IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5469{
5470 /*
5471 * Guest non-register state.
5472 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5473 */
5474 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5475 const char *const pszFailure = "VM-exit";
5476
5477 /*
5478 * Activity state.
5479 */
5480 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5481 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5482 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5486
5487 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5488 if ( !AttrSs.n.u2Dpl
5489 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5490 { /* likely */ }
5491 else
5492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5493
5494 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5495 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5496 {
5497 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5498 { /* likely */ }
5499 else
5500 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5501 }
5502
5503 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5504 {
5505 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5506 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5507 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5508 switch (pVmcs->u32GuestActivityState)
5509 {
5510 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5511 {
5512 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5513 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5514 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5515 && ( uVector == X86_XCPT_DB
5516 || uVector == X86_XCPT_MC))
5517 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5518 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5519 { /* likely */ }
5520 else
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5522 break;
5523 }
5524
5525 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5526 {
5527 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5528 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5529 && uVector == X86_XCPT_MC))
5530 { /* likely */ }
5531 else
5532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5533 break;
5534 }
5535
5536 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5537 default:
5538 break;
5539 }
5540 }
5541
5542 /*
5543 * Interruptibility state.
5544 */
5545 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5549
5550 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5551 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5552 { /* likely */ }
5553 else
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5555
5556 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5557 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5558 { /* likely */ }
5559 else
5560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5561
5562 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5563 {
5564 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5565 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5566 {
5567 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5568 { /* likely */ }
5569 else
5570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5571 }
5572 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5573 {
5574 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5575 { /* likely */ }
5576 else
5577 {
5578 /*
5579 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5580 * We update the Exit qualification only when blocking-by-STI is set
5581 * without blocking-by-MovSS being set. Although in practise it does not
5582 * make much difference since the order of checks are implementation defined.
5583 */
5584 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5585 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5587 }
5588
5589 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5590 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5594 }
5595 }
5596
5597 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5598 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5599 { /* likely */ }
5600 else
5601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5602
5603 /* We don't support SGX yet. So enclave-interruption must not be set. */
5604 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5605 { /* likely */ }
5606 else
5607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5608
5609 /*
5610 * Pending debug exceptions.
5611 */
5612 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5613 ? pVmcs->u64GuestPendingDbgXcpt.u
5614 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5615 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5616 { /* likely */ }
5617 else
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5619
5620 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5621 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5622 {
5623 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5624 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5625 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5627
5628 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5629 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5630 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5632 }
5633
5634 /* We don't support RTM (Real-time Transactional Memory) yet. */
5635 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5636 { /* likely */ }
5637 else
5638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5639
5640 /*
5641 * VMCS link pointer.
5642 */
5643 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5644 {
5645 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5646 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5647 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5648 { /* likely */ }
5649 else
5650 {
5651 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5653 }
5654
5655 /* Validate the address. */
5656 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5657 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5658 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5659 { /* likely */ }
5660 else
5661 {
5662 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5663 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5664 }
5665
5666 /* Read the VMCS-link pointer from guest memory. */
5667 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5668 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5669 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5670 if (RT_SUCCESS(rc))
5671 { /* likely */ }
5672 else
5673 {
5674 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5675 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5676 }
5677
5678 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5679 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5680 { /* likely */ }
5681 else
5682 {
5683 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5685 }
5686
5687 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5688 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5689 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5690 { /* likely */ }
5691 else
5692 {
5693 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5694 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5695 }
5696
5697 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5698 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5699 }
5700
5701 NOREF(pszInstr);
5702 NOREF(pszFailure);
5703 return VINF_SUCCESS;
5704}
5705
5706
5707/**
5708 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5709 * VM-entry.
5710 *
5711 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5712 * @param pVCpu The cross context virtual CPU structure.
5713 * @param pszInstr The VMX instruction name (for logging purposes).
5714 * @param pVmcs Pointer to the virtual VMCS.
5715 */
5716IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5717{
5718 /*
5719 * Check PDPTEs.
5720 * See Intel spec. 4.4.1 "PDPTE Registers".
5721 */
5722 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5723 const char *const pszFailure = "VM-exit";
5724
5725 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5726 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5727 if (RT_SUCCESS(rc))
5728 {
5729 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5730 {
5731 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5732 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5733 { /* likely */ }
5734 else
5735 {
5736 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5737 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5739 }
5740 }
5741 }
5742 else
5743 {
5744 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5746 }
5747
5748 NOREF(pszFailure);
5749 NOREF(pszInstr);
5750 return rc;
5751}
5752
5753
5754/**
5755 * Checks guest PDPTEs as part of VM-entry.
5756 *
5757 * @param pVCpu The cross context virtual CPU structure.
5758 * @param pszInstr The VMX instruction name (for logging purposes).
5759 */
5760IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5761{
5762 /*
5763 * Guest PDPTEs.
5764 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5765 */
5766 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5767 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5768
5769 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5770 int rc;
5771 if ( !fGstInLongMode
5772 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5773 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5774 {
5775 /*
5776 * We don't support nested-paging for nested-guests yet.
5777 *
5778 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5779 * rather we need to check the PDPTEs referenced by the guest CR3.
5780 */
5781 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5782 }
5783 else
5784 rc = VINF_SUCCESS;
5785 return rc;
5786}
5787
5788
5789/**
5790 * Checks guest-state as part of VM-entry.
5791 *
5792 * @returns VBox status code.
5793 * @param pVCpu The cross context virtual CPU structure.
5794 * @param pszInstr The VMX instruction name (for logging purposes).
5795 */
5796IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5797{
5798 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5799 if (RT_SUCCESS(rc))
5800 {
5801 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5802 if (RT_SUCCESS(rc))
5803 {
5804 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5805 if (RT_SUCCESS(rc))
5806 {
5807 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5808 if (RT_SUCCESS(rc))
5809 {
5810 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5811 if (RT_SUCCESS(rc))
5812 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5813 }
5814 }
5815 }
5816 }
5817 return rc;
5818}
5819
5820
5821/**
5822 * Checks host-state as part of VM-entry.
5823 *
5824 * @returns VBox status code.
5825 * @param pVCpu The cross context virtual CPU structure.
5826 * @param pszInstr The VMX instruction name (for logging purposes).
5827 */
5828IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
5829{
5830 /*
5831 * Host Control Registers and MSRs.
5832 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5833 */
5834 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5835 const char * const pszFailure = "VMFail";
5836
5837 /* CR0 reserved bits. */
5838 {
5839 /* CR0 MB1 bits. */
5840 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5841 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5845
5846 /* CR0 MBZ bits. */
5847 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5848 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5849 { /* likely */ }
5850 else
5851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5852 }
5853
5854 /* CR4 reserved bits. */
5855 {
5856 /* CR4 MB1 bits. */
5857 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5858 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5859 { /* likely */ }
5860 else
5861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5862
5863 /* CR4 MBZ bits. */
5864 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5865 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5869 }
5870
5871 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5872 {
5873 /* CR3 reserved bits. */
5874 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5875 { /* likely */ }
5876 else
5877 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5878
5879 /* SYSENTER ESP and SYSENTER EIP. */
5880 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5881 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5882 { /* likely */ }
5883 else
5884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5885 }
5886
5887 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5888 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5889
5890 /* PAT MSR. */
5891 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5892 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5893 { /* likely */ }
5894 else
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5896
5897 /* EFER MSR. */
5898 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5899 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5900 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5904
5905 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5906 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5907 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5908 if ( fHostInLongMode == fHostLma
5909 && fHostInLongMode == fHostLme)
5910 { /* likely */ }
5911 else
5912 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5913
5914 /*
5915 * Host Segment and Descriptor-Table Registers.
5916 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5917 */
5918 /* Selector RPL and TI. */
5919 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5920 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5921 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5922 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5923 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5924 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5925 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5926 { /* likely */ }
5927 else
5928 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5929
5930 /* CS and TR selectors cannot be 0. */
5931 if ( pVmcs->HostCs
5932 && pVmcs->HostTr)
5933 { /* likely */ }
5934 else
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5936
5937 /* SS cannot be 0 if 32-bit host. */
5938 if ( fHostInLongMode
5939 || pVmcs->HostSs)
5940 { /* likely */ }
5941 else
5942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5943
5944 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5945 {
5946 /* FS, GS, GDTR, IDTR, TR base address. */
5947 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5948 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5949 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5950 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5951 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5952 { /* likely */ }
5953 else
5954 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5955 }
5956
5957 /*
5958 * Host address-space size for 64-bit CPUs.
5959 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5960 */
5961 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5962 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5963 {
5964 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5965
5966 /* Logical processor in IA-32e mode. */
5967 if (fCpuInLongMode)
5968 {
5969 if (fHostInLongMode)
5970 {
5971 /* PAE must be set. */
5972 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5976
5977 /* RIP must be canonical. */
5978 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5979 { /* likely */ }
5980 else
5981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5982 }
5983 else
5984 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5985 }
5986 else
5987 {
5988 /* Logical processor is outside IA-32e mode. */
5989 if ( !fGstInLongMode
5990 && !fHostInLongMode)
5991 {
5992 /* PCIDE should not be set. */
5993 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5994 { /* likely */ }
5995 else
5996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5997
5998 /* The high 32-bits of RIP MBZ. */
5999 if (!pVmcs->u64HostRip.s.Hi)
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6003 }
6004 else
6005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6006 }
6007 }
6008 else
6009 {
6010 /* Host address-space size for 32-bit CPUs. */
6011 if ( !fGstInLongMode
6012 && !fHostInLongMode)
6013 { /* likely */ }
6014 else
6015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6016 }
6017
6018 NOREF(pszInstr);
6019 NOREF(pszFailure);
6020 return VINF_SUCCESS;
6021}
6022
6023
6024/**
6025 * Checks VM-entry controls fields as part of VM-entry.
6026 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6027 *
6028 * @returns VBox status code.
6029 * @param pVCpu The cross context virtual CPU structure.
6030 * @param pszInstr The VMX instruction name (for logging purposes).
6031 */
6032IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6033{
6034 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6035 const char * const pszFailure = "VMFail";
6036
6037 /* VM-entry controls. */
6038 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6039 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6040 { /* likely */ }
6041 else
6042 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6043
6044 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6045 { /* likely */ }
6046 else
6047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6048
6049 /* Event injection. */
6050 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6051 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6052 {
6053 /* Type and vector. */
6054 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6055 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6056 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6057 if ( !uRsvd
6058 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6059 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6060 { /* likely */ }
6061 else
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6063
6064 /* Exception error code. */
6065 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6066 {
6067 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6068 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6069 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6073
6074 /* Exceptions that provide an error code. */
6075 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6076 && ( uVector == X86_XCPT_DF
6077 || uVector == X86_XCPT_TS
6078 || uVector == X86_XCPT_NP
6079 || uVector == X86_XCPT_SS
6080 || uVector == X86_XCPT_GP
6081 || uVector == X86_XCPT_PF
6082 || uVector == X86_XCPT_AC))
6083 { /* likely */ }
6084 else
6085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6086
6087 /* Exception error-code reserved bits. */
6088 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6089 { /* likely */ }
6090 else
6091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6092
6093 /* Injecting a software interrupt, software exception or privileged software exception. */
6094 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6095 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6096 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6097 {
6098 /* Instruction length must be in the range 0-15. */
6099 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6100 { /* likely */ }
6101 else
6102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6103
6104 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6105 if ( pVmcs->u32EntryInstrLen == 0
6106 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6108 }
6109 }
6110 }
6111
6112 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6113 if (pVmcs->u32EntryMsrLoadCount)
6114 {
6115 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6116 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6117 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6118 { /* likely */ }
6119 else
6120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6121 }
6122
6123 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6124 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6125
6126 NOREF(pszInstr);
6127 NOREF(pszFailure);
6128 return VINF_SUCCESS;
6129}
6130
6131
6132/**
6133 * Checks VM-exit controls fields as part of VM-entry.
6134 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6135 *
6136 * @returns VBox status code.
6137 * @param pVCpu The cross context virtual CPU structure.
6138 * @param pszInstr The VMX instruction name (for logging purposes).
6139 */
6140IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6141{
6142 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6143 const char * const pszFailure = "VMFail";
6144
6145 /* VM-exit controls. */
6146 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6147 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6148 { /* likely */ }
6149 else
6150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6151
6152 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6153 { /* likely */ }
6154 else
6155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6156
6157 /* Save preemption timer without activating it. */
6158 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6159 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6163
6164 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6165 if (pVmcs->u32ExitMsrStoreCount)
6166 {
6167 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6168 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6169 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6173 }
6174
6175 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6176 if (pVmcs->u32ExitMsrLoadCount)
6177 {
6178 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6179 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6180 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6181 { /* likely */ }
6182 else
6183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6184 }
6185
6186 NOREF(pszInstr);
6187 NOREF(pszFailure);
6188 return VINF_SUCCESS;
6189}
6190
6191
6192/**
6193 * Checks VM-execution controls fields as part of VM-entry.
6194 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6195 *
6196 * @returns VBox status code.
6197 * @param pVCpu The cross context virtual CPU structure.
6198 * @param pszInstr The VMX instruction name (for logging purposes).
6199 *
6200 * @remarks This may update secondary-processor based VM-execution control fields
6201 * in the current VMCS if necessary.
6202 */
6203IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6204{
6205 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6206 const char * const pszFailure = "VMFail";
6207
6208 /* Pin-based VM-execution controls. */
6209 {
6210 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6211 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6215
6216 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6217 { /* likely */ }
6218 else
6219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6220 }
6221
6222 /* Processor-based VM-execution controls. */
6223 {
6224 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6225 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6226 { /* likely */ }
6227 else
6228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6229
6230 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6231 { /* likely */ }
6232 else
6233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6234 }
6235
6236 /* Secondary processor-based VM-execution controls. */
6237 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6238 {
6239 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6240 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6241 { /* likely */ }
6242 else
6243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6244
6245 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6246 { /* likely */ }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6249 }
6250 else
6251 Assert(!pVmcs->u32ProcCtls2);
6252
6253 /* CR3-target count. */
6254 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6255 { /* likely */ }
6256 else
6257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6258
6259 /* I/O bitmaps physical addresses. */
6260 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6261 {
6262 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6263 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6264 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6265 { /* likely */ }
6266 else
6267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6268
6269 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6270 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6271 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6272 { /* likely */ }
6273 else
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6275 }
6276
6277 /* MSR bitmap physical address. */
6278 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6279 {
6280 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6281 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6282 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6283 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6284 { /* likely */ }
6285 else
6286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6287
6288 /* Read the MSR bitmap. */
6289 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6290 * implementing fast path. */
6291 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6292 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6293 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6294 if (RT_SUCCESS(rc))
6295 { /* likely */ }
6296 else
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6298 }
6299
6300 /* TPR shadow related controls. */
6301 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6302 {
6303 /* Virtual-APIC page physical address. */
6304 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6305 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6306 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6307 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6308 { /* likely */ }
6309 else
6310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6311
6312 /* TPR threshold without virtual-interrupt delivery. */
6313 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6314 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6316
6317 /* TPR threshold and VTPR. */
6318 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6319 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6320 {
6321 /* Read the VTPR from the virtual-APIC page. */
6322 uint8_t u8VTpr;
6323 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6324 if (RT_SUCCESS(rc))
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6328
6329 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6330 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6331 { /* likely */ }
6332 else
6333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6334 }
6335 }
6336 else
6337 {
6338 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6339 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6340 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6341 { /* likely */ }
6342 else
6343 {
6344 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6345 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6346 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6347 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6348 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6350 }
6351 }
6352
6353 /* NMI exiting and virtual-NMIs. */
6354 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6355 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6356 { /* likely */ }
6357 else
6358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6359
6360 /* Virtual-NMIs and NMI-window exiting. */
6361 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6362 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6363 { /* likely */ }
6364 else
6365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6366
6367 /* Virtualize APIC accesses. */
6368 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6369 {
6370 /* APIC-access physical address. */
6371 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6372 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6373 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6374 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6375 { /* likely */ }
6376 else
6377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6378
6379 /*
6380 * Disallow APIC-access page and virtual-APIC page from being the same address.
6381 * Note! This is not an Intel requirement, but one imposed by our implementation.
6382 */
6383 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6384 * redirecting accesses between the APIC-access page and the virtual-APIC
6385 * page. If any guest hypervisor requires this, we can implement it later. */
6386 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6387 {
6388 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6389 if (GCPhysVirtApic != GCPhysApicAccess)
6390 { /* likely */ }
6391 else
6392 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6393 }
6394
6395 /*
6396 * Register the handler for the APIC-access page.
6397 *
6398 * We don't deregister the APIC-access page handler during the VM-exit as a different
6399 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6400 *
6401 * We leave the page registered until the first access that happens outside VMX non-root
6402 * mode. Guest software is allowed to access structures such as the APIC-access page
6403 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6404 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6405 *
6406 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6407 */
6408 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6409 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6410 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6411 if (RT_SUCCESS(rc))
6412 { /* likely */ }
6413 else
6414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6415 }
6416
6417 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6418 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6419 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6420 { /* likely */ }
6421 else
6422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6423
6424 /* Virtual-interrupt delivery requires external interrupt exiting. */
6425 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6426 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6427 { /* likely */ }
6428 else
6429 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6430
6431 /* VPID. */
6432 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6433 || pVmcs->u16Vpid != 0)
6434 { /* likely */ }
6435 else
6436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6437
6438 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6439 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6440 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6441 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6442 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6443 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6444 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6445
6446 /* VMCS shadowing. */
6447 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6448 {
6449 /* VMREAD-bitmap physical address. */
6450 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6451 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6452 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6453 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6454 { /* likely */ }
6455 else
6456 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6457
6458 /* VMWRITE-bitmap physical address. */
6459 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6460 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6461 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6462 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6463 { /* likely */ }
6464 else
6465 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6466
6467 /* Read the VMREAD-bitmap. */
6468 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6469 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6470 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6471 if (RT_SUCCESS(rc))
6472 { /* likely */ }
6473 else
6474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6475
6476 /* Read the VMWRITE-bitmap. */
6477 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6478 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6479 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6480 if (RT_SUCCESS(rc))
6481 { /* likely */ }
6482 else
6483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6484 }
6485
6486 NOREF(pszInstr);
6487 NOREF(pszFailure);
6488 return VINF_SUCCESS;
6489}
6490
6491
6492/**
6493 * Loads the guest control registers, debug register and some MSRs as part of
6494 * VM-entry.
6495 *
6496 * @param pVCpu The cross context virtual CPU structure.
6497 */
6498IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6499{
6500 /*
6501 * Load guest control registers, debug registers and MSRs.
6502 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6503 */
6504 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6505
6506 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6507 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6508 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6509 CPUMSetGuestCR0(pVCpu, uGstCr0);
6510 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6511 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6512
6513 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6514 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6515
6516 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6517 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6518 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6519
6520 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6521 {
6522 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6523
6524 /* EFER MSR. */
6525 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6526 {
6527 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6528 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6529 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6530 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6531 if (fGstInLongMode)
6532 {
6533 /* If the nested-guest is in long mode, LMA and LME are both set. */
6534 Assert(fGstPaging);
6535 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6536 }
6537 else
6538 {
6539 /*
6540 * If the nested-guest is outside long mode:
6541 * - With paging: LMA is cleared, LME is cleared.
6542 * - Without paging: LMA is cleared, LME is left unmodified.
6543 */
6544 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6545 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6546 }
6547 }
6548 /* else: see below. */
6549 }
6550
6551 /* PAT MSR. */
6552 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6553 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6554
6555 /* EFER MSR. */
6556 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6557 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6558
6559 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6560 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6561
6562 /* We don't support IA32_BNDCFGS MSR yet. */
6563 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6564
6565 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6566}
6567
6568
6569/**
6570 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6571 *
6572 * @param pVCpu The cross context virtual CPU structure.
6573 */
6574IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6575{
6576 /*
6577 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6578 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6579 */
6580 /* CS, SS, ES, DS, FS, GS. */
6581 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6582 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6583 {
6584 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6585 CPUMSELREG VmcsSelReg;
6586 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6587 AssertRC(rc); NOREF(rc);
6588 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6589 {
6590 pGstSelReg->Sel = VmcsSelReg.Sel;
6591 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6592 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6593 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6594 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6595 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6596 }
6597 else
6598 {
6599 pGstSelReg->Sel = VmcsSelReg.Sel;
6600 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6601 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6602 switch (iSegReg)
6603 {
6604 case X86_SREG_CS:
6605 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6606 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6607 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6608 break;
6609
6610 case X86_SREG_SS:
6611 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6612 pGstSelReg->u32Limit = 0;
6613 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6614 break;
6615
6616 case X86_SREG_ES:
6617 case X86_SREG_DS:
6618 pGstSelReg->u64Base = 0;
6619 pGstSelReg->u32Limit = 0;
6620 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6621 break;
6622
6623 case X86_SREG_FS:
6624 case X86_SREG_GS:
6625 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6626 pGstSelReg->u32Limit = 0;
6627 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6628 break;
6629 }
6630 Assert(pGstSelReg->Attr.n.u1Unusable);
6631 }
6632 }
6633
6634 /* LDTR. */
6635 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6636 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6637 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6638 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6639 {
6640 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6641 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6642 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6643 }
6644 else
6645 {
6646 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6647 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6648 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6649 }
6650
6651 /* TR. */
6652 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6653 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6654 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6655 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6656 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6657 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6658 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6659
6660 /* GDTR. */
6661 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6662 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6663
6664 /* IDTR. */
6665 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6666 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6667}
6668
6669
6670/**
6671 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6672 *
6673 * @returns VBox status code.
6674 * @param pVCpu The cross context virtual CPU structure.
6675 * @param pszInstr The VMX instruction name (for logging purposes).
6676 */
6677IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6678{
6679 /*
6680 * Load guest MSRs.
6681 * See Intel spec. 26.4 "Loading MSRs".
6682 */
6683 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6684 const char *const pszFailure = "VM-exit";
6685
6686 /*
6687 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6688 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6689 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6690 */
6691 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6692 if (!cMsrs)
6693 return VINF_SUCCESS;
6694
6695 /*
6696 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6697 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6698 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6699 */
6700 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6701 if (fIsMsrCountValid)
6702 { /* likely */ }
6703 else
6704 {
6705 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6706 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6707 }
6708
6709 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6710 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6711 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6712 if (RT_SUCCESS(rc))
6713 {
6714 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6715 Assert(pMsr);
6716 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6717 {
6718 if ( !pMsr->u32Reserved
6719 && pMsr->u32Msr != MSR_K8_FS_BASE
6720 && pMsr->u32Msr != MSR_K8_GS_BASE
6721 && pMsr->u32Msr != MSR_K6_EFER
6722 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6723 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6724 {
6725 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6726 if (rcStrict == VINF_SUCCESS)
6727 continue;
6728
6729 /*
6730 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6731 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6732 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6733 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6734 * MSR in ring-0 if possible, or come up with a better, generic solution.
6735 */
6736 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6737 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6738 ? kVmxVDiag_Vmentry_MsrLoadRing3
6739 : kVmxVDiag_Vmentry_MsrLoad;
6740 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6741 }
6742 else
6743 {
6744 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6745 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6746 }
6747 }
6748 }
6749 else
6750 {
6751 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6753 }
6754
6755 NOREF(pszInstr);
6756 NOREF(pszFailure);
6757 return VINF_SUCCESS;
6758}
6759
6760
6761/**
6762 * Loads the guest-state non-register state as part of VM-entry.
6763 *
6764 * @returns VBox status code.
6765 * @param pVCpu The cross context virtual CPU structure.
6766 *
6767 * @remarks This must be called only after loading the nested-guest register state
6768 * (especially nested-guest RIP).
6769 */
6770IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6771{
6772 /*
6773 * Load guest non-register state.
6774 * See Intel spec. 26.6 "Special Features of VM Entry"
6775 */
6776 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6777
6778 /*
6779 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6780 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6781 *
6782 * See Intel spec. 26.6.1 "Interruptibility State".
6783 */
6784 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6785 if ( !fEntryVectoring
6786 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6787 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6788 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6789 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6790
6791 /* NMI blocking. */
6792 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6793 {
6794 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6795 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6796 else
6797 {
6798 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6799 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6800 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6801 }
6802 }
6803 else
6804 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6805
6806 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6807
6808 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6809 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6810
6811 /* VPID is irrelevant. We don't support VPID yet. */
6812
6813 /* Clear address-range monitoring. */
6814 EMMonitorWaitClear(pVCpu);
6815}
6816
6817
6818/**
6819 * Loads the guest-state as part of VM-entry.
6820 *
6821 * @returns VBox status code.
6822 * @param pVCpu The cross context virtual CPU structure.
6823 * @param pszInstr The VMX instruction name (for logging purposes).
6824 *
6825 * @remarks This must be done after all the necessary steps prior to loading of
6826 * guest-state (e.g. checking various VMCS state).
6827 */
6828IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6829{
6830 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6831 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6832
6833 /*
6834 * Load guest RIP, RSP and RFLAGS.
6835 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6836 */
6837 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6838 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6839 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6840 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6841
6842 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6843 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6844 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6845
6846 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6847
6848 NOREF(pszInstr);
6849 return VINF_SUCCESS;
6850}
6851
6852
6853/**
6854 * Returns whether there are is a pending debug exception on VM-entry.
6855 *
6856 * @param pVCpu The cross context virtual CPU structure.
6857 * @param pszInstr The VMX instruction name (for logging purposes).
6858 */
6859IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6860{
6861 /*
6862 * Pending debug exceptions.
6863 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6864 */
6865 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6866 Assert(pVmcs);
6867
6868 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6869 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6870 if (fPendingDbgXcpt)
6871 {
6872 uint8_t uEntryIntInfoType;
6873 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6874 if (fEntryVectoring)
6875 {
6876 switch (uEntryIntInfoType)
6877 {
6878 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6879 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6880 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6881 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6882 fPendingDbgXcpt = false;
6883 break;
6884
6885 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6886 {
6887 /*
6888 * Whether the pending debug exception for software exceptions other than
6889 * #BP and #OF is delivered after injecting the exception or is discard
6890 * is CPU implementation specific. We will discard them (easier).
6891 */
6892 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6893 if ( uVector != X86_XCPT_BP
6894 && uVector != X86_XCPT_OF)
6895 fPendingDbgXcpt = false;
6896 RT_FALL_THRU();
6897 }
6898 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6899 {
6900 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6901 fPendingDbgXcpt = false;
6902 break;
6903 }
6904 }
6905 }
6906 else
6907 {
6908 /*
6909 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6910 * pending debug exception is held pending or is discarded is CPU implementation
6911 * specific. We will discard them (easier).
6912 */
6913 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6914 fPendingDbgXcpt = false;
6915
6916 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6917 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6918 fPendingDbgXcpt = false;
6919 }
6920 }
6921
6922 NOREF(pszInstr);
6923 return fPendingDbgXcpt;
6924}
6925
6926
6927/**
6928 * Set up the monitor-trap flag (MTF).
6929 *
6930 * @param pVCpu The cross context virtual CPU structure.
6931 * @param pszInstr The VMX instruction name (for logging purposes).
6932 */
6933IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
6934{
6935 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6936 Assert(pVmcs);
6937 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6938 {
6939 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6940 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6941 }
6942 else
6943 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6944 NOREF(pszInstr);
6945}
6946
6947
6948/**
6949 * Sets up NMI-window exiting.
6950 *
6951 * @param pVCpu The cross context virtual CPU structure.
6952 * @param pszInstr The VMX instruction name (for logging purposes).
6953 */
6954IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
6955{
6956 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6957 Assert(pVmcs);
6958 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6959 {
6960 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6961 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6962 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6963 }
6964 else
6965 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6966 NOREF(pszInstr);
6967}
6968
6969
6970/**
6971 * Sets up interrupt-window exiting.
6972 *
6973 * @param pVCpu The cross context virtual CPU structure.
6974 * @param pszInstr The VMX instruction name (for logging purposes).
6975 */
6976IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
6977{
6978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6979 Assert(pVmcs);
6980 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6981 {
6982 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6983 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6984 }
6985 else
6986 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6987 NOREF(pszInstr);
6988}
6989
6990
6991/**
6992 * Set up the VMX-preemption timer.
6993 *
6994 * @param pVCpu The cross context virtual CPU structure.
6995 * @param pszInstr The VMX instruction name (for logging purposes).
6996 */
6997IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
6998{
6999 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7000 Assert(pVmcs);
7001 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7002 {
7003 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7004 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7005 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7006
7007 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7008 }
7009 else
7010 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7011
7012 NOREF(pszInstr);
7013}
7014
7015
7016/**
7017 * Injects an event using TRPM given a VM-entry interruption info. and related
7018 * fields.
7019 *
7020 * @returns VBox status code.
7021 * @param pVCpu The cross context virtual CPU structure.
7022 * @param uEntryIntInfo The VM-entry interruption info.
7023 * @param uErrCode The error code associated with the event if any.
7024 * @param cbInstr The VM-entry instruction length (for software
7025 * interrupts and software exceptions). Pass 0
7026 * otherwise.
7027 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7028 */
7029IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7030 RTGCUINTPTR GCPtrFaultAddress)
7031{
7032 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7033
7034 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7035 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7036 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7037
7038 TRPMEVENT enmTrapType;
7039 switch (uType)
7040 {
7041 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7042 enmTrapType = TRPM_HARDWARE_INT;
7043 break;
7044
7045 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7046 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7047 enmTrapType = TRPM_TRAP;
7048 break;
7049
7050 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7051 enmTrapType = TRPM_SOFTWARE_INT;
7052 break;
7053
7054 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7055 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7056 enmTrapType = TRPM_SOFTWARE_INT;
7057 break;
7058
7059 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7060 Assert(uVector == X86_XCPT_DB);
7061 enmTrapType = TRPM_SOFTWARE_INT;
7062 break;
7063
7064 default:
7065 /* Shouldn't really happen. */
7066 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7067 break;
7068 }
7069
7070 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7071 AssertRCReturn(rc, rc);
7072
7073 if (fErrCodeValid)
7074 TRPMSetErrorCode(pVCpu, uErrCode);
7075
7076 if ( enmTrapType == TRPM_TRAP
7077 && uVector == X86_XCPT_PF)
7078 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7079 else if (enmTrapType == TRPM_SOFTWARE_INT)
7080 TRPMSetInstrLength(pVCpu, cbInstr);
7081
7082 return VINF_SUCCESS;
7083}
7084
7085
7086/**
7087 * Performs event injection (if any) as part of VM-entry.
7088 *
7089 * @param pVCpu The cross context virtual CPU structure.
7090 * @param pszInstr The VMX instruction name (for logging purposes).
7091 */
7092IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7093{
7094 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7095
7096 /*
7097 * Inject events.
7098 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7099 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7100 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7101 * the actually delivery of this event.
7102 *
7103 * See Intel spec. 26.5 "Event Injection".
7104 */
7105 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7106 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7107
7108 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7109 if (fEntryIntInfoValid)
7110 {
7111 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7112 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7113 {
7114 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7115 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7116 return VINF_SUCCESS;
7117 }
7118
7119 int rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7120 pVCpu->cpum.GstCtx.cr2);
7121 if (RT_SUCCESS(rc))
7122 {
7123 /*
7124 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7125 *
7126 * However, we do it here on VM-entry because while it continues to not be visible to
7127 * guest software until VM-exit, when HM looks at the VMCS to continue nested-guest
7128 * execution using hardware-assisted VT-x, it can simply copy the VM-entry interruption
7129 * information field.
7130 *
7131 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7132 */
7133 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7134 }
7135 return rc;
7136 }
7137
7138 /*
7139 * Inject any pending guest debug exception.
7140 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7141 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7142 */
7143 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7144 if (fPendingDbgXcpt)
7145 {
7146 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7147 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7148 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7149 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7150 0 /* GCPtrFaultAddress */);
7151 }
7152
7153 NOREF(pszInstr);
7154 return VINF_SUCCESS;
7155}
7156
7157
7158/**
7159 * Initializes all read-only VMCS fields as part of VM-entry.
7160 *
7161 * @param pVCpu The cross context virtual CPU structure.
7162 */
7163IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7164{
7165 /*
7166 * Any VMCS field which we do not establish on every VM-exit but may potentially
7167 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7168 * specified to be undefined needs to be initialized here.
7169 *
7170 * Thus, it is especially important to clear the Exit qualification field
7171 * since it must be zero for VM-exits where it is not used. Similarly, the
7172 * VM-exit interruption information field's valid bit needs to be cleared for
7173 * the same reasons.
7174 */
7175 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7176 Assert(pVmcs);
7177
7178 /* 16-bit (none currently). */
7179 /* 32-bit. */
7180 pVmcs->u32RoVmInstrError = 0;
7181 pVmcs->u32RoExitReason = 0;
7182 pVmcs->u32RoExitIntInfo = 0;
7183 pVmcs->u32RoExitIntErrCode = 0;
7184 pVmcs->u32RoIdtVectoringInfo = 0;
7185 pVmcs->u32RoIdtVectoringErrCode = 0;
7186 pVmcs->u32RoExitInstrLen = 0;
7187 pVmcs->u32RoExitInstrInfo = 0;
7188
7189 /* 64-bit. */
7190 pVmcs->u64RoGuestPhysAddr.u = 0;
7191
7192 /* Natural-width. */
7193 pVmcs->u64RoExitQual.u = 0;
7194 pVmcs->u64RoIoRcx.u = 0;
7195 pVmcs->u64RoIoRsi.u = 0;
7196 pVmcs->u64RoIoRdi.u = 0;
7197 pVmcs->u64RoIoRip.u = 0;
7198 pVmcs->u64RoGuestLinearAddr.u = 0;
7199}
7200
7201
7202/**
7203 * VMLAUNCH/VMRESUME instruction execution worker.
7204 *
7205 * @returns Strict VBox status code.
7206 * @param pVCpu The cross context virtual CPU structure.
7207 * @param cbInstr The instruction length in bytes.
7208 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7209 * VMXINSTRID_VMRESUME).
7210 *
7211 * @remarks Common VMX instruction checks are already expected to by the caller,
7212 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7213 */
7214IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7215{
7216# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7217 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7218 return VINF_EM_RAW_EMULATE_INSTR;
7219# else
7220 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7221 || uInstrId == VMXINSTRID_VMRESUME);
7222 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7223
7224 /* Nested-guest intercept. */
7225 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7226 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7227
7228 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7229
7230 /*
7231 * Basic VM-entry checks.
7232 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7233 * The checks following that do not have to follow a specific order.
7234 *
7235 * See Intel spec. 26.1 "Basic VM-entry Checks".
7236 */
7237
7238 /* CPL. */
7239 if (pVCpu->iem.s.uCpl == 0)
7240 { /* likely */ }
7241 else
7242 {
7243 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7244 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7245 return iemRaiseGeneralProtectionFault0(pVCpu);
7246 }
7247
7248 /* Current VMCS valid. */
7249 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7250 { /* likely */ }
7251 else
7252 {
7253 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7254 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7255 iemVmxVmFailInvalid(pVCpu);
7256 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7257 return VINF_SUCCESS;
7258 }
7259
7260 /* Current VMCS is not a shadow VMCS. */
7261 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7262 { /* likely */ }
7263 else
7264 {
7265 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7266 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7267 iemVmxVmFailInvalid(pVCpu);
7268 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7269 return VINF_SUCCESS;
7270 }
7271
7272 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7273 * use block-by-STI here which is not quite correct. */
7274 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7275 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7276 { /* likely */ }
7277 else
7278 {
7279 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7280 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7281 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7282 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7283 return VINF_SUCCESS;
7284 }
7285
7286 if (uInstrId == VMXINSTRID_VMLAUNCH)
7287 {
7288 /* VMLAUNCH with non-clear VMCS. */
7289 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7290 { /* likely */ }
7291 else
7292 {
7293 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7294 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7295 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7296 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7297 return VINF_SUCCESS;
7298 }
7299 }
7300 else
7301 {
7302 /* VMRESUME with non-launched VMCS. */
7303 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7304 { /* likely */ }
7305 else
7306 {
7307 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7309 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7310 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7311 return VINF_SUCCESS;
7312 }
7313 }
7314
7315 /*
7316 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7317 * while entering VMX non-root mode. We do some of this while checking VM-execution
7318 * controls. The guest hypervisor should not make assumptions and cannot expect
7319 * predictable behavior if changes to these structures are made in guest memory while
7320 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7321 * modify them anyway as we cache them in host memory.
7322 *
7323 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7324 */
7325 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7326 Assert(pVmcs);
7327 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7328
7329 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7330 if (RT_SUCCESS(rc))
7331 {
7332 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7333 if (RT_SUCCESS(rc))
7334 {
7335 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7336 if (RT_SUCCESS(rc))
7337 {
7338 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7339 if (RT_SUCCESS(rc))
7340 {
7341 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7342 iemVmxVmentryInitReadOnlyFields(pVCpu);
7343
7344 /*
7345 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7346 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7347 * VM-exit when required.
7348 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7349 */
7350 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7351
7352 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7353 if (RT_SUCCESS(rc))
7354 {
7355 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7356 if (RT_SUCCESS(rc))
7357 {
7358 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7359 if (RT_SUCCESS(rc))
7360 {
7361 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7362
7363 /* VMLAUNCH instruction must update the VMCS launch state. */
7364 if (uInstrId == VMXINSTRID_VMLAUNCH)
7365 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7366
7367 /* Perform the VMX transition (PGM updates). */
7368 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7369 if (rcStrict == VINF_SUCCESS)
7370 { /* likely */ }
7371 else if (RT_SUCCESS(rcStrict))
7372 {
7373 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7374 VBOXSTRICTRC_VAL(rcStrict)));
7375 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7376 }
7377 else
7378 {
7379 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7380 return rcStrict;
7381 }
7382
7383 /* We've now entered nested-guest execution. */
7384 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7385
7386 /*
7387 * The priority of potential VM-exits during VM-entry is important.
7388 * The priorities of VM-exits and events are listed from highest
7389 * to lowest as follows:
7390 *
7391 * 1. Event injection.
7392 * 2. Trap on task-switch (T flag set in TSS).
7393 * 3. TPR below threshold / APIC-write.
7394 * 4. SMI, INIT.
7395 * 5. MTF exit.
7396 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7397 * 7. VMX-preemption timer.
7398 * 9. NMI-window exit.
7399 * 10. NMI injection.
7400 * 11. Interrupt-window exit.
7401 * 12. Virtual-interrupt injection.
7402 * 13. Interrupt injection.
7403 * 14. Process next instruction (fetch, decode, execute).
7404 */
7405
7406 /* Setup the VMX-preemption timer. */
7407 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7408
7409 /* Setup monitor-trap flag. */
7410 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7411
7412 /* Setup NMI-window exiting. */
7413 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7414
7415 /* Setup interrupt-window exiting. */
7416 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7417
7418 /* Now that we've switched page tables, we can go ahead and inject any event. */
7419 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7420 if (RT_SUCCESS(rcStrict))
7421 {
7422 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7423# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7424 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7425 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7426 if (rcSched != VINF_SUCCESS)
7427 iemSetPassUpStatus(pVCpu, rcSched);
7428# endif
7429 return VINF_SUCCESS;
7430 }
7431
7432 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7433 return rcStrict;
7434 }
7435 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7436 pVmcs->u64RoExitQual.u);
7437 }
7438 }
7439 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7440 pVmcs->u64RoExitQual.u);
7441 }
7442
7443 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7444 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7445 return VINF_SUCCESS;
7446 }
7447 }
7448 }
7449
7450 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7451 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7452 return VINF_SUCCESS;
7453# endif
7454}
7455
7456
7457/**
7458 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7459 * (causes a VM-exit) or not.
7460 *
7461 * @returns @c true if the instruction is intercepted, @c false otherwise.
7462 * @param pVCpu The cross context virtual CPU structure.
7463 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7464 * VMX_EXIT_WRMSR).
7465 * @param idMsr The MSR.
7466 */
7467IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7468{
7469 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7470 Assert( uExitReason == VMX_EXIT_RDMSR
7471 || uExitReason == VMX_EXIT_WRMSR);
7472
7473 /* Consult the MSR bitmap if the feature is supported. */
7474 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7475 Assert(pVmcs);
7476 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7477 {
7478 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7479 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7480 if (uExitReason == VMX_EXIT_RDMSR)
7481 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7482 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7483 }
7484
7485 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7486 return true;
7487}
7488
7489
7490/**
7491 * VMREAD instruction execution worker that does not perform any validation checks.
7492 *
7493 * Callers are expected to have performed the necessary checks and to ensure the
7494 * VMREAD will succeed.
7495 *
7496 * @param pVmcs Pointer to the virtual VMCS.
7497 * @param pu64Dst Where to write the VMCS value.
7498 * @param u64VmcsField The VMCS field.
7499 *
7500 * @remarks May be called with interrupts disabled.
7501 */
7502IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7503{
7504 VMXVMCSFIELD VmcsField;
7505 VmcsField.u = u64VmcsField;
7506 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7507 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7508 uint8_t const uWidthType = (uWidth << 2) | uType;
7509 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7512 Assert(offField < VMX_V_VMCS_SIZE);
7513 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7514
7515 /*
7516 * Read the VMCS component based on the field's effective width.
7517 *
7518 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7519 * indicates high bits (little endian).
7520 *
7521 * Note! The caller is responsible to trim the result and update registers
7522 * or memory locations are required. Here we just zero-extend to the largest
7523 * type (i.e. 64-bits).
7524 */
7525 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7526 uint8_t const *pbField = pbVmcs + offField;
7527 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7528 switch (uEffWidth)
7529 {
7530 case VMX_VMCSFIELD_WIDTH_64BIT:
7531 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7532 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7533 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7534 }
7535}
7536
7537
7538/**
7539 * VMREAD common (memory/register) instruction execution worker.
7540 *
7541 * @returns Strict VBox status code.
7542 * @param pVCpu The cross context virtual CPU structure.
7543 * @param cbInstr The instruction length in bytes.
7544 * @param pu64Dst Where to write the VMCS value (only updated when
7545 * VINF_SUCCESS is returned).
7546 * @param u64VmcsField The VMCS field.
7547 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7548 * NULL.
7549 */
7550IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7551 PCVMXVEXITINFO pExitInfo)
7552{
7553 /* Nested-guest intercept. */
7554 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7555 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7556 {
7557 if (pExitInfo)
7558 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7559 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7560 }
7561
7562 /* CPL. */
7563 if (pVCpu->iem.s.uCpl == 0)
7564 { /* likely */ }
7565 else
7566 {
7567 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7569 return iemRaiseGeneralProtectionFault0(pVCpu);
7570 }
7571
7572 /* VMCS pointer in root mode. */
7573 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7574 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7575 { /* likely */ }
7576 else
7577 {
7578 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7580 iemVmxVmFailInvalid(pVCpu);
7581 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7582 return VINF_SUCCESS;
7583 }
7584
7585 /* VMCS-link pointer in non-root mode. */
7586 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7587 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7588 { /* likely */ }
7589 else
7590 {
7591 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7593 iemVmxVmFailInvalid(pVCpu);
7594 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7595 return VINF_SUCCESS;
7596 }
7597
7598 /* Supported VMCS field. */
7599 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7600 { /* likely */ }
7601 else
7602 {
7603 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7605 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7606 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7607 return VINF_SUCCESS;
7608 }
7609
7610 /*
7611 * Reading from the current or shadow VMCS.
7612 */
7613 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7614 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7615 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7616 Assert(pVmcs);
7617 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7618 return VINF_SUCCESS;
7619}
7620
7621
7622/**
7623 * VMREAD (64-bit register) instruction execution worker.
7624 *
7625 * @returns Strict VBox status code.
7626 * @param pVCpu The cross context virtual CPU structure.
7627 * @param cbInstr The instruction length in bytes.
7628 * @param pu64Dst Where to store the VMCS field's value.
7629 * @param u64VmcsField The VMCS field.
7630 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7631 * NULL.
7632 */
7633IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7634 PCVMXVEXITINFO pExitInfo)
7635{
7636 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7637 if (rcStrict == VINF_SUCCESS)
7638 {
7639 iemVmxVmreadSuccess(pVCpu, cbInstr);
7640 return VINF_SUCCESS;
7641 }
7642
7643 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7644 return rcStrict;
7645}
7646
7647
7648/**
7649 * VMREAD (32-bit register) instruction execution worker.
7650 *
7651 * @returns Strict VBox status code.
7652 * @param pVCpu The cross context virtual CPU structure.
7653 * @param cbInstr The instruction length in bytes.
7654 * @param pu32Dst Where to store the VMCS field's value.
7655 * @param u32VmcsField The VMCS field.
7656 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7657 * NULL.
7658 */
7659IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7660 PCVMXVEXITINFO pExitInfo)
7661{
7662 uint64_t u64Dst;
7663 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7664 if (rcStrict == VINF_SUCCESS)
7665 {
7666 *pu32Dst = u64Dst;
7667 iemVmxVmreadSuccess(pVCpu, cbInstr);
7668 return VINF_SUCCESS;
7669 }
7670
7671 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7672 return rcStrict;
7673}
7674
7675
7676/**
7677 * VMREAD (memory) instruction execution worker.
7678 *
7679 * @returns Strict VBox status code.
7680 * @param pVCpu The cross context virtual CPU structure.
7681 * @param cbInstr The instruction length in bytes.
7682 * @param iEffSeg The effective segment register to use with @a u64Val.
7683 * Pass UINT8_MAX if it is a register access.
7684 * @param GCPtrDst The guest linear address to store the VMCS field's
7685 * value.
7686 * @param u64VmcsField The VMCS field.
7687 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7688 * NULL.
7689 */
7690IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7691 PCVMXVEXITINFO pExitInfo)
7692{
7693 uint64_t u64Dst;
7694 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7695 if (rcStrict == VINF_SUCCESS)
7696 {
7697 /*
7698 * Write the VMCS field's value to the location specified in guest-memory.
7699 */
7700 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7701 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7702 else
7703 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7704 if (rcStrict == VINF_SUCCESS)
7705 {
7706 iemVmxVmreadSuccess(pVCpu, cbInstr);
7707 return VINF_SUCCESS;
7708 }
7709
7710 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7711 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7712 return rcStrict;
7713 }
7714
7715 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7716 return rcStrict;
7717}
7718
7719
7720/**
7721 * VMWRITE instruction execution worker that does not perform any validation
7722 * checks.
7723 *
7724 * Callers are expected to have performed the necessary checks and to ensure the
7725 * VMWRITE will succeed.
7726 *
7727 * @param pVmcs Pointer to the virtual VMCS.
7728 * @param u64Val The value to write.
7729 * @param u64VmcsField The VMCS field.
7730 *
7731 * @remarks May be called with interrupts disabled.
7732 */
7733IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7734{
7735 VMXVMCSFIELD VmcsField;
7736 VmcsField.u = u64VmcsField;
7737 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7738 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7739 uint8_t const uWidthType = (uWidth << 2) | uType;
7740 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7741 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7742 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7743 Assert(offField < VMX_V_VMCS_SIZE);
7744 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7745
7746 /*
7747 * Write the VMCS component based on the field's effective width.
7748 *
7749 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7750 * indicates high bits (little endian).
7751 */
7752 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7753 uint8_t *pbField = pbVmcs + offField;
7754 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7755 switch (uEffWidth)
7756 {
7757 case VMX_VMCSFIELD_WIDTH_64BIT:
7758 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7759 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7760 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7761 }
7762}
7763
7764
7765/**
7766 * VMWRITE instruction execution worker.
7767 *
7768 * @returns Strict VBox status code.
7769 * @param pVCpu The cross context virtual CPU structure.
7770 * @param cbInstr The instruction length in bytes.
7771 * @param iEffSeg The effective segment register to use with @a u64Val.
7772 * Pass UINT8_MAX if it is a register access.
7773 * @param u64Val The value to write (or guest linear address to the
7774 * value), @a iEffSeg will indicate if it's a memory
7775 * operand.
7776 * @param u64VmcsField The VMCS field.
7777 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7778 * NULL.
7779 */
7780IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7781 PCVMXVEXITINFO pExitInfo)
7782{
7783 /* Nested-guest intercept. */
7784 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7785 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7786 {
7787 if (pExitInfo)
7788 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7789 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7790 }
7791
7792 /* CPL. */
7793 if (pVCpu->iem.s.uCpl == 0)
7794 { /* likely */ }
7795 else
7796 {
7797 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7798 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7799 return iemRaiseGeneralProtectionFault0(pVCpu);
7800 }
7801
7802 /* VMCS pointer in root mode. */
7803 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7804 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7805 { /* likely */ }
7806 else
7807 {
7808 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7809 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7810 iemVmxVmFailInvalid(pVCpu);
7811 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7812 return VINF_SUCCESS;
7813 }
7814
7815 /* VMCS-link pointer in non-root mode. */
7816 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7817 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7818 { /* likely */ }
7819 else
7820 {
7821 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7822 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7823 iemVmxVmFailInvalid(pVCpu);
7824 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7825 return VINF_SUCCESS;
7826 }
7827
7828 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7829 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7830 if (!fIsRegOperand)
7831 {
7832 /* Read the value from the specified guest memory location. */
7833 VBOXSTRICTRC rcStrict;
7834 RTGCPTR const GCPtrVal = u64Val;
7835 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7836 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7837 else
7838 {
7839 uint32_t u32Val;
7840 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7841 u64Val = u32Val;
7842 }
7843 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7844 {
7845 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7846 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7847 return rcStrict;
7848 }
7849 }
7850 else
7851 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7852
7853 /* Supported VMCS field. */
7854 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7855 { /* likely */ }
7856 else
7857 {
7858 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7859 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7860 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7861 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7862 return VINF_SUCCESS;
7863 }
7864
7865 /* Read-only VMCS field. */
7866 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
7867 if ( !fIsFieldReadOnly
7868 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7869 { /* likely */ }
7870 else
7871 {
7872 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7873 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7874 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7875 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7876 return VINF_SUCCESS;
7877 }
7878
7879 /*
7880 * Write to the current or shadow VMCS.
7881 */
7882 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7883 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7884 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7885 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7886 Assert(pVmcs);
7887 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7888
7889 /* Notify HM that the VMCS content might have changed. */
7890 if (!fInVmxNonRootMode)
7891 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7892
7893 iemVmxVmSucceed(pVCpu);
7894 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7895 return VINF_SUCCESS;
7896}
7897
7898
7899/**
7900 * VMCLEAR instruction execution worker.
7901 *
7902 * @returns Strict VBox status code.
7903 * @param pVCpu The cross context virtual CPU structure.
7904 * @param cbInstr The instruction length in bytes.
7905 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7906 * @param GCPtrVmcs The linear address of the VMCS pointer.
7907 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7908 *
7909 * @remarks Common VMX instruction checks are already expected to by the caller,
7910 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7911 */
7912IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7913 PCVMXVEXITINFO pExitInfo)
7914{
7915 /* Nested-guest intercept. */
7916 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7917 {
7918 if (pExitInfo)
7919 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7920 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7921 }
7922
7923 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7924
7925 /* CPL. */
7926 if (pVCpu->iem.s.uCpl == 0)
7927 { /* likely */ }
7928 else
7929 {
7930 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7931 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7932 return iemRaiseGeneralProtectionFault0(pVCpu);
7933 }
7934
7935 /* Get the VMCS pointer from the location specified by the source memory operand. */
7936 RTGCPHYS GCPhysVmcs;
7937 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7938 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7939 { /* likely */ }
7940 else
7941 {
7942 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7943 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7944 return rcStrict;
7945 }
7946
7947 /* VMCS pointer alignment. */
7948 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7949 { /* likely */ }
7950 else
7951 {
7952 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7953 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7954 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7955 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7956 return VINF_SUCCESS;
7957 }
7958
7959 /* VMCS physical-address width limits. */
7960 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7961 { /* likely */ }
7962 else
7963 {
7964 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7965 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7966 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7967 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7968 return VINF_SUCCESS;
7969 }
7970
7971 /* VMCS is not the VMXON region. */
7972 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7973 { /* likely */ }
7974 else
7975 {
7976 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7978 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7979 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7980 return VINF_SUCCESS;
7981 }
7982
7983 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7984 restriction imposed by our implementation. */
7985 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7986 { /* likely */ }
7987 else
7988 {
7989 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7990 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7991 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7992 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7993 return VINF_SUCCESS;
7994 }
7995
7996 /*
7997 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7998 *
7999 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8000 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8001 * to 'clear'.
8002 */
8003 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8004 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8005 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8006 {
8007 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8008 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8009 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8010 }
8011 else
8012 {
8013 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8014 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8015 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8016 if (RT_FAILURE(rcStrict))
8017 return rcStrict;
8018 }
8019
8020 iemVmxVmSucceed(pVCpu);
8021 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8022 return VINF_SUCCESS;
8023}
8024
8025
8026/**
8027 * VMPTRST instruction execution worker.
8028 *
8029 * @returns Strict VBox status code.
8030 * @param pVCpu The cross context virtual CPU structure.
8031 * @param cbInstr The instruction length in bytes.
8032 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8033 * @param GCPtrVmcs The linear address of where to store the current VMCS
8034 * pointer.
8035 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8036 *
8037 * @remarks Common VMX instruction checks are already expected to by the caller,
8038 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8039 */
8040IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8041 PCVMXVEXITINFO pExitInfo)
8042{
8043 /* Nested-guest intercept. */
8044 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8045 {
8046 if (pExitInfo)
8047 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8048 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8049 }
8050
8051 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8052
8053 /* CPL. */
8054 if (pVCpu->iem.s.uCpl == 0)
8055 { /* likely */ }
8056 else
8057 {
8058 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8059 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8060 return iemRaiseGeneralProtectionFault0(pVCpu);
8061 }
8062
8063 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8064 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8065 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8066 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8067 {
8068 iemVmxVmSucceed(pVCpu);
8069 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8070 return rcStrict;
8071 }
8072
8073 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8074 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8075 return rcStrict;
8076}
8077
8078
8079/**
8080 * VMPTRLD instruction execution worker.
8081 *
8082 * @returns Strict VBox status code.
8083 * @param pVCpu The cross context virtual CPU structure.
8084 * @param cbInstr The instruction length in bytes.
8085 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8086 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8087 *
8088 * @remarks Common VMX instruction checks are already expected to by the caller,
8089 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8090 */
8091IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8092 PCVMXVEXITINFO pExitInfo)
8093{
8094 /* Nested-guest intercept. */
8095 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8096 {
8097 if (pExitInfo)
8098 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8099 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8100 }
8101
8102 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8103
8104 /* CPL. */
8105 if (pVCpu->iem.s.uCpl == 0)
8106 { /* likely */ }
8107 else
8108 {
8109 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8110 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8111 return iemRaiseGeneralProtectionFault0(pVCpu);
8112 }
8113
8114 /* Get the VMCS pointer from the location specified by the source memory operand. */
8115 RTGCPHYS GCPhysVmcs;
8116 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8117 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8118 { /* likely */ }
8119 else
8120 {
8121 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8122 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8123 return rcStrict;
8124 }
8125
8126 /* VMCS pointer alignment. */
8127 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8128 { /* likely */ }
8129 else
8130 {
8131 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8132 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8133 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8134 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8135 return VINF_SUCCESS;
8136 }
8137
8138 /* VMCS physical-address width limits. */
8139 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8140 { /* likely */ }
8141 else
8142 {
8143 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8144 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8145 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8146 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8147 return VINF_SUCCESS;
8148 }
8149
8150 /* VMCS is not the VMXON region. */
8151 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8152 { /* likely */ }
8153 else
8154 {
8155 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8157 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8158 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8159 return VINF_SUCCESS;
8160 }
8161
8162 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8163 restriction imposed by our implementation. */
8164 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8165 { /* likely */ }
8166 else
8167 {
8168 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8170 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173 }
8174
8175 /* Read just the VMCS revision from the VMCS. */
8176 VMXVMCSREVID VmcsRevId;
8177 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8178 if (RT_SUCCESS(rc))
8179 { /* likely */ }
8180 else
8181 {
8182 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8183 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8184 return rc;
8185 }
8186
8187 /*
8188 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8189 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8190 */
8191 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8192 && ( !VmcsRevId.n.fIsShadowVmcs
8193 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8194 { /* likely */ }
8195 else
8196 {
8197 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8198 {
8199 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8200 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8201 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8202 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8203 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8204 return VINF_SUCCESS;
8205 }
8206
8207 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8209 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8210 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8211 return VINF_SUCCESS;
8212 }
8213
8214 /*
8215 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8216 * the cache of an existing, current VMCS back to guest memory before loading a new,
8217 * different current VMCS.
8218 */
8219 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8220 {
8221 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8222 {
8223 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8224 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8225 }
8226
8227 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8228 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8229 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8230 if (RT_SUCCESS(rc))
8231 {
8232 /* Notify HM that a new, current VMCS is loaded. */
8233 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8234 }
8235 else
8236 {
8237 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8238 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8239 return rc;
8240 }
8241 }
8242
8243 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8244 iemVmxVmSucceed(pVCpu);
8245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8246 return VINF_SUCCESS;
8247}
8248
8249
8250/**
8251 * INVVPID instruction execution worker.
8252 *
8253 * @returns Strict VBox status code.
8254 * @param pVCpu The cross context virtual CPU structure.
8255 * @param cbInstr The instruction length in bytes.
8256 * @param iEffSeg The segment of the invvpid descriptor.
8257 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8258 * @param u64InvvpidType The invalidation type.
8259 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8260 * NULL.
8261 *
8262 * @remarks Common VMX instruction checks are already expected to by the caller,
8263 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8264 */
8265IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8266 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8267{
8268 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8269 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8270 return iemRaiseUndefinedOpcode(pVCpu);
8271
8272 /* Nested-guest intercept. */
8273 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8274 {
8275 if (pExitInfo)
8276 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8277 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8278 }
8279
8280 /* CPL. */
8281 if (pVCpu->iem.s.uCpl != 0)
8282 {
8283 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8284 return iemRaiseGeneralProtectionFault0(pVCpu);
8285 }
8286
8287 /*
8288 * Validate INVVPID invalidation type.
8289 *
8290 * The instruction specifies exactly ONE of the supported invalidation types.
8291 *
8292 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8293 * supported. In theory, it's possible for a CPU to not support flushing individual
8294 * addresses but all the other types or any other combination. We do not take any
8295 * shortcuts here by assuming the types we currently expose to the guest.
8296 */
8297 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8298 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8299 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8300 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8301 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8302 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8303 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8304 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8305 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8306 { /* likely */ }
8307 else
8308 {
8309 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8311 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8312 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8313 return VINF_SUCCESS;
8314 }
8315
8316 /*
8317 * Fetch the invvpid descriptor from guest memory.
8318 */
8319 RTUINT128U uDesc;
8320 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8321 if (rcStrict == VINF_SUCCESS)
8322 {
8323 /*
8324 * Validate the descriptor.
8325 */
8326 if (uDesc.s.Lo > 0xfff)
8327 {
8328 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8329 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8330 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8331 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8332 return VINF_SUCCESS;
8333 }
8334
8335 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8336 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8337 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8338 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8339 switch (u64InvvpidType)
8340 {
8341 case VMXTLBFLUSHVPID_INDIV_ADDR:
8342 {
8343 if (uVpid != 0)
8344 {
8345 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8346 {
8347 /* Invalidate mappings for the linear address tagged with VPID. */
8348 /** @todo PGM support for VPID? Currently just flush everything. */
8349 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8350 iemVmxVmSucceed(pVCpu);
8351 }
8352 else
8353 {
8354 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8355 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8356 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8357 }
8358 }
8359 else
8360 {
8361 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8362 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8363 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8364 }
8365 break;
8366 }
8367
8368 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8369 {
8370 if (uVpid != 0)
8371 {
8372 /* Invalidate all mappings with VPID. */
8373 /** @todo PGM support for VPID? Currently just flush everything. */
8374 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8375 iemVmxVmSucceed(pVCpu);
8376 }
8377 else
8378 {
8379 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8380 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8381 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8382 }
8383 break;
8384 }
8385
8386 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8387 {
8388 /* Invalidate all mappings with non-zero VPIDs. */
8389 /** @todo PGM support for VPID? Currently just flush everything. */
8390 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8391 iemVmxVmSucceed(pVCpu);
8392 break;
8393 }
8394
8395 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8396 {
8397 if (uVpid != 0)
8398 {
8399 /* Invalidate all mappings with VPID except global translations. */
8400 /** @todo PGM support for VPID? Currently just flush everything. */
8401 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8402 iemVmxVmSucceed(pVCpu);
8403 }
8404 else
8405 {
8406 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8407 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8408 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8409 }
8410 break;
8411 }
8412 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8413 }
8414 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8415 }
8416 return rcStrict;
8417}
8418
8419
8420/**
8421 * VMXON instruction execution worker.
8422 *
8423 * @returns Strict VBox status code.
8424 * @param pVCpu The cross context virtual CPU structure.
8425 * @param cbInstr The instruction length in bytes.
8426 * @param iEffSeg The effective segment register to use with @a
8427 * GCPtrVmxon.
8428 * @param GCPtrVmxon The linear address of the VMXON pointer.
8429 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8430 *
8431 * @remarks Common VMX instruction checks are already expected to by the caller,
8432 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8433 */
8434IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8435 PCVMXVEXITINFO pExitInfo)
8436{
8437 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8438 {
8439 /* CPL. */
8440 if (pVCpu->iem.s.uCpl == 0)
8441 { /* likely */ }
8442 else
8443 {
8444 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8445 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8446 return iemRaiseGeneralProtectionFault0(pVCpu);
8447 }
8448
8449 /* A20M (A20 Masked) mode. */
8450 if (PGMPhysIsA20Enabled(pVCpu))
8451 { /* likely */ }
8452 else
8453 {
8454 Log(("vmxon: A20M mode -> #GP(0)\n"));
8455 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8456 return iemRaiseGeneralProtectionFault0(pVCpu);
8457 }
8458
8459 /* CR0. */
8460 {
8461 /* CR0 MB1 bits. */
8462 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8463 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8464 { /* likely */ }
8465 else
8466 {
8467 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8469 return iemRaiseGeneralProtectionFault0(pVCpu);
8470 }
8471
8472 /* CR0 MBZ bits. */
8473 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8474 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8475 { /* likely */ }
8476 else
8477 {
8478 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8480 return iemRaiseGeneralProtectionFault0(pVCpu);
8481 }
8482 }
8483
8484 /* CR4. */
8485 {
8486 /* CR4 MB1 bits. */
8487 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8488 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8489 { /* likely */ }
8490 else
8491 {
8492 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8493 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8494 return iemRaiseGeneralProtectionFault0(pVCpu);
8495 }
8496
8497 /* CR4 MBZ bits. */
8498 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8499 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8500 { /* likely */ }
8501 else
8502 {
8503 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8505 return iemRaiseGeneralProtectionFault0(pVCpu);
8506 }
8507 }
8508
8509 /* Feature control MSR's LOCK and VMXON bits. */
8510 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8511 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8512 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8513 { /* likely */ }
8514 else
8515 {
8516 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8518 return iemRaiseGeneralProtectionFault0(pVCpu);
8519 }
8520
8521 /* Get the VMXON pointer from the location specified by the source memory operand. */
8522 RTGCPHYS GCPhysVmxon;
8523 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8524 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8525 { /* likely */ }
8526 else
8527 {
8528 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8529 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8530 return rcStrict;
8531 }
8532
8533 /* VMXON region pointer alignment. */
8534 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8535 { /* likely */ }
8536 else
8537 {
8538 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8539 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8540 iemVmxVmFailInvalid(pVCpu);
8541 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8542 return VINF_SUCCESS;
8543 }
8544
8545 /* VMXON physical-address width limits. */
8546 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8547 { /* likely */ }
8548 else
8549 {
8550 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8552 iemVmxVmFailInvalid(pVCpu);
8553 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8554 return VINF_SUCCESS;
8555 }
8556
8557 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8558 restriction imposed by our implementation. */
8559 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8560 { /* likely */ }
8561 else
8562 {
8563 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8564 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8565 iemVmxVmFailInvalid(pVCpu);
8566 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8567 return VINF_SUCCESS;
8568 }
8569
8570 /* Read the VMCS revision ID from the VMXON region. */
8571 VMXVMCSREVID VmcsRevId;
8572 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8573 if (RT_SUCCESS(rc))
8574 { /* likely */ }
8575 else
8576 {
8577 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8578 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8579 return rc;
8580 }
8581
8582 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8583 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8584 { /* likely */ }
8585 else
8586 {
8587 /* Revision ID mismatch. */
8588 if (!VmcsRevId.n.fIsShadowVmcs)
8589 {
8590 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8591 VmcsRevId.n.u31RevisionId));
8592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8593 iemVmxVmFailInvalid(pVCpu);
8594 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8595 return VINF_SUCCESS;
8596 }
8597
8598 /* Shadow VMCS disallowed. */
8599 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8600 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8601 iemVmxVmFailInvalid(pVCpu);
8602 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8603 return VINF_SUCCESS;
8604 }
8605
8606 /*
8607 * Record that we're in VMX operation, block INIT, block and disable A20M.
8608 */
8609 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8610 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8612
8613 /* Clear address-range monitoring. */
8614 EMMonitorWaitClear(pVCpu);
8615 /** @todo NSTVMX: Intel PT. */
8616
8617 iemVmxVmSucceed(pVCpu);
8618 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8619 return VINF_SUCCESS;
8620 }
8621 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8622 {
8623 /* Nested-guest intercept. */
8624 if (pExitInfo)
8625 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8626 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8627 }
8628
8629 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8630
8631 /* CPL. */
8632 if (pVCpu->iem.s.uCpl > 0)
8633 {
8634 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8635 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8636 return iemRaiseGeneralProtectionFault0(pVCpu);
8637 }
8638
8639 /* VMXON when already in VMX root mode. */
8640 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8641 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8642 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8643 return VINF_SUCCESS;
8644}
8645
8646
8647/**
8648 * Implements 'VMXOFF'.
8649 *
8650 * @remarks Common VMX instruction checks are already expected to by the caller,
8651 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8652 */
8653IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8654{
8655 /* Nested-guest intercept. */
8656 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8657 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8658
8659 /* CPL. */
8660 if (pVCpu->iem.s.uCpl == 0)
8661 { /* likely */ }
8662 else
8663 {
8664 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8665 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8666 return iemRaiseGeneralProtectionFault0(pVCpu);
8667 }
8668
8669 /* Dual monitor treatment of SMIs and SMM. */
8670 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8671 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8672 { /* likely */ }
8673 else
8674 {
8675 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8676 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8677 return VINF_SUCCESS;
8678 }
8679
8680 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8681 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8682 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8683
8684 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8685 { /** @todo NSTVMX: Unblock SMI. */ }
8686
8687 EMMonitorWaitClear(pVCpu);
8688 /** @todo NSTVMX: Unblock and enable A20M. */
8689
8690 iemVmxVmSucceed(pVCpu);
8691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8692 return VINF_SUCCESS;
8693}
8694
8695
8696/**
8697 * Implements 'VMXON'.
8698 */
8699IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8700{
8701 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8702}
8703
8704
8705/**
8706 * Implements 'VMLAUNCH'.
8707 */
8708IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8709{
8710 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8711}
8712
8713
8714/**
8715 * Implements 'VMRESUME'.
8716 */
8717IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8718{
8719 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8720}
8721
8722
8723/**
8724 * Implements 'VMPTRLD'.
8725 */
8726IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8727{
8728 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8729}
8730
8731
8732/**
8733 * Implements 'VMPTRST'.
8734 */
8735IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8736{
8737 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8738}
8739
8740
8741/**
8742 * Implements 'VMCLEAR'.
8743 */
8744IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8745{
8746 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8747}
8748
8749
8750/**
8751 * Implements 'VMWRITE' register.
8752 */
8753IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8754{
8755 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8756}
8757
8758
8759/**
8760 * Implements 'VMWRITE' memory.
8761 */
8762IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8763{
8764 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8765}
8766
8767
8768/**
8769 * Implements 'VMREAD' register (64-bit).
8770 */
8771IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8772{
8773 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8774}
8775
8776
8777/**
8778 * Implements 'VMREAD' register (32-bit).
8779 */
8780IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8781{
8782 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8783}
8784
8785
8786/**
8787 * Implements 'VMREAD' memory, 64-bit register.
8788 */
8789IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8790{
8791 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8792}
8793
8794
8795/**
8796 * Implements 'VMREAD' memory, 32-bit register.
8797 */
8798IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8799{
8800 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8801}
8802
8803
8804/**
8805 * Implements 'INVVPID'.
8806 */
8807IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8808{
8809 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8810}
8811
8812
8813/**
8814 * Implements VMX's implementation of PAUSE.
8815 */
8816IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8817{
8818 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8819 {
8820 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8821 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8822 return rcStrict;
8823 }
8824
8825 /*
8826 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8827 * a VM-exit, the instruction operates normally.
8828 */
8829 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8830 return VINF_SUCCESS;
8831}
8832
8833#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8834
8835
8836/**
8837 * Implements 'VMCALL'.
8838 */
8839IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8840{
8841#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8842 /* Nested-guest intercept. */
8843 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8844 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8845#endif
8846
8847 /* Join forces with vmmcall. */
8848 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8849}
8850
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