VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 79600

Last change on this file since 79600 was 79600, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 Caller provides all necessary valid info. for iemVmxVmexitTaskSwitchWithInfo. Assertions.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 79600 2019-07-08 16:11:15Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Implements VMSucceed for VMX instruction success.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 */
788DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
789{
790 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
791}
792
793
794/**
795 * Implements VMFailInvalid for VMX instruction failure.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
800{
801 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
802}
803
804
805/**
806 * Implements VMFail for VMX instruction failure.
807 *
808 * @param pVCpu The cross context virtual CPU structure.
809 * @param enmInsErr The VM instruction error.
810 */
811DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
812{
813 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
814}
815
816
817/**
818 * Checks if the given auto-load/store MSR area count is valid for the
819 * implementation.
820 *
821 * @returns @c true if it's within the valid limit, @c false otherwise.
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param uMsrCount The MSR area count to check.
824 */
825DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
826{
827 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
828 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
829 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
830 if (uMsrCount <= cMaxSupportedMsrs)
831 return true;
832 return false;
833}
834
835
836/**
837 * Flushes the current VMCS contents back to guest memory.
838 *
839 * @returns VBox status code.
840 * @param pVCpu The cross context virtual CPU structure.
841 */
842DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPU pVCpu)
843{
844 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
845 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
846 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
847 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
848 return rc;
849}
850
851
852/**
853 * Populates the current VMCS contents from guest memory.
854 *
855 * @returns VBox status code.
856 * @param pVCpu The cross context virtual CPU structure.
857 */
858DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPU pVCpu)
859{
860 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
861 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
862 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
863 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
864 return rc;
865}
866
867
868/**
869 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
870 *
871 * @param pVCpu The cross context virtual CPU structure.
872 */
873DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
874{
875 iemVmxVmSucceed(pVCpu);
876 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
877}
878
879
880/**
881 * Gets the instruction diagnostic for segment base checks during VM-entry of a
882 * nested-guest.
883 *
884 * @param iSegReg The segment index (X86_SREG_XXX).
885 */
886IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
887{
888 switch (iSegReg)
889 {
890 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
891 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
892 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
893 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
894 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
895 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
896 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
897 }
898}
899
900
901/**
902 * Gets the instruction diagnostic for segment base checks during VM-entry of a
903 * nested-guest that is in Virtual-8086 mode.
904 *
905 * @param iSegReg The segment index (X86_SREG_XXX).
906 */
907IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
908{
909 switch (iSegReg)
910 {
911 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
912 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
913 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
914 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
915 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
916 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
917 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
918 }
919}
920
921
922/**
923 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
924 * nested-guest that is in Virtual-8086 mode.
925 *
926 * @param iSegReg The segment index (X86_SREG_XXX).
927 */
928IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
929{
930 switch (iSegReg)
931 {
932 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
933 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
934 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
935 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
936 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
937 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
938 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
939 }
940}
941
942
943/**
944 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
945 * nested-guest that is in Virtual-8086 mode.
946 *
947 * @param iSegReg The segment index (X86_SREG_XXX).
948 */
949IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
950{
951 switch (iSegReg)
952 {
953 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
954 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
955 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
956 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
957 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
958 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
959 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
960 }
961}
962
963
964/**
965 * Gets the instruction diagnostic for segment attributes reserved bits failure
966 * during VM-entry of a nested-guest.
967 *
968 * @param iSegReg The segment index (X86_SREG_XXX).
969 */
970IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
971{
972 switch (iSegReg)
973 {
974 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
975 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
976 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
977 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
978 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
979 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
980 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
981 }
982}
983
984
985/**
986 * Gets the instruction diagnostic for segment attributes descriptor-type
987 * (code/segment or system) failure during VM-entry of a nested-guest.
988 *
989 * @param iSegReg The segment index (X86_SREG_XXX).
990 */
991IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
992{
993 switch (iSegReg)
994 {
995 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
996 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
997 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
998 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
999 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1000 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1001 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1002 }
1003}
1004
1005
1006/**
1007 * Gets the instruction diagnostic for segment attributes descriptor-type
1008 * (code/segment or system) failure during VM-entry of a nested-guest.
1009 *
1010 * @param iSegReg The segment index (X86_SREG_XXX).
1011 */
1012IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1013{
1014 switch (iSegReg)
1015 {
1016 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1017 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1018 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1019 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1020 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1021 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1022 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1023 }
1024}
1025
1026
1027/**
1028 * Gets the instruction diagnostic for segment attribute granularity failure during
1029 * VM-entry of a nested-guest.
1030 *
1031 * @param iSegReg The segment index (X86_SREG_XXX).
1032 */
1033IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1034{
1035 switch (iSegReg)
1036 {
1037 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1038 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1039 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1040 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1041 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1042 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1043 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1044 }
1045}
1046
1047/**
1048 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1049 * VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attribute type accessed failure
1070 * during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1091 * failure during VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The PDPTE entry index.
1094 */
1095IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1096{
1097 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1098 switch (iPdpte)
1099 {
1100 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1101 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1102 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1103 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1104 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1105 }
1106}
1107
1108
1109/**
1110 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1111 * failure during VM-exit of a nested-guest.
1112 *
1113 * @param iSegReg The PDPTE entry index.
1114 */
1115IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1116{
1117 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1118 switch (iPdpte)
1119 {
1120 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1121 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1122 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1123 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1124 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1125 }
1126}
1127
1128
1129/**
1130 * Saves the guest control registers, debug registers and some MSRs are part of
1131 * VM-exit.
1132 *
1133 * @param pVCpu The cross context virtual CPU structure.
1134 */
1135IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1136{
1137 /*
1138 * Saves the guest control registers, debug registers and some MSRs.
1139 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1140 */
1141 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1142
1143 /* Save control registers. */
1144 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1145 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1146 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1147
1148 /* Save SYSENTER CS, ESP, EIP. */
1149 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1150 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1151 {
1152 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1153 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1154 }
1155 else
1156 {
1157 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1158 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1159 }
1160
1161 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1162 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1163 {
1164 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1165 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1166 }
1167
1168 /* Save PAT MSR. */
1169 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1170 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1171
1172 /* Save EFER MSR. */
1173 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1174 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1175
1176 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1177 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1178
1179 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1180}
1181
1182
1183/**
1184 * Saves the guest force-flags in preparation of entering the nested-guest.
1185 *
1186 * @param pVCpu The cross context virtual CPU structure.
1187 */
1188IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1189{
1190 /* We shouldn't be called multiple times during VM-entry. */
1191 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1192
1193 /* MTF should not be set outside VMX non-root mode. */
1194 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1195
1196 /*
1197 * Preserve the required force-flags.
1198 *
1199 * We cache and clear force-flags that would affect the execution of the
1200 * nested-guest. Cached flags are then restored while returning to the guest
1201 * if necessary.
1202 *
1203 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1204 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1205 * instruction. Interrupt inhibition for any nested-guest instruction
1206 * is supplied by the guest-interruptibility state VMCS field and will
1207 * be set up as part of loading the guest state.
1208 *
1209 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1210 * successful VM-entry (due to invalid guest-state) need to continue
1211 * blocking NMIs if it was in effect before VM-entry.
1212 *
1213 * - MTF need not be preserved as it's used only in VMX non-root mode and
1214 * is supplied through the VM-execution controls.
1215 *
1216 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1217 * we will be able to generate interrupts that may cause VM-exits for
1218 * the nested-guest.
1219 */
1220 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1221}
1222
1223
1224/**
1225 * Restores the guest force-flags in preparation of exiting the nested-guest.
1226 *
1227 * @param pVCpu The cross context virtual CPU structure.
1228 */
1229IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1230{
1231 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1232 {
1233 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1235 }
1236}
1237
1238
1239/**
1240 * Perform a VMX transition updated PGM, IEM and CPUM.
1241 *
1242 * @param pVCpu The cross context virtual CPU structure.
1243 */
1244IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1245{
1246 /*
1247 * Inform PGM about paging mode changes.
1248 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1249 * see comment in iemMemPageTranslateAndCheckAccess().
1250 */
1251 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1252# ifdef IN_RING3
1253 Assert(rc != VINF_PGM_CHANGE_MODE);
1254# endif
1255 AssertRCReturn(rc, rc);
1256
1257 /* Inform CPUM (recompiler), can later be removed. */
1258 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1259
1260 /*
1261 * Flush the TLB with new CR3. This is required in case the PGM mode change
1262 * above doesn't actually change anything.
1263 */
1264 if (rc == VINF_SUCCESS)
1265 {
1266 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1267 AssertRCReturn(rc, rc);
1268 }
1269
1270 /* Re-initialize IEM cache/state after the drastic mode switch. */
1271 iemReInitExec(pVCpu);
1272 return rc;
1273}
1274
1275
1276/**
1277 * Calculates the current VMX-preemption timer value.
1278 *
1279 * @returns The current VMX-preemption timer value.
1280 * @param pVCpu The cross context virtual CPU structure.
1281 */
1282IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1283{
1284 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1285 Assert(pVmcs);
1286
1287 /*
1288 * Assume the following:
1289 * PreemptTimerShift = 5
1290 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1291 * EntryTick = 50000 (TSC at time of VM-entry)
1292 *
1293 * CurTick Delta PreemptTimerVal
1294 * ----------------------------------
1295 * 60000 10000 2
1296 * 80000 30000 1
1297 * 90000 40000 0 -> VM-exit.
1298 *
1299 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1300 * The saved VMX-preemption timer value is calculated as follows:
1301 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1302 * E.g.:
1303 * Delta = 10000
1304 * Tmp = 10000 / (2 * 10000) = 0.5
1305 * NewPt = 2 - 0.5 = 2
1306 * Delta = 30000
1307 * Tmp = 30000 / (2 * 10000) = 1.5
1308 * NewPt = 2 - 1.5 = 1
1309 * Delta = 40000
1310 * Tmp = 40000 / 20000 = 2
1311 * NewPt = 2 - 2 = 0
1312 */
1313 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1314 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1315 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1316 uint64_t const uDelta = uCurTick - uEntryTick;
1317 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1318 uint32_t const uPreemptTimer = uVmcsPreemptVal
1319 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1320 return uPreemptTimer;
1321}
1322
1323
1324/**
1325 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1326 *
1327 * @param pVCpu The cross context virtual CPU structure.
1328 */
1329IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1330{
1331 /*
1332 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1333 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1334 */
1335 /* CS, SS, ES, DS, FS, GS. */
1336 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1337 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1338 {
1339 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1340 if (!pSelReg->Attr.n.u1Unusable)
1341 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1342 else
1343 {
1344 /*
1345 * For unusable segments the attributes are undefined except for CS and SS.
1346 * For the rest we don't bother preserving anything but the unusable bit.
1347 */
1348 switch (iSegReg)
1349 {
1350 case X86_SREG_CS:
1351 pVmcs->GuestCs = pSelReg->Sel;
1352 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1353 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1354 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1355 | X86DESCATTR_UNUSABLE);
1356 break;
1357
1358 case X86_SREG_SS:
1359 pVmcs->GuestSs = pSelReg->Sel;
1360 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1361 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1362 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1363 break;
1364
1365 case X86_SREG_DS:
1366 pVmcs->GuestDs = pSelReg->Sel;
1367 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1368 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1369 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1370 break;
1371
1372 case X86_SREG_ES:
1373 pVmcs->GuestEs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1377 break;
1378
1379 case X86_SREG_FS:
1380 pVmcs->GuestFs = pSelReg->Sel;
1381 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1382 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1383 break;
1384
1385 case X86_SREG_GS:
1386 pVmcs->GuestGs = pSelReg->Sel;
1387 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1388 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1389 break;
1390 }
1391 }
1392 }
1393
1394 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1395 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1396 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1397 | X86DESCATTR_UNUSABLE;
1398 /* LDTR. */
1399 {
1400 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1401 pVmcs->GuestLdtr = pSelReg->Sel;
1402 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1403 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1404 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1405 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1406 }
1407
1408 /* TR. */
1409 {
1410 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1411 pVmcs->GuestTr = pSelReg->Sel;
1412 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1413 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1414 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1415 }
1416
1417 /* GDTR. */
1418 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1419 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1420
1421 /* IDTR. */
1422 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1423 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1424}
1425
1426
1427/**
1428 * Saves guest non-register state as part of VM-exit.
1429 *
1430 * @param pVCpu The cross context virtual CPU structure.
1431 * @param uExitReason The VM-exit reason.
1432 */
1433IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1434{
1435 /*
1436 * Save guest non-register state.
1437 * See Intel spec. 27.3.4 "Saving Non-Register State".
1438 */
1439 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1440
1441 /*
1442 * Activity state.
1443 * Most VM-exits will occur in the active state. However, if the first instruction
1444 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1445 * the VM-exit will be from the HLT activity state.
1446 *
1447 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1448 */
1449 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1450 * not? */
1451 EMSTATE const enmActivityState = EMGetState(pVCpu);
1452 switch (enmActivityState)
1453 {
1454 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1455 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1456 }
1457
1458 /*
1459 * Interruptibility-state.
1460 */
1461 /* NMI. */
1462 pVmcs->u32GuestIntrState = 0;
1463 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1464 {
1465 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1466 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1467 }
1468 else
1469 {
1470 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1471 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1472 }
1473
1474 /* Blocking-by-STI. */
1475 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1476 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1477 {
1478 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1479 * currently. */
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1481 }
1482 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1483
1484 /*
1485 * Pending debug exceptions.
1486 */
1487 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1488 && uExitReason != VMX_EXIT_SMI
1489 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1490 && !HMVmxIsVmexitTrapLike(uExitReason))
1491 {
1492 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1493 * block-by-MovSS is in effect. */
1494 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1495 }
1496 else
1497 {
1498 /*
1499 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1500 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1501 *
1502 * See Intel spec. 24.4.2 "Guest Non-Register State".
1503 */
1504 /** @todo r=ramshankar: NSTVMX: I'm not quite sure if we can simply derive this from
1505 * DR6. */
1506 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1507 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1508 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1509 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1510 if (fPendingDbgMask & fBpHitMask)
1511 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1512 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1513 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1514 }
1515
1516 /*
1517 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1518 *
1519 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1520 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1521 */
1522 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1523 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1524 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1525
1526 /* PDPTEs. */
1527 /* We don't support EPT yet. */
1528 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1529 pVmcs->u64GuestPdpte0.u = 0;
1530 pVmcs->u64GuestPdpte1.u = 0;
1531 pVmcs->u64GuestPdpte2.u = 0;
1532 pVmcs->u64GuestPdpte3.u = 0;
1533}
1534
1535
1536/**
1537 * Saves the guest-state as part of VM-exit.
1538 *
1539 * @returns VBox status code.
1540 * @param pVCpu The cross context virtual CPU structure.
1541 * @param uExitReason The VM-exit reason.
1542 */
1543IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1544{
1545 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1546 Assert(pVmcs);
1547
1548 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1549 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1550
1551 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1552 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1553 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1554
1555 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1556}
1557
1558
1559/**
1560 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1561 *
1562 * @returns VBox status code.
1563 * @param pVCpu The cross context virtual CPU structure.
1564 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1565 */
1566IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1567{
1568 /*
1569 * Save guest MSRs.
1570 * See Intel spec. 27.4 "Saving MSRs".
1571 */
1572 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1573 const char *const pszFailure = "VMX-abort";
1574
1575 /*
1576 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1577 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1578 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1579 */
1580 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1581 if (!cMsrs)
1582 return VINF_SUCCESS;
1583
1584 /*
1585 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1586 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1587 * implementation causes a VMX-abort followed by a triple-fault.
1588 */
1589 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1590 if (fIsMsrCountValid)
1591 { /* likely */ }
1592 else
1593 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1594
1595 /*
1596 * Optimization if the guest hypervisor is using the same guest-physical page for both
1597 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1598 */
1599 PVMXAUTOMSR pMsrArea;
1600 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1601 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1602 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1603 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1604 else
1605 {
1606 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1607 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1608 if (RT_SUCCESS(rc))
1609 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1610 else
1611 {
1612 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1613 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1614 }
1615 }
1616
1617 /*
1618 * Update VM-exit MSR store area.
1619 */
1620 PVMXAUTOMSR pMsr = pMsrArea;
1621 Assert(pMsr);
1622 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1623 {
1624 if ( !pMsr->u32Reserved
1625 && pMsr->u32Msr != MSR_IA32_SMBASE
1626 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1627 {
1628 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1629 if (rcStrict == VINF_SUCCESS)
1630 continue;
1631
1632 /*
1633 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1634 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1635 * recording the MSR index in the auxiliary info. field and indicated further by our
1636 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1637 * if possible, or come up with a better, generic solution.
1638 */
1639 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1640 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1641 ? kVmxVDiag_Vmexit_MsrStoreRing3
1642 : kVmxVDiag_Vmexit_MsrStore;
1643 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1644 }
1645 else
1646 {
1647 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1649 }
1650 }
1651
1652 /*
1653 * Commit the VM-exit MSR store are to guest memory.
1654 */
1655 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1656 if (RT_SUCCESS(rc))
1657 return VINF_SUCCESS;
1658
1659 NOREF(uExitReason);
1660 NOREF(pszFailure);
1661
1662 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1663 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1664}
1665
1666
1667/**
1668 * Performs a VMX abort (due to an fatal error during VM-exit).
1669 *
1670 * @returns Strict VBox status code.
1671 * @param pVCpu The cross context virtual CPU structure.
1672 * @param enmAbort The VMX abort reason.
1673 */
1674IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1675{
1676 /*
1677 * Perform the VMX abort.
1678 * See Intel spec. 27.7 "VMX Aborts".
1679 */
1680 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
1681
1682 /* We don't support SMX yet. */
1683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1684 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1685 {
1686 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1687 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1688 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1689 }
1690
1691 return VINF_EM_TRIPLE_FAULT;
1692}
1693
1694
1695/**
1696 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1697 *
1698 * @param pVCpu The cross context virtual CPU structure.
1699 */
1700IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
1701{
1702 /*
1703 * Load host control registers, debug registers and MSRs.
1704 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1705 */
1706 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1707 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1708
1709 /* CR0. */
1710 {
1711 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1712 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1713 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1714 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1715 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1716 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1717 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1718 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1719 }
1720
1721 /* CR4. */
1722 {
1723 /* Fixed CR4 bits are not modified. */
1724 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1725 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1726 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1727 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1728 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1729 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1730 if (fHostInLongMode)
1731 uValidHostCr4 |= X86_CR4_PAE;
1732 else
1733 uValidHostCr4 &= ~X86_CR4_PCIDE;
1734 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1735 }
1736
1737 /* CR3 (host value validated while checking host-state during VM-entry). */
1738 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1739
1740 /* DR7. */
1741 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1742
1743 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1744
1745 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1746 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1747 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1748 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1749
1750 /* FS, GS bases are loaded later while we load host segment registers. */
1751
1752 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1753 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1754 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1755 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1756 {
1757 if (fHostInLongMode)
1758 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 else
1760 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1761 }
1762
1763 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1764
1765 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1766 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1767 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1768
1769 /* We don't support IA32_BNDCFGS MSR yet. */
1770}
1771
1772
1773/**
1774 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1775 *
1776 * @param pVCpu The cross context virtual CPU structure.
1777 */
1778IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
1779{
1780 /*
1781 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1782 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1783 *
1784 * Warning! Be careful to not touch fields that are reserved by VT-x,
1785 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1786 */
1787 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1788 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1789
1790 /* CS, SS, ES, DS, FS, GS. */
1791 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1792 {
1793 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1794 bool const fUnusable = RT_BOOL(HostSel == 0);
1795 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1796
1797 /* Selector. */
1798 pSelReg->Sel = HostSel;
1799 pSelReg->ValidSel = HostSel;
1800 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1801
1802 /* Limit. */
1803 pSelReg->u32Limit = 0xffffffff;
1804
1805 /* Base. */
1806 pSelReg->u64Base = 0;
1807
1808 /* Attributes. */
1809 if (iSegReg == X86_SREG_CS)
1810 {
1811 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1812 pSelReg->Attr.n.u1DescType = 1;
1813 pSelReg->Attr.n.u2Dpl = 0;
1814 pSelReg->Attr.n.u1Present = 1;
1815 pSelReg->Attr.n.u1Long = fHostInLongMode;
1816 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1817 pSelReg->Attr.n.u1Granularity = 1;
1818 Assert(!pSelReg->Attr.n.u1Unusable);
1819 Assert(!fUnusable);
1820 }
1821 else
1822 {
1823 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1824 pSelReg->Attr.n.u1DescType = 1;
1825 pSelReg->Attr.n.u2Dpl = 0;
1826 pSelReg->Attr.n.u1Present = 1;
1827 pSelReg->Attr.n.u1DefBig = 1;
1828 pSelReg->Attr.n.u1Granularity = 1;
1829 pSelReg->Attr.n.u1Unusable = fUnusable;
1830 }
1831 }
1832
1833 /* FS base. */
1834 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1835 || fHostInLongMode)
1836 {
1837 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1838 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1839 }
1840
1841 /* GS base. */
1842 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1843 || fHostInLongMode)
1844 {
1845 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1846 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1847 }
1848
1849 /* TR. */
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1851 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1852 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1853 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1854 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1855 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1856 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1861 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1862 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1863
1864 /* LDTR (Warning! do not touch the base and limits here). */
1865 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1866 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1867 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1868 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1869
1870 /* GDTR. */
1871 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1872 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1873 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1874
1875 /* IDTR.*/
1876 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1877 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1878 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1879}
1880
1881
1882/**
1883 * Checks host PDPTes as part of VM-exit.
1884 *
1885 * @param pVCpu The cross context virtual CPU structure.
1886 * @param uExitReason The VM-exit reason (for logging purposes).
1887 */
1888IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
1889{
1890 /*
1891 * Check host PDPTEs.
1892 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1893 */
1894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1895 const char *const pszFailure = "VMX-abort";
1896 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1897
1898 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1899 && !fHostInLongMode)
1900 {
1901 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1902 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1903 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1904 if (RT_SUCCESS(rc))
1905 {
1906 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1907 {
1908 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1909 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1910 { /* likely */ }
1911 else
1912 {
1913 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1914 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1915 }
1916 }
1917 }
1918 else
1919 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1920 }
1921
1922 NOREF(pszFailure);
1923 NOREF(uExitReason);
1924 return VINF_SUCCESS;
1925}
1926
1927
1928/**
1929 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1930 *
1931 * @returns VBox status code.
1932 * @param pVCpu The cross context virtual CPU structure.
1933 * @param pszInstr The VMX instruction name (for logging purposes).
1934 */
1935IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1936{
1937 /*
1938 * Load host MSRs.
1939 * See Intel spec. 27.6 "Loading MSRs".
1940 */
1941 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1942 const char *const pszFailure = "VMX-abort";
1943
1944 /*
1945 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1946 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1947 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1948 */
1949 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1950 if (!cMsrs)
1951 return VINF_SUCCESS;
1952
1953 /*
1954 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1955 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1956 * implementation causes a VMX-abort followed by a triple-fault.
1957 */
1958 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1959 if (fIsMsrCountValid)
1960 { /* likely */ }
1961 else
1962 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1963
1964 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1965 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1966 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1967 if (RT_SUCCESS(rc))
1968 {
1969 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1970 Assert(pMsr);
1971 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1972 {
1973 if ( !pMsr->u32Reserved
1974 && pMsr->u32Msr != MSR_K8_FS_BASE
1975 && pMsr->u32Msr != MSR_K8_GS_BASE
1976 && pMsr->u32Msr != MSR_K6_EFER
1977 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1978 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1979 {
1980 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1981 if (rcStrict == VINF_SUCCESS)
1982 continue;
1983
1984 /*
1985 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1986 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1987 * recording the MSR index in the auxiliary info. field and indicated further by our
1988 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1989 * if possible, or come up with a better, generic solution.
1990 */
1991 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1992 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1993 ? kVmxVDiag_Vmexit_MsrLoadRing3
1994 : kVmxVDiag_Vmexit_MsrLoad;
1995 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1996 }
1997 else
1998 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1999 }
2000 }
2001 else
2002 {
2003 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2005 }
2006
2007 NOREF(uExitReason);
2008 NOREF(pszFailure);
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/**
2014 * Loads the host state as part of VM-exit.
2015 *
2016 * @returns Strict VBox status code.
2017 * @param pVCpu The cross context virtual CPU structure.
2018 * @param uExitReason The VM-exit reason (for logging purposes).
2019 */
2020IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2021{
2022 /*
2023 * Load host state.
2024 * See Intel spec. 27.5 "Loading Host State".
2025 */
2026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2027 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2028
2029 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2030 if ( CPUMIsGuestInLongMode(pVCpu)
2031 && !fHostInLongMode)
2032 {
2033 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2034 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2035 }
2036
2037 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2038 iemVmxVmexitLoadHostSegRegs(pVCpu);
2039
2040 /*
2041 * Load host RIP, RSP and RFLAGS.
2042 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2043 */
2044 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2045 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2046 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2047
2048 /* Clear address range monitoring. */
2049 EMMonitorWaitClear(pVCpu);
2050
2051 /* Perform the VMX transition (PGM updates). */
2052 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2053 if (rcStrict == VINF_SUCCESS)
2054 {
2055 /* Check host PDPTEs (only when we've fully switched page tables_. */
2056 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2057 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2058 if (RT_FAILURE(rc))
2059 {
2060 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2061 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2062 }
2063 }
2064 else if (RT_SUCCESS(rcStrict))
2065 {
2066 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2067 uExitReason));
2068 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2069 }
2070 else
2071 {
2072 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2073 return VBOXSTRICTRC_VAL(rcStrict);
2074 }
2075
2076 Assert(rcStrict == VINF_SUCCESS);
2077
2078 /* Load MSRs from the VM-exit auto-load MSR area. */
2079 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2080 if (RT_FAILURE(rc))
2081 {
2082 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2083 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2084 }
2085 return VINF_SUCCESS;
2086}
2087
2088
2089/**
2090 * Gets VM-exit instruction information along with any displacement for an
2091 * instruction VM-exit.
2092 *
2093 * @returns The VM-exit instruction information.
2094 * @param pVCpu The cross context virtual CPU structure.
2095 * @param uExitReason The VM-exit reason.
2096 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2097 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2098 * NULL.
2099 */
2100IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2101{
2102 RTGCPTR GCPtrDisp;
2103 VMXEXITINSTRINFO ExitInstrInfo;
2104 ExitInstrInfo.u = 0;
2105
2106 /*
2107 * Get and parse the ModR/M byte from our decoded opcodes.
2108 */
2109 uint8_t bRm;
2110 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2111 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2112 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2113 {
2114 /*
2115 * ModR/M indicates register addressing.
2116 *
2117 * The primary/secondary register operands are reported in the iReg1 or iReg2
2118 * fields depending on whether it is a read/write form.
2119 */
2120 uint8_t idxReg1;
2121 uint8_t idxReg2;
2122 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2123 {
2124 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2125 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2126 }
2127 else
2128 {
2129 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2130 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 }
2132 ExitInstrInfo.All.u2Scaling = 0;
2133 ExitInstrInfo.All.iReg1 = idxReg1;
2134 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2135 ExitInstrInfo.All.fIsRegOperand = 1;
2136 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2137 ExitInstrInfo.All.iSegReg = 0;
2138 ExitInstrInfo.All.iIdxReg = 0;
2139 ExitInstrInfo.All.fIdxRegInvalid = 1;
2140 ExitInstrInfo.All.iBaseReg = 0;
2141 ExitInstrInfo.All.fBaseRegInvalid = 1;
2142 ExitInstrInfo.All.iReg2 = idxReg2;
2143
2144 /* Displacement not applicable for register addressing. */
2145 GCPtrDisp = 0;
2146 }
2147 else
2148 {
2149 /*
2150 * ModR/M indicates memory addressing.
2151 */
2152 uint8_t uScale = 0;
2153 bool fBaseRegValid = false;
2154 bool fIdxRegValid = false;
2155 uint8_t iBaseReg = 0;
2156 uint8_t iIdxReg = 0;
2157 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2158 {
2159 /*
2160 * Parse the ModR/M, displacement for 16-bit addressing mode.
2161 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2162 */
2163 uint16_t u16Disp = 0;
2164 uint8_t const offDisp = offModRm + sizeof(bRm);
2165 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2166 {
2167 /* Displacement without any registers. */
2168 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2169 }
2170 else
2171 {
2172 /* Register (index and base). */
2173 switch (bRm & X86_MODRM_RM_MASK)
2174 {
2175 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2180 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2181 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2182 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2183 }
2184
2185 /* Register + displacement. */
2186 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2187 {
2188 case 0: break;
2189 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2190 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2191 default:
2192 {
2193 /* Register addressing, handled at the beginning. */
2194 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2195 break;
2196 }
2197 }
2198 }
2199
2200 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2201 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2202 }
2203 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2204 {
2205 /*
2206 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2207 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2208 */
2209 uint32_t u32Disp = 0;
2210 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2211 {
2212 /* Displacement without any registers. */
2213 uint8_t const offDisp = offModRm + sizeof(bRm);
2214 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2215 }
2216 else
2217 {
2218 /* Register (and perhaps scale, index and base). */
2219 uint8_t offDisp = offModRm + sizeof(bRm);
2220 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2221 if (iBaseReg == 4)
2222 {
2223 /* An SIB byte follows the ModR/M byte, parse it. */
2224 uint8_t bSib;
2225 uint8_t const offSib = offModRm + sizeof(bRm);
2226 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2227
2228 /* A displacement may follow SIB, update its offset. */
2229 offDisp += sizeof(bSib);
2230
2231 /* Get the scale. */
2232 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2233
2234 /* Get the index register. */
2235 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2236 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2237
2238 /* Get the base register. */
2239 iBaseReg = bSib & X86_SIB_BASE_MASK;
2240 fBaseRegValid = true;
2241 if (iBaseReg == 5)
2242 {
2243 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2244 {
2245 /* Mod is 0 implies a 32-bit displacement with no base. */
2246 fBaseRegValid = false;
2247 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2248 }
2249 else
2250 {
2251 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2252 iBaseReg = X86_GREG_xBP;
2253 }
2254 }
2255 }
2256
2257 /* Register + displacement. */
2258 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2259 {
2260 case 0: /* Handled above */ break;
2261 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2262 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2263 default:
2264 {
2265 /* Register addressing, handled at the beginning. */
2266 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2267 break;
2268 }
2269 }
2270 }
2271
2272 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2273 }
2274 else
2275 {
2276 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2277
2278 /*
2279 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2280 * See Intel instruction spec. 2.2 "IA-32e Mode".
2281 */
2282 uint64_t u64Disp = 0;
2283 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2284 if (fRipRelativeAddr)
2285 {
2286 /*
2287 * RIP-relative addressing mode.
2288 *
2289 * The displacement is 32-bit signed implying an offset range of +/-2G.
2290 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2291 */
2292 uint8_t const offDisp = offModRm + sizeof(bRm);
2293 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2294 }
2295 else
2296 {
2297 uint8_t offDisp = offModRm + sizeof(bRm);
2298
2299 /*
2300 * Register (and perhaps scale, index and base).
2301 *
2302 * REX.B extends the most-significant bit of the base register. However, REX.B
2303 * is ignored while determining whether an SIB follows the opcode. Hence, we
2304 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2305 *
2306 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2307 */
2308 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2309 if (iBaseReg == 4)
2310 {
2311 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2312 uint8_t bSib;
2313 uint8_t const offSib = offModRm + sizeof(bRm);
2314 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2315
2316 /* Displacement may follow SIB, update its offset. */
2317 offDisp += sizeof(bSib);
2318
2319 /* Get the scale. */
2320 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2321
2322 /* Get the index. */
2323 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2324 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2325
2326 /* Get the base. */
2327 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2328 fBaseRegValid = true;
2329 if (iBaseReg == 5)
2330 {
2331 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2332 {
2333 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2334 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2335 }
2336 else
2337 {
2338 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2339 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2340 }
2341 }
2342 }
2343 iBaseReg |= pVCpu->iem.s.uRexB;
2344
2345 /* Register + displacement. */
2346 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2347 {
2348 case 0: /* Handled above */ break;
2349 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2350 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2351 default:
2352 {
2353 /* Register addressing, handled at the beginning. */
2354 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2355 break;
2356 }
2357 }
2358 }
2359
2360 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2361 }
2362
2363 /*
2364 * The primary or secondary register operand is reported in iReg2 depending
2365 * on whether the primary operand is in read/write form.
2366 */
2367 uint8_t idxReg2;
2368 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2369 {
2370 idxReg2 = bRm & X86_MODRM_RM_MASK;
2371 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2372 idxReg2 |= pVCpu->iem.s.uRexB;
2373 }
2374 else
2375 {
2376 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexReg;
2379 }
2380 ExitInstrInfo.All.u2Scaling = uScale;
2381 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2382 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2383 ExitInstrInfo.All.fIsRegOperand = 0;
2384 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2385 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2386 ExitInstrInfo.All.iIdxReg = iIdxReg;
2387 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2388 ExitInstrInfo.All.iBaseReg = iBaseReg;
2389 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2390 ExitInstrInfo.All.iReg2 = idxReg2;
2391 }
2392
2393 /*
2394 * Handle exceptions to the norm for certain instructions.
2395 * (e.g. some instructions convey an instruction identity in place of iReg2).
2396 */
2397 switch (uExitReason)
2398 {
2399 case VMX_EXIT_GDTR_IDTR_ACCESS:
2400 {
2401 Assert(VMXINSTRID_IS_VALID(uInstrId));
2402 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2403 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2404 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2405 break;
2406 }
2407
2408 case VMX_EXIT_LDTR_TR_ACCESS:
2409 {
2410 Assert(VMXINSTRID_IS_VALID(uInstrId));
2411 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2412 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2413 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2414 break;
2415 }
2416
2417 case VMX_EXIT_RDRAND:
2418 case VMX_EXIT_RDSEED:
2419 {
2420 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2421 break;
2422 }
2423 }
2424
2425 /* Update displacement and return the constructed VM-exit instruction information field. */
2426 if (pGCPtrDisp)
2427 *pGCPtrDisp = GCPtrDisp;
2428
2429 return ExitInstrInfo.u;
2430}
2431
2432
2433/**
2434 * VMX VM-exit handler.
2435 *
2436 * @returns Strict VBox status code.
2437 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2438 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2439 * triple-fault.
2440 *
2441 * @param pVCpu The cross context virtual CPU structure.
2442 * @param uExitReason The VM-exit reason.
2443 * @param u64ExitQual The Exit qualification.
2444 */
2445IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2446{
2447# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2448 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2449 return VINF_EM_RAW_EMULATE_INSTR;
2450# else
2451 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2452 Assert(pVmcs);
2453
2454 /*
2455 * Import all the guest-CPU state.
2456 *
2457 * HM on returning to guest execution would have to reset up a whole lot of state
2458 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2459 * the state and flag reloading the entire state on re-entry. So import the entire
2460 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2461 */
2462 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2463
2464 /*
2465 * Ensure VM-entry interruption information valid bit is cleared.
2466 *
2467 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2468 * by invalid-guest state or machine-check exceptions) also clear this bit.
2469 *
2470 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2471 */
2472 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2473 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2474
2475 /*
2476 * Update the VM-exit reason and Exit qualification.
2477 * Other VMCS read-only data fields are expected to be updated by the caller already.
2478 */
2479 pVmcs->u32RoExitReason = uExitReason;
2480 pVmcs->u64RoExitQual.u = u64ExitQual;
2481
2482 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2483 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2484
2485 /*
2486 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2487 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2488 */
2489 {
2490 uint8_t uVector;
2491 uint32_t fFlags;
2492 uint32_t uErrCode;
2493 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2494 if (fInEventDelivery)
2495 {
2496 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2497 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2498 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2499 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2500 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2501 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2502 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2503 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2504 }
2505 }
2506
2507 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2508 Assert(pVmcs->u64RoIoRcx.u == 0);
2509 Assert(pVmcs->u64RoIoRsi.u == 0);
2510 Assert(pVmcs->u64RoIoRdi.u == 0);
2511 Assert(pVmcs->u64RoIoRip.u == 0);
2512
2513 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2514 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2515 {
2516 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2517 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2518 }
2519
2520 /* Paranoia. */
2521 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2522
2523 /*
2524 * Save the guest state back into the VMCS.
2525 * We only need to save the state when the VM-entry was successful.
2526 */
2527 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2528 if (!fVmentryFailed)
2529 {
2530 /*
2531 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2532 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2533 *
2534 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2535 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2536 * as guest-CPU state would not been modified. Hence for now, we do this only when
2537 * the VM-entry succeeded.
2538 */
2539 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2540 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2541 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2542 {
2543 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2544 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2545 else
2546 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2547 }
2548
2549 /*
2550 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2551 * occurs in enclave mode/SMM which we don't support yet.
2552 *
2553 * If we ever add support for it, we can pass just the lower bits to the functions
2554 * below, till then an assert should suffice.
2555 */
2556 Assert(!RT_HI_U16(uExitReason));
2557
2558 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2559 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2560 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2561 if (RT_SUCCESS(rc))
2562 { /* likely */ }
2563 else
2564 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2565
2566 /*
2567 * Write the contents of the virtual-APIC page back into guest memory (shouldn't really fail).
2568 */
2569 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty)
2570 {
2571 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
2572 int rc2 = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrVirtApic.u,
2573 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage), VMX_V_VIRT_APIC_SIZE);
2574 AssertRCReturn(rc2, rc2);
2575
2576 /* Clear the virtual-APIC page dirty bit now that it's written back to guest memory. */
2577 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = false;
2578 }
2579
2580 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2581 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2582 }
2583 else
2584 {
2585 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2586 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2587 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2588 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2589 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2590 }
2591
2592 /*
2593 * Clear any pending VMX nested-guest force-flags.
2594 * These force-flags have no effect on guest execution and will
2595 * be re-evaluated and setup on the next nested-guest VM-entry.
2596 */
2597 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2598 | VMCPU_FF_VMX_MTF
2599 | VMCPU_FF_VMX_APIC_WRITE
2600 | VMCPU_FF_VMX_INT_WINDOW
2601 | VMCPU_FF_VMX_NMI_WINDOW);
2602
2603 /* Restore the host (outer guest) state. */
2604 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2605 if (RT_SUCCESS(rcStrict))
2606 {
2607 Assert(rcStrict == VINF_SUCCESS);
2608 rcStrict = VINF_VMX_VMEXIT;
2609 }
2610 else
2611 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2612
2613 /* Notify HM that the current VMCS fields have been modified. */
2614 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2615
2616 /* Notify HM that we've completed the VM-exit. */
2617 HMNotifyVmxNstGstVmexit(pVCpu);
2618
2619 /* We're no longer in nested-guest execution mode. */
2620 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2621
2622# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2623 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2624 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2625 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2626 if (rcSched != VINF_SUCCESS)
2627 iemSetPassUpStatus(pVCpu, rcSched);
2628# endif
2629 return rcStrict;
2630# endif
2631}
2632
2633
2634/**
2635 * VMX VM-exit handler for VM-exits due to instruction execution.
2636 *
2637 * This is intended for instructions where the caller provides all the relevant
2638 * VM-exit information.
2639 *
2640 * @returns Strict VBox status code.
2641 * @param pVCpu The cross context virtual CPU structure.
2642 * @param pExitInfo Pointer to the VM-exit information.
2643 */
2644IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2645{
2646 /*
2647 * For instructions where any of the following fields are not applicable:
2648 * - Exit qualification must be cleared.
2649 * - VM-exit instruction info. is undefined.
2650 * - Guest-linear address is undefined.
2651 * - Guest-physical address is undefined.
2652 *
2653 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2654 * instruction execution. For VM-exits that are not due to instruction execution this
2655 * field is undefined.
2656 *
2657 * In our implementation in IEM, all undefined fields are generally cleared. However,
2658 * if the caller supplies information (from say the physical CPU directly) it is
2659 * then possible that the undefined fields are not cleared.
2660 *
2661 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2662 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2663 */
2664 Assert(pExitInfo);
2665 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2666 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2667 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2668
2669 /* Update all the relevant fields from the VM-exit instruction information struct. */
2670 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2671 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2672 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2673 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2674
2675 /* Perform the VM-exit. */
2676 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2677}
2678
2679
2680/**
2681 * VMX VM-exit handler for VM-exits due to instruction execution.
2682 *
2683 * This is intended for instructions that only provide the VM-exit instruction
2684 * length.
2685 *
2686 * @param pVCpu The cross context virtual CPU structure.
2687 * @param uExitReason The VM-exit reason.
2688 * @param cbInstr The instruction length in bytes.
2689 */
2690IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2691{
2692 VMXVEXITINFO ExitInfo;
2693 RT_ZERO(ExitInfo);
2694 ExitInfo.uReason = uExitReason;
2695 ExitInfo.cbInstr = cbInstr;
2696
2697#ifdef VBOX_STRICT
2698 /*
2699 * To prevent us from shooting ourselves in the foot.
2700 * The follow instructions should convey more than just the instruction length.
2701 */
2702 switch (uExitReason)
2703 {
2704 case VMX_EXIT_INVEPT:
2705 case VMX_EXIT_INVPCID:
2706 case VMX_EXIT_INVVPID:
2707 case VMX_EXIT_LDTR_TR_ACCESS:
2708 case VMX_EXIT_GDTR_IDTR_ACCESS:
2709 case VMX_EXIT_VMCLEAR:
2710 case VMX_EXIT_VMPTRLD:
2711 case VMX_EXIT_VMPTRST:
2712 case VMX_EXIT_VMREAD:
2713 case VMX_EXIT_VMWRITE:
2714 case VMX_EXIT_VMXON:
2715 case VMX_EXIT_XRSTORS:
2716 case VMX_EXIT_XSAVES:
2717 case VMX_EXIT_RDRAND:
2718 case VMX_EXIT_RDSEED:
2719 case VMX_EXIT_IO_INSTR:
2720 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2721 break;
2722 }
2723#endif
2724
2725 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2726}
2727
2728
2729/**
2730 * VMX VM-exit handler for VM-exits due to instruction execution.
2731 *
2732 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2733 * instruction information and Exit qualification fields.
2734 *
2735 * @param pVCpu The cross context virtual CPU structure.
2736 * @param uExitReason The VM-exit reason.
2737 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2738 * @param cbInstr The instruction length in bytes.
2739 *
2740 * @remarks Do not use this for INS/OUTS instruction.
2741 */
2742IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2743{
2744 VMXVEXITINFO ExitInfo;
2745 RT_ZERO(ExitInfo);
2746 ExitInfo.uReason = uExitReason;
2747 ExitInfo.cbInstr = cbInstr;
2748
2749 /*
2750 * Update the Exit qualification field with displacement bytes.
2751 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2752 */
2753 switch (uExitReason)
2754 {
2755 case VMX_EXIT_INVEPT:
2756 case VMX_EXIT_INVPCID:
2757 case VMX_EXIT_INVVPID:
2758 case VMX_EXIT_LDTR_TR_ACCESS:
2759 case VMX_EXIT_GDTR_IDTR_ACCESS:
2760 case VMX_EXIT_VMCLEAR:
2761 case VMX_EXIT_VMPTRLD:
2762 case VMX_EXIT_VMPTRST:
2763 case VMX_EXIT_VMREAD:
2764 case VMX_EXIT_VMWRITE:
2765 case VMX_EXIT_VMXON:
2766 case VMX_EXIT_XRSTORS:
2767 case VMX_EXIT_XSAVES:
2768 case VMX_EXIT_RDRAND:
2769 case VMX_EXIT_RDSEED:
2770 {
2771 /* Construct the VM-exit instruction information. */
2772 RTGCPTR GCPtrDisp;
2773 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2774
2775 /* Update the VM-exit instruction information. */
2776 ExitInfo.InstrInfo.u = uInstrInfo;
2777
2778 /* Update the Exit qualification. */
2779 ExitInfo.u64Qual = GCPtrDisp;
2780 break;
2781 }
2782
2783 default:
2784 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2785 break;
2786 }
2787
2788 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2789}
2790
2791
2792/**
2793 * VMX VM-exit handler for VM-exits due to INVLPG.
2794 *
2795 * @returns Strict VBox status code.
2796 * @param pVCpu The cross context virtual CPU structure.
2797 * @param GCPtrPage The guest-linear address of the page being invalidated.
2798 * @param cbInstr The instruction length in bytes.
2799 */
2800IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2801{
2802 VMXVEXITINFO ExitInfo;
2803 RT_ZERO(ExitInfo);
2804 ExitInfo.uReason = VMX_EXIT_INVLPG;
2805 ExitInfo.cbInstr = cbInstr;
2806 ExitInfo.u64Qual = GCPtrPage;
2807 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2808
2809 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2810}
2811
2812
2813/**
2814 * VMX VM-exit handler for VM-exits due to LMSW.
2815 *
2816 * @returns Strict VBox status code.
2817 * @param pVCpu The cross context virtual CPU structure.
2818 * @param uGuestCr0 The current guest CR0.
2819 * @param pu16NewMsw The machine-status word specified in LMSW's source
2820 * operand. This will be updated depending on the VMX
2821 * guest/host CR0 mask if LMSW is not intercepted.
2822 * @param GCPtrEffDst The guest-linear address of the source operand in case
2823 * of a memory operand. For register operand, pass
2824 * NIL_RTGCPTR.
2825 * @param cbInstr The instruction length in bytes.
2826 */
2827IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2828 uint8_t cbInstr)
2829{
2830 Assert(pu16NewMsw);
2831
2832 uint16_t const uNewMsw = *pu16NewMsw;
2833 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2834 {
2835 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2836
2837 VMXVEXITINFO ExitInfo;
2838 RT_ZERO(ExitInfo);
2839 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2840 ExitInfo.cbInstr = cbInstr;
2841
2842 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2843 if (fMemOperand)
2844 {
2845 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2846 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2847 }
2848
2849 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2850 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2851 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2852 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2853
2854 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2855 }
2856
2857 /*
2858 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2859 * CR0 guest/host mask must be left unmodified.
2860 *
2861 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2862 */
2863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2864 Assert(pVmcs);
2865 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2866 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2867 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2868
2869 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2870}
2871
2872
2873/**
2874 * VMX VM-exit handler for VM-exits due to CLTS.
2875 *
2876 * @returns Strict VBox status code.
2877 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2878 * VM-exit but must not modify the guest CR0.TS bit.
2879 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2880 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2881 * CR0 fixed bits in VMX operation).
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param cbInstr The instruction length in bytes.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
2886{
2887 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2888 Assert(pVmcs);
2889
2890 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2891 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2892
2893 /*
2894 * If CR0.TS is owned by the host:
2895 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2896 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2897 * CLTS instruction completes without clearing CR0.TS.
2898 *
2899 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2900 */
2901 if (fGstHostMask & X86_CR0_TS)
2902 {
2903 if (fReadShadow & X86_CR0_TS)
2904 {
2905 Log2(("clts: Guest intercept -> VM-exit\n"));
2906
2907 VMXVEXITINFO ExitInfo;
2908 RT_ZERO(ExitInfo);
2909 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2910 ExitInfo.cbInstr = cbInstr;
2911 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2912 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2913 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2914 }
2915
2916 return VINF_VMX_MODIFIES_BEHAVIOR;
2917 }
2918
2919 /*
2920 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2921 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2922 */
2923 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2924}
2925
2926
2927/**
2928 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2929 * (CR0/CR4 write).
2930 *
2931 * @returns Strict VBox status code.
2932 * @param pVCpu The cross context virtual CPU structure.
2933 * @param iCrReg The control register (either CR0 or CR4).
2934 * @param uGuestCrX The current guest CR0/CR4.
2935 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2936 * VM-exit is caused.
2937 * @param iGReg The general register from which the CR0/CR4 value is being
2938 * loaded.
2939 * @param cbInstr The instruction length in bytes.
2940 */
2941IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2942 uint8_t cbInstr)
2943{
2944 Assert(puNewCrX);
2945 Assert(iCrReg == 0 || iCrReg == 4);
2946 Assert(iGReg < X86_GREG_COUNT);
2947
2948 uint64_t const uNewCrX = *puNewCrX;
2949 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2950 {
2951 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2952
2953 VMXVEXITINFO ExitInfo;
2954 RT_ZERO(ExitInfo);
2955 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2956 ExitInfo.cbInstr = cbInstr;
2957 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2958 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2959 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2960 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2961 }
2962
2963 /*
2964 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2965 * must not be modified the instruction.
2966 *
2967 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2968 */
2969 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2970 Assert(pVmcs);
2971 uint64_t uGuestCrX;
2972 uint64_t fGstHostMask;
2973 if (iCrReg == 0)
2974 {
2975 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2976 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2977 fGstHostMask = pVmcs->u64Cr0Mask.u;
2978 }
2979 else
2980 {
2981 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2982 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2983 fGstHostMask = pVmcs->u64Cr4Mask.u;
2984 }
2985
2986 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2987 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2988}
2989
2990
2991/**
2992 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2993 *
2994 * @returns VBox strict status code.
2995 * @param pVCpu The cross context virtual CPU structure.
2996 * @param iGReg The general register to which the CR3 value is being stored.
2997 * @param cbInstr The instruction length in bytes.
2998 */
2999IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3000{
3001 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3002 Assert(pVmcs);
3003 Assert(iGReg < X86_GREG_COUNT);
3004 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3005
3006 /*
3007 * If the CR3-store exiting control is set, we must cause a VM-exit.
3008 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3009 */
3010 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3011 {
3012 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3013
3014 VMXVEXITINFO ExitInfo;
3015 RT_ZERO(ExitInfo);
3016 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3017 ExitInfo.cbInstr = cbInstr;
3018 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3021 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3022 }
3023
3024 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3025}
3026
3027
3028/**
3029 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3030 *
3031 * @returns VBox strict status code.
3032 * @param pVCpu The cross context virtual CPU structure.
3033 * @param uNewCr3 The new CR3 value.
3034 * @param iGReg The general register from which the CR3 value is being
3035 * loaded.
3036 * @param cbInstr The instruction length in bytes.
3037 */
3038IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3039{
3040 Assert(iGReg < X86_GREG_COUNT);
3041
3042 /*
3043 * If the CR3-load exiting control is set and the new CR3 value does not
3044 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3045 *
3046 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3047 */
3048 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3049 {
3050 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3051
3052 VMXVEXITINFO ExitInfo;
3053 RT_ZERO(ExitInfo);
3054 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3055 ExitInfo.cbInstr = cbInstr;
3056 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3058 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3059 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3060 }
3061
3062 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3063}
3064
3065
3066/**
3067 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3068 *
3069 * @returns VBox strict status code.
3070 * @param pVCpu The cross context virtual CPU structure.
3071 * @param iGReg The general register to which the CR8 value is being stored.
3072 * @param cbInstr The instruction length in bytes.
3073 */
3074IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3075{
3076 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3077 Assert(pVmcs);
3078 Assert(iGReg < X86_GREG_COUNT);
3079
3080 /*
3081 * If the CR8-store exiting control is set, we must cause a VM-exit.
3082 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3083 */
3084 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3085 {
3086 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3087
3088 VMXVEXITINFO ExitInfo;
3089 RT_ZERO(ExitInfo);
3090 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3091 ExitInfo.cbInstr = cbInstr;
3092 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3094 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3095 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3096 }
3097
3098 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3099}
3100
3101
3102/**
3103 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3104 *
3105 * @returns VBox strict status code.
3106 * @param pVCpu The cross context virtual CPU structure.
3107 * @param iGReg The general register from which the CR8 value is being
3108 * loaded.
3109 * @param cbInstr The instruction length in bytes.
3110 */
3111IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3112{
3113 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3114 Assert(pVmcs);
3115 Assert(iGReg < X86_GREG_COUNT);
3116
3117 /*
3118 * If the CR8-load exiting control is set, we must cause a VM-exit.
3119 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3120 */
3121 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3122 {
3123 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3124
3125 VMXVEXITINFO ExitInfo;
3126 RT_ZERO(ExitInfo);
3127 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3128 ExitInfo.cbInstr = cbInstr;
3129 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3130 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3131 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3132 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3133 }
3134
3135 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3136}
3137
3138
3139/**
3140 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3141 * GReg,DRx' (DRx read).
3142 *
3143 * @returns VBox strict status code.
3144 * @param pVCpu The cross context virtual CPU structure.
3145 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3146 * VMXINSTRID_MOV_FROM_DRX).
3147 * @param iDrReg The debug register being accessed.
3148 * @param iGReg The general register to/from which the DRx value is being
3149 * store/loaded.
3150 * @param cbInstr The instruction length in bytes.
3151 */
3152IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3153 uint8_t cbInstr)
3154{
3155 Assert(iDrReg <= 7);
3156 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3157 Assert(iGReg < X86_GREG_COUNT);
3158
3159 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3160 Assert(pVmcs);
3161
3162 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3163 {
3164 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3165 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3166 VMXVEXITINFO ExitInfo;
3167 RT_ZERO(ExitInfo);
3168 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3169 ExitInfo.cbInstr = cbInstr;
3170 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3171 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3173 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3174 }
3175
3176 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3177}
3178
3179
3180/**
3181 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3182 *
3183 * @returns VBox strict status code.
3184 * @param pVCpu The cross context virtual CPU structure.
3185 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3186 * VMXINSTRID_IO_OUT).
3187 * @param u16Port The I/O port being accessed.
3188 * @param fImm Whether the I/O port was encoded using an immediate operand
3189 * or the implicit DX register.
3190 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3191 * @param cbInstr The instruction length in bytes.
3192 */
3193IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3194 uint8_t cbInstr)
3195{
3196 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3197 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3198
3199 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3200 if (fIntercept)
3201 {
3202 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3203 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3204 VMXVEXITINFO ExitInfo;
3205 RT_ZERO(ExitInfo);
3206 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3207 ExitInfo.cbInstr = cbInstr;
3208 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3209 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3210 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3211 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3212 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3213 }
3214
3215 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3216}
3217
3218
3219/**
3220 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3221 *
3222 * @returns VBox strict status code.
3223 * @param pVCpu The cross context virtual CPU structure.
3224 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3225 * VMXINSTRID_IO_OUTS).
3226 * @param u16Port The I/O port being accessed.
3227 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3228 * @param fRep Whether the instruction has a REP prefix or not.
3229 * @param ExitInstrInfo The VM-exit instruction info. field.
3230 * @param cbInstr The instruction length in bytes.
3231 */
3232IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3233 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3234{
3235 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3236 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3237 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3238 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3239 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3240
3241 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3242 if (fIntercept)
3243 {
3244 /*
3245 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3246 */
3247 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3248 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3249 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3250 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3251 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3252
3253 uint32_t uDirection;
3254 uint64_t uGuestLinearAddr;
3255 if (uInstrId == VMXINSTRID_IO_INS)
3256 {
3257 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3258 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3259 }
3260 else
3261 {
3262 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3263 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3264 }
3265
3266 /*
3267 * If the segment is unusable, the guest-linear address in undefined.
3268 * We shall clear it for consistency.
3269 *
3270 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3271 */
3272 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3273 uGuestLinearAddr = 0;
3274
3275 VMXVEXITINFO ExitInfo;
3276 RT_ZERO(ExitInfo);
3277 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3278 ExitInfo.cbInstr = cbInstr;
3279 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3280 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3284 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3285 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3286 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3287 ExitInfo.InstrInfo = ExitInstrInfo;
3288 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3289 }
3290
3291 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3292}
3293
3294
3295/**
3296 * VMX VM-exit handler for VM-exits due to MWAIT.
3297 *
3298 * @returns VBox strict status code.
3299 * @param pVCpu The cross context virtual CPU structure.
3300 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3301 * @param cbInstr The instruction length in bytes.
3302 */
3303IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3304{
3305 VMXVEXITINFO ExitInfo;
3306 RT_ZERO(ExitInfo);
3307 ExitInfo.uReason = VMX_EXIT_MWAIT;
3308 ExitInfo.cbInstr = cbInstr;
3309 ExitInfo.u64Qual = fMonitorHwArmed;
3310 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3311}
3312
3313
3314/**
3315 * VMX VM-exit handler for VM-exits due to PAUSE.
3316 *
3317 * @returns VBox strict status code.
3318 * @param pVCpu The cross context virtual CPU structure.
3319 * @param cbInstr The instruction length in bytes.
3320 */
3321IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3322{
3323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3324 Assert(pVmcs);
3325
3326 /*
3327 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3328 * "PAUSE-loop exiting" control.
3329 *
3330 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3331 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3332 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3333 * a VM-exit.
3334 *
3335 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3336 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3337 */
3338 bool fIntercept = false;
3339 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3340 fIntercept = true;
3341 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3342 && pVCpu->iem.s.uCpl == 0)
3343 {
3344 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3345
3346 /*
3347 * A previous-PAUSE-tick value of 0 is used to identify the first time
3348 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3349 * consider this to be the first execution of PAUSE in a loop according
3350 * to the Intel.
3351 *
3352 * All subsequent records for the previous-PAUSE-tick we ensure that it
3353 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3354 */
3355 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3356 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3357 uint64_t const uTick = TMCpuTickGet(pVCpu);
3358 uint32_t const uPleGap = pVmcs->u32PleGap;
3359 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3360 if ( *puPrevPauseTick == 0
3361 || uTick - *puPrevPauseTick > uPleGap)
3362 *puFirstPauseLoopTick = uTick;
3363 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3364 fIntercept = true;
3365
3366 *puPrevPauseTick = uTick | 1;
3367 }
3368
3369 if (fIntercept)
3370 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3371
3372 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3373}
3374
3375
3376/**
3377 * VMX VM-exit handler for VM-exits due to task switches.
3378 *
3379 * @returns VBox strict status code.
3380 * @param pVCpu The cross context virtual CPU structure.
3381 * @param enmTaskSwitch The cause of the task switch.
3382 * @param SelNewTss The selector of the new TSS.
3383 * @param cbInstr The instruction length in bytes.
3384 */
3385IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3386{
3387 /*
3388 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3389 *
3390 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3391 * instruction or delivery of the exception generated by one of these instructions
3392 * lead to a task switch through a task gate in the IDT, we need to provide the
3393 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3394 * leaves the VM-exit instruction length field undefined.
3395 *
3396 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3397 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3398 */
3399 Assert(cbInstr <= 15);
3400
3401 uint8_t uType;
3402 switch (enmTaskSwitch)
3403 {
3404 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3405 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3406 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3407 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3408 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3409 }
3410
3411 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3412 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3413 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3414 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3415}
3416
3417
3418/**
3419 * VMX VM-exit handler for VM-exits due to task switches.
3420 *
3421 * This is intended for task switches where the caller provides all the relevant
3422 * VM-exit information.
3423 *
3424 * @returns VBox strict status code.
3425 * @param pVCpu The cross context virtual CPU structure.
3426 * @param pExitInfo Pointer to the VM-exit information.
3427 * @param pExitEventInfo Pointer to the VM-exit event information.
3428 */
3429IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3430 PCVMXVEXITEVENTINFO pExitEventInfo)
3431{
3432 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3433 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3434 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3435 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3436 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3437}
3438
3439
3440/**
3441 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3442 *
3443 * @returns VBox strict status code.
3444 * @param pVCpu The cross context virtual CPU structure.
3445 */
3446IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3447{
3448 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3449 Assert(pVmcs);
3450
3451 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3452 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3453 {
3454 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3455 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3456
3457 /*
3458 * Calculate the current VMX-preemption timer value.
3459 * Only if the value has reached zero, we cause the VM-exit.
3460 */
3461 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3462 if (!uPreemptTimer)
3463 {
3464 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3465 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3466 pVmcs->u32PreemptTimer = 0;
3467
3468 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3469 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3470 }
3471 }
3472
3473 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3474}
3475
3476
3477/**
3478 * VMX VM-exit handler for VM-exits due to external interrupts.
3479 *
3480 * @returns VBox strict status code.
3481 * @param pVCpu The cross context virtual CPU structure.
3482 * @param uVector The external interrupt vector (pass 0 if the interrupt
3483 * is still pending since we typically won't know the
3484 * vector).
3485 * @param fIntPending Whether the external interrupt is pending or
3486 * acknowledged in the interrupt controller.
3487 */
3488IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3489{
3490 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3491 Assert(pVmcs);
3492 Assert(fIntPending || uVector == 0);
3493
3494 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3495 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3496 * functions require prior checking of a blanket intercept and which don't.
3497 * It is better for the caller to check a blanket intercept performance wise
3498 * than making a function call. Leaving this as a todo because it is more
3499 * a performance issue. */
3500
3501 /* The VM-exit is subject to "External interrupt exiting" being set. */
3502 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3503 {
3504 if (fIntPending)
3505 {
3506 /*
3507 * If the interrupt is pending and we don't need to acknowledge the
3508 * interrupt on VM-exit, cause the VM-exit immediately.
3509 *
3510 * See Intel spec 25.2 "Other Causes Of VM Exits".
3511 */
3512 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3513 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3514
3515 /*
3516 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3517 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3518 * acknowledged that the interrupt has been consumed.
3519 */
3520 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3521 }
3522
3523 /*
3524 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3525 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3526 * all set, we cause the VM-exit now. We need to record the external interrupt that
3527 * just occurred in the VM-exit interruption information field.
3528 *
3529 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3530 */
3531 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3532 {
3533 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3534 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3535 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3536 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3537 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3538 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3539 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3540 }
3541 }
3542
3543 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3544}
3545
3546
3547/**
3548 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3549 * an event.
3550 *
3551 * @returns VBox strict status code.
3552 * @param pVCpu The cross context virtual CPU structure.
3553 */
3554IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3555{
3556 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3557 Assert(pVmcs);
3558
3559 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3560 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3561 {
3562 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3563 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3564 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3565 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3566 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3567 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3568 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3569 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3570 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3571
3572 /*
3573 * A VM-exit is not considered to occur during event delivery when the original
3574 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3575 * using the exception bitmap).
3576 *
3577 * Therefore, we must clear the original event from the IDT-vectoring fields which
3578 * would've been recorded before causing the VM-exit.
3579 *
3580 * 27.2.3 "Information for VM Exits During Event Delivery"
3581 */
3582 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3583 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3584 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3585 }
3586
3587 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3588}
3589
3590
3591/**
3592 * VMX VM-exit handler for VM-exit due to delivery of an events.
3593 *
3594 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3595 * all the relevant VM-exit information.
3596 *
3597 * @returns VBox strict status code.
3598 * @param pVCpu The cross context virtual CPU structure.
3599 * @param pExitInfo Pointer to the VM-exit information.
3600 * @param pExitEventInfo Pointer to the VM-exit event information.
3601 */
3602IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3603{
3604 Assert(pExitInfo);
3605 Assert(pExitEventInfo);
3606 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3607
3608 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3609 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3610 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3611 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3612 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3613 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3614}
3615
3616
3617/**
3618 * VMX VM-exit handler for VM-exits due to delivery of an event.
3619 *
3620 * @returns VBox strict status code.
3621 * @param pVCpu The cross context virtual CPU structure.
3622 * @param uVector The interrupt / exception vector.
3623 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3624 * @param uErrCode The error code associated with the event.
3625 * @param uCr2 The CR2 value in case of a \#PF exception.
3626 * @param cbInstr The instruction length in bytes.
3627 */
3628IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3629 uint8_t cbInstr)
3630{
3631 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3632 Assert(pVmcs);
3633
3634 /*
3635 * If the event is being injected as part of VM-entry, it is -not- subject to event
3636 * intercepts in the nested-guest. However, secondary exceptions that occur during
3637 * injection of any event -are- subject to event interception.
3638 *
3639 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3640 */
3641 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3642 {
3643 /*
3644 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3645 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3646 *
3647 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3648 */
3649 if ( uVector == X86_XCPT_NMI
3650 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3651 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3652 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3653 else
3654 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3655
3656 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3657 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3658 }
3659
3660 /*
3661 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3662 * If not, the caller will continue delivery of the external interrupt as it would
3663 * normally. The interrupt is no longer pending in the interrupt controller at this
3664 * point.
3665 */
3666 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3667 {
3668 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3669 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3670 }
3671
3672 /*
3673 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3674 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3675 * interrupts.
3676 */
3677 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3678 bool fIntercept;
3679 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3680 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3681 {
3682 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3683 }
3684 else
3685 {
3686 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3687 fIntercept = false;
3688 }
3689
3690 /*
3691 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3692 * relevant VM-exit information and cause the VM-exit.
3693 */
3694 if (fIntercept)
3695 {
3696 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3697
3698 /* Construct the rest of the event related information fields and cause the VM-exit. */
3699 uint64_t u64ExitQual;
3700 if (uVector == X86_XCPT_PF)
3701 {
3702 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3703 u64ExitQual = uCr2;
3704 }
3705 else if (uVector == X86_XCPT_DB)
3706 {
3707 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3708 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3709 }
3710 else
3711 u64ExitQual = 0;
3712
3713 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3714 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3715 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3716 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3717 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3718 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3719 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3720 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3721 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3722 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3723
3724 /*
3725 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3726 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3727 * length.
3728 */
3729 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3730 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3731 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3732 else
3733 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3734
3735 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3736 }
3737
3738 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3739}
3740
3741
3742/**
3743 * VMX VM-exit handler for VM-exits due to a triple fault.
3744 *
3745 * @returns VBox strict status code.
3746 * @param pVCpu The cross context virtual CPU structure.
3747 */
3748IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
3749{
3750 /*
3751 * A VM-exit is not considered to occur during event delivery when the original
3752 * event results in a triple-fault.
3753 *
3754 * Therefore, we must clear the original event from the IDT-vectoring fields which
3755 * would've been recorded before causing the VM-exit.
3756 *
3757 * 27.2.3 "Information for VM Exits During Event Delivery"
3758 */
3759 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3760 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3761
3762 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
3763}
3764
3765
3766/**
3767 * VMX VM-exit handler for APIC accesses.
3768 *
3769 * @param pVCpu The cross context virtual CPU structure.
3770 * @param offAccess The offset of the register being accessed.
3771 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3772 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3773 */
3774IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
3775{
3776 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3777
3778 VMXAPICACCESS enmAccess;
3779 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3780 if (fInEventDelivery)
3781 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3782 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3783 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3784 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3785 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3786 else
3787 enmAccess = VMXAPICACCESS_LINEAR_READ;
3788
3789 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3790 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3791 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3792}
3793
3794
3795/**
3796 * VMX VM-exit handler for APIC accesses.
3797 *
3798 * This is intended for APIC accesses where the caller provides all the
3799 * relevant VM-exit information.
3800 *
3801 * @returns VBox strict status code.
3802 * @param pVCpu The cross context virtual CPU structure.
3803 * @param pExitInfo Pointer to the VM-exit information.
3804 * @param pExitEventInfo Pointer to the VM-exit event information.
3805 */
3806IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo,
3807 PCVMXVEXITEVENTINFO pExitEventInfo)
3808{
3809 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3810 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3811 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3812 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3813 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3814 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3815 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3816}
3817
3818
3819/**
3820 * VMX VM-exit handler for APIC-write VM-exits.
3821 *
3822 * @param pVCpu The cross context virtual CPU structure.
3823 * @param offApic The write to the virtual-APIC page offset that caused this
3824 * VM-exit.
3825 */
3826IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
3827{
3828 Assert(offApic < XAPIC_OFF_END + 4);
3829 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3830 offApic &= UINT16_C(0xfff);
3831 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3832}
3833
3834
3835/**
3836 * Sets virtual-APIC write emulation as pending.
3837 *
3838 * @param pVCpu The cross context virtual CPU structure.
3839 * @param offApic The offset in the virtual-APIC page that was written.
3840 */
3841DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
3842{
3843 Assert(offApic < XAPIC_OFF_END + 4);
3844
3845 /*
3846 * Record the currently updated APIC offset, as we need this later for figuring
3847 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3848 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3849 */
3850 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3851
3852 /*
3853 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3854 * virtualization or APIC-write emulation).
3855 */
3856 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3857 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3858}
3859
3860
3861/**
3862 * Clears any pending virtual-APIC write emulation.
3863 *
3864 * @returns The virtual-APIC offset that was written before clearing it.
3865 * @param pVCpu The cross context virtual CPU structure.
3866 */
3867DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
3868{
3869 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3870 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3871 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3872 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3873 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3874 return offVirtApicWrite;
3875}
3876
3877
3878/**
3879 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3880 *
3881 * @returns The register from the virtual-APIC page.
3882 * @param pVCpu The cross context virtual CPU structure.
3883 * @param offReg The offset of the register being read.
3884 */
3885IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
3886{
3887 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3888 Assert(pVmcs);
3889 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3890 uint32_t const *pbVirtApicPage = (uint32_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
3891 pbVirtApicPage += offReg;
3892 uint32_t const uReg = *pbVirtApicPage;
3893 return uReg;
3894}
3895
3896
3897/**
3898 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3899 *
3900 * @returns The register from the virtual-APIC page.
3901 * @param pVCpu The cross context virtual CPU structure.
3902 * @param offReg The offset of the register being read.
3903 */
3904IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
3905{
3906 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3907 Assert(pVmcs);
3908 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3909 uint64_t const *pbVirtApicPage = (uint64_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
3910 pbVirtApicPage += offReg;
3911 uint64_t const uReg = *pbVirtApicPage;
3912 return uReg;
3913}
3914
3915
3916/**
3917 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3918 *
3919 * @param pVCpu The cross context virtual CPU structure.
3920 * @param offReg The offset of the register being written.
3921 * @param uReg The register value to write.
3922 */
3923IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
3924{
3925 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3926 Assert(pVmcs);
3927 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3928 uint32_t *pbVirtApicPage = (uint32_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
3929 pbVirtApicPage += offReg;
3930 *pbVirtApicPage = uReg;
3931 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = true;
3932}
3933
3934
3935/**
3936 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3937 *
3938 * @param pVCpu The cross context virtual CPU structure.
3939 * @param offReg The offset of the register being written.
3940 * @param uReg The register value to write.
3941 */
3942IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
3943{
3944 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3945 Assert(pVmcs);
3946 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3947 uint64_t *pbVirtApicPage = (uint64_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
3948 pbVirtApicPage += offReg;
3949 *pbVirtApicPage = uReg;
3950 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = true;
3951}
3952
3953
3954/**
3955 * Sets the vector in a virtual-APIC 256-bit sparse register.
3956 *
3957 * @param pVCpu The cross context virtual CPU structure.
3958 * @param offReg The offset of the 256-bit spare register.
3959 * @param uVector The vector to set.
3960 *
3961 * @remarks This is based on our APIC device code.
3962 */
3963IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
3964{
3965 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3966 Assert(pVmcs);
3967
3968 /* Determine the vector offset within the chunk. */
3969 uint32_t uReg;
3970 uint32_t *pbVirtApicPage = (uint32_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
3971 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3972
3973 /* Read the chunk at the offset. */
3974 pbVirtApicPage += offReg + offVector;
3975 uReg = *pbVirtApicPage;
3976
3977 /* Set the vector bit in the chunk. */
3978 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3979 uReg |= RT_BIT(idxVectorBit);
3980
3981 /* Write back the chunk at the offset. */
3982 pbVirtApicPage += offReg + offVector;
3983 *pbVirtApicPage = uReg;
3984
3985 /* Mark the page dirty. */
3986 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = true;
3987}
3988
3989
3990/**
3991 * Clears the vector in a virtual-APIC 256-bit sparse register.
3992 *
3993 * @param pVCpu The cross context virtual CPU structure.
3994 * @param offReg The offset of the 256-bit spare register.
3995 * @param uVector The vector to clear.
3996 *
3997 * @remarks This is based on our APIC device code.
3998 */
3999IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4000{
4001 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4002 Assert(pVmcs);
4003
4004 /* Determine the vector offset within the chunk. */
4005 uint32_t uReg;
4006 uint32_t *pbVirtApicPage = (uint32_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4007 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4008
4009 /* Read the chunk at the offset. */
4010 pbVirtApicPage += offReg + offVector;
4011 uReg = *pbVirtApicPage;
4012
4013 /* Clear the vector bit in the chunk. */
4014 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4015 uReg &= ~RT_BIT(idxVectorBit);
4016
4017 /* Write back the chunk at the offset. */
4018 pbVirtApicPage += offReg + offVector;
4019 *pbVirtApicPage = uReg;
4020
4021 /* Mark the page dirty. */
4022 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = true;
4023}
4024
4025
4026/**
4027 * Checks if a memory access to the APIC-access page must causes an APIC-access
4028 * VM-exit.
4029 *
4030 * @param pVCpu The cross context virtual CPU structure.
4031 * @param offAccess The offset of the register being accessed.
4032 * @param cbAccess The size of the access in bytes.
4033 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4034 * IEM_ACCESS_TYPE_WRITE).
4035 *
4036 * @remarks This must not be used for MSR-based APIC-access page accesses!
4037 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4038 */
4039IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4040{
4041 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4042 Assert(pVmcs);
4043 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4044
4045 /*
4046 * We must cause a VM-exit if any of the following are true:
4047 * - TPR shadowing isn't active.
4048 * - The access size exceeds 32-bits.
4049 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4050 *
4051 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4052 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4053 */
4054 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4055 || cbAccess > sizeof(uint32_t)
4056 || ((offAccess + cbAccess - 1) & 0xc)
4057 || offAccess >= XAPIC_OFF_END + 4)
4058 return true;
4059
4060 /*
4061 * If the access is part of an operation where we have already
4062 * virtualized a virtual-APIC write, we must cause a VM-exit.
4063 */
4064 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4065 return true;
4066
4067 /*
4068 * Check write accesses to the APIC-access page that cause VM-exits.
4069 */
4070 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4071 {
4072 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4073 {
4074 /*
4075 * With APIC-register virtualization, a write access to any of the
4076 * following registers are virtualized. Accessing any other register
4077 * causes a VM-exit.
4078 */
4079 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4080 switch (offAlignedAccess)
4081 {
4082 case XAPIC_OFF_ID:
4083 case XAPIC_OFF_TPR:
4084 case XAPIC_OFF_EOI:
4085 case XAPIC_OFF_LDR:
4086 case XAPIC_OFF_DFR:
4087 case XAPIC_OFF_SVR:
4088 case XAPIC_OFF_ESR:
4089 case XAPIC_OFF_ICR_LO:
4090 case XAPIC_OFF_ICR_HI:
4091 case XAPIC_OFF_LVT_TIMER:
4092 case XAPIC_OFF_LVT_THERMAL:
4093 case XAPIC_OFF_LVT_PERF:
4094 case XAPIC_OFF_LVT_LINT0:
4095 case XAPIC_OFF_LVT_LINT1:
4096 case XAPIC_OFF_LVT_ERROR:
4097 case XAPIC_OFF_TIMER_ICR:
4098 case XAPIC_OFF_TIMER_DCR:
4099 break;
4100 default:
4101 return true;
4102 }
4103 }
4104 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4105 {
4106 /*
4107 * With virtual-interrupt delivery, a write access to any of the
4108 * following registers are virtualized. Accessing any other register
4109 * causes a VM-exit.
4110 *
4111 * Note! The specification does not allow writing to offsets in-between
4112 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4113 */
4114 switch (offAccess)
4115 {
4116 case XAPIC_OFF_TPR:
4117 case XAPIC_OFF_EOI:
4118 case XAPIC_OFF_ICR_LO:
4119 break;
4120 default:
4121 return true;
4122 }
4123 }
4124 else
4125 {
4126 /*
4127 * Without APIC-register virtualization or virtual-interrupt delivery,
4128 * only TPR accesses are virtualized.
4129 */
4130 if (offAccess == XAPIC_OFF_TPR)
4131 { /* likely */ }
4132 else
4133 return true;
4134 }
4135 }
4136 else
4137 {
4138 /*
4139 * Check read accesses to the APIC-access page that cause VM-exits.
4140 */
4141 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4142 {
4143 /*
4144 * With APIC-register virtualization, a read access to any of the
4145 * following registers are virtualized. Accessing any other register
4146 * causes a VM-exit.
4147 */
4148 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4149 switch (offAlignedAccess)
4150 {
4151 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4152 case XAPIC_OFF_ID:
4153 case XAPIC_OFF_VERSION:
4154 case XAPIC_OFF_TPR:
4155 case XAPIC_OFF_EOI:
4156 case XAPIC_OFF_LDR:
4157 case XAPIC_OFF_DFR:
4158 case XAPIC_OFF_SVR:
4159 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4160 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4161 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4162 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4163 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4164 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4165 case XAPIC_OFF_ESR:
4166 case XAPIC_OFF_ICR_LO:
4167 case XAPIC_OFF_ICR_HI:
4168 case XAPIC_OFF_LVT_TIMER:
4169 case XAPIC_OFF_LVT_THERMAL:
4170 case XAPIC_OFF_LVT_PERF:
4171 case XAPIC_OFF_LVT_LINT0:
4172 case XAPIC_OFF_LVT_LINT1:
4173 case XAPIC_OFF_LVT_ERROR:
4174 case XAPIC_OFF_TIMER_ICR:
4175 case XAPIC_OFF_TIMER_DCR:
4176 break;
4177 default:
4178 return true;
4179 }
4180 }
4181 else
4182 {
4183 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4184 if (offAccess == XAPIC_OFF_TPR)
4185 { /* likely */ }
4186 else
4187 return true;
4188 }
4189 }
4190
4191 /* The APIC access is virtualized, does not cause a VM-exit. */
4192 return false;
4193}
4194
4195
4196/**
4197 * Virtualizes a memory-based APIC access where the address is not used to access
4198 * memory.
4199 *
4200 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4201 * page-faults but do not use the address to access memory.
4202 *
4203 * @param pVCpu The cross context virtual CPU structure.
4204 * @param pGCPhysAccess Pointer to the guest-physical address used.
4205 */
4206IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4207{
4208 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4209 Assert(pVmcs);
4210 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4211 Assert(pGCPhysAccess);
4212
4213 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4214 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4215 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4216
4217 if (GCPhysAccess == GCPhysApic)
4218 {
4219 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4220 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4221 uint16_t const cbAccess = 1;
4222 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4223 if (fIntercept)
4224 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4225
4226 *pGCPhysAccess = GCPhysApic | offAccess;
4227 return VINF_VMX_MODIFIES_BEHAVIOR;
4228 }
4229
4230 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4231}
4232
4233
4234/**
4235 * Virtualizes a memory-based APIC access.
4236 *
4237 * @returns VBox strict status code.
4238 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4239 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4240 *
4241 * @param pVCpu The cross context virtual CPU structure.
4242 * @param offAccess The offset of the register being accessed (within the
4243 * APIC-access page).
4244 * @param cbAccess The size of the access in bytes.
4245 * @param pvData Pointer to the data being written or where to store the data
4246 * being read.
4247 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4248 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4249 */
4250IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4251 uint32_t fAccess)
4252{
4253 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4254 Assert(pVmcs);
4255 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4256 Assert(pvData);
4257 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4258 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4259 || (fAccess & IEM_ACCESS_INSTRUCTION));
4260
4261 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4262 if (fIntercept)
4263 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4264
4265 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4266 {
4267 /*
4268 * A write access to the APIC-access page that is virtualized (rather than
4269 * causing a VM-exit) writes data to the virtual-APIC page.
4270 */
4271 uint32_t const u32Data = *(uint32_t *)pvData;
4272 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4273
4274 /*
4275 * Record the currently updated APIC offset, as we need this later for figuring
4276 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4277 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4278 *
4279 * After completion of the current operation, we need to perform TPR virtualization,
4280 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4281 *
4282 * The current operation may be a REP-prefixed string instruction, execution of any
4283 * other instruction, or delivery of an event through the IDT.
4284 *
4285 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4286 * performed now but later after completion of the current operation.
4287 *
4288 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4289 */
4290 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4291 }
4292 else
4293 {
4294 /*
4295 * A read access from the APIC-access page that is virtualized (rather than
4296 * causing a VM-exit) returns data from the virtual-APIC page.
4297 *
4298 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4299 */
4300 Assert(cbAccess <= 4);
4301 Assert(offAccess < XAPIC_OFF_END + 4);
4302 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4303
4304 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4305 u32Data &= s_auAccessSizeMasks[cbAccess];
4306 *(uint32_t *)pvData = u32Data;
4307 }
4308
4309 return VINF_VMX_MODIFIES_BEHAVIOR;
4310}
4311
4312
4313/**
4314 * Virtualizes an MSR-based APIC read access.
4315 *
4316 * @returns VBox strict status code.
4317 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4318 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4319 * handled by the x2APIC device.
4320 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4321 * not within the range of valid MSRs, caller must raise \#GP(0).
4322 * @param pVCpu The cross context virtual CPU structure.
4323 * @param idMsr The x2APIC MSR being read.
4324 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4325 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4326 */
4327IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4328{
4329 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4330 Assert(pVmcs);
4331 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4332 Assert(pu64Value);
4333
4334 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4335 {
4336 /*
4337 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4338 * what the end of the valid x2APIC MSR range is. Hence the use of different
4339 * macros here.
4340 *
4341 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4342 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4343 */
4344 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4345 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4346 {
4347 uint16_t const offReg = (idMsr & 0xff) << 4;
4348 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4349 *pu64Value = u64Value;
4350 return VINF_VMX_MODIFIES_BEHAVIOR;
4351 }
4352 return VERR_OUT_OF_RANGE;
4353 }
4354
4355 if (idMsr == MSR_IA32_X2APIC_TPR)
4356 {
4357 uint16_t const offReg = (idMsr & 0xff) << 4;
4358 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4359 *pu64Value = u64Value;
4360 return VINF_VMX_MODIFIES_BEHAVIOR;
4361 }
4362
4363 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4364}
4365
4366
4367/**
4368 * Virtualizes an MSR-based APIC write access.
4369 *
4370 * @returns VBox strict status code.
4371 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4372 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4373 * not within the range of valid MSRs, caller must raise \#GP(0).
4374 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4375 *
4376 * @param pVCpu The cross context virtual CPU structure.
4377 * @param idMsr The x2APIC MSR being written.
4378 * @param u64Value The value of the x2APIC MSR being written.
4379 */
4380IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4381{
4382 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4383 Assert(pVmcs);
4384
4385 /*
4386 * Check if the access is to be virtualized.
4387 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4388 */
4389 if ( idMsr == MSR_IA32_X2APIC_TPR
4390 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4391 && ( idMsr == MSR_IA32_X2APIC_EOI
4392 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4393 {
4394 /* Validate the MSR write depending on the register. */
4395 switch (idMsr)
4396 {
4397 case MSR_IA32_X2APIC_TPR:
4398 case MSR_IA32_X2APIC_SELF_IPI:
4399 {
4400 if (u64Value & UINT64_C(0xffffffffffffff00))
4401 return VERR_OUT_OF_RANGE;
4402 break;
4403 }
4404 case MSR_IA32_X2APIC_EOI:
4405 {
4406 if (u64Value != 0)
4407 return VERR_OUT_OF_RANGE;
4408 break;
4409 }
4410 }
4411
4412 /* Write the MSR to the virtual-APIC page. */
4413 uint16_t const offReg = (idMsr & 0xff) << 4;
4414 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4415
4416 /*
4417 * Record the currently updated APIC offset, as we need this later for figuring
4418 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4419 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4420 */
4421 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4422
4423 return VINF_VMX_MODIFIES_BEHAVIOR;
4424 }
4425
4426 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4427}
4428
4429
4430/**
4431 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4432 *
4433 * @returns VBox status code.
4434 * @retval VINF_SUCCESS when the highest set bit is found.
4435 * @retval VERR_NOT_FOUND when no bit is set.
4436 *
4437 * @param pVCpu The cross context virtual CPU structure.
4438 * @param offReg The offset of the APIC 256-bit sparse register.
4439 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4440 * set in the register. Only valid when VINF_SUCCESS is
4441 * returned.
4442 *
4443 * @remarks The format of the 256-bit sparse register here mirrors that found in
4444 * real APIC hardware.
4445 */
4446static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4447{
4448 Assert(offReg < XAPIC_OFF_END + 4);
4449 Assert(pidxHighestBit);
4450 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4451
4452 /*
4453 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4454 * However, in each fragment only the first 4 bytes are used.
4455 */
4456 uint8_t const cFrags = 8;
4457 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4458 {
4459 uint16_t const offFrag = iFrag * 16;
4460 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4461 if (!u32Frag)
4462 continue;
4463
4464 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4465 Assert(idxHighestBit > 0);
4466 --idxHighestBit;
4467 Assert(idxHighestBit <= UINT8_MAX);
4468 *pidxHighestBit = idxHighestBit;
4469 return VINF_SUCCESS;
4470 }
4471 return VERR_NOT_FOUND;
4472}
4473
4474
4475/**
4476 * Evaluates pending virtual interrupts.
4477 *
4478 * @param pVCpu The cross context virtual CPU structure.
4479 */
4480IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4481{
4482 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4483 Assert(pVmcs);
4484 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4485
4486 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4487 {
4488 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4489 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4490
4491 if ((uRvi >> 4) > (uPpr >> 4))
4492 {
4493 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4494 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4495 }
4496 else
4497 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4498 }
4499}
4500
4501
4502/**
4503 * Performs PPR virtualization.
4504 *
4505 * @returns VBox strict status code.
4506 * @param pVCpu The cross context virtual CPU structure.
4507 */
4508IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4509{
4510 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4511 Assert(pVmcs);
4512 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4513 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4514
4515 /*
4516 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4517 * or EOI-virtualization.
4518 *
4519 * See Intel spec. 29.1.3 "PPR Virtualization".
4520 */
4521 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4522 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4523
4524 uint32_t uPpr;
4525 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4526 uPpr = uTpr & 0xff;
4527 else
4528 uPpr = uSvi & 0xf0;
4529
4530 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4531 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4532}
4533
4534
4535/**
4536 * Performs VMX TPR virtualization.
4537 *
4538 * @returns VBox strict status code.
4539 * @param pVCpu The cross context virtual CPU structure.
4540 */
4541IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4542{
4543 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4544 Assert(pVmcs);
4545 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4546
4547 /*
4548 * We should have already performed the virtual-APIC write to the TPR offset
4549 * in the virtual-APIC page. We now perform TPR virtualization.
4550 *
4551 * See Intel spec. 29.1.2 "TPR Virtualization".
4552 */
4553 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4554 {
4555 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4556 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4557
4558 /*
4559 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4560 * See Intel spec. 29.1.2 "TPR Virtualization".
4561 */
4562 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4563 {
4564 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4565 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4566 }
4567 }
4568 else
4569 {
4570 iemVmxPprVirtualization(pVCpu);
4571 iemVmxEvalPendingVirtIntrs(pVCpu);
4572 }
4573
4574 return VINF_SUCCESS;
4575}
4576
4577
4578/**
4579 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4580 * not.
4581 *
4582 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4583 * @param pVCpu The cross context virtual CPU structure.
4584 * @param uVector The interrupt that was acknowledged using an EOI.
4585 */
4586IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4587{
4588 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4589 Assert(pVmcs);
4590 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4591
4592 if (uVector < 64)
4593 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4594 if (uVector < 128)
4595 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4596 if (uVector < 192)
4597 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4598 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4599}
4600
4601
4602/**
4603 * Performs EOI virtualization.
4604 *
4605 * @returns VBox strict status code.
4606 * @param pVCpu The cross context virtual CPU structure.
4607 */
4608IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4609{
4610 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4611 Assert(pVmcs);
4612 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4613
4614 /*
4615 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4616 * and get the next guest-interrupt that's in-service (if any).
4617 *
4618 * See Intel spec. 29.1.4 "EOI Virtualization".
4619 */
4620 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4621 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4622 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4623
4624 uint8_t uVector = uSvi;
4625 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4626
4627 uVector = 0;
4628 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4629
4630 if (uVector)
4631 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4632 else
4633 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4634
4635 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4636 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4637
4638 iemVmxPprVirtualization(pVCpu);
4639 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4640 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4641 iemVmxEvalPendingVirtIntrs(pVCpu);
4642 return VINF_SUCCESS;
4643}
4644
4645
4646/**
4647 * Performs self-IPI virtualization.
4648 *
4649 * @returns VBox strict status code.
4650 * @param pVCpu The cross context virtual CPU structure.
4651 */
4652IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4653{
4654 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4655 Assert(pVmcs);
4656 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4657
4658 /*
4659 * We should have already performed the virtual-APIC write to the self-IPI offset
4660 * in the virtual-APIC page. We now perform self-IPI virtualization.
4661 *
4662 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4663 */
4664 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4665 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4666 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4667 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4668 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4669 if (uVector > uRvi)
4670 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4671 iemVmxEvalPendingVirtIntrs(pVCpu);
4672 return VINF_SUCCESS;
4673}
4674
4675
4676/**
4677 * Performs VMX APIC-write emulation.
4678 *
4679 * @returns VBox strict status code.
4680 * @param pVCpu The cross context virtual CPU structure.
4681 */
4682IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
4683{
4684 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4685 Assert(pVmcs);
4686
4687 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4688 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4689
4690 /*
4691 * Perform APIC-write emulation based on the virtual-APIC register written.
4692 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4693 */
4694 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4695 VBOXSTRICTRC rcStrict;
4696 switch (offApicWrite)
4697 {
4698 case XAPIC_OFF_TPR:
4699 {
4700 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4701 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4702 uTpr &= UINT32_C(0x000000ff);
4703 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4704 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4705 rcStrict = iemVmxTprVirtualization(pVCpu);
4706 break;
4707 }
4708
4709 case XAPIC_OFF_EOI:
4710 {
4711 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4712 {
4713 /* Clear VEOI and perform EOI virtualization. */
4714 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4715 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4716 rcStrict = iemVmxEoiVirtualization(pVCpu);
4717 }
4718 else
4719 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4720 break;
4721 }
4722
4723 case XAPIC_OFF_ICR_LO:
4724 {
4725 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4726 {
4727 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4728 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4729 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4730 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4731 if ( !(uIcrLo & fIcrLoMb0)
4732 && (uIcrLo & fIcrLoMb1))
4733 {
4734 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4735 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4736 }
4737 else
4738 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4739 }
4740 else
4741 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4742 break;
4743 }
4744
4745 case XAPIC_OFF_ICR_HI:
4746 {
4747 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4748 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4749 uIcrHi &= UINT32_C(0xff000000);
4750 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4751 rcStrict = VINF_SUCCESS;
4752 break;
4753 }
4754
4755 default:
4756 {
4757 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4758 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4759 break;
4760 }
4761 }
4762
4763 return rcStrict;
4764}
4765
4766
4767/**
4768 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4769 *
4770 * @param pVCpu The cross context virtual CPU structure.
4771 * @param pszInstr The VMX instruction name (for logging purposes).
4772 */
4773IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
4774{
4775 /*
4776 * Guest Control Registers, Debug Registers, and MSRs.
4777 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4778 */
4779 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4780 const char *const pszFailure = "VM-exit";
4781 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4782
4783 /* CR0 reserved bits. */
4784 {
4785 /* CR0 MB1 bits. */
4786 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4787 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4788 if (fUnrestrictedGuest)
4789 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4790 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4791 { /* likely */ }
4792 else
4793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4794
4795 /* CR0 MBZ bits. */
4796 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4797 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4798 { /* likely */ }
4799 else
4800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4801
4802 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4803 if ( !fUnrestrictedGuest
4804 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4805 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4806 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4807 }
4808
4809 /* CR4 reserved bits. */
4810 {
4811 /* CR4 MB1 bits. */
4812 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4813 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4814 { /* likely */ }
4815 else
4816 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4817
4818 /* CR4 MBZ bits. */
4819 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4820 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4821 { /* likely */ }
4822 else
4823 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4824 }
4825
4826 /* DEBUGCTL MSR. */
4827 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4828 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4829 { /* likely */ }
4830 else
4831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4832
4833 /* 64-bit CPU checks. */
4834 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4835 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4836 {
4837 if (fGstInLongMode)
4838 {
4839 /* PAE must be set. */
4840 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4841 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4842 { /* likely */ }
4843 else
4844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4845 }
4846 else
4847 {
4848 /* PCIDE should not be set. */
4849 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4850 { /* likely */ }
4851 else
4852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4853 }
4854
4855 /* CR3. */
4856 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4857 { /* likely */ }
4858 else
4859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4860
4861 /* DR7. */
4862 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4863 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4864 { /* likely */ }
4865 else
4866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4867
4868 /* SYSENTER ESP and SYSENTER EIP. */
4869 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4870 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4871 { /* likely */ }
4872 else
4873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4874 }
4875
4876 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4877 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4878
4879 /* PAT MSR. */
4880 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4881 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4882 { /* likely */ }
4883 else
4884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4885
4886 /* EFER MSR. */
4887 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4888 {
4889 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4890 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4891 { /* likely */ }
4892 else
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4894
4895 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4896 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4897 if ( fGstLma == fGstInLongMode
4898 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4899 || fGstLma == fGstLme))
4900 { /* likely */ }
4901 else
4902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4903 }
4904
4905 /* We don't support IA32_BNDCFGS MSR yet. */
4906 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4907
4908 NOREF(pszInstr);
4909 NOREF(pszFailure);
4910 return VINF_SUCCESS;
4911}
4912
4913
4914/**
4915 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4916 *
4917 * @param pVCpu The cross context virtual CPU structure.
4918 * @param pszInstr The VMX instruction name (for logging purposes).
4919 */
4920IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
4921{
4922 /*
4923 * Segment registers.
4924 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4925 */
4926 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4927 const char *const pszFailure = "VM-exit";
4928 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4929 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4930 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4931
4932 /* Selectors. */
4933 if ( !fGstInV86Mode
4934 && !fUnrestrictedGuest
4935 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4936 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4937
4938 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4939 {
4940 CPUMSELREG SelReg;
4941 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4942 if (RT_LIKELY(rc == VINF_SUCCESS))
4943 { /* likely */ }
4944 else
4945 return rc;
4946
4947 /*
4948 * Virtual-8086 mode checks.
4949 */
4950 if (fGstInV86Mode)
4951 {
4952 /* Base address. */
4953 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4954 { /* likely */ }
4955 else
4956 {
4957 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4958 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4959 }
4960
4961 /* Limit. */
4962 if (SelReg.u32Limit == 0xffff)
4963 { /* likely */ }
4964 else
4965 {
4966 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4968 }
4969
4970 /* Attribute. */
4971 if (SelReg.Attr.u == 0xf3)
4972 { /* likely */ }
4973 else
4974 {
4975 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4977 }
4978
4979 /* We're done; move to checking the next segment. */
4980 continue;
4981 }
4982
4983 /* Checks done by 64-bit CPUs. */
4984 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4985 {
4986 /* Base address. */
4987 if ( iSegReg == X86_SREG_FS
4988 || iSegReg == X86_SREG_GS)
4989 {
4990 if (X86_IS_CANONICAL(SelReg.u64Base))
4991 { /* likely */ }
4992 else
4993 {
4994 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4996 }
4997 }
4998 else if (iSegReg == X86_SREG_CS)
4999 {
5000 if (!RT_HI_U32(SelReg.u64Base))
5001 { /* likely */ }
5002 else
5003 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5004 }
5005 else
5006 {
5007 if ( SelReg.Attr.n.u1Unusable
5008 || !RT_HI_U32(SelReg.u64Base))
5009 { /* likely */ }
5010 else
5011 {
5012 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5014 }
5015 }
5016 }
5017
5018 /*
5019 * Checks outside Virtual-8086 mode.
5020 */
5021 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5022 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5023 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5024 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5025 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5026 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5027 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5028 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5029
5030 /* Code or usable segment. */
5031 if ( iSegReg == X86_SREG_CS
5032 || fUsable)
5033 {
5034 /* Reserved bits (bits 31:17 and bits 11:8). */
5035 if (!(SelReg.Attr.u & 0xfffe0f00))
5036 { /* likely */ }
5037 else
5038 {
5039 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5041 }
5042
5043 /* Descriptor type. */
5044 if (fCodeDataSeg)
5045 { /* likely */ }
5046 else
5047 {
5048 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5050 }
5051
5052 /* Present. */
5053 if (fPresent)
5054 { /* likely */ }
5055 else
5056 {
5057 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5059 }
5060
5061 /* Granularity. */
5062 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5063 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5064 { /* likely */ }
5065 else
5066 {
5067 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5069 }
5070 }
5071
5072 if (iSegReg == X86_SREG_CS)
5073 {
5074 /* Segment Type and DPL. */
5075 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5076 && fUnrestrictedGuest)
5077 {
5078 if (uDpl == 0)
5079 { /* likely */ }
5080 else
5081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5082 }
5083 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5084 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5085 {
5086 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5087 if (uDpl == AttrSs.n.u2Dpl)
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5091 }
5092 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5093 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5094 {
5095 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5096 if (uDpl <= AttrSs.n.u2Dpl)
5097 { /* likely */ }
5098 else
5099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5100 }
5101 else
5102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5103
5104 /* Def/Big. */
5105 if ( fGstInLongMode
5106 && fSegLong)
5107 {
5108 if (uDefBig == 0)
5109 { /* likely */ }
5110 else
5111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5112 }
5113 }
5114 else if (iSegReg == X86_SREG_SS)
5115 {
5116 /* Segment Type. */
5117 if ( !fUsable
5118 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5119 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5120 { /* likely */ }
5121 else
5122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5123
5124 /* DPL. */
5125 if (!fUnrestrictedGuest)
5126 {
5127 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5131 }
5132 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5133 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5134 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5135 {
5136 if (uDpl == 0)
5137 { /* likely */ }
5138 else
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5140 }
5141 }
5142 else
5143 {
5144 /* DS, ES, FS, GS. */
5145 if (fUsable)
5146 {
5147 /* Segment type. */
5148 if (uSegType & X86_SEL_TYPE_ACCESSED)
5149 { /* likely */ }
5150 else
5151 {
5152 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5154 }
5155
5156 if ( !(uSegType & X86_SEL_TYPE_CODE)
5157 || (uSegType & X86_SEL_TYPE_READ))
5158 { /* likely */ }
5159 else
5160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5161
5162 /* DPL. */
5163 if ( !fUnrestrictedGuest
5164 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5165 {
5166 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5167 { /* likely */ }
5168 else
5169 {
5170 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5172 }
5173 }
5174 }
5175 }
5176 }
5177
5178 /*
5179 * LDTR.
5180 */
5181 {
5182 CPUMSELREG Ldtr;
5183 Ldtr.Sel = pVmcs->GuestLdtr;
5184 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5185 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5186 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5187
5188 if (!Ldtr.Attr.n.u1Unusable)
5189 {
5190 /* Selector. */
5191 if (!(Ldtr.Sel & X86_SEL_LDT))
5192 { /* likely */ }
5193 else
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5195
5196 /* Base. */
5197 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5198 {
5199 if (X86_IS_CANONICAL(Ldtr.u64Base))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5203 }
5204
5205 /* Attributes. */
5206 /* Reserved bits (bits 31:17 and bits 11:8). */
5207 if (!(Ldtr.Attr.u & 0xfffe0f00))
5208 { /* likely */ }
5209 else
5210 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5211
5212 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5216
5217 if (!Ldtr.Attr.n.u1DescType)
5218 { /* likely */ }
5219 else
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5221
5222 if (Ldtr.Attr.n.u1Present)
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5226
5227 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5228 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5229 { /* likely */ }
5230 else
5231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5232 }
5233 }
5234
5235 /*
5236 * TR.
5237 */
5238 {
5239 CPUMSELREG Tr;
5240 Tr.Sel = pVmcs->GuestTr;
5241 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5242 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5243 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5244
5245 /* Selector. */
5246 if (!(Tr.Sel & X86_SEL_LDT))
5247 { /* likely */ }
5248 else
5249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5250
5251 /* Base. */
5252 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5253 {
5254 if (X86_IS_CANONICAL(Tr.u64Base))
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5258 }
5259
5260 /* Attributes. */
5261 /* Reserved bits (bits 31:17 and bits 11:8). */
5262 if (!(Tr.Attr.u & 0xfffe0f00))
5263 { /* likely */ }
5264 else
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5266
5267 if (!Tr.Attr.n.u1Unusable)
5268 { /* likely */ }
5269 else
5270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5271
5272 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5273 || ( !fGstInLongMode
5274 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5275 { /* likely */ }
5276 else
5277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5278
5279 if (!Tr.Attr.n.u1DescType)
5280 { /* likely */ }
5281 else
5282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5283
5284 if (Tr.Attr.n.u1Present)
5285 { /* likely */ }
5286 else
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5288
5289 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5290 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5291 { /* likely */ }
5292 else
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5294 }
5295
5296 NOREF(pszInstr);
5297 NOREF(pszFailure);
5298 return VINF_SUCCESS;
5299}
5300
5301
5302/**
5303 * Checks guest GDTR and IDTR as part of VM-entry.
5304 *
5305 * @param pVCpu The cross context virtual CPU structure.
5306 * @param pszInstr The VMX instruction name (for logging purposes).
5307 */
5308IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5309{
5310 /*
5311 * GDTR and IDTR.
5312 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5313 */
5314 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5315 const char *const pszFailure = "VM-exit";
5316
5317 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5318 {
5319 /* Base. */
5320 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5321 { /* likely */ }
5322 else
5323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5324
5325 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5326 { /* likely */ }
5327 else
5328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5329 }
5330
5331 /* Limit. */
5332 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5333 { /* likely */ }
5334 else
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5336
5337 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5338 { /* likely */ }
5339 else
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5341
5342 NOREF(pszInstr);
5343 NOREF(pszFailure);
5344 return VINF_SUCCESS;
5345}
5346
5347
5348/**
5349 * Checks guest RIP and RFLAGS as part of VM-entry.
5350 *
5351 * @param pVCpu The cross context virtual CPU structure.
5352 * @param pszInstr The VMX instruction name (for logging purposes).
5353 */
5354IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5355{
5356 /*
5357 * RIP and RFLAGS.
5358 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5359 */
5360 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5361 const char *const pszFailure = "VM-exit";
5362 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5363
5364 /* RIP. */
5365 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5366 {
5367 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5368 if ( !fGstInLongMode
5369 || !AttrCs.n.u1Long)
5370 {
5371 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5372 { /* likely */ }
5373 else
5374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5375 }
5376
5377 if ( fGstInLongMode
5378 && AttrCs.n.u1Long)
5379 {
5380 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5381 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5382 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5383 { /* likely */ }
5384 else
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5386 }
5387 }
5388
5389 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5390 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5391 : pVmcs->u64GuestRFlags.s.Lo;
5392 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5393 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5394 { /* likely */ }
5395 else
5396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5397
5398 if ( fGstInLongMode
5399 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5400 {
5401 if (!(uGuestRFlags & X86_EFL_VM))
5402 { /* likely */ }
5403 else
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5405 }
5406
5407 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5408 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5409 {
5410 if (uGuestRFlags & X86_EFL_IF)
5411 { /* likely */ }
5412 else
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5414 }
5415
5416 NOREF(pszInstr);
5417 NOREF(pszFailure);
5418 return VINF_SUCCESS;
5419}
5420
5421
5422/**
5423 * Checks guest non-register state as part of VM-entry.
5424 *
5425 * @param pVCpu The cross context virtual CPU structure.
5426 * @param pszInstr The VMX instruction name (for logging purposes).
5427 */
5428IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5429{
5430 /*
5431 * Guest non-register state.
5432 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5433 */
5434 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5435 const char *const pszFailure = "VM-exit";
5436
5437 /*
5438 * Activity state.
5439 */
5440 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5441 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5442 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5446
5447 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5448 if ( !AttrSs.n.u2Dpl
5449 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5450 { /* likely */ }
5451 else
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5453
5454 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5455 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5456 {
5457 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5458 { /* likely */ }
5459 else
5460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5461 }
5462
5463 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5464 {
5465 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5466 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5467 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5468 switch (pVmcs->u32GuestActivityState)
5469 {
5470 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5471 {
5472 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5473 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5474 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5475 && ( uVector == X86_XCPT_DB
5476 || uVector == X86_XCPT_MC))
5477 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5478 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5479 { /* likely */ }
5480 else
5481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5482 break;
5483 }
5484
5485 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5486 {
5487 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5488 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5489 && uVector == X86_XCPT_MC))
5490 { /* likely */ }
5491 else
5492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5493 break;
5494 }
5495
5496 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5497 default:
5498 break;
5499 }
5500 }
5501
5502 /*
5503 * Interruptibility state.
5504 */
5505 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5506 { /* likely */ }
5507 else
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5509
5510 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5511 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5512 { /* likely */ }
5513 else
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5515
5516 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5517 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5518 { /* likely */ }
5519 else
5520 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5521
5522 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5523 {
5524 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5525 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5526 {
5527 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5528 { /* likely */ }
5529 else
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5531 }
5532 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5533 {
5534 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5535 { /* likely */ }
5536 else
5537 {
5538 /*
5539 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5540 * We update the Exit qualification only when blocking-by-STI is set
5541 * without blocking-by-MovSS being set. Although in practise it does not
5542 * make much difference since the order of checks are implementation defined.
5543 */
5544 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5545 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5547 }
5548
5549 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5550 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5554 }
5555 }
5556
5557 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5558 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5562
5563 /* We don't support SGX yet. So enclave-interruption must not be set. */
5564 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5565 { /* likely */ }
5566 else
5567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5568
5569 /*
5570 * Pending debug exceptions.
5571 */
5572 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5573 ? pVmcs->u64GuestPendingDbgXcpt.u
5574 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5575 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5579
5580 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5581 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5582 {
5583 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5584 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5585 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5587
5588 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5589 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5590 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5592 }
5593
5594 /* We don't support RTM (Real-time Transactional Memory) yet. */
5595 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5596 { /* likely */ }
5597 else
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5599
5600 /*
5601 * VMCS link pointer.
5602 */
5603 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5604 {
5605 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5606 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5607 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5608 { /* likely */ }
5609 else
5610 {
5611 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5613 }
5614
5615 /* Validate the address. */
5616 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5617 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5618 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5619 { /* likely */ }
5620 else
5621 {
5622 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5624 }
5625
5626 /* Read the VMCS-link pointer from guest memory. */
5627 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5628 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5629 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5630 if (RT_SUCCESS(rc))
5631 { /* likely */ }
5632 else
5633 {
5634 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5636 }
5637
5638 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5639 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5640 { /* likely */ }
5641 else
5642 {
5643 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5645 }
5646
5647 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5648 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5649 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5650 { /* likely */ }
5651 else
5652 {
5653 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5655 }
5656
5657 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5658 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5659 }
5660
5661 NOREF(pszInstr);
5662 NOREF(pszFailure);
5663 return VINF_SUCCESS;
5664}
5665
5666
5667/**
5668 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5669 * VM-entry.
5670 *
5671 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5672 * @param pVCpu The cross context virtual CPU structure.
5673 * @param pszInstr The VMX instruction name (for logging purposes).
5674 * @param pVmcs Pointer to the virtual VMCS.
5675 */
5676IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5677{
5678 /*
5679 * Check PDPTEs.
5680 * See Intel spec. 4.4.1 "PDPTE Registers".
5681 */
5682 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5683 const char *const pszFailure = "VM-exit";
5684
5685 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5686 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5687 if (RT_SUCCESS(rc))
5688 {
5689 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5690 {
5691 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5692 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5693 { /* likely */ }
5694 else
5695 {
5696 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5697 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5699 }
5700 }
5701 }
5702 else
5703 {
5704 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5706 }
5707
5708 NOREF(pszFailure);
5709 NOREF(pszInstr);
5710 return rc;
5711}
5712
5713
5714/**
5715 * Checks guest PDPTEs as part of VM-entry.
5716 *
5717 * @param pVCpu The cross context virtual CPU structure.
5718 * @param pszInstr The VMX instruction name (for logging purposes).
5719 */
5720IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
5721{
5722 /*
5723 * Guest PDPTEs.
5724 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5725 */
5726 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5727 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5728
5729 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5730 int rc;
5731 if ( !fGstInLongMode
5732 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5733 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5734 {
5735 /*
5736 * We don't support nested-paging for nested-guests yet.
5737 *
5738 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5739 * rather we need to check the PDPTEs referenced by the guest CR3.
5740 */
5741 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5742 }
5743 else
5744 rc = VINF_SUCCESS;
5745 return rc;
5746}
5747
5748
5749/**
5750 * Checks guest-state as part of VM-entry.
5751 *
5752 * @returns VBox status code.
5753 * @param pVCpu The cross context virtual CPU structure.
5754 * @param pszInstr The VMX instruction name (for logging purposes).
5755 */
5756IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
5757{
5758 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5759 if (RT_SUCCESS(rc))
5760 {
5761 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5762 if (RT_SUCCESS(rc))
5763 {
5764 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5765 if (RT_SUCCESS(rc))
5766 {
5767 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5768 if (RT_SUCCESS(rc))
5769 {
5770 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5771 if (RT_SUCCESS(rc))
5772 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5773 }
5774 }
5775 }
5776 }
5777 return rc;
5778}
5779
5780
5781/**
5782 * Checks host-state as part of VM-entry.
5783 *
5784 * @returns VBox status code.
5785 * @param pVCpu The cross context virtual CPU structure.
5786 * @param pszInstr The VMX instruction name (for logging purposes).
5787 */
5788IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
5789{
5790 /*
5791 * Host Control Registers and MSRs.
5792 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5793 */
5794 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5795 const char * const pszFailure = "VMFail";
5796
5797 /* CR0 reserved bits. */
5798 {
5799 /* CR0 MB1 bits. */
5800 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5801 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5805
5806 /* CR0 MBZ bits. */
5807 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5808 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5812 }
5813
5814 /* CR4 reserved bits. */
5815 {
5816 /* CR4 MB1 bits. */
5817 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5818 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5819 { /* likely */ }
5820 else
5821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5822
5823 /* CR4 MBZ bits. */
5824 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5825 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5826 { /* likely */ }
5827 else
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5829 }
5830
5831 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5832 {
5833 /* CR3 reserved bits. */
5834 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5838
5839 /* SYSENTER ESP and SYSENTER EIP. */
5840 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5841 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5845 }
5846
5847 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5848 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5849
5850 /* PAT MSR. */
5851 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5852 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5856
5857 /* EFER MSR. */
5858 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5859 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5860 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5861 { /* likely */ }
5862 else
5863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5864
5865 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5866 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5867 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5868 if ( fHostInLongMode == fHostLma
5869 && fHostInLongMode == fHostLme)
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5873
5874 /*
5875 * Host Segment and Descriptor-Table Registers.
5876 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5877 */
5878 /* Selector RPL and TI. */
5879 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5880 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5881 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5882 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5883 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5884 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5885 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5886 { /* likely */ }
5887 else
5888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5889
5890 /* CS and TR selectors cannot be 0. */
5891 if ( pVmcs->HostCs
5892 && pVmcs->HostTr)
5893 { /* likely */ }
5894 else
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5896
5897 /* SS cannot be 0 if 32-bit host. */
5898 if ( fHostInLongMode
5899 || pVmcs->HostSs)
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5903
5904 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5905 {
5906 /* FS, GS, GDTR, IDTR, TR base address. */
5907 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5908 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5909 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5910 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5911 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5912 { /* likely */ }
5913 else
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5915 }
5916
5917 /*
5918 * Host address-space size for 64-bit CPUs.
5919 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5920 */
5921 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5922 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5923 {
5924 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5925
5926 /* Logical processor in IA-32e mode. */
5927 if (fCpuInLongMode)
5928 {
5929 if (fHostInLongMode)
5930 {
5931 /* PAE must be set. */
5932 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5933 { /* likely */ }
5934 else
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5936
5937 /* RIP must be canonical. */
5938 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5942 }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5945 }
5946 else
5947 {
5948 /* Logical processor is outside IA-32e mode. */
5949 if ( !fGstInLongMode
5950 && !fHostInLongMode)
5951 {
5952 /* PCIDE should not be set. */
5953 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5954 { /* likely */ }
5955 else
5956 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5957
5958 /* The high 32-bits of RIP MBZ. */
5959 if (!pVmcs->u64HostRip.s.Hi)
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5963 }
5964 else
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5966 }
5967 }
5968 else
5969 {
5970 /* Host address-space size for 32-bit CPUs. */
5971 if ( !fGstInLongMode
5972 && !fHostInLongMode)
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5976 }
5977
5978 NOREF(pszInstr);
5979 NOREF(pszFailure);
5980 return VINF_SUCCESS;
5981}
5982
5983
5984/**
5985 * Checks VM-entry controls fields as part of VM-entry.
5986 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
5987 *
5988 * @returns VBox status code.
5989 * @param pVCpu The cross context virtual CPU structure.
5990 * @param pszInstr The VMX instruction name (for logging purposes).
5991 */
5992IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
5993{
5994 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5995 const char * const pszFailure = "VMFail";
5996
5997 /* VM-entry controls. */
5998 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
5999 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6003
6004 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6005 { /* likely */ }
6006 else
6007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6008
6009 /* Event injection. */
6010 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6011 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6012 {
6013 /* Type and vector. */
6014 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6015 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6016 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6017 if ( !uRsvd
6018 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6019 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6020 { /* likely */ }
6021 else
6022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6023
6024 /* Exception error code. */
6025 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6026 {
6027 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6028 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6029 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6030 { /* likely */ }
6031 else
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6033
6034 /* Exceptions that provide an error code. */
6035 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6036 && ( uVector == X86_XCPT_DF
6037 || uVector == X86_XCPT_TS
6038 || uVector == X86_XCPT_NP
6039 || uVector == X86_XCPT_SS
6040 || uVector == X86_XCPT_GP
6041 || uVector == X86_XCPT_PF
6042 || uVector == X86_XCPT_AC))
6043 { /* likely */ }
6044 else
6045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6046
6047 /* Exception error-code reserved bits. */
6048 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6049 { /* likely */ }
6050 else
6051 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6052
6053 /* Injecting a software interrupt, software exception or privileged software exception. */
6054 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6055 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6056 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6057 {
6058 /* Instruction length must be in the range 0-15. */
6059 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6060 { /* likely */ }
6061 else
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6063
6064 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6065 if ( pVmcs->u32EntryInstrLen == 0
6066 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6068 }
6069 }
6070 }
6071
6072 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6073 if (pVmcs->u32EntryMsrLoadCount)
6074 {
6075 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6076 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6077 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6078 { /* likely */ }
6079 else
6080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6081 }
6082
6083 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6084 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6085
6086 NOREF(pszInstr);
6087 NOREF(pszFailure);
6088 return VINF_SUCCESS;
6089}
6090
6091
6092/**
6093 * Checks VM-exit controls fields as part of VM-entry.
6094 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6095 *
6096 * @returns VBox status code.
6097 * @param pVCpu The cross context virtual CPU structure.
6098 * @param pszInstr The VMX instruction name (for logging purposes).
6099 */
6100IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6101{
6102 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6103 const char * const pszFailure = "VMFail";
6104
6105 /* VM-exit controls. */
6106 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6107 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6108 { /* likely */ }
6109 else
6110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6111
6112 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6113 { /* likely */ }
6114 else
6115 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6116
6117 /* Save preemption timer without activating it. */
6118 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6119 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6120 { /* likely */ }
6121 else
6122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6123
6124 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6125 if (pVmcs->u32ExitMsrStoreCount)
6126 {
6127 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6128 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6129 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6133 }
6134
6135 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6136 if (pVmcs->u32ExitMsrLoadCount)
6137 {
6138 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6139 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6140 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6141 { /* likely */ }
6142 else
6143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6144 }
6145
6146 NOREF(pszInstr);
6147 NOREF(pszFailure);
6148 return VINF_SUCCESS;
6149}
6150
6151
6152/**
6153 * Checks VM-execution controls fields as part of VM-entry.
6154 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6155 *
6156 * @returns VBox status code.
6157 * @param pVCpu The cross context virtual CPU structure.
6158 * @param pszInstr The VMX instruction name (for logging purposes).
6159 *
6160 * @remarks This may update secondary-processor based VM-execution control fields
6161 * in the current VMCS if necessary.
6162 */
6163IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6164{
6165 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6166 const char * const pszFailure = "VMFail";
6167
6168 /* Pin-based VM-execution controls. */
6169 {
6170 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6171 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6172 { /* likely */ }
6173 else
6174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6175
6176 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6177 { /* likely */ }
6178 else
6179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6180 }
6181
6182 /* Processor-based VM-execution controls. */
6183 {
6184 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6185 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6186 { /* likely */ }
6187 else
6188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6189
6190 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6191 { /* likely */ }
6192 else
6193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6194 }
6195
6196 /* Secondary processor-based VM-execution controls. */
6197 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6198 {
6199 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6200 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6201 { /* likely */ }
6202 else
6203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6204
6205 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6209 }
6210 else
6211 Assert(!pVmcs->u32ProcCtls2);
6212
6213 /* CR3-target count. */
6214 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6215 { /* likely */ }
6216 else
6217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6218
6219 /* I/O bitmaps physical addresses. */
6220 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6221 {
6222 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6223 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6224 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6225 { /* likely */ }
6226 else
6227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6228
6229 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6230 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6231 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6232 { /* likely */ }
6233 else
6234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6235 }
6236
6237 /* MSR bitmap physical address. */
6238 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6239 {
6240 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6241 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6242 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6243 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6247
6248 /* Read the MSR bitmap. */
6249 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6250 * implementing fast path. */
6251 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6252 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6253 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6254 if (RT_SUCCESS(rc))
6255 { /* likely */ }
6256 else
6257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6258 }
6259
6260 /* TPR shadow related controls. */
6261 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6262 {
6263 /* Virtual-APIC page physical address. */
6264 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6265 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6266 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6267 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6268 { /* likely */ }
6269 else
6270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6271
6272 /* Read the virtual-APIC page. */
6273 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6274 GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
6275 if (RT_SUCCESS(rc))
6276 { /* likely */ }
6277 else
6278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6279
6280 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6281 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6282 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6286
6287 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6288 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6289 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6290 {
6291 /* Read the VTPR from the virtual-APIC page. */
6292 uint8_t const *pbVirtApicPage = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6293 pbVirtApicPage += XAPIC_OFF_TPR;
6294 uint8_t const u8VTpr = *pbVirtApicPage;
6295
6296 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6297 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6298 { /* likely */ }
6299 else
6300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6301 }
6302 }
6303 else
6304 {
6305 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6306 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6307 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6308 { /* likely */ }
6309 else
6310 {
6311 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6313 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6315 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6317 }
6318 }
6319
6320 /* NMI exiting and virtual-NMIs. */
6321 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6322 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6326
6327 /* Virtual-NMIs and NMI-window exiting. */
6328 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6329 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6330 { /* likely */ }
6331 else
6332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6333
6334 /* Virtualize APIC accesses. */
6335 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6336 {
6337 /* APIC-access physical address. */
6338 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6339 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6340 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6341 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6342 { /* likely */ }
6343 else
6344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6345
6346 /*
6347 * Disallow APIC-access page and virtual-APIC page from being the same address.
6348 * Note! This is not an Intel requirement, but one imposed by our implementation.
6349 */
6350 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6351 * redirecting accesses between the APIC-access page and the virtual-APIC
6352 * page. If any guest hypervisor requires this, we can implement it later. */
6353 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6354 {
6355 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6356 if (GCPhysVirtApic != GCPhysApicAccess)
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6360 }
6361
6362 /*
6363 * Register the handler for the APIC-access page.
6364 *
6365 * We don't deregister the APIC-access page handler during the VM-exit as a different
6366 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6367 *
6368 * We leave the page registered until the first access that happens outside VMX non-root
6369 * mode. Guest software is allowed to access structures such as the APIC-access page
6370 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6371 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6372 *
6373 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6374 */
6375 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6376 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6377 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6378 if (RT_SUCCESS(rc))
6379 { /* likely */ }
6380 else
6381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6382 }
6383
6384 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6385 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6386 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6387 { /* likely */ }
6388 else
6389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6390
6391 /* Virtual-interrupt delivery requires external interrupt exiting. */
6392 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6393 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6394 { /* likely */ }
6395 else
6396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6397
6398 /* VPID. */
6399 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6400 || pVmcs->u16Vpid != 0)
6401 { /* likely */ }
6402 else
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6404
6405 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6406 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6407 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6408 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6409 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6410 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6411 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6412
6413 /* VMCS shadowing. */
6414 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6415 {
6416 /* VMREAD-bitmap physical address. */
6417 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6418 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6419 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6420 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6421 { /* likely */ }
6422 else
6423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6424
6425 /* VMWRITE-bitmap physical address. */
6426 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6427 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6428 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6429 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6430 { /* likely */ }
6431 else
6432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6433
6434 /* Read the VMREAD-bitmap. */
6435 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6436 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6437 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6438 if (RT_SUCCESS(rc))
6439 { /* likely */ }
6440 else
6441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6442
6443 /* Read the VMWRITE-bitmap. */
6444 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6445 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6446 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6447 if (RT_SUCCESS(rc))
6448 { /* likely */ }
6449 else
6450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6451 }
6452
6453 NOREF(pszInstr);
6454 NOREF(pszFailure);
6455 return VINF_SUCCESS;
6456}
6457
6458
6459/**
6460 * Loads the guest control registers, debug register and some MSRs as part of
6461 * VM-entry.
6462 *
6463 * @param pVCpu The cross context virtual CPU structure.
6464 */
6465IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6466{
6467 /*
6468 * Load guest control registers, debug registers and MSRs.
6469 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6470 */
6471 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6472
6473 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6474 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6475 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6476 CPUMSetGuestCR0(pVCpu, uGstCr0);
6477 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6478 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6479
6480 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6481 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6482
6483 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6484 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6485 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6486
6487 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6488 {
6489 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6490
6491 /* EFER MSR. */
6492 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6493 {
6494 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6495 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6496 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6497 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6498 if (fGstInLongMode)
6499 {
6500 /* If the nested-guest is in long mode, LMA and LME are both set. */
6501 Assert(fGstPaging);
6502 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6503 }
6504 else
6505 {
6506 /*
6507 * If the nested-guest is outside long mode:
6508 * - With paging: LMA is cleared, LME is cleared.
6509 * - Without paging: LMA is cleared, LME is left unmodified.
6510 */
6511 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6512 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6513 }
6514 }
6515 /* else: see below. */
6516 }
6517
6518 /* PAT MSR. */
6519 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6520 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6521
6522 /* EFER MSR. */
6523 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6524 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6525
6526 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6527 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6528
6529 /* We don't support IA32_BNDCFGS MSR yet. */
6530 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6531
6532 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6533}
6534
6535
6536/**
6537 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6538 *
6539 * @param pVCpu The cross context virtual CPU structure.
6540 */
6541IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6542{
6543 /*
6544 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6545 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6546 */
6547 /* CS, SS, ES, DS, FS, GS. */
6548 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6549 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6550 {
6551 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6552 CPUMSELREG VmcsSelReg;
6553 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6554 AssertRC(rc); NOREF(rc);
6555 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6556 {
6557 pGstSelReg->Sel = VmcsSelReg.Sel;
6558 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6559 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6560 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6561 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6562 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6563 }
6564 else
6565 {
6566 pGstSelReg->Sel = VmcsSelReg.Sel;
6567 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6568 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6569 switch (iSegReg)
6570 {
6571 case X86_SREG_CS:
6572 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6573 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6574 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6575 break;
6576
6577 case X86_SREG_SS:
6578 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6579 pGstSelReg->u32Limit = 0;
6580 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6581 break;
6582
6583 case X86_SREG_ES:
6584 case X86_SREG_DS:
6585 pGstSelReg->u64Base = 0;
6586 pGstSelReg->u32Limit = 0;
6587 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6588 break;
6589
6590 case X86_SREG_FS:
6591 case X86_SREG_GS:
6592 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6593 pGstSelReg->u32Limit = 0;
6594 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6595 break;
6596 }
6597 Assert(pGstSelReg->Attr.n.u1Unusable);
6598 }
6599 }
6600
6601 /* LDTR. */
6602 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6603 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6604 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6605 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6606 {
6607 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6608 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6609 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6610 }
6611 else
6612 {
6613 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6614 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6615 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6616 }
6617
6618 /* TR. */
6619 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6620 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6621 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6622 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6623 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6624 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6625 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6626
6627 /* GDTR. */
6628 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6629 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6630
6631 /* IDTR. */
6632 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6633 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6634}
6635
6636
6637/**
6638 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6639 *
6640 * @returns VBox status code.
6641 * @param pVCpu The cross context virtual CPU structure.
6642 * @param pszInstr The VMX instruction name (for logging purposes).
6643 */
6644IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6645{
6646 /*
6647 * Load guest MSRs.
6648 * See Intel spec. 26.4 "Loading MSRs".
6649 */
6650 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6651 const char *const pszFailure = "VM-exit";
6652
6653 /*
6654 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6655 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6656 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6657 */
6658 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6659 if (!cMsrs)
6660 return VINF_SUCCESS;
6661
6662 /*
6663 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6664 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6665 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6666 */
6667 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6668 if (fIsMsrCountValid)
6669 { /* likely */ }
6670 else
6671 {
6672 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6673 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6674 }
6675
6676 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6677 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6678 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6679 if (RT_SUCCESS(rc))
6680 {
6681 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6682 Assert(pMsr);
6683 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6684 {
6685 if ( !pMsr->u32Reserved
6686 && pMsr->u32Msr != MSR_K8_FS_BASE
6687 && pMsr->u32Msr != MSR_K8_GS_BASE
6688 && pMsr->u32Msr != MSR_K6_EFER
6689 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6690 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6691 {
6692 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6693 if (rcStrict == VINF_SUCCESS)
6694 continue;
6695
6696 /*
6697 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6698 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6699 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6700 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6701 * MSR in ring-0 if possible, or come up with a better, generic solution.
6702 */
6703 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6704 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6705 ? kVmxVDiag_Vmentry_MsrLoadRing3
6706 : kVmxVDiag_Vmentry_MsrLoad;
6707 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6708 }
6709 else
6710 {
6711 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6713 }
6714 }
6715 }
6716 else
6717 {
6718 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6720 }
6721
6722 NOREF(pszInstr);
6723 NOREF(pszFailure);
6724 return VINF_SUCCESS;
6725}
6726
6727
6728/**
6729 * Loads the guest-state non-register state as part of VM-entry.
6730 *
6731 * @returns VBox status code.
6732 * @param pVCpu The cross context virtual CPU structure.
6733 *
6734 * @remarks This must be called only after loading the nested-guest register state
6735 * (especially nested-guest RIP).
6736 */
6737IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
6738{
6739 /*
6740 * Load guest non-register state.
6741 * See Intel spec. 26.6 "Special Features of VM Entry"
6742 */
6743 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6744
6745 /*
6746 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6747 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6748 *
6749 * See Intel spec. 26.6.1 "Interruptibility State".
6750 */
6751 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6752 if ( !fEntryVectoring
6753 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6754 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6755 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6756 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6757
6758 /* NMI blocking. */
6759 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6760 {
6761 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6762 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6763 else
6764 {
6765 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6766 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6767 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6768 }
6769 }
6770 else
6771 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6772
6773 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6774
6775 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6776 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6777
6778 /* VPID is irrelevant. We don't support VPID yet. */
6779
6780 /* Clear address-range monitoring. */
6781 EMMonitorWaitClear(pVCpu);
6782}
6783
6784
6785/**
6786 * Loads the guest-state as part of VM-entry.
6787 *
6788 * @returns VBox status code.
6789 * @param pVCpu The cross context virtual CPU structure.
6790 * @param pszInstr The VMX instruction name (for logging purposes).
6791 *
6792 * @remarks This must be done after all the necessary steps prior to loading of
6793 * guest-state (e.g. checking various VMCS state).
6794 */
6795IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
6796{
6797 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6798 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6799
6800 /*
6801 * Load guest RIP, RSP and RFLAGS.
6802 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6803 */
6804 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6805 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6806 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6807 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6808
6809 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6810 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6811 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6812
6813 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6814
6815 NOREF(pszInstr);
6816 return VINF_SUCCESS;
6817}
6818
6819
6820/**
6821 * Returns whether there are is a pending debug exception on VM-entry.
6822 *
6823 * @param pVCpu The cross context virtual CPU structure.
6824 * @param pszInstr The VMX instruction name (for logging purposes).
6825 */
6826IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
6827{
6828 /*
6829 * Pending debug exceptions.
6830 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6831 */
6832 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6833 Assert(pVmcs);
6834
6835 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6836 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6837 if (fPendingDbgXcpt)
6838 {
6839 uint8_t uEntryIntInfoType;
6840 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6841 if (fEntryVectoring)
6842 {
6843 switch (uEntryIntInfoType)
6844 {
6845 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6846 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6847 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6848 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6849 fPendingDbgXcpt = false;
6850 break;
6851
6852 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6853 {
6854 /*
6855 * Whether the pending debug exception for software exceptions other than
6856 * #BP and #OF is delivered after injecting the exception or is discard
6857 * is CPU implementation specific. We will discard them (easier).
6858 */
6859 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6860 if ( uVector != X86_XCPT_BP
6861 && uVector != X86_XCPT_OF)
6862 fPendingDbgXcpt = false;
6863 RT_FALL_THRU();
6864 }
6865 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6866 {
6867 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6868 fPendingDbgXcpt = false;
6869 break;
6870 }
6871 }
6872 }
6873 else
6874 {
6875 /*
6876 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6877 * pending debug exception is held pending or is discarded is CPU implementation
6878 * specific. We will discard them (easier).
6879 */
6880 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6881 fPendingDbgXcpt = false;
6882
6883 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6884 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6885 fPendingDbgXcpt = false;
6886 }
6887 }
6888
6889 NOREF(pszInstr);
6890 return fPendingDbgXcpt;
6891}
6892
6893
6894/**
6895 * Set up the monitor-trap flag (MTF).
6896 *
6897 * @param pVCpu The cross context virtual CPU structure.
6898 * @param pszInstr The VMX instruction name (for logging purposes).
6899 */
6900IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
6901{
6902 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6903 Assert(pVmcs);
6904 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6905 {
6906 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6907 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6908 }
6909 else
6910 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6911 NOREF(pszInstr);
6912}
6913
6914
6915/**
6916 * Sets up NMI-window exiting.
6917 *
6918 * @param pVCpu The cross context virtual CPU structure.
6919 * @param pszInstr The VMX instruction name (for logging purposes).
6920 */
6921IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPU pVCpu, const char *pszInstr)
6922{
6923 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6924 Assert(pVmcs);
6925 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6926 {
6927 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6928 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6929 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6930 }
6931 else
6932 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6933 NOREF(pszInstr);
6934}
6935
6936
6937/**
6938 * Sets up interrupt-window exiting.
6939 *
6940 * @param pVCpu The cross context virtual CPU structure.
6941 * @param pszInstr The VMX instruction name (for logging purposes).
6942 */
6943IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPU pVCpu, const char *pszInstr)
6944{
6945 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6946 Assert(pVmcs);
6947 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6948 {
6949 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6950 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6951 }
6952 else
6953 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6954 NOREF(pszInstr);
6955}
6956
6957
6958/**
6959 * Set up the VMX-preemption timer.
6960 *
6961 * @param pVCpu The cross context virtual CPU structure.
6962 * @param pszInstr The VMX instruction name (for logging purposes).
6963 */
6964IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
6965{
6966 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6967 Assert(pVmcs);
6968 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6969 {
6970 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
6971 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
6972 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
6973
6974 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
6975 }
6976 else
6977 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
6978
6979 NOREF(pszInstr);
6980}
6981
6982
6983/**
6984 * Injects an event using TRPM given a VM-entry interruption info. and related
6985 * fields.
6986 *
6987 * @returns VBox status code.
6988 * @param pVCpu The cross context virtual CPU structure.
6989 * @param uEntryIntInfo The VM-entry interruption info.
6990 * @param uErrCode The error code associated with the event if any.
6991 * @param cbInstr The VM-entry instruction length (for software
6992 * interrupts and software exceptions). Pass 0
6993 * otherwise.
6994 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
6995 */
6996IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
6997 RTGCUINTPTR GCPtrFaultAddress)
6998{
6999 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7000
7001 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7002 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7003 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7004
7005 TRPMEVENT enmTrapType;
7006 switch (uType)
7007 {
7008 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7009 enmTrapType = TRPM_HARDWARE_INT;
7010 break;
7011
7012 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7013 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7014 enmTrapType = TRPM_TRAP;
7015 break;
7016
7017 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7018 enmTrapType = TRPM_SOFTWARE_INT;
7019 break;
7020
7021 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7022 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7023 enmTrapType = TRPM_SOFTWARE_INT;
7024 break;
7025
7026 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* #DB (INT1/ICEBP). */
7027 Assert(uVector == X86_XCPT_DB);
7028 enmTrapType = TRPM_SOFTWARE_INT;
7029 break;
7030
7031 default:
7032 /* Shouldn't really happen. */
7033 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7034 break;
7035 }
7036
7037 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7038 if (RT_SUCCESS(rc))
7039 {
7040 if (fErrCodeValid)
7041 TRPMSetErrorCode(pVCpu, uErrCode);
7042
7043 if ( enmTrapType == TRPM_TRAP
7044 && uVector == X86_XCPT_PF)
7045 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7046 else if (enmTrapType == TRPM_SOFTWARE_INT)
7047 TRPMSetInstrLength(pVCpu, cbInstr);
7048 }
7049
7050 return rc;
7051}
7052
7053
7054/**
7055 * Performs event injection (if any) as part of VM-entry.
7056 *
7057 * @param pVCpu The cross context virtual CPU structure.
7058 * @param pszInstr The VMX instruction name (for logging purposes).
7059 */
7060IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7061{
7062 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7063
7064 /*
7065 * Inject events.
7066 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7067 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7068 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7069 * the actually delivery of this event.
7070 *
7071 * See Intel spec. 26.5 "Event Injection".
7072 */
7073 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7074 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7075
7076 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7077 if (fEntryIntInfoValid)
7078 {
7079 int rc;
7080 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7081 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7082 {
7083 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7084 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7085 rc = VINF_SUCCESS;
7086 }
7087 else
7088 {
7089 rc = iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7090 pVCpu->cpum.GstCtx.cr2);
7091 }
7092
7093 /*
7094 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7095 *
7096 * However, we do it here on VM-entry as well because while it isn't visible to guest
7097 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7098 * execution using hardware-assisted VT-x, it will not be try to inject the event again.
7099 *
7100 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7101 */
7102 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7103 return rc;
7104 }
7105
7106 /*
7107 * Inject any pending guest debug exception.
7108 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7109 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7110 */
7111 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7112 if (fPendingDbgXcpt)
7113 {
7114 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7115 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7116 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7117 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7118 0 /* GCPtrFaultAddress */);
7119 }
7120
7121 NOREF(pszInstr);
7122 return VINF_SUCCESS;
7123}
7124
7125
7126/**
7127 * Initializes all read-only VMCS fields as part of VM-entry.
7128 *
7129 * @param pVCpu The cross context virtual CPU structure.
7130 */
7131IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7132{
7133 /*
7134 * Any VMCS field which we do not establish on every VM-exit but may potentially
7135 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7136 * specified to be undefined needs to be initialized here.
7137 *
7138 * Thus, it is especially important to clear the Exit qualification field
7139 * since it must be zero for VM-exits where it is not used. Similarly, the
7140 * VM-exit interruption information field's valid bit needs to be cleared for
7141 * the same reasons.
7142 */
7143 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7144 Assert(pVmcs);
7145
7146 /* 16-bit (none currently). */
7147 /* 32-bit. */
7148 pVmcs->u32RoVmInstrError = 0;
7149 pVmcs->u32RoExitReason = 0;
7150 pVmcs->u32RoExitIntInfo = 0;
7151 pVmcs->u32RoExitIntErrCode = 0;
7152 pVmcs->u32RoIdtVectoringInfo = 0;
7153 pVmcs->u32RoIdtVectoringErrCode = 0;
7154 pVmcs->u32RoExitInstrLen = 0;
7155 pVmcs->u32RoExitInstrInfo = 0;
7156
7157 /* 64-bit. */
7158 pVmcs->u64RoGuestPhysAddr.u = 0;
7159
7160 /* Natural-width. */
7161 pVmcs->u64RoExitQual.u = 0;
7162 pVmcs->u64RoIoRcx.u = 0;
7163 pVmcs->u64RoIoRsi.u = 0;
7164 pVmcs->u64RoIoRdi.u = 0;
7165 pVmcs->u64RoIoRip.u = 0;
7166 pVmcs->u64RoGuestLinearAddr.u = 0;
7167}
7168
7169
7170/**
7171 * VMLAUNCH/VMRESUME instruction execution worker.
7172 *
7173 * @returns Strict VBox status code.
7174 * @param pVCpu The cross context virtual CPU structure.
7175 * @param cbInstr The instruction length in bytes.
7176 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7177 * VMXINSTRID_VMRESUME).
7178 *
7179 * @remarks Common VMX instruction checks are already expected to by the caller,
7180 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7181 */
7182IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7183{
7184# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7185 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7186 return VINF_EM_RAW_EMULATE_INSTR;
7187# else
7188 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7189 || uInstrId == VMXINSTRID_VMRESUME);
7190 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7191
7192 /* Nested-guest intercept. */
7193 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7194 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7195
7196 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7197
7198 /*
7199 * Basic VM-entry checks.
7200 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7201 * The checks following that do not have to follow a specific order.
7202 *
7203 * See Intel spec. 26.1 "Basic VM-entry Checks".
7204 */
7205
7206 /* CPL. */
7207 if (pVCpu->iem.s.uCpl == 0)
7208 { /* likely */ }
7209 else
7210 {
7211 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7212 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7213 return iemRaiseGeneralProtectionFault0(pVCpu);
7214 }
7215
7216 /* Current VMCS valid. */
7217 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7218 { /* likely */ }
7219 else
7220 {
7221 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7222 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7223 iemVmxVmFailInvalid(pVCpu);
7224 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7225 return VINF_SUCCESS;
7226 }
7227
7228 /* Current VMCS is not a shadow VMCS. */
7229 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7230 { /* likely */ }
7231 else
7232 {
7233 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7234 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7235 iemVmxVmFailInvalid(pVCpu);
7236 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7237 return VINF_SUCCESS;
7238 }
7239
7240 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7241 * use block-by-STI here which is not quite correct. */
7242 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7243 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7244 { /* likely */ }
7245 else
7246 {
7247 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7248 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7249 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7250 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7251 return VINF_SUCCESS;
7252 }
7253
7254 if (uInstrId == VMXINSTRID_VMLAUNCH)
7255 {
7256 /* VMLAUNCH with non-clear VMCS. */
7257 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7258 { /* likely */ }
7259 else
7260 {
7261 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7262 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7263 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7264 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7265 return VINF_SUCCESS;
7266 }
7267 }
7268 else
7269 {
7270 /* VMRESUME with non-launched VMCS. */
7271 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7272 { /* likely */ }
7273 else
7274 {
7275 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7276 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7277 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7278 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7279 return VINF_SUCCESS;
7280 }
7281 }
7282
7283 /*
7284 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7285 * while entering VMX non-root mode. We do some of this while checking VM-execution
7286 * controls. The guest hypervisor should not make assumptions and cannot expect
7287 * predictable behavior if changes to these structures are made in guest memory while
7288 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7289 * modify them anyway as we cache them in host memory.
7290 *
7291 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7292 */
7293 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7294 Assert(pVmcs);
7295 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7296
7297 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7298 if (RT_SUCCESS(rc))
7299 {
7300 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7301 if (RT_SUCCESS(rc))
7302 {
7303 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7304 if (RT_SUCCESS(rc))
7305 {
7306 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7307 if (RT_SUCCESS(rc))
7308 {
7309 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7310 iemVmxVmentryInitReadOnlyFields(pVCpu);
7311
7312 /*
7313 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7314 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7315 * VM-exit when required.
7316 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7317 */
7318 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7319
7320 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7321 if (RT_SUCCESS(rc))
7322 {
7323 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7324 if (RT_SUCCESS(rc))
7325 {
7326 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7327 if (RT_SUCCESS(rc))
7328 {
7329 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7330
7331 /* VMLAUNCH instruction must update the VMCS launch state. */
7332 if (uInstrId == VMXINSTRID_VMLAUNCH)
7333 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7334
7335 /* Perform the VMX transition (PGM updates). */
7336 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7337 if (rcStrict == VINF_SUCCESS)
7338 { /* likely */ }
7339 else if (RT_SUCCESS(rcStrict))
7340 {
7341 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7342 VBOXSTRICTRC_VAL(rcStrict)));
7343 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7344 }
7345 else
7346 {
7347 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7348 return rcStrict;
7349 }
7350
7351 /* Clear virtual-APIC page dirty bit to ensure it's not stale due to prior, failed VM-exits. */
7352 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtApicPageDirty = false;
7353
7354 /* We've now entered nested-guest execution. */
7355 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7356
7357 /*
7358 * The priority of potential VM-exits during VM-entry is important.
7359 * The priorities of VM-exits and events are listed from highest
7360 * to lowest as follows:
7361 *
7362 * 1. Event injection.
7363 * 2. Trap on task-switch (T flag set in TSS).
7364 * 3. TPR below threshold / APIC-write.
7365 * 4. SMI, INIT.
7366 * 5. MTF exit.
7367 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7368 * 7. VMX-preemption timer.
7369 * 9. NMI-window exit.
7370 * 10. NMI injection.
7371 * 11. Interrupt-window exit.
7372 * 12. Virtual-interrupt injection.
7373 * 13. Interrupt injection.
7374 * 14. Process next instruction (fetch, decode, execute).
7375 */
7376
7377 /* Setup the VMX-preemption timer. */
7378 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7379
7380 /* Setup monitor-trap flag. */
7381 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7382
7383 /* Setup NMI-window exiting. */
7384 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7385
7386 /* Setup interrupt-window exiting. */
7387 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7388
7389 /* Now that we've switched page tables, we can go ahead and inject any event. */
7390 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7391 if (RT_SUCCESS(rcStrict))
7392 {
7393 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7394# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7395 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7396 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7397 if (rcSched != VINF_SUCCESS)
7398 iemSetPassUpStatus(pVCpu, rcSched);
7399# endif
7400 return VINF_SUCCESS;
7401 }
7402
7403 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7404 return rcStrict;
7405 }
7406 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7407 pVmcs->u64RoExitQual.u);
7408 }
7409 }
7410 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7411 pVmcs->u64RoExitQual.u);
7412 }
7413
7414 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7415 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7416 return VINF_SUCCESS;
7417 }
7418 }
7419 }
7420
7421 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7422 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7423 return VINF_SUCCESS;
7424# endif
7425}
7426
7427
7428/**
7429 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7430 * (causes a VM-exit) or not.
7431 *
7432 * @returns @c true if the instruction is intercepted, @c false otherwise.
7433 * @param pVCpu The cross context virtual CPU structure.
7434 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7435 * VMX_EXIT_WRMSR).
7436 * @param idMsr The MSR.
7437 */
7438IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7439{
7440 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7441 Assert( uExitReason == VMX_EXIT_RDMSR
7442 || uExitReason == VMX_EXIT_WRMSR);
7443
7444 /* Consult the MSR bitmap if the feature is supported. */
7445 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7446 Assert(pVmcs);
7447 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7448 {
7449 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7450 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7451 if (uExitReason == VMX_EXIT_RDMSR)
7452 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7453 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7454 }
7455
7456 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7457 return true;
7458}
7459
7460
7461/**
7462 * VMREAD instruction execution worker that does not perform any validation checks.
7463 *
7464 * Callers are expected to have performed the necessary checks and to ensure the
7465 * VMREAD will succeed.
7466 *
7467 * @param pVmcs Pointer to the virtual VMCS.
7468 * @param pu64Dst Where to write the VMCS value.
7469 * @param u64VmcsField The VMCS field.
7470 *
7471 * @remarks May be called with interrupts disabled.
7472 */
7473IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7474{
7475 VMXVMCSFIELD VmcsField;
7476 VmcsField.u = u64VmcsField;
7477 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7478 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7479 uint8_t const uWidthType = (uWidth << 2) | uType;
7480 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7481 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7482 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7483 Assert(offField < VMX_V_VMCS_SIZE);
7484 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7485
7486 /*
7487 * Read the VMCS component based on the field's effective width.
7488 *
7489 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7490 * indicates high bits (little endian).
7491 *
7492 * Note! The caller is responsible to trim the result and update registers
7493 * or memory locations are required. Here we just zero-extend to the largest
7494 * type (i.e. 64-bits).
7495 */
7496 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7497 uint8_t const *pbField = pbVmcs + offField;
7498 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7499 switch (uEffWidth)
7500 {
7501 case VMX_VMCSFIELD_WIDTH_64BIT:
7502 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7503 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7504 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7505 }
7506}
7507
7508
7509/**
7510 * VMREAD common (memory/register) instruction execution worker.
7511 *
7512 * @returns Strict VBox status code.
7513 * @param pVCpu The cross context virtual CPU structure.
7514 * @param cbInstr The instruction length in bytes.
7515 * @param pu64Dst Where to write the VMCS value (only updated when
7516 * VINF_SUCCESS is returned).
7517 * @param u64VmcsField The VMCS field.
7518 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7519 * NULL.
7520 */
7521IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7522 PCVMXVEXITINFO pExitInfo)
7523{
7524 /* Nested-guest intercept. */
7525 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7526 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7527 {
7528 if (pExitInfo)
7529 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7530 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7531 }
7532
7533 /* CPL. */
7534 if (pVCpu->iem.s.uCpl == 0)
7535 { /* likely */ }
7536 else
7537 {
7538 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7539 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7540 return iemRaiseGeneralProtectionFault0(pVCpu);
7541 }
7542
7543 /* VMCS pointer in root mode. */
7544 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7545 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7546 { /* likely */ }
7547 else
7548 {
7549 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7550 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7551 iemVmxVmFailInvalid(pVCpu);
7552 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7553 return VINF_SUCCESS;
7554 }
7555
7556 /* VMCS-link pointer in non-root mode. */
7557 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7558 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7559 { /* likely */ }
7560 else
7561 {
7562 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7564 iemVmxVmFailInvalid(pVCpu);
7565 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7566 return VINF_SUCCESS;
7567 }
7568
7569 /* Supported VMCS field. */
7570 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7571 { /* likely */ }
7572 else
7573 {
7574 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7576 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7578 return VINF_SUCCESS;
7579 }
7580
7581 /*
7582 * Reading from the current or shadow VMCS.
7583 */
7584 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7585 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7586 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7587 Assert(pVmcs);
7588 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7589 return VINF_SUCCESS;
7590}
7591
7592
7593/**
7594 * VMREAD (64-bit register) instruction execution worker.
7595 *
7596 * @returns Strict VBox status code.
7597 * @param pVCpu The cross context virtual CPU structure.
7598 * @param cbInstr The instruction length in bytes.
7599 * @param pu64Dst Where to store the VMCS field's value.
7600 * @param u64VmcsField The VMCS field.
7601 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7602 * NULL.
7603 */
7604IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7605 PCVMXVEXITINFO pExitInfo)
7606{
7607 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7608 if (rcStrict == VINF_SUCCESS)
7609 {
7610 iemVmxVmreadSuccess(pVCpu, cbInstr);
7611 return VINF_SUCCESS;
7612 }
7613
7614 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7615 return rcStrict;
7616}
7617
7618
7619/**
7620 * VMREAD (32-bit register) instruction execution worker.
7621 *
7622 * @returns Strict VBox status code.
7623 * @param pVCpu The cross context virtual CPU structure.
7624 * @param cbInstr The instruction length in bytes.
7625 * @param pu32Dst Where to store the VMCS field's value.
7626 * @param u32VmcsField The VMCS field.
7627 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7628 * NULL.
7629 */
7630IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7631 PCVMXVEXITINFO pExitInfo)
7632{
7633 uint64_t u64Dst;
7634 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7635 if (rcStrict == VINF_SUCCESS)
7636 {
7637 *pu32Dst = u64Dst;
7638 iemVmxVmreadSuccess(pVCpu, cbInstr);
7639 return VINF_SUCCESS;
7640 }
7641
7642 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7643 return rcStrict;
7644}
7645
7646
7647/**
7648 * VMREAD (memory) instruction execution worker.
7649 *
7650 * @returns Strict VBox status code.
7651 * @param pVCpu The cross context virtual CPU structure.
7652 * @param cbInstr The instruction length in bytes.
7653 * @param iEffSeg The effective segment register to use with @a u64Val.
7654 * Pass UINT8_MAX if it is a register access.
7655 * @param GCPtrDst The guest linear address to store the VMCS field's
7656 * value.
7657 * @param u64VmcsField The VMCS field.
7658 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7659 * NULL.
7660 */
7661IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7662 PCVMXVEXITINFO pExitInfo)
7663{
7664 uint64_t u64Dst;
7665 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7666 if (rcStrict == VINF_SUCCESS)
7667 {
7668 /*
7669 * Write the VMCS field's value to the location specified in guest-memory.
7670 */
7671 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7672 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7673 else
7674 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7675 if (rcStrict == VINF_SUCCESS)
7676 {
7677 iemVmxVmreadSuccess(pVCpu, cbInstr);
7678 return VINF_SUCCESS;
7679 }
7680
7681 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7682 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7683 return rcStrict;
7684 }
7685
7686 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7687 return rcStrict;
7688}
7689
7690
7691/**
7692 * VMWRITE instruction execution worker that does not perform any validation
7693 * checks.
7694 *
7695 * Callers are expected to have performed the necessary checks and to ensure the
7696 * VMWRITE will succeed.
7697 *
7698 * @param pVmcs Pointer to the virtual VMCS.
7699 * @param u64Val The value to write.
7700 * @param u64VmcsField The VMCS field.
7701 *
7702 * @remarks May be called with interrupts disabled.
7703 */
7704IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7705{
7706 VMXVMCSFIELD VmcsField;
7707 VmcsField.u = u64VmcsField;
7708 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7709 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7710 uint8_t const uWidthType = (uWidth << 2) | uType;
7711 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7712 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7713 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7714 Assert(offField < VMX_V_VMCS_SIZE);
7715 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7716
7717 /*
7718 * Write the VMCS component based on the field's effective width.
7719 *
7720 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7721 * indicates high bits (little endian).
7722 */
7723 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7724 uint8_t *pbField = pbVmcs + offField;
7725 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(VmcsField.u);
7726 switch (uEffWidth)
7727 {
7728 case VMX_VMCSFIELD_WIDTH_64BIT:
7729 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7730 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7731 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7732 }
7733}
7734
7735
7736/**
7737 * VMWRITE instruction execution worker.
7738 *
7739 * @returns Strict VBox status code.
7740 * @param pVCpu The cross context virtual CPU structure.
7741 * @param cbInstr The instruction length in bytes.
7742 * @param iEffSeg The effective segment register to use with @a u64Val.
7743 * Pass UINT8_MAX if it is a register access.
7744 * @param u64Val The value to write (or guest linear address to the
7745 * value), @a iEffSeg will indicate if it's a memory
7746 * operand.
7747 * @param u64VmcsField The VMCS field.
7748 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7749 * NULL.
7750 */
7751IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7752 PCVMXVEXITINFO pExitInfo)
7753{
7754 /* Nested-guest intercept. */
7755 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7756 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7757 {
7758 if (pExitInfo)
7759 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7760 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7761 }
7762
7763 /* CPL. */
7764 if (pVCpu->iem.s.uCpl == 0)
7765 { /* likely */ }
7766 else
7767 {
7768 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7769 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7770 return iemRaiseGeneralProtectionFault0(pVCpu);
7771 }
7772
7773 /* VMCS pointer in root mode. */
7774 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7775 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7776 { /* likely */ }
7777 else
7778 {
7779 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7780 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7781 iemVmxVmFailInvalid(pVCpu);
7782 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7783 return VINF_SUCCESS;
7784 }
7785
7786 /* VMCS-link pointer in non-root mode. */
7787 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7788 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7789 { /* likely */ }
7790 else
7791 {
7792 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7793 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7794 iemVmxVmFailInvalid(pVCpu);
7795 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7796 return VINF_SUCCESS;
7797 }
7798
7799 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7800 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7801 if (!fIsRegOperand)
7802 {
7803 /* Read the value from the specified guest memory location. */
7804 VBOXSTRICTRC rcStrict;
7805 RTGCPTR const GCPtrVal = u64Val;
7806 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7807 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7808 else
7809 {
7810 uint32_t u32Val;
7811 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7812 u64Val = u32Val;
7813 }
7814 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7815 {
7816 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7817 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7818 return rcStrict;
7819 }
7820 }
7821 else
7822 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7823
7824 /* Supported VMCS field. */
7825 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7826 { /* likely */ }
7827 else
7828 {
7829 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7830 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7831 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7832 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7833 return VINF_SUCCESS;
7834 }
7835
7836 /* Read-only VMCS field. */
7837 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64VmcsField);
7838 if ( !fIsFieldReadOnly
7839 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7840 { /* likely */ }
7841 else
7842 {
7843 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7845 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7846 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7847 return VINF_SUCCESS;
7848 }
7849
7850 /*
7851 * Write to the current or shadow VMCS.
7852 */
7853 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7854 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7855 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7856 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7857 Assert(pVmcs);
7858 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7859
7860 /* Notify HM that the VMCS content might have changed. */
7861 if (!fInVmxNonRootMode)
7862 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7863
7864 iemVmxVmSucceed(pVCpu);
7865 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7866 return VINF_SUCCESS;
7867}
7868
7869
7870/**
7871 * VMCLEAR instruction execution worker.
7872 *
7873 * @returns Strict VBox status code.
7874 * @param pVCpu The cross context virtual CPU structure.
7875 * @param cbInstr The instruction length in bytes.
7876 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7877 * @param GCPtrVmcs The linear address of the VMCS pointer.
7878 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7879 *
7880 * @remarks Common VMX instruction checks are already expected to by the caller,
7881 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7882 */
7883IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7884 PCVMXVEXITINFO pExitInfo)
7885{
7886 /* Nested-guest intercept. */
7887 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7888 {
7889 if (pExitInfo)
7890 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7891 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7892 }
7893
7894 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7895
7896 /* CPL. */
7897 if (pVCpu->iem.s.uCpl == 0)
7898 { /* likely */ }
7899 else
7900 {
7901 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7902 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7903 return iemRaiseGeneralProtectionFault0(pVCpu);
7904 }
7905
7906 /* Get the VMCS pointer from the location specified by the source memory operand. */
7907 RTGCPHYS GCPhysVmcs;
7908 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7909 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7910 { /* likely */ }
7911 else
7912 {
7913 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7914 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7915 return rcStrict;
7916 }
7917
7918 /* VMCS pointer alignment. */
7919 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7920 { /* likely */ }
7921 else
7922 {
7923 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7924 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7925 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7926 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7927 return VINF_SUCCESS;
7928 }
7929
7930 /* VMCS physical-address width limits. */
7931 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7932 { /* likely */ }
7933 else
7934 {
7935 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7936 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7937 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7938 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7939 return VINF_SUCCESS;
7940 }
7941
7942 /* VMCS is not the VMXON region. */
7943 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7944 { /* likely */ }
7945 else
7946 {
7947 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7948 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7949 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7950 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7951 return VINF_SUCCESS;
7952 }
7953
7954 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7955 restriction imposed by our implementation. */
7956 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7957 { /* likely */ }
7958 else
7959 {
7960 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7961 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7962 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7963 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7964 return VINF_SUCCESS;
7965 }
7966
7967 /*
7968 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7969 *
7970 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7971 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7972 * to 'clear'.
7973 */
7974 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7975 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7976 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7977 {
7978 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
7979 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
7980 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7981 }
7982 else
7983 {
7984 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
7985 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7986 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
7987 if (RT_FAILURE(rcStrict))
7988 return rcStrict;
7989 }
7990
7991 iemVmxVmSucceed(pVCpu);
7992 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7993 return VINF_SUCCESS;
7994}
7995
7996
7997/**
7998 * VMPTRST instruction execution worker.
7999 *
8000 * @returns Strict VBox status code.
8001 * @param pVCpu The cross context virtual CPU structure.
8002 * @param cbInstr The instruction length in bytes.
8003 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8004 * @param GCPtrVmcs The linear address of where to store the current VMCS
8005 * pointer.
8006 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8007 *
8008 * @remarks Common VMX instruction checks are already expected to by the caller,
8009 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8010 */
8011IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8012 PCVMXVEXITINFO pExitInfo)
8013{
8014 /* Nested-guest intercept. */
8015 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8016 {
8017 if (pExitInfo)
8018 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8019 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8020 }
8021
8022 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8023
8024 /* CPL. */
8025 if (pVCpu->iem.s.uCpl == 0)
8026 { /* likely */ }
8027 else
8028 {
8029 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8030 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8031 return iemRaiseGeneralProtectionFault0(pVCpu);
8032 }
8033
8034 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8035 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8036 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8037 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8038 {
8039 iemVmxVmSucceed(pVCpu);
8040 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8041 return rcStrict;
8042 }
8043
8044 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8045 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8046 return rcStrict;
8047}
8048
8049
8050/**
8051 * VMPTRLD instruction execution worker.
8052 *
8053 * @returns Strict VBox status code.
8054 * @param pVCpu The cross context virtual CPU structure.
8055 * @param cbInstr The instruction length in bytes.
8056 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8057 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8058 *
8059 * @remarks Common VMX instruction checks are already expected to by the caller,
8060 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8061 */
8062IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8063 PCVMXVEXITINFO pExitInfo)
8064{
8065 /* Nested-guest intercept. */
8066 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8067 {
8068 if (pExitInfo)
8069 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8070 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8071 }
8072
8073 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8074
8075 /* CPL. */
8076 if (pVCpu->iem.s.uCpl == 0)
8077 { /* likely */ }
8078 else
8079 {
8080 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8081 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8082 return iemRaiseGeneralProtectionFault0(pVCpu);
8083 }
8084
8085 /* Get the VMCS pointer from the location specified by the source memory operand. */
8086 RTGCPHYS GCPhysVmcs;
8087 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8088 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8089 { /* likely */ }
8090 else
8091 {
8092 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8093 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8094 return rcStrict;
8095 }
8096
8097 /* VMCS pointer alignment. */
8098 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8099 { /* likely */ }
8100 else
8101 {
8102 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8103 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8104 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8105 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8106 return VINF_SUCCESS;
8107 }
8108
8109 /* VMCS physical-address width limits. */
8110 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8111 { /* likely */ }
8112 else
8113 {
8114 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8115 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8116 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8117 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8118 return VINF_SUCCESS;
8119 }
8120
8121 /* VMCS is not the VMXON region. */
8122 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8123 { /* likely */ }
8124 else
8125 {
8126 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8127 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8128 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8129 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8130 return VINF_SUCCESS;
8131 }
8132
8133 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8134 restriction imposed by our implementation. */
8135 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8136 { /* likely */ }
8137 else
8138 {
8139 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8140 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8141 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8142 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8143 return VINF_SUCCESS;
8144 }
8145
8146 /* Read just the VMCS revision from the VMCS. */
8147 VMXVMCSREVID VmcsRevId;
8148 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8149 if (RT_SUCCESS(rc))
8150 { /* likely */ }
8151 else
8152 {
8153 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8154 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8155 return rc;
8156 }
8157
8158 /*
8159 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8160 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8161 */
8162 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8163 && ( !VmcsRevId.n.fIsShadowVmcs
8164 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8165 { /* likely */ }
8166 else
8167 {
8168 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8169 {
8170 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8171 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8172 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8173 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8174 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8175 return VINF_SUCCESS;
8176 }
8177
8178 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8179 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8180 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8181 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8182 return VINF_SUCCESS;
8183 }
8184
8185 /*
8186 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8187 * the cache of an existing, current VMCS back to guest memory before loading a new,
8188 * different current VMCS.
8189 */
8190 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8191 {
8192 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8193 {
8194 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8195 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8196 }
8197
8198 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8199 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8200 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8201 if (RT_SUCCESS(rc))
8202 {
8203 /* Notify HM that a new, current VMCS is loaded. */
8204 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8205 }
8206 else
8207 {
8208 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8209 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8210 return rc;
8211 }
8212 }
8213
8214 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8215 iemVmxVmSucceed(pVCpu);
8216 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8217 return VINF_SUCCESS;
8218}
8219
8220
8221/**
8222 * INVVPID instruction execution worker.
8223 *
8224 * @returns Strict VBox status code.
8225 * @param pVCpu The cross context virtual CPU structure.
8226 * @param cbInstr The instruction length in bytes.
8227 * @param iEffSeg The segment of the invvpid descriptor.
8228 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8229 * @param u64InvvpidType The invalidation type.
8230 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8231 * NULL.
8232 *
8233 * @remarks Common VMX instruction checks are already expected to by the caller,
8234 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8235 */
8236IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8237 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8238{
8239 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8240 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8241 return iemRaiseUndefinedOpcode(pVCpu);
8242
8243 /* Nested-guest intercept. */
8244 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8245 {
8246 if (pExitInfo)
8247 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8248 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8249 }
8250
8251 /* CPL. */
8252 if (pVCpu->iem.s.uCpl != 0)
8253 {
8254 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8255 return iemRaiseGeneralProtectionFault0(pVCpu);
8256 }
8257
8258 /*
8259 * Validate INVVPID invalidation type.
8260 *
8261 * The instruction specifies exactly ONE of the supported invalidation types.
8262 *
8263 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8264 * supported. In theory, it's possible for a CPU to not support flushing individual
8265 * addresses but all the other types or any other combination. We do not take any
8266 * shortcuts here by assuming the types we currently expose to the guest.
8267 */
8268 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8269 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8270 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8271 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8272 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8273 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8274 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8275 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8276 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8277 { /* likely */ }
8278 else
8279 {
8280 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8281 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8282 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8283 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8284 return VINF_SUCCESS;
8285 }
8286
8287 /*
8288 * Fetch the invvpid descriptor from guest memory.
8289 */
8290 RTUINT128U uDesc;
8291 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8292 if (rcStrict == VINF_SUCCESS)
8293 {
8294 /*
8295 * Validate the descriptor.
8296 */
8297 if (uDesc.s.Lo > 0xfff)
8298 {
8299 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8300 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8301 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8302 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8303 return VINF_SUCCESS;
8304 }
8305
8306 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8307 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8308 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8309 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8310 switch (u64InvvpidType)
8311 {
8312 case VMXTLBFLUSHVPID_INDIV_ADDR:
8313 {
8314 if (uVpid != 0)
8315 {
8316 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8317 {
8318 /* Invalidate mappings for the linear address tagged with VPID. */
8319 /** @todo PGM support for VPID? Currently just flush everything. */
8320 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8321 iemVmxVmSucceed(pVCpu);
8322 }
8323 else
8324 {
8325 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8326 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8327 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8328 }
8329 }
8330 else
8331 {
8332 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8333 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8334 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8335 }
8336 break;
8337 }
8338
8339 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8340 {
8341 if (uVpid != 0)
8342 {
8343 /* Invalidate all mappings with VPID. */
8344 /** @todo PGM support for VPID? Currently just flush everything. */
8345 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8346 iemVmxVmSucceed(pVCpu);
8347 }
8348 else
8349 {
8350 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8351 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8352 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8353 }
8354 break;
8355 }
8356
8357 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8358 {
8359 /* Invalidate all mappings with non-zero VPIDs. */
8360 /** @todo PGM support for VPID? Currently just flush everything. */
8361 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8362 iemVmxVmSucceed(pVCpu);
8363 break;
8364 }
8365
8366 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8367 {
8368 if (uVpid != 0)
8369 {
8370 /* Invalidate all mappings with VPID except global translations. */
8371 /** @todo PGM support for VPID? Currently just flush everything. */
8372 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8373 iemVmxVmSucceed(pVCpu);
8374 }
8375 else
8376 {
8377 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8378 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8379 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8380 }
8381 break;
8382 }
8383 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8384 }
8385 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8386 }
8387 return rcStrict;
8388}
8389
8390
8391/**
8392 * VMXON instruction execution worker.
8393 *
8394 * @returns Strict VBox status code.
8395 * @param pVCpu The cross context virtual CPU structure.
8396 * @param cbInstr The instruction length in bytes.
8397 * @param iEffSeg The effective segment register to use with @a
8398 * GCPtrVmxon.
8399 * @param GCPtrVmxon The linear address of the VMXON pointer.
8400 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8401 *
8402 * @remarks Common VMX instruction checks are already expected to by the caller,
8403 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8404 */
8405IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8406 PCVMXVEXITINFO pExitInfo)
8407{
8408 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8409 {
8410 /* CPL. */
8411 if (pVCpu->iem.s.uCpl == 0)
8412 { /* likely */ }
8413 else
8414 {
8415 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8416 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8417 return iemRaiseGeneralProtectionFault0(pVCpu);
8418 }
8419
8420 /* A20M (A20 Masked) mode. */
8421 if (PGMPhysIsA20Enabled(pVCpu))
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmxon: A20M mode -> #GP(0)\n"));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8427 return iemRaiseGeneralProtectionFault0(pVCpu);
8428 }
8429
8430 /* CR0. */
8431 {
8432 /* CR0 MB1 bits. */
8433 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8434 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8435 { /* likely */ }
8436 else
8437 {
8438 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8439 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8440 return iemRaiseGeneralProtectionFault0(pVCpu);
8441 }
8442
8443 /* CR0 MBZ bits. */
8444 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8445 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8446 { /* likely */ }
8447 else
8448 {
8449 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8450 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8451 return iemRaiseGeneralProtectionFault0(pVCpu);
8452 }
8453 }
8454
8455 /* CR4. */
8456 {
8457 /* CR4 MB1 bits. */
8458 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8459 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8460 { /* likely */ }
8461 else
8462 {
8463 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8464 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8465 return iemRaiseGeneralProtectionFault0(pVCpu);
8466 }
8467
8468 /* CR4 MBZ bits. */
8469 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8470 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8471 { /* likely */ }
8472 else
8473 {
8474 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8475 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8476 return iemRaiseGeneralProtectionFault0(pVCpu);
8477 }
8478 }
8479
8480 /* Feature control MSR's LOCK and VMXON bits. */
8481 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8482 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8483 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8484 { /* likely */ }
8485 else
8486 {
8487 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8488 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8489 return iemRaiseGeneralProtectionFault0(pVCpu);
8490 }
8491
8492 /* Get the VMXON pointer from the location specified by the source memory operand. */
8493 RTGCPHYS GCPhysVmxon;
8494 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8495 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8496 { /* likely */ }
8497 else
8498 {
8499 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8500 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8501 return rcStrict;
8502 }
8503
8504 /* VMXON region pointer alignment. */
8505 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8506 { /* likely */ }
8507 else
8508 {
8509 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8510 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8511 iemVmxVmFailInvalid(pVCpu);
8512 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8513 return VINF_SUCCESS;
8514 }
8515
8516 /* VMXON physical-address width limits. */
8517 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8518 { /* likely */ }
8519 else
8520 {
8521 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8523 iemVmxVmFailInvalid(pVCpu);
8524 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8525 return VINF_SUCCESS;
8526 }
8527
8528 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8529 restriction imposed by our implementation. */
8530 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8531 { /* likely */ }
8532 else
8533 {
8534 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8535 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8536 iemVmxVmFailInvalid(pVCpu);
8537 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8538 return VINF_SUCCESS;
8539 }
8540
8541 /* Read the VMCS revision ID from the VMXON region. */
8542 VMXVMCSREVID VmcsRevId;
8543 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8544 if (RT_SUCCESS(rc))
8545 { /* likely */ }
8546 else
8547 {
8548 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8550 return rc;
8551 }
8552
8553 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8554 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8555 { /* likely */ }
8556 else
8557 {
8558 /* Revision ID mismatch. */
8559 if (!VmcsRevId.n.fIsShadowVmcs)
8560 {
8561 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8562 VmcsRevId.n.u31RevisionId));
8563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8564 iemVmxVmFailInvalid(pVCpu);
8565 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8566 return VINF_SUCCESS;
8567 }
8568
8569 /* Shadow VMCS disallowed. */
8570 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8572 iemVmxVmFailInvalid(pVCpu);
8573 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8574 return VINF_SUCCESS;
8575 }
8576
8577 /*
8578 * Record that we're in VMX operation, block INIT, block and disable A20M.
8579 */
8580 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8581 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8582 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8583
8584 /* Clear address-range monitoring. */
8585 EMMonitorWaitClear(pVCpu);
8586 /** @todo NSTVMX: Intel PT. */
8587
8588 iemVmxVmSucceed(pVCpu);
8589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8590 return VINF_SUCCESS;
8591 }
8592 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8593 {
8594 /* Nested-guest intercept. */
8595 if (pExitInfo)
8596 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8597 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8598 }
8599
8600 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8601
8602 /* CPL. */
8603 if (pVCpu->iem.s.uCpl > 0)
8604 {
8605 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8607 return iemRaiseGeneralProtectionFault0(pVCpu);
8608 }
8609
8610 /* VMXON when already in VMX root mode. */
8611 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8613 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8614 return VINF_SUCCESS;
8615}
8616
8617
8618/**
8619 * Implements 'VMXOFF'.
8620 *
8621 * @remarks Common VMX instruction checks are already expected to by the caller,
8622 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8623 */
8624IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8625{
8626 /* Nested-guest intercept. */
8627 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8628 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8629
8630 /* CPL. */
8631 if (pVCpu->iem.s.uCpl == 0)
8632 { /* likely */ }
8633 else
8634 {
8635 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8636 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8637 return iemRaiseGeneralProtectionFault0(pVCpu);
8638 }
8639
8640 /* Dual monitor treatment of SMIs and SMM. */
8641 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8642 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8643 { /* likely */ }
8644 else
8645 {
8646 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8647 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8648 return VINF_SUCCESS;
8649 }
8650
8651 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8653 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8654
8655 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8656 { /** @todo NSTVMX: Unblock SMI. */ }
8657
8658 EMMonitorWaitClear(pVCpu);
8659 /** @todo NSTVMX: Unblock and enable A20M. */
8660
8661 iemVmxVmSucceed(pVCpu);
8662 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8663 return VINF_SUCCESS;
8664}
8665
8666
8667/**
8668 * Implements 'VMXON'.
8669 */
8670IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8671{
8672 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8673}
8674
8675
8676/**
8677 * Implements 'VMLAUNCH'.
8678 */
8679IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8680{
8681 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8682}
8683
8684
8685/**
8686 * Implements 'VMRESUME'.
8687 */
8688IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8689{
8690 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8691}
8692
8693
8694/**
8695 * Implements 'VMPTRLD'.
8696 */
8697IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8698{
8699 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8700}
8701
8702
8703/**
8704 * Implements 'VMPTRST'.
8705 */
8706IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8707{
8708 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8709}
8710
8711
8712/**
8713 * Implements 'VMCLEAR'.
8714 */
8715IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8716{
8717 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8718}
8719
8720
8721/**
8722 * Implements 'VMWRITE' register.
8723 */
8724IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8725{
8726 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8727}
8728
8729
8730/**
8731 * Implements 'VMWRITE' memory.
8732 */
8733IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8734{
8735 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8736}
8737
8738
8739/**
8740 * Implements 'VMREAD' register (64-bit).
8741 */
8742IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8743{
8744 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8745}
8746
8747
8748/**
8749 * Implements 'VMREAD' register (32-bit).
8750 */
8751IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8752{
8753 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8754}
8755
8756
8757/**
8758 * Implements 'VMREAD' memory, 64-bit register.
8759 */
8760IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8761{
8762 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8763}
8764
8765
8766/**
8767 * Implements 'VMREAD' memory, 32-bit register.
8768 */
8769IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8770{
8771 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8772}
8773
8774
8775/**
8776 * Implements 'INVVPID'.
8777 */
8778IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8779{
8780 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8781}
8782
8783
8784/**
8785 * Implements VMX's implementation of PAUSE.
8786 */
8787IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8788{
8789 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8790 {
8791 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8792 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8793 return rcStrict;
8794 }
8795
8796 /*
8797 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8798 * a VM-exit, the instruction operates normally.
8799 */
8800 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8801 return VINF_SUCCESS;
8802}
8803
8804#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8805
8806
8807/**
8808 * Implements 'VMCALL'.
8809 */
8810IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8811{
8812#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8813 /* Nested-guest intercept. */
8814 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8815 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8816#endif
8817
8818 /* Join forces with vmmcall. */
8819 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8820}
8821
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