VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 80387

Last change on this file since 80387 was 80387, checked in by vboxsync, 5 years ago

VMM: Nested VMX: bugref:9180 Renamed u64GuestPendingDbgXcpt to u64GuestPendingDbgXcpts to better match the spec.
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File size: 349.2 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 80387 2019-08-22 14:44:42Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Sets the guest pending-debug exceptions field.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
788 */
789DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
790{
791 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
792 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
793 pVmcs->u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
794}
795
796
797/**
798 * Implements VMSucceed for VMX instruction success.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
803{
804 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
805}
806
807
808/**
809 * Implements VMFailInvalid for VMX instruction failure.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
814{
815 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
816}
817
818
819/**
820 * Implements VMFail for VMX instruction failure.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param enmInsErr The VM instruction error.
824 */
825DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
826{
827 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
828}
829
830
831/**
832 * Checks if the given auto-load/store MSR area count is valid for the
833 * implementation.
834 *
835 * @returns @c true if it's within the valid limit, @c false otherwise.
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param uMsrCount The MSR area count to check.
838 */
839DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
840{
841 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
842 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
843 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
844 if (uMsrCount <= cMaxSupportedMsrs)
845 return true;
846 return false;
847}
848
849
850/**
851 * Flushes the current VMCS contents back to guest memory.
852 *
853 * @returns VBox status code.
854 * @param pVCpu The cross context virtual CPU structure.
855 */
856DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
857{
858 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
859 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
860 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
861 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
862 return rc;
863}
864
865
866/**
867 * Populates the current VMCS contents from guest memory.
868 *
869 * @returns VBox status code.
870 * @param pVCpu The cross context virtual CPU structure.
871 */
872DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
873{
874 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
875 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
877 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
878 return rc;
879}
880
881
882/**
883 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
884 *
885 * @param pVCpu The cross context virtual CPU structure.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
888{
889 iemVmxVmSucceed(pVCpu);
890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
891}
892
893
894/**
895 * Gets the instruction diagnostic for segment base checks during VM-entry of a
896 * nested-guest.
897 *
898 * @param iSegReg The segment index (X86_SREG_XXX).
899 */
900IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
901{
902 switch (iSegReg)
903 {
904 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
905 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
906 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
907 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
908 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
909 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
910 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
911 }
912}
913
914
915/**
916 * Gets the instruction diagnostic for segment base checks during VM-entry of a
917 * nested-guest that is in Virtual-8086 mode.
918 *
919 * @param iSegReg The segment index (X86_SREG_XXX).
920 */
921IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
922{
923 switch (iSegReg)
924 {
925 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
926 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
927 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
928 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
929 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
930 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
931 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
932 }
933}
934
935
936/**
937 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
938 * nested-guest that is in Virtual-8086 mode.
939 *
940 * @param iSegReg The segment index (X86_SREG_XXX).
941 */
942IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
943{
944 switch (iSegReg)
945 {
946 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
947 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
948 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
949 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
950 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
951 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
952 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
953 }
954}
955
956
957/**
958 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
959 * nested-guest that is in Virtual-8086 mode.
960 *
961 * @param iSegReg The segment index (X86_SREG_XXX).
962 */
963IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
964{
965 switch (iSegReg)
966 {
967 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
968 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
969 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
970 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
971 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
972 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
973 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
974 }
975}
976
977
978/**
979 * Gets the instruction diagnostic for segment attributes reserved bits failure
980 * during VM-entry of a nested-guest.
981 *
982 * @param iSegReg The segment index (X86_SREG_XXX).
983 */
984IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
985{
986 switch (iSegReg)
987 {
988 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
989 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
990 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
991 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
992 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
993 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
994 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
995 }
996}
997
998
999/**
1000 * Gets the instruction diagnostic for segment attributes descriptor-type
1001 * (code/segment or system) failure during VM-entry of a nested-guest.
1002 *
1003 * @param iSegReg The segment index (X86_SREG_XXX).
1004 */
1005IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1006{
1007 switch (iSegReg)
1008 {
1009 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1010 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1011 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1012 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1013 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1014 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1015 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1016 }
1017}
1018
1019
1020/**
1021 * Gets the instruction diagnostic for segment attributes descriptor-type
1022 * (code/segment or system) failure during VM-entry of a nested-guest.
1023 *
1024 * @param iSegReg The segment index (X86_SREG_XXX).
1025 */
1026IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1027{
1028 switch (iSegReg)
1029 {
1030 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1031 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1032 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1033 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1034 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1035 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1036 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1037 }
1038}
1039
1040
1041/**
1042 * Gets the instruction diagnostic for segment attribute granularity failure during
1043 * VM-entry of a nested-guest.
1044 *
1045 * @param iSegReg The segment index (X86_SREG_XXX).
1046 */
1047IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1048{
1049 switch (iSegReg)
1050 {
1051 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1052 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1053 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1054 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1055 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1056 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1057 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1058 }
1059}
1060
1061/**
1062 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1063 * VM-entry of a nested-guest.
1064 *
1065 * @param iSegReg The segment index (X86_SREG_XXX).
1066 */
1067IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1068{
1069 switch (iSegReg)
1070 {
1071 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1072 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1073 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1074 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1075 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1076 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1077 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1078 }
1079}
1080
1081
1082/**
1083 * Gets the instruction diagnostic for segment attribute type accessed failure
1084 * during VM-entry of a nested-guest.
1085 *
1086 * @param iSegReg The segment index (X86_SREG_XXX).
1087 */
1088IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1089{
1090 switch (iSegReg)
1091 {
1092 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1093 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1094 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1095 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1096 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1097 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1098 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1099 }
1100}
1101
1102
1103/**
1104 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1105 * failure during VM-entry of a nested-guest.
1106 *
1107 * @param iSegReg The PDPTE entry index.
1108 */
1109IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1110{
1111 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1112 switch (iPdpte)
1113 {
1114 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1115 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1116 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1117 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1118 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1119 }
1120}
1121
1122
1123/**
1124 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1125 * failure during VM-exit of a nested-guest.
1126 *
1127 * @param iSegReg The PDPTE entry index.
1128 */
1129IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1130{
1131 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1132 switch (iPdpte)
1133 {
1134 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1135 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1136 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1137 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1138 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1139 }
1140}
1141
1142
1143/**
1144 * Saves the guest control registers, debug registers and some MSRs are part of
1145 * VM-exit.
1146 *
1147 * @param pVCpu The cross context virtual CPU structure.
1148 */
1149IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1150{
1151 /*
1152 * Saves the guest control registers, debug registers and some MSRs.
1153 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1154 */
1155 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1156
1157 /* Save control registers. */
1158 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1159 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1160 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1161
1162 /* Save SYSENTER CS, ESP, EIP. */
1163 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1165 {
1166 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1167 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1168 }
1169 else
1170 {
1171 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1172 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1173 }
1174
1175 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1176 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1177 {
1178 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1179 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1180 }
1181
1182 /* Save PAT MSR. */
1183 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1184 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1185
1186 /* Save EFER MSR. */
1187 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1188 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1189
1190 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1191 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1192
1193 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1194}
1195
1196
1197/**
1198 * Saves the guest force-flags in preparation of entering the nested-guest.
1199 *
1200 * @param pVCpu The cross context virtual CPU structure.
1201 */
1202IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1203{
1204 /* We shouldn't be called multiple times during VM-entry. */
1205 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1206
1207 /* MTF should not be set outside VMX non-root mode. */
1208 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1209
1210 /*
1211 * Preserve the required force-flags.
1212 *
1213 * We cache and clear force-flags that would affect the execution of the
1214 * nested-guest. Cached flags are then restored while returning to the guest
1215 * if necessary.
1216 *
1217 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1218 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1219 * instruction. Interrupt inhibition for any nested-guest instruction
1220 * is supplied by the guest-interruptibility state VMCS field and will
1221 * be set up as part of loading the guest state.
1222 *
1223 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1224 * successful VM-entry (due to invalid guest-state) need to continue
1225 * blocking NMIs if it was in effect before VM-entry.
1226 *
1227 * - MTF need not be preserved as it's used only in VMX non-root mode and
1228 * is supplied through the VM-execution controls.
1229 *
1230 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1231 * we will be able to generate interrupts that may cause VM-exits for
1232 * the nested-guest.
1233 */
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1235}
1236
1237
1238/**
1239 * Restores the guest force-flags in preparation of exiting the nested-guest.
1240 *
1241 * @param pVCpu The cross context virtual CPU structure.
1242 */
1243IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1244{
1245 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1246 {
1247 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1248 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1249 }
1250}
1251
1252
1253/**
1254 * Perform a VMX transition updated PGM, IEM and CPUM.
1255 *
1256 * @param pVCpu The cross context virtual CPU structure.
1257 */
1258IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1259{
1260 /*
1261 * Inform PGM about paging mode changes.
1262 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1263 * see comment in iemMemPageTranslateAndCheckAccess().
1264 */
1265 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1266# ifdef IN_RING3
1267 Assert(rc != VINF_PGM_CHANGE_MODE);
1268# endif
1269 AssertRCReturn(rc, rc);
1270
1271 /* Inform CPUM (recompiler), can later be removed. */
1272 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1273
1274 /*
1275 * Flush the TLB with new CR3. This is required in case the PGM mode change
1276 * above doesn't actually change anything.
1277 */
1278 if (rc == VINF_SUCCESS)
1279 {
1280 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1281 AssertRCReturn(rc, rc);
1282 }
1283
1284 /* Re-initialize IEM cache/state after the drastic mode switch. */
1285 iemReInitExec(pVCpu);
1286 return rc;
1287}
1288
1289
1290/**
1291 * Calculates the current VMX-preemption timer value.
1292 *
1293 * @returns The current VMX-preemption timer value.
1294 * @param pVCpu The cross context virtual CPU structure.
1295 */
1296IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1297{
1298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1299 Assert(pVmcs);
1300
1301 /*
1302 * Assume the following:
1303 * PreemptTimerShift = 5
1304 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1305 * EntryTick = 50000 (TSC at time of VM-entry)
1306 *
1307 * CurTick Delta PreemptTimerVal
1308 * ----------------------------------
1309 * 60000 10000 2
1310 * 80000 30000 1
1311 * 90000 40000 0 -> VM-exit.
1312 *
1313 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1314 * The saved VMX-preemption timer value is calculated as follows:
1315 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1316 * E.g.:
1317 * Delta = 10000
1318 * Tmp = 10000 / (2 * 10000) = 0.5
1319 * NewPt = 2 - 0.5 = 2
1320 * Delta = 30000
1321 * Tmp = 30000 / (2 * 10000) = 1.5
1322 * NewPt = 2 - 1.5 = 1
1323 * Delta = 40000
1324 * Tmp = 40000 / 20000 = 2
1325 * NewPt = 2 - 2 = 0
1326 */
1327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1328 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1329 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1330 uint64_t const uDelta = uCurTick - uEntryTick;
1331 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1332 uint32_t const uPreemptTimer = uVmcsPreemptVal
1333 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1334 return uPreemptTimer;
1335}
1336
1337
1338/**
1339 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1340 *
1341 * @param pVCpu The cross context virtual CPU structure.
1342 */
1343IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1344{
1345 /*
1346 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1347 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1348 */
1349 /* CS, SS, ES, DS, FS, GS. */
1350 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1351 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1352 {
1353 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1354 if (!pSelReg->Attr.n.u1Unusable)
1355 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1356 else
1357 {
1358 /*
1359 * For unusable segments the attributes are undefined except for CS and SS.
1360 * For the rest we don't bother preserving anything but the unusable bit.
1361 */
1362 switch (iSegReg)
1363 {
1364 case X86_SREG_CS:
1365 pVmcs->GuestCs = pSelReg->Sel;
1366 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1367 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1368 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1369 | X86DESCATTR_UNUSABLE);
1370 break;
1371
1372 case X86_SREG_SS:
1373 pVmcs->GuestSs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_DS:
1380 pVmcs->GuestDs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1384 break;
1385
1386 case X86_SREG_ES:
1387 pVmcs->GuestEs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_FS:
1394 pVmcs->GuestFs = pSelReg->Sel;
1395 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1396 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1397 break;
1398
1399 case X86_SREG_GS:
1400 pVmcs->GuestGs = pSelReg->Sel;
1401 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1403 break;
1404 }
1405 }
1406 }
1407
1408 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1409 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1410 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1411 | X86DESCATTR_UNUSABLE;
1412 /* LDTR. */
1413 {
1414 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1415 pVmcs->GuestLdtr = pSelReg->Sel;
1416 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1417 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1418 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1419 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1420 }
1421
1422 /* TR. */
1423 {
1424 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1425 pVmcs->GuestTr = pSelReg->Sel;
1426 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1427 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1428 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1429 }
1430
1431 /* GDTR. */
1432 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1433 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1434
1435 /* IDTR. */
1436 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1437 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1438}
1439
1440
1441/**
1442 * Saves guest non-register state as part of VM-exit.
1443 *
1444 * @param pVCpu The cross context virtual CPU structure.
1445 * @param uExitReason The VM-exit reason.
1446 */
1447IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1448{
1449 /*
1450 * Save guest non-register state.
1451 * See Intel spec. 27.3.4 "Saving Non-Register State".
1452 */
1453 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1454
1455 /*
1456 * Activity state.
1457 * Most VM-exits will occur in the active state. However, if the first instruction
1458 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1459 * the VM-exit will be from the HLT activity state.
1460 *
1461 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1462 */
1463 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1464 * not? */
1465 EMSTATE const enmActivityState = EMGetState(pVCpu);
1466 switch (enmActivityState)
1467 {
1468 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1469 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1470 }
1471
1472 /*
1473 * Interruptibility-state.
1474 */
1475 /* NMI. */
1476 pVmcs->u32GuestIntrState = 0;
1477 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1478 {
1479 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1481 }
1482 else
1483 {
1484 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1485 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1486 }
1487
1488 /* Blocking-by-STI. */
1489 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1490 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1491 {
1492 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1493 * currently. */
1494 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1495 }
1496 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1497
1498 /*
1499 * Pending debug exceptions.
1500 *
1501 * For VM-exits where it is not applicable, we can safely zero out the field.
1502 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1503 */
1504 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1505 && uExitReason != VMX_EXIT_SMI
1506 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1507 && !VMXIsVmexitTrapLike(uExitReason))
1508 {
1509 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1510 * block-by-MovSS is in effect. */
1511 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1512 }
1513
1514 /*
1515 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1516 *
1517 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1518 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1519 */
1520 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1521 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1522 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1523
1524 /* PDPTEs. */
1525 /* We don't support EPT yet. */
1526 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1527 pVmcs->u64GuestPdpte0.u = 0;
1528 pVmcs->u64GuestPdpte1.u = 0;
1529 pVmcs->u64GuestPdpte2.u = 0;
1530 pVmcs->u64GuestPdpte3.u = 0;
1531}
1532
1533
1534/**
1535 * Saves the guest-state as part of VM-exit.
1536 *
1537 * @returns VBox status code.
1538 * @param pVCpu The cross context virtual CPU structure.
1539 * @param uExitReason The VM-exit reason.
1540 */
1541IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1542{
1543 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1544 Assert(pVmcs);
1545
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1571 const char *const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the guest hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 Assert(pMsr);
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1717 }
1718
1719 /* CR4. */
1720 {
1721 /* Fixed CR4 bits are not modified. */
1722 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1723 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1724 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1725 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1726 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1727 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1728 if (fHostInLongMode)
1729 uValidHostCr4 |= X86_CR4_PAE;
1730 else
1731 uValidHostCr4 &= ~X86_CR4_PCIDE;
1732 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1733 }
1734
1735 /* CR3 (host value validated while checking host-state during VM-entry). */
1736 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1737
1738 /* DR7. */
1739 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1740
1741 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1742
1743 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1745 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1746 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1747
1748 /* FS, GS bases are loaded later while we load host segment registers. */
1749
1750 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1751 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1752 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1753 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1754 {
1755 if (fHostInLongMode)
1756 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1757 else
1758 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 }
1760
1761 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1762
1763 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1764 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1765 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1766
1767 /* We don't support IA32_BNDCFGS MSR yet. */
1768}
1769
1770
1771/**
1772 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1773 *
1774 * @param pVCpu The cross context virtual CPU structure.
1775 */
1776IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1777{
1778 /*
1779 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1780 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1781 *
1782 * Warning! Be careful to not touch fields that are reserved by VT-x,
1783 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1784 */
1785 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1786 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1787
1788 /* CS, SS, ES, DS, FS, GS. */
1789 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1790 {
1791 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1792 bool const fUnusable = RT_BOOL(HostSel == 0);
1793 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1794
1795 /* Selector. */
1796 pSelReg->Sel = HostSel;
1797 pSelReg->ValidSel = HostSel;
1798 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1799
1800 /* Limit. */
1801 pSelReg->u32Limit = 0xffffffff;
1802
1803 /* Base. */
1804 pSelReg->u64Base = 0;
1805
1806 /* Attributes. */
1807 if (iSegReg == X86_SREG_CS)
1808 {
1809 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1810 pSelReg->Attr.n.u1DescType = 1;
1811 pSelReg->Attr.n.u2Dpl = 0;
1812 pSelReg->Attr.n.u1Present = 1;
1813 pSelReg->Attr.n.u1Long = fHostInLongMode;
1814 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1815 pSelReg->Attr.n.u1Granularity = 1;
1816 Assert(!pSelReg->Attr.n.u1Unusable);
1817 Assert(!fUnusable);
1818 }
1819 else
1820 {
1821 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1822 pSelReg->Attr.n.u1DescType = 1;
1823 pSelReg->Attr.n.u2Dpl = 0;
1824 pSelReg->Attr.n.u1Present = 1;
1825 pSelReg->Attr.n.u1DefBig = 1;
1826 pSelReg->Attr.n.u1Granularity = 1;
1827 pSelReg->Attr.n.u1Unusable = fUnusable;
1828 }
1829 }
1830
1831 /* FS base. */
1832 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1833 || fHostInLongMode)
1834 {
1835 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1836 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1837 }
1838
1839 /* GS base. */
1840 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1844 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1845 }
1846
1847 /* TR. */
1848 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1849 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1850 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1851 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1852 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1853 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1854 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1856 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1861
1862 /* LDTR (Warning! do not touch the base and limits here). */
1863 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1864 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1865 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1866 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1867
1868 /* GDTR. */
1869 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1870 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1871 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1872
1873 /* IDTR.*/
1874 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1875 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1876 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1877}
1878
1879
1880/**
1881 * Checks host PDPTes as part of VM-exit.
1882 *
1883 * @param pVCpu The cross context virtual CPU structure.
1884 * @param uExitReason The VM-exit reason (for logging purposes).
1885 */
1886IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1887{
1888 /*
1889 * Check host PDPTEs.
1890 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1891 */
1892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1893 const char *const pszFailure = "VMX-abort";
1894 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1895
1896 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1897 && !fHostInLongMode)
1898 {
1899 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1900 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1901 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1902 if (RT_SUCCESS(rc))
1903 {
1904 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1905 {
1906 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1907 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1908 { /* likely */ }
1909 else
1910 {
1911 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1912 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1913 }
1914 }
1915 }
1916 else
1917 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1918 }
1919
1920 NOREF(pszFailure);
1921 NOREF(uExitReason);
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/**
1927 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1928 *
1929 * @returns VBox status code.
1930 * @param pVCpu The cross context virtual CPU structure.
1931 * @param pszInstr The VMX instruction name (for logging purposes).
1932 */
1933IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1934{
1935 /*
1936 * Load host MSRs.
1937 * See Intel spec. 27.6 "Loading MSRs".
1938 */
1939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1940 const char *const pszFailure = "VMX-abort";
1941
1942 /*
1943 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1944 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1945 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1946 */
1947 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1948 if (!cMsrs)
1949 return VINF_SUCCESS;
1950
1951 /*
1952 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1953 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1954 * implementation causes a VMX-abort followed by a triple-fault.
1955 */
1956 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1957 if (fIsMsrCountValid)
1958 { /* likely */ }
1959 else
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1961
1962 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1963 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1964 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1965 if (RT_SUCCESS(rc))
1966 {
1967 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1968 Assert(pMsr);
1969 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1970 {
1971 if ( !pMsr->u32Reserved
1972 && pMsr->u32Msr != MSR_K8_FS_BASE
1973 && pMsr->u32Msr != MSR_K8_GS_BASE
1974 && pMsr->u32Msr != MSR_K6_EFER
1975 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1976 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1977 {
1978 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1979 if (rcStrict == VINF_SUCCESS)
1980 continue;
1981
1982 /*
1983 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1984 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1985 * recording the MSR index in the auxiliary info. field and indicated further by our
1986 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1987 * if possible, or come up with a better, generic solution.
1988 */
1989 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1990 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1991 ? kVmxVDiag_Vmexit_MsrLoadRing3
1992 : kVmxVDiag_Vmexit_MsrLoad;
1993 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1994 }
1995 else
1996 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1997 }
1998 }
1999 else
2000 {
2001 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2003 }
2004
2005 NOREF(uExitReason);
2006 NOREF(pszFailure);
2007 return VINF_SUCCESS;
2008}
2009
2010
2011/**
2012 * Loads the host state as part of VM-exit.
2013 *
2014 * @returns Strict VBox status code.
2015 * @param pVCpu The cross context virtual CPU structure.
2016 * @param uExitReason The VM-exit reason (for logging purposes).
2017 */
2018IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2019{
2020 /*
2021 * Load host state.
2022 * See Intel spec. 27.5 "Loading Host State".
2023 */
2024 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2025 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2026
2027 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2028 if ( CPUMIsGuestInLongMode(pVCpu)
2029 && !fHostInLongMode)
2030 {
2031 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2032 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2033 }
2034
2035 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2036 iemVmxVmexitLoadHostSegRegs(pVCpu);
2037
2038 /*
2039 * Load host RIP, RSP and RFLAGS.
2040 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2041 */
2042 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2043 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2044 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2045
2046 /* Clear address range monitoring. */
2047 EMMonitorWaitClear(pVCpu);
2048
2049 /* Perform the VMX transition (PGM updates). */
2050 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2051 if (rcStrict == VINF_SUCCESS)
2052 {
2053 /* Check host PDPTEs (only when we've fully switched page tables_. */
2054 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2055 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2056 if (RT_FAILURE(rc))
2057 {
2058 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2059 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2060 }
2061 }
2062 else if (RT_SUCCESS(rcStrict))
2063 {
2064 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2065 uExitReason));
2066 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2067 }
2068 else
2069 {
2070 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2071 return VBOXSTRICTRC_VAL(rcStrict);
2072 }
2073
2074 Assert(rcStrict == VINF_SUCCESS);
2075
2076 /* Load MSRs from the VM-exit auto-load MSR area. */
2077 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2078 if (RT_FAILURE(rc))
2079 {
2080 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2081 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2082 }
2083 return VINF_SUCCESS;
2084}
2085
2086
2087/**
2088 * Gets VM-exit instruction information along with any displacement for an
2089 * instruction VM-exit.
2090 *
2091 * @returns The VM-exit instruction information.
2092 * @param pVCpu The cross context virtual CPU structure.
2093 * @param uExitReason The VM-exit reason.
2094 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2095 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2096 * NULL.
2097 */
2098IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2099{
2100 RTGCPTR GCPtrDisp;
2101 VMXEXITINSTRINFO ExitInstrInfo;
2102 ExitInstrInfo.u = 0;
2103
2104 /*
2105 * Get and parse the ModR/M byte from our decoded opcodes.
2106 */
2107 uint8_t bRm;
2108 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2109 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2110 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2111 {
2112 /*
2113 * ModR/M indicates register addressing.
2114 *
2115 * The primary/secondary register operands are reported in the iReg1 or iReg2
2116 * fields depending on whether it is a read/write form.
2117 */
2118 uint8_t idxReg1;
2119 uint8_t idxReg2;
2120 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2121 {
2122 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2123 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2124 }
2125 else
2126 {
2127 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2128 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2129 }
2130 ExitInstrInfo.All.u2Scaling = 0;
2131 ExitInstrInfo.All.iReg1 = idxReg1;
2132 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2133 ExitInstrInfo.All.fIsRegOperand = 1;
2134 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2135 ExitInstrInfo.All.iSegReg = 0;
2136 ExitInstrInfo.All.iIdxReg = 0;
2137 ExitInstrInfo.All.fIdxRegInvalid = 1;
2138 ExitInstrInfo.All.iBaseReg = 0;
2139 ExitInstrInfo.All.fBaseRegInvalid = 1;
2140 ExitInstrInfo.All.iReg2 = idxReg2;
2141
2142 /* Displacement not applicable for register addressing. */
2143 GCPtrDisp = 0;
2144 }
2145 else
2146 {
2147 /*
2148 * ModR/M indicates memory addressing.
2149 */
2150 uint8_t uScale = 0;
2151 bool fBaseRegValid = false;
2152 bool fIdxRegValid = false;
2153 uint8_t iBaseReg = 0;
2154 uint8_t iIdxReg = 0;
2155 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2156 {
2157 /*
2158 * Parse the ModR/M, displacement for 16-bit addressing mode.
2159 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2160 */
2161 uint16_t u16Disp = 0;
2162 uint8_t const offDisp = offModRm + sizeof(bRm);
2163 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2164 {
2165 /* Displacement without any registers. */
2166 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2167 }
2168 else
2169 {
2170 /* Register (index and base). */
2171 switch (bRm & X86_MODRM_RM_MASK)
2172 {
2173 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2174 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2175 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2180 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2181 }
2182
2183 /* Register + displacement. */
2184 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2185 {
2186 case 0: break;
2187 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2188 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2189 default:
2190 {
2191 /* Register addressing, handled at the beginning. */
2192 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2193 break;
2194 }
2195 }
2196 }
2197
2198 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2199 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2200 }
2201 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2202 {
2203 /*
2204 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2205 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2206 */
2207 uint32_t u32Disp = 0;
2208 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2209 {
2210 /* Displacement without any registers. */
2211 uint8_t const offDisp = offModRm + sizeof(bRm);
2212 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2213 }
2214 else
2215 {
2216 /* Register (and perhaps scale, index and base). */
2217 uint8_t offDisp = offModRm + sizeof(bRm);
2218 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2219 if (iBaseReg == 4)
2220 {
2221 /* An SIB byte follows the ModR/M byte, parse it. */
2222 uint8_t bSib;
2223 uint8_t const offSib = offModRm + sizeof(bRm);
2224 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2225
2226 /* A displacement may follow SIB, update its offset. */
2227 offDisp += sizeof(bSib);
2228
2229 /* Get the scale. */
2230 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2231
2232 /* Get the index register. */
2233 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2234 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2235
2236 /* Get the base register. */
2237 iBaseReg = bSib & X86_SIB_BASE_MASK;
2238 fBaseRegValid = true;
2239 if (iBaseReg == 5)
2240 {
2241 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2242 {
2243 /* Mod is 0 implies a 32-bit displacement with no base. */
2244 fBaseRegValid = false;
2245 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2246 }
2247 else
2248 {
2249 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2250 iBaseReg = X86_GREG_xBP;
2251 }
2252 }
2253 }
2254
2255 /* Register + displacement. */
2256 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2257 {
2258 case 0: /* Handled above */ break;
2259 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2260 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2261 default:
2262 {
2263 /* Register addressing, handled at the beginning. */
2264 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2265 break;
2266 }
2267 }
2268 }
2269
2270 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2271 }
2272 else
2273 {
2274 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2275
2276 /*
2277 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2278 * See Intel instruction spec. 2.2 "IA-32e Mode".
2279 */
2280 uint64_t u64Disp = 0;
2281 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2282 if (fRipRelativeAddr)
2283 {
2284 /*
2285 * RIP-relative addressing mode.
2286 *
2287 * The displacement is 32-bit signed implying an offset range of +/-2G.
2288 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2289 */
2290 uint8_t const offDisp = offModRm + sizeof(bRm);
2291 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2292 }
2293 else
2294 {
2295 uint8_t offDisp = offModRm + sizeof(bRm);
2296
2297 /*
2298 * Register (and perhaps scale, index and base).
2299 *
2300 * REX.B extends the most-significant bit of the base register. However, REX.B
2301 * is ignored while determining whether an SIB follows the opcode. Hence, we
2302 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2303 *
2304 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2305 */
2306 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2307 if (iBaseReg == 4)
2308 {
2309 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2310 uint8_t bSib;
2311 uint8_t const offSib = offModRm + sizeof(bRm);
2312 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2313
2314 /* Displacement may follow SIB, update its offset. */
2315 offDisp += sizeof(bSib);
2316
2317 /* Get the scale. */
2318 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2319
2320 /* Get the index. */
2321 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2322 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2323
2324 /* Get the base. */
2325 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2326 fBaseRegValid = true;
2327 if (iBaseReg == 5)
2328 {
2329 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2330 {
2331 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2332 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2333 }
2334 else
2335 {
2336 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2337 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2338 }
2339 }
2340 }
2341 iBaseReg |= pVCpu->iem.s.uRexB;
2342
2343 /* Register + displacement. */
2344 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2345 {
2346 case 0: /* Handled above */ break;
2347 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2348 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2349 default:
2350 {
2351 /* Register addressing, handled at the beginning. */
2352 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2353 break;
2354 }
2355 }
2356 }
2357
2358 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2359 }
2360
2361 /*
2362 * The primary or secondary register operand is reported in iReg2 depending
2363 * on whether the primary operand is in read/write form.
2364 */
2365 uint8_t idxReg2;
2366 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2367 {
2368 idxReg2 = bRm & X86_MODRM_RM_MASK;
2369 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2370 idxReg2 |= pVCpu->iem.s.uRexB;
2371 }
2372 else
2373 {
2374 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2375 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2376 idxReg2 |= pVCpu->iem.s.uRexReg;
2377 }
2378 ExitInstrInfo.All.u2Scaling = uScale;
2379 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2380 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2381 ExitInstrInfo.All.fIsRegOperand = 0;
2382 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2383 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2384 ExitInstrInfo.All.iIdxReg = iIdxReg;
2385 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2386 ExitInstrInfo.All.iBaseReg = iBaseReg;
2387 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2388 ExitInstrInfo.All.iReg2 = idxReg2;
2389 }
2390
2391 /*
2392 * Handle exceptions to the norm for certain instructions.
2393 * (e.g. some instructions convey an instruction identity in place of iReg2).
2394 */
2395 switch (uExitReason)
2396 {
2397 case VMX_EXIT_GDTR_IDTR_ACCESS:
2398 {
2399 Assert(VMXINSTRID_IS_VALID(uInstrId));
2400 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2401 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2402 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2403 break;
2404 }
2405
2406 case VMX_EXIT_LDTR_TR_ACCESS:
2407 {
2408 Assert(VMXINSTRID_IS_VALID(uInstrId));
2409 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2410 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2411 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2412 break;
2413 }
2414
2415 case VMX_EXIT_RDRAND:
2416 case VMX_EXIT_RDSEED:
2417 {
2418 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2419 break;
2420 }
2421 }
2422
2423 /* Update displacement and return the constructed VM-exit instruction information field. */
2424 if (pGCPtrDisp)
2425 *pGCPtrDisp = GCPtrDisp;
2426
2427 return ExitInstrInfo.u;
2428}
2429
2430
2431/**
2432 * VMX VM-exit handler.
2433 *
2434 * @returns Strict VBox status code.
2435 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2436 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2437 * triple-fault.
2438 *
2439 * @param pVCpu The cross context virtual CPU structure.
2440 * @param uExitReason The VM-exit reason.
2441 * @param u64ExitQual The Exit qualification.
2442 */
2443IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2444{
2445# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2446 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2447 return VINF_EM_RAW_EMULATE_INSTR;
2448# else
2449 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2450 Assert(pVmcs);
2451
2452 /*
2453 * Import all the guest-CPU state.
2454 *
2455 * HM on returning to guest execution would have to reset up a whole lot of state
2456 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2457 * the state and flag reloading the entire state on re-entry. So import the entire
2458 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2459 */
2460 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2461
2462 /*
2463 * Ensure VM-entry interruption information valid bit is cleared.
2464 *
2465 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2466 * by invalid-guest state or machine-check exceptions) also clear this bit.
2467 *
2468 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2469 */
2470 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2471 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2472
2473 /*
2474 * Update the VM-exit reason and Exit qualification.
2475 * Other VMCS read-only data fields are expected to be updated by the caller already.
2476 */
2477 pVmcs->u32RoExitReason = uExitReason;
2478 pVmcs->u64RoExitQual.u = u64ExitQual;
2479
2480 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2481 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2482
2483 /*
2484 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2485 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2486 */
2487 {
2488 uint8_t uVector;
2489 uint32_t fFlags;
2490 uint32_t uErrCode;
2491 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2492 if (fInEventDelivery)
2493 {
2494 /*
2495 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2496 * caused by a triple-fault or the original event results in a double-fault that
2497 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2498 * original event information into the IDT-vectoring information fields.
2499 *
2500 * See Intel spec. 27.2.4 Information for VM Exits During Event Delivery
2501 */
2502 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2503 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2504 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2505 {
2506 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2507 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2508 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2509 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2510 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2511 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2512 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2513 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2514 }
2515 }
2516 }
2517
2518 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2519 Assert(pVmcs->u64RoIoRcx.u == 0);
2520 Assert(pVmcs->u64RoIoRsi.u == 0);
2521 Assert(pVmcs->u64RoIoRdi.u == 0);
2522 Assert(pVmcs->u64RoIoRip.u == 0);
2523
2524 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2525 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2526 {
2527 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2528 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2529 }
2530
2531 /* Paranoia. */
2532 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2533
2534 /*
2535 * Save the guest state back into the VMCS.
2536 * We only need to save the state when the VM-entry was successful.
2537 */
2538 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2539 if (!fVmentryFailed)
2540 {
2541 /*
2542 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2543 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2544 *
2545 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2546 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2547 * as guest-CPU state would not been modified. Hence for now, we do this only when
2548 * the VM-entry succeeded.
2549 */
2550 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2551 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2552 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2553 {
2554 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2555 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2556 else
2557 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2558 }
2559
2560 /*
2561 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2562 * occurs in enclave mode/SMM which we don't support yet.
2563 *
2564 * If we ever add support for it, we can pass just the lower bits to the functions
2565 * below, till then an assert should suffice.
2566 */
2567 Assert(!RT_HI_U16(uExitReason));
2568
2569 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2570 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2571 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2572 if (RT_SUCCESS(rc))
2573 { /* likely */ }
2574 else
2575 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2576
2577 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2578 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2579 }
2580 else
2581 {
2582 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2583 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2584 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2585 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2586 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2587 }
2588
2589 /*
2590 * Clear any pending VMX nested-guest force-flags.
2591 * These force-flags have no effect on guest execution and will
2592 * be re-evaluated and setup on the next nested-guest VM-entry.
2593 */
2594 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2595 | VMCPU_FF_VMX_MTF
2596 | VMCPU_FF_VMX_APIC_WRITE
2597 | VMCPU_FF_VMX_INT_WINDOW
2598 | VMCPU_FF_VMX_NMI_WINDOW);
2599
2600 /* Restore the host (outer guest) state. */
2601 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2602 if (RT_SUCCESS(rcStrict))
2603 {
2604 Assert(rcStrict == VINF_SUCCESS);
2605 rcStrict = VINF_VMX_VMEXIT;
2606 }
2607 else
2608 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2609
2610 /* We're no longer in nested-guest execution mode. */
2611 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2612
2613 /* Notify HM that the current VMCS fields have been modified. */
2614 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2615
2616 /* Notify HM that we've completed the VM-exit. */
2617 HMNotifyVmxNstGstVmexit(pVCpu);
2618
2619# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2620 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2621 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2622 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2623 if (rcSched != VINF_SUCCESS)
2624 iemSetPassUpStatus(pVCpu, rcSched);
2625# endif
2626 return rcStrict;
2627# endif
2628}
2629
2630
2631/**
2632 * VMX VM-exit handler for VM-exits due to instruction execution.
2633 *
2634 * This is intended for instructions where the caller provides all the relevant
2635 * VM-exit information.
2636 *
2637 * @returns Strict VBox status code.
2638 * @param pVCpu The cross context virtual CPU structure.
2639 * @param pExitInfo Pointer to the VM-exit information.
2640 */
2641IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2642{
2643 /*
2644 * For instructions where any of the following fields are not applicable:
2645 * - Exit qualification must be cleared.
2646 * - VM-exit instruction info. is undefined.
2647 * - Guest-linear address is undefined.
2648 * - Guest-physical address is undefined.
2649 *
2650 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2651 * instruction execution. For VM-exits that are not due to instruction execution this
2652 * field is undefined.
2653 *
2654 * In our implementation in IEM, all undefined fields are generally cleared. However,
2655 * if the caller supplies information (from say the physical CPU directly) it is
2656 * then possible that the undefined fields are not cleared.
2657 *
2658 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2659 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2660 */
2661 Assert(pExitInfo);
2662 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2663 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2664 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2665
2666 /* Update all the relevant fields from the VM-exit instruction information struct. */
2667 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2668 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2669 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2670 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2671
2672 /* Perform the VM-exit. */
2673 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2674}
2675
2676
2677/**
2678 * VMX VM-exit handler for VM-exits due to instruction execution.
2679 *
2680 * This is intended for instructions that only provide the VM-exit instruction
2681 * length.
2682 *
2683 * @param pVCpu The cross context virtual CPU structure.
2684 * @param uExitReason The VM-exit reason.
2685 * @param cbInstr The instruction length in bytes.
2686 */
2687IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2688{
2689 VMXVEXITINFO ExitInfo;
2690 RT_ZERO(ExitInfo);
2691 ExitInfo.uReason = uExitReason;
2692 ExitInfo.cbInstr = cbInstr;
2693
2694#ifdef VBOX_STRICT
2695 /*
2696 * To prevent us from shooting ourselves in the foot.
2697 * The follow instructions should convey more than just the instruction length.
2698 */
2699 switch (uExitReason)
2700 {
2701 case VMX_EXIT_INVEPT:
2702 case VMX_EXIT_INVPCID:
2703 case VMX_EXIT_INVVPID:
2704 case VMX_EXIT_LDTR_TR_ACCESS:
2705 case VMX_EXIT_GDTR_IDTR_ACCESS:
2706 case VMX_EXIT_VMCLEAR:
2707 case VMX_EXIT_VMPTRLD:
2708 case VMX_EXIT_VMPTRST:
2709 case VMX_EXIT_VMREAD:
2710 case VMX_EXIT_VMWRITE:
2711 case VMX_EXIT_VMXON:
2712 case VMX_EXIT_XRSTORS:
2713 case VMX_EXIT_XSAVES:
2714 case VMX_EXIT_RDRAND:
2715 case VMX_EXIT_RDSEED:
2716 case VMX_EXIT_IO_INSTR:
2717 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2718 break;
2719 }
2720#endif
2721
2722 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2723}
2724
2725
2726/**
2727 * VMX VM-exit handler for VM-exits due to instruction execution.
2728 *
2729 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2730 * instruction information and Exit qualification fields.
2731 *
2732 * @param pVCpu The cross context virtual CPU structure.
2733 * @param uExitReason The VM-exit reason.
2734 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2735 * @param cbInstr The instruction length in bytes.
2736 *
2737 * @remarks Do not use this for INS/OUTS instruction.
2738 */
2739IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2740{
2741 VMXVEXITINFO ExitInfo;
2742 RT_ZERO(ExitInfo);
2743 ExitInfo.uReason = uExitReason;
2744 ExitInfo.cbInstr = cbInstr;
2745
2746 /*
2747 * Update the Exit qualification field with displacement bytes.
2748 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2749 */
2750 switch (uExitReason)
2751 {
2752 case VMX_EXIT_INVEPT:
2753 case VMX_EXIT_INVPCID:
2754 case VMX_EXIT_INVVPID:
2755 case VMX_EXIT_LDTR_TR_ACCESS:
2756 case VMX_EXIT_GDTR_IDTR_ACCESS:
2757 case VMX_EXIT_VMCLEAR:
2758 case VMX_EXIT_VMPTRLD:
2759 case VMX_EXIT_VMPTRST:
2760 case VMX_EXIT_VMREAD:
2761 case VMX_EXIT_VMWRITE:
2762 case VMX_EXIT_VMXON:
2763 case VMX_EXIT_XRSTORS:
2764 case VMX_EXIT_XSAVES:
2765 case VMX_EXIT_RDRAND:
2766 case VMX_EXIT_RDSEED:
2767 {
2768 /* Construct the VM-exit instruction information. */
2769 RTGCPTR GCPtrDisp;
2770 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2771
2772 /* Update the VM-exit instruction information. */
2773 ExitInfo.InstrInfo.u = uInstrInfo;
2774
2775 /* Update the Exit qualification. */
2776 ExitInfo.u64Qual = GCPtrDisp;
2777 break;
2778 }
2779
2780 default:
2781 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2782 break;
2783 }
2784
2785 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2786}
2787
2788
2789/**
2790 * VMX VM-exit handler for VM-exits due to INVLPG.
2791 *
2792 * @returns Strict VBox status code.
2793 * @param pVCpu The cross context virtual CPU structure.
2794 * @param GCPtrPage The guest-linear address of the page being invalidated.
2795 * @param cbInstr The instruction length in bytes.
2796 */
2797IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2798{
2799 VMXVEXITINFO ExitInfo;
2800 RT_ZERO(ExitInfo);
2801 ExitInfo.uReason = VMX_EXIT_INVLPG;
2802 ExitInfo.cbInstr = cbInstr;
2803 ExitInfo.u64Qual = GCPtrPage;
2804 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2805
2806 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2807}
2808
2809
2810/**
2811 * VMX VM-exit handler for VM-exits due to LMSW.
2812 *
2813 * @returns Strict VBox status code.
2814 * @param pVCpu The cross context virtual CPU structure.
2815 * @param uGuestCr0 The current guest CR0.
2816 * @param pu16NewMsw The machine-status word specified in LMSW's source
2817 * operand. This will be updated depending on the VMX
2818 * guest/host CR0 mask if LMSW is not intercepted.
2819 * @param GCPtrEffDst The guest-linear address of the source operand in case
2820 * of a memory operand. For register operand, pass
2821 * NIL_RTGCPTR.
2822 * @param cbInstr The instruction length in bytes.
2823 */
2824IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2825 uint8_t cbInstr)
2826{
2827 Assert(pu16NewMsw);
2828
2829 uint16_t const uNewMsw = *pu16NewMsw;
2830 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2831 {
2832 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2833
2834 VMXVEXITINFO ExitInfo;
2835 RT_ZERO(ExitInfo);
2836 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2837 ExitInfo.cbInstr = cbInstr;
2838
2839 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2840 if (fMemOperand)
2841 {
2842 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2843 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2844 }
2845
2846 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2847 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2848 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2849 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2850
2851 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2852 }
2853
2854 /*
2855 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2856 * CR0 guest/host mask must be left unmodified.
2857 *
2858 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2859 */
2860 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2861 Assert(pVmcs);
2862 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2863 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2864 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2865
2866 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2867}
2868
2869
2870/**
2871 * VMX VM-exit handler for VM-exits due to CLTS.
2872 *
2873 * @returns Strict VBox status code.
2874 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2875 * VM-exit but must not modify the guest CR0.TS bit.
2876 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2877 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2878 * CR0 fixed bits in VMX operation).
2879 * @param pVCpu The cross context virtual CPU structure.
2880 * @param cbInstr The instruction length in bytes.
2881 */
2882IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2883{
2884 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2885 Assert(pVmcs);
2886
2887 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2888 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2889
2890 /*
2891 * If CR0.TS is owned by the host:
2892 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2893 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2894 * CLTS instruction completes without clearing CR0.TS.
2895 *
2896 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2897 */
2898 if (fGstHostMask & X86_CR0_TS)
2899 {
2900 if (fReadShadow & X86_CR0_TS)
2901 {
2902 Log2(("clts: Guest intercept -> VM-exit\n"));
2903
2904 VMXVEXITINFO ExitInfo;
2905 RT_ZERO(ExitInfo);
2906 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2907 ExitInfo.cbInstr = cbInstr;
2908 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2909 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2910 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2911 }
2912
2913 return VINF_VMX_MODIFIES_BEHAVIOR;
2914 }
2915
2916 /*
2917 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2918 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2919 */
2920 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2921}
2922
2923
2924/**
2925 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2926 * (CR0/CR4 write).
2927 *
2928 * @returns Strict VBox status code.
2929 * @param pVCpu The cross context virtual CPU structure.
2930 * @param iCrReg The control register (either CR0 or CR4).
2931 * @param uGuestCrX The current guest CR0/CR4.
2932 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2933 * VM-exit is caused.
2934 * @param iGReg The general register from which the CR0/CR4 value is being
2935 * loaded.
2936 * @param cbInstr The instruction length in bytes.
2937 */
2938IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2939 uint8_t cbInstr)
2940{
2941 Assert(puNewCrX);
2942 Assert(iCrReg == 0 || iCrReg == 4);
2943 Assert(iGReg < X86_GREG_COUNT);
2944
2945 uint64_t const uNewCrX = *puNewCrX;
2946 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2947 {
2948 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2949
2950 VMXVEXITINFO ExitInfo;
2951 RT_ZERO(ExitInfo);
2952 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2953 ExitInfo.cbInstr = cbInstr;
2954 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2955 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2956 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2957 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2958 }
2959
2960 /*
2961 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2962 * must not be modified the instruction.
2963 *
2964 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2965 */
2966 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2967 Assert(pVmcs);
2968 uint64_t uGuestCrX;
2969 uint64_t fGstHostMask;
2970 if (iCrReg == 0)
2971 {
2972 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2973 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2974 fGstHostMask = pVmcs->u64Cr0Mask.u;
2975 }
2976 else
2977 {
2978 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2979 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2980 fGstHostMask = pVmcs->u64Cr4Mask.u;
2981 }
2982
2983 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2984 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2985}
2986
2987
2988/**
2989 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2990 *
2991 * @returns VBox strict status code.
2992 * @param pVCpu The cross context virtual CPU structure.
2993 * @param iGReg The general register to which the CR3 value is being stored.
2994 * @param cbInstr The instruction length in bytes.
2995 */
2996IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2997{
2998 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2999 Assert(pVmcs);
3000 Assert(iGReg < X86_GREG_COUNT);
3001 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3002
3003 /*
3004 * If the CR3-store exiting control is set, we must cause a VM-exit.
3005 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3006 */
3007 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3008 {
3009 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3010
3011 VMXVEXITINFO ExitInfo;
3012 RT_ZERO(ExitInfo);
3013 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3014 ExitInfo.cbInstr = cbInstr;
3015 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3016 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3017 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3018 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3019 }
3020
3021 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3022}
3023
3024
3025/**
3026 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3027 *
3028 * @returns VBox strict status code.
3029 * @param pVCpu The cross context virtual CPU structure.
3030 * @param uNewCr3 The new CR3 value.
3031 * @param iGReg The general register from which the CR3 value is being
3032 * loaded.
3033 * @param cbInstr The instruction length in bytes.
3034 */
3035IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3036{
3037 Assert(iGReg < X86_GREG_COUNT);
3038
3039 /*
3040 * If the CR3-load exiting control is set and the new CR3 value does not
3041 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3042 *
3043 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3044 */
3045 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3046 {
3047 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3048
3049 VMXVEXITINFO ExitInfo;
3050 RT_ZERO(ExitInfo);
3051 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3052 ExitInfo.cbInstr = cbInstr;
3053 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3054 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3055 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3056 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3057 }
3058
3059 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3060}
3061
3062
3063/**
3064 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3065 *
3066 * @returns VBox strict status code.
3067 * @param pVCpu The cross context virtual CPU structure.
3068 * @param iGReg The general register to which the CR8 value is being stored.
3069 * @param cbInstr The instruction length in bytes.
3070 */
3071IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3072{
3073 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3074 Assert(pVmcs);
3075 Assert(iGReg < X86_GREG_COUNT);
3076
3077 /*
3078 * If the CR8-store exiting control is set, we must cause a VM-exit.
3079 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3080 */
3081 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3082 {
3083 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3084
3085 VMXVEXITINFO ExitInfo;
3086 RT_ZERO(ExitInfo);
3087 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3088 ExitInfo.cbInstr = cbInstr;
3089 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3090 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3092 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3093 }
3094
3095 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3096}
3097
3098
3099/**
3100 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3101 *
3102 * @returns VBox strict status code.
3103 * @param pVCpu The cross context virtual CPU structure.
3104 * @param iGReg The general register from which the CR8 value is being
3105 * loaded.
3106 * @param cbInstr The instruction length in bytes.
3107 */
3108IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3109{
3110 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3111 Assert(pVmcs);
3112 Assert(iGReg < X86_GREG_COUNT);
3113
3114 /*
3115 * If the CR8-load exiting control is set, we must cause a VM-exit.
3116 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3117 */
3118 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3119 {
3120 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3121
3122 VMXVEXITINFO ExitInfo;
3123 RT_ZERO(ExitInfo);
3124 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3125 ExitInfo.cbInstr = cbInstr;
3126 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3128 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3129 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3130 }
3131
3132 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3133}
3134
3135
3136/**
3137 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3138 * GReg,DRx' (DRx read).
3139 *
3140 * @returns VBox strict status code.
3141 * @param pVCpu The cross context virtual CPU structure.
3142 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3143 * VMXINSTRID_MOV_FROM_DRX).
3144 * @param iDrReg The debug register being accessed.
3145 * @param iGReg The general register to/from which the DRx value is being
3146 * store/loaded.
3147 * @param cbInstr The instruction length in bytes.
3148 */
3149IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3150 uint8_t cbInstr)
3151{
3152 Assert(iDrReg <= 7);
3153 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3154 Assert(iGReg < X86_GREG_COUNT);
3155
3156 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3157 Assert(pVmcs);
3158
3159 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3160 {
3161 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3162 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3163 VMXVEXITINFO ExitInfo;
3164 RT_ZERO(ExitInfo);
3165 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3166 ExitInfo.cbInstr = cbInstr;
3167 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3168 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3169 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3170 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3171 }
3172
3173 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3174}
3175
3176
3177/**
3178 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3179 *
3180 * @returns VBox strict status code.
3181 * @param pVCpu The cross context virtual CPU structure.
3182 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3183 * VMXINSTRID_IO_OUT).
3184 * @param u16Port The I/O port being accessed.
3185 * @param fImm Whether the I/O port was encoded using an immediate operand
3186 * or the implicit DX register.
3187 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3188 * @param cbInstr The instruction length in bytes.
3189 */
3190IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3191 uint8_t cbInstr)
3192{
3193 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3194 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3195
3196 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3197 if (fIntercept)
3198 {
3199 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3200 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3201 VMXVEXITINFO ExitInfo;
3202 RT_ZERO(ExitInfo);
3203 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3204 ExitInfo.cbInstr = cbInstr;
3205 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3206 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3207 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3208 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3209 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3210 }
3211
3212 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3213}
3214
3215
3216/**
3217 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3218 *
3219 * @returns VBox strict status code.
3220 * @param pVCpu The cross context virtual CPU structure.
3221 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3222 * VMXINSTRID_IO_OUTS).
3223 * @param u16Port The I/O port being accessed.
3224 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3225 * @param fRep Whether the instruction has a REP prefix or not.
3226 * @param ExitInstrInfo The VM-exit instruction info. field.
3227 * @param cbInstr The instruction length in bytes.
3228 */
3229IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3230 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3231{
3232 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3233 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3234 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3235 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3236 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3237
3238 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3239 if (fIntercept)
3240 {
3241 /*
3242 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3243 */
3244 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3245 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3246 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3247 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3248 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3249
3250 uint32_t uDirection;
3251 uint64_t uGuestLinearAddr;
3252 if (uInstrId == VMXINSTRID_IO_INS)
3253 {
3254 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3255 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3256 }
3257 else
3258 {
3259 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3260 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3261 }
3262
3263 /*
3264 * If the segment is unusable, the guest-linear address in undefined.
3265 * We shall clear it for consistency.
3266 *
3267 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3268 */
3269 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3270 uGuestLinearAddr = 0;
3271
3272 VMXVEXITINFO ExitInfo;
3273 RT_ZERO(ExitInfo);
3274 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3275 ExitInfo.cbInstr = cbInstr;
3276 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3277 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3278 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3279 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3280 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3283 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3284 ExitInfo.InstrInfo = ExitInstrInfo;
3285 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3286 }
3287
3288 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3289}
3290
3291
3292/**
3293 * VMX VM-exit handler for VM-exits due to MWAIT.
3294 *
3295 * @returns VBox strict status code.
3296 * @param pVCpu The cross context virtual CPU structure.
3297 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3298 * @param cbInstr The instruction length in bytes.
3299 */
3300IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3301{
3302 VMXVEXITINFO ExitInfo;
3303 RT_ZERO(ExitInfo);
3304 ExitInfo.uReason = VMX_EXIT_MWAIT;
3305 ExitInfo.cbInstr = cbInstr;
3306 ExitInfo.u64Qual = fMonitorHwArmed;
3307 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3308}
3309
3310
3311/**
3312 * VMX VM-exit handler for VM-exits due to PAUSE.
3313 *
3314 * @returns VBox strict status code.
3315 * @param pVCpu The cross context virtual CPU structure.
3316 * @param cbInstr The instruction length in bytes.
3317 */
3318IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3319{
3320 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3321 Assert(pVmcs);
3322
3323 /*
3324 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3325 * "PAUSE-loop exiting" control.
3326 *
3327 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3328 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3329 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3330 * a VM-exit.
3331 *
3332 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3333 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3334 */
3335 bool fIntercept = false;
3336 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3337 fIntercept = true;
3338 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3339 && pVCpu->iem.s.uCpl == 0)
3340 {
3341 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3342
3343 /*
3344 * A previous-PAUSE-tick value of 0 is used to identify the first time
3345 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3346 * consider this to be the first execution of PAUSE in a loop according
3347 * to the Intel.
3348 *
3349 * All subsequent records for the previous-PAUSE-tick we ensure that it
3350 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3351 */
3352 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3353 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3354 uint64_t const uTick = TMCpuTickGet(pVCpu);
3355 uint32_t const uPleGap = pVmcs->u32PleGap;
3356 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3357 if ( *puPrevPauseTick == 0
3358 || uTick - *puPrevPauseTick > uPleGap)
3359 *puFirstPauseLoopTick = uTick;
3360 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3361 fIntercept = true;
3362
3363 *puPrevPauseTick = uTick | 1;
3364 }
3365
3366 if (fIntercept)
3367 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3368
3369 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3370}
3371
3372
3373/**
3374 * VMX VM-exit handler for VM-exits due to task switches.
3375 *
3376 * @returns VBox strict status code.
3377 * @param pVCpu The cross context virtual CPU structure.
3378 * @param enmTaskSwitch The cause of the task switch.
3379 * @param SelNewTss The selector of the new TSS.
3380 * @param cbInstr The instruction length in bytes.
3381 */
3382IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3383{
3384 /*
3385 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3386 *
3387 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3388 * instruction or delivery of the exception generated by one of these instructions
3389 * lead to a task switch through a task gate in the IDT, we need to provide the
3390 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3391 * leaves the VM-exit instruction length field undefined.
3392 *
3393 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3394 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3395 */
3396 Assert(cbInstr <= 15);
3397
3398 uint8_t uType;
3399 switch (enmTaskSwitch)
3400 {
3401 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3402 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3403 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3404 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3405 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3406 }
3407
3408 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3409 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3410 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3411 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3412}
3413
3414
3415/**
3416 * VMX VM-exit handler for trap-like VM-exits.
3417 *
3418 * @returns VBox strict status code.
3419 * @param pVCpu The cross context virtual CPU structure.
3420 * @param pExitInfo Pointer to the VM-exit information.
3421 * @param pExitEventInfo Pointer to the VM-exit event information.
3422 */
3423IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3424{
3425 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3426 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3427 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3428}
3429
3430
3431/**
3432 * VMX VM-exit handler for VM-exits due to task switches.
3433 *
3434 * This is intended for task switches where the caller provides all the relevant
3435 * VM-exit information.
3436 *
3437 * @returns VBox strict status code.
3438 * @param pVCpu The cross context virtual CPU structure.
3439 * @param pExitInfo Pointer to the VM-exit information.
3440 * @param pExitEventInfo Pointer to the VM-exit event information.
3441 */
3442IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3443 PCVMXVEXITEVENTINFO pExitEventInfo)
3444{
3445 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3446 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3447 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3448 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3449 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3450}
3451
3452
3453/**
3454 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3455 *
3456 * @returns VBox strict status code.
3457 * @param pVCpu The cross context virtual CPU structure.
3458 */
3459IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3460{
3461 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3462 Assert(pVmcs);
3463
3464 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3465 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3466 {
3467 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3468 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3469
3470 /*
3471 * Calculate the current VMX-preemption timer value.
3472 * Only if the value has reached zero, we cause the VM-exit.
3473 */
3474 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3475 if (!uPreemptTimer)
3476 {
3477 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3478 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3479 pVmcs->u32PreemptTimer = 0;
3480
3481 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3482 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3483 }
3484 }
3485
3486 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3487}
3488
3489
3490/**
3491 * VMX VM-exit handler for VM-exits due to external interrupts.
3492 *
3493 * @returns VBox strict status code.
3494 * @param pVCpu The cross context virtual CPU structure.
3495 * @param uVector The external interrupt vector (pass 0 if the interrupt
3496 * is still pending since we typically won't know the
3497 * vector).
3498 * @param fIntPending Whether the external interrupt is pending or
3499 * acknowledged in the interrupt controller.
3500 */
3501IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3502{
3503 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3504 Assert(pVmcs);
3505 Assert(fIntPending || uVector == 0);
3506
3507 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3508 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3509 * functions require prior checking of a blanket intercept and which don't.
3510 * It is better for the caller to check a blanket intercept performance wise
3511 * than making a function call. Leaving this as a todo because it is more
3512 * a performance issue. */
3513
3514 /* The VM-exit is subject to "External interrupt exiting" being set. */
3515 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3516 {
3517 if (fIntPending)
3518 {
3519 /*
3520 * If the interrupt is pending and we don't need to acknowledge the
3521 * interrupt on VM-exit, cause the VM-exit immediately.
3522 *
3523 * See Intel spec 25.2 "Other Causes Of VM Exits".
3524 */
3525 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3526 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3527
3528 /*
3529 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3530 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3531 * acknowledged that the interrupt has been consumed.
3532 */
3533 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3534 }
3535
3536 /*
3537 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3538 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3539 * all set, we cause the VM-exit now. We need to record the external interrupt that
3540 * just occurred in the VM-exit interruption information field.
3541 *
3542 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3543 */
3544 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3545 {
3546 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3547 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3548 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3549 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3550 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3551 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3552 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3553 }
3554 }
3555
3556 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3557}
3558
3559
3560/**
3561 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3562 * an event.
3563 *
3564 * @returns VBox strict status code.
3565 * @param pVCpu The cross context virtual CPU structure.
3566 */
3567IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3568{
3569 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3570 Assert(pVmcs);
3571
3572 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3573 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3574 {
3575 /*
3576 * The NMI-unblocking due to IRET field need not be set for double faults.
3577 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3578 */
3579 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3580 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3581 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3582 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3583 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3584 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3585 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3586 }
3587
3588 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3589}
3590
3591
3592/**
3593 * VMX VM-exit handler for VM-exit due to delivery of an events.
3594 *
3595 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3596 * all the relevant VM-exit information.
3597 *
3598 * @returns VBox strict status code.
3599 * @param pVCpu The cross context virtual CPU structure.
3600 * @param pExitInfo Pointer to the VM-exit information.
3601 * @param pExitEventInfo Pointer to the VM-exit event information.
3602 */
3603IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3604{
3605 Assert(pExitInfo);
3606 Assert(pExitEventInfo);
3607 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3608
3609 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3610 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3611 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3612 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3613 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3614 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3615}
3616
3617
3618/**
3619 * VMX VM-exit handler for VM-exits due to delivery of an event.
3620 *
3621 * @returns VBox strict status code.
3622 * @param pVCpu The cross context virtual CPU structure.
3623 * @param uVector The interrupt / exception vector.
3624 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3625 * @param uErrCode The error code associated with the event.
3626 * @param uCr2 The CR2 value in case of a \#PF exception.
3627 * @param cbInstr The instruction length in bytes.
3628 */
3629IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3630 uint8_t cbInstr)
3631{
3632 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3633 Assert(pVmcs);
3634
3635 /*
3636 * If the event is being injected as part of VM-entry, it is -not- subject to event
3637 * intercepts in the nested-guest. However, secondary exceptions that occur during
3638 * injection of any event -are- subject to event interception.
3639 *
3640 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3641 */
3642 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3643 {
3644 /*
3645 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3646 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3647 *
3648 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3649 */
3650 if ( uVector == X86_XCPT_NMI
3651 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3652 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3653 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3654 else
3655 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3656
3657 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3658 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3659 }
3660
3661 /*
3662 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3663 * If not, the caller will continue delivery of the external interrupt as it would
3664 * normally. The interrupt is no longer pending in the interrupt controller at this
3665 * point.
3666 */
3667 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3668 {
3669 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3670 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3671 }
3672
3673 /*
3674 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3675 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3676 * interrupts.
3677 */
3678 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3679 bool fIntercept;
3680 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3681 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3682 {
3683 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3684 }
3685 else
3686 {
3687 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3688 fIntercept = false;
3689 }
3690
3691 /*
3692 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3693 * relevant VM-exit information and cause the VM-exit.
3694 */
3695 if (fIntercept)
3696 {
3697 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3698
3699 /* Construct the rest of the event related information fields and cause the VM-exit. */
3700 uint64_t u64ExitQual;
3701 if (uVector == X86_XCPT_PF)
3702 {
3703 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3704 u64ExitQual = uCr2;
3705 }
3706 else if (uVector == X86_XCPT_DB)
3707 {
3708 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3709 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3710 }
3711 else
3712 u64ExitQual = 0;
3713
3714 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3715 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3716 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3717 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3718 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3719 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3720 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3721 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3722 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3723 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3724
3725 /*
3726 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3727 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3728 * length.
3729 */
3730 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3731 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3732 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3733 else
3734 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3735
3736 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3737 }
3738
3739 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3740}
3741
3742
3743/**
3744 * VMX VM-exit handler for APIC accesses.
3745 *
3746 * @param pVCpu The cross context virtual CPU structure.
3747 * @param offAccess The offset of the register being accessed.
3748 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3749 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3750 */
3751IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3752{
3753 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3754
3755 VMXAPICACCESS enmAccess;
3756 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3757 if (fInEventDelivery)
3758 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3759 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3760 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3761 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3762 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3763 else
3764 enmAccess = VMXAPICACCESS_LINEAR_READ;
3765
3766 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3767 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3768 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3769}
3770
3771
3772/**
3773 * VMX VM-exit handler for APIC accesses.
3774 *
3775 * This is intended for APIC accesses where the caller provides all the
3776 * relevant VM-exit information.
3777 *
3778 * @returns VBox strict status code.
3779 * @param pVCpu The cross context virtual CPU structure.
3780 * @param pExitInfo Pointer to the VM-exit information.
3781 * @param pExitEventInfo Pointer to the VM-exit event information.
3782 */
3783IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3784 PCVMXVEXITEVENTINFO pExitEventInfo)
3785{
3786 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3787 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3788 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3789 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3790 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3791 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3792 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3793 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3794 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3795}
3796
3797
3798/**
3799 * VMX VM-exit handler for APIC-write VM-exits.
3800 *
3801 * @param pVCpu The cross context virtual CPU structure.
3802 * @param offApic The write to the virtual-APIC page offset that caused this
3803 * VM-exit.
3804 */
3805IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3806{
3807 Assert(offApic < XAPIC_OFF_END + 4);
3808 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3809 offApic &= UINT16_C(0xfff);
3810 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3811}
3812
3813
3814/**
3815 * Sets virtual-APIC write emulation as pending.
3816 *
3817 * @param pVCpu The cross context virtual CPU structure.
3818 * @param offApic The offset in the virtual-APIC page that was written.
3819 */
3820DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3821{
3822 Assert(offApic < XAPIC_OFF_END + 4);
3823
3824 /*
3825 * Record the currently updated APIC offset, as we need this later for figuring
3826 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3827 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3828 */
3829 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3830
3831 /*
3832 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3833 * virtualization or APIC-write emulation).
3834 */
3835 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3836 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3837}
3838
3839
3840/**
3841 * Clears any pending virtual-APIC write emulation.
3842 *
3843 * @returns The virtual-APIC offset that was written before clearing it.
3844 * @param pVCpu The cross context virtual CPU structure.
3845 */
3846DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3847{
3848 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3849 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3850 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3851 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3852 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3853 return offVirtApicWrite;
3854}
3855
3856
3857/**
3858 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3859 *
3860 * @returns The register from the virtual-APIC page.
3861 * @param pVCpu The cross context virtual CPU structure.
3862 * @param offReg The offset of the register being read.
3863 */
3864IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3865{
3866 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3867 Assert(pVmcs);
3868 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3869
3870 uint32_t uReg;
3871 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3872 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3873 if (RT_SUCCESS(rc))
3874 { /* likely */ }
3875 else
3876 {
3877 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3878 GCPhysVirtApic));
3879 uReg = 0;
3880 }
3881 return uReg;
3882}
3883
3884
3885/**
3886 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3887 *
3888 * @returns The register from the virtual-APIC page.
3889 * @param pVCpu The cross context virtual CPU structure.
3890 * @param offReg The offset of the register being read.
3891 */
3892IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3893{
3894 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3895 Assert(pVmcs);
3896 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3897
3898 uint64_t uReg;
3899 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3900 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3901 if (RT_SUCCESS(rc))
3902 { /* likely */ }
3903 else
3904 {
3905 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3906 GCPhysVirtApic));
3907 uReg = 0;
3908 }
3909 return uReg;
3910}
3911
3912
3913/**
3914 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3915 *
3916 * @param pVCpu The cross context virtual CPU structure.
3917 * @param offReg The offset of the register being written.
3918 * @param uReg The register value to write.
3919 */
3920IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3921{
3922 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3923 Assert(pVmcs);
3924 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3925
3926 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3927 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3928 if (RT_SUCCESS(rc))
3929 { /* likely */ }
3930 else
3931 {
3932 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3933 GCPhysVirtApic));
3934 }
3935}
3936
3937
3938/**
3939 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3940 *
3941 * @param pVCpu The cross context virtual CPU structure.
3942 * @param offReg The offset of the register being written.
3943 * @param uReg The register value to write.
3944 */
3945IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3946{
3947 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3948 Assert(pVmcs);
3949 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3950
3951 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3952 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3953 if (RT_SUCCESS(rc))
3954 { /* likely */ }
3955 else
3956 {
3957 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3958 GCPhysVirtApic));
3959 }
3960}
3961
3962
3963/**
3964 * Sets the vector in a virtual-APIC 256-bit sparse register.
3965 *
3966 * @param pVCpu The cross context virtual CPU structure.
3967 * @param offReg The offset of the 256-bit spare register.
3968 * @param uVector The vector to set.
3969 *
3970 * @remarks This is based on our APIC device code.
3971 */
3972IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3973{
3974 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3975 Assert(pVmcs);
3976
3977 /* Determine the vector offset within the chunk. */
3978 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3979
3980 /* Read the chunk at the offset. */
3981 uint32_t uReg;
3982 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3983 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3984 if (RT_SUCCESS(rc))
3985 {
3986 /* Modify the chunk. */
3987 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3988 uReg |= RT_BIT(idxVectorBit);
3989
3990 /* Write the chunk. */
3991 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3992 if (RT_SUCCESS(rc))
3993 { /* likely */ }
3994 else
3995 {
3996 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
3997 uVector, offReg, GCPhysVirtApic));
3998 }
3999 }
4000 else
4001 {
4002 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4003 uVector, offReg, GCPhysVirtApic));
4004 }
4005}
4006
4007
4008/**
4009 * Clears the vector in a virtual-APIC 256-bit sparse register.
4010 *
4011 * @param pVCpu The cross context virtual CPU structure.
4012 * @param offReg The offset of the 256-bit spare register.
4013 * @param uVector The vector to clear.
4014 *
4015 * @remarks This is based on our APIC device code.
4016 */
4017IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4018{
4019 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4020 Assert(pVmcs);
4021
4022 /* Determine the vector offset within the chunk. */
4023 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4024
4025 /* Read the chunk at the offset. */
4026 uint32_t uReg;
4027 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4028 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4029 if (RT_SUCCESS(rc))
4030 {
4031 /* Modify the chunk. */
4032 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4033 uReg &= ~RT_BIT(idxVectorBit);
4034
4035 /* Write the chunk. */
4036 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4037 if (RT_SUCCESS(rc))
4038 { /* likely */ }
4039 else
4040 {
4041 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4042 uVector, offReg, GCPhysVirtApic));
4043 }
4044 }
4045 else
4046 {
4047 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4048 uVector, offReg, GCPhysVirtApic));
4049 }
4050}
4051
4052
4053/**
4054 * Checks if a memory access to the APIC-access page must causes an APIC-access
4055 * VM-exit.
4056 *
4057 * @param pVCpu The cross context virtual CPU structure.
4058 * @param offAccess The offset of the register being accessed.
4059 * @param cbAccess The size of the access in bytes.
4060 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4061 * IEM_ACCESS_TYPE_WRITE).
4062 *
4063 * @remarks This must not be used for MSR-based APIC-access page accesses!
4064 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4065 */
4066IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4067{
4068 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4069 Assert(pVmcs);
4070 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4071
4072 /*
4073 * We must cause a VM-exit if any of the following are true:
4074 * - TPR shadowing isn't active.
4075 * - The access size exceeds 32-bits.
4076 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4077 *
4078 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4079 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4080 */
4081 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4082 || cbAccess > sizeof(uint32_t)
4083 || ((offAccess + cbAccess - 1) & 0xc)
4084 || offAccess >= XAPIC_OFF_END + 4)
4085 return true;
4086
4087 /*
4088 * If the access is part of an operation where we have already
4089 * virtualized a virtual-APIC write, we must cause a VM-exit.
4090 */
4091 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4092 return true;
4093
4094 /*
4095 * Check write accesses to the APIC-access page that cause VM-exits.
4096 */
4097 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4098 {
4099 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4100 {
4101 /*
4102 * With APIC-register virtualization, a write access to any of the
4103 * following registers are virtualized. Accessing any other register
4104 * causes a VM-exit.
4105 */
4106 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4107 switch (offAlignedAccess)
4108 {
4109 case XAPIC_OFF_ID:
4110 case XAPIC_OFF_TPR:
4111 case XAPIC_OFF_EOI:
4112 case XAPIC_OFF_LDR:
4113 case XAPIC_OFF_DFR:
4114 case XAPIC_OFF_SVR:
4115 case XAPIC_OFF_ESR:
4116 case XAPIC_OFF_ICR_LO:
4117 case XAPIC_OFF_ICR_HI:
4118 case XAPIC_OFF_LVT_TIMER:
4119 case XAPIC_OFF_LVT_THERMAL:
4120 case XAPIC_OFF_LVT_PERF:
4121 case XAPIC_OFF_LVT_LINT0:
4122 case XAPIC_OFF_LVT_LINT1:
4123 case XAPIC_OFF_LVT_ERROR:
4124 case XAPIC_OFF_TIMER_ICR:
4125 case XAPIC_OFF_TIMER_DCR:
4126 break;
4127 default:
4128 return true;
4129 }
4130 }
4131 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4132 {
4133 /*
4134 * With virtual-interrupt delivery, a write access to any of the
4135 * following registers are virtualized. Accessing any other register
4136 * causes a VM-exit.
4137 *
4138 * Note! The specification does not allow writing to offsets in-between
4139 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4140 */
4141 switch (offAccess)
4142 {
4143 case XAPIC_OFF_TPR:
4144 case XAPIC_OFF_EOI:
4145 case XAPIC_OFF_ICR_LO:
4146 break;
4147 default:
4148 return true;
4149 }
4150 }
4151 else
4152 {
4153 /*
4154 * Without APIC-register virtualization or virtual-interrupt delivery,
4155 * only TPR accesses are virtualized.
4156 */
4157 if (offAccess == XAPIC_OFF_TPR)
4158 { /* likely */ }
4159 else
4160 return true;
4161 }
4162 }
4163 else
4164 {
4165 /*
4166 * Check read accesses to the APIC-access page that cause VM-exits.
4167 */
4168 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4169 {
4170 /*
4171 * With APIC-register virtualization, a read access to any of the
4172 * following registers are virtualized. Accessing any other register
4173 * causes a VM-exit.
4174 */
4175 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4176 switch (offAlignedAccess)
4177 {
4178 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4179 case XAPIC_OFF_ID:
4180 case XAPIC_OFF_VERSION:
4181 case XAPIC_OFF_TPR:
4182 case XAPIC_OFF_EOI:
4183 case XAPIC_OFF_LDR:
4184 case XAPIC_OFF_DFR:
4185 case XAPIC_OFF_SVR:
4186 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4187 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4188 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4189 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4190 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4191 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4192 case XAPIC_OFF_ESR:
4193 case XAPIC_OFF_ICR_LO:
4194 case XAPIC_OFF_ICR_HI:
4195 case XAPIC_OFF_LVT_TIMER:
4196 case XAPIC_OFF_LVT_THERMAL:
4197 case XAPIC_OFF_LVT_PERF:
4198 case XAPIC_OFF_LVT_LINT0:
4199 case XAPIC_OFF_LVT_LINT1:
4200 case XAPIC_OFF_LVT_ERROR:
4201 case XAPIC_OFF_TIMER_ICR:
4202 case XAPIC_OFF_TIMER_DCR:
4203 break;
4204 default:
4205 return true;
4206 }
4207 }
4208 else
4209 {
4210 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4211 if (offAccess == XAPIC_OFF_TPR)
4212 { /* likely */ }
4213 else
4214 return true;
4215 }
4216 }
4217
4218 /* The APIC access is virtualized, does not cause a VM-exit. */
4219 return false;
4220}
4221
4222
4223/**
4224 * Virtualizes a memory-based APIC access where the address is not used to access
4225 * memory.
4226 *
4227 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4228 * page-faults but do not use the address to access memory.
4229 *
4230 * @param pVCpu The cross context virtual CPU structure.
4231 * @param pGCPhysAccess Pointer to the guest-physical address used.
4232 */
4233IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4234{
4235 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4236 Assert(pVmcs);
4237 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4238 Assert(pGCPhysAccess);
4239
4240 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4241 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4242 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4243
4244 if (GCPhysAccess == GCPhysApic)
4245 {
4246 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4247 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4248 uint16_t const cbAccess = 1;
4249 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4250 if (fIntercept)
4251 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4252
4253 *pGCPhysAccess = GCPhysApic | offAccess;
4254 return VINF_VMX_MODIFIES_BEHAVIOR;
4255 }
4256
4257 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4258}
4259
4260
4261/**
4262 * Virtualizes a memory-based APIC access.
4263 *
4264 * @returns VBox strict status code.
4265 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4266 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4267 *
4268 * @param pVCpu The cross context virtual CPU structure.
4269 * @param offAccess The offset of the register being accessed (within the
4270 * APIC-access page).
4271 * @param cbAccess The size of the access in bytes.
4272 * @param pvData Pointer to the data being written or where to store the data
4273 * being read.
4274 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4275 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4276 */
4277IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4278 uint32_t fAccess)
4279{
4280 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4281 Assert(pVmcs);
4282 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4283 Assert(pvData);
4284 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4285 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4286 || (fAccess & IEM_ACCESS_INSTRUCTION));
4287
4288 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4289 if (fIntercept)
4290 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4291
4292 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4293 {
4294 /*
4295 * A write access to the APIC-access page that is virtualized (rather than
4296 * causing a VM-exit) writes data to the virtual-APIC page.
4297 */
4298 uint32_t const u32Data = *(uint32_t *)pvData;
4299 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4300
4301 /*
4302 * Record the currently updated APIC offset, as we need this later for figuring
4303 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4304 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4305 *
4306 * After completion of the current operation, we need to perform TPR virtualization,
4307 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4308 *
4309 * The current operation may be a REP-prefixed string instruction, execution of any
4310 * other instruction, or delivery of an event through the IDT.
4311 *
4312 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4313 * performed now but later after completion of the current operation.
4314 *
4315 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4316 */
4317 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4318 }
4319 else
4320 {
4321 /*
4322 * A read access from the APIC-access page that is virtualized (rather than
4323 * causing a VM-exit) returns data from the virtual-APIC page.
4324 *
4325 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4326 */
4327 Assert(cbAccess <= 4);
4328 Assert(offAccess < XAPIC_OFF_END + 4);
4329 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4330
4331 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4332 u32Data &= s_auAccessSizeMasks[cbAccess];
4333 *(uint32_t *)pvData = u32Data;
4334 }
4335
4336 return VINF_VMX_MODIFIES_BEHAVIOR;
4337}
4338
4339
4340/**
4341 * Virtualizes an MSR-based APIC read access.
4342 *
4343 * @returns VBox strict status code.
4344 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4345 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4346 * handled by the x2APIC device.
4347 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4348 * not within the range of valid MSRs, caller must raise \#GP(0).
4349 * @param pVCpu The cross context virtual CPU structure.
4350 * @param idMsr The x2APIC MSR being read.
4351 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4352 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4353 */
4354IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4355{
4356 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4357 Assert(pVmcs);
4358 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4359 Assert(pu64Value);
4360
4361 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4362 {
4363 /*
4364 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4365 * what the end of the valid x2APIC MSR range is. Hence the use of different
4366 * macros here.
4367 *
4368 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4369 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4370 */
4371 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4372 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4373 {
4374 uint16_t const offReg = (idMsr & 0xff) << 4;
4375 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4376 *pu64Value = u64Value;
4377 return VINF_VMX_MODIFIES_BEHAVIOR;
4378 }
4379 return VERR_OUT_OF_RANGE;
4380 }
4381
4382 if (idMsr == MSR_IA32_X2APIC_TPR)
4383 {
4384 uint16_t const offReg = (idMsr & 0xff) << 4;
4385 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4386 *pu64Value = u64Value;
4387 return VINF_VMX_MODIFIES_BEHAVIOR;
4388 }
4389
4390 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4391}
4392
4393
4394/**
4395 * Virtualizes an MSR-based APIC write access.
4396 *
4397 * @returns VBox strict status code.
4398 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4399 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4400 * not within the range of valid MSRs, caller must raise \#GP(0).
4401 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4402 *
4403 * @param pVCpu The cross context virtual CPU structure.
4404 * @param idMsr The x2APIC MSR being written.
4405 * @param u64Value The value of the x2APIC MSR being written.
4406 */
4407IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4408{
4409 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4410 Assert(pVmcs);
4411
4412 /*
4413 * Check if the access is to be virtualized.
4414 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4415 */
4416 if ( idMsr == MSR_IA32_X2APIC_TPR
4417 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4418 && ( idMsr == MSR_IA32_X2APIC_EOI
4419 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4420 {
4421 /* Validate the MSR write depending on the register. */
4422 switch (idMsr)
4423 {
4424 case MSR_IA32_X2APIC_TPR:
4425 case MSR_IA32_X2APIC_SELF_IPI:
4426 {
4427 if (u64Value & UINT64_C(0xffffffffffffff00))
4428 return VERR_OUT_OF_RANGE;
4429 break;
4430 }
4431 case MSR_IA32_X2APIC_EOI:
4432 {
4433 if (u64Value != 0)
4434 return VERR_OUT_OF_RANGE;
4435 break;
4436 }
4437 }
4438
4439 /* Write the MSR to the virtual-APIC page. */
4440 uint16_t const offReg = (idMsr & 0xff) << 4;
4441 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4442
4443 /*
4444 * Record the currently updated APIC offset, as we need this later for figuring
4445 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4446 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4447 */
4448 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4449
4450 return VINF_VMX_MODIFIES_BEHAVIOR;
4451 }
4452
4453 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4454}
4455
4456
4457/**
4458 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4459 *
4460 * @returns VBox status code.
4461 * @retval VINF_SUCCESS when the highest set bit is found.
4462 * @retval VERR_NOT_FOUND when no bit is set.
4463 *
4464 * @param pVCpu The cross context virtual CPU structure.
4465 * @param offReg The offset of the APIC 256-bit sparse register.
4466 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4467 * set in the register. Only valid when VINF_SUCCESS is
4468 * returned.
4469 *
4470 * @remarks The format of the 256-bit sparse register here mirrors that found in
4471 * real APIC hardware.
4472 */
4473static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4474{
4475 Assert(offReg < XAPIC_OFF_END + 4);
4476 Assert(pidxHighestBit);
4477 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4478
4479 /*
4480 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4481 * However, in each fragment only the first 4 bytes are used.
4482 */
4483 uint8_t const cFrags = 8;
4484 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4485 {
4486 uint16_t const offFrag = iFrag * 16;
4487 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4488 if (!u32Frag)
4489 continue;
4490
4491 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4492 Assert(idxHighestBit > 0);
4493 --idxHighestBit;
4494 Assert(idxHighestBit <= UINT8_MAX);
4495 *pidxHighestBit = idxHighestBit;
4496 return VINF_SUCCESS;
4497 }
4498 return VERR_NOT_FOUND;
4499}
4500
4501
4502/**
4503 * Evaluates pending virtual interrupts.
4504 *
4505 * @param pVCpu The cross context virtual CPU structure.
4506 */
4507IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4508{
4509 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4510 Assert(pVmcs);
4511 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4512
4513 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4514 {
4515 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4516 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4517
4518 if ((uRvi >> 4) > (uPpr >> 4))
4519 {
4520 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4521 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4522 }
4523 else
4524 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4525 }
4526}
4527
4528
4529/**
4530 * Performs PPR virtualization.
4531 *
4532 * @returns VBox strict status code.
4533 * @param pVCpu The cross context virtual CPU structure.
4534 */
4535IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4536{
4537 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4538 Assert(pVmcs);
4539 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4540 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4541
4542 /*
4543 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4544 * or EOI-virtualization.
4545 *
4546 * See Intel spec. 29.1.3 "PPR Virtualization".
4547 */
4548 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4549 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4550
4551 uint32_t uPpr;
4552 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4553 uPpr = uTpr & 0xff;
4554 else
4555 uPpr = uSvi & 0xf0;
4556
4557 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4558 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4559}
4560
4561
4562/**
4563 * Performs VMX TPR virtualization.
4564 *
4565 * @returns VBox strict status code.
4566 * @param pVCpu The cross context virtual CPU structure.
4567 */
4568IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4569{
4570 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4571 Assert(pVmcs);
4572 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4573
4574 /*
4575 * We should have already performed the virtual-APIC write to the TPR offset
4576 * in the virtual-APIC page. We now perform TPR virtualization.
4577 *
4578 * See Intel spec. 29.1.2 "TPR Virtualization".
4579 */
4580 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4581 {
4582 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4583 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4584
4585 /*
4586 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4587 * See Intel spec. 29.1.2 "TPR Virtualization".
4588 */
4589 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4590 {
4591 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4592 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4593 }
4594 }
4595 else
4596 {
4597 iemVmxPprVirtualization(pVCpu);
4598 iemVmxEvalPendingVirtIntrs(pVCpu);
4599 }
4600
4601 return VINF_SUCCESS;
4602}
4603
4604
4605/**
4606 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4607 * not.
4608 *
4609 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4610 * @param pVCpu The cross context virtual CPU structure.
4611 * @param uVector The interrupt that was acknowledged using an EOI.
4612 */
4613IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4614{
4615 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4616 Assert(pVmcs);
4617 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4618
4619 if (uVector < 64)
4620 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4621 if (uVector < 128)
4622 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4623 if (uVector < 192)
4624 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4625 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4626}
4627
4628
4629/**
4630 * Performs EOI virtualization.
4631 *
4632 * @returns VBox strict status code.
4633 * @param pVCpu The cross context virtual CPU structure.
4634 */
4635IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4636{
4637 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4638 Assert(pVmcs);
4639 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4640
4641 /*
4642 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4643 * and get the next guest-interrupt that's in-service (if any).
4644 *
4645 * See Intel spec. 29.1.4 "EOI Virtualization".
4646 */
4647 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4648 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4649 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4650
4651 uint8_t uVector = uSvi;
4652 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4653
4654 uVector = 0;
4655 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4656
4657 if (uVector)
4658 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4659 else
4660 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4661
4662 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4663 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4664
4665 iemVmxPprVirtualization(pVCpu);
4666 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4667 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4668 iemVmxEvalPendingVirtIntrs(pVCpu);
4669 return VINF_SUCCESS;
4670}
4671
4672
4673/**
4674 * Performs self-IPI virtualization.
4675 *
4676 * @returns VBox strict status code.
4677 * @param pVCpu The cross context virtual CPU structure.
4678 */
4679IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4680{
4681 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4682 Assert(pVmcs);
4683 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4684
4685 /*
4686 * We should have already performed the virtual-APIC write to the self-IPI offset
4687 * in the virtual-APIC page. We now perform self-IPI virtualization.
4688 *
4689 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4690 */
4691 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4692 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4693 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4694 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4695 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4696 if (uVector > uRvi)
4697 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4698 iemVmxEvalPendingVirtIntrs(pVCpu);
4699 return VINF_SUCCESS;
4700}
4701
4702
4703/**
4704 * Performs VMX APIC-write emulation.
4705 *
4706 * @returns VBox strict status code.
4707 * @param pVCpu The cross context virtual CPU structure.
4708 */
4709IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4710{
4711 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4712 Assert(pVmcs);
4713
4714 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4715 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4716
4717 /*
4718 * Perform APIC-write emulation based on the virtual-APIC register written.
4719 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4720 */
4721 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4722 VBOXSTRICTRC rcStrict;
4723 switch (offApicWrite)
4724 {
4725 case XAPIC_OFF_TPR:
4726 {
4727 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4728 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4729 uTpr &= UINT32_C(0x000000ff);
4730 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4731 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4732 rcStrict = iemVmxTprVirtualization(pVCpu);
4733 break;
4734 }
4735
4736 case XAPIC_OFF_EOI:
4737 {
4738 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4739 {
4740 /* Clear VEOI and perform EOI virtualization. */
4741 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4742 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4743 rcStrict = iemVmxEoiVirtualization(pVCpu);
4744 }
4745 else
4746 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4747 break;
4748 }
4749
4750 case XAPIC_OFF_ICR_LO:
4751 {
4752 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4753 {
4754 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4755 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4756 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4757 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4758 if ( !(uIcrLo & fIcrLoMb0)
4759 && (uIcrLo & fIcrLoMb1))
4760 {
4761 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4762 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4763 }
4764 else
4765 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4766 }
4767 else
4768 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4769 break;
4770 }
4771
4772 case XAPIC_OFF_ICR_HI:
4773 {
4774 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4775 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4776 uIcrHi &= UINT32_C(0xff000000);
4777 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4778 rcStrict = VINF_SUCCESS;
4779 break;
4780 }
4781
4782 default:
4783 {
4784 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4785 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4786 break;
4787 }
4788 }
4789
4790 return rcStrict;
4791}
4792
4793
4794/**
4795 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4796 *
4797 * @param pVCpu The cross context virtual CPU structure.
4798 * @param pszInstr The VMX instruction name (for logging purposes).
4799 */
4800IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4801{
4802 /*
4803 * Guest Control Registers, Debug Registers, and MSRs.
4804 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4805 */
4806 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4807 const char *const pszFailure = "VM-exit";
4808 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4809
4810 /* CR0 reserved bits. */
4811 {
4812 /* CR0 MB1 bits. */
4813 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4814 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4815 if (fUnrestrictedGuest)
4816 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4817 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4818 { /* likely */ }
4819 else
4820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4821
4822 /* CR0 MBZ bits. */
4823 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4824 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4825 { /* likely */ }
4826 else
4827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4828
4829 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4830 if ( !fUnrestrictedGuest
4831 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4832 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4834 }
4835
4836 /* CR4 reserved bits. */
4837 {
4838 /* CR4 MB1 bits. */
4839 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4840 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4841 { /* likely */ }
4842 else
4843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4844
4845 /* CR4 MBZ bits. */
4846 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4847 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4848 { /* likely */ }
4849 else
4850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4851 }
4852
4853 /* DEBUGCTL MSR. */
4854 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4855 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4856 { /* likely */ }
4857 else
4858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4859
4860 /* 64-bit CPU checks. */
4861 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4862 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4863 {
4864 if (fGstInLongMode)
4865 {
4866 /* PAE must be set. */
4867 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4868 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4869 { /* likely */ }
4870 else
4871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4872 }
4873 else
4874 {
4875 /* PCIDE should not be set. */
4876 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4877 { /* likely */ }
4878 else
4879 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4880 }
4881
4882 /* CR3. */
4883 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4884 { /* likely */ }
4885 else
4886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4887
4888 /* DR7. */
4889 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4890 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4891 { /* likely */ }
4892 else
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4894
4895 /* SYSENTER ESP and SYSENTER EIP. */
4896 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4897 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4898 { /* likely */ }
4899 else
4900 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4901 }
4902
4903 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4904 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4905
4906 /* PAT MSR. */
4907 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4908 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4909 { /* likely */ }
4910 else
4911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4912
4913 /* EFER MSR. */
4914 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4915 {
4916 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4917 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4918 { /* likely */ }
4919 else
4920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4921
4922 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4923 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4924 if ( fGstLma == fGstInLongMode
4925 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4926 || fGstLma == fGstLme))
4927 { /* likely */ }
4928 else
4929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4930 }
4931
4932 /* We don't support IA32_BNDCFGS MSR yet. */
4933 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4934
4935 NOREF(pszInstr);
4936 NOREF(pszFailure);
4937 return VINF_SUCCESS;
4938}
4939
4940
4941/**
4942 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4943 *
4944 * @param pVCpu The cross context virtual CPU structure.
4945 * @param pszInstr The VMX instruction name (for logging purposes).
4946 */
4947IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4948{
4949 /*
4950 * Segment registers.
4951 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4952 */
4953 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4954 const char *const pszFailure = "VM-exit";
4955 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4956 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4957 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4958
4959 /* Selectors. */
4960 if ( !fGstInV86Mode
4961 && !fUnrestrictedGuest
4962 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4964
4965 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4966 {
4967 CPUMSELREG SelReg;
4968 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4969 if (RT_LIKELY(rc == VINF_SUCCESS))
4970 { /* likely */ }
4971 else
4972 return rc;
4973
4974 /*
4975 * Virtual-8086 mode checks.
4976 */
4977 if (fGstInV86Mode)
4978 {
4979 /* Base address. */
4980 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4981 { /* likely */ }
4982 else
4983 {
4984 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4986 }
4987
4988 /* Limit. */
4989 if (SelReg.u32Limit == 0xffff)
4990 { /* likely */ }
4991 else
4992 {
4993 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4995 }
4996
4997 /* Attribute. */
4998 if (SelReg.Attr.u == 0xf3)
4999 { /* likely */ }
5000 else
5001 {
5002 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5003 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5004 }
5005
5006 /* We're done; move to checking the next segment. */
5007 continue;
5008 }
5009
5010 /* Checks done by 64-bit CPUs. */
5011 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5012 {
5013 /* Base address. */
5014 if ( iSegReg == X86_SREG_FS
5015 || iSegReg == X86_SREG_GS)
5016 {
5017 if (X86_IS_CANONICAL(SelReg.u64Base))
5018 { /* likely */ }
5019 else
5020 {
5021 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5023 }
5024 }
5025 else if (iSegReg == X86_SREG_CS)
5026 {
5027 if (!RT_HI_U32(SelReg.u64Base))
5028 { /* likely */ }
5029 else
5030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5031 }
5032 else
5033 {
5034 if ( SelReg.Attr.n.u1Unusable
5035 || !RT_HI_U32(SelReg.u64Base))
5036 { /* likely */ }
5037 else
5038 {
5039 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5041 }
5042 }
5043 }
5044
5045 /*
5046 * Checks outside Virtual-8086 mode.
5047 */
5048 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5049 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5050 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5051 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5052 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5053 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5054 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5055 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5056
5057 /* Code or usable segment. */
5058 if ( iSegReg == X86_SREG_CS
5059 || fUsable)
5060 {
5061 /* Reserved bits (bits 31:17 and bits 11:8). */
5062 if (!(SelReg.Attr.u & 0xfffe0f00))
5063 { /* likely */ }
5064 else
5065 {
5066 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5068 }
5069
5070 /* Descriptor type. */
5071 if (fCodeDataSeg)
5072 { /* likely */ }
5073 else
5074 {
5075 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5076 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5077 }
5078
5079 /* Present. */
5080 if (fPresent)
5081 { /* likely */ }
5082 else
5083 {
5084 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5086 }
5087
5088 /* Granularity. */
5089 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5090 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5091 { /* likely */ }
5092 else
5093 {
5094 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5096 }
5097 }
5098
5099 if (iSegReg == X86_SREG_CS)
5100 {
5101 /* Segment Type and DPL. */
5102 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5103 && fUnrestrictedGuest)
5104 {
5105 if (uDpl == 0)
5106 { /* likely */ }
5107 else
5108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5109 }
5110 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5111 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5112 {
5113 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5114 if (uDpl == AttrSs.n.u2Dpl)
5115 { /* likely */ }
5116 else
5117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5118 }
5119 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5120 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5121 {
5122 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5123 if (uDpl <= AttrSs.n.u2Dpl)
5124 { /* likely */ }
5125 else
5126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5127 }
5128 else
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5130
5131 /* Def/Big. */
5132 if ( fGstInLongMode
5133 && fSegLong)
5134 {
5135 if (uDefBig == 0)
5136 { /* likely */ }
5137 else
5138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5139 }
5140 }
5141 else if (iSegReg == X86_SREG_SS)
5142 {
5143 /* Segment Type. */
5144 if ( !fUsable
5145 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5146 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5147 { /* likely */ }
5148 else
5149 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5150
5151 /* DPL. */
5152 if (!fUnrestrictedGuest)
5153 {
5154 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5155 { /* likely */ }
5156 else
5157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5158 }
5159 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5160 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5161 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5162 {
5163 if (uDpl == 0)
5164 { /* likely */ }
5165 else
5166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5167 }
5168 }
5169 else
5170 {
5171 /* DS, ES, FS, GS. */
5172 if (fUsable)
5173 {
5174 /* Segment type. */
5175 if (uSegType & X86_SEL_TYPE_ACCESSED)
5176 { /* likely */ }
5177 else
5178 {
5179 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5181 }
5182
5183 if ( !(uSegType & X86_SEL_TYPE_CODE)
5184 || (uSegType & X86_SEL_TYPE_READ))
5185 { /* likely */ }
5186 else
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5188
5189 /* DPL. */
5190 if ( !fUnrestrictedGuest
5191 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5192 {
5193 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5194 { /* likely */ }
5195 else
5196 {
5197 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5198 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5199 }
5200 }
5201 }
5202 }
5203 }
5204
5205 /*
5206 * LDTR.
5207 */
5208 {
5209 CPUMSELREG Ldtr;
5210 Ldtr.Sel = pVmcs->GuestLdtr;
5211 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5212 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5213 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5214
5215 if (!Ldtr.Attr.n.u1Unusable)
5216 {
5217 /* Selector. */
5218 if (!(Ldtr.Sel & X86_SEL_LDT))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5222
5223 /* Base. */
5224 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5225 {
5226 if (X86_IS_CANONICAL(Ldtr.u64Base))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5230 }
5231
5232 /* Attributes. */
5233 /* Reserved bits (bits 31:17 and bits 11:8). */
5234 if (!(Ldtr.Attr.u & 0xfffe0f00))
5235 { /* likely */ }
5236 else
5237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5238
5239 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5240 { /* likely */ }
5241 else
5242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5243
5244 if (!Ldtr.Attr.n.u1DescType)
5245 { /* likely */ }
5246 else
5247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5248
5249 if (Ldtr.Attr.n.u1Present)
5250 { /* likely */ }
5251 else
5252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5253
5254 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5255 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5256 { /* likely */ }
5257 else
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5259 }
5260 }
5261
5262 /*
5263 * TR.
5264 */
5265 {
5266 CPUMSELREG Tr;
5267 Tr.Sel = pVmcs->GuestTr;
5268 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5269 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5270 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5271
5272 /* Selector. */
5273 if (!(Tr.Sel & X86_SEL_LDT))
5274 { /* likely */ }
5275 else
5276 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5277
5278 /* Base. */
5279 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5280 {
5281 if (X86_IS_CANONICAL(Tr.u64Base))
5282 { /* likely */ }
5283 else
5284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5285 }
5286
5287 /* Attributes. */
5288 /* Reserved bits (bits 31:17 and bits 11:8). */
5289 if (!(Tr.Attr.u & 0xfffe0f00))
5290 { /* likely */ }
5291 else
5292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5293
5294 if (!Tr.Attr.n.u1Unusable)
5295 { /* likely */ }
5296 else
5297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5298
5299 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5300 || ( !fGstInLongMode
5301 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5302 { /* likely */ }
5303 else
5304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5305
5306 if (!Tr.Attr.n.u1DescType)
5307 { /* likely */ }
5308 else
5309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5310
5311 if (Tr.Attr.n.u1Present)
5312 { /* likely */ }
5313 else
5314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5315
5316 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5317 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5318 { /* likely */ }
5319 else
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5321 }
5322
5323 NOREF(pszInstr);
5324 NOREF(pszFailure);
5325 return VINF_SUCCESS;
5326}
5327
5328
5329/**
5330 * Checks guest GDTR and IDTR as part of VM-entry.
5331 *
5332 * @param pVCpu The cross context virtual CPU structure.
5333 * @param pszInstr The VMX instruction name (for logging purposes).
5334 */
5335IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5336{
5337 /*
5338 * GDTR and IDTR.
5339 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5340 */
5341 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5342 const char *const pszFailure = "VM-exit";
5343
5344 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5345 {
5346 /* Base. */
5347 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5348 { /* likely */ }
5349 else
5350 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5351
5352 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5353 { /* likely */ }
5354 else
5355 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5356 }
5357
5358 /* Limit. */
5359 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5360 { /* likely */ }
5361 else
5362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5363
5364 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5365 { /* likely */ }
5366 else
5367 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5368
5369 NOREF(pszInstr);
5370 NOREF(pszFailure);
5371 return VINF_SUCCESS;
5372}
5373
5374
5375/**
5376 * Checks guest RIP and RFLAGS as part of VM-entry.
5377 *
5378 * @param pVCpu The cross context virtual CPU structure.
5379 * @param pszInstr The VMX instruction name (for logging purposes).
5380 */
5381IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5382{
5383 /*
5384 * RIP and RFLAGS.
5385 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5386 */
5387 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5388 const char *const pszFailure = "VM-exit";
5389 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5390
5391 /* RIP. */
5392 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5393 {
5394 X86DESCATTR AttrCs;
5395 AttrCs.u = pVmcs->u32GuestCsAttr;
5396 if ( !fGstInLongMode
5397 || !AttrCs.n.u1Long)
5398 {
5399 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5400 { /* likely */ }
5401 else
5402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5403 }
5404
5405 if ( fGstInLongMode
5406 && AttrCs.n.u1Long)
5407 {
5408 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5409 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5410 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5411 { /* likely */ }
5412 else
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5414 }
5415 }
5416
5417 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5418 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5419 : pVmcs->u64GuestRFlags.s.Lo;
5420 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5421 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5422 { /* likely */ }
5423 else
5424 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5425
5426 if ( fGstInLongMode
5427 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5428 {
5429 if (!(uGuestRFlags & X86_EFL_VM))
5430 { /* likely */ }
5431 else
5432 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5433 }
5434
5435 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5436 {
5437 if (uGuestRFlags & X86_EFL_IF)
5438 { /* likely */ }
5439 else
5440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5441 }
5442
5443 NOREF(pszInstr);
5444 NOREF(pszFailure);
5445 return VINF_SUCCESS;
5446}
5447
5448
5449/**
5450 * Checks guest non-register state as part of VM-entry.
5451 *
5452 * @param pVCpu The cross context virtual CPU structure.
5453 * @param pszInstr The VMX instruction name (for logging purposes).
5454 */
5455IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5456{
5457 /*
5458 * Guest non-register state.
5459 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5460 */
5461 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5462 const char *const pszFailure = "VM-exit";
5463
5464 /*
5465 * Activity state.
5466 */
5467 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5468 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5469 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5470 { /* likely */ }
5471 else
5472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5473
5474 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5475 if ( !AttrSs.n.u2Dpl
5476 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5477 { /* likely */ }
5478 else
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5480
5481 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5482 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5483 {
5484 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5488 }
5489
5490 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5491 {
5492 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5493 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5494 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5495 switch (pVmcs->u32GuestActivityState)
5496 {
5497 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5498 {
5499 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5500 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5501 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5502 && ( uVector == X86_XCPT_DB
5503 || uVector == X86_XCPT_MC))
5504 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5505 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5506 { /* likely */ }
5507 else
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5509 break;
5510 }
5511
5512 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5513 {
5514 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5515 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5516 && uVector == X86_XCPT_MC))
5517 { /* likely */ }
5518 else
5519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5520 break;
5521 }
5522
5523 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5524 default:
5525 break;
5526 }
5527 }
5528
5529 /*
5530 * Interruptibility state.
5531 */
5532 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5533 { /* likely */ }
5534 else
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5536
5537 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5538 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5539 { /* likely */ }
5540 else
5541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5542
5543 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5544 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5545 { /* likely */ }
5546 else
5547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5548
5549 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5550 {
5551 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5552 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5553 {
5554 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5555 { /* likely */ }
5556 else
5557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5558 }
5559 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5560 {
5561 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5562 { /* likely */ }
5563 else
5564 {
5565 /*
5566 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5567 * We update the Exit qualification only when blocking-by-STI is set
5568 * without blocking-by-MovSS being set. Although in practise it does not
5569 * make much difference since the order of checks are implementation defined.
5570 */
5571 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5572 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5574 }
5575
5576 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5577 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5578 { /* likely */ }
5579 else
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5581 }
5582 }
5583
5584 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5585 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5586 { /* likely */ }
5587 else
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5589
5590 /* We don't support SGX yet. So enclave-interruption must not be set. */
5591 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5592 { /* likely */ }
5593 else
5594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5595
5596 /*
5597 * Pending debug exceptions.
5598 */
5599 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5600 ? pVmcs->u64GuestPendingDbgXcpts.u
5601 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5602 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5603 { /* likely */ }
5604 else
5605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5606
5607 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5608 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5609 {
5610 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5611 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5612 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5614
5615 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5616 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5617 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5619 }
5620
5621 /* We don't support RTM (Real-time Transactional Memory) yet. */
5622 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5623 { /* likely */ }
5624 else
5625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5626
5627 /*
5628 * VMCS link pointer.
5629 */
5630 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5631 {
5632 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5633 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5634 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5635 { /* likely */ }
5636 else
5637 {
5638 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5640 }
5641
5642 /* Validate the address. */
5643 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5644 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5645 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5646 { /* likely */ }
5647 else
5648 {
5649 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5651 }
5652
5653 /* Read the VMCS-link pointer from guest memory. */
5654 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5655 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5656 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5657 if (RT_SUCCESS(rc))
5658 { /* likely */ }
5659 else
5660 {
5661 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5662 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5663 }
5664
5665 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5666 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5667 { /* likely */ }
5668 else
5669 {
5670 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5671 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5672 }
5673
5674 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5675 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5676 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5677 { /* likely */ }
5678 else
5679 {
5680 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5682 }
5683
5684 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5685 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5686 }
5687
5688 NOREF(pszInstr);
5689 NOREF(pszFailure);
5690 return VINF_SUCCESS;
5691}
5692
5693
5694/**
5695 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5696 * VM-entry.
5697 *
5698 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5699 * @param pVCpu The cross context virtual CPU structure.
5700 * @param pszInstr The VMX instruction name (for logging purposes).
5701 * @param pVmcs Pointer to the virtual VMCS.
5702 */
5703IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5704{
5705 /*
5706 * Check PDPTEs.
5707 * See Intel spec. 4.4.1 "PDPTE Registers".
5708 */
5709 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5710 const char *const pszFailure = "VM-exit";
5711
5712 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5713 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5714 if (RT_SUCCESS(rc))
5715 {
5716 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5717 {
5718 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5719 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5720 { /* likely */ }
5721 else
5722 {
5723 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5724 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5726 }
5727 }
5728 }
5729 else
5730 {
5731 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5732 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5733 }
5734
5735 NOREF(pszFailure);
5736 NOREF(pszInstr);
5737 return rc;
5738}
5739
5740
5741/**
5742 * Checks guest PDPTEs as part of VM-entry.
5743 *
5744 * @param pVCpu The cross context virtual CPU structure.
5745 * @param pszInstr The VMX instruction name (for logging purposes).
5746 */
5747IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5748{
5749 /*
5750 * Guest PDPTEs.
5751 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5752 */
5753 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5754 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5755
5756 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5757 int rc;
5758 if ( !fGstInLongMode
5759 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5760 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5761 {
5762 /*
5763 * We don't support nested-paging for nested-guests yet.
5764 *
5765 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5766 * rather we need to check the PDPTEs referenced by the guest CR3.
5767 */
5768 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5769 }
5770 else
5771 rc = VINF_SUCCESS;
5772 return rc;
5773}
5774
5775
5776/**
5777 * Checks guest-state as part of VM-entry.
5778 *
5779 * @returns VBox status code.
5780 * @param pVCpu The cross context virtual CPU structure.
5781 * @param pszInstr The VMX instruction name (for logging purposes).
5782 */
5783IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5784{
5785 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5786 if (RT_SUCCESS(rc))
5787 {
5788 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5789 if (RT_SUCCESS(rc))
5790 {
5791 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5792 if (RT_SUCCESS(rc))
5793 {
5794 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5795 if (RT_SUCCESS(rc))
5796 {
5797 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5798 if (RT_SUCCESS(rc))
5799 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5800 }
5801 }
5802 }
5803 }
5804 return rc;
5805}
5806
5807
5808/**
5809 * Checks host-state as part of VM-entry.
5810 *
5811 * @returns VBox status code.
5812 * @param pVCpu The cross context virtual CPU structure.
5813 * @param pszInstr The VMX instruction name (for logging purposes).
5814 */
5815IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5816{
5817 /*
5818 * Host Control Registers and MSRs.
5819 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5820 */
5821 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5822 const char * const pszFailure = "VMFail";
5823
5824 /* CR0 reserved bits. */
5825 {
5826 /* CR0 MB1 bits. */
5827 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5828 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5829 { /* likely */ }
5830 else
5831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5832
5833 /* CR0 MBZ bits. */
5834 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5835 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5836 { /* likely */ }
5837 else
5838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5839 }
5840
5841 /* CR4 reserved bits. */
5842 {
5843 /* CR4 MB1 bits. */
5844 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5845 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5846 { /* likely */ }
5847 else
5848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5849
5850 /* CR4 MBZ bits. */
5851 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5852 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5856 }
5857
5858 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5859 {
5860 /* CR3 reserved bits. */
5861 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5862 { /* likely */ }
5863 else
5864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5865
5866 /* SYSENTER ESP and SYSENTER EIP. */
5867 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5868 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5872 }
5873
5874 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5875 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5876
5877 /* PAT MSR. */
5878 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5879 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5883
5884 /* EFER MSR. */
5885 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5886 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5887 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5888 { /* likely */ }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5891
5892 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5893 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5894 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5895 if ( fHostInLongMode == fHostLma
5896 && fHostInLongMode == fHostLme)
5897 { /* likely */ }
5898 else
5899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5900
5901 /*
5902 * Host Segment and Descriptor-Table Registers.
5903 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5904 */
5905 /* Selector RPL and TI. */
5906 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5907 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5908 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5909 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5910 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5911 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5912 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5916
5917 /* CS and TR selectors cannot be 0. */
5918 if ( pVmcs->HostCs
5919 && pVmcs->HostTr)
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5923
5924 /* SS cannot be 0 if 32-bit host. */
5925 if ( fHostInLongMode
5926 || pVmcs->HostSs)
5927 { /* likely */ }
5928 else
5929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5930
5931 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5932 {
5933 /* FS, GS, GDTR, IDTR, TR base address. */
5934 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5935 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5936 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5937 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5938 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5942 }
5943
5944 /*
5945 * Host address-space size for 64-bit CPUs.
5946 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5947 */
5948 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5949 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5950 {
5951 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5952
5953 /* Logical processor in IA-32e mode. */
5954 if (fCpuInLongMode)
5955 {
5956 if (fHostInLongMode)
5957 {
5958 /* PAE must be set. */
5959 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5963
5964 /* RIP must be canonical. */
5965 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5966 { /* likely */ }
5967 else
5968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5969 }
5970 else
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5972 }
5973 else
5974 {
5975 /* Logical processor is outside IA-32e mode. */
5976 if ( !fGstInLongMode
5977 && !fHostInLongMode)
5978 {
5979 /* PCIDE should not be set. */
5980 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5981 { /* likely */ }
5982 else
5983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5984
5985 /* The high 32-bits of RIP MBZ. */
5986 if (!pVmcs->u64HostRip.s.Hi)
5987 { /* likely */ }
5988 else
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5990 }
5991 else
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5993 }
5994 }
5995 else
5996 {
5997 /* Host address-space size for 32-bit CPUs. */
5998 if ( !fGstInLongMode
5999 && !fHostInLongMode)
6000 { /* likely */ }
6001 else
6002 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6003 }
6004
6005 NOREF(pszInstr);
6006 NOREF(pszFailure);
6007 return VINF_SUCCESS;
6008}
6009
6010
6011/**
6012 * Checks VM-entry controls fields as part of VM-entry.
6013 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6014 *
6015 * @returns VBox status code.
6016 * @param pVCpu The cross context virtual CPU structure.
6017 * @param pszInstr The VMX instruction name (for logging purposes).
6018 */
6019IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPUCC pVCpu, const char *pszInstr)
6020{
6021 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6022 const char * const pszFailure = "VMFail";
6023
6024 /* VM-entry controls. */
6025 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6026 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6027 { /* likely */ }
6028 else
6029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6030
6031 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6032 { /* likely */ }
6033 else
6034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6035
6036 /* Event injection. */
6037 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6038 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6039 {
6040 /* Type and vector. */
6041 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6042 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6043 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6044 if ( !uRsvd
6045 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6046 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6047 { /* likely */ }
6048 else
6049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6050
6051 /* Exception error code. */
6052 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6053 {
6054 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6055 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6056 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6057 { /* likely */ }
6058 else
6059 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6060
6061 /* Exceptions that provide an error code. */
6062 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6063 && ( uVector == X86_XCPT_DF
6064 || uVector == X86_XCPT_TS
6065 || uVector == X86_XCPT_NP
6066 || uVector == X86_XCPT_SS
6067 || uVector == X86_XCPT_GP
6068 || uVector == X86_XCPT_PF
6069 || uVector == X86_XCPT_AC))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6073
6074 /* Exception error-code reserved bits. */
6075 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6076 { /* likely */ }
6077 else
6078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6079
6080 /* Injecting a software interrupt, software exception or privileged software exception. */
6081 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6082 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6083 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6084 {
6085 /* Instruction length must be in the range 0-15. */
6086 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6087 { /* likely */ }
6088 else
6089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6090
6091 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6092 if ( pVmcs->u32EntryInstrLen != 0
6093 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6094 { /* likely */ }
6095 else
6096 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6097 }
6098 }
6099 }
6100
6101 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6102 if (pVmcs->u32EntryMsrLoadCount)
6103 {
6104 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6105 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6106 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6107 { /* likely */ }
6108 else
6109 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6110 }
6111
6112 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6113 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6114
6115 NOREF(pszInstr);
6116 NOREF(pszFailure);
6117 return VINF_SUCCESS;
6118}
6119
6120
6121/**
6122 * Checks VM-exit controls fields as part of VM-entry.
6123 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6124 *
6125 * @returns VBox status code.
6126 * @param pVCpu The cross context virtual CPU structure.
6127 * @param pszInstr The VMX instruction name (for logging purposes).
6128 */
6129IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPUCC pVCpu, const char *pszInstr)
6130{
6131 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6132 const char * const pszFailure = "VMFail";
6133
6134 /* VM-exit controls. */
6135 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6136 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6140
6141 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6142 { /* likely */ }
6143 else
6144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6145
6146 /* Save preemption timer without activating it. */
6147 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6148 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6152
6153 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6154 if (pVmcs->u32ExitMsrStoreCount)
6155 {
6156 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6157 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6158 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6159 { /* likely */ }
6160 else
6161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6162 }
6163
6164 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6165 if (pVmcs->u32ExitMsrLoadCount)
6166 {
6167 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6168 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6169 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6173 }
6174
6175 NOREF(pszInstr);
6176 NOREF(pszFailure);
6177 return VINF_SUCCESS;
6178}
6179
6180
6181/**
6182 * Checks VM-execution controls fields as part of VM-entry.
6183 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6184 *
6185 * @returns VBox status code.
6186 * @param pVCpu The cross context virtual CPU structure.
6187 * @param pszInstr The VMX instruction name (for logging purposes).
6188 *
6189 * @remarks This may update secondary-processor based VM-execution control fields
6190 * in the current VMCS if necessary.
6191 */
6192IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPUCC pVCpu, const char *pszInstr)
6193{
6194 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6195 const char * const pszFailure = "VMFail";
6196
6197 /* Pin-based VM-execution controls. */
6198 {
6199 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6200 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6201 { /* likely */ }
6202 else
6203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6204
6205 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6209 }
6210
6211 /* Processor-based VM-execution controls. */
6212 {
6213 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6214 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6215 { /* likely */ }
6216 else
6217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6218
6219 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6220 { /* likely */ }
6221 else
6222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6223 }
6224
6225 /* Secondary processor-based VM-execution controls. */
6226 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6227 {
6228 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6229 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6233
6234 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6235 { /* likely */ }
6236 else
6237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6238 }
6239 else
6240 Assert(!pVmcs->u32ProcCtls2);
6241
6242 /* CR3-target count. */
6243 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6247
6248 /* I/O bitmaps physical addresses. */
6249 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6250 {
6251 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6252 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6253 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6254 { /* likely */ }
6255 else
6256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6257
6258 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6259 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6260 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6261 { /* likely */ }
6262 else
6263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6264 }
6265
6266 /* MSR bitmap physical address. */
6267 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6268 {
6269 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6270 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6271 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6272 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6273 { /* likely */ }
6274 else
6275 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6276
6277 /* Read the MSR bitmap. */
6278 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6279 * implementing fast path. */
6280 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6281 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6282 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6283 if (RT_SUCCESS(rc))
6284 { /* likely */ }
6285 else
6286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6287 }
6288
6289 /* TPR shadow related controls. */
6290 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6291 {
6292 /* Virtual-APIC page physical address. */
6293 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6294 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6295 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6296 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6297 { /* likely */ }
6298 else
6299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6300
6301 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6302 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6303 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6304 { /* likely */ }
6305 else
6306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6307
6308 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6309 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6310 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6311 {
6312 /* Read the VTPR from the virtual-APIC page. */
6313 uint8_t u8VTpr;
6314 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6315 if (RT_SUCCESS(rc))
6316 { /* likely */ }
6317 else
6318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6319
6320 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6321 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6322 { /* likely */ }
6323 else
6324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6325 }
6326 }
6327 else
6328 {
6329 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6330 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6331 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6332 { /* likely */ }
6333 else
6334 {
6335 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6337 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6339 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6341 }
6342 }
6343
6344 /* NMI exiting and virtual-NMIs. */
6345 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6346 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6347 { /* likely */ }
6348 else
6349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6350
6351 /* Virtual-NMIs and NMI-window exiting. */
6352 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6353 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6354 { /* likely */ }
6355 else
6356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6357
6358 /* Virtualize APIC accesses. */
6359 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6360 {
6361 /* APIC-access physical address. */
6362 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6363 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6364 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6365 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6366 { /* likely */ }
6367 else
6368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6369
6370 /*
6371 * Disallow APIC-access page and virtual-APIC page from being the same address.
6372 * Note! This is not an Intel requirement, but one imposed by our implementation.
6373 */
6374 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6375 * redirecting accesses between the APIC-access page and the virtual-APIC
6376 * page. If any guest hypervisor requires this, we can implement it later. */
6377 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6378 {
6379 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6380 if (GCPhysVirtApic != GCPhysApicAccess)
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6384 }
6385
6386 /*
6387 * Register the handler for the APIC-access page.
6388 *
6389 * We don't deregister the APIC-access page handler during the VM-exit as a different
6390 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6391 *
6392 * We leave the page registered until the first access that happens outside VMX non-root
6393 * mode. Guest software is allowed to access structures such as the APIC-access page
6394 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6395 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6396 *
6397 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6398 */
6399 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6400 {
6401 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6402 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6403 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6404 if (RT_SUCCESS(rc))
6405 { /* likely */ }
6406 else
6407 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6408 }
6409 }
6410
6411 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6412 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6413 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6414 { /* likely */ }
6415 else
6416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6417
6418 /* Virtual-interrupt delivery requires external interrupt exiting. */
6419 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6420 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6421 { /* likely */ }
6422 else
6423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6424
6425 /* VPID. */
6426 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6427 || pVmcs->u16Vpid != 0)
6428 { /* likely */ }
6429 else
6430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6431
6432 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6433 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6434 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6435 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6436 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6437 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6438 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6439
6440 /* VMCS shadowing. */
6441 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6442 {
6443 /* VMREAD-bitmap physical address. */
6444 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6445 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6446 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6447 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6448 { /* likely */ }
6449 else
6450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6451
6452 /* VMWRITE-bitmap physical address. */
6453 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6454 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6455 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6456 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6457 { /* likely */ }
6458 else
6459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6460
6461 /* Read the VMREAD-bitmap. */
6462 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6463 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6464 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6465 if (RT_SUCCESS(rc))
6466 { /* likely */ }
6467 else
6468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6469
6470 /* Read the VMWRITE-bitmap. */
6471 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6472 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6473 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6474 if (RT_SUCCESS(rc))
6475 { /* likely */ }
6476 else
6477 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6478 }
6479
6480 NOREF(pszInstr);
6481 NOREF(pszFailure);
6482 return VINF_SUCCESS;
6483}
6484
6485
6486/**
6487 * Loads the guest control registers, debug register and some MSRs as part of
6488 * VM-entry.
6489 *
6490 * @param pVCpu The cross context virtual CPU structure.
6491 */
6492IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6493{
6494 /*
6495 * Load guest control registers, debug registers and MSRs.
6496 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6497 */
6498 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6499
6500 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6501 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6502 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6503 CPUMSetGuestCR0(pVCpu, uGstCr0);
6504 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6505 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6506
6507 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6508 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6509
6510 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6511 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6512 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6513
6514 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6515 {
6516 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6517
6518 /* EFER MSR. */
6519 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6520 {
6521 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6522 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6523 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6524 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6525 if (fGstInLongMode)
6526 {
6527 /* If the nested-guest is in long mode, LMA and LME are both set. */
6528 Assert(fGstPaging);
6529 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6530 }
6531 else
6532 {
6533 /*
6534 * If the nested-guest is outside long mode:
6535 * - With paging: LMA is cleared, LME is cleared.
6536 * - Without paging: LMA is cleared, LME is left unmodified.
6537 */
6538 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6539 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6540 }
6541 }
6542 /* else: see below. */
6543 }
6544
6545 /* PAT MSR. */
6546 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6547 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6548
6549 /* EFER MSR. */
6550 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6551 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6552
6553 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6554 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6555
6556 /* We don't support IA32_BNDCFGS MSR yet. */
6557 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6558
6559 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6560}
6561
6562
6563/**
6564 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6565 *
6566 * @param pVCpu The cross context virtual CPU structure.
6567 */
6568IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6569{
6570 /*
6571 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6572 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6573 */
6574 /* CS, SS, ES, DS, FS, GS. */
6575 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6576 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6577 {
6578 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6579 CPUMSELREG VmcsSelReg;
6580 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6581 AssertRC(rc); NOREF(rc);
6582 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6583 {
6584 pGstSelReg->Sel = VmcsSelReg.Sel;
6585 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6586 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6587 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6588 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6589 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6590 }
6591 else
6592 {
6593 pGstSelReg->Sel = VmcsSelReg.Sel;
6594 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6595 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6596 switch (iSegReg)
6597 {
6598 case X86_SREG_CS:
6599 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6600 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6601 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6602 break;
6603
6604 case X86_SREG_SS:
6605 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6606 pGstSelReg->u32Limit = 0;
6607 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6608 break;
6609
6610 case X86_SREG_ES:
6611 case X86_SREG_DS:
6612 pGstSelReg->u64Base = 0;
6613 pGstSelReg->u32Limit = 0;
6614 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6615 break;
6616
6617 case X86_SREG_FS:
6618 case X86_SREG_GS:
6619 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6620 pGstSelReg->u32Limit = 0;
6621 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6622 break;
6623 }
6624 Assert(pGstSelReg->Attr.n.u1Unusable);
6625 }
6626 }
6627
6628 /* LDTR. */
6629 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6630 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6631 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6632 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6633 {
6634 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6635 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6636 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6637 }
6638 else
6639 {
6640 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6641 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6642 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6643 }
6644
6645 /* TR. */
6646 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6647 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6648 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6649 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6650 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6651 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6652 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6653
6654 /* GDTR. */
6655 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6656 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6657
6658 /* IDTR. */
6659 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6660 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6661}
6662
6663
6664/**
6665 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6666 *
6667 * @returns VBox status code.
6668 * @param pVCpu The cross context virtual CPU structure.
6669 * @param pszInstr The VMX instruction name (for logging purposes).
6670 */
6671IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6672{
6673 /*
6674 * Load guest MSRs.
6675 * See Intel spec. 26.4 "Loading MSRs".
6676 */
6677 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6678 const char *const pszFailure = "VM-exit";
6679
6680 /*
6681 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6682 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6683 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6684 */
6685 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6686 if (!cMsrs)
6687 return VINF_SUCCESS;
6688
6689 /*
6690 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6691 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6692 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6693 */
6694 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6695 if (fIsMsrCountValid)
6696 { /* likely */ }
6697 else
6698 {
6699 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6701 }
6702
6703 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6704 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6705 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6706 if (RT_SUCCESS(rc))
6707 {
6708 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6709 Assert(pMsr);
6710 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6711 {
6712 if ( !pMsr->u32Reserved
6713 && pMsr->u32Msr != MSR_K8_FS_BASE
6714 && pMsr->u32Msr != MSR_K8_GS_BASE
6715 && pMsr->u32Msr != MSR_K6_EFER
6716 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6717 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6718 {
6719 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6720 if (rcStrict == VINF_SUCCESS)
6721 continue;
6722
6723 /*
6724 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6725 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6726 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6727 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6728 * MSR in ring-0 if possible, or come up with a better, generic solution.
6729 */
6730 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6731 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6732 ? kVmxVDiag_Vmentry_MsrLoadRing3
6733 : kVmxVDiag_Vmentry_MsrLoad;
6734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6735 }
6736 else
6737 {
6738 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6740 }
6741 }
6742 }
6743 else
6744 {
6745 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6747 }
6748
6749 NOREF(pszInstr);
6750 NOREF(pszFailure);
6751 return VINF_SUCCESS;
6752}
6753
6754
6755/**
6756 * Loads the guest-state non-register state as part of VM-entry.
6757 *
6758 * @returns VBox status code.
6759 * @param pVCpu The cross context virtual CPU structure.
6760 *
6761 * @remarks This must be called only after loading the nested-guest register state
6762 * (especially nested-guest RIP).
6763 */
6764IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6765{
6766 /*
6767 * Load guest non-register state.
6768 * See Intel spec. 26.6 "Special Features of VM Entry"
6769 */
6770 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6771
6772 /*
6773 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6774 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6775 *
6776 * See Intel spec. 26.6.1 "Interruptibility State".
6777 */
6778 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6779 if ( !fEntryVectoring
6780 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6781 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6782 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6783 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6784
6785 /* NMI blocking. */
6786 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6787 {
6788 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6789 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6790 else
6791 {
6792 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6793 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6794 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6795 }
6796 }
6797 else
6798 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6799
6800 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6801
6802 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6803 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6804
6805 /* VPID is irrelevant. We don't support VPID yet. */
6806
6807 /* Clear address-range monitoring. */
6808 EMMonitorWaitClear(pVCpu);
6809}
6810
6811
6812/**
6813 * Loads the guest-state as part of VM-entry.
6814 *
6815 * @returns VBox status code.
6816 * @param pVCpu The cross context virtual CPU structure.
6817 * @param pszInstr The VMX instruction name (for logging purposes).
6818 *
6819 * @remarks This must be done after all the necessary steps prior to loading of
6820 * guest-state (e.g. checking various VMCS state).
6821 */
6822IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6823{
6824 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6825 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6826
6827 /*
6828 * Load guest RIP, RSP and RFLAGS.
6829 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6830 */
6831 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6832 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6833 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6834 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6835
6836 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6837 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6838 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6839
6840 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6841
6842 NOREF(pszInstr);
6843 return VINF_SUCCESS;
6844}
6845
6846
6847/**
6848 * Returns whether there are is a pending debug exception on VM-entry.
6849 *
6850 * @param pVCpu The cross context virtual CPU structure.
6851 * @param pszInstr The VMX instruction name (for logging purposes).
6852 */
6853IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6854{
6855 /*
6856 * Pending debug exceptions.
6857 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6858 */
6859 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6860 Assert(pVmcs);
6861
6862 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6863 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6864 if (fPendingDbgXcpt)
6865 {
6866 uint8_t uEntryIntInfoType;
6867 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6868 if (fEntryVectoring)
6869 {
6870 switch (uEntryIntInfoType)
6871 {
6872 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6873 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6874 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6875 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6876 fPendingDbgXcpt = false;
6877 break;
6878
6879 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6880 {
6881 /*
6882 * Whether the pending debug exception for software exceptions other than
6883 * #BP and #OF is delivered after injecting the exception or is discard
6884 * is CPU implementation specific. We will discard them (easier).
6885 */
6886 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6887 if ( uVector != X86_XCPT_BP
6888 && uVector != X86_XCPT_OF)
6889 fPendingDbgXcpt = false;
6890 RT_FALL_THRU();
6891 }
6892 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6893 {
6894 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6895 fPendingDbgXcpt = false;
6896 break;
6897 }
6898 }
6899 }
6900 else
6901 {
6902 /*
6903 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6904 * pending debug exception is held pending or is discarded is CPU implementation
6905 * specific. We will discard them (easier).
6906 */
6907 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6908 fPendingDbgXcpt = false;
6909
6910 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6911 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6912 fPendingDbgXcpt = false;
6913 }
6914 }
6915
6916 NOREF(pszInstr);
6917 return fPendingDbgXcpt;
6918}
6919
6920
6921/**
6922 * Set up the monitor-trap flag (MTF).
6923 *
6924 * @param pVCpu The cross context virtual CPU structure.
6925 * @param pszInstr The VMX instruction name (for logging purposes).
6926 */
6927IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6928{
6929 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6930 Assert(pVmcs);
6931 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6932 {
6933 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6934 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6935 }
6936 else
6937 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6938 NOREF(pszInstr);
6939}
6940
6941
6942/**
6943 * Sets up NMI-window exiting.
6944 *
6945 * @param pVCpu The cross context virtual CPU structure.
6946 * @param pszInstr The VMX instruction name (for logging purposes).
6947 */
6948IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6949{
6950 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6951 Assert(pVmcs);
6952 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6953 {
6954 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6955 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6956 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6957 }
6958 else
6959 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6960 NOREF(pszInstr);
6961}
6962
6963
6964/**
6965 * Sets up interrupt-window exiting.
6966 *
6967 * @param pVCpu The cross context virtual CPU structure.
6968 * @param pszInstr The VMX instruction name (for logging purposes).
6969 */
6970IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6971{
6972 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6973 Assert(pVmcs);
6974 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6975 {
6976 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6977 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6978 }
6979 else
6980 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6981 NOREF(pszInstr);
6982}
6983
6984
6985/**
6986 * Set up the VMX-preemption timer.
6987 *
6988 * @param pVCpu The cross context virtual CPU structure.
6989 * @param pszInstr The VMX instruction name (for logging purposes).
6990 */
6991IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6992{
6993 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6994 Assert(pVmcs);
6995 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6996 {
6997 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
6998 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
6999 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7000
7001 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7002 }
7003 else
7004 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7005
7006 NOREF(pszInstr);
7007}
7008
7009
7010/**
7011 * Injects an event using TRPM given a VM-entry interruption info. and related
7012 * fields.
7013 *
7014 * @param pVCpu The cross context virtual CPU structure.
7015 * @param pszInstr The VMX instruction name (for logging purposes).
7016 * @param uEntryIntInfo The VM-entry interruption info.
7017 * @param uErrCode The error code associated with the event if any.
7018 * @param cbInstr The VM-entry instruction length (for software
7019 * interrupts and software exceptions). Pass 0
7020 * otherwise.
7021 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7022 */
7023IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7024 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7025{
7026 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7027
7028 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7029 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7030 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7031
7032 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7033
7034 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7035 AssertRC(rc);
7036 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7037
7038 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7039 {
7040 TRPMSetErrorCode(pVCpu, uErrCode);
7041 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7042 }
7043
7044 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7045 {
7046 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7047 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7048 }
7049 else
7050 {
7051 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7052 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7053 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7054 {
7055 TRPMSetInstrLength(pVCpu, cbInstr);
7056 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7057 }
7058 }
7059
7060 NOREF(pszInstr);
7061}
7062
7063
7064/**
7065 * Performs event injection (if any) as part of VM-entry.
7066 *
7067 * @param pVCpu The cross context virtual CPU structure.
7068 * @param pszInstr The VMX instruction name (for logging purposes).
7069 */
7070IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7071{
7072 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7073
7074 /*
7075 * Inject events.
7076 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7077 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7078 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7079 * the actually delivery of this event.
7080 *
7081 * See Intel spec. 26.5 "Event Injection".
7082 */
7083 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7084 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7085
7086 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7087 if (fEntryIntInfoValid)
7088 {
7089 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7090 {
7091 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7092 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7093 }
7094 else
7095 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7096 pVCpu->cpum.GstCtx.cr2);
7097
7098 /*
7099 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7100 *
7101 * However, we do it here on VM-entry as well because while it isn't visible to guest
7102 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7103 * execution using hardware-assisted VT-x, it will not be try to inject the event again.
7104 *
7105 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7106 */
7107 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7108 }
7109 else
7110 {
7111 /*
7112 * Inject any pending guest debug exception.
7113 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7114 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7115 */
7116 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7117 if (fPendingDbgXcpt)
7118 {
7119 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7120 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7121 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7122 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7123 0 /* GCPtrFaultAddress */);
7124 }
7125 }
7126
7127 NOREF(pszInstr);
7128}
7129
7130
7131/**
7132 * Initializes all read-only VMCS fields as part of VM-entry.
7133 *
7134 * @param pVCpu The cross context virtual CPU structure.
7135 */
7136IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7137{
7138 /*
7139 * Any VMCS field which we do not establish on every VM-exit but may potentially
7140 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7141 * specified to be undefined needs to be initialized here.
7142 *
7143 * Thus, it is especially important to clear the Exit qualification field
7144 * since it must be zero for VM-exits where it is not used. Similarly, the
7145 * VM-exit interruption information field's valid bit needs to be cleared for
7146 * the same reasons.
7147 */
7148 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7149 Assert(pVmcs);
7150
7151 /* 16-bit (none currently). */
7152 /* 32-bit. */
7153 pVmcs->u32RoVmInstrError = 0;
7154 pVmcs->u32RoExitReason = 0;
7155 pVmcs->u32RoExitIntInfo = 0;
7156 pVmcs->u32RoExitIntErrCode = 0;
7157 pVmcs->u32RoIdtVectoringInfo = 0;
7158 pVmcs->u32RoIdtVectoringErrCode = 0;
7159 pVmcs->u32RoExitInstrLen = 0;
7160 pVmcs->u32RoExitInstrInfo = 0;
7161
7162 /* 64-bit. */
7163 pVmcs->u64RoGuestPhysAddr.u = 0;
7164
7165 /* Natural-width. */
7166 pVmcs->u64RoExitQual.u = 0;
7167 pVmcs->u64RoIoRcx.u = 0;
7168 pVmcs->u64RoIoRsi.u = 0;
7169 pVmcs->u64RoIoRdi.u = 0;
7170 pVmcs->u64RoIoRip.u = 0;
7171 pVmcs->u64RoGuestLinearAddr.u = 0;
7172}
7173
7174
7175/**
7176 * VMLAUNCH/VMRESUME instruction execution worker.
7177 *
7178 * @returns Strict VBox status code.
7179 * @param pVCpu The cross context virtual CPU structure.
7180 * @param cbInstr The instruction length in bytes.
7181 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7182 * VMXINSTRID_VMRESUME).
7183 *
7184 * @remarks Common VMX instruction checks are already expected to by the caller,
7185 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7186 */
7187IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7188{
7189# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7190 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7191 return VINF_EM_RAW_EMULATE_INSTR;
7192# else
7193 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7194 || uInstrId == VMXINSTRID_VMRESUME);
7195 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7196
7197 /* Nested-guest intercept. */
7198 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7199 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7200
7201 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7202
7203 /*
7204 * Basic VM-entry checks.
7205 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7206 * The checks following that do not have to follow a specific order.
7207 *
7208 * See Intel spec. 26.1 "Basic VM-entry Checks".
7209 */
7210
7211 /* CPL. */
7212 if (pVCpu->iem.s.uCpl == 0)
7213 { /* likely */ }
7214 else
7215 {
7216 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7217 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7218 return iemRaiseGeneralProtectionFault0(pVCpu);
7219 }
7220
7221 /* Current VMCS valid. */
7222 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7223 { /* likely */ }
7224 else
7225 {
7226 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7227 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7228 iemVmxVmFailInvalid(pVCpu);
7229 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7230 return VINF_SUCCESS;
7231 }
7232
7233 /* Current VMCS is not a shadow VMCS. */
7234 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7235 { /* likely */ }
7236 else
7237 {
7238 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7239 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7240 iemVmxVmFailInvalid(pVCpu);
7241 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7242 return VINF_SUCCESS;
7243 }
7244
7245 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7246 * use block-by-STI here which is not quite correct. */
7247 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7248 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7249 { /* likely */ }
7250 else
7251 {
7252 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7253 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7254 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7255 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7256 return VINF_SUCCESS;
7257 }
7258
7259 if (uInstrId == VMXINSTRID_VMLAUNCH)
7260 {
7261 /* VMLAUNCH with non-clear VMCS. */
7262 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7263 { /* likely */ }
7264 else
7265 {
7266 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7267 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7268 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7269 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7270 return VINF_SUCCESS;
7271 }
7272 }
7273 else
7274 {
7275 /* VMRESUME with non-launched VMCS. */
7276 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7277 { /* likely */ }
7278 else
7279 {
7280 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7281 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7282 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7283 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7284 return VINF_SUCCESS;
7285 }
7286 }
7287
7288 /*
7289 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7290 * while entering VMX non-root mode. We do some of this while checking VM-execution
7291 * controls. The guest hypervisor should not make assumptions and cannot expect
7292 * predictable behavior if changes to these structures are made in guest memory while
7293 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7294 * modify them anyway as we cache them in host memory.
7295 *
7296 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7297 */
7298 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7299 Assert(pVmcs);
7300 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7301
7302 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7303 if (RT_SUCCESS(rc))
7304 {
7305 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7306 if (RT_SUCCESS(rc))
7307 {
7308 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7309 if (RT_SUCCESS(rc))
7310 {
7311 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7312 if (RT_SUCCESS(rc))
7313 {
7314 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7315 iemVmxVmentryInitReadOnlyFields(pVCpu);
7316
7317 /*
7318 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7319 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7320 * VM-exit when required.
7321 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7322 */
7323 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7324
7325 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7326 if (RT_SUCCESS(rc))
7327 {
7328 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7329 if (RT_SUCCESS(rc))
7330 {
7331 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7332 if (RT_SUCCESS(rc))
7333 {
7334 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7335
7336 /* VMLAUNCH instruction must update the VMCS launch state. */
7337 if (uInstrId == VMXINSTRID_VMLAUNCH)
7338 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7339
7340 /* Perform the VMX transition (PGM updates). */
7341 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7342 if (rcStrict == VINF_SUCCESS)
7343 { /* likely */ }
7344 else if (RT_SUCCESS(rcStrict))
7345 {
7346 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7347 VBOXSTRICTRC_VAL(rcStrict)));
7348 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7349 }
7350 else
7351 {
7352 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7353 return rcStrict;
7354 }
7355
7356 /* Paranoia. */
7357 Assert(rcStrict == VINF_SUCCESS);
7358
7359 /* We've now entered nested-guest execution. */
7360 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7361
7362 /*
7363 * The priority of potential VM-exits during VM-entry is important.
7364 * The priorities of VM-exits and events are listed from highest
7365 * to lowest as follows:
7366 *
7367 * 1. Event injection.
7368 * 2. Trap on task-switch (T flag set in TSS).
7369 * 3. TPR below threshold / APIC-write.
7370 * 4. SMI, INIT.
7371 * 5. MTF exit.
7372 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7373 * 7. VMX-preemption timer.
7374 * 9. NMI-window exit.
7375 * 10. NMI injection.
7376 * 11. Interrupt-window exit.
7377 * 12. Virtual-interrupt injection.
7378 * 13. Interrupt injection.
7379 * 14. Process next instruction (fetch, decode, execute).
7380 */
7381
7382 /* Setup VMX-preemption timer. */
7383 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7384
7385 /* Setup monitor-trap flag. */
7386 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7387
7388 /* Setup NMI-window exiting. */
7389 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7390
7391 /* Setup interrupt-window exiting. */
7392 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7393
7394 /*
7395 * Inject any event that the guest hypervisor wants to inject.
7396 * Note! We cannot immediately perform the event injection here as we may have
7397 * pending PGM operations to perform due to switching page tables and/or
7398 * mode.
7399 */
7400 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7401
7402# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7403 /* Reschedule to IEM-only execution of the nested-guest. */
7404 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7405 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7406 if (rcSched != VINF_SUCCESS)
7407 iemSetPassUpStatus(pVCpu, rcSched);
7408# endif
7409
7410 /* Finally, done. */
7411 Log(("%s: cs:rip=%#04x:%#RX64 cr3=%#RX64\n", pszInstr, pVCpu->cpum.GstCtx.cs.Sel,
7412 pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr3));
7413 return VINF_SUCCESS;
7414 }
7415 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7416 pVmcs->u64RoExitQual.u);
7417 }
7418 }
7419 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7420 pVmcs->u64RoExitQual.u);
7421 }
7422
7423 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7424 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7425 return VINF_SUCCESS;
7426 }
7427 }
7428 }
7429
7430 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7431 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7432 return VINF_SUCCESS;
7433# endif
7434}
7435
7436
7437/**
7438 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7439 * (causes a VM-exit) or not.
7440 *
7441 * @returns @c true if the instruction is intercepted, @c false otherwise.
7442 * @param pVCpu The cross context virtual CPU structure.
7443 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7444 * VMX_EXIT_WRMSR).
7445 * @param idMsr The MSR.
7446 */
7447IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7448{
7449 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7450 Assert( uExitReason == VMX_EXIT_RDMSR
7451 || uExitReason == VMX_EXIT_WRMSR);
7452
7453 /* Consult the MSR bitmap if the feature is supported. */
7454 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7455 Assert(pVmcs);
7456 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7457 {
7458 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7459 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7460 if (uExitReason == VMX_EXIT_RDMSR)
7461 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7462 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7463 }
7464
7465 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7466 return true;
7467}
7468
7469
7470/**
7471 * VMREAD instruction execution worker that does not perform any validation checks.
7472 *
7473 * Callers are expected to have performed the necessary checks and to ensure the
7474 * VMREAD will succeed.
7475 *
7476 * @param pVmcs Pointer to the virtual VMCS.
7477 * @param pu64Dst Where to write the VMCS value.
7478 * @param u64VmcsField The VMCS field.
7479 *
7480 * @remarks May be called with interrupts disabled.
7481 */
7482IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7483{
7484 VMXVMCSFIELD VmcsField;
7485 VmcsField.u = u64VmcsField;
7486 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7487 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7488 uint8_t const uWidthType = (uWidth << 2) | uType;
7489 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7490 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7491 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7492 Assert(offField < VMX_V_VMCS_SIZE);
7493 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7494
7495 /*
7496 * Read the VMCS component based on the field's effective width.
7497 *
7498 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7499 * indicates high bits (little endian).
7500 *
7501 * Note! The caller is responsible to trim the result and update registers
7502 * or memory locations are required. Here we just zero-extend to the largest
7503 * type (i.e. 64-bits).
7504 */
7505 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7506 uint8_t const *pbField = pbVmcs + offField;
7507 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7508 switch (uEffWidth)
7509 {
7510 case VMX_VMCSFIELD_WIDTH_64BIT:
7511 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7512 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7513 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7514 }
7515}
7516
7517
7518/**
7519 * VMREAD common (memory/register) instruction execution worker.
7520 *
7521 * @returns Strict VBox status code.
7522 * @param pVCpu The cross context virtual CPU structure.
7523 * @param cbInstr The instruction length in bytes.
7524 * @param pu64Dst Where to write the VMCS value (only updated when
7525 * VINF_SUCCESS is returned).
7526 * @param u64VmcsField The VMCS field.
7527 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7528 * NULL.
7529 */
7530IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7531 PCVMXVEXITINFO pExitInfo)
7532{
7533 /* Nested-guest intercept. */
7534 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7535 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7536 {
7537 if (pExitInfo)
7538 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7539 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7540 }
7541
7542 /* CPL. */
7543 if (pVCpu->iem.s.uCpl == 0)
7544 { /* likely */ }
7545 else
7546 {
7547 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7548 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7549 return iemRaiseGeneralProtectionFault0(pVCpu);
7550 }
7551
7552 /* VMCS pointer in root mode. */
7553 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7554 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7555 { /* likely */ }
7556 else
7557 {
7558 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7559 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7560 iemVmxVmFailInvalid(pVCpu);
7561 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7562 return VINF_SUCCESS;
7563 }
7564
7565 /* VMCS-link pointer in non-root mode. */
7566 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7567 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7568 { /* likely */ }
7569 else
7570 {
7571 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7572 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7573 iemVmxVmFailInvalid(pVCpu);
7574 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7575 return VINF_SUCCESS;
7576 }
7577
7578 /* Supported VMCS field. */
7579 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7580 { /* likely */ }
7581 else
7582 {
7583 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7584 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7585 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7586 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7587 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7588 return VINF_SUCCESS;
7589 }
7590
7591 /*
7592 * Reading from the current or shadow VMCS.
7593 */
7594 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7595 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7596 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7597 Assert(pVmcs);
7598 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7599 return VINF_SUCCESS;
7600}
7601
7602
7603/**
7604 * VMREAD (64-bit register) instruction execution worker.
7605 *
7606 * @returns Strict VBox status code.
7607 * @param pVCpu The cross context virtual CPU structure.
7608 * @param cbInstr The instruction length in bytes.
7609 * @param pu64Dst Where to store the VMCS field's value.
7610 * @param u64VmcsField The VMCS field.
7611 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7612 * NULL.
7613 */
7614IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7615 PCVMXVEXITINFO pExitInfo)
7616{
7617 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7618 if (rcStrict == VINF_SUCCESS)
7619 {
7620 iemVmxVmreadSuccess(pVCpu, cbInstr);
7621 return VINF_SUCCESS;
7622 }
7623
7624 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7625 return rcStrict;
7626}
7627
7628
7629/**
7630 * VMREAD (32-bit register) instruction execution worker.
7631 *
7632 * @returns Strict VBox status code.
7633 * @param pVCpu The cross context virtual CPU structure.
7634 * @param cbInstr The instruction length in bytes.
7635 * @param pu32Dst Where to store the VMCS field's value.
7636 * @param u32VmcsField The VMCS field.
7637 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7638 * NULL.
7639 */
7640IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7641 PCVMXVEXITINFO pExitInfo)
7642{
7643 uint64_t u64Dst;
7644 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7645 if (rcStrict == VINF_SUCCESS)
7646 {
7647 *pu32Dst = u64Dst;
7648 iemVmxVmreadSuccess(pVCpu, cbInstr);
7649 return VINF_SUCCESS;
7650 }
7651
7652 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7653 return rcStrict;
7654}
7655
7656
7657/**
7658 * VMREAD (memory) instruction execution worker.
7659 *
7660 * @returns Strict VBox status code.
7661 * @param pVCpu The cross context virtual CPU structure.
7662 * @param cbInstr The instruction length in bytes.
7663 * @param iEffSeg The effective segment register to use with @a u64Val.
7664 * Pass UINT8_MAX if it is a register access.
7665 * @param GCPtrDst The guest linear address to store the VMCS field's
7666 * value.
7667 * @param u64VmcsField The VMCS field.
7668 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7669 * NULL.
7670 */
7671IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7672 PCVMXVEXITINFO pExitInfo)
7673{
7674 uint64_t u64Dst;
7675 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7676 if (rcStrict == VINF_SUCCESS)
7677 {
7678 /*
7679 * Write the VMCS field's value to the location specified in guest-memory.
7680 */
7681 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7682 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7683 else
7684 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7685 if (rcStrict == VINF_SUCCESS)
7686 {
7687 iemVmxVmreadSuccess(pVCpu, cbInstr);
7688 return VINF_SUCCESS;
7689 }
7690
7691 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7693 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7694 return rcStrict;
7695 }
7696
7697 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7698 return rcStrict;
7699}
7700
7701
7702/**
7703 * VMWRITE instruction execution worker that does not perform any validation
7704 * checks.
7705 *
7706 * Callers are expected to have performed the necessary checks and to ensure the
7707 * VMWRITE will succeed.
7708 *
7709 * @param pVmcs Pointer to the virtual VMCS.
7710 * @param u64Val The value to write.
7711 * @param u64VmcsField The VMCS field.
7712 *
7713 * @remarks May be called with interrupts disabled.
7714 */
7715IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7716{
7717 VMXVMCSFIELD VmcsField;
7718 VmcsField.u = u64VmcsField;
7719 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7720 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7721 uint8_t const uWidthType = (uWidth << 2) | uType;
7722 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7723 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7724 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7725 Assert(offField < VMX_V_VMCS_SIZE);
7726 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7727
7728 /*
7729 * Write the VMCS component based on the field's effective width.
7730 *
7731 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7732 * indicates high bits (little endian).
7733 */
7734 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7735 uint8_t *pbField = pbVmcs + offField;
7736 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7737 switch (uEffWidth)
7738 {
7739 case VMX_VMCSFIELD_WIDTH_64BIT:
7740 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7741 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7742 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7743 }
7744}
7745
7746
7747/**
7748 * VMWRITE instruction execution worker.
7749 *
7750 * @returns Strict VBox status code.
7751 * @param pVCpu The cross context virtual CPU structure.
7752 * @param cbInstr The instruction length in bytes.
7753 * @param iEffSeg The effective segment register to use with @a u64Val.
7754 * Pass UINT8_MAX if it is a register access.
7755 * @param u64Val The value to write (or guest linear address to the
7756 * value), @a iEffSeg will indicate if it's a memory
7757 * operand.
7758 * @param u64VmcsField The VMCS field.
7759 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7760 * NULL.
7761 */
7762IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7763 PCVMXVEXITINFO pExitInfo)
7764{
7765 /* Nested-guest intercept. */
7766 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7767 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7768 {
7769 if (pExitInfo)
7770 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7771 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7772 }
7773
7774 /* CPL. */
7775 if (pVCpu->iem.s.uCpl == 0)
7776 { /* likely */ }
7777 else
7778 {
7779 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7780 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7781 return iemRaiseGeneralProtectionFault0(pVCpu);
7782 }
7783
7784 /* VMCS pointer in root mode. */
7785 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7786 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7787 { /* likely */ }
7788 else
7789 {
7790 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7791 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7792 iemVmxVmFailInvalid(pVCpu);
7793 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7794 return VINF_SUCCESS;
7795 }
7796
7797 /* VMCS-link pointer in non-root mode. */
7798 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7799 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7800 { /* likely */ }
7801 else
7802 {
7803 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7805 iemVmxVmFailInvalid(pVCpu);
7806 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7807 return VINF_SUCCESS;
7808 }
7809
7810 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7811 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7812 if (!fIsRegOperand)
7813 {
7814 /* Read the value from the specified guest memory location. */
7815 VBOXSTRICTRC rcStrict;
7816 RTGCPTR const GCPtrVal = u64Val;
7817 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7818 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7819 else
7820 {
7821 uint32_t u32Val;
7822 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7823 u64Val = u32Val;
7824 }
7825 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7826 {
7827 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7828 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7829 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7830 return rcStrict;
7831 }
7832 }
7833 else
7834 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7835
7836 /* Supported VMCS field. */
7837 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7838 { /* likely */ }
7839 else
7840 {
7841 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7842 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7843 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7844 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7845 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7846 return VINF_SUCCESS;
7847 }
7848
7849 /* Read-only VMCS field. */
7850 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7851 if ( !fIsFieldReadOnly
7852 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7853 { /* likely */ }
7854 else
7855 {
7856 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7857 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7858 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7859 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7860 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7861 return VINF_SUCCESS;
7862 }
7863
7864 /*
7865 * Write to the current or shadow VMCS.
7866 */
7867 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7868 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7869 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7870 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7871 Assert(pVmcs);
7872 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7873
7874 /* Notify HM that the VMCS content might have changed. */
7875 if (!fInVmxNonRootMode)
7876 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7877
7878 iemVmxVmSucceed(pVCpu);
7879 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7880 return VINF_SUCCESS;
7881}
7882
7883
7884/**
7885 * VMCLEAR instruction execution worker.
7886 *
7887 * @returns Strict VBox status code.
7888 * @param pVCpu The cross context virtual CPU structure.
7889 * @param cbInstr The instruction length in bytes.
7890 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7891 * @param GCPtrVmcs The linear address of the VMCS pointer.
7892 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7893 *
7894 * @remarks Common VMX instruction checks are already expected to by the caller,
7895 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7896 */
7897IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7898 PCVMXVEXITINFO pExitInfo)
7899{
7900 /* Nested-guest intercept. */
7901 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7902 {
7903 if (pExitInfo)
7904 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7905 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7906 }
7907
7908 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7909
7910 /* CPL. */
7911 if (pVCpu->iem.s.uCpl == 0)
7912 { /* likely */ }
7913 else
7914 {
7915 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7916 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7917 return iemRaiseGeneralProtectionFault0(pVCpu);
7918 }
7919
7920 /* Get the VMCS pointer from the location specified by the source memory operand. */
7921 RTGCPHYS GCPhysVmcs;
7922 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7923 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7924 { /* likely */ }
7925 else
7926 {
7927 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7928 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7929 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7930 return rcStrict;
7931 }
7932
7933 /* VMCS pointer alignment. */
7934 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7935 { /* likely */ }
7936 else
7937 {
7938 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7939 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7940 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7941 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7942 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7943 return VINF_SUCCESS;
7944 }
7945
7946 /* VMCS physical-address width limits. */
7947 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7948 { /* likely */ }
7949 else
7950 {
7951 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7952 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7953 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7954 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7955 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7956 return VINF_SUCCESS;
7957 }
7958
7959 /* VMCS is not the VMXON region. */
7960 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7961 { /* likely */ }
7962 else
7963 {
7964 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7965 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7966 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7967 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7968 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7969 return VINF_SUCCESS;
7970 }
7971
7972 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7973 restriction imposed by our implementation. */
7974 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7975 { /* likely */ }
7976 else
7977 {
7978 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7979 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7980 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7981 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7982 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7983 return VINF_SUCCESS;
7984 }
7985
7986 /*
7987 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7988 *
7989 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7990 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7991 * to 'clear'.
7992 */
7993 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7994 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7995 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7996 {
7997 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
7998 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
7999 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8000 }
8001 else
8002 {
8003 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8004 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8005 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8006 if (RT_FAILURE(rcStrict))
8007 return rcStrict;
8008 }
8009
8010 iemVmxVmSucceed(pVCpu);
8011 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8012 return VINF_SUCCESS;
8013}
8014
8015
8016/**
8017 * VMPTRST instruction execution worker.
8018 *
8019 * @returns Strict VBox status code.
8020 * @param pVCpu The cross context virtual CPU structure.
8021 * @param cbInstr The instruction length in bytes.
8022 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8023 * @param GCPtrVmcs The linear address of where to store the current VMCS
8024 * pointer.
8025 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8026 *
8027 * @remarks Common VMX instruction checks are already expected to by the caller,
8028 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8029 */
8030IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8031 PCVMXVEXITINFO pExitInfo)
8032{
8033 /* Nested-guest intercept. */
8034 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8035 {
8036 if (pExitInfo)
8037 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8038 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8039 }
8040
8041 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8042
8043 /* CPL. */
8044 if (pVCpu->iem.s.uCpl == 0)
8045 { /* likely */ }
8046 else
8047 {
8048 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8049 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8050 return iemRaiseGeneralProtectionFault0(pVCpu);
8051 }
8052
8053 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8054 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8055 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8056 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8057 {
8058 iemVmxVmSucceed(pVCpu);
8059 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8060 return rcStrict;
8061 }
8062
8063 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8064 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8065 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8066 return rcStrict;
8067}
8068
8069
8070/**
8071 * VMPTRLD instruction execution worker.
8072 *
8073 * @returns Strict VBox status code.
8074 * @param pVCpu The cross context virtual CPU structure.
8075 * @param cbInstr The instruction length in bytes.
8076 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8077 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8078 *
8079 * @remarks Common VMX instruction checks are already expected to by the caller,
8080 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8081 */
8082IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8083 PCVMXVEXITINFO pExitInfo)
8084{
8085 /* Nested-guest intercept. */
8086 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8087 {
8088 if (pExitInfo)
8089 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8090 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8091 }
8092
8093 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8094
8095 /* CPL. */
8096 if (pVCpu->iem.s.uCpl == 0)
8097 { /* likely */ }
8098 else
8099 {
8100 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8102 return iemRaiseGeneralProtectionFault0(pVCpu);
8103 }
8104
8105 /* Get the VMCS pointer from the location specified by the source memory operand. */
8106 RTGCPHYS GCPhysVmcs;
8107 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8108 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8109 { /* likely */ }
8110 else
8111 {
8112 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8113 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8114 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8115 return rcStrict;
8116 }
8117
8118 /* VMCS pointer alignment. */
8119 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8120 { /* likely */ }
8121 else
8122 {
8123 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8124 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8125 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8126 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8128 return VINF_SUCCESS;
8129 }
8130
8131 /* VMCS physical-address width limits. */
8132 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8133 { /* likely */ }
8134 else
8135 {
8136 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8137 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8138 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8139 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8140 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8141 return VINF_SUCCESS;
8142 }
8143
8144 /* VMCS is not the VMXON region. */
8145 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8146 { /* likely */ }
8147 else
8148 {
8149 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8151 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8152 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8153 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8154 return VINF_SUCCESS;
8155 }
8156
8157 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8158 restriction imposed by our implementation. */
8159 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8160 { /* likely */ }
8161 else
8162 {
8163 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8164 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8165 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8166 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8167 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8168 return VINF_SUCCESS;
8169 }
8170
8171 /* Read just the VMCS revision from the VMCS. */
8172 VMXVMCSREVID VmcsRevId;
8173 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8174 if (RT_SUCCESS(rc))
8175 { /* likely */ }
8176 else
8177 {
8178 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8179 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8180 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8181 return rc;
8182 }
8183
8184 /*
8185 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8186 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8187 */
8188 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8189 && ( !VmcsRevId.n.fIsShadowVmcs
8190 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8191 { /* likely */ }
8192 else
8193 {
8194 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8195 {
8196 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8197 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8198 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8199 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8200 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8201 return VINF_SUCCESS;
8202 }
8203
8204 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8205 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8206 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8207 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8208 return VINF_SUCCESS;
8209 }
8210
8211 /*
8212 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8213 * the cache of an existing, current VMCS back to guest memory before loading a new,
8214 * different current VMCS.
8215 */
8216 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8217 {
8218 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8219 {
8220 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8221 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8222 }
8223
8224 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8225 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8226 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8227 if (RT_SUCCESS(rc))
8228 {
8229 /* Notify HM that a new, current VMCS is loaded. */
8230 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8231 }
8232 else
8233 {
8234 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8235 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8236 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8237 return rc;
8238 }
8239 }
8240
8241 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8242 iemVmxVmSucceed(pVCpu);
8243 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8244 return VINF_SUCCESS;
8245}
8246
8247
8248/**
8249 * INVVPID instruction execution worker.
8250 *
8251 * @returns Strict VBox status code.
8252 * @param pVCpu The cross context virtual CPU structure.
8253 * @param cbInstr The instruction length in bytes.
8254 * @param iEffSeg The segment of the invvpid descriptor.
8255 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8256 * @param u64InvvpidType The invalidation type.
8257 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8258 * NULL.
8259 *
8260 * @remarks Common VMX instruction checks are already expected to by the caller,
8261 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8262 */
8263IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8264 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8265{
8266 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8267 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8268 return iemRaiseUndefinedOpcode(pVCpu);
8269
8270 /* Nested-guest intercept. */
8271 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8272 {
8273 if (pExitInfo)
8274 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8275 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8276 }
8277
8278 /* CPL. */
8279 if (pVCpu->iem.s.uCpl != 0)
8280 {
8281 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8282 return iemRaiseGeneralProtectionFault0(pVCpu);
8283 }
8284
8285 /*
8286 * Validate INVVPID invalidation type.
8287 *
8288 * The instruction specifies exactly ONE of the supported invalidation types.
8289 *
8290 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8291 * supported. In theory, it's possible for a CPU to not support flushing individual
8292 * addresses but all the other types or any other combination. We do not take any
8293 * shortcuts here by assuming the types we currently expose to the guest.
8294 */
8295 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8296 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8297 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8298 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8299 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8300 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8301 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8302 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8303 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8304 { /* likely */ }
8305 else
8306 {
8307 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8309 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8310 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8311 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8312 return VINF_SUCCESS;
8313 }
8314
8315 /*
8316 * Fetch the invvpid descriptor from guest memory.
8317 */
8318 RTUINT128U uDesc;
8319 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8320 if (rcStrict == VINF_SUCCESS)
8321 {
8322 /*
8323 * Validate the descriptor.
8324 */
8325 if (uDesc.s.Lo > 0xfff)
8326 {
8327 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8329 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8330 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8331 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8332 return VINF_SUCCESS;
8333 }
8334
8335 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8336 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8337 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8338 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8339 switch (u64InvvpidType)
8340 {
8341 case VMXTLBFLUSHVPID_INDIV_ADDR:
8342 {
8343 if (uVpid != 0)
8344 {
8345 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8346 {
8347 /* Invalidate mappings for the linear address tagged with VPID. */
8348 /** @todo PGM support for VPID? Currently just flush everything. */
8349 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8350 iemVmxVmSucceed(pVCpu);
8351 }
8352 else
8353 {
8354 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8355 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8356 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8357 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8358 }
8359 }
8360 else
8361 {
8362 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8363 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8364 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8365 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8366 }
8367 break;
8368 }
8369
8370 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8371 {
8372 if (uVpid != 0)
8373 {
8374 /* Invalidate all mappings with VPID. */
8375 /** @todo PGM support for VPID? Currently just flush everything. */
8376 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8377 iemVmxVmSucceed(pVCpu);
8378 }
8379 else
8380 {
8381 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8382 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8383 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8384 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8385 }
8386 break;
8387 }
8388
8389 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8390 {
8391 /* Invalidate all mappings with non-zero VPIDs. */
8392 /** @todo PGM support for VPID? Currently just flush everything. */
8393 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8394 iemVmxVmSucceed(pVCpu);
8395 break;
8396 }
8397
8398 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8399 {
8400 if (uVpid != 0)
8401 {
8402 /* Invalidate all mappings with VPID except global translations. */
8403 /** @todo PGM support for VPID? Currently just flush everything. */
8404 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8405 iemVmxVmSucceed(pVCpu);
8406 }
8407 else
8408 {
8409 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8410 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8411 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8412 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8413 }
8414 break;
8415 }
8416 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8417 }
8418 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8419 }
8420 return rcStrict;
8421}
8422
8423
8424/**
8425 * VMXON instruction execution worker.
8426 *
8427 * @returns Strict VBox status code.
8428 * @param pVCpu The cross context virtual CPU structure.
8429 * @param cbInstr The instruction length in bytes.
8430 * @param iEffSeg The effective segment register to use with @a
8431 * GCPtrVmxon.
8432 * @param GCPtrVmxon The linear address of the VMXON pointer.
8433 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8434 *
8435 * @remarks Common VMX instruction checks are already expected to by the caller,
8436 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8437 */
8438IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8439 PCVMXVEXITINFO pExitInfo)
8440{
8441 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8442 {
8443 /* CPL. */
8444 if (pVCpu->iem.s.uCpl == 0)
8445 { /* likely */ }
8446 else
8447 {
8448 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8449 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8450 return iemRaiseGeneralProtectionFault0(pVCpu);
8451 }
8452
8453 /* A20M (A20 Masked) mode. */
8454 if (PGMPhysIsA20Enabled(pVCpu))
8455 { /* likely */ }
8456 else
8457 {
8458 Log(("vmxon: A20M mode -> #GP(0)\n"));
8459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8460 return iemRaiseGeneralProtectionFault0(pVCpu);
8461 }
8462
8463 /* CR0. */
8464 {
8465 /* CR0 MB1 bits. */
8466 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8467 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8468 { /* likely */ }
8469 else
8470 {
8471 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8473 return iemRaiseGeneralProtectionFault0(pVCpu);
8474 }
8475
8476 /* CR0 MBZ bits. */
8477 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8478 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8479 { /* likely */ }
8480 else
8481 {
8482 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8484 return iemRaiseGeneralProtectionFault0(pVCpu);
8485 }
8486 }
8487
8488 /* CR4. */
8489 {
8490 /* CR4 MB1 bits. */
8491 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8492 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8493 { /* likely */ }
8494 else
8495 {
8496 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8497 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8498 return iemRaiseGeneralProtectionFault0(pVCpu);
8499 }
8500
8501 /* CR4 MBZ bits. */
8502 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8503 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8504 { /* likely */ }
8505 else
8506 {
8507 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8508 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8509 return iemRaiseGeneralProtectionFault0(pVCpu);
8510 }
8511 }
8512
8513 /* Feature control MSR's LOCK and VMXON bits. */
8514 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8515 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8516 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8517 { /* likely */ }
8518 else
8519 {
8520 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8521 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8522 return iemRaiseGeneralProtectionFault0(pVCpu);
8523 }
8524
8525 /* Get the VMXON pointer from the location specified by the source memory operand. */
8526 RTGCPHYS GCPhysVmxon;
8527 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8528 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8529 { /* likely */ }
8530 else
8531 {
8532 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8533 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8534 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8535 return rcStrict;
8536 }
8537
8538 /* VMXON region pointer alignment. */
8539 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8540 { /* likely */ }
8541 else
8542 {
8543 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8544 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8545 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8546 iemVmxVmFailInvalid(pVCpu);
8547 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8548 return VINF_SUCCESS;
8549 }
8550
8551 /* VMXON physical-address width limits. */
8552 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8553 { /* likely */ }
8554 else
8555 {
8556 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8557 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8558 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8559 iemVmxVmFailInvalid(pVCpu);
8560 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8561 return VINF_SUCCESS;
8562 }
8563
8564 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8565 restriction imposed by our implementation. */
8566 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8567 { /* likely */ }
8568 else
8569 {
8570 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8571 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8572 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8573 iemVmxVmFailInvalid(pVCpu);
8574 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8575 return VINF_SUCCESS;
8576 }
8577
8578 /* Read the VMCS revision ID from the VMXON region. */
8579 VMXVMCSREVID VmcsRevId;
8580 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8581 if (RT_SUCCESS(rc))
8582 { /* likely */ }
8583 else
8584 {
8585 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8587 return rc;
8588 }
8589
8590 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8591 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8592 { /* likely */ }
8593 else
8594 {
8595 /* Revision ID mismatch. */
8596 if (!VmcsRevId.n.fIsShadowVmcs)
8597 {
8598 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8599 VmcsRevId.n.u31RevisionId));
8600 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8601 iemVmxVmFailInvalid(pVCpu);
8602 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8603 return VINF_SUCCESS;
8604 }
8605
8606 /* Shadow VMCS disallowed. */
8607 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8608 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8609 iemVmxVmFailInvalid(pVCpu);
8610 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8611 return VINF_SUCCESS;
8612 }
8613
8614 /*
8615 * Record that we're in VMX operation, block INIT, block and disable A20M.
8616 */
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8618 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8619 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8620
8621 /* Clear address-range monitoring. */
8622 EMMonitorWaitClear(pVCpu);
8623 /** @todo NSTVMX: Intel PT. */
8624
8625 iemVmxVmSucceed(pVCpu);
8626 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8627 return VINF_SUCCESS;
8628 }
8629 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8630 {
8631 /* Nested-guest intercept. */
8632 if (pExitInfo)
8633 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8634 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8635 }
8636
8637 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8638
8639 /* CPL. */
8640 if (pVCpu->iem.s.uCpl > 0)
8641 {
8642 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8644 return iemRaiseGeneralProtectionFault0(pVCpu);
8645 }
8646
8647 /* VMXON when already in VMX root mode. */
8648 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8649 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8651 return VINF_SUCCESS;
8652}
8653
8654
8655/**
8656 * Implements 'VMXOFF'.
8657 *
8658 * @remarks Common VMX instruction checks are already expected to by the caller,
8659 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8660 */
8661IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8662{
8663 /* Nested-guest intercept. */
8664 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8665 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8666
8667 /* CPL. */
8668 if (pVCpu->iem.s.uCpl == 0)
8669 { /* likely */ }
8670 else
8671 {
8672 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8673 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8674 return iemRaiseGeneralProtectionFault0(pVCpu);
8675 }
8676
8677 /* Dual monitor treatment of SMIs and SMM. */
8678 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8679 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8680 { /* likely */ }
8681 else
8682 {
8683 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8684 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8685 return VINF_SUCCESS;
8686 }
8687
8688 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8689 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8690 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8691
8692 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8693 { /** @todo NSTVMX: Unblock SMI. */ }
8694
8695 EMMonitorWaitClear(pVCpu);
8696 /** @todo NSTVMX: Unblock and enable A20M. */
8697
8698 iemVmxVmSucceed(pVCpu);
8699 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8700 return VINF_SUCCESS;
8701}
8702
8703
8704/**
8705 * Implements 'VMXON'.
8706 */
8707IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8708{
8709 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8710}
8711
8712
8713/**
8714 * Implements 'VMLAUNCH'.
8715 */
8716IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8717{
8718 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8719}
8720
8721
8722/**
8723 * Implements 'VMRESUME'.
8724 */
8725IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8726{
8727 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8728}
8729
8730
8731/**
8732 * Implements 'VMPTRLD'.
8733 */
8734IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8735{
8736 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8737}
8738
8739
8740/**
8741 * Implements 'VMPTRST'.
8742 */
8743IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8744{
8745 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8746}
8747
8748
8749/**
8750 * Implements 'VMCLEAR'.
8751 */
8752IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8753{
8754 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8755}
8756
8757
8758/**
8759 * Implements 'VMWRITE' register.
8760 */
8761IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8762{
8763 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8764}
8765
8766
8767/**
8768 * Implements 'VMWRITE' memory.
8769 */
8770IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8771{
8772 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8773}
8774
8775
8776/**
8777 * Implements 'VMREAD' register (64-bit).
8778 */
8779IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8780{
8781 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8782}
8783
8784
8785/**
8786 * Implements 'VMREAD' register (32-bit).
8787 */
8788IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8789{
8790 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8791}
8792
8793
8794/**
8795 * Implements 'VMREAD' memory, 64-bit register.
8796 */
8797IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8798{
8799 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8800}
8801
8802
8803/**
8804 * Implements 'VMREAD' memory, 32-bit register.
8805 */
8806IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8807{
8808 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8809}
8810
8811
8812/**
8813 * Implements 'INVVPID'.
8814 */
8815IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8816{
8817 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8818}
8819
8820
8821/**
8822 * Implements VMX's implementation of PAUSE.
8823 */
8824IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8825{
8826 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8827 {
8828 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8829 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8830 return rcStrict;
8831 }
8832
8833 /*
8834 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8835 * a VM-exit, the instruction operates normally.
8836 */
8837 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8838 return VINF_SUCCESS;
8839}
8840
8841#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8842
8843
8844/**
8845 * Implements 'VMCALL'.
8846 */
8847IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8848{
8849#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8850 /* Nested-guest intercept. */
8851 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8852 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8853#endif
8854
8855 /* Join forces with vmmcall. */
8856 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8857}
8858
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