VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 80556

Last change on this file since 80556 was 80556, checked in by vboxsync, 5 years ago

VMM/IEM: Nested VMX: bugref:9180 Nits.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 80556 2019-09-03 05:37:47Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Sets the guest pending-debug exceptions field.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
788 */
789DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
790{
791 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
792 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
793 pVmcs->u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
794}
795
796
797/**
798 * Implements VMSucceed for VMX instruction success.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
803{
804 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
805}
806
807
808/**
809 * Implements VMFailInvalid for VMX instruction failure.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
814{
815 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
816}
817
818
819/**
820 * Implements VMFail for VMX instruction failure.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param enmInsErr The VM instruction error.
824 */
825DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
826{
827 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
828}
829
830
831/**
832 * Checks if the given auto-load/store MSR area count is valid for the
833 * implementation.
834 *
835 * @returns @c true if it's within the valid limit, @c false otherwise.
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param uMsrCount The MSR area count to check.
838 */
839DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
840{
841 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
842 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
843 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
844 if (uMsrCount <= cMaxSupportedMsrs)
845 return true;
846 return false;
847}
848
849
850/**
851 * Flushes the current VMCS contents back to guest memory.
852 *
853 * @returns VBox status code.
854 * @param pVCpu The cross context virtual CPU structure.
855 */
856DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
857{
858 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
859 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
860 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
861 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
862 return rc;
863}
864
865
866/**
867 * Populates the current VMCS contents from guest memory.
868 *
869 * @returns VBox status code.
870 * @param pVCpu The cross context virtual CPU structure.
871 */
872DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
873{
874 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
875 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
877 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
878 return rc;
879}
880
881
882/**
883 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
884 *
885 * @param pVCpu The cross context virtual CPU structure.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
888{
889 iemVmxVmSucceed(pVCpu);
890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
891}
892
893
894/**
895 * Gets the instruction diagnostic for segment base checks during VM-entry of a
896 * nested-guest.
897 *
898 * @param iSegReg The segment index (X86_SREG_XXX).
899 */
900IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
901{
902 switch (iSegReg)
903 {
904 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
905 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
906 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
907 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
908 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
909 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
910 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
911 }
912}
913
914
915/**
916 * Gets the instruction diagnostic for segment base checks during VM-entry of a
917 * nested-guest that is in Virtual-8086 mode.
918 *
919 * @param iSegReg The segment index (X86_SREG_XXX).
920 */
921IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
922{
923 switch (iSegReg)
924 {
925 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
926 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
927 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
928 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
929 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
930 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
931 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
932 }
933}
934
935
936/**
937 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
938 * nested-guest that is in Virtual-8086 mode.
939 *
940 * @param iSegReg The segment index (X86_SREG_XXX).
941 */
942IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
943{
944 switch (iSegReg)
945 {
946 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
947 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
948 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
949 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
950 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
951 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
952 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
953 }
954}
955
956
957/**
958 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
959 * nested-guest that is in Virtual-8086 mode.
960 *
961 * @param iSegReg The segment index (X86_SREG_XXX).
962 */
963IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
964{
965 switch (iSegReg)
966 {
967 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
968 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
969 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
970 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
971 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
972 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
973 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
974 }
975}
976
977
978/**
979 * Gets the instruction diagnostic for segment attributes reserved bits failure
980 * during VM-entry of a nested-guest.
981 *
982 * @param iSegReg The segment index (X86_SREG_XXX).
983 */
984IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
985{
986 switch (iSegReg)
987 {
988 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
989 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
990 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
991 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
992 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
993 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
994 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
995 }
996}
997
998
999/**
1000 * Gets the instruction diagnostic for segment attributes descriptor-type
1001 * (code/segment or system) failure during VM-entry of a nested-guest.
1002 *
1003 * @param iSegReg The segment index (X86_SREG_XXX).
1004 */
1005IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1006{
1007 switch (iSegReg)
1008 {
1009 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1010 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1011 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1012 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1013 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1014 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1015 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1016 }
1017}
1018
1019
1020/**
1021 * Gets the instruction diagnostic for segment attributes descriptor-type
1022 * (code/segment or system) failure during VM-entry of a nested-guest.
1023 *
1024 * @param iSegReg The segment index (X86_SREG_XXX).
1025 */
1026IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1027{
1028 switch (iSegReg)
1029 {
1030 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1031 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1032 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1033 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1034 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1035 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1036 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1037 }
1038}
1039
1040
1041/**
1042 * Gets the instruction diagnostic for segment attribute granularity failure during
1043 * VM-entry of a nested-guest.
1044 *
1045 * @param iSegReg The segment index (X86_SREG_XXX).
1046 */
1047IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1048{
1049 switch (iSegReg)
1050 {
1051 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1052 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1053 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1054 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1055 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1056 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1057 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1058 }
1059}
1060
1061/**
1062 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1063 * VM-entry of a nested-guest.
1064 *
1065 * @param iSegReg The segment index (X86_SREG_XXX).
1066 */
1067IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1068{
1069 switch (iSegReg)
1070 {
1071 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1072 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1073 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1074 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1075 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1076 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1077 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1078 }
1079}
1080
1081
1082/**
1083 * Gets the instruction diagnostic for segment attribute type accessed failure
1084 * during VM-entry of a nested-guest.
1085 *
1086 * @param iSegReg The segment index (X86_SREG_XXX).
1087 */
1088IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1089{
1090 switch (iSegReg)
1091 {
1092 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1093 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1094 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1095 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1096 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1097 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1098 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1099 }
1100}
1101
1102
1103/**
1104 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1105 * failure during VM-entry of a nested-guest.
1106 *
1107 * @param iSegReg The PDPTE entry index.
1108 */
1109IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1110{
1111 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1112 switch (iPdpte)
1113 {
1114 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1115 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1116 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1117 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1118 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1119 }
1120}
1121
1122
1123/**
1124 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1125 * failure during VM-exit of a nested-guest.
1126 *
1127 * @param iSegReg The PDPTE entry index.
1128 */
1129IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1130{
1131 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1132 switch (iPdpte)
1133 {
1134 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1135 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1136 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1137 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1138 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1139 }
1140}
1141
1142
1143/**
1144 * Saves the guest control registers, debug registers and some MSRs are part of
1145 * VM-exit.
1146 *
1147 * @param pVCpu The cross context virtual CPU structure.
1148 */
1149IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1150{
1151 /*
1152 * Saves the guest control registers, debug registers and some MSRs.
1153 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1154 */
1155 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1156
1157 /* Save control registers. */
1158 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1159 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1160 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1161
1162 /* Save SYSENTER CS, ESP, EIP. */
1163 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1165 {
1166 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1167 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1168 }
1169 else
1170 {
1171 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1172 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1173 }
1174
1175 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1176 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1177 {
1178 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1179 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1180 }
1181
1182 /* Save PAT MSR. */
1183 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1184 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1185
1186 /* Save EFER MSR. */
1187 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1188 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1189
1190 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1191 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1192
1193 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1194}
1195
1196
1197/**
1198 * Saves the guest force-flags in preparation of entering the nested-guest.
1199 *
1200 * @param pVCpu The cross context virtual CPU structure.
1201 */
1202IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1203{
1204 /* We shouldn't be called multiple times during VM-entry. */
1205 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1206
1207 /* MTF should not be set outside VMX non-root mode. */
1208 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1209
1210 /*
1211 * Preserve the required force-flags.
1212 *
1213 * We cache and clear force-flags that would affect the execution of the
1214 * nested-guest. Cached flags are then restored while returning to the guest
1215 * if necessary.
1216 *
1217 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1218 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1219 * instruction. Interrupt inhibition for any nested-guest instruction
1220 * is supplied by the guest-interruptibility state VMCS field and will
1221 * be set up as part of loading the guest state.
1222 *
1223 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1224 * successful VM-entry (due to invalid guest-state) need to continue
1225 * blocking NMIs if it was in effect before VM-entry.
1226 *
1227 * - MTF need not be preserved as it's used only in VMX non-root mode and
1228 * is supplied through the VM-execution controls.
1229 *
1230 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1231 * we will be able to generate interrupts that may cause VM-exits for
1232 * the nested-guest.
1233 */
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1235}
1236
1237
1238/**
1239 * Restores the guest force-flags in preparation of exiting the nested-guest.
1240 *
1241 * @param pVCpu The cross context virtual CPU structure.
1242 */
1243IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1244{
1245 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1246 {
1247 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1248 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1249 }
1250}
1251
1252
1253/**
1254 * Perform a VMX transition updated PGM, IEM and CPUM.
1255 *
1256 * @param pVCpu The cross context virtual CPU structure.
1257 */
1258IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1259{
1260 /*
1261 * Inform PGM about paging mode changes.
1262 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1263 * see comment in iemMemPageTranslateAndCheckAccess().
1264 */
1265 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1266# ifdef IN_RING3
1267 Assert(rc != VINF_PGM_CHANGE_MODE);
1268# endif
1269 AssertRCReturn(rc, rc);
1270
1271 /* Inform CPUM (recompiler), can later be removed. */
1272 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1273
1274 /*
1275 * Flush the TLB with new CR3. This is required in case the PGM mode change
1276 * above doesn't actually change anything.
1277 */
1278 if (rc == VINF_SUCCESS)
1279 {
1280 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1281 AssertRCReturn(rc, rc);
1282 }
1283
1284 /* Re-initialize IEM cache/state after the drastic mode switch. */
1285 iemReInitExec(pVCpu);
1286 return rc;
1287}
1288
1289
1290/**
1291 * Calculates the current VMX-preemption timer value.
1292 *
1293 * @returns The current VMX-preemption timer value.
1294 * @param pVCpu The cross context virtual CPU structure.
1295 */
1296IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1297{
1298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1299 Assert(pVmcs);
1300
1301 /*
1302 * Assume the following:
1303 * PreemptTimerShift = 5
1304 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1305 * EntryTick = 50000 (TSC at time of VM-entry)
1306 *
1307 * CurTick Delta PreemptTimerVal
1308 * ----------------------------------
1309 * 60000 10000 2
1310 * 80000 30000 1
1311 * 90000 40000 0 -> VM-exit.
1312 *
1313 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1314 * The saved VMX-preemption timer value is calculated as follows:
1315 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1316 * E.g.:
1317 * Delta = 10000
1318 * Tmp = 10000 / (2 * 10000) = 0.5
1319 * NewPt = 2 - 0.5 = 2
1320 * Delta = 30000
1321 * Tmp = 30000 / (2 * 10000) = 1.5
1322 * NewPt = 2 - 1.5 = 1
1323 * Delta = 40000
1324 * Tmp = 40000 / 20000 = 2
1325 * NewPt = 2 - 2 = 0
1326 */
1327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1328 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1329 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1330 uint64_t const uDelta = uCurTick - uEntryTick;
1331 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1332 uint32_t const uPreemptTimer = uVmcsPreemptVal
1333 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1334 return uPreemptTimer;
1335}
1336
1337
1338/**
1339 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1340 *
1341 * @param pVCpu The cross context virtual CPU structure.
1342 */
1343IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1344{
1345 /*
1346 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1347 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1348 */
1349 /* CS, SS, ES, DS, FS, GS. */
1350 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1351 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1352 {
1353 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1354 if (!pSelReg->Attr.n.u1Unusable)
1355 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1356 else
1357 {
1358 /*
1359 * For unusable segments the attributes are undefined except for CS and SS.
1360 * For the rest we don't bother preserving anything but the unusable bit.
1361 */
1362 switch (iSegReg)
1363 {
1364 case X86_SREG_CS:
1365 pVmcs->GuestCs = pSelReg->Sel;
1366 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1367 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1368 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1369 | X86DESCATTR_UNUSABLE);
1370 break;
1371
1372 case X86_SREG_SS:
1373 pVmcs->GuestSs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_DS:
1380 pVmcs->GuestDs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1384 break;
1385
1386 case X86_SREG_ES:
1387 pVmcs->GuestEs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_FS:
1394 pVmcs->GuestFs = pSelReg->Sel;
1395 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1396 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1397 break;
1398
1399 case X86_SREG_GS:
1400 pVmcs->GuestGs = pSelReg->Sel;
1401 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1403 break;
1404 }
1405 }
1406 }
1407
1408 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1409 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1410 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1411 | X86DESCATTR_UNUSABLE;
1412 /* LDTR. */
1413 {
1414 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1415 pVmcs->GuestLdtr = pSelReg->Sel;
1416 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1417 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1418 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1419 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1420 }
1421
1422 /* TR. */
1423 {
1424 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1425 pVmcs->GuestTr = pSelReg->Sel;
1426 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1427 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1428 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1429 }
1430
1431 /* GDTR. */
1432 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1433 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1434
1435 /* IDTR. */
1436 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1437 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1438}
1439
1440
1441/**
1442 * Saves guest non-register state as part of VM-exit.
1443 *
1444 * @param pVCpu The cross context virtual CPU structure.
1445 * @param uExitReason The VM-exit reason.
1446 */
1447IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1448{
1449 /*
1450 * Save guest non-register state.
1451 * See Intel spec. 27.3.4 "Saving Non-Register State".
1452 */
1453 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1454
1455 /*
1456 * Activity state.
1457 * Most VM-exits will occur in the active state. However, if the first instruction
1458 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1459 * the VM-exit will be from the HLT activity state.
1460 *
1461 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1462 */
1463 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1464 * not? */
1465 EMSTATE const enmActivityState = EMGetState(pVCpu);
1466 switch (enmActivityState)
1467 {
1468 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1469 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1470 }
1471
1472 /*
1473 * Interruptibility-state.
1474 */
1475 /* NMI. */
1476 pVmcs->u32GuestIntrState = 0;
1477 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1478 {
1479 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1481 }
1482 else
1483 {
1484 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1485 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1486 }
1487
1488 /* Blocking-by-STI. */
1489 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1490 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1491 {
1492 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1493 * currently. */
1494 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1495 }
1496 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1497
1498 /*
1499 * Pending debug exceptions.
1500 *
1501 * For VM-exits where it is not applicable, we can safely zero out the field.
1502 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1503 */
1504 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1505 && uExitReason != VMX_EXIT_SMI
1506 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1507 && !VMXIsVmexitTrapLike(uExitReason))
1508 {
1509 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1510 * block-by-MovSS is in effect. */
1511 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1512 }
1513
1514 /*
1515 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1516 *
1517 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1518 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1519 */
1520 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1521 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1522 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1523
1524 /* PDPTEs. */
1525 /* We don't support EPT yet. */
1526 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1527 pVmcs->u64GuestPdpte0.u = 0;
1528 pVmcs->u64GuestPdpte1.u = 0;
1529 pVmcs->u64GuestPdpte2.u = 0;
1530 pVmcs->u64GuestPdpte3.u = 0;
1531}
1532
1533
1534/**
1535 * Saves the guest-state as part of VM-exit.
1536 *
1537 * @returns VBox status code.
1538 * @param pVCpu The cross context virtual CPU structure.
1539 * @param uExitReason The VM-exit reason.
1540 */
1541IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1542{
1543 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1544 Assert(pVmcs);
1545
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1571 const char *const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the guest hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 Assert(pMsr);
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1717 }
1718
1719 /* CR4. */
1720 {
1721 /* Fixed CR4 bits are not modified. */
1722 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1723 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1724 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1725 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1726 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1727 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1728 if (fHostInLongMode)
1729 uValidHostCr4 |= X86_CR4_PAE;
1730 else
1731 uValidHostCr4 &= ~X86_CR4_PCIDE;
1732 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1733 }
1734
1735 /* CR3 (host value validated while checking host-state during VM-entry). */
1736 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1737
1738 /* DR7. */
1739 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1740
1741 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1742
1743 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1745 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1746 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1747
1748 /* FS, GS bases are loaded later while we load host segment registers. */
1749
1750 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1751 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1752 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1753 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1754 {
1755 if (fHostInLongMode)
1756 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1757 else
1758 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 }
1760
1761 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1762
1763 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1764 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1765 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1766
1767 /* We don't support IA32_BNDCFGS MSR yet. */
1768}
1769
1770
1771/**
1772 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1773 *
1774 * @param pVCpu The cross context virtual CPU structure.
1775 */
1776IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1777{
1778 /*
1779 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1780 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1781 *
1782 * Warning! Be careful to not touch fields that are reserved by VT-x,
1783 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1784 */
1785 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1786 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1787
1788 /* CS, SS, ES, DS, FS, GS. */
1789 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1790 {
1791 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1792 bool const fUnusable = RT_BOOL(HostSel == 0);
1793 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1794
1795 /* Selector. */
1796 pSelReg->Sel = HostSel;
1797 pSelReg->ValidSel = HostSel;
1798 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1799
1800 /* Limit. */
1801 pSelReg->u32Limit = 0xffffffff;
1802
1803 /* Base. */
1804 pSelReg->u64Base = 0;
1805
1806 /* Attributes. */
1807 if (iSegReg == X86_SREG_CS)
1808 {
1809 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1810 pSelReg->Attr.n.u1DescType = 1;
1811 pSelReg->Attr.n.u2Dpl = 0;
1812 pSelReg->Attr.n.u1Present = 1;
1813 pSelReg->Attr.n.u1Long = fHostInLongMode;
1814 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1815 pSelReg->Attr.n.u1Granularity = 1;
1816 Assert(!pSelReg->Attr.n.u1Unusable);
1817 Assert(!fUnusable);
1818 }
1819 else
1820 {
1821 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1822 pSelReg->Attr.n.u1DescType = 1;
1823 pSelReg->Attr.n.u2Dpl = 0;
1824 pSelReg->Attr.n.u1Present = 1;
1825 pSelReg->Attr.n.u1DefBig = 1;
1826 pSelReg->Attr.n.u1Granularity = 1;
1827 pSelReg->Attr.n.u1Unusable = fUnusable;
1828 }
1829 }
1830
1831 /* FS base. */
1832 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1833 || fHostInLongMode)
1834 {
1835 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1836 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1837 }
1838
1839 /* GS base. */
1840 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1844 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1845 }
1846
1847 /* TR. */
1848 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1849 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1850 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1851 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1852 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1853 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1854 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1856 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1861
1862 /* LDTR (Warning! do not touch the base and limits here). */
1863 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1864 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1865 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1866 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1867
1868 /* GDTR. */
1869 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1870 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1871 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1872
1873 /* IDTR.*/
1874 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1875 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1876 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1877}
1878
1879
1880/**
1881 * Checks host PDPTes as part of VM-exit.
1882 *
1883 * @param pVCpu The cross context virtual CPU structure.
1884 * @param uExitReason The VM-exit reason (for logging purposes).
1885 */
1886IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1887{
1888 /*
1889 * Check host PDPTEs.
1890 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1891 */
1892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1893 const char *const pszFailure = "VMX-abort";
1894 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1895
1896 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1897 && !fHostInLongMode)
1898 {
1899 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1900 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1901 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1902 if (RT_SUCCESS(rc))
1903 {
1904 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1905 {
1906 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1907 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1908 { /* likely */ }
1909 else
1910 {
1911 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1912 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1913 }
1914 }
1915 }
1916 else
1917 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1918 }
1919
1920 NOREF(pszFailure);
1921 NOREF(uExitReason);
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/**
1927 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1928 *
1929 * @returns VBox status code.
1930 * @param pVCpu The cross context virtual CPU structure.
1931 * @param pszInstr The VMX instruction name (for logging purposes).
1932 */
1933IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1934{
1935 /*
1936 * Load host MSRs.
1937 * See Intel spec. 27.6 "Loading MSRs".
1938 */
1939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1940 const char *const pszFailure = "VMX-abort";
1941
1942 /*
1943 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1944 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1945 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1946 */
1947 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1948 if (!cMsrs)
1949 return VINF_SUCCESS;
1950
1951 /*
1952 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1953 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1954 * implementation causes a VMX-abort followed by a triple-fault.
1955 */
1956 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1957 if (fIsMsrCountValid)
1958 { /* likely */ }
1959 else
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1961
1962 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1963 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1964 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1965 if (RT_SUCCESS(rc))
1966 {
1967 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1968 Assert(pMsr);
1969 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1970 {
1971 if ( !pMsr->u32Reserved
1972 && pMsr->u32Msr != MSR_K8_FS_BASE
1973 && pMsr->u32Msr != MSR_K8_GS_BASE
1974 && pMsr->u32Msr != MSR_K6_EFER
1975 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1976 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1977 {
1978 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1979 if (rcStrict == VINF_SUCCESS)
1980 continue;
1981
1982 /*
1983 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1984 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1985 * recording the MSR index in the auxiliary info. field and indicated further by our
1986 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1987 * if possible, or come up with a better, generic solution.
1988 */
1989 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1990 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1991 ? kVmxVDiag_Vmexit_MsrLoadRing3
1992 : kVmxVDiag_Vmexit_MsrLoad;
1993 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1994 }
1995 else
1996 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1997 }
1998 }
1999 else
2000 {
2001 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2003 }
2004
2005 NOREF(uExitReason);
2006 NOREF(pszFailure);
2007 return VINF_SUCCESS;
2008}
2009
2010
2011/**
2012 * Loads the host state as part of VM-exit.
2013 *
2014 * @returns Strict VBox status code.
2015 * @param pVCpu The cross context virtual CPU structure.
2016 * @param uExitReason The VM-exit reason (for logging purposes).
2017 */
2018IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2019{
2020 /*
2021 * Load host state.
2022 * See Intel spec. 27.5 "Loading Host State".
2023 */
2024 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2025 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2026
2027 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2028 if ( CPUMIsGuestInLongMode(pVCpu)
2029 && !fHostInLongMode)
2030 {
2031 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2032 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2033 }
2034
2035 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2036 iemVmxVmexitLoadHostSegRegs(pVCpu);
2037
2038 /*
2039 * Load host RIP, RSP and RFLAGS.
2040 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2041 */
2042 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2043 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2044 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2045
2046 /* Clear address range monitoring. */
2047 EMMonitorWaitClear(pVCpu);
2048
2049 /* Perform the VMX transition (PGM updates). */
2050 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2051 if (rcStrict == VINF_SUCCESS)
2052 {
2053 /* Check host PDPTEs (only when we've fully switched page tables_. */
2054 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2055 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2056 if (RT_FAILURE(rc))
2057 {
2058 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2059 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2060 }
2061 }
2062 else if (RT_SUCCESS(rcStrict))
2063 {
2064 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2065 uExitReason));
2066 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2067 }
2068 else
2069 {
2070 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2071 return VBOXSTRICTRC_VAL(rcStrict);
2072 }
2073
2074 Assert(rcStrict == VINF_SUCCESS);
2075
2076 /* Load MSRs from the VM-exit auto-load MSR area. */
2077 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2078 if (RT_FAILURE(rc))
2079 {
2080 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2081 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2082 }
2083 return VINF_SUCCESS;
2084}
2085
2086
2087/**
2088 * Gets VM-exit instruction information along with any displacement for an
2089 * instruction VM-exit.
2090 *
2091 * @returns The VM-exit instruction information.
2092 * @param pVCpu The cross context virtual CPU structure.
2093 * @param uExitReason The VM-exit reason.
2094 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2095 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2096 * NULL.
2097 */
2098IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2099{
2100 RTGCPTR GCPtrDisp;
2101 VMXEXITINSTRINFO ExitInstrInfo;
2102 ExitInstrInfo.u = 0;
2103
2104 /*
2105 * Get and parse the ModR/M byte from our decoded opcodes.
2106 */
2107 uint8_t bRm;
2108 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2109 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2110 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2111 {
2112 /*
2113 * ModR/M indicates register addressing.
2114 *
2115 * The primary/secondary register operands are reported in the iReg1 or iReg2
2116 * fields depending on whether it is a read/write form.
2117 */
2118 uint8_t idxReg1;
2119 uint8_t idxReg2;
2120 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2121 {
2122 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2123 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2124 }
2125 else
2126 {
2127 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2128 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2129 }
2130 ExitInstrInfo.All.u2Scaling = 0;
2131 ExitInstrInfo.All.iReg1 = idxReg1;
2132 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2133 ExitInstrInfo.All.fIsRegOperand = 1;
2134 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2135 ExitInstrInfo.All.iSegReg = 0;
2136 ExitInstrInfo.All.iIdxReg = 0;
2137 ExitInstrInfo.All.fIdxRegInvalid = 1;
2138 ExitInstrInfo.All.iBaseReg = 0;
2139 ExitInstrInfo.All.fBaseRegInvalid = 1;
2140 ExitInstrInfo.All.iReg2 = idxReg2;
2141
2142 /* Displacement not applicable for register addressing. */
2143 GCPtrDisp = 0;
2144 }
2145 else
2146 {
2147 /*
2148 * ModR/M indicates memory addressing.
2149 */
2150 uint8_t uScale = 0;
2151 bool fBaseRegValid = false;
2152 bool fIdxRegValid = false;
2153 uint8_t iBaseReg = 0;
2154 uint8_t iIdxReg = 0;
2155 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2156 {
2157 /*
2158 * Parse the ModR/M, displacement for 16-bit addressing mode.
2159 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2160 */
2161 uint16_t u16Disp = 0;
2162 uint8_t const offDisp = offModRm + sizeof(bRm);
2163 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2164 {
2165 /* Displacement without any registers. */
2166 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2167 }
2168 else
2169 {
2170 /* Register (index and base). */
2171 switch (bRm & X86_MODRM_RM_MASK)
2172 {
2173 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2174 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2175 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2180 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2181 }
2182
2183 /* Register + displacement. */
2184 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2185 {
2186 case 0: break;
2187 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2188 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2189 default:
2190 {
2191 /* Register addressing, handled at the beginning. */
2192 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2193 break;
2194 }
2195 }
2196 }
2197
2198 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2199 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2200 }
2201 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2202 {
2203 /*
2204 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2205 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2206 */
2207 uint32_t u32Disp = 0;
2208 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2209 {
2210 /* Displacement without any registers. */
2211 uint8_t const offDisp = offModRm + sizeof(bRm);
2212 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2213 }
2214 else
2215 {
2216 /* Register (and perhaps scale, index and base). */
2217 uint8_t offDisp = offModRm + sizeof(bRm);
2218 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2219 if (iBaseReg == 4)
2220 {
2221 /* An SIB byte follows the ModR/M byte, parse it. */
2222 uint8_t bSib;
2223 uint8_t const offSib = offModRm + sizeof(bRm);
2224 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2225
2226 /* A displacement may follow SIB, update its offset. */
2227 offDisp += sizeof(bSib);
2228
2229 /* Get the scale. */
2230 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2231
2232 /* Get the index register. */
2233 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2234 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2235
2236 /* Get the base register. */
2237 iBaseReg = bSib & X86_SIB_BASE_MASK;
2238 fBaseRegValid = true;
2239 if (iBaseReg == 5)
2240 {
2241 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2242 {
2243 /* Mod is 0 implies a 32-bit displacement with no base. */
2244 fBaseRegValid = false;
2245 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2246 }
2247 else
2248 {
2249 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2250 iBaseReg = X86_GREG_xBP;
2251 }
2252 }
2253 }
2254
2255 /* Register + displacement. */
2256 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2257 {
2258 case 0: /* Handled above */ break;
2259 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2260 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2261 default:
2262 {
2263 /* Register addressing, handled at the beginning. */
2264 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2265 break;
2266 }
2267 }
2268 }
2269
2270 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2271 }
2272 else
2273 {
2274 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2275
2276 /*
2277 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2278 * See Intel instruction spec. 2.2 "IA-32e Mode".
2279 */
2280 uint64_t u64Disp = 0;
2281 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2282 if (fRipRelativeAddr)
2283 {
2284 /*
2285 * RIP-relative addressing mode.
2286 *
2287 * The displacement is 32-bit signed implying an offset range of +/-2G.
2288 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2289 */
2290 uint8_t const offDisp = offModRm + sizeof(bRm);
2291 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2292 }
2293 else
2294 {
2295 uint8_t offDisp = offModRm + sizeof(bRm);
2296
2297 /*
2298 * Register (and perhaps scale, index and base).
2299 *
2300 * REX.B extends the most-significant bit of the base register. However, REX.B
2301 * is ignored while determining whether an SIB follows the opcode. Hence, we
2302 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2303 *
2304 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2305 */
2306 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2307 if (iBaseReg == 4)
2308 {
2309 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2310 uint8_t bSib;
2311 uint8_t const offSib = offModRm + sizeof(bRm);
2312 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2313
2314 /* Displacement may follow SIB, update its offset. */
2315 offDisp += sizeof(bSib);
2316
2317 /* Get the scale. */
2318 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2319
2320 /* Get the index. */
2321 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2322 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2323
2324 /* Get the base. */
2325 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2326 fBaseRegValid = true;
2327 if (iBaseReg == 5)
2328 {
2329 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2330 {
2331 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2332 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2333 }
2334 else
2335 {
2336 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2337 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2338 }
2339 }
2340 }
2341 iBaseReg |= pVCpu->iem.s.uRexB;
2342
2343 /* Register + displacement. */
2344 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2345 {
2346 case 0: /* Handled above */ break;
2347 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2348 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2349 default:
2350 {
2351 /* Register addressing, handled at the beginning. */
2352 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2353 break;
2354 }
2355 }
2356 }
2357
2358 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2359 }
2360
2361 /*
2362 * The primary or secondary register operand is reported in iReg2 depending
2363 * on whether the primary operand is in read/write form.
2364 */
2365 uint8_t idxReg2;
2366 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2367 {
2368 idxReg2 = bRm & X86_MODRM_RM_MASK;
2369 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2370 idxReg2 |= pVCpu->iem.s.uRexB;
2371 }
2372 else
2373 {
2374 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2375 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2376 idxReg2 |= pVCpu->iem.s.uRexReg;
2377 }
2378 ExitInstrInfo.All.u2Scaling = uScale;
2379 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2380 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2381 ExitInstrInfo.All.fIsRegOperand = 0;
2382 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2383 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2384 ExitInstrInfo.All.iIdxReg = iIdxReg;
2385 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2386 ExitInstrInfo.All.iBaseReg = iBaseReg;
2387 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2388 ExitInstrInfo.All.iReg2 = idxReg2;
2389 }
2390
2391 /*
2392 * Handle exceptions to the norm for certain instructions.
2393 * (e.g. some instructions convey an instruction identity in place of iReg2).
2394 */
2395 switch (uExitReason)
2396 {
2397 case VMX_EXIT_GDTR_IDTR_ACCESS:
2398 {
2399 Assert(VMXINSTRID_IS_VALID(uInstrId));
2400 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2401 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2402 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2403 break;
2404 }
2405
2406 case VMX_EXIT_LDTR_TR_ACCESS:
2407 {
2408 Assert(VMXINSTRID_IS_VALID(uInstrId));
2409 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2410 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2411 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2412 break;
2413 }
2414
2415 case VMX_EXIT_RDRAND:
2416 case VMX_EXIT_RDSEED:
2417 {
2418 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2419 break;
2420 }
2421 }
2422
2423 /* Update displacement and return the constructed VM-exit instruction information field. */
2424 if (pGCPtrDisp)
2425 *pGCPtrDisp = GCPtrDisp;
2426
2427 return ExitInstrInfo.u;
2428}
2429
2430
2431/**
2432 * VMX VM-exit handler.
2433 *
2434 * @returns Strict VBox status code.
2435 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2436 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2437 * triple-fault.
2438 *
2439 * @param pVCpu The cross context virtual CPU structure.
2440 * @param uExitReason The VM-exit reason.
2441 * @param u64ExitQual The Exit qualification.
2442 */
2443IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2444{
2445# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2446 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2447 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2448 return VERR_IEM_IPE_7;
2449# else
2450 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2451 Assert(pVmcs);
2452
2453 /*
2454 * Import all the guest-CPU state.
2455 *
2456 * HM on returning to guest execution would have to reset up a whole lot of state
2457 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2458 * the state and flag reloading the entire state on re-entry. So import the entire
2459 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2460 */
2461 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2462
2463 /*
2464 * Ensure VM-entry interruption information valid bit is cleared.
2465 *
2466 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2467 * by invalid-guest state or machine-check exceptions) also clear this bit.
2468 *
2469 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2470 */
2471 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2472 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2473
2474 /*
2475 * Update the VM-exit reason and Exit qualification.
2476 * Other VMCS read-only data fields are expected to be updated by the caller already.
2477 */
2478 pVmcs->u32RoExitReason = uExitReason;
2479 pVmcs->u64RoExitQual.u = u64ExitQual;
2480
2481 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2482 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2483
2484 /*
2485 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2486 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2487 */
2488 {
2489 uint8_t uVector;
2490 uint32_t fFlags;
2491 uint32_t uErrCode;
2492 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2493 if (fInEventDelivery)
2494 {
2495 /*
2496 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2497 * caused by a triple-fault or the original event results in a double-fault that
2498 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2499 * original event information into the IDT-vectoring information fields.
2500 *
2501 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2502 */
2503 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2504 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2505 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2506 {
2507 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2508 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2509 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2510 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2511 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2512 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2513 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2514 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2515 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32\n", uIdtVectoringInfo, uErrCode));
2516 }
2517 }
2518 }
2519
2520 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2521 Assert(pVmcs->u64RoIoRcx.u == 0);
2522 Assert(pVmcs->u64RoIoRsi.u == 0);
2523 Assert(pVmcs->u64RoIoRdi.u == 0);
2524 Assert(pVmcs->u64RoIoRip.u == 0);
2525
2526 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2527 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2528 {
2529 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2530 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2531 }
2532
2533 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2534 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2535
2536 /*
2537 * Save the guest state back into the VMCS.
2538 * We only need to save the state when the VM-entry was successful.
2539 */
2540 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2541 if (!fVmentryFailed)
2542 {
2543 /*
2544 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2545 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2546 *
2547 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2548 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2549 * as guest-CPU state would not been modified. Hence for now, we do this only when
2550 * the VM-entry succeeded.
2551 */
2552 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2553 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2554 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2555 {
2556 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2557 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2558 else
2559 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2560 }
2561
2562 /*
2563 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2564 * occurs in enclave mode/SMM which we don't support yet.
2565 *
2566 * If we ever add support for it, we can pass just the lower bits to the functions
2567 * below, till then an assert should suffice.
2568 */
2569 Assert(!RT_HI_U16(uExitReason));
2570
2571 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2572 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2573 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2574 if (RT_SUCCESS(rc))
2575 { /* likely */ }
2576 else
2577 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2578
2579 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2580 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2581 }
2582 else
2583 {
2584 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2585 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2586 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2587 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2588 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2589 }
2590
2591 /*
2592 * Clear any pending VMX nested-guest force-flags.
2593 * These force-flags have no effect on guest execution and will
2594 * be re-evaluated and setup on the next nested-guest VM-entry.
2595 */
2596 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2597 | VMCPU_FF_VMX_MTF
2598 | VMCPU_FF_VMX_APIC_WRITE
2599 | VMCPU_FF_VMX_INT_WINDOW
2600 | VMCPU_FF_VMX_NMI_WINDOW);
2601
2602 /* Restore the host (outer guest) state. */
2603 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2604 if (RT_SUCCESS(rcStrict))
2605 {
2606 Assert(rcStrict == VINF_SUCCESS);
2607 rcStrict = VINF_VMX_VMEXIT;
2608 }
2609 else
2610 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2611
2612 /* We're no longer in nested-guest execution mode. */
2613 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2614
2615 /* Notify HM that the current VMCS fields have been modified. */
2616 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2617
2618 /* Notify HM that we've completed the VM-exit. */
2619 HMNotifyVmxNstGstVmexit(pVCpu);
2620
2621# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2622 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2623 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2624 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2625 if (rcSched != VINF_SUCCESS)
2626 iemSetPassUpStatus(pVCpu, rcSched);
2627# endif
2628 return rcStrict;
2629# endif
2630}
2631
2632
2633/**
2634 * VMX VM-exit handler for VM-exits due to instruction execution.
2635 *
2636 * This is intended for instructions where the caller provides all the relevant
2637 * VM-exit information.
2638 *
2639 * @returns Strict VBox status code.
2640 * @param pVCpu The cross context virtual CPU structure.
2641 * @param pExitInfo Pointer to the VM-exit information.
2642 */
2643IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2644{
2645 /*
2646 * For instructions where any of the following fields are not applicable:
2647 * - Exit qualification must be cleared.
2648 * - VM-exit instruction info. is undefined.
2649 * - Guest-linear address is undefined.
2650 * - Guest-physical address is undefined.
2651 *
2652 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2653 * instruction execution. For VM-exits that are not due to instruction execution this
2654 * field is undefined.
2655 *
2656 * In our implementation in IEM, all undefined fields are generally cleared. However,
2657 * if the caller supplies information (from say the physical CPU directly) it is
2658 * then possible that the undefined fields are not cleared.
2659 *
2660 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2661 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2662 */
2663 Assert(pExitInfo);
2664 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2665 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2666 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2667
2668 /* Update all the relevant fields from the VM-exit instruction information struct. */
2669 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2670 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2671 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2672 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2673
2674 /* Perform the VM-exit. */
2675 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2676}
2677
2678
2679/**
2680 * VMX VM-exit handler for VM-exits due to instruction execution.
2681 *
2682 * This is intended for instructions that only provide the VM-exit instruction
2683 * length.
2684 *
2685 * @param pVCpu The cross context virtual CPU structure.
2686 * @param uExitReason The VM-exit reason.
2687 * @param cbInstr The instruction length in bytes.
2688 */
2689IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2690{
2691 VMXVEXITINFO ExitInfo;
2692 RT_ZERO(ExitInfo);
2693 ExitInfo.uReason = uExitReason;
2694 ExitInfo.cbInstr = cbInstr;
2695
2696#ifdef VBOX_STRICT
2697 /*
2698 * To prevent us from shooting ourselves in the foot.
2699 * The follow instructions should convey more than just the instruction length.
2700 */
2701 switch (uExitReason)
2702 {
2703 case VMX_EXIT_INVEPT:
2704 case VMX_EXIT_INVPCID:
2705 case VMX_EXIT_INVVPID:
2706 case VMX_EXIT_LDTR_TR_ACCESS:
2707 case VMX_EXIT_GDTR_IDTR_ACCESS:
2708 case VMX_EXIT_VMCLEAR:
2709 case VMX_EXIT_VMPTRLD:
2710 case VMX_EXIT_VMPTRST:
2711 case VMX_EXIT_VMREAD:
2712 case VMX_EXIT_VMWRITE:
2713 case VMX_EXIT_VMXON:
2714 case VMX_EXIT_XRSTORS:
2715 case VMX_EXIT_XSAVES:
2716 case VMX_EXIT_RDRAND:
2717 case VMX_EXIT_RDSEED:
2718 case VMX_EXIT_IO_INSTR:
2719 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2720 break;
2721 }
2722#endif
2723
2724 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2725}
2726
2727
2728/**
2729 * VMX VM-exit handler for VM-exits due to instruction execution.
2730 *
2731 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2732 * instruction information and Exit qualification fields.
2733 *
2734 * @param pVCpu The cross context virtual CPU structure.
2735 * @param uExitReason The VM-exit reason.
2736 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2737 * @param cbInstr The instruction length in bytes.
2738 *
2739 * @remarks Do not use this for INS/OUTS instruction.
2740 */
2741IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2742{
2743 VMXVEXITINFO ExitInfo;
2744 RT_ZERO(ExitInfo);
2745 ExitInfo.uReason = uExitReason;
2746 ExitInfo.cbInstr = cbInstr;
2747
2748 /*
2749 * Update the Exit qualification field with displacement bytes.
2750 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2751 */
2752 switch (uExitReason)
2753 {
2754 case VMX_EXIT_INVEPT:
2755 case VMX_EXIT_INVPCID:
2756 case VMX_EXIT_INVVPID:
2757 case VMX_EXIT_LDTR_TR_ACCESS:
2758 case VMX_EXIT_GDTR_IDTR_ACCESS:
2759 case VMX_EXIT_VMCLEAR:
2760 case VMX_EXIT_VMPTRLD:
2761 case VMX_EXIT_VMPTRST:
2762 case VMX_EXIT_VMREAD:
2763 case VMX_EXIT_VMWRITE:
2764 case VMX_EXIT_VMXON:
2765 case VMX_EXIT_XRSTORS:
2766 case VMX_EXIT_XSAVES:
2767 case VMX_EXIT_RDRAND:
2768 case VMX_EXIT_RDSEED:
2769 {
2770 /* Construct the VM-exit instruction information. */
2771 RTGCPTR GCPtrDisp;
2772 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2773
2774 /* Update the VM-exit instruction information. */
2775 ExitInfo.InstrInfo.u = uInstrInfo;
2776
2777 /* Update the Exit qualification. */
2778 ExitInfo.u64Qual = GCPtrDisp;
2779 break;
2780 }
2781
2782 default:
2783 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2784 break;
2785 }
2786
2787 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2788}
2789
2790
2791/**
2792 * VMX VM-exit handler for VM-exits due to INVLPG.
2793 *
2794 * @returns Strict VBox status code.
2795 * @param pVCpu The cross context virtual CPU structure.
2796 * @param GCPtrPage The guest-linear address of the page being invalidated.
2797 * @param cbInstr The instruction length in bytes.
2798 */
2799IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2800{
2801 VMXVEXITINFO ExitInfo;
2802 RT_ZERO(ExitInfo);
2803 ExitInfo.uReason = VMX_EXIT_INVLPG;
2804 ExitInfo.cbInstr = cbInstr;
2805 ExitInfo.u64Qual = GCPtrPage;
2806 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2807
2808 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2809}
2810
2811
2812/**
2813 * VMX VM-exit handler for VM-exits due to LMSW.
2814 *
2815 * @returns Strict VBox status code.
2816 * @param pVCpu The cross context virtual CPU structure.
2817 * @param uGuestCr0 The current guest CR0.
2818 * @param pu16NewMsw The machine-status word specified in LMSW's source
2819 * operand. This will be updated depending on the VMX
2820 * guest/host CR0 mask if LMSW is not intercepted.
2821 * @param GCPtrEffDst The guest-linear address of the source operand in case
2822 * of a memory operand. For register operand, pass
2823 * NIL_RTGCPTR.
2824 * @param cbInstr The instruction length in bytes.
2825 */
2826IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2827 uint8_t cbInstr)
2828{
2829 Assert(pu16NewMsw);
2830
2831 uint16_t const uNewMsw = *pu16NewMsw;
2832 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2833 {
2834 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2835
2836 VMXVEXITINFO ExitInfo;
2837 RT_ZERO(ExitInfo);
2838 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2839 ExitInfo.cbInstr = cbInstr;
2840
2841 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2842 if (fMemOperand)
2843 {
2844 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2845 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2846 }
2847
2848 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2849 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2850 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2851 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2852
2853 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2854 }
2855
2856 /*
2857 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2858 * CR0 guest/host mask must be left unmodified.
2859 *
2860 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2861 */
2862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2863 Assert(pVmcs);
2864 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2865 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2866 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2867
2868 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2869}
2870
2871
2872/**
2873 * VMX VM-exit handler for VM-exits due to CLTS.
2874 *
2875 * @returns Strict VBox status code.
2876 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2877 * VM-exit but must not modify the guest CR0.TS bit.
2878 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2879 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2880 * CR0 fixed bits in VMX operation).
2881 * @param pVCpu The cross context virtual CPU structure.
2882 * @param cbInstr The instruction length in bytes.
2883 */
2884IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2885{
2886 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2887 Assert(pVmcs);
2888
2889 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2890 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2891
2892 /*
2893 * If CR0.TS is owned by the host:
2894 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2895 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2896 * CLTS instruction completes without clearing CR0.TS.
2897 *
2898 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2899 */
2900 if (fGstHostMask & X86_CR0_TS)
2901 {
2902 if (fReadShadow & X86_CR0_TS)
2903 {
2904 Log2(("clts: Guest intercept -> VM-exit\n"));
2905
2906 VMXVEXITINFO ExitInfo;
2907 RT_ZERO(ExitInfo);
2908 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2909 ExitInfo.cbInstr = cbInstr;
2910 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2911 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2912 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2913 }
2914
2915 return VINF_VMX_MODIFIES_BEHAVIOR;
2916 }
2917
2918 /*
2919 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2920 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2921 */
2922 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2923}
2924
2925
2926/**
2927 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2928 * (CR0/CR4 write).
2929 *
2930 * @returns Strict VBox status code.
2931 * @param pVCpu The cross context virtual CPU structure.
2932 * @param iCrReg The control register (either CR0 or CR4).
2933 * @param uGuestCrX The current guest CR0/CR4.
2934 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2935 * VM-exit is caused.
2936 * @param iGReg The general register from which the CR0/CR4 value is being
2937 * loaded.
2938 * @param cbInstr The instruction length in bytes.
2939 */
2940IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2941 uint8_t cbInstr)
2942{
2943 Assert(puNewCrX);
2944 Assert(iCrReg == 0 || iCrReg == 4);
2945 Assert(iGReg < X86_GREG_COUNT);
2946
2947 uint64_t const uNewCrX = *puNewCrX;
2948 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2949 {
2950 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2951
2952 VMXVEXITINFO ExitInfo;
2953 RT_ZERO(ExitInfo);
2954 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2955 ExitInfo.cbInstr = cbInstr;
2956 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2957 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2958 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2959 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2960 }
2961
2962 /*
2963 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2964 * must not be modified the instruction.
2965 *
2966 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2967 */
2968 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2969 Assert(pVmcs);
2970 uint64_t uGuestCrX;
2971 uint64_t fGstHostMask;
2972 if (iCrReg == 0)
2973 {
2974 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2975 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2976 fGstHostMask = pVmcs->u64Cr0Mask.u;
2977 }
2978 else
2979 {
2980 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2981 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2982 fGstHostMask = pVmcs->u64Cr4Mask.u;
2983 }
2984
2985 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2986 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2987}
2988
2989
2990/**
2991 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2992 *
2993 * @returns VBox strict status code.
2994 * @param pVCpu The cross context virtual CPU structure.
2995 * @param iGReg The general register to which the CR3 value is being stored.
2996 * @param cbInstr The instruction length in bytes.
2997 */
2998IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2999{
3000 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3001 Assert(pVmcs);
3002 Assert(iGReg < X86_GREG_COUNT);
3003 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3004
3005 /*
3006 * If the CR3-store exiting control is set, we must cause a VM-exit.
3007 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3008 */
3009 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3010 {
3011 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3012
3013 VMXVEXITINFO ExitInfo;
3014 RT_ZERO(ExitInfo);
3015 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3016 ExitInfo.cbInstr = cbInstr;
3017 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3018 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3020 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3021 }
3022
3023 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3024}
3025
3026
3027/**
3028 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3029 *
3030 * @returns VBox strict status code.
3031 * @param pVCpu The cross context virtual CPU structure.
3032 * @param uNewCr3 The new CR3 value.
3033 * @param iGReg The general register from which the CR3 value is being
3034 * loaded.
3035 * @param cbInstr The instruction length in bytes.
3036 */
3037IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3038{
3039 Assert(iGReg < X86_GREG_COUNT);
3040
3041 /*
3042 * If the CR3-load exiting control is set and the new CR3 value does not
3043 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3044 *
3045 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3046 */
3047 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3048 {
3049 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3050
3051 VMXVEXITINFO ExitInfo;
3052 RT_ZERO(ExitInfo);
3053 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3054 ExitInfo.cbInstr = cbInstr;
3055 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3056 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3058 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3059 }
3060
3061 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3062}
3063
3064
3065/**
3066 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3067 *
3068 * @returns VBox strict status code.
3069 * @param pVCpu The cross context virtual CPU structure.
3070 * @param iGReg The general register to which the CR8 value is being stored.
3071 * @param cbInstr The instruction length in bytes.
3072 */
3073IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3074{
3075 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3076 Assert(pVmcs);
3077 Assert(iGReg < X86_GREG_COUNT);
3078
3079 /*
3080 * If the CR8-store exiting control is set, we must cause a VM-exit.
3081 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3082 */
3083 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3084 {
3085 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3086
3087 VMXVEXITINFO ExitInfo;
3088 RT_ZERO(ExitInfo);
3089 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3090 ExitInfo.cbInstr = cbInstr;
3091 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096
3097 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3098}
3099
3100
3101/**
3102 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3103 *
3104 * @returns VBox strict status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 * @param iGReg The general register from which the CR8 value is being
3107 * loaded.
3108 * @param cbInstr The instruction length in bytes.
3109 */
3110IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3111{
3112 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3113 Assert(pVmcs);
3114 Assert(iGReg < X86_GREG_COUNT);
3115
3116 /*
3117 * If the CR8-load exiting control is set, we must cause a VM-exit.
3118 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3119 */
3120 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3121 {
3122 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3123
3124 VMXVEXITINFO ExitInfo;
3125 RT_ZERO(ExitInfo);
3126 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3127 ExitInfo.cbInstr = cbInstr;
3128 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3129 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3130 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3131 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3132 }
3133
3134 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3135}
3136
3137
3138/**
3139 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3140 * GReg,DRx' (DRx read).
3141 *
3142 * @returns VBox strict status code.
3143 * @param pVCpu The cross context virtual CPU structure.
3144 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3145 * VMXINSTRID_MOV_FROM_DRX).
3146 * @param iDrReg The debug register being accessed.
3147 * @param iGReg The general register to/from which the DRx value is being
3148 * store/loaded.
3149 * @param cbInstr The instruction length in bytes.
3150 */
3151IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3152 uint8_t cbInstr)
3153{
3154 Assert(iDrReg <= 7);
3155 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3156 Assert(iGReg < X86_GREG_COUNT);
3157
3158 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3159 Assert(pVmcs);
3160
3161 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3162 {
3163 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3164 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3165 VMXVEXITINFO ExitInfo;
3166 RT_ZERO(ExitInfo);
3167 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3168 ExitInfo.cbInstr = cbInstr;
3169 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3170 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3171 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3172 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3173 }
3174
3175 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3176}
3177
3178
3179/**
3180 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3181 *
3182 * @returns VBox strict status code.
3183 * @param pVCpu The cross context virtual CPU structure.
3184 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3185 * VMXINSTRID_IO_OUT).
3186 * @param u16Port The I/O port being accessed.
3187 * @param fImm Whether the I/O port was encoded using an immediate operand
3188 * or the implicit DX register.
3189 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3190 * @param cbInstr The instruction length in bytes.
3191 */
3192IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3193 uint8_t cbInstr)
3194{
3195 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3196 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3197
3198 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3199 if (fIntercept)
3200 {
3201 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3202 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3203 VMXVEXITINFO ExitInfo;
3204 RT_ZERO(ExitInfo);
3205 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3206 ExitInfo.cbInstr = cbInstr;
3207 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3208 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3209 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3210 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3211 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3212 }
3213
3214 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3215}
3216
3217
3218/**
3219 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3220 *
3221 * @returns VBox strict status code.
3222 * @param pVCpu The cross context virtual CPU structure.
3223 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3224 * VMXINSTRID_IO_OUTS).
3225 * @param u16Port The I/O port being accessed.
3226 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3227 * @param fRep Whether the instruction has a REP prefix or not.
3228 * @param ExitInstrInfo The VM-exit instruction info. field.
3229 * @param cbInstr The instruction length in bytes.
3230 */
3231IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3232 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3233{
3234 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3235 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3236 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3237 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3238 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3239
3240 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3241 if (fIntercept)
3242 {
3243 /*
3244 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3245 */
3246 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3247 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3248 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3249 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3250 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3251
3252 uint32_t uDirection;
3253 uint64_t uGuestLinearAddr;
3254 if (uInstrId == VMXINSTRID_IO_INS)
3255 {
3256 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3257 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3258 }
3259 else
3260 {
3261 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3262 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3263 }
3264
3265 /*
3266 * If the segment is unusable, the guest-linear address in undefined.
3267 * We shall clear it for consistency.
3268 *
3269 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3270 */
3271 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3272 uGuestLinearAddr = 0;
3273
3274 VMXVEXITINFO ExitInfo;
3275 RT_ZERO(ExitInfo);
3276 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3277 ExitInfo.cbInstr = cbInstr;
3278 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3279 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3280 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3284 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3285 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3286 ExitInfo.InstrInfo = ExitInstrInfo;
3287 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3288 }
3289
3290 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3291}
3292
3293
3294/**
3295 * VMX VM-exit handler for VM-exits due to MWAIT.
3296 *
3297 * @returns VBox strict status code.
3298 * @param pVCpu The cross context virtual CPU structure.
3299 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3300 * @param cbInstr The instruction length in bytes.
3301 */
3302IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3303{
3304 VMXVEXITINFO ExitInfo;
3305 RT_ZERO(ExitInfo);
3306 ExitInfo.uReason = VMX_EXIT_MWAIT;
3307 ExitInfo.cbInstr = cbInstr;
3308 ExitInfo.u64Qual = fMonitorHwArmed;
3309 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3310}
3311
3312
3313/**
3314 * VMX VM-exit handler for VM-exits due to PAUSE.
3315 *
3316 * @returns VBox strict status code.
3317 * @param pVCpu The cross context virtual CPU structure.
3318 * @param cbInstr The instruction length in bytes.
3319 */
3320IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3321{
3322 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3323 Assert(pVmcs);
3324
3325 /*
3326 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3327 * "PAUSE-loop exiting" control.
3328 *
3329 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3330 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3331 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3332 * a VM-exit.
3333 *
3334 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3335 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3336 */
3337 bool fIntercept = false;
3338 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3339 fIntercept = true;
3340 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3341 && pVCpu->iem.s.uCpl == 0)
3342 {
3343 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3344
3345 /*
3346 * A previous-PAUSE-tick value of 0 is used to identify the first time
3347 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3348 * consider this to be the first execution of PAUSE in a loop according
3349 * to the Intel.
3350 *
3351 * All subsequent records for the previous-PAUSE-tick we ensure that it
3352 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3353 */
3354 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3355 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3356 uint64_t const uTick = TMCpuTickGet(pVCpu);
3357 uint32_t const uPleGap = pVmcs->u32PleGap;
3358 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3359 if ( *puPrevPauseTick == 0
3360 || uTick - *puPrevPauseTick > uPleGap)
3361 *puFirstPauseLoopTick = uTick;
3362 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3363 fIntercept = true;
3364
3365 *puPrevPauseTick = uTick | 1;
3366 }
3367
3368 if (fIntercept)
3369 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3370
3371 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3372}
3373
3374
3375/**
3376 * VMX VM-exit handler for VM-exits due to task switches.
3377 *
3378 * @returns VBox strict status code.
3379 * @param pVCpu The cross context virtual CPU structure.
3380 * @param enmTaskSwitch The cause of the task switch.
3381 * @param SelNewTss The selector of the new TSS.
3382 * @param cbInstr The instruction length in bytes.
3383 */
3384IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3385{
3386 /*
3387 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3388 *
3389 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3390 * instruction or delivery of the exception generated by one of these instructions
3391 * lead to a task switch through a task gate in the IDT, we need to provide the
3392 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3393 * leaves the VM-exit instruction length field undefined.
3394 *
3395 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3396 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3397 */
3398 Assert(cbInstr <= 15);
3399
3400 uint8_t uType;
3401 switch (enmTaskSwitch)
3402 {
3403 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3404 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3405 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3406 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3407 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3408 }
3409
3410 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3411 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3412 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3413 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3414}
3415
3416
3417/**
3418 * VMX VM-exit handler for trap-like VM-exits.
3419 *
3420 * @returns VBox strict status code.
3421 * @param pVCpu The cross context virtual CPU structure.
3422 * @param pExitInfo Pointer to the VM-exit information.
3423 * @param pExitEventInfo Pointer to the VM-exit event information.
3424 */
3425IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3426{
3427 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3428 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3429 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3430}
3431
3432
3433/**
3434 * VMX VM-exit handler for VM-exits due to task switches.
3435 *
3436 * This is intended for task switches where the caller provides all the relevant
3437 * VM-exit information.
3438 *
3439 * @returns VBox strict status code.
3440 * @param pVCpu The cross context virtual CPU structure.
3441 * @param pExitInfo Pointer to the VM-exit information.
3442 * @param pExitEventInfo Pointer to the VM-exit event information.
3443 */
3444IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3445 PCVMXVEXITEVENTINFO pExitEventInfo)
3446{
3447 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3448 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3449 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3450 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3451 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3452}
3453
3454
3455/**
3456 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3457 *
3458 * @returns VBox strict status code.
3459 * @param pVCpu The cross context virtual CPU structure.
3460 */
3461IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3462{
3463 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3464 Assert(pVmcs);
3465
3466 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3467 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3468 {
3469 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3470 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3471
3472 /*
3473 * Calculate the current VMX-preemption timer value.
3474 * Only if the value has reached zero, we cause the VM-exit.
3475 */
3476 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3477 if (!uPreemptTimer)
3478 {
3479 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3480 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3481 pVmcs->u32PreemptTimer = 0;
3482
3483 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3484 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3485 }
3486 }
3487
3488 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3489}
3490
3491
3492/**
3493 * VMX VM-exit handler for VM-exits due to external interrupts.
3494 *
3495 * @returns VBox strict status code.
3496 * @param pVCpu The cross context virtual CPU structure.
3497 * @param uVector The external interrupt vector (pass 0 if the interrupt
3498 * is still pending since we typically won't know the
3499 * vector).
3500 * @param fIntPending Whether the external interrupt is pending or
3501 * acknowledged in the interrupt controller.
3502 */
3503IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3504{
3505 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3506 Assert(pVmcs);
3507 Assert(fIntPending || uVector == 0);
3508
3509 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3510 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3511 * functions require prior checking of a blanket intercept and which don't.
3512 * It is better for the caller to check a blanket intercept performance wise
3513 * than making a function call. Leaving this as a todo because it is more
3514 * a performance issue. */
3515
3516 /* The VM-exit is subject to "External interrupt exiting" being set. */
3517 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3518 {
3519 if (fIntPending)
3520 {
3521 /*
3522 * If the interrupt is pending and we don't need to acknowledge the
3523 * interrupt on VM-exit, cause the VM-exit immediately.
3524 *
3525 * See Intel spec 25.2 "Other Causes Of VM Exits".
3526 */
3527 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3528 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3529
3530 /*
3531 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3532 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3533 * acknowledged that the interrupt has been consumed.
3534 */
3535 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3536 }
3537
3538 /*
3539 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3540 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3541 * all set, we cause the VM-exit now. We need to record the external interrupt that
3542 * just occurred in the VM-exit interruption information field.
3543 *
3544 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3545 */
3546 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3547 {
3548 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3549 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3550 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3551 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3552 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3553 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3554 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3555 }
3556 }
3557
3558 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3559}
3560
3561
3562/**
3563 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3564 * an event.
3565 *
3566 * @returns VBox strict status code.
3567 * @param pVCpu The cross context virtual CPU structure.
3568 */
3569IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3570{
3571 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3572 Assert(pVmcs);
3573
3574 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3575 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3576 {
3577 /*
3578 * The NMI-unblocking due to IRET field need not be set for double faults.
3579 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3580 */
3581 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3582 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3583 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3584 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3585 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3586 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3587 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3588 }
3589
3590 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3591}
3592
3593
3594/**
3595 * VMX VM-exit handler for VM-exit due to delivery of an events.
3596 *
3597 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3598 * all the relevant VM-exit information.
3599 *
3600 * @returns VBox strict status code.
3601 * @param pVCpu The cross context virtual CPU structure.
3602 * @param pExitInfo Pointer to the VM-exit information.
3603 * @param pExitEventInfo Pointer to the VM-exit event information.
3604 */
3605IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3606{
3607 Assert(pExitInfo);
3608 Assert(pExitEventInfo);
3609 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3610 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3611
3612 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3613 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3614 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3615 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3616 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3617 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3618}
3619
3620
3621/**
3622 * VMX VM-exit handler for VM-exits due to delivery of an event.
3623 *
3624 * @returns VBox strict status code.
3625 * @param pVCpu The cross context virtual CPU structure.
3626 * @param uVector The interrupt / exception vector.
3627 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3628 * @param uErrCode The error code associated with the event.
3629 * @param uCr2 The CR2 value in case of a \#PF exception.
3630 * @param cbInstr The instruction length in bytes.
3631 */
3632IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3633 uint8_t cbInstr)
3634{
3635 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3636 Assert(pVmcs);
3637
3638 /*
3639 * If the event is being injected as part of VM-entry, it is -not- subject to event
3640 * intercepts in the nested-guest. However, secondary exceptions that occur during
3641 * injection of any event -are- subject to event interception.
3642 *
3643 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3644 */
3645 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3646 {
3647 /*
3648 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3649 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3650 *
3651 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3652 */
3653 if ( uVector == X86_XCPT_NMI
3654 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3655 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3656 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3657 else
3658 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3659
3660 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3661 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3662 }
3663
3664 /*
3665 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3666 * If not, the caller will continue delivery of the external interrupt as it would
3667 * normally. The interrupt is no longer pending in the interrupt controller at this
3668 * point.
3669 */
3670 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3671 {
3672 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3673 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3674 }
3675
3676 /*
3677 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3678 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3679 * interrupts.
3680 */
3681 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3682 bool fIntercept;
3683 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3684 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3685 {
3686 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3687 }
3688 else
3689 {
3690 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3691 fIntercept = false;
3692 }
3693
3694 /*
3695 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3696 * relevant VM-exit information and cause the VM-exit.
3697 */
3698 if (fIntercept)
3699 {
3700 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3701
3702 /* Construct the rest of the event related information fields and cause the VM-exit. */
3703 uint64_t u64ExitQual;
3704 if (uVector == X86_XCPT_PF)
3705 {
3706 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3707 u64ExitQual = uCr2;
3708 }
3709 else if (uVector == X86_XCPT_DB)
3710 {
3711 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3712 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3713 }
3714 else
3715 u64ExitQual = 0;
3716
3717 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3718 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3719 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3720 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3721 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3722 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3723 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3724 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3725 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3726 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3727
3728 /*
3729 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3730 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3731 * length.
3732 */
3733 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3734 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3735 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3736 else
3737 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3738
3739 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3740 }
3741
3742 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3743}
3744
3745
3746/**
3747 * VMX VM-exit handler for APIC accesses.
3748 *
3749 * @param pVCpu The cross context virtual CPU structure.
3750 * @param offAccess The offset of the register being accessed.
3751 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3752 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3753 */
3754IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3755{
3756 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3757
3758 VMXAPICACCESS enmAccess;
3759 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3760 if (fInEventDelivery)
3761 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3762 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3763 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3764 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3765 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3766 else
3767 enmAccess = VMXAPICACCESS_LINEAR_READ;
3768
3769 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3770 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3771 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3772}
3773
3774
3775/**
3776 * VMX VM-exit handler for APIC accesses.
3777 *
3778 * This is intended for APIC accesses where the caller provides all the
3779 * relevant VM-exit information.
3780 *
3781 * @returns VBox strict status code.
3782 * @param pVCpu The cross context virtual CPU structure.
3783 * @param pExitInfo Pointer to the VM-exit information.
3784 * @param pExitEventInfo Pointer to the VM-exit event information.
3785 */
3786IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3787 PCVMXVEXITEVENTINFO pExitEventInfo)
3788{
3789 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3790 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3791 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3792 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3793 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3794 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3795 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3796 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3797 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3798}
3799
3800
3801/**
3802 * VMX VM-exit handler for APIC-write VM-exits.
3803 *
3804 * @param pVCpu The cross context virtual CPU structure.
3805 * @param offApic The write to the virtual-APIC page offset that caused this
3806 * VM-exit.
3807 */
3808IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3809{
3810 Assert(offApic < XAPIC_OFF_END + 4);
3811 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3812 offApic &= UINT16_C(0xfff);
3813 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3814}
3815
3816
3817/**
3818 * Sets virtual-APIC write emulation as pending.
3819 *
3820 * @param pVCpu The cross context virtual CPU structure.
3821 * @param offApic The offset in the virtual-APIC page that was written.
3822 */
3823DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3824{
3825 Assert(offApic < XAPIC_OFF_END + 4);
3826
3827 /*
3828 * Record the currently updated APIC offset, as we need this later for figuring
3829 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3830 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3831 */
3832 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3833
3834 /*
3835 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3836 * virtualization or APIC-write emulation).
3837 */
3838 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3839 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3840}
3841
3842
3843/**
3844 * Clears any pending virtual-APIC write emulation.
3845 *
3846 * @returns The virtual-APIC offset that was written before clearing it.
3847 * @param pVCpu The cross context virtual CPU structure.
3848 */
3849DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3850{
3851 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3852 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3853 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3854 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3855 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3856 return offVirtApicWrite;
3857}
3858
3859
3860/**
3861 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3862 *
3863 * @returns The register from the virtual-APIC page.
3864 * @param pVCpu The cross context virtual CPU structure.
3865 * @param offReg The offset of the register being read.
3866 */
3867IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3868{
3869 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3870 Assert(pVmcs);
3871 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3872
3873 uint32_t uReg;
3874 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3875 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3876 if (RT_SUCCESS(rc))
3877 { /* likely */ }
3878 else
3879 {
3880 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3881 GCPhysVirtApic));
3882 uReg = 0;
3883 }
3884 return uReg;
3885}
3886
3887
3888/**
3889 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3890 *
3891 * @returns The register from the virtual-APIC page.
3892 * @param pVCpu The cross context virtual CPU structure.
3893 * @param offReg The offset of the register being read.
3894 */
3895IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3896{
3897 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3898 Assert(pVmcs);
3899 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3900
3901 uint64_t uReg;
3902 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3903 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3904 if (RT_SUCCESS(rc))
3905 { /* likely */ }
3906 else
3907 {
3908 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3909 GCPhysVirtApic));
3910 uReg = 0;
3911 }
3912 return uReg;
3913}
3914
3915
3916/**
3917 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3918 *
3919 * @param pVCpu The cross context virtual CPU structure.
3920 * @param offReg The offset of the register being written.
3921 * @param uReg The register value to write.
3922 */
3923IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3924{
3925 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3926 Assert(pVmcs);
3927 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3928
3929 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3930 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3931 if (RT_SUCCESS(rc))
3932 { /* likely */ }
3933 else
3934 {
3935 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3936 GCPhysVirtApic));
3937 }
3938}
3939
3940
3941/**
3942 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3943 *
3944 * @param pVCpu The cross context virtual CPU structure.
3945 * @param offReg The offset of the register being written.
3946 * @param uReg The register value to write.
3947 */
3948IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3949{
3950 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3951 Assert(pVmcs);
3952 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3953
3954 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3955 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3956 if (RT_SUCCESS(rc))
3957 { /* likely */ }
3958 else
3959 {
3960 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3961 GCPhysVirtApic));
3962 }
3963}
3964
3965
3966/**
3967 * Sets the vector in a virtual-APIC 256-bit sparse register.
3968 *
3969 * @param pVCpu The cross context virtual CPU structure.
3970 * @param offReg The offset of the 256-bit spare register.
3971 * @param uVector The vector to set.
3972 *
3973 * @remarks This is based on our APIC device code.
3974 */
3975IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3976{
3977 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3978 Assert(pVmcs);
3979
3980 /* Determine the vector offset within the chunk. */
3981 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3982
3983 /* Read the chunk at the offset. */
3984 uint32_t uReg;
3985 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3986 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3987 if (RT_SUCCESS(rc))
3988 {
3989 /* Modify the chunk. */
3990 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3991 uReg |= RT_BIT(idxVectorBit);
3992
3993 /* Write the chunk. */
3994 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3995 if (RT_SUCCESS(rc))
3996 { /* likely */ }
3997 else
3998 {
3999 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4000 uVector, offReg, GCPhysVirtApic));
4001 }
4002 }
4003 else
4004 {
4005 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4006 uVector, offReg, GCPhysVirtApic));
4007 }
4008}
4009
4010
4011/**
4012 * Clears the vector in a virtual-APIC 256-bit sparse register.
4013 *
4014 * @param pVCpu The cross context virtual CPU structure.
4015 * @param offReg The offset of the 256-bit spare register.
4016 * @param uVector The vector to clear.
4017 *
4018 * @remarks This is based on our APIC device code.
4019 */
4020IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4021{
4022 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4023 Assert(pVmcs);
4024
4025 /* Determine the vector offset within the chunk. */
4026 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4027
4028 /* Read the chunk at the offset. */
4029 uint32_t uReg;
4030 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4031 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4032 if (RT_SUCCESS(rc))
4033 {
4034 /* Modify the chunk. */
4035 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4036 uReg &= ~RT_BIT(idxVectorBit);
4037
4038 /* Write the chunk. */
4039 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4040 if (RT_SUCCESS(rc))
4041 { /* likely */ }
4042 else
4043 {
4044 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4045 uVector, offReg, GCPhysVirtApic));
4046 }
4047 }
4048 else
4049 {
4050 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4051 uVector, offReg, GCPhysVirtApic));
4052 }
4053}
4054
4055
4056/**
4057 * Checks if a memory access to the APIC-access page must causes an APIC-access
4058 * VM-exit.
4059 *
4060 * @param pVCpu The cross context virtual CPU structure.
4061 * @param offAccess The offset of the register being accessed.
4062 * @param cbAccess The size of the access in bytes.
4063 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4064 * IEM_ACCESS_TYPE_WRITE).
4065 *
4066 * @remarks This must not be used for MSR-based APIC-access page accesses!
4067 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4068 */
4069IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4070{
4071 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4072 Assert(pVmcs);
4073 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4074
4075 /*
4076 * We must cause a VM-exit if any of the following are true:
4077 * - TPR shadowing isn't active.
4078 * - The access size exceeds 32-bits.
4079 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4080 *
4081 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4082 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4083 */
4084 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4085 || cbAccess > sizeof(uint32_t)
4086 || ((offAccess + cbAccess - 1) & 0xc)
4087 || offAccess >= XAPIC_OFF_END + 4)
4088 return true;
4089
4090 /*
4091 * If the access is part of an operation where we have already
4092 * virtualized a virtual-APIC write, we must cause a VM-exit.
4093 */
4094 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4095 return true;
4096
4097 /*
4098 * Check write accesses to the APIC-access page that cause VM-exits.
4099 */
4100 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4101 {
4102 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4103 {
4104 /*
4105 * With APIC-register virtualization, a write access to any of the
4106 * following registers are virtualized. Accessing any other register
4107 * causes a VM-exit.
4108 */
4109 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4110 switch (offAlignedAccess)
4111 {
4112 case XAPIC_OFF_ID:
4113 case XAPIC_OFF_TPR:
4114 case XAPIC_OFF_EOI:
4115 case XAPIC_OFF_LDR:
4116 case XAPIC_OFF_DFR:
4117 case XAPIC_OFF_SVR:
4118 case XAPIC_OFF_ESR:
4119 case XAPIC_OFF_ICR_LO:
4120 case XAPIC_OFF_ICR_HI:
4121 case XAPIC_OFF_LVT_TIMER:
4122 case XAPIC_OFF_LVT_THERMAL:
4123 case XAPIC_OFF_LVT_PERF:
4124 case XAPIC_OFF_LVT_LINT0:
4125 case XAPIC_OFF_LVT_LINT1:
4126 case XAPIC_OFF_LVT_ERROR:
4127 case XAPIC_OFF_TIMER_ICR:
4128 case XAPIC_OFF_TIMER_DCR:
4129 break;
4130 default:
4131 return true;
4132 }
4133 }
4134 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4135 {
4136 /*
4137 * With virtual-interrupt delivery, a write access to any of the
4138 * following registers are virtualized. Accessing any other register
4139 * causes a VM-exit.
4140 *
4141 * Note! The specification does not allow writing to offsets in-between
4142 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4143 */
4144 switch (offAccess)
4145 {
4146 case XAPIC_OFF_TPR:
4147 case XAPIC_OFF_EOI:
4148 case XAPIC_OFF_ICR_LO:
4149 break;
4150 default:
4151 return true;
4152 }
4153 }
4154 else
4155 {
4156 /*
4157 * Without APIC-register virtualization or virtual-interrupt delivery,
4158 * only TPR accesses are virtualized.
4159 */
4160 if (offAccess == XAPIC_OFF_TPR)
4161 { /* likely */ }
4162 else
4163 return true;
4164 }
4165 }
4166 else
4167 {
4168 /*
4169 * Check read accesses to the APIC-access page that cause VM-exits.
4170 */
4171 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4172 {
4173 /*
4174 * With APIC-register virtualization, a read access to any of the
4175 * following registers are virtualized. Accessing any other register
4176 * causes a VM-exit.
4177 */
4178 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4179 switch (offAlignedAccess)
4180 {
4181 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4182 case XAPIC_OFF_ID:
4183 case XAPIC_OFF_VERSION:
4184 case XAPIC_OFF_TPR:
4185 case XAPIC_OFF_EOI:
4186 case XAPIC_OFF_LDR:
4187 case XAPIC_OFF_DFR:
4188 case XAPIC_OFF_SVR:
4189 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4190 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4191 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4192 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4193 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4194 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4195 case XAPIC_OFF_ESR:
4196 case XAPIC_OFF_ICR_LO:
4197 case XAPIC_OFF_ICR_HI:
4198 case XAPIC_OFF_LVT_TIMER:
4199 case XAPIC_OFF_LVT_THERMAL:
4200 case XAPIC_OFF_LVT_PERF:
4201 case XAPIC_OFF_LVT_LINT0:
4202 case XAPIC_OFF_LVT_LINT1:
4203 case XAPIC_OFF_LVT_ERROR:
4204 case XAPIC_OFF_TIMER_ICR:
4205 case XAPIC_OFF_TIMER_DCR:
4206 break;
4207 default:
4208 return true;
4209 }
4210 }
4211 else
4212 {
4213 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4214 if (offAccess == XAPIC_OFF_TPR)
4215 { /* likely */ }
4216 else
4217 return true;
4218 }
4219 }
4220
4221 /* The APIC access is virtualized, does not cause a VM-exit. */
4222 return false;
4223}
4224
4225
4226/**
4227 * Virtualizes a memory-based APIC access where the address is not used to access
4228 * memory.
4229 *
4230 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4231 * page-faults but do not use the address to access memory.
4232 *
4233 * @param pVCpu The cross context virtual CPU structure.
4234 * @param pGCPhysAccess Pointer to the guest-physical address used.
4235 */
4236IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4237{
4238 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4239 Assert(pVmcs);
4240 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4241 Assert(pGCPhysAccess);
4242
4243 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4244 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4245 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4246
4247 if (GCPhysAccess == GCPhysApic)
4248 {
4249 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4250 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4251 uint16_t const cbAccess = 1;
4252 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4253 if (fIntercept)
4254 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4255
4256 *pGCPhysAccess = GCPhysApic | offAccess;
4257 return VINF_VMX_MODIFIES_BEHAVIOR;
4258 }
4259
4260 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4261}
4262
4263
4264/**
4265 * Virtualizes a memory-based APIC access.
4266 *
4267 * @returns VBox strict status code.
4268 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4269 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4270 *
4271 * @param pVCpu The cross context virtual CPU structure.
4272 * @param offAccess The offset of the register being accessed (within the
4273 * APIC-access page).
4274 * @param cbAccess The size of the access in bytes.
4275 * @param pvData Pointer to the data being written or where to store the data
4276 * being read.
4277 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4278 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4279 */
4280IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4281 uint32_t fAccess)
4282{
4283 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4284 Assert(pVmcs);
4285 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4286 Assert(pvData);
4287 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4288 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4289 || (fAccess & IEM_ACCESS_INSTRUCTION));
4290
4291 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4292 if (fIntercept)
4293 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4294
4295 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4296 {
4297 /*
4298 * A write access to the APIC-access page that is virtualized (rather than
4299 * causing a VM-exit) writes data to the virtual-APIC page.
4300 */
4301 uint32_t const u32Data = *(uint32_t *)pvData;
4302 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4303
4304 /*
4305 * Record the currently updated APIC offset, as we need this later for figuring
4306 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4307 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4308 *
4309 * After completion of the current operation, we need to perform TPR virtualization,
4310 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4311 *
4312 * The current operation may be a REP-prefixed string instruction, execution of any
4313 * other instruction, or delivery of an event through the IDT.
4314 *
4315 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4316 * performed now but later after completion of the current operation.
4317 *
4318 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4319 */
4320 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4321 }
4322 else
4323 {
4324 /*
4325 * A read access from the APIC-access page that is virtualized (rather than
4326 * causing a VM-exit) returns data from the virtual-APIC page.
4327 *
4328 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4329 */
4330 Assert(cbAccess <= 4);
4331 Assert(offAccess < XAPIC_OFF_END + 4);
4332 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4333
4334 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4335 u32Data &= s_auAccessSizeMasks[cbAccess];
4336 *(uint32_t *)pvData = u32Data;
4337 }
4338
4339 return VINF_VMX_MODIFIES_BEHAVIOR;
4340}
4341
4342
4343/**
4344 * Virtualizes an MSR-based APIC read access.
4345 *
4346 * @returns VBox strict status code.
4347 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4348 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4349 * handled by the x2APIC device.
4350 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4351 * not within the range of valid MSRs, caller must raise \#GP(0).
4352 * @param pVCpu The cross context virtual CPU structure.
4353 * @param idMsr The x2APIC MSR being read.
4354 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4355 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4356 */
4357IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4358{
4359 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4360 Assert(pVmcs);
4361 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4362 Assert(pu64Value);
4363
4364 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4365 {
4366 /*
4367 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4368 * what the end of the valid x2APIC MSR range is. Hence the use of different
4369 * macros here.
4370 *
4371 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4372 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4373 */
4374 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4375 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4376 {
4377 uint16_t const offReg = (idMsr & 0xff) << 4;
4378 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4379 *pu64Value = u64Value;
4380 return VINF_VMX_MODIFIES_BEHAVIOR;
4381 }
4382 return VERR_OUT_OF_RANGE;
4383 }
4384
4385 if (idMsr == MSR_IA32_X2APIC_TPR)
4386 {
4387 uint16_t const offReg = (idMsr & 0xff) << 4;
4388 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4389 *pu64Value = u64Value;
4390 return VINF_VMX_MODIFIES_BEHAVIOR;
4391 }
4392
4393 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4394}
4395
4396
4397/**
4398 * Virtualizes an MSR-based APIC write access.
4399 *
4400 * @returns VBox strict status code.
4401 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4402 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4403 * not within the range of valid MSRs, caller must raise \#GP(0).
4404 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4405 *
4406 * @param pVCpu The cross context virtual CPU structure.
4407 * @param idMsr The x2APIC MSR being written.
4408 * @param u64Value The value of the x2APIC MSR being written.
4409 */
4410IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4411{
4412 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4413 Assert(pVmcs);
4414
4415 /*
4416 * Check if the access is to be virtualized.
4417 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4418 */
4419 if ( idMsr == MSR_IA32_X2APIC_TPR
4420 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4421 && ( idMsr == MSR_IA32_X2APIC_EOI
4422 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4423 {
4424 /* Validate the MSR write depending on the register. */
4425 switch (idMsr)
4426 {
4427 case MSR_IA32_X2APIC_TPR:
4428 case MSR_IA32_X2APIC_SELF_IPI:
4429 {
4430 if (u64Value & UINT64_C(0xffffffffffffff00))
4431 return VERR_OUT_OF_RANGE;
4432 break;
4433 }
4434 case MSR_IA32_X2APIC_EOI:
4435 {
4436 if (u64Value != 0)
4437 return VERR_OUT_OF_RANGE;
4438 break;
4439 }
4440 }
4441
4442 /* Write the MSR to the virtual-APIC page. */
4443 uint16_t const offReg = (idMsr & 0xff) << 4;
4444 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4445
4446 /*
4447 * Record the currently updated APIC offset, as we need this later for figuring
4448 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4449 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4450 */
4451 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4452
4453 return VINF_VMX_MODIFIES_BEHAVIOR;
4454 }
4455
4456 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4457}
4458
4459
4460/**
4461 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4462 *
4463 * @returns VBox status code.
4464 * @retval VINF_SUCCESS when the highest set bit is found.
4465 * @retval VERR_NOT_FOUND when no bit is set.
4466 *
4467 * @param pVCpu The cross context virtual CPU structure.
4468 * @param offReg The offset of the APIC 256-bit sparse register.
4469 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4470 * set in the register. Only valid when VINF_SUCCESS is
4471 * returned.
4472 *
4473 * @remarks The format of the 256-bit sparse register here mirrors that found in
4474 * real APIC hardware.
4475 */
4476static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4477{
4478 Assert(offReg < XAPIC_OFF_END + 4);
4479 Assert(pidxHighestBit);
4480 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4481
4482 /*
4483 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4484 * However, in each fragment only the first 4 bytes are used.
4485 */
4486 uint8_t const cFrags = 8;
4487 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4488 {
4489 uint16_t const offFrag = iFrag * 16;
4490 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4491 if (!u32Frag)
4492 continue;
4493
4494 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4495 Assert(idxHighestBit > 0);
4496 --idxHighestBit;
4497 Assert(idxHighestBit <= UINT8_MAX);
4498 *pidxHighestBit = idxHighestBit;
4499 return VINF_SUCCESS;
4500 }
4501 return VERR_NOT_FOUND;
4502}
4503
4504
4505/**
4506 * Evaluates pending virtual interrupts.
4507 *
4508 * @param pVCpu The cross context virtual CPU structure.
4509 */
4510IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4511{
4512 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4513 Assert(pVmcs);
4514 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4515
4516 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4517 {
4518 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4519 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4520
4521 if ((uRvi >> 4) > (uPpr >> 4))
4522 {
4523 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4524 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4525 }
4526 else
4527 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4528 }
4529}
4530
4531
4532/**
4533 * Performs PPR virtualization.
4534 *
4535 * @returns VBox strict status code.
4536 * @param pVCpu The cross context virtual CPU structure.
4537 */
4538IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4539{
4540 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4541 Assert(pVmcs);
4542 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4543 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4544
4545 /*
4546 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4547 * or EOI-virtualization.
4548 *
4549 * See Intel spec. 29.1.3 "PPR Virtualization".
4550 */
4551 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4552 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4553
4554 uint32_t uPpr;
4555 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4556 uPpr = uTpr & 0xff;
4557 else
4558 uPpr = uSvi & 0xf0;
4559
4560 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4561 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4562}
4563
4564
4565/**
4566 * Performs VMX TPR virtualization.
4567 *
4568 * @returns VBox strict status code.
4569 * @param pVCpu The cross context virtual CPU structure.
4570 */
4571IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4572{
4573 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4574 Assert(pVmcs);
4575 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4576
4577 /*
4578 * We should have already performed the virtual-APIC write to the TPR offset
4579 * in the virtual-APIC page. We now perform TPR virtualization.
4580 *
4581 * See Intel spec. 29.1.2 "TPR Virtualization".
4582 */
4583 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4584 {
4585 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4586 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4587
4588 /*
4589 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4590 * See Intel spec. 29.1.2 "TPR Virtualization".
4591 */
4592 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4593 {
4594 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4595 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4596 }
4597 }
4598 else
4599 {
4600 iemVmxPprVirtualization(pVCpu);
4601 iemVmxEvalPendingVirtIntrs(pVCpu);
4602 }
4603
4604 return VINF_SUCCESS;
4605}
4606
4607
4608/**
4609 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4610 * not.
4611 *
4612 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4613 * @param pVCpu The cross context virtual CPU structure.
4614 * @param uVector The interrupt that was acknowledged using an EOI.
4615 */
4616IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4617{
4618 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4619 Assert(pVmcs);
4620 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4621
4622 if (uVector < 64)
4623 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4624 if (uVector < 128)
4625 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4626 if (uVector < 192)
4627 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4628 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4629}
4630
4631
4632/**
4633 * Performs EOI virtualization.
4634 *
4635 * @returns VBox strict status code.
4636 * @param pVCpu The cross context virtual CPU structure.
4637 */
4638IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4639{
4640 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4641 Assert(pVmcs);
4642 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4643
4644 /*
4645 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4646 * and get the next guest-interrupt that's in-service (if any).
4647 *
4648 * See Intel spec. 29.1.4 "EOI Virtualization".
4649 */
4650 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4651 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4652 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4653
4654 uint8_t uVector = uSvi;
4655 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4656
4657 uVector = 0;
4658 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4659
4660 if (uVector)
4661 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4662 else
4663 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4664
4665 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4666 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4667
4668 iemVmxPprVirtualization(pVCpu);
4669 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4670 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4671 iemVmxEvalPendingVirtIntrs(pVCpu);
4672 return VINF_SUCCESS;
4673}
4674
4675
4676/**
4677 * Performs self-IPI virtualization.
4678 *
4679 * @returns VBox strict status code.
4680 * @param pVCpu The cross context virtual CPU structure.
4681 */
4682IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4683{
4684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4685 Assert(pVmcs);
4686 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4687
4688 /*
4689 * We should have already performed the virtual-APIC write to the self-IPI offset
4690 * in the virtual-APIC page. We now perform self-IPI virtualization.
4691 *
4692 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4693 */
4694 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4695 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4696 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4697 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4698 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4699 if (uVector > uRvi)
4700 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4701 iemVmxEvalPendingVirtIntrs(pVCpu);
4702 return VINF_SUCCESS;
4703}
4704
4705
4706/**
4707 * Performs VMX APIC-write emulation.
4708 *
4709 * @returns VBox strict status code.
4710 * @param pVCpu The cross context virtual CPU structure.
4711 */
4712IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4713{
4714 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4715 Assert(pVmcs);
4716
4717 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4718 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4719
4720 /*
4721 * Perform APIC-write emulation based on the virtual-APIC register written.
4722 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4723 */
4724 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4725 VBOXSTRICTRC rcStrict;
4726 switch (offApicWrite)
4727 {
4728 case XAPIC_OFF_TPR:
4729 {
4730 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4731 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4732 uTpr &= UINT32_C(0x000000ff);
4733 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4734 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4735 rcStrict = iemVmxTprVirtualization(pVCpu);
4736 break;
4737 }
4738
4739 case XAPIC_OFF_EOI:
4740 {
4741 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4742 {
4743 /* Clear VEOI and perform EOI virtualization. */
4744 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4745 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4746 rcStrict = iemVmxEoiVirtualization(pVCpu);
4747 }
4748 else
4749 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4750 break;
4751 }
4752
4753 case XAPIC_OFF_ICR_LO:
4754 {
4755 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4756 {
4757 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4758 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4759 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4760 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4761 if ( !(uIcrLo & fIcrLoMb0)
4762 && (uIcrLo & fIcrLoMb1))
4763 {
4764 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4765 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4766 }
4767 else
4768 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4769 }
4770 else
4771 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4772 break;
4773 }
4774
4775 case XAPIC_OFF_ICR_HI:
4776 {
4777 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4778 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4779 uIcrHi &= UINT32_C(0xff000000);
4780 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4781 rcStrict = VINF_SUCCESS;
4782 break;
4783 }
4784
4785 default:
4786 {
4787 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4788 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4789 break;
4790 }
4791 }
4792
4793 return rcStrict;
4794}
4795
4796
4797/**
4798 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4799 *
4800 * @param pVCpu The cross context virtual CPU structure.
4801 * @param pszInstr The VMX instruction name (for logging purposes).
4802 */
4803IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4804{
4805 /*
4806 * Guest Control Registers, Debug Registers, and MSRs.
4807 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4808 */
4809 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4810 const char *const pszFailure = "VM-exit";
4811 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4812
4813 /* CR0 reserved bits. */
4814 {
4815 /* CR0 MB1 bits. */
4816 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4817 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4818 if (fUnrestrictedGuest)
4819 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4820 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4821 { /* likely */ }
4822 else
4823 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4824
4825 /* CR0 MBZ bits. */
4826 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4827 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4828 { /* likely */ }
4829 else
4830 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4831
4832 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4833 if ( !fUnrestrictedGuest
4834 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4835 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4837 }
4838
4839 /* CR4 reserved bits. */
4840 {
4841 /* CR4 MB1 bits. */
4842 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4843 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4844 { /* likely */ }
4845 else
4846 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4847
4848 /* CR4 MBZ bits. */
4849 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4850 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4851 { /* likely */ }
4852 else
4853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4854 }
4855
4856 /* DEBUGCTL MSR. */
4857 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4858 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4859 { /* likely */ }
4860 else
4861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4862
4863 /* 64-bit CPU checks. */
4864 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4865 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4866 {
4867 if (fGstInLongMode)
4868 {
4869 /* PAE must be set. */
4870 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4871 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4872 { /* likely */ }
4873 else
4874 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4875 }
4876 else
4877 {
4878 /* PCIDE should not be set. */
4879 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4880 { /* likely */ }
4881 else
4882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4883 }
4884
4885 /* CR3. */
4886 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4887 { /* likely */ }
4888 else
4889 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4890
4891 /* DR7. */
4892 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4893 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4894 { /* likely */ }
4895 else
4896 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4897
4898 /* SYSENTER ESP and SYSENTER EIP. */
4899 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4900 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4901 { /* likely */ }
4902 else
4903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4904 }
4905
4906 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4907 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4908
4909 /* PAT MSR. */
4910 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4911 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4912 { /* likely */ }
4913 else
4914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4915
4916 /* EFER MSR. */
4917 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4918 {
4919 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4920 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4921 { /* likely */ }
4922 else
4923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4924
4925 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4926 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4927 if ( fGstLma == fGstInLongMode
4928 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4929 || fGstLma == fGstLme))
4930 { /* likely */ }
4931 else
4932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4933 }
4934
4935 /* We don't support IA32_BNDCFGS MSR yet. */
4936 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4937
4938 NOREF(pszInstr);
4939 NOREF(pszFailure);
4940 return VINF_SUCCESS;
4941}
4942
4943
4944/**
4945 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4946 *
4947 * @param pVCpu The cross context virtual CPU structure.
4948 * @param pszInstr The VMX instruction name (for logging purposes).
4949 */
4950IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4951{
4952 /*
4953 * Segment registers.
4954 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4955 */
4956 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4957 const char *const pszFailure = "VM-exit";
4958 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4959 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4960 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4961
4962 /* Selectors. */
4963 if ( !fGstInV86Mode
4964 && !fUnrestrictedGuest
4965 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4966 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4967
4968 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4969 {
4970 CPUMSELREG SelReg;
4971 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4972 if (RT_LIKELY(rc == VINF_SUCCESS))
4973 { /* likely */ }
4974 else
4975 return rc;
4976
4977 /*
4978 * Virtual-8086 mode checks.
4979 */
4980 if (fGstInV86Mode)
4981 {
4982 /* Base address. */
4983 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4984 { /* likely */ }
4985 else
4986 {
4987 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4989 }
4990
4991 /* Limit. */
4992 if (SelReg.u32Limit == 0xffff)
4993 { /* likely */ }
4994 else
4995 {
4996 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4997 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4998 }
4999
5000 /* Attribute. */
5001 if (SelReg.Attr.u == 0xf3)
5002 { /* likely */ }
5003 else
5004 {
5005 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5007 }
5008
5009 /* We're done; move to checking the next segment. */
5010 continue;
5011 }
5012
5013 /* Checks done by 64-bit CPUs. */
5014 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5015 {
5016 /* Base address. */
5017 if ( iSegReg == X86_SREG_FS
5018 || iSegReg == X86_SREG_GS)
5019 {
5020 if (X86_IS_CANONICAL(SelReg.u64Base))
5021 { /* likely */ }
5022 else
5023 {
5024 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5026 }
5027 }
5028 else if (iSegReg == X86_SREG_CS)
5029 {
5030 if (!RT_HI_U32(SelReg.u64Base))
5031 { /* likely */ }
5032 else
5033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5034 }
5035 else
5036 {
5037 if ( SelReg.Attr.n.u1Unusable
5038 || !RT_HI_U32(SelReg.u64Base))
5039 { /* likely */ }
5040 else
5041 {
5042 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5044 }
5045 }
5046 }
5047
5048 /*
5049 * Checks outside Virtual-8086 mode.
5050 */
5051 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5052 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5053 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5054 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5055 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5056 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5057 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5058 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5059
5060 /* Code or usable segment. */
5061 if ( iSegReg == X86_SREG_CS
5062 || fUsable)
5063 {
5064 /* Reserved bits (bits 31:17 and bits 11:8). */
5065 if (!(SelReg.Attr.u & 0xfffe0f00))
5066 { /* likely */ }
5067 else
5068 {
5069 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5070 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5071 }
5072
5073 /* Descriptor type. */
5074 if (fCodeDataSeg)
5075 { /* likely */ }
5076 else
5077 {
5078 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5080 }
5081
5082 /* Present. */
5083 if (fPresent)
5084 { /* likely */ }
5085 else
5086 {
5087 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5088 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5089 }
5090
5091 /* Granularity. */
5092 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5093 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5094 { /* likely */ }
5095 else
5096 {
5097 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5099 }
5100 }
5101
5102 if (iSegReg == X86_SREG_CS)
5103 {
5104 /* Segment Type and DPL. */
5105 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5106 && fUnrestrictedGuest)
5107 {
5108 if (uDpl == 0)
5109 { /* likely */ }
5110 else
5111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5112 }
5113 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5114 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5115 {
5116 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5117 if (uDpl == AttrSs.n.u2Dpl)
5118 { /* likely */ }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5121 }
5122 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5123 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5124 {
5125 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5126 if (uDpl <= AttrSs.n.u2Dpl)
5127 { /* likely */ }
5128 else
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5130 }
5131 else
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5133
5134 /* Def/Big. */
5135 if ( fGstInLongMode
5136 && fSegLong)
5137 {
5138 if (uDefBig == 0)
5139 { /* likely */ }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5142 }
5143 }
5144 else if (iSegReg == X86_SREG_SS)
5145 {
5146 /* Segment Type. */
5147 if ( !fUsable
5148 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5149 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5153
5154 /* DPL. */
5155 if (!fUnrestrictedGuest)
5156 {
5157 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5158 { /* likely */ }
5159 else
5160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5161 }
5162 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5163 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5164 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5165 {
5166 if (uDpl == 0)
5167 { /* likely */ }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5170 }
5171 }
5172 else
5173 {
5174 /* DS, ES, FS, GS. */
5175 if (fUsable)
5176 {
5177 /* Segment type. */
5178 if (uSegType & X86_SEL_TYPE_ACCESSED)
5179 { /* likely */ }
5180 else
5181 {
5182 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5184 }
5185
5186 if ( !(uSegType & X86_SEL_TYPE_CODE)
5187 || (uSegType & X86_SEL_TYPE_READ))
5188 { /* likely */ }
5189 else
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5191
5192 /* DPL. */
5193 if ( !fUnrestrictedGuest
5194 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5195 {
5196 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5197 { /* likely */ }
5198 else
5199 {
5200 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5202 }
5203 }
5204 }
5205 }
5206 }
5207
5208 /*
5209 * LDTR.
5210 */
5211 {
5212 CPUMSELREG Ldtr;
5213 Ldtr.Sel = pVmcs->GuestLdtr;
5214 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5215 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5216 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5217
5218 if (!Ldtr.Attr.n.u1Unusable)
5219 {
5220 /* Selector. */
5221 if (!(Ldtr.Sel & X86_SEL_LDT))
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5225
5226 /* Base. */
5227 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5228 {
5229 if (X86_IS_CANONICAL(Ldtr.u64Base))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5233 }
5234
5235 /* Attributes. */
5236 /* Reserved bits (bits 31:17 and bits 11:8). */
5237 if (!(Ldtr.Attr.u & 0xfffe0f00))
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5241
5242 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5243 { /* likely */ }
5244 else
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5246
5247 if (!Ldtr.Attr.n.u1DescType)
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5251
5252 if (Ldtr.Attr.n.u1Present)
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5256
5257 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5258 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5262 }
5263 }
5264
5265 /*
5266 * TR.
5267 */
5268 {
5269 CPUMSELREG Tr;
5270 Tr.Sel = pVmcs->GuestTr;
5271 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5272 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5273 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5274
5275 /* Selector. */
5276 if (!(Tr.Sel & X86_SEL_LDT))
5277 { /* likely */ }
5278 else
5279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5280
5281 /* Base. */
5282 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5283 {
5284 if (X86_IS_CANONICAL(Tr.u64Base))
5285 { /* likely */ }
5286 else
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5288 }
5289
5290 /* Attributes. */
5291 /* Reserved bits (bits 31:17 and bits 11:8). */
5292 if (!(Tr.Attr.u & 0xfffe0f00))
5293 { /* likely */ }
5294 else
5295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5296
5297 if (!Tr.Attr.n.u1Unusable)
5298 { /* likely */ }
5299 else
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5301
5302 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5303 || ( !fGstInLongMode
5304 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5305 { /* likely */ }
5306 else
5307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5308
5309 if (!Tr.Attr.n.u1DescType)
5310 { /* likely */ }
5311 else
5312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5313
5314 if (Tr.Attr.n.u1Present)
5315 { /* likely */ }
5316 else
5317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5318
5319 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5320 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5321 { /* likely */ }
5322 else
5323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5324 }
5325
5326 NOREF(pszInstr);
5327 NOREF(pszFailure);
5328 return VINF_SUCCESS;
5329}
5330
5331
5332/**
5333 * Checks guest GDTR and IDTR as part of VM-entry.
5334 *
5335 * @param pVCpu The cross context virtual CPU structure.
5336 * @param pszInstr The VMX instruction name (for logging purposes).
5337 */
5338IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5339{
5340 /*
5341 * GDTR and IDTR.
5342 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5343 */
5344 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5345 const char *const pszFailure = "VM-exit";
5346
5347 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5348 {
5349 /* Base. */
5350 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5351 { /* likely */ }
5352 else
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5354
5355 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5356 { /* likely */ }
5357 else
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5359 }
5360
5361 /* Limit. */
5362 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5363 { /* likely */ }
5364 else
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5366
5367 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5371
5372 NOREF(pszInstr);
5373 NOREF(pszFailure);
5374 return VINF_SUCCESS;
5375}
5376
5377
5378/**
5379 * Checks guest RIP and RFLAGS as part of VM-entry.
5380 *
5381 * @param pVCpu The cross context virtual CPU structure.
5382 * @param pszInstr The VMX instruction name (for logging purposes).
5383 */
5384IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5385{
5386 /*
5387 * RIP and RFLAGS.
5388 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5389 */
5390 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5391 const char *const pszFailure = "VM-exit";
5392 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5393
5394 /* RIP. */
5395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5396 {
5397 X86DESCATTR AttrCs;
5398 AttrCs.u = pVmcs->u32GuestCsAttr;
5399 if ( !fGstInLongMode
5400 || !AttrCs.n.u1Long)
5401 {
5402 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5403 { /* likely */ }
5404 else
5405 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5406 }
5407
5408 if ( fGstInLongMode
5409 && AttrCs.n.u1Long)
5410 {
5411 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5412 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5413 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5414 { /* likely */ }
5415 else
5416 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5417 }
5418 }
5419
5420 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5421 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5422 : pVmcs->u64GuestRFlags.s.Lo;
5423 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5424 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5425 { /* likely */ }
5426 else
5427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5428
5429 if ( fGstInLongMode
5430 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5431 {
5432 if (!(uGuestRFlags & X86_EFL_VM))
5433 { /* likely */ }
5434 else
5435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5436 }
5437
5438 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5439 {
5440 if (uGuestRFlags & X86_EFL_IF)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5444 }
5445
5446 NOREF(pszInstr);
5447 NOREF(pszFailure);
5448 return VINF_SUCCESS;
5449}
5450
5451
5452/**
5453 * Checks guest non-register state as part of VM-entry.
5454 *
5455 * @param pVCpu The cross context virtual CPU structure.
5456 * @param pszInstr The VMX instruction name (for logging purposes).
5457 */
5458IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5459{
5460 /*
5461 * Guest non-register state.
5462 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5463 */
5464 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5465 const char *const pszFailure = "VM-exit";
5466
5467 /*
5468 * Activity state.
5469 */
5470 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5471 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5472 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5476
5477 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5478 if ( !AttrSs.n.u2Dpl
5479 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5480 { /* likely */ }
5481 else
5482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5483
5484 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5485 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5486 {
5487 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5488 { /* likely */ }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5491 }
5492
5493 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5494 {
5495 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5496 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5497 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5498 switch (pVmcs->u32GuestActivityState)
5499 {
5500 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5501 {
5502 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5503 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5504 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5505 && ( uVector == X86_XCPT_DB
5506 || uVector == X86_XCPT_MC))
5507 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5508 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5509 { /* likely */ }
5510 else
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5512 break;
5513 }
5514
5515 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5516 {
5517 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5518 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5519 && uVector == X86_XCPT_MC))
5520 { /* likely */ }
5521 else
5522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5523 break;
5524 }
5525
5526 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5527 default:
5528 break;
5529 }
5530 }
5531
5532 /*
5533 * Interruptibility state.
5534 */
5535 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5536 { /* likely */ }
5537 else
5538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5539
5540 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5541 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5542 { /* likely */ }
5543 else
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5545
5546 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5547 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5548 { /* likely */ }
5549 else
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5551
5552 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5553 {
5554 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5555 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5556 {
5557 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5558 { /* likely */ }
5559 else
5560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5561 }
5562 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5563 {
5564 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5565 { /* likely */ }
5566 else
5567 {
5568 /*
5569 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5570 * We update the Exit qualification only when blocking-by-STI is set
5571 * without blocking-by-MovSS being set. Although in practise it does not
5572 * make much difference since the order of checks are implementation defined.
5573 */
5574 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5575 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5577 }
5578
5579 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5580 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5581 { /* likely */ }
5582 else
5583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5584 }
5585 }
5586
5587 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5588 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5589 { /* likely */ }
5590 else
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5592
5593 /* We don't support SGX yet. So enclave-interruption must not be set. */
5594 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5598
5599 /*
5600 * Pending debug exceptions.
5601 */
5602 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5603 ? pVmcs->u64GuestPendingDbgXcpts.u
5604 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5605 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5606 { /* likely */ }
5607 else
5608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5609
5610 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5611 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5612 {
5613 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5614 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5615 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5617
5618 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5619 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5620 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5622 }
5623
5624 /* We don't support RTM (Real-time Transactional Memory) yet. */
5625 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5626 { /* likely */ }
5627 else
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5629
5630 /*
5631 * VMCS link pointer.
5632 */
5633 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5634 {
5635 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5636 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5637 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5638 { /* likely */ }
5639 else
5640 {
5641 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5643 }
5644
5645 /* Validate the address. */
5646 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5647 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5648 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5649 { /* likely */ }
5650 else
5651 {
5652 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5654 }
5655
5656 /* Read the VMCS-link pointer from guest memory. */
5657 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5658 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5659 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5660 if (RT_SUCCESS(rc))
5661 { /* likely */ }
5662 else
5663 {
5664 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5666 }
5667
5668 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5669 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5670 { /* likely */ }
5671 else
5672 {
5673 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5674 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5675 }
5676
5677 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5678 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5679 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5680 { /* likely */ }
5681 else
5682 {
5683 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5685 }
5686
5687 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5688 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5689 }
5690
5691 NOREF(pszInstr);
5692 NOREF(pszFailure);
5693 return VINF_SUCCESS;
5694}
5695
5696
5697/**
5698 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5699 * VM-entry.
5700 *
5701 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5702 * @param pVCpu The cross context virtual CPU structure.
5703 * @param pszInstr The VMX instruction name (for logging purposes).
5704 * @param pVmcs Pointer to the virtual VMCS.
5705 */
5706IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5707{
5708 /*
5709 * Check PDPTEs.
5710 * See Intel spec. 4.4.1 "PDPTE Registers".
5711 */
5712 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5713 const char *const pszFailure = "VM-exit";
5714
5715 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5716 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5717 if (RT_SUCCESS(rc))
5718 {
5719 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5720 {
5721 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5722 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5723 { /* likely */ }
5724 else
5725 {
5726 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5727 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5729 }
5730 }
5731 }
5732 else
5733 {
5734 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5735 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5736 }
5737
5738 NOREF(pszFailure);
5739 NOREF(pszInstr);
5740 return rc;
5741}
5742
5743
5744/**
5745 * Checks guest PDPTEs as part of VM-entry.
5746 *
5747 * @param pVCpu The cross context virtual CPU structure.
5748 * @param pszInstr The VMX instruction name (for logging purposes).
5749 */
5750IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5751{
5752 /*
5753 * Guest PDPTEs.
5754 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5755 */
5756 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5757 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5758
5759 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5760 int rc;
5761 if ( !fGstInLongMode
5762 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5763 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5764 {
5765 /*
5766 * We don't support nested-paging for nested-guests yet.
5767 *
5768 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5769 * rather we need to check the PDPTEs referenced by the guest CR3.
5770 */
5771 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5772 }
5773 else
5774 rc = VINF_SUCCESS;
5775 return rc;
5776}
5777
5778
5779/**
5780 * Checks guest-state as part of VM-entry.
5781 *
5782 * @returns VBox status code.
5783 * @param pVCpu The cross context virtual CPU structure.
5784 * @param pszInstr The VMX instruction name (for logging purposes).
5785 */
5786IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5787{
5788 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5789 if (RT_SUCCESS(rc))
5790 {
5791 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5792 if (RT_SUCCESS(rc))
5793 {
5794 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5795 if (RT_SUCCESS(rc))
5796 {
5797 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5798 if (RT_SUCCESS(rc))
5799 {
5800 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5801 if (RT_SUCCESS(rc))
5802 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5803 }
5804 }
5805 }
5806 }
5807 return rc;
5808}
5809
5810
5811/**
5812 * Checks host-state as part of VM-entry.
5813 *
5814 * @returns VBox status code.
5815 * @param pVCpu The cross context virtual CPU structure.
5816 * @param pszInstr The VMX instruction name (for logging purposes).
5817 */
5818IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5819{
5820 /*
5821 * Host Control Registers and MSRs.
5822 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5823 */
5824 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5825 const char * const pszFailure = "VMFail";
5826
5827 /* CR0 reserved bits. */
5828 {
5829 /* CR0 MB1 bits. */
5830 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5831 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5835
5836 /* CR0 MBZ bits. */
5837 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5838 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5839 { /* likely */ }
5840 else
5841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5842 }
5843
5844 /* CR4 reserved bits. */
5845 {
5846 /* CR4 MB1 bits. */
5847 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5848 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5849 { /* likely */ }
5850 else
5851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5852
5853 /* CR4 MBZ bits. */
5854 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5855 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5856 { /* likely */ }
5857 else
5858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5859 }
5860
5861 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5862 {
5863 /* CR3 reserved bits. */
5864 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5865 { /* likely */ }
5866 else
5867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5868
5869 /* SYSENTER ESP and SYSENTER EIP. */
5870 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5871 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5872 { /* likely */ }
5873 else
5874 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5875 }
5876
5877 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5878 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5879
5880 /* PAT MSR. */
5881 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5882 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5886
5887 /* EFER MSR. */
5888 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5889 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5890 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5891 { /* likely */ }
5892 else
5893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5894
5895 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5896 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5897 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5898 if ( fHostInLongMode == fHostLma
5899 && fHostInLongMode == fHostLme)
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5903
5904 /*
5905 * Host Segment and Descriptor-Table Registers.
5906 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5907 */
5908 /* Selector RPL and TI. */
5909 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5910 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5911 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5912 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5913 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5914 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5915 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5916 { /* likely */ }
5917 else
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5919
5920 /* CS and TR selectors cannot be 0. */
5921 if ( pVmcs->HostCs
5922 && pVmcs->HostTr)
5923 { /* likely */ }
5924 else
5925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5926
5927 /* SS cannot be 0 if 32-bit host. */
5928 if ( fHostInLongMode
5929 || pVmcs->HostSs)
5930 { /* likely */ }
5931 else
5932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5933
5934 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5935 {
5936 /* FS, GS, GDTR, IDTR, TR base address. */
5937 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5938 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5939 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5940 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5941 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5942 { /* likely */ }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5945 }
5946
5947 /*
5948 * Host address-space size for 64-bit CPUs.
5949 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5950 */
5951 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5952 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5953 {
5954 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5955
5956 /* Logical processor in IA-32e mode. */
5957 if (fCpuInLongMode)
5958 {
5959 if (fHostInLongMode)
5960 {
5961 /* PAE must be set. */
5962 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5963 { /* likely */ }
5964 else
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5966
5967 /* RIP must be canonical. */
5968 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5969 { /* likely */ }
5970 else
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5972 }
5973 else
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5975 }
5976 else
5977 {
5978 /* Logical processor is outside IA-32e mode. */
5979 if ( !fGstInLongMode
5980 && !fHostInLongMode)
5981 {
5982 /* PCIDE should not be set. */
5983 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5984 { /* likely */ }
5985 else
5986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5987
5988 /* The high 32-bits of RIP MBZ. */
5989 if (!pVmcs->u64HostRip.s.Hi)
5990 { /* likely */ }
5991 else
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5993 }
5994 else
5995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5996 }
5997 }
5998 else
5999 {
6000 /* Host address-space size for 32-bit CPUs. */
6001 if ( !fGstInLongMode
6002 && !fHostInLongMode)
6003 { /* likely */ }
6004 else
6005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6006 }
6007
6008 NOREF(pszInstr);
6009 NOREF(pszFailure);
6010 return VINF_SUCCESS;
6011}
6012
6013
6014/**
6015 * Checks VM-entry controls fields as part of VM-entry.
6016 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6017 *
6018 * @returns VBox status code.
6019 * @param pVCpu The cross context virtual CPU structure.
6020 * @param pszInstr The VMX instruction name (for logging purposes).
6021 */
6022IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPUCC pVCpu, const char *pszInstr)
6023{
6024 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6025 const char * const pszFailure = "VMFail";
6026
6027 /* VM-entry controls. */
6028 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6029 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6030 { /* likely */ }
6031 else
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6033
6034 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6035 { /* likely */ }
6036 else
6037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6038
6039 /* Event injection. */
6040 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6041 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6042 {
6043 /* Type and vector. */
6044 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6045 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6046 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6047 if ( !uRsvd
6048 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6049 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6050 { /* likely */ }
6051 else
6052 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6053
6054 /* Exception error code. */
6055 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6056 {
6057 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6058 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6059 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6060 { /* likely */ }
6061 else
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6063
6064 /* Exceptions that provide an error code. */
6065 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6066 && ( uVector == X86_XCPT_DF
6067 || uVector == X86_XCPT_TS
6068 || uVector == X86_XCPT_NP
6069 || uVector == X86_XCPT_SS
6070 || uVector == X86_XCPT_GP
6071 || uVector == X86_XCPT_PF
6072 || uVector == X86_XCPT_AC))
6073 { /* likely */ }
6074 else
6075 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6076
6077 /* Exception error-code reserved bits. */
6078 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6079 { /* likely */ }
6080 else
6081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6082
6083 /* Injecting a software interrupt, software exception or privileged software exception. */
6084 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6085 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6086 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6087 {
6088 /* Instruction length must be in the range 0-15. */
6089 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6090 { /* likely */ }
6091 else
6092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6093
6094 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6095 if ( pVmcs->u32EntryInstrLen != 0
6096 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6100 }
6101 }
6102 }
6103
6104 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6105 if (pVmcs->u32EntryMsrLoadCount)
6106 {
6107 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6108 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6109 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6110 { /* likely */ }
6111 else
6112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6113 }
6114
6115 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6116 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6117
6118 NOREF(pszInstr);
6119 NOREF(pszFailure);
6120 return VINF_SUCCESS;
6121}
6122
6123
6124/**
6125 * Checks VM-exit controls fields as part of VM-entry.
6126 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6127 *
6128 * @returns VBox status code.
6129 * @param pVCpu The cross context virtual CPU structure.
6130 * @param pszInstr The VMX instruction name (for logging purposes).
6131 */
6132IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPUCC pVCpu, const char *pszInstr)
6133{
6134 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6135 const char * const pszFailure = "VMFail";
6136
6137 /* VM-exit controls. */
6138 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6139 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6140 { /* likely */ }
6141 else
6142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6143
6144 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6148
6149 /* Save preemption timer without activating it. */
6150 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6151 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6152 { /* likely */ }
6153 else
6154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6155
6156 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6157 if (pVmcs->u32ExitMsrStoreCount)
6158 {
6159 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6160 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6161 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6165 }
6166
6167 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6168 if (pVmcs->u32ExitMsrLoadCount)
6169 {
6170 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6171 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6172 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6176 }
6177
6178 NOREF(pszInstr);
6179 NOREF(pszFailure);
6180 return VINF_SUCCESS;
6181}
6182
6183
6184/**
6185 * Checks VM-execution controls fields as part of VM-entry.
6186 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6187 *
6188 * @returns VBox status code.
6189 * @param pVCpu The cross context virtual CPU structure.
6190 * @param pszInstr The VMX instruction name (for logging purposes).
6191 *
6192 * @remarks This may update secondary-processor based VM-execution control fields
6193 * in the current VMCS if necessary.
6194 */
6195IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPUCC pVCpu, const char *pszInstr)
6196{
6197 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6198 const char * const pszFailure = "VMFail";
6199
6200 /* Pin-based VM-execution controls. */
6201 {
6202 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6203 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6204 { /* likely */ }
6205 else
6206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6207
6208 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6209 { /* likely */ }
6210 else
6211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6212 }
6213
6214 /* Processor-based VM-execution controls. */
6215 {
6216 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6217 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6218 { /* likely */ }
6219 else
6220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6221
6222 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6223 { /* likely */ }
6224 else
6225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6226 }
6227
6228 /* Secondary processor-based VM-execution controls. */
6229 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6230 {
6231 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6232 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6233 { /* likely */ }
6234 else
6235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6236
6237 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6241 }
6242 else
6243 Assert(!pVmcs->u32ProcCtls2);
6244
6245 /* CR3-target count. */
6246 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6247 { /* likely */ }
6248 else
6249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6250
6251 /* I/O bitmaps physical addresses. */
6252 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6253 {
6254 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6255 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6256 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6257 { /* likely */ }
6258 else
6259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6260
6261 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6262 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6263 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6264 { /* likely */ }
6265 else
6266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6267 }
6268
6269 /* MSR bitmap physical address. */
6270 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6271 {
6272 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6273 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6274 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6275 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6276 { /* likely */ }
6277 else
6278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6279
6280 /* Read the MSR bitmap. */
6281 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6282 * implementing fast path. */
6283 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6284 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6285 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6286 if (RT_SUCCESS(rc))
6287 { /* likely */ }
6288 else
6289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6290 }
6291
6292 /* TPR shadow related controls. */
6293 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6294 {
6295 /* Virtual-APIC page physical address. */
6296 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6297 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6298 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6299 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6300 { /* likely */ }
6301 else
6302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6303
6304 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6305 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6306 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6307 { /* likely */ }
6308 else
6309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6310
6311 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6312 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6313 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6314 {
6315 /* Read the VTPR from the virtual-APIC page. */
6316 uint8_t u8VTpr;
6317 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6318 if (RT_SUCCESS(rc))
6319 { /* likely */ }
6320 else
6321 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6322
6323 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6324 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6328 }
6329 }
6330 else
6331 {
6332 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6333 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6334 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6335 { /* likely */ }
6336 else
6337 {
6338 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6339 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6340 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6342 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6344 }
6345 }
6346
6347 /* NMI exiting and virtual-NMIs. */
6348 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6349 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6353
6354 /* Virtual-NMIs and NMI-window exiting. */
6355 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6356 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6360
6361 /* Virtualize APIC accesses. */
6362 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6363 {
6364 /* APIC-access physical address. */
6365 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6366 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6367 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6368 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6369 { /* likely */ }
6370 else
6371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6372
6373 /*
6374 * Disallow APIC-access page and virtual-APIC page from being the same address.
6375 * Note! This is not an Intel requirement, but one imposed by our implementation.
6376 */
6377 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6378 * redirecting accesses between the APIC-access page and the virtual-APIC
6379 * page. If any guest hypervisor requires this, we can implement it later. */
6380 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6381 {
6382 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6383 if (GCPhysVirtApic != GCPhysApicAccess)
6384 { /* likely */ }
6385 else
6386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6387 }
6388
6389 /*
6390 * Register the handler for the APIC-access page.
6391 *
6392 * We don't deregister the APIC-access page handler during the VM-exit as a different
6393 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6394 *
6395 * We leave the page registered until the first access that happens outside VMX non-root
6396 * mode. Guest software is allowed to access structures such as the APIC-access page
6397 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6398 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6399 *
6400 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6401 */
6402 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6403 {
6404 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6405 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6406 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6407 if (RT_SUCCESS(rc))
6408 { /* likely */ }
6409 else
6410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6411 }
6412 }
6413
6414 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6415 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6416 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6417 { /* likely */ }
6418 else
6419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6420
6421 /* Virtual-interrupt delivery requires external interrupt exiting. */
6422 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6423 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6424 { /* likely */ }
6425 else
6426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6427
6428 /* VPID. */
6429 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6430 || pVmcs->u16Vpid != 0)
6431 { /* likely */ }
6432 else
6433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6434
6435 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6436 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6437 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6438 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6439 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6440 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6441 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6442
6443 /* VMCS shadowing. */
6444 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6445 {
6446 /* VMREAD-bitmap physical address. */
6447 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6448 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6449 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6450 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6451 { /* likely */ }
6452 else
6453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6454
6455 /* VMWRITE-bitmap physical address. */
6456 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6457 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6458 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6459 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6460 { /* likely */ }
6461 else
6462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6463
6464 /* Read the VMREAD-bitmap. */
6465 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6466 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6467 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6468 if (RT_SUCCESS(rc))
6469 { /* likely */ }
6470 else
6471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6472
6473 /* Read the VMWRITE-bitmap. */
6474 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6475 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6476 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6477 if (RT_SUCCESS(rc))
6478 { /* likely */ }
6479 else
6480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6481 }
6482
6483 NOREF(pszInstr);
6484 NOREF(pszFailure);
6485 return VINF_SUCCESS;
6486}
6487
6488
6489/**
6490 * Loads the guest control registers, debug register and some MSRs as part of
6491 * VM-entry.
6492 *
6493 * @param pVCpu The cross context virtual CPU structure.
6494 */
6495IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6496{
6497 /*
6498 * Load guest control registers, debug registers and MSRs.
6499 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6500 */
6501 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6502
6503 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6504 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6505 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6506 CPUMSetGuestCR0(pVCpu, uGstCr0);
6507 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6508 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6509
6510 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6511 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6512
6513 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6514 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6515 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6516
6517 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6518 {
6519 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6520
6521 /* EFER MSR. */
6522 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6523 {
6524 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6525 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6526 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6527 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6528 if (fGstInLongMode)
6529 {
6530 /* If the nested-guest is in long mode, LMA and LME are both set. */
6531 Assert(fGstPaging);
6532 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6533 }
6534 else
6535 {
6536 /*
6537 * If the nested-guest is outside long mode:
6538 * - With paging: LMA is cleared, LME is cleared.
6539 * - Without paging: LMA is cleared, LME is left unmodified.
6540 */
6541 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6542 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6543 }
6544 }
6545 /* else: see below. */
6546 }
6547
6548 /* PAT MSR. */
6549 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6550 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6551
6552 /* EFER MSR. */
6553 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6554 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6555
6556 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6557 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6558
6559 /* We don't support IA32_BNDCFGS MSR yet. */
6560 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6561
6562 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6563}
6564
6565
6566/**
6567 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6568 *
6569 * @param pVCpu The cross context virtual CPU structure.
6570 */
6571IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6572{
6573 /*
6574 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6575 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6576 */
6577 /* CS, SS, ES, DS, FS, GS. */
6578 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6579 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6580 {
6581 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6582 CPUMSELREG VmcsSelReg;
6583 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6584 AssertRC(rc); NOREF(rc);
6585 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6586 {
6587 pGstSelReg->Sel = VmcsSelReg.Sel;
6588 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6589 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6590 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6591 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6592 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6593 }
6594 else
6595 {
6596 pGstSelReg->Sel = VmcsSelReg.Sel;
6597 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6598 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6599 switch (iSegReg)
6600 {
6601 case X86_SREG_CS:
6602 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6603 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6604 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6605 break;
6606
6607 case X86_SREG_SS:
6608 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6609 pGstSelReg->u32Limit = 0;
6610 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6611 break;
6612
6613 case X86_SREG_ES:
6614 case X86_SREG_DS:
6615 pGstSelReg->u64Base = 0;
6616 pGstSelReg->u32Limit = 0;
6617 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6618 break;
6619
6620 case X86_SREG_FS:
6621 case X86_SREG_GS:
6622 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6623 pGstSelReg->u32Limit = 0;
6624 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6625 break;
6626 }
6627 Assert(pGstSelReg->Attr.n.u1Unusable);
6628 }
6629 }
6630
6631 /* LDTR. */
6632 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6633 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6634 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6635 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6636 {
6637 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6638 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6639 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6640 }
6641 else
6642 {
6643 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6644 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6645 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6646 }
6647
6648 /* TR. */
6649 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6650 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6651 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6652 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6653 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6654 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6655 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6656
6657 /* GDTR. */
6658 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6659 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6660
6661 /* IDTR. */
6662 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6663 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6664}
6665
6666
6667/**
6668 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6669 *
6670 * @returns VBox status code.
6671 * @param pVCpu The cross context virtual CPU structure.
6672 * @param pszInstr The VMX instruction name (for logging purposes).
6673 */
6674IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6675{
6676 /*
6677 * Load guest MSRs.
6678 * See Intel spec. 26.4 "Loading MSRs".
6679 */
6680 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6681 const char *const pszFailure = "VM-exit";
6682
6683 /*
6684 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6685 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6686 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6687 */
6688 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6689 if (!cMsrs)
6690 return VINF_SUCCESS;
6691
6692 /*
6693 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6694 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6695 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6696 */
6697 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6698 if (fIsMsrCountValid)
6699 { /* likely */ }
6700 else
6701 {
6702 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6704 }
6705
6706 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6707 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6708 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6709 if (RT_SUCCESS(rc))
6710 {
6711 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6712 Assert(pMsr);
6713 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6714 {
6715 if ( !pMsr->u32Reserved
6716 && pMsr->u32Msr != MSR_K8_FS_BASE
6717 && pMsr->u32Msr != MSR_K8_GS_BASE
6718 && pMsr->u32Msr != MSR_K6_EFER
6719 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6720 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6721 {
6722 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6723 if (rcStrict == VINF_SUCCESS)
6724 continue;
6725
6726 /*
6727 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6728 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6729 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6730 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6731 * MSR in ring-0 if possible, or come up with a better, generic solution.
6732 */
6733 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6734 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6735 ? kVmxVDiag_Vmentry_MsrLoadRing3
6736 : kVmxVDiag_Vmentry_MsrLoad;
6737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6738 }
6739 else
6740 {
6741 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6742 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6743 }
6744 }
6745 }
6746 else
6747 {
6748 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6749 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6750 }
6751
6752 NOREF(pszInstr);
6753 NOREF(pszFailure);
6754 return VINF_SUCCESS;
6755}
6756
6757
6758/**
6759 * Loads the guest-state non-register state as part of VM-entry.
6760 *
6761 * @returns VBox status code.
6762 * @param pVCpu The cross context virtual CPU structure.
6763 *
6764 * @remarks This must be called only after loading the nested-guest register state
6765 * (especially nested-guest RIP).
6766 */
6767IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6768{
6769 /*
6770 * Load guest non-register state.
6771 * See Intel spec. 26.6 "Special Features of VM Entry"
6772 */
6773 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6774
6775 /*
6776 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6777 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6778 *
6779 * See Intel spec. 26.6.1 "Interruptibility State".
6780 */
6781 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6782 if ( !fEntryVectoring
6783 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6784 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6785 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6786 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6787
6788 /* NMI blocking. */
6789 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6790 {
6791 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6792 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6793 else
6794 {
6795 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6796 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6797 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6798 }
6799 }
6800 else
6801 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6802
6803 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6804
6805 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6806 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6807
6808 /* VPID is irrelevant. We don't support VPID yet. */
6809
6810 /* Clear address-range monitoring. */
6811 EMMonitorWaitClear(pVCpu);
6812}
6813
6814
6815/**
6816 * Loads the guest-state as part of VM-entry.
6817 *
6818 * @returns VBox status code.
6819 * @param pVCpu The cross context virtual CPU structure.
6820 * @param pszInstr The VMX instruction name (for logging purposes).
6821 *
6822 * @remarks This must be done after all the necessary steps prior to loading of
6823 * guest-state (e.g. checking various VMCS state).
6824 */
6825IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6826{
6827 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6828 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6829
6830 /*
6831 * Load guest RIP, RSP and RFLAGS.
6832 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6833 */
6834 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6835 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6836 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6837 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6838
6839 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6840 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6841 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6842
6843 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6844
6845 NOREF(pszInstr);
6846 return VINF_SUCCESS;
6847}
6848
6849
6850/**
6851 * Returns whether there are is a pending debug exception on VM-entry.
6852 *
6853 * @param pVCpu The cross context virtual CPU structure.
6854 * @param pszInstr The VMX instruction name (for logging purposes).
6855 */
6856IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6857{
6858 /*
6859 * Pending debug exceptions.
6860 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6861 */
6862 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6863 Assert(pVmcs);
6864
6865 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6866 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6867 if (fPendingDbgXcpt)
6868 {
6869 uint8_t uEntryIntInfoType;
6870 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6871 if (fEntryVectoring)
6872 {
6873 switch (uEntryIntInfoType)
6874 {
6875 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6876 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6877 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6878 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6879 fPendingDbgXcpt = false;
6880 break;
6881
6882 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6883 {
6884 /*
6885 * Whether the pending debug exception for software exceptions other than
6886 * #BP and #OF is delivered after injecting the exception or is discard
6887 * is CPU implementation specific. We will discard them (easier).
6888 */
6889 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6890 if ( uVector != X86_XCPT_BP
6891 && uVector != X86_XCPT_OF)
6892 fPendingDbgXcpt = false;
6893 RT_FALL_THRU();
6894 }
6895 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6896 {
6897 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6898 fPendingDbgXcpt = false;
6899 break;
6900 }
6901 }
6902 }
6903 else
6904 {
6905 /*
6906 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6907 * pending debug exception is held pending or is discarded is CPU implementation
6908 * specific. We will discard them (easier).
6909 */
6910 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6911 fPendingDbgXcpt = false;
6912
6913 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6914 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6915 fPendingDbgXcpt = false;
6916 }
6917 }
6918
6919 NOREF(pszInstr);
6920 return fPendingDbgXcpt;
6921}
6922
6923
6924/**
6925 * Set up the monitor-trap flag (MTF).
6926 *
6927 * @param pVCpu The cross context virtual CPU structure.
6928 * @param pszInstr The VMX instruction name (for logging purposes).
6929 */
6930IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6931{
6932 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6933 Assert(pVmcs);
6934 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6935 {
6936 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6937 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6938 }
6939 else
6940 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6941 NOREF(pszInstr);
6942}
6943
6944
6945/**
6946 * Sets up NMI-window exiting.
6947 *
6948 * @param pVCpu The cross context virtual CPU structure.
6949 * @param pszInstr The VMX instruction name (for logging purposes).
6950 */
6951IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6952{
6953 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6954 Assert(pVmcs);
6955 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6956 {
6957 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6958 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6959 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6960 }
6961 else
6962 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6963 NOREF(pszInstr);
6964}
6965
6966
6967/**
6968 * Sets up interrupt-window exiting.
6969 *
6970 * @param pVCpu The cross context virtual CPU structure.
6971 * @param pszInstr The VMX instruction name (for logging purposes).
6972 */
6973IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6974{
6975 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6976 Assert(pVmcs);
6977 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6978 {
6979 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6980 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6981 }
6982 else
6983 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6984 NOREF(pszInstr);
6985}
6986
6987
6988/**
6989 * Set up the VMX-preemption timer.
6990 *
6991 * @param pVCpu The cross context virtual CPU structure.
6992 * @param pszInstr The VMX instruction name (for logging purposes).
6993 */
6994IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6995{
6996 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6997 Assert(pVmcs);
6998 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6999 {
7000 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7001 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7002 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7003
7004 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7005 }
7006 else
7007 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7008
7009 NOREF(pszInstr);
7010}
7011
7012
7013/**
7014 * Injects an event using TRPM given a VM-entry interruption info. and related
7015 * fields.
7016 *
7017 * @param pVCpu The cross context virtual CPU structure.
7018 * @param pszInstr The VMX instruction name (for logging purposes).
7019 * @param uEntryIntInfo The VM-entry interruption info.
7020 * @param uErrCode The error code associated with the event if any.
7021 * @param cbInstr The VM-entry instruction length (for software
7022 * interrupts and software exceptions). Pass 0
7023 * otherwise.
7024 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7025 */
7026IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7027 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7028{
7029 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7030
7031 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7032 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7033 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7034
7035 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7036
7037 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7038 AssertRC(rc);
7039 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7040
7041 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7042 {
7043 TRPMSetErrorCode(pVCpu, uErrCode);
7044 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7045 }
7046
7047 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7048 {
7049 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7050 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7051 }
7052 else
7053 {
7054 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7055 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7056 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7057 {
7058 TRPMSetInstrLength(pVCpu, cbInstr);
7059 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7060 }
7061 }
7062
7063 NOREF(pszInstr);
7064}
7065
7066
7067/**
7068 * Performs event injection (if any) as part of VM-entry.
7069 *
7070 * @param pVCpu The cross context virtual CPU structure.
7071 * @param pszInstr The VMX instruction name (for logging purposes).
7072 */
7073IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7074{
7075 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7076
7077 /*
7078 * Inject events.
7079 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7080 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7081 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7082 * the actually delivery of this event.
7083 *
7084 * See Intel spec. 26.5 "Event Injection".
7085 */
7086 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7087 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7088
7089 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7090 if (fEntryIntInfoValid)
7091 {
7092 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7093 {
7094 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7095 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7096 }
7097 else
7098 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7099 pVCpu->cpum.GstCtx.cr2);
7100
7101 /*
7102 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7103 *
7104 * However, we do it here on VM-entry as well because while it isn't visible to guest
7105 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7106 * execution using hardware-assisted VT-x, it will not be try to inject the event again.
7107 *
7108 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7109 */
7110 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7111 }
7112 else
7113 {
7114 /*
7115 * Inject any pending guest debug exception.
7116 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7117 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7118 */
7119 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7120 if (fPendingDbgXcpt)
7121 {
7122 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7123 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7124 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7125 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7126 0 /* GCPtrFaultAddress */);
7127 }
7128 }
7129
7130 NOREF(pszInstr);
7131}
7132
7133
7134/**
7135 * Initializes all read-only VMCS fields as part of VM-entry.
7136 *
7137 * @param pVCpu The cross context virtual CPU structure.
7138 */
7139IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7140{
7141 /*
7142 * Any VMCS field which we do not establish on every VM-exit but may potentially
7143 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7144 * specified to be undefined needs to be initialized here.
7145 *
7146 * Thus, it is especially important to clear the Exit qualification field
7147 * since it must be zero for VM-exits where it is not used. Similarly, the
7148 * VM-exit interruption information field's valid bit needs to be cleared for
7149 * the same reasons.
7150 */
7151 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7152 Assert(pVmcs);
7153
7154 /* 16-bit (none currently). */
7155 /* 32-bit. */
7156 pVmcs->u32RoVmInstrError = 0;
7157 pVmcs->u32RoExitReason = 0;
7158 pVmcs->u32RoExitIntInfo = 0;
7159 pVmcs->u32RoExitIntErrCode = 0;
7160 pVmcs->u32RoIdtVectoringInfo = 0;
7161 pVmcs->u32RoIdtVectoringErrCode = 0;
7162 pVmcs->u32RoExitInstrLen = 0;
7163 pVmcs->u32RoExitInstrInfo = 0;
7164
7165 /* 64-bit. */
7166 pVmcs->u64RoGuestPhysAddr.u = 0;
7167
7168 /* Natural-width. */
7169 pVmcs->u64RoExitQual.u = 0;
7170 pVmcs->u64RoIoRcx.u = 0;
7171 pVmcs->u64RoIoRsi.u = 0;
7172 pVmcs->u64RoIoRdi.u = 0;
7173 pVmcs->u64RoIoRip.u = 0;
7174 pVmcs->u64RoGuestLinearAddr.u = 0;
7175}
7176
7177
7178/**
7179 * VMLAUNCH/VMRESUME instruction execution worker.
7180 *
7181 * @returns Strict VBox status code.
7182 * @param pVCpu The cross context virtual CPU structure.
7183 * @param cbInstr The instruction length in bytes.
7184 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7185 * VMXINSTRID_VMRESUME).
7186 *
7187 * @remarks Common VMX instruction checks are already expected to by the caller,
7188 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7189 */
7190IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7191{
7192# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7193 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7194 return VINF_EM_RAW_EMULATE_INSTR;
7195# else
7196 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7197 || uInstrId == VMXINSTRID_VMRESUME);
7198 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7199
7200 /* Nested-guest intercept. */
7201 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7202 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7203
7204 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7205
7206 /*
7207 * Basic VM-entry checks.
7208 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7209 * The checks following that do not have to follow a specific order.
7210 *
7211 * See Intel spec. 26.1 "Basic VM-entry Checks".
7212 */
7213
7214 /* CPL. */
7215 if (pVCpu->iem.s.uCpl == 0)
7216 { /* likely */ }
7217 else
7218 {
7219 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7220 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7221 return iemRaiseGeneralProtectionFault0(pVCpu);
7222 }
7223
7224 /* Current VMCS valid. */
7225 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7226 { /* likely */ }
7227 else
7228 {
7229 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7230 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7231 iemVmxVmFailInvalid(pVCpu);
7232 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7233 return VINF_SUCCESS;
7234 }
7235
7236 /* Current VMCS is not a shadow VMCS. */
7237 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7238 { /* likely */ }
7239 else
7240 {
7241 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7242 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7243 iemVmxVmFailInvalid(pVCpu);
7244 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7245 return VINF_SUCCESS;
7246 }
7247
7248 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7249 * use block-by-STI here which is not quite correct. */
7250 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7251 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7252 { /* likely */ }
7253 else
7254 {
7255 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7256 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7257 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7258 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7259 return VINF_SUCCESS;
7260 }
7261
7262 if (uInstrId == VMXINSTRID_VMLAUNCH)
7263 {
7264 /* VMLAUNCH with non-clear VMCS. */
7265 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7266 { /* likely */ }
7267 else
7268 {
7269 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7270 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7271 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7273 return VINF_SUCCESS;
7274 }
7275 }
7276 else
7277 {
7278 /* VMRESUME with non-launched VMCS. */
7279 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7280 { /* likely */ }
7281 else
7282 {
7283 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7284 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7285 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7286 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7287 return VINF_SUCCESS;
7288 }
7289 }
7290
7291 /*
7292 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7293 * while entering VMX non-root mode. We do some of this while checking VM-execution
7294 * controls. The guest hypervisor should not make assumptions and cannot expect
7295 * predictable behavior if changes to these structures are made in guest memory while
7296 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7297 * modify them anyway as we cache them in host memory.
7298 *
7299 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7300 */
7301 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7302 Assert(pVmcs);
7303 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7304
7305 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7306 if (RT_SUCCESS(rc))
7307 {
7308 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7309 if (RT_SUCCESS(rc))
7310 {
7311 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7312 if (RT_SUCCESS(rc))
7313 {
7314 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7315 if (RT_SUCCESS(rc))
7316 {
7317 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7318 iemVmxVmentryInitReadOnlyFields(pVCpu);
7319
7320 /*
7321 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7322 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7323 * VM-exit when required.
7324 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7325 */
7326 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7327
7328 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7329 if (RT_SUCCESS(rc))
7330 {
7331 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7332 if (RT_SUCCESS(rc))
7333 {
7334 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7335 if (RT_SUCCESS(rc))
7336 {
7337 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7338
7339 /* VMLAUNCH instruction must update the VMCS launch state. */
7340 if (uInstrId == VMXINSTRID_VMLAUNCH)
7341 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7342
7343 /* Perform the VMX transition (PGM updates). */
7344 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7345 if (rcStrict == VINF_SUCCESS)
7346 { /* likely */ }
7347 else if (RT_SUCCESS(rcStrict))
7348 {
7349 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7350 VBOXSTRICTRC_VAL(rcStrict)));
7351 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7352 }
7353 else
7354 {
7355 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7356 return rcStrict;
7357 }
7358
7359 /* Paranoia. */
7360 Assert(rcStrict == VINF_SUCCESS);
7361
7362 /* We've now entered nested-guest execution. */
7363 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7364
7365 /*
7366 * The priority of potential VM-exits during VM-entry is important.
7367 * The priorities of VM-exits and events are listed from highest
7368 * to lowest as follows:
7369 *
7370 * 1. Event injection.
7371 * 2. Trap on task-switch (T flag set in TSS).
7372 * 3. TPR below threshold / APIC-write.
7373 * 4. SMI, INIT.
7374 * 5. MTF exit.
7375 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7376 * 7. VMX-preemption timer.
7377 * 9. NMI-window exit.
7378 * 10. NMI injection.
7379 * 11. Interrupt-window exit.
7380 * 12. Virtual-interrupt injection.
7381 * 13. Interrupt injection.
7382 * 14. Process next instruction (fetch, decode, execute).
7383 */
7384
7385 /* Setup VMX-preemption timer. */
7386 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7387
7388 /* Setup monitor-trap flag. */
7389 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7390
7391 /* Setup NMI-window exiting. */
7392 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7393
7394 /* Setup interrupt-window exiting. */
7395 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7396
7397 /*
7398 * Inject any event that the guest hypervisor wants to inject.
7399 * Note! We cannot immediately perform the event injection here as we may have
7400 * pending PGM operations to perform due to switching page tables and/or
7401 * mode.
7402 */
7403 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7404
7405# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7406 /* Reschedule to IEM-only execution of the nested-guest. */
7407 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7408 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7409 if (rcSched != VINF_SUCCESS)
7410 iemSetPassUpStatus(pVCpu, rcSched);
7411# endif
7412
7413 /* Finally, done. */
7414 Log(("%s: cs:rip=%#04x:%#RX64 cr3=%#RX64\n", pszInstr, pVCpu->cpum.GstCtx.cs.Sel,
7415 pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr3));
7416 return VINF_SUCCESS;
7417 }
7418 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7419 pVmcs->u64RoExitQual.u);
7420 }
7421 }
7422 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7423 pVmcs->u64RoExitQual.u);
7424 }
7425
7426 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7427 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7428 return VINF_SUCCESS;
7429 }
7430 }
7431 }
7432
7433 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7434 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7435 return VINF_SUCCESS;
7436# endif
7437}
7438
7439
7440/**
7441 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7442 * (causes a VM-exit) or not.
7443 *
7444 * @returns @c true if the instruction is intercepted, @c false otherwise.
7445 * @param pVCpu The cross context virtual CPU structure.
7446 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7447 * VMX_EXIT_WRMSR).
7448 * @param idMsr The MSR.
7449 */
7450IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7451{
7452 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7453 Assert( uExitReason == VMX_EXIT_RDMSR
7454 || uExitReason == VMX_EXIT_WRMSR);
7455
7456 /* Consult the MSR bitmap if the feature is supported. */
7457 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7458 Assert(pVmcs);
7459 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7460 {
7461 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7462 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7463 if (uExitReason == VMX_EXIT_RDMSR)
7464 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7465 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7466 }
7467
7468 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7469 return true;
7470}
7471
7472
7473/**
7474 * VMREAD instruction execution worker that does not perform any validation checks.
7475 *
7476 * Callers are expected to have performed the necessary checks and to ensure the
7477 * VMREAD will succeed.
7478 *
7479 * @param pVmcs Pointer to the virtual VMCS.
7480 * @param pu64Dst Where to write the VMCS value.
7481 * @param u64VmcsField The VMCS field.
7482 *
7483 * @remarks May be called with interrupts disabled.
7484 */
7485IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7486{
7487 VMXVMCSFIELD VmcsField;
7488 VmcsField.u = u64VmcsField;
7489 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7490 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7491 uint8_t const uWidthType = (uWidth << 2) | uType;
7492 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7493 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7494 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7495 Assert(offField < VMX_V_VMCS_SIZE);
7496 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7497
7498 /*
7499 * Read the VMCS component based on the field's effective width.
7500 *
7501 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7502 * indicates high bits (little endian).
7503 *
7504 * Note! The caller is responsible to trim the result and update registers
7505 * or memory locations are required. Here we just zero-extend to the largest
7506 * type (i.e. 64-bits).
7507 */
7508 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7509 uint8_t const *pbField = pbVmcs + offField;
7510 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7511 switch (uEffWidth)
7512 {
7513 case VMX_VMCSFIELD_WIDTH_64BIT:
7514 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7515 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7516 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7517 }
7518}
7519
7520
7521/**
7522 * VMREAD common (memory/register) instruction execution worker.
7523 *
7524 * @returns Strict VBox status code.
7525 * @param pVCpu The cross context virtual CPU structure.
7526 * @param cbInstr The instruction length in bytes.
7527 * @param pu64Dst Where to write the VMCS value (only updated when
7528 * VINF_SUCCESS is returned).
7529 * @param u64VmcsField The VMCS field.
7530 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7531 * NULL.
7532 */
7533IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7534 PCVMXVEXITINFO pExitInfo)
7535{
7536 /* Nested-guest intercept. */
7537 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7538 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7539 {
7540 if (pExitInfo)
7541 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7542 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7543 }
7544
7545 /* CPL. */
7546 if (pVCpu->iem.s.uCpl == 0)
7547 { /* likely */ }
7548 else
7549 {
7550 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7552 return iemRaiseGeneralProtectionFault0(pVCpu);
7553 }
7554
7555 /* VMCS pointer in root mode. */
7556 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7557 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7558 { /* likely */ }
7559 else
7560 {
7561 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7563 iemVmxVmFailInvalid(pVCpu);
7564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7565 return VINF_SUCCESS;
7566 }
7567
7568 /* VMCS-link pointer in non-root mode. */
7569 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7570 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7571 { /* likely */ }
7572 else
7573 {
7574 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7576 iemVmxVmFailInvalid(pVCpu);
7577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7578 return VINF_SUCCESS;
7579 }
7580
7581 /* Supported VMCS field. */
7582 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7583 { /* likely */ }
7584 else
7585 {
7586 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7588 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7589 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7590 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7591 return VINF_SUCCESS;
7592 }
7593
7594 /*
7595 * Reading from the current or shadow VMCS.
7596 */
7597 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7598 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7599 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7600 Assert(pVmcs);
7601 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7602 return VINF_SUCCESS;
7603}
7604
7605
7606/**
7607 * VMREAD (64-bit register) instruction execution worker.
7608 *
7609 * @returns Strict VBox status code.
7610 * @param pVCpu The cross context virtual CPU structure.
7611 * @param cbInstr The instruction length in bytes.
7612 * @param pu64Dst Where to store the VMCS field's value.
7613 * @param u64VmcsField The VMCS field.
7614 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7615 * NULL.
7616 */
7617IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7618 PCVMXVEXITINFO pExitInfo)
7619{
7620 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7621 if (rcStrict == VINF_SUCCESS)
7622 {
7623 iemVmxVmreadSuccess(pVCpu, cbInstr);
7624 return VINF_SUCCESS;
7625 }
7626
7627 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7628 return rcStrict;
7629}
7630
7631
7632/**
7633 * VMREAD (32-bit register) instruction execution worker.
7634 *
7635 * @returns Strict VBox status code.
7636 * @param pVCpu The cross context virtual CPU structure.
7637 * @param cbInstr The instruction length in bytes.
7638 * @param pu32Dst Where to store the VMCS field's value.
7639 * @param u32VmcsField The VMCS field.
7640 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7641 * NULL.
7642 */
7643IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7644 PCVMXVEXITINFO pExitInfo)
7645{
7646 uint64_t u64Dst;
7647 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7648 if (rcStrict == VINF_SUCCESS)
7649 {
7650 *pu32Dst = u64Dst;
7651 iemVmxVmreadSuccess(pVCpu, cbInstr);
7652 return VINF_SUCCESS;
7653 }
7654
7655 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7656 return rcStrict;
7657}
7658
7659
7660/**
7661 * VMREAD (memory) instruction execution worker.
7662 *
7663 * @returns Strict VBox status code.
7664 * @param pVCpu The cross context virtual CPU structure.
7665 * @param cbInstr The instruction length in bytes.
7666 * @param iEffSeg The effective segment register to use with @a u64Val.
7667 * Pass UINT8_MAX if it is a register access.
7668 * @param GCPtrDst The guest linear address to store the VMCS field's
7669 * value.
7670 * @param u64VmcsField The VMCS field.
7671 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7672 * NULL.
7673 */
7674IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7675 PCVMXVEXITINFO pExitInfo)
7676{
7677 uint64_t u64Dst;
7678 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7679 if (rcStrict == VINF_SUCCESS)
7680 {
7681 /*
7682 * Write the VMCS field's value to the location specified in guest-memory.
7683 */
7684 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7685 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7686 else
7687 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7688 if (rcStrict == VINF_SUCCESS)
7689 {
7690 iemVmxVmreadSuccess(pVCpu, cbInstr);
7691 return VINF_SUCCESS;
7692 }
7693
7694 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7695 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7696 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7697 return rcStrict;
7698 }
7699
7700 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7701 return rcStrict;
7702}
7703
7704
7705/**
7706 * VMWRITE instruction execution worker that does not perform any validation
7707 * checks.
7708 *
7709 * Callers are expected to have performed the necessary checks and to ensure the
7710 * VMWRITE will succeed.
7711 *
7712 * @param pVmcs Pointer to the virtual VMCS.
7713 * @param u64Val The value to write.
7714 * @param u64VmcsField The VMCS field.
7715 *
7716 * @remarks May be called with interrupts disabled.
7717 */
7718IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7719{
7720 VMXVMCSFIELD VmcsField;
7721 VmcsField.u = u64VmcsField;
7722 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7723 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7724 uint8_t const uWidthType = (uWidth << 2) | uType;
7725 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7726 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7727 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7728 Assert(offField < VMX_V_VMCS_SIZE);
7729 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7730
7731 /*
7732 * Write the VMCS component based on the field's effective width.
7733 *
7734 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7735 * indicates high bits (little endian).
7736 */
7737 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7738 uint8_t *pbField = pbVmcs + offField;
7739 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7740 switch (uEffWidth)
7741 {
7742 case VMX_VMCSFIELD_WIDTH_64BIT:
7743 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7744 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7745 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7746 }
7747}
7748
7749
7750/**
7751 * VMWRITE instruction execution worker.
7752 *
7753 * @returns Strict VBox status code.
7754 * @param pVCpu The cross context virtual CPU structure.
7755 * @param cbInstr The instruction length in bytes.
7756 * @param iEffSeg The effective segment register to use with @a u64Val.
7757 * Pass UINT8_MAX if it is a register access.
7758 * @param u64Val The value to write (or guest linear address to the
7759 * value), @a iEffSeg will indicate if it's a memory
7760 * operand.
7761 * @param u64VmcsField The VMCS field.
7762 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7763 * NULL.
7764 */
7765IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7766 PCVMXVEXITINFO pExitInfo)
7767{
7768 /* Nested-guest intercept. */
7769 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7770 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7771 {
7772 if (pExitInfo)
7773 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7774 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7775 }
7776
7777 /* CPL. */
7778 if (pVCpu->iem.s.uCpl == 0)
7779 { /* likely */ }
7780 else
7781 {
7782 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7784 return iemRaiseGeneralProtectionFault0(pVCpu);
7785 }
7786
7787 /* VMCS pointer in root mode. */
7788 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7789 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7790 { /* likely */ }
7791 else
7792 {
7793 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7794 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7795 iemVmxVmFailInvalid(pVCpu);
7796 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7797 return VINF_SUCCESS;
7798 }
7799
7800 /* VMCS-link pointer in non-root mode. */
7801 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7802 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7803 { /* likely */ }
7804 else
7805 {
7806 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7807 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7808 iemVmxVmFailInvalid(pVCpu);
7809 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7810 return VINF_SUCCESS;
7811 }
7812
7813 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7814 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7815 if (!fIsRegOperand)
7816 {
7817 /* Read the value from the specified guest memory location. */
7818 VBOXSTRICTRC rcStrict;
7819 RTGCPTR const GCPtrVal = u64Val;
7820 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7821 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7822 else
7823 {
7824 uint32_t u32Val;
7825 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7826 u64Val = u32Val;
7827 }
7828 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7829 {
7830 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7831 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7832 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7833 return rcStrict;
7834 }
7835 }
7836 else
7837 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7838
7839 /* Supported VMCS field. */
7840 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7841 { /* likely */ }
7842 else
7843 {
7844 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7846 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7847 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7848 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7849 return VINF_SUCCESS;
7850 }
7851
7852 /* Read-only VMCS field. */
7853 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7854 if ( !fIsFieldReadOnly
7855 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7856 { /* likely */ }
7857 else
7858 {
7859 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7860 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7861 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7862 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7863 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7864 return VINF_SUCCESS;
7865 }
7866
7867 /*
7868 * Write to the current or shadow VMCS.
7869 */
7870 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7871 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7872 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7873 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7874 Assert(pVmcs);
7875 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7876
7877 /* Notify HM that the VMCS content might have changed. */
7878 if (!fInVmxNonRootMode)
7879 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7880
7881 iemVmxVmSucceed(pVCpu);
7882 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7883 return VINF_SUCCESS;
7884}
7885
7886
7887/**
7888 * VMCLEAR instruction execution worker.
7889 *
7890 * @returns Strict VBox status code.
7891 * @param pVCpu The cross context virtual CPU structure.
7892 * @param cbInstr The instruction length in bytes.
7893 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7894 * @param GCPtrVmcs The linear address of the VMCS pointer.
7895 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7896 *
7897 * @remarks Common VMX instruction checks are already expected to by the caller,
7898 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7899 */
7900IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7901 PCVMXVEXITINFO pExitInfo)
7902{
7903 /* Nested-guest intercept. */
7904 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7905 {
7906 if (pExitInfo)
7907 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7908 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7909 }
7910
7911 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7912
7913 /* CPL. */
7914 if (pVCpu->iem.s.uCpl == 0)
7915 { /* likely */ }
7916 else
7917 {
7918 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7919 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7920 return iemRaiseGeneralProtectionFault0(pVCpu);
7921 }
7922
7923 /* Get the VMCS pointer from the location specified by the source memory operand. */
7924 RTGCPHYS GCPhysVmcs;
7925 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7926 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7927 { /* likely */ }
7928 else
7929 {
7930 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7931 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7932 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7933 return rcStrict;
7934 }
7935
7936 /* VMCS pointer alignment. */
7937 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7938 { /* likely */ }
7939 else
7940 {
7941 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7942 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7943 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7944 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7945 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7946 return VINF_SUCCESS;
7947 }
7948
7949 /* VMCS physical-address width limits. */
7950 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7951 { /* likely */ }
7952 else
7953 {
7954 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7955 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7956 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7957 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7958 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7959 return VINF_SUCCESS;
7960 }
7961
7962 /* VMCS is not the VMXON region. */
7963 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7964 { /* likely */ }
7965 else
7966 {
7967 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7968 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7969 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7970 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7971 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7972 return VINF_SUCCESS;
7973 }
7974
7975 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7976 restriction imposed by our implementation. */
7977 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7978 { /* likely */ }
7979 else
7980 {
7981 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7982 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7983 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7984 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7985 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7986 return VINF_SUCCESS;
7987 }
7988
7989 /*
7990 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7991 *
7992 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7993 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7994 * to 'clear'.
7995 */
7996 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7997 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7998 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7999 {
8000 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8001 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8002 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8003 }
8004 else
8005 {
8006 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8007 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8008 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8009 if (RT_FAILURE(rcStrict))
8010 return rcStrict;
8011 }
8012
8013 iemVmxVmSucceed(pVCpu);
8014 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8015 return VINF_SUCCESS;
8016}
8017
8018
8019/**
8020 * VMPTRST instruction execution worker.
8021 *
8022 * @returns Strict VBox status code.
8023 * @param pVCpu The cross context virtual CPU structure.
8024 * @param cbInstr The instruction length in bytes.
8025 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8026 * @param GCPtrVmcs The linear address of where to store the current VMCS
8027 * pointer.
8028 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8029 *
8030 * @remarks Common VMX instruction checks are already expected to by the caller,
8031 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8032 */
8033IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8034 PCVMXVEXITINFO pExitInfo)
8035{
8036 /* Nested-guest intercept. */
8037 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8038 {
8039 if (pExitInfo)
8040 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8041 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8042 }
8043
8044 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8045
8046 /* CPL. */
8047 if (pVCpu->iem.s.uCpl == 0)
8048 { /* likely */ }
8049 else
8050 {
8051 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8052 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8053 return iemRaiseGeneralProtectionFault0(pVCpu);
8054 }
8055
8056 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8057 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8058 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8059 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8060 {
8061 iemVmxVmSucceed(pVCpu);
8062 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8063 return rcStrict;
8064 }
8065
8066 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8067 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8068 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8069 return rcStrict;
8070}
8071
8072
8073/**
8074 * VMPTRLD instruction execution worker.
8075 *
8076 * @returns Strict VBox status code.
8077 * @param pVCpu The cross context virtual CPU structure.
8078 * @param cbInstr The instruction length in bytes.
8079 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8080 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8081 *
8082 * @remarks Common VMX instruction checks are already expected to by the caller,
8083 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8084 */
8085IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8086 PCVMXVEXITINFO pExitInfo)
8087{
8088 /* Nested-guest intercept. */
8089 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8090 {
8091 if (pExitInfo)
8092 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8093 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8094 }
8095
8096 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8097
8098 /* CPL. */
8099 if (pVCpu->iem.s.uCpl == 0)
8100 { /* likely */ }
8101 else
8102 {
8103 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8104 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8105 return iemRaiseGeneralProtectionFault0(pVCpu);
8106 }
8107
8108 /* Get the VMCS pointer from the location specified by the source memory operand. */
8109 RTGCPHYS GCPhysVmcs;
8110 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8111 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8112 { /* likely */ }
8113 else
8114 {
8115 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8116 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8117 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8118 return rcStrict;
8119 }
8120
8121 /* VMCS pointer alignment. */
8122 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8123 { /* likely */ }
8124 else
8125 {
8126 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8127 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8128 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8129 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8130 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8131 return VINF_SUCCESS;
8132 }
8133
8134 /* VMCS physical-address width limits. */
8135 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8136 { /* likely */ }
8137 else
8138 {
8139 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8140 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8141 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8142 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8143 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8144 return VINF_SUCCESS;
8145 }
8146
8147 /* VMCS is not the VMXON region. */
8148 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8149 { /* likely */ }
8150 else
8151 {
8152 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8153 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8154 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8155 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8156 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8157 return VINF_SUCCESS;
8158 }
8159
8160 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8161 restriction imposed by our implementation. */
8162 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8163 { /* likely */ }
8164 else
8165 {
8166 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8167 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8168 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8169 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8170 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8171 return VINF_SUCCESS;
8172 }
8173
8174 /* Read just the VMCS revision from the VMCS. */
8175 VMXVMCSREVID VmcsRevId;
8176 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8177 if (RT_SUCCESS(rc))
8178 { /* likely */ }
8179 else
8180 {
8181 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8182 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8183 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8184 return rc;
8185 }
8186
8187 /*
8188 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8189 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8190 */
8191 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8192 && ( !VmcsRevId.n.fIsShadowVmcs
8193 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8194 { /* likely */ }
8195 else
8196 {
8197 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8198 {
8199 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8200 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8201 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8202 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8203 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8204 return VINF_SUCCESS;
8205 }
8206
8207 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8209 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8210 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8211 return VINF_SUCCESS;
8212 }
8213
8214 /*
8215 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8216 * the cache of an existing, current VMCS back to guest memory before loading a new,
8217 * different current VMCS.
8218 */
8219 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8220 {
8221 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8222 {
8223 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8224 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8225 }
8226
8227 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8228 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8229 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8230 if (RT_SUCCESS(rc))
8231 {
8232 /* Notify HM that a new, current VMCS is loaded. */
8233 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8234 }
8235 else
8236 {
8237 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8238 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8239 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8240 return rc;
8241 }
8242 }
8243
8244 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8245 iemVmxVmSucceed(pVCpu);
8246 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8247 return VINF_SUCCESS;
8248}
8249
8250
8251/**
8252 * INVVPID instruction execution worker.
8253 *
8254 * @returns Strict VBox status code.
8255 * @param pVCpu The cross context virtual CPU structure.
8256 * @param cbInstr The instruction length in bytes.
8257 * @param iEffSeg The segment of the invvpid descriptor.
8258 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8259 * @param u64InvvpidType The invalidation type.
8260 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8261 * NULL.
8262 *
8263 * @remarks Common VMX instruction checks are already expected to by the caller,
8264 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8265 */
8266IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8267 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8268{
8269 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8270 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8271 return iemRaiseUndefinedOpcode(pVCpu);
8272
8273 /* Nested-guest intercept. */
8274 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8275 {
8276 if (pExitInfo)
8277 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8278 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8279 }
8280
8281 /* CPL. */
8282 if (pVCpu->iem.s.uCpl != 0)
8283 {
8284 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8285 return iemRaiseGeneralProtectionFault0(pVCpu);
8286 }
8287
8288 /*
8289 * Validate INVVPID invalidation type.
8290 *
8291 * The instruction specifies exactly ONE of the supported invalidation types.
8292 *
8293 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8294 * supported. In theory, it's possible for a CPU to not support flushing individual
8295 * addresses but all the other types or any other combination. We do not take any
8296 * shortcuts here by assuming the types we currently expose to the guest.
8297 */
8298 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8299 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8300 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8301 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8302 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8303 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8304 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8305 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8306 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8307 { /* likely */ }
8308 else
8309 {
8310 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8311 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8313 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315 return VINF_SUCCESS;
8316 }
8317
8318 /*
8319 * Fetch the invvpid descriptor from guest memory.
8320 */
8321 RTUINT128U uDesc;
8322 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8323 if (rcStrict == VINF_SUCCESS)
8324 {
8325 /*
8326 * Validate the descriptor.
8327 */
8328 if (uDesc.s.Lo > 0xfff)
8329 {
8330 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8331 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8332 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8333 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8335 return VINF_SUCCESS;
8336 }
8337
8338 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8339 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8340 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8341 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8342 switch (u64InvvpidType)
8343 {
8344 case VMXTLBFLUSHVPID_INDIV_ADDR:
8345 {
8346 if (uVpid != 0)
8347 {
8348 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8349 {
8350 /* Invalidate mappings for the linear address tagged with VPID. */
8351 /** @todo PGM support for VPID? Currently just flush everything. */
8352 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8353 iemVmxVmSucceed(pVCpu);
8354 }
8355 else
8356 {
8357 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8358 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8359 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8360 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8361 }
8362 }
8363 else
8364 {
8365 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8366 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8367 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8368 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8369 }
8370 break;
8371 }
8372
8373 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8374 {
8375 if (uVpid != 0)
8376 {
8377 /* Invalidate all mappings with VPID. */
8378 /** @todo PGM support for VPID? Currently just flush everything. */
8379 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8380 iemVmxVmSucceed(pVCpu);
8381 }
8382 else
8383 {
8384 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8385 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8386 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8387 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8388 }
8389 break;
8390 }
8391
8392 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8393 {
8394 /* Invalidate all mappings with non-zero VPIDs. */
8395 /** @todo PGM support for VPID? Currently just flush everything. */
8396 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8397 iemVmxVmSucceed(pVCpu);
8398 break;
8399 }
8400
8401 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8402 {
8403 if (uVpid != 0)
8404 {
8405 /* Invalidate all mappings with VPID except global translations. */
8406 /** @todo PGM support for VPID? Currently just flush everything. */
8407 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8408 iemVmxVmSucceed(pVCpu);
8409 }
8410 else
8411 {
8412 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8416 }
8417 break;
8418 }
8419 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8420 }
8421 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8422 }
8423 return rcStrict;
8424}
8425
8426
8427/**
8428 * VMXON instruction execution worker.
8429 *
8430 * @returns Strict VBox status code.
8431 * @param pVCpu The cross context virtual CPU structure.
8432 * @param cbInstr The instruction length in bytes.
8433 * @param iEffSeg The effective segment register to use with @a
8434 * GCPtrVmxon.
8435 * @param GCPtrVmxon The linear address of the VMXON pointer.
8436 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8437 *
8438 * @remarks Common VMX instruction checks are already expected to by the caller,
8439 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8440 */
8441IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8442 PCVMXVEXITINFO pExitInfo)
8443{
8444 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8445 {
8446 /* CPL. */
8447 if (pVCpu->iem.s.uCpl == 0)
8448 { /* likely */ }
8449 else
8450 {
8451 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8452 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8453 return iemRaiseGeneralProtectionFault0(pVCpu);
8454 }
8455
8456 /* A20M (A20 Masked) mode. */
8457 if (PGMPhysIsA20Enabled(pVCpu))
8458 { /* likely */ }
8459 else
8460 {
8461 Log(("vmxon: A20M mode -> #GP(0)\n"));
8462 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8463 return iemRaiseGeneralProtectionFault0(pVCpu);
8464 }
8465
8466 /* CR0. */
8467 {
8468 /* CR0 MB1 bits. */
8469 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8470 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8471 { /* likely */ }
8472 else
8473 {
8474 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8475 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8476 return iemRaiseGeneralProtectionFault0(pVCpu);
8477 }
8478
8479 /* CR0 MBZ bits. */
8480 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8481 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8482 { /* likely */ }
8483 else
8484 {
8485 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8486 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8487 return iemRaiseGeneralProtectionFault0(pVCpu);
8488 }
8489 }
8490
8491 /* CR4. */
8492 {
8493 /* CR4 MB1 bits. */
8494 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8495 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8496 { /* likely */ }
8497 else
8498 {
8499 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8500 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8501 return iemRaiseGeneralProtectionFault0(pVCpu);
8502 }
8503
8504 /* CR4 MBZ bits. */
8505 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8506 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8507 { /* likely */ }
8508 else
8509 {
8510 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8511 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8512 return iemRaiseGeneralProtectionFault0(pVCpu);
8513 }
8514 }
8515
8516 /* Feature control MSR's LOCK and VMXON bits. */
8517 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8518 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8519 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8520 { /* likely */ }
8521 else
8522 {
8523 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8524 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8525 return iemRaiseGeneralProtectionFault0(pVCpu);
8526 }
8527
8528 /* Get the VMXON pointer from the location specified by the source memory operand. */
8529 RTGCPHYS GCPhysVmxon;
8530 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8531 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8532 { /* likely */ }
8533 else
8534 {
8535 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8536 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8537 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8538 return rcStrict;
8539 }
8540
8541 /* VMXON region pointer alignment. */
8542 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8543 { /* likely */ }
8544 else
8545 {
8546 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8547 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8548 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8549 iemVmxVmFailInvalid(pVCpu);
8550 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8551 return VINF_SUCCESS;
8552 }
8553
8554 /* VMXON physical-address width limits. */
8555 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8556 { /* likely */ }
8557 else
8558 {
8559 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8560 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8561 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8562 iemVmxVmFailInvalid(pVCpu);
8563 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8564 return VINF_SUCCESS;
8565 }
8566
8567 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8568 restriction imposed by our implementation. */
8569 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8570 { /* likely */ }
8571 else
8572 {
8573 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8574 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8575 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8576 iemVmxVmFailInvalid(pVCpu);
8577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8578 return VINF_SUCCESS;
8579 }
8580
8581 /* Read the VMCS revision ID from the VMXON region. */
8582 VMXVMCSREVID VmcsRevId;
8583 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8584 if (RT_SUCCESS(rc))
8585 { /* likely */ }
8586 else
8587 {
8588 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8589 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8590 return rc;
8591 }
8592
8593 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8594 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8595 { /* likely */ }
8596 else
8597 {
8598 /* Revision ID mismatch. */
8599 if (!VmcsRevId.n.fIsShadowVmcs)
8600 {
8601 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8602 VmcsRevId.n.u31RevisionId));
8603 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8604 iemVmxVmFailInvalid(pVCpu);
8605 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8606 return VINF_SUCCESS;
8607 }
8608
8609 /* Shadow VMCS disallowed. */
8610 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8612 iemVmxVmFailInvalid(pVCpu);
8613 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8614 return VINF_SUCCESS;
8615 }
8616
8617 /*
8618 * Record that we're in VMX operation, block INIT, block and disable A20M.
8619 */
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8621 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8622 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8623
8624 /* Clear address-range monitoring. */
8625 EMMonitorWaitClear(pVCpu);
8626 /** @todo NSTVMX: Intel PT. */
8627
8628 iemVmxVmSucceed(pVCpu);
8629 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8630 return VINF_SUCCESS;
8631 }
8632 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8633 {
8634 /* Nested-guest intercept. */
8635 if (pExitInfo)
8636 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8637 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8638 }
8639
8640 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8641
8642 /* CPL. */
8643 if (pVCpu->iem.s.uCpl > 0)
8644 {
8645 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8646 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8647 return iemRaiseGeneralProtectionFault0(pVCpu);
8648 }
8649
8650 /* VMXON when already in VMX root mode. */
8651 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8653 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8654 return VINF_SUCCESS;
8655}
8656
8657
8658/**
8659 * Implements 'VMXOFF'.
8660 *
8661 * @remarks Common VMX instruction checks are already expected to by the caller,
8662 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8663 */
8664IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8665{
8666 /* Nested-guest intercept. */
8667 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8668 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8669
8670 /* CPL. */
8671 if (pVCpu->iem.s.uCpl == 0)
8672 { /* likely */ }
8673 else
8674 {
8675 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8676 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8677 return iemRaiseGeneralProtectionFault0(pVCpu);
8678 }
8679
8680 /* Dual monitor treatment of SMIs and SMM. */
8681 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8682 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8683 { /* likely */ }
8684 else
8685 {
8686 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8688 return VINF_SUCCESS;
8689 }
8690
8691 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8692 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8693 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8694
8695 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8696 { /** @todo NSTVMX: Unblock SMI. */ }
8697
8698 EMMonitorWaitClear(pVCpu);
8699 /** @todo NSTVMX: Unblock and enable A20M. */
8700
8701 iemVmxVmSucceed(pVCpu);
8702 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8703 return VINF_SUCCESS;
8704}
8705
8706
8707/**
8708 * Implements 'VMXON'.
8709 */
8710IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8711{
8712 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8713}
8714
8715
8716/**
8717 * Implements 'VMLAUNCH'.
8718 */
8719IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8720{
8721 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8722}
8723
8724
8725/**
8726 * Implements 'VMRESUME'.
8727 */
8728IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8729{
8730 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8731}
8732
8733
8734/**
8735 * Implements 'VMPTRLD'.
8736 */
8737IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8738{
8739 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8740}
8741
8742
8743/**
8744 * Implements 'VMPTRST'.
8745 */
8746IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8747{
8748 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8749}
8750
8751
8752/**
8753 * Implements 'VMCLEAR'.
8754 */
8755IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8756{
8757 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8758}
8759
8760
8761/**
8762 * Implements 'VMWRITE' register.
8763 */
8764IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8765{
8766 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8767}
8768
8769
8770/**
8771 * Implements 'VMWRITE' memory.
8772 */
8773IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8774{
8775 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8776}
8777
8778
8779/**
8780 * Implements 'VMREAD' register (64-bit).
8781 */
8782IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8783{
8784 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8785}
8786
8787
8788/**
8789 * Implements 'VMREAD' register (32-bit).
8790 */
8791IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8792{
8793 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8794}
8795
8796
8797/**
8798 * Implements 'VMREAD' memory, 64-bit register.
8799 */
8800IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8801{
8802 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8803}
8804
8805
8806/**
8807 * Implements 'VMREAD' memory, 32-bit register.
8808 */
8809IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8810{
8811 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8812}
8813
8814
8815/**
8816 * Implements 'INVVPID'.
8817 */
8818IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8819{
8820 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8821}
8822
8823
8824/**
8825 * Implements VMX's implementation of PAUSE.
8826 */
8827IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8828{
8829 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8830 {
8831 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8832 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8833 return rcStrict;
8834 }
8835
8836 /*
8837 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8838 * a VM-exit, the instruction operates normally.
8839 */
8840 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8841 return VINF_SUCCESS;
8842}
8843
8844#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8845
8846
8847/**
8848 * Implements 'VMCALL'.
8849 */
8850IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8851{
8852#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8853 /* Nested-guest intercept. */
8854 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8855 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8856#endif
8857
8858 /* Join forces with vmmcall. */
8859 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8860}
8861
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