VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 80572

Last change on this file since 80572 was 80572, checked in by vboxsync, 5 years ago

VMM/IEM: Nested VMX: bugref:9180 Logging.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 80572 2019-09-04 04:39:54Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_APIC_ACCESS
177 * VMX_EXIT_EPT_VIOLATION
178 * VMX_EXIT_EPT_MISCONFIG
179 * VMX_EXIT_INVEPT
180 * VMX_EXIT_RDRAND
181 * VMX_EXIT_VMFUNC
182 * VMX_EXIT_ENCLS
183 * VMX_EXIT_RDSEED
184 * VMX_EXIT_PML_FULL
185 * VMX_EXIT_XSAVES
186 * VMX_EXIT_XRSTORS
187 */
188/**
189 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
190 *
191 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
192 * second dimension is the Index, see VMXVMCSFIELD.
193 */
194uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
195{
196 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
197 {
198 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
199 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
200 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
201 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-25 */ UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
226 },
227 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
228 {
229 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
230 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
231 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
232 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
233 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
234 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
235 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
236 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239 },
240 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
241 {
242 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
243 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
244 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
245 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
246 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
247 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
248 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
249 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
250 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
251 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
252 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
253 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
254 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
255 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
256 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
257 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
258 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
259 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
260 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
261 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
262 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
263 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
264 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
265 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
266 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
267 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
268 },
269 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
270 {
271 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
272 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
275 /* 25 */ UINT16_MAX
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
280 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
281 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
282 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
283 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
284 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
285 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
286 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
287 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
288 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
289 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
290 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
291 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
292 },
293 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
294 {
295 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
296 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
297 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
298 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
300 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
301 },
302 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
303 {
304 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
305 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
306 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
307 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
308 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
309 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
310 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
311 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
312 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
313 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
314 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
315 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
316 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
317 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
318 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
319 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
320 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
321 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
334 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 24-25 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
348 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
349 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
350 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
351 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
352 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
353 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
354 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
355 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
356 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
357 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
358 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
359 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
360 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
361 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
362 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Sets the guest pending-debug exceptions field.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
788 */
789DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
790{
791 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
792 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
793 pVmcs->u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
794}
795
796
797/**
798 * Implements VMSucceed for VMX instruction success.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
803{
804 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
805}
806
807
808/**
809 * Implements VMFailInvalid for VMX instruction failure.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
814{
815 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
816}
817
818
819/**
820 * Implements VMFail for VMX instruction failure.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param enmInsErr The VM instruction error.
824 */
825DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
826{
827 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
828}
829
830
831/**
832 * Checks if the given auto-load/store MSR area count is valid for the
833 * implementation.
834 *
835 * @returns @c true if it's within the valid limit, @c false otherwise.
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param uMsrCount The MSR area count to check.
838 */
839DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
840{
841 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
842 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
843 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
844 if (uMsrCount <= cMaxSupportedMsrs)
845 return true;
846 return false;
847}
848
849
850/**
851 * Flushes the current VMCS contents back to guest memory.
852 *
853 * @returns VBox status code.
854 * @param pVCpu The cross context virtual CPU structure.
855 */
856DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
857{
858 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
859 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
860 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
861 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
862 return rc;
863}
864
865
866/**
867 * Populates the current VMCS contents from guest memory.
868 *
869 * @returns VBox status code.
870 * @param pVCpu The cross context virtual CPU structure.
871 */
872DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
873{
874 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
875 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
877 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
878 return rc;
879}
880
881
882/**
883 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
884 *
885 * @param pVCpu The cross context virtual CPU structure.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
888{
889 iemVmxVmSucceed(pVCpu);
890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
891}
892
893
894/**
895 * Gets the instruction diagnostic for segment base checks during VM-entry of a
896 * nested-guest.
897 *
898 * @param iSegReg The segment index (X86_SREG_XXX).
899 */
900IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
901{
902 switch (iSegReg)
903 {
904 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
905 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
906 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
907 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
908 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
909 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
910 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
911 }
912}
913
914
915/**
916 * Gets the instruction diagnostic for segment base checks during VM-entry of a
917 * nested-guest that is in Virtual-8086 mode.
918 *
919 * @param iSegReg The segment index (X86_SREG_XXX).
920 */
921IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
922{
923 switch (iSegReg)
924 {
925 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
926 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
927 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
928 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
929 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
930 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
931 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
932 }
933}
934
935
936/**
937 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
938 * nested-guest that is in Virtual-8086 mode.
939 *
940 * @param iSegReg The segment index (X86_SREG_XXX).
941 */
942IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
943{
944 switch (iSegReg)
945 {
946 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
947 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
948 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
949 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
950 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
951 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
952 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
953 }
954}
955
956
957/**
958 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
959 * nested-guest that is in Virtual-8086 mode.
960 *
961 * @param iSegReg The segment index (X86_SREG_XXX).
962 */
963IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
964{
965 switch (iSegReg)
966 {
967 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
968 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
969 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
970 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
971 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
972 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
973 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
974 }
975}
976
977
978/**
979 * Gets the instruction diagnostic for segment attributes reserved bits failure
980 * during VM-entry of a nested-guest.
981 *
982 * @param iSegReg The segment index (X86_SREG_XXX).
983 */
984IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
985{
986 switch (iSegReg)
987 {
988 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
989 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
990 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
991 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
992 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
993 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
994 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
995 }
996}
997
998
999/**
1000 * Gets the instruction diagnostic for segment attributes descriptor-type
1001 * (code/segment or system) failure during VM-entry of a nested-guest.
1002 *
1003 * @param iSegReg The segment index (X86_SREG_XXX).
1004 */
1005IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1006{
1007 switch (iSegReg)
1008 {
1009 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1010 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1011 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1012 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1013 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1014 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1015 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1016 }
1017}
1018
1019
1020/**
1021 * Gets the instruction diagnostic for segment attributes descriptor-type
1022 * (code/segment or system) failure during VM-entry of a nested-guest.
1023 *
1024 * @param iSegReg The segment index (X86_SREG_XXX).
1025 */
1026IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1027{
1028 switch (iSegReg)
1029 {
1030 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1031 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1032 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1033 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1034 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1035 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1036 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1037 }
1038}
1039
1040
1041/**
1042 * Gets the instruction diagnostic for segment attribute granularity failure during
1043 * VM-entry of a nested-guest.
1044 *
1045 * @param iSegReg The segment index (X86_SREG_XXX).
1046 */
1047IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1048{
1049 switch (iSegReg)
1050 {
1051 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1052 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1053 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1054 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1055 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1056 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1057 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1058 }
1059}
1060
1061/**
1062 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1063 * VM-entry of a nested-guest.
1064 *
1065 * @param iSegReg The segment index (X86_SREG_XXX).
1066 */
1067IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1068{
1069 switch (iSegReg)
1070 {
1071 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1072 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1073 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1074 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1075 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1076 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1077 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1078 }
1079}
1080
1081
1082/**
1083 * Gets the instruction diagnostic for segment attribute type accessed failure
1084 * during VM-entry of a nested-guest.
1085 *
1086 * @param iSegReg The segment index (X86_SREG_XXX).
1087 */
1088IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1089{
1090 switch (iSegReg)
1091 {
1092 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1093 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1094 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1095 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1096 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1097 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1098 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1099 }
1100}
1101
1102
1103/**
1104 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1105 * failure during VM-entry of a nested-guest.
1106 *
1107 * @param iSegReg The PDPTE entry index.
1108 */
1109IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1110{
1111 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1112 switch (iPdpte)
1113 {
1114 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1115 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1116 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1117 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1118 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1119 }
1120}
1121
1122
1123/**
1124 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1125 * failure during VM-exit of a nested-guest.
1126 *
1127 * @param iSegReg The PDPTE entry index.
1128 */
1129IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1130{
1131 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1132 switch (iPdpte)
1133 {
1134 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1135 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1136 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1137 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1138 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1139 }
1140}
1141
1142
1143/**
1144 * Saves the guest control registers, debug registers and some MSRs are part of
1145 * VM-exit.
1146 *
1147 * @param pVCpu The cross context virtual CPU structure.
1148 */
1149IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1150{
1151 /*
1152 * Saves the guest control registers, debug registers and some MSRs.
1153 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1154 */
1155 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1156
1157 /* Save control registers. */
1158 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1159 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1160 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1161
1162 /* Save SYSENTER CS, ESP, EIP. */
1163 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1165 {
1166 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1167 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1168 }
1169 else
1170 {
1171 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1172 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1173 }
1174
1175 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1176 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1177 {
1178 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1179 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1180 }
1181
1182 /* Save PAT MSR. */
1183 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1184 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1185
1186 /* Save EFER MSR. */
1187 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1188 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1189
1190 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1191 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1192
1193 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1194}
1195
1196
1197/**
1198 * Saves the guest force-flags in preparation of entering the nested-guest.
1199 *
1200 * @param pVCpu The cross context virtual CPU structure.
1201 */
1202IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1203{
1204 /* We shouldn't be called multiple times during VM-entry. */
1205 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1206
1207 /* MTF should not be set outside VMX non-root mode. */
1208 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1209
1210 /*
1211 * Preserve the required force-flags.
1212 *
1213 * We cache and clear force-flags that would affect the execution of the
1214 * nested-guest. Cached flags are then restored while returning to the guest
1215 * if necessary.
1216 *
1217 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1218 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1219 * instruction. Interrupt inhibition for any nested-guest instruction
1220 * is supplied by the guest-interruptibility state VMCS field and will
1221 * be set up as part of loading the guest state.
1222 *
1223 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1224 * successful VM-entry (due to invalid guest-state) need to continue
1225 * blocking NMIs if it was in effect before VM-entry.
1226 *
1227 * - MTF need not be preserved as it's used only in VMX non-root mode and
1228 * is supplied through the VM-execution controls.
1229 *
1230 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1231 * we will be able to generate interrupts that may cause VM-exits for
1232 * the nested-guest.
1233 */
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1235}
1236
1237
1238/**
1239 * Restores the guest force-flags in preparation of exiting the nested-guest.
1240 *
1241 * @param pVCpu The cross context virtual CPU structure.
1242 */
1243IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1244{
1245 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1246 {
1247 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1248 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1249 }
1250}
1251
1252
1253/**
1254 * Perform a VMX transition updated PGM, IEM and CPUM.
1255 *
1256 * @param pVCpu The cross context virtual CPU structure.
1257 */
1258IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1259{
1260 /*
1261 * Inform PGM about paging mode changes.
1262 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1263 * see comment in iemMemPageTranslateAndCheckAccess().
1264 */
1265 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1266# ifdef IN_RING3
1267 Assert(rc != VINF_PGM_CHANGE_MODE);
1268# endif
1269 AssertRCReturn(rc, rc);
1270
1271 /* Inform CPUM (recompiler), can later be removed. */
1272 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1273
1274 /*
1275 * Flush the TLB with new CR3. This is required in case the PGM mode change
1276 * above doesn't actually change anything.
1277 */
1278 if (rc == VINF_SUCCESS)
1279 {
1280 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1281 AssertRCReturn(rc, rc);
1282 }
1283
1284 /* Re-initialize IEM cache/state after the drastic mode switch. */
1285 iemReInitExec(pVCpu);
1286 return rc;
1287}
1288
1289
1290/**
1291 * Calculates the current VMX-preemption timer value.
1292 *
1293 * @returns The current VMX-preemption timer value.
1294 * @param pVCpu The cross context virtual CPU structure.
1295 */
1296IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1297{
1298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1299 Assert(pVmcs);
1300
1301 /*
1302 * Assume the following:
1303 * PreemptTimerShift = 5
1304 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1305 * EntryTick = 50000 (TSC at time of VM-entry)
1306 *
1307 * CurTick Delta PreemptTimerVal
1308 * ----------------------------------
1309 * 60000 10000 2
1310 * 80000 30000 1
1311 * 90000 40000 0 -> VM-exit.
1312 *
1313 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1314 * The saved VMX-preemption timer value is calculated as follows:
1315 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1316 * E.g.:
1317 * Delta = 10000
1318 * Tmp = 10000 / (2 * 10000) = 0.5
1319 * NewPt = 2 - 0.5 = 2
1320 * Delta = 30000
1321 * Tmp = 30000 / (2 * 10000) = 1.5
1322 * NewPt = 2 - 1.5 = 1
1323 * Delta = 40000
1324 * Tmp = 40000 / 20000 = 2
1325 * NewPt = 2 - 2 = 0
1326 */
1327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1328 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1329 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1330 uint64_t const uDelta = uCurTick - uEntryTick;
1331 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1332 uint32_t const uPreemptTimer = uVmcsPreemptVal
1333 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1334 return uPreemptTimer;
1335}
1336
1337
1338/**
1339 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1340 *
1341 * @param pVCpu The cross context virtual CPU structure.
1342 */
1343IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1344{
1345 /*
1346 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1347 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1348 */
1349 /* CS, SS, ES, DS, FS, GS. */
1350 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1351 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1352 {
1353 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1354 if (!pSelReg->Attr.n.u1Unusable)
1355 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1356 else
1357 {
1358 /*
1359 * For unusable segments the attributes are undefined except for CS and SS.
1360 * For the rest we don't bother preserving anything but the unusable bit.
1361 */
1362 switch (iSegReg)
1363 {
1364 case X86_SREG_CS:
1365 pVmcs->GuestCs = pSelReg->Sel;
1366 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1367 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1368 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1369 | X86DESCATTR_UNUSABLE);
1370 break;
1371
1372 case X86_SREG_SS:
1373 pVmcs->GuestSs = pSelReg->Sel;
1374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1375 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1376 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_DS:
1380 pVmcs->GuestDs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1384 break;
1385
1386 case X86_SREG_ES:
1387 pVmcs->GuestEs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_FS:
1394 pVmcs->GuestFs = pSelReg->Sel;
1395 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1396 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1397 break;
1398
1399 case X86_SREG_GS:
1400 pVmcs->GuestGs = pSelReg->Sel;
1401 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1403 break;
1404 }
1405 }
1406 }
1407
1408 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1409 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1410 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1411 | X86DESCATTR_UNUSABLE;
1412 /* LDTR. */
1413 {
1414 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1415 pVmcs->GuestLdtr = pSelReg->Sel;
1416 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1417 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1418 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1419 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1420 }
1421
1422 /* TR. */
1423 {
1424 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1425 pVmcs->GuestTr = pSelReg->Sel;
1426 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1427 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1428 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1429 }
1430
1431 /* GDTR. */
1432 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1433 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1434
1435 /* IDTR. */
1436 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1437 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1438}
1439
1440
1441/**
1442 * Saves guest non-register state as part of VM-exit.
1443 *
1444 * @param pVCpu The cross context virtual CPU structure.
1445 * @param uExitReason The VM-exit reason.
1446 */
1447IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1448{
1449 /*
1450 * Save guest non-register state.
1451 * See Intel spec. 27.3.4 "Saving Non-Register State".
1452 */
1453 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1454
1455 /*
1456 * Activity state.
1457 * Most VM-exits will occur in the active state. However, if the first instruction
1458 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1459 * the VM-exit will be from the HLT activity state.
1460 *
1461 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1462 */
1463 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1464 * not? */
1465 EMSTATE const enmActivityState = EMGetState(pVCpu);
1466 switch (enmActivityState)
1467 {
1468 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1469 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1470 }
1471
1472 /*
1473 * Interruptibility-state.
1474 */
1475 /* NMI. */
1476 pVmcs->u32GuestIntrState = 0;
1477 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1478 {
1479 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1480 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1481 }
1482 else
1483 {
1484 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1485 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1486 }
1487
1488 /* Blocking-by-STI. */
1489 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1490 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1491 {
1492 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1493 * currently. */
1494 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1495 }
1496 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1497
1498 /*
1499 * Pending debug exceptions.
1500 *
1501 * For VM-exits where it is not applicable, we can safely zero out the field.
1502 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1503 */
1504 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1505 && uExitReason != VMX_EXIT_SMI
1506 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1507 && !VMXIsVmexitTrapLike(uExitReason))
1508 {
1509 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1510 * block-by-MovSS is in effect. */
1511 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1512 }
1513
1514 /*
1515 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1516 *
1517 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1518 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1519 */
1520 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1521 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1522 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1523
1524 /* PDPTEs. */
1525 /* We don't support EPT yet. */
1526 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1527 pVmcs->u64GuestPdpte0.u = 0;
1528 pVmcs->u64GuestPdpte1.u = 0;
1529 pVmcs->u64GuestPdpte2.u = 0;
1530 pVmcs->u64GuestPdpte3.u = 0;
1531}
1532
1533
1534/**
1535 * Saves the guest-state as part of VM-exit.
1536 *
1537 * @returns VBox status code.
1538 * @param pVCpu The cross context virtual CPU structure.
1539 * @param uExitReason The VM-exit reason.
1540 */
1541IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1542{
1543 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1544 Assert(pVmcs);
1545
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1571 const char *const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the guest hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 Assert(pMsr);
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and fixed CR0 bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ffaffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1717 }
1718
1719 /* CR4. */
1720 {
1721 /* Fixed CR4 bits are not modified. */
1722 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1723 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1724 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1725 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1726 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1727 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1728 if (fHostInLongMode)
1729 uValidHostCr4 |= X86_CR4_PAE;
1730 else
1731 uValidHostCr4 &= ~X86_CR4_PCIDE;
1732 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1733 }
1734
1735 /* CR3 (host value validated while checking host-state during VM-entry). */
1736 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1737
1738 /* DR7. */
1739 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1740
1741 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1742
1743 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1745 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1746 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1747
1748 /* FS, GS bases are loaded later while we load host segment registers. */
1749
1750 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1751 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1752 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1753 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1754 {
1755 if (fHostInLongMode)
1756 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1757 else
1758 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1759 }
1760
1761 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1762
1763 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1764 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1765 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1766
1767 /* We don't support IA32_BNDCFGS MSR yet. */
1768}
1769
1770
1771/**
1772 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1773 *
1774 * @param pVCpu The cross context virtual CPU structure.
1775 */
1776IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1777{
1778 /*
1779 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1780 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1781 *
1782 * Warning! Be careful to not touch fields that are reserved by VT-x,
1783 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1784 */
1785 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1786 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1787
1788 /* CS, SS, ES, DS, FS, GS. */
1789 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1790 {
1791 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1792 bool const fUnusable = RT_BOOL(HostSel == 0);
1793 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1794
1795 /* Selector. */
1796 pSelReg->Sel = HostSel;
1797 pSelReg->ValidSel = HostSel;
1798 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1799
1800 /* Limit. */
1801 pSelReg->u32Limit = 0xffffffff;
1802
1803 /* Base. */
1804 pSelReg->u64Base = 0;
1805
1806 /* Attributes. */
1807 if (iSegReg == X86_SREG_CS)
1808 {
1809 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1810 pSelReg->Attr.n.u1DescType = 1;
1811 pSelReg->Attr.n.u2Dpl = 0;
1812 pSelReg->Attr.n.u1Present = 1;
1813 pSelReg->Attr.n.u1Long = fHostInLongMode;
1814 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1815 pSelReg->Attr.n.u1Granularity = 1;
1816 Assert(!pSelReg->Attr.n.u1Unusable);
1817 Assert(!fUnusable);
1818 }
1819 else
1820 {
1821 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1822 pSelReg->Attr.n.u1DescType = 1;
1823 pSelReg->Attr.n.u2Dpl = 0;
1824 pSelReg->Attr.n.u1Present = 1;
1825 pSelReg->Attr.n.u1DefBig = 1;
1826 pSelReg->Attr.n.u1Granularity = 1;
1827 pSelReg->Attr.n.u1Unusable = fUnusable;
1828 }
1829 }
1830
1831 /* FS base. */
1832 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1833 || fHostInLongMode)
1834 {
1835 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1836 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1837 }
1838
1839 /* GS base. */
1840 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1844 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1845 }
1846
1847 /* TR. */
1848 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1849 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1850 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1851 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1852 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1853 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1854 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1856 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1858 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1859 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1860 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1861
1862 /* LDTR (Warning! do not touch the base and limits here). */
1863 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1864 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1865 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1866 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1867
1868 /* GDTR. */
1869 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1870 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1871 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1872
1873 /* IDTR.*/
1874 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1875 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1876 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1877}
1878
1879
1880/**
1881 * Checks host PDPTes as part of VM-exit.
1882 *
1883 * @param pVCpu The cross context virtual CPU structure.
1884 * @param uExitReason The VM-exit reason (for logging purposes).
1885 */
1886IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1887{
1888 /*
1889 * Check host PDPTEs.
1890 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1891 */
1892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1893 const char *const pszFailure = "VMX-abort";
1894 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1895
1896 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1897 && !fHostInLongMode)
1898 {
1899 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1900 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1901 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1902 if (RT_SUCCESS(rc))
1903 {
1904 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1905 {
1906 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1907 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1908 { /* likely */ }
1909 else
1910 {
1911 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1912 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1913 }
1914 }
1915 }
1916 else
1917 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1918 }
1919
1920 NOREF(pszFailure);
1921 NOREF(uExitReason);
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/**
1927 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1928 *
1929 * @returns VBox status code.
1930 * @param pVCpu The cross context virtual CPU structure.
1931 * @param pszInstr The VMX instruction name (for logging purposes).
1932 */
1933IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1934{
1935 /*
1936 * Load host MSRs.
1937 * See Intel spec. 27.6 "Loading MSRs".
1938 */
1939 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1940 const char *const pszFailure = "VMX-abort";
1941
1942 /*
1943 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1944 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1945 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1946 */
1947 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1948 if (!cMsrs)
1949 return VINF_SUCCESS;
1950
1951 /*
1952 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1953 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1954 * implementation causes a VMX-abort followed by a triple-fault.
1955 */
1956 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1957 if (fIsMsrCountValid)
1958 { /* likely */ }
1959 else
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1961
1962 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1963 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1964 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1965 if (RT_SUCCESS(rc))
1966 {
1967 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1968 Assert(pMsr);
1969 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1970 {
1971 if ( !pMsr->u32Reserved
1972 && pMsr->u32Msr != MSR_K8_FS_BASE
1973 && pMsr->u32Msr != MSR_K8_GS_BASE
1974 && pMsr->u32Msr != MSR_K6_EFER
1975 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1976 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1977 {
1978 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1979 if (rcStrict == VINF_SUCCESS)
1980 continue;
1981
1982 /*
1983 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1984 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1985 * recording the MSR index in the auxiliary info. field and indicated further by our
1986 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1987 * if possible, or come up with a better, generic solution.
1988 */
1989 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1990 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1991 ? kVmxVDiag_Vmexit_MsrLoadRing3
1992 : kVmxVDiag_Vmexit_MsrLoad;
1993 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1994 }
1995 else
1996 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1997 }
1998 }
1999 else
2000 {
2001 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2003 }
2004
2005 NOREF(uExitReason);
2006 NOREF(pszFailure);
2007 return VINF_SUCCESS;
2008}
2009
2010
2011/**
2012 * Loads the host state as part of VM-exit.
2013 *
2014 * @returns Strict VBox status code.
2015 * @param pVCpu The cross context virtual CPU structure.
2016 * @param uExitReason The VM-exit reason (for logging purposes).
2017 */
2018IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2019{
2020 /*
2021 * Load host state.
2022 * See Intel spec. 27.5 "Loading Host State".
2023 */
2024 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2025 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2026
2027 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2028 if ( CPUMIsGuestInLongMode(pVCpu)
2029 && !fHostInLongMode)
2030 {
2031 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2032 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2033 }
2034
2035 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2036 iemVmxVmexitLoadHostSegRegs(pVCpu);
2037
2038 /*
2039 * Load host RIP, RSP and RFLAGS.
2040 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2041 */
2042 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2043 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2044 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2045
2046 /* Clear address range monitoring. */
2047 EMMonitorWaitClear(pVCpu);
2048
2049 /* Perform the VMX transition (PGM updates). */
2050 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2051 if (rcStrict == VINF_SUCCESS)
2052 {
2053 /* Check host PDPTEs (only when we've fully switched page tables_. */
2054 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2055 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2056 if (RT_FAILURE(rc))
2057 {
2058 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2059 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2060 }
2061 }
2062 else if (RT_SUCCESS(rcStrict))
2063 {
2064 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2065 uExitReason));
2066 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2067 }
2068 else
2069 {
2070 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2071 return VBOXSTRICTRC_VAL(rcStrict);
2072 }
2073
2074 Assert(rcStrict == VINF_SUCCESS);
2075
2076 /* Load MSRs from the VM-exit auto-load MSR area. */
2077 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2078 if (RT_FAILURE(rc))
2079 {
2080 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2081 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2082 }
2083 return VINF_SUCCESS;
2084}
2085
2086
2087/**
2088 * Gets VM-exit instruction information along with any displacement for an
2089 * instruction VM-exit.
2090 *
2091 * @returns The VM-exit instruction information.
2092 * @param pVCpu The cross context virtual CPU structure.
2093 * @param uExitReason The VM-exit reason.
2094 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2095 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2096 * NULL.
2097 */
2098IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2099{
2100 RTGCPTR GCPtrDisp;
2101 VMXEXITINSTRINFO ExitInstrInfo;
2102 ExitInstrInfo.u = 0;
2103
2104 /*
2105 * Get and parse the ModR/M byte from our decoded opcodes.
2106 */
2107 uint8_t bRm;
2108 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2109 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2110 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2111 {
2112 /*
2113 * ModR/M indicates register addressing.
2114 *
2115 * The primary/secondary register operands are reported in the iReg1 or iReg2
2116 * fields depending on whether it is a read/write form.
2117 */
2118 uint8_t idxReg1;
2119 uint8_t idxReg2;
2120 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2121 {
2122 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2123 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2124 }
2125 else
2126 {
2127 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2128 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2129 }
2130 ExitInstrInfo.All.u2Scaling = 0;
2131 ExitInstrInfo.All.iReg1 = idxReg1;
2132 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2133 ExitInstrInfo.All.fIsRegOperand = 1;
2134 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2135 ExitInstrInfo.All.iSegReg = 0;
2136 ExitInstrInfo.All.iIdxReg = 0;
2137 ExitInstrInfo.All.fIdxRegInvalid = 1;
2138 ExitInstrInfo.All.iBaseReg = 0;
2139 ExitInstrInfo.All.fBaseRegInvalid = 1;
2140 ExitInstrInfo.All.iReg2 = idxReg2;
2141
2142 /* Displacement not applicable for register addressing. */
2143 GCPtrDisp = 0;
2144 }
2145 else
2146 {
2147 /*
2148 * ModR/M indicates memory addressing.
2149 */
2150 uint8_t uScale = 0;
2151 bool fBaseRegValid = false;
2152 bool fIdxRegValid = false;
2153 uint8_t iBaseReg = 0;
2154 uint8_t iIdxReg = 0;
2155 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2156 {
2157 /*
2158 * Parse the ModR/M, displacement for 16-bit addressing mode.
2159 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2160 */
2161 uint16_t u16Disp = 0;
2162 uint8_t const offDisp = offModRm + sizeof(bRm);
2163 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2164 {
2165 /* Displacement without any registers. */
2166 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2167 }
2168 else
2169 {
2170 /* Register (index and base). */
2171 switch (bRm & X86_MODRM_RM_MASK)
2172 {
2173 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2174 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2175 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2176 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2177 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2178 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2179 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2180 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2181 }
2182
2183 /* Register + displacement. */
2184 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2185 {
2186 case 0: break;
2187 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2188 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2189 default:
2190 {
2191 /* Register addressing, handled at the beginning. */
2192 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2193 break;
2194 }
2195 }
2196 }
2197
2198 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2199 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2200 }
2201 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2202 {
2203 /*
2204 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2205 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2206 */
2207 uint32_t u32Disp = 0;
2208 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2209 {
2210 /* Displacement without any registers. */
2211 uint8_t const offDisp = offModRm + sizeof(bRm);
2212 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2213 }
2214 else
2215 {
2216 /* Register (and perhaps scale, index and base). */
2217 uint8_t offDisp = offModRm + sizeof(bRm);
2218 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2219 if (iBaseReg == 4)
2220 {
2221 /* An SIB byte follows the ModR/M byte, parse it. */
2222 uint8_t bSib;
2223 uint8_t const offSib = offModRm + sizeof(bRm);
2224 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2225
2226 /* A displacement may follow SIB, update its offset. */
2227 offDisp += sizeof(bSib);
2228
2229 /* Get the scale. */
2230 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2231
2232 /* Get the index register. */
2233 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2234 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2235
2236 /* Get the base register. */
2237 iBaseReg = bSib & X86_SIB_BASE_MASK;
2238 fBaseRegValid = true;
2239 if (iBaseReg == 5)
2240 {
2241 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2242 {
2243 /* Mod is 0 implies a 32-bit displacement with no base. */
2244 fBaseRegValid = false;
2245 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2246 }
2247 else
2248 {
2249 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2250 iBaseReg = X86_GREG_xBP;
2251 }
2252 }
2253 }
2254
2255 /* Register + displacement. */
2256 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2257 {
2258 case 0: /* Handled above */ break;
2259 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2260 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2261 default:
2262 {
2263 /* Register addressing, handled at the beginning. */
2264 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2265 break;
2266 }
2267 }
2268 }
2269
2270 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2271 }
2272 else
2273 {
2274 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2275
2276 /*
2277 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2278 * See Intel instruction spec. 2.2 "IA-32e Mode".
2279 */
2280 uint64_t u64Disp = 0;
2281 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2282 if (fRipRelativeAddr)
2283 {
2284 /*
2285 * RIP-relative addressing mode.
2286 *
2287 * The displacement is 32-bit signed implying an offset range of +/-2G.
2288 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2289 */
2290 uint8_t const offDisp = offModRm + sizeof(bRm);
2291 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2292 }
2293 else
2294 {
2295 uint8_t offDisp = offModRm + sizeof(bRm);
2296
2297 /*
2298 * Register (and perhaps scale, index and base).
2299 *
2300 * REX.B extends the most-significant bit of the base register. However, REX.B
2301 * is ignored while determining whether an SIB follows the opcode. Hence, we
2302 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2303 *
2304 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2305 */
2306 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2307 if (iBaseReg == 4)
2308 {
2309 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2310 uint8_t bSib;
2311 uint8_t const offSib = offModRm + sizeof(bRm);
2312 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2313
2314 /* Displacement may follow SIB, update its offset. */
2315 offDisp += sizeof(bSib);
2316
2317 /* Get the scale. */
2318 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2319
2320 /* Get the index. */
2321 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2322 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2323
2324 /* Get the base. */
2325 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2326 fBaseRegValid = true;
2327 if (iBaseReg == 5)
2328 {
2329 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2330 {
2331 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2332 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2333 }
2334 else
2335 {
2336 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2337 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2338 }
2339 }
2340 }
2341 iBaseReg |= pVCpu->iem.s.uRexB;
2342
2343 /* Register + displacement. */
2344 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2345 {
2346 case 0: /* Handled above */ break;
2347 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2348 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2349 default:
2350 {
2351 /* Register addressing, handled at the beginning. */
2352 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2353 break;
2354 }
2355 }
2356 }
2357
2358 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2359 }
2360
2361 /*
2362 * The primary or secondary register operand is reported in iReg2 depending
2363 * on whether the primary operand is in read/write form.
2364 */
2365 uint8_t idxReg2;
2366 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2367 {
2368 idxReg2 = bRm & X86_MODRM_RM_MASK;
2369 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2370 idxReg2 |= pVCpu->iem.s.uRexB;
2371 }
2372 else
2373 {
2374 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2375 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2376 idxReg2 |= pVCpu->iem.s.uRexReg;
2377 }
2378 ExitInstrInfo.All.u2Scaling = uScale;
2379 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2380 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2381 ExitInstrInfo.All.fIsRegOperand = 0;
2382 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2383 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2384 ExitInstrInfo.All.iIdxReg = iIdxReg;
2385 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2386 ExitInstrInfo.All.iBaseReg = iBaseReg;
2387 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2388 ExitInstrInfo.All.iReg2 = idxReg2;
2389 }
2390
2391 /*
2392 * Handle exceptions to the norm for certain instructions.
2393 * (e.g. some instructions convey an instruction identity in place of iReg2).
2394 */
2395 switch (uExitReason)
2396 {
2397 case VMX_EXIT_GDTR_IDTR_ACCESS:
2398 {
2399 Assert(VMXINSTRID_IS_VALID(uInstrId));
2400 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2401 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2402 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2403 break;
2404 }
2405
2406 case VMX_EXIT_LDTR_TR_ACCESS:
2407 {
2408 Assert(VMXINSTRID_IS_VALID(uInstrId));
2409 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2410 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2411 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2412 break;
2413 }
2414
2415 case VMX_EXIT_RDRAND:
2416 case VMX_EXIT_RDSEED:
2417 {
2418 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2419 break;
2420 }
2421 }
2422
2423 /* Update displacement and return the constructed VM-exit instruction information field. */
2424 if (pGCPtrDisp)
2425 *pGCPtrDisp = GCPtrDisp;
2426
2427 return ExitInstrInfo.u;
2428}
2429
2430
2431/**
2432 * VMX VM-exit handler.
2433 *
2434 * @returns Strict VBox status code.
2435 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2436 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2437 * triple-fault.
2438 *
2439 * @param pVCpu The cross context virtual CPU structure.
2440 * @param uExitReason The VM-exit reason.
2441 * @param u64ExitQual The Exit qualification.
2442 */
2443IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2444{
2445# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2446 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2447 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2448 return VERR_IEM_IPE_7;
2449# else
2450 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2451 Assert(pVmcs);
2452
2453 /*
2454 * Import all the guest-CPU state.
2455 *
2456 * HM on returning to guest execution would have to reset up a whole lot of state
2457 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2458 * the state and flag reloading the entire state on re-entry. So import the entire
2459 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2460 */
2461 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2462
2463 /*
2464 * Ensure VM-entry interruption information valid bit is cleared.
2465 *
2466 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2467 * by invalid-guest state or machine-check exceptions) also clear this bit.
2468 *
2469 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2470 */
2471 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2472 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2473
2474 /*
2475 * Update the VM-exit reason and Exit qualification.
2476 * Other VMCS read-only data fields are expected to be updated by the caller already.
2477 */
2478 pVmcs->u32RoExitReason = uExitReason;
2479 pVmcs->u64RoExitQual.u = u64ExitQual;
2480
2481 Log3(("vmexit: uExitReason=%#RX32 u64ExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual.u,
2482 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
2483
2484 /*
2485 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2486 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2487 */
2488 {
2489 uint8_t uVector;
2490 uint32_t fFlags;
2491 uint32_t uErrCode;
2492 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2493 if (fInEventDelivery)
2494 {
2495 /*
2496 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2497 * caused by a triple-fault or the original event results in a double-fault that
2498 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2499 * original event information into the IDT-vectoring information fields.
2500 *
2501 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2502 */
2503 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2504 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2505 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2506 {
2507 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2508 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2509 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2510 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2511 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2512 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2513 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2514 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2515 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2516 pVCpu->cpum.GstCtx.cr2));
2517 }
2518 }
2519 }
2520
2521 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2522 Assert(pVmcs->u64RoIoRcx.u == 0);
2523 Assert(pVmcs->u64RoIoRsi.u == 0);
2524 Assert(pVmcs->u64RoIoRdi.u == 0);
2525 Assert(pVmcs->u64RoIoRip.u == 0);
2526
2527 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2528 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
2529 {
2530 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2531 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2532 }
2533
2534 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2535 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2536
2537 /*
2538 * Save the guest state back into the VMCS.
2539 * We only need to save the state when the VM-entry was successful.
2540 */
2541 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2542 if (!fVmentryFailed)
2543 {
2544 /*
2545 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2546 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2547 *
2548 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2549 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2550 * as guest-CPU state would not been modified. Hence for now, we do this only when
2551 * the VM-entry succeeded.
2552 */
2553 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2554 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2555 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2556 {
2557 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2558 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2559 else
2560 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2561 }
2562
2563 /*
2564 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2565 * occurs in enclave mode/SMM which we don't support yet.
2566 *
2567 * If we ever add support for it, we can pass just the lower bits to the functions
2568 * below, till then an assert should suffice.
2569 */
2570 Assert(!RT_HI_U16(uExitReason));
2571
2572 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2573 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2574 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2575 if (RT_SUCCESS(rc))
2576 { /* likely */ }
2577 else
2578 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2579
2580 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2581 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2582 }
2583 else
2584 {
2585 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2586 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2587 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2588 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2589 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2590 }
2591
2592 /*
2593 * Clear any pending VMX nested-guest force-flags.
2594 * These force-flags have no effect on guest execution and will
2595 * be re-evaluated and setup on the next nested-guest VM-entry.
2596 */
2597 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER
2598 | VMCPU_FF_VMX_MTF
2599 | VMCPU_FF_VMX_APIC_WRITE
2600 | VMCPU_FF_VMX_INT_WINDOW
2601 | VMCPU_FF_VMX_NMI_WINDOW);
2602
2603 /* Restore the host (outer guest) state. */
2604 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2605 if (RT_SUCCESS(rcStrict))
2606 {
2607 Assert(rcStrict == VINF_SUCCESS);
2608 rcStrict = VINF_VMX_VMEXIT;
2609 }
2610 else
2611 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2612
2613 /* We're no longer in nested-guest execution mode. */
2614 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2615
2616 /* Notify HM that the current VMCS fields have been modified. */
2617 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2618
2619 /* Notify HM that we've completed the VM-exit. */
2620 HMNotifyVmxNstGstVmexit(pVCpu);
2621
2622# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2623 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2624 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2625 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2626 if (rcSched != VINF_SUCCESS)
2627 iemSetPassUpStatus(pVCpu, rcSched);
2628# endif
2629 return rcStrict;
2630# endif
2631}
2632
2633
2634/**
2635 * VMX VM-exit handler for VM-exits due to instruction execution.
2636 *
2637 * This is intended for instructions where the caller provides all the relevant
2638 * VM-exit information.
2639 *
2640 * @returns Strict VBox status code.
2641 * @param pVCpu The cross context virtual CPU structure.
2642 * @param pExitInfo Pointer to the VM-exit information.
2643 */
2644IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2645{
2646 /*
2647 * For instructions where any of the following fields are not applicable:
2648 * - Exit qualification must be cleared.
2649 * - VM-exit instruction info. is undefined.
2650 * - Guest-linear address is undefined.
2651 * - Guest-physical address is undefined.
2652 *
2653 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2654 * instruction execution. For VM-exits that are not due to instruction execution this
2655 * field is undefined.
2656 *
2657 * In our implementation in IEM, all undefined fields are generally cleared. However,
2658 * if the caller supplies information (from say the physical CPU directly) it is
2659 * then possible that the undefined fields are not cleared.
2660 *
2661 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2662 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2663 */
2664 Assert(pExitInfo);
2665 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2666 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2667 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2668
2669 /* Update all the relevant fields from the VM-exit instruction information struct. */
2670 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2671 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2672 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2673 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2674
2675 /* Perform the VM-exit. */
2676 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2677}
2678
2679
2680/**
2681 * VMX VM-exit handler for VM-exits due to instruction execution.
2682 *
2683 * This is intended for instructions that only provide the VM-exit instruction
2684 * length.
2685 *
2686 * @param pVCpu The cross context virtual CPU structure.
2687 * @param uExitReason The VM-exit reason.
2688 * @param cbInstr The instruction length in bytes.
2689 */
2690IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2691{
2692 VMXVEXITINFO ExitInfo;
2693 RT_ZERO(ExitInfo);
2694 ExitInfo.uReason = uExitReason;
2695 ExitInfo.cbInstr = cbInstr;
2696
2697#ifdef VBOX_STRICT
2698 /*
2699 * To prevent us from shooting ourselves in the foot.
2700 * The follow instructions should convey more than just the instruction length.
2701 */
2702 switch (uExitReason)
2703 {
2704 case VMX_EXIT_INVEPT:
2705 case VMX_EXIT_INVPCID:
2706 case VMX_EXIT_INVVPID:
2707 case VMX_EXIT_LDTR_TR_ACCESS:
2708 case VMX_EXIT_GDTR_IDTR_ACCESS:
2709 case VMX_EXIT_VMCLEAR:
2710 case VMX_EXIT_VMPTRLD:
2711 case VMX_EXIT_VMPTRST:
2712 case VMX_EXIT_VMREAD:
2713 case VMX_EXIT_VMWRITE:
2714 case VMX_EXIT_VMXON:
2715 case VMX_EXIT_XRSTORS:
2716 case VMX_EXIT_XSAVES:
2717 case VMX_EXIT_RDRAND:
2718 case VMX_EXIT_RDSEED:
2719 case VMX_EXIT_IO_INSTR:
2720 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2721 break;
2722 }
2723#endif
2724
2725 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2726}
2727
2728
2729/**
2730 * VMX VM-exit handler for VM-exits due to instruction execution.
2731 *
2732 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2733 * instruction information and Exit qualification fields.
2734 *
2735 * @param pVCpu The cross context virtual CPU structure.
2736 * @param uExitReason The VM-exit reason.
2737 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2738 * @param cbInstr The instruction length in bytes.
2739 *
2740 * @remarks Do not use this for INS/OUTS instruction.
2741 */
2742IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2743{
2744 VMXVEXITINFO ExitInfo;
2745 RT_ZERO(ExitInfo);
2746 ExitInfo.uReason = uExitReason;
2747 ExitInfo.cbInstr = cbInstr;
2748
2749 /*
2750 * Update the Exit qualification field with displacement bytes.
2751 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2752 */
2753 switch (uExitReason)
2754 {
2755 case VMX_EXIT_INVEPT:
2756 case VMX_EXIT_INVPCID:
2757 case VMX_EXIT_INVVPID:
2758 case VMX_EXIT_LDTR_TR_ACCESS:
2759 case VMX_EXIT_GDTR_IDTR_ACCESS:
2760 case VMX_EXIT_VMCLEAR:
2761 case VMX_EXIT_VMPTRLD:
2762 case VMX_EXIT_VMPTRST:
2763 case VMX_EXIT_VMREAD:
2764 case VMX_EXIT_VMWRITE:
2765 case VMX_EXIT_VMXON:
2766 case VMX_EXIT_XRSTORS:
2767 case VMX_EXIT_XSAVES:
2768 case VMX_EXIT_RDRAND:
2769 case VMX_EXIT_RDSEED:
2770 {
2771 /* Construct the VM-exit instruction information. */
2772 RTGCPTR GCPtrDisp;
2773 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2774
2775 /* Update the VM-exit instruction information. */
2776 ExitInfo.InstrInfo.u = uInstrInfo;
2777
2778 /* Update the Exit qualification. */
2779 ExitInfo.u64Qual = GCPtrDisp;
2780 break;
2781 }
2782
2783 default:
2784 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2785 break;
2786 }
2787
2788 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2789}
2790
2791
2792/**
2793 * VMX VM-exit handler for VM-exits due to INVLPG.
2794 *
2795 * @returns Strict VBox status code.
2796 * @param pVCpu The cross context virtual CPU structure.
2797 * @param GCPtrPage The guest-linear address of the page being invalidated.
2798 * @param cbInstr The instruction length in bytes.
2799 */
2800IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2801{
2802 VMXVEXITINFO ExitInfo;
2803 RT_ZERO(ExitInfo);
2804 ExitInfo.uReason = VMX_EXIT_INVLPG;
2805 ExitInfo.cbInstr = cbInstr;
2806 ExitInfo.u64Qual = GCPtrPage;
2807 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2808
2809 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2810}
2811
2812
2813/**
2814 * VMX VM-exit handler for VM-exits due to LMSW.
2815 *
2816 * @returns Strict VBox status code.
2817 * @param pVCpu The cross context virtual CPU structure.
2818 * @param uGuestCr0 The current guest CR0.
2819 * @param pu16NewMsw The machine-status word specified in LMSW's source
2820 * operand. This will be updated depending on the VMX
2821 * guest/host CR0 mask if LMSW is not intercepted.
2822 * @param GCPtrEffDst The guest-linear address of the source operand in case
2823 * of a memory operand. For register operand, pass
2824 * NIL_RTGCPTR.
2825 * @param cbInstr The instruction length in bytes.
2826 */
2827IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2828 uint8_t cbInstr)
2829{
2830 Assert(pu16NewMsw);
2831
2832 uint16_t const uNewMsw = *pu16NewMsw;
2833 if (CPUMIsGuestVmxLmswInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uNewMsw))
2834 {
2835 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2836
2837 VMXVEXITINFO ExitInfo;
2838 RT_ZERO(ExitInfo);
2839 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2840 ExitInfo.cbInstr = cbInstr;
2841
2842 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2843 if (fMemOperand)
2844 {
2845 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2846 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2847 }
2848
2849 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2850 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2851 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2852 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2853
2854 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2855 }
2856
2857 /*
2858 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2859 * CR0 guest/host mask must be left unmodified.
2860 *
2861 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2862 */
2863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2864 Assert(pVmcs);
2865 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2866 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2867 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2868
2869 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2870}
2871
2872
2873/**
2874 * VMX VM-exit handler for VM-exits due to CLTS.
2875 *
2876 * @returns Strict VBox status code.
2877 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2878 * VM-exit but must not modify the guest CR0.TS bit.
2879 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2880 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2881 * CR0 fixed bits in VMX operation).
2882 * @param pVCpu The cross context virtual CPU structure.
2883 * @param cbInstr The instruction length in bytes.
2884 */
2885IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2886{
2887 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2888 Assert(pVmcs);
2889
2890 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2891 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2892
2893 /*
2894 * If CR0.TS is owned by the host:
2895 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2896 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2897 * CLTS instruction completes without clearing CR0.TS.
2898 *
2899 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2900 */
2901 if (fGstHostMask & X86_CR0_TS)
2902 {
2903 if (fReadShadow & X86_CR0_TS)
2904 {
2905 Log2(("clts: Guest intercept -> VM-exit\n"));
2906
2907 VMXVEXITINFO ExitInfo;
2908 RT_ZERO(ExitInfo);
2909 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2910 ExitInfo.cbInstr = cbInstr;
2911 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2912 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2913 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2914 }
2915
2916 return VINF_VMX_MODIFIES_BEHAVIOR;
2917 }
2918
2919 /*
2920 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2921 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2922 */
2923 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2924}
2925
2926
2927/**
2928 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2929 * (CR0/CR4 write).
2930 *
2931 * @returns Strict VBox status code.
2932 * @param pVCpu The cross context virtual CPU structure.
2933 * @param iCrReg The control register (either CR0 or CR4).
2934 * @param uGuestCrX The current guest CR0/CR4.
2935 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2936 * VM-exit is caused.
2937 * @param iGReg The general register from which the CR0/CR4 value is being
2938 * loaded.
2939 * @param cbInstr The instruction length in bytes.
2940 */
2941IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2942 uint8_t cbInstr)
2943{
2944 Assert(puNewCrX);
2945 Assert(iCrReg == 0 || iCrReg == 4);
2946 Assert(iGReg < X86_GREG_COUNT);
2947
2948 uint64_t const uNewCrX = *puNewCrX;
2949 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(pVCpu, &pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2950 {
2951 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2952
2953 VMXVEXITINFO ExitInfo;
2954 RT_ZERO(ExitInfo);
2955 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2956 ExitInfo.cbInstr = cbInstr;
2957 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2958 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2959 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2960 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2961 }
2962
2963 /*
2964 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2965 * must not be modified the instruction.
2966 *
2967 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2968 */
2969 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2970 Assert(pVmcs);
2971 uint64_t uGuestCrX;
2972 uint64_t fGstHostMask;
2973 if (iCrReg == 0)
2974 {
2975 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2976 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2977 fGstHostMask = pVmcs->u64Cr0Mask.u;
2978 }
2979 else
2980 {
2981 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2982 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2983 fGstHostMask = pVmcs->u64Cr4Mask.u;
2984 }
2985
2986 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2987 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2988}
2989
2990
2991/**
2992 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2993 *
2994 * @returns VBox strict status code.
2995 * @param pVCpu The cross context virtual CPU structure.
2996 * @param iGReg The general register to which the CR3 value is being stored.
2997 * @param cbInstr The instruction length in bytes.
2998 */
2999IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3000{
3001 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3002 Assert(pVmcs);
3003 Assert(iGReg < X86_GREG_COUNT);
3004 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3005
3006 /*
3007 * If the CR3-store exiting control is set, we must cause a VM-exit.
3008 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3009 */
3010 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3011 {
3012 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3013
3014 VMXVEXITINFO ExitInfo;
3015 RT_ZERO(ExitInfo);
3016 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3017 ExitInfo.cbInstr = cbInstr;
3018 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3021 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3022 }
3023
3024 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3025}
3026
3027
3028/**
3029 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3030 *
3031 * @returns VBox strict status code.
3032 * @param pVCpu The cross context virtual CPU structure.
3033 * @param uNewCr3 The new CR3 value.
3034 * @param iGReg The general register from which the CR3 value is being
3035 * loaded.
3036 * @param cbInstr The instruction length in bytes.
3037 */
3038IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3039{
3040 Assert(iGReg < X86_GREG_COUNT);
3041
3042 /*
3043 * If the CR3-load exiting control is set and the new CR3 value does not
3044 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3045 *
3046 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3047 */
3048 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3049 {
3050 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3051
3052 VMXVEXITINFO ExitInfo;
3053 RT_ZERO(ExitInfo);
3054 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3055 ExitInfo.cbInstr = cbInstr;
3056 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3058 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3059 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3060 }
3061
3062 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3063}
3064
3065
3066/**
3067 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3068 *
3069 * @returns VBox strict status code.
3070 * @param pVCpu The cross context virtual CPU structure.
3071 * @param iGReg The general register to which the CR8 value is being stored.
3072 * @param cbInstr The instruction length in bytes.
3073 */
3074IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3075{
3076 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3077 Assert(pVmcs);
3078 Assert(iGReg < X86_GREG_COUNT);
3079
3080 /*
3081 * If the CR8-store exiting control is set, we must cause a VM-exit.
3082 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3083 */
3084 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3085 {
3086 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3087
3088 VMXVEXITINFO ExitInfo;
3089 RT_ZERO(ExitInfo);
3090 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3091 ExitInfo.cbInstr = cbInstr;
3092 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3094 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3095 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3096 }
3097
3098 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3099}
3100
3101
3102/**
3103 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3104 *
3105 * @returns VBox strict status code.
3106 * @param pVCpu The cross context virtual CPU structure.
3107 * @param iGReg The general register from which the CR8 value is being
3108 * loaded.
3109 * @param cbInstr The instruction length in bytes.
3110 */
3111IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3112{
3113 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3114 Assert(pVmcs);
3115 Assert(iGReg < X86_GREG_COUNT);
3116
3117 /*
3118 * If the CR8-load exiting control is set, we must cause a VM-exit.
3119 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3120 */
3121 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3122 {
3123 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3124
3125 VMXVEXITINFO ExitInfo;
3126 RT_ZERO(ExitInfo);
3127 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3128 ExitInfo.cbInstr = cbInstr;
3129 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3130 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3131 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3132 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3133 }
3134
3135 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3136}
3137
3138
3139/**
3140 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3141 * GReg,DRx' (DRx read).
3142 *
3143 * @returns VBox strict status code.
3144 * @param pVCpu The cross context virtual CPU structure.
3145 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3146 * VMXINSTRID_MOV_FROM_DRX).
3147 * @param iDrReg The debug register being accessed.
3148 * @param iGReg The general register to/from which the DRx value is being
3149 * store/loaded.
3150 * @param cbInstr The instruction length in bytes.
3151 */
3152IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3153 uint8_t cbInstr)
3154{
3155 Assert(iDrReg <= 7);
3156 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3157 Assert(iGReg < X86_GREG_COUNT);
3158
3159 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3160 Assert(pVmcs);
3161
3162 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3163 {
3164 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3165 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3166 VMXVEXITINFO ExitInfo;
3167 RT_ZERO(ExitInfo);
3168 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3169 ExitInfo.cbInstr = cbInstr;
3170 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3171 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3173 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3174 }
3175
3176 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3177}
3178
3179
3180/**
3181 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3182 *
3183 * @returns VBox strict status code.
3184 * @param pVCpu The cross context virtual CPU structure.
3185 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3186 * VMXINSTRID_IO_OUT).
3187 * @param u16Port The I/O port being accessed.
3188 * @param fImm Whether the I/O port was encoded using an immediate operand
3189 * or the implicit DX register.
3190 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3191 * @param cbInstr The instruction length in bytes.
3192 */
3193IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3194 uint8_t cbInstr)
3195{
3196 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3197 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3198
3199 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3200 if (fIntercept)
3201 {
3202 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3203 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3204 VMXVEXITINFO ExitInfo;
3205 RT_ZERO(ExitInfo);
3206 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3207 ExitInfo.cbInstr = cbInstr;
3208 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3209 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3210 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3211 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3212 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3213 }
3214
3215 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3216}
3217
3218
3219/**
3220 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3221 *
3222 * @returns VBox strict status code.
3223 * @param pVCpu The cross context virtual CPU structure.
3224 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3225 * VMXINSTRID_IO_OUTS).
3226 * @param u16Port The I/O port being accessed.
3227 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3228 * @param fRep Whether the instruction has a REP prefix or not.
3229 * @param ExitInstrInfo The VM-exit instruction info. field.
3230 * @param cbInstr The instruction length in bytes.
3231 */
3232IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3233 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3234{
3235 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3236 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3237 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3238 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3239 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3240
3241 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3242 if (fIntercept)
3243 {
3244 /*
3245 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3246 */
3247 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3248 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3249 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3250 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3251 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3252
3253 uint32_t uDirection;
3254 uint64_t uGuestLinearAddr;
3255 if (uInstrId == VMXINSTRID_IO_INS)
3256 {
3257 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3258 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3259 }
3260 else
3261 {
3262 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3263 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3264 }
3265
3266 /*
3267 * If the segment is unusable, the guest-linear address in undefined.
3268 * We shall clear it for consistency.
3269 *
3270 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3271 */
3272 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3273 uGuestLinearAddr = 0;
3274
3275 VMXVEXITINFO ExitInfo;
3276 RT_ZERO(ExitInfo);
3277 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3278 ExitInfo.cbInstr = cbInstr;
3279 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3280 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3284 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3285 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3286 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3287 ExitInfo.InstrInfo = ExitInstrInfo;
3288 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3289 }
3290
3291 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3292}
3293
3294
3295/**
3296 * VMX VM-exit handler for VM-exits due to MWAIT.
3297 *
3298 * @returns VBox strict status code.
3299 * @param pVCpu The cross context virtual CPU structure.
3300 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3301 * @param cbInstr The instruction length in bytes.
3302 */
3303IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3304{
3305 VMXVEXITINFO ExitInfo;
3306 RT_ZERO(ExitInfo);
3307 ExitInfo.uReason = VMX_EXIT_MWAIT;
3308 ExitInfo.cbInstr = cbInstr;
3309 ExitInfo.u64Qual = fMonitorHwArmed;
3310 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3311}
3312
3313
3314/**
3315 * VMX VM-exit handler for VM-exits due to PAUSE.
3316 *
3317 * @returns VBox strict status code.
3318 * @param pVCpu The cross context virtual CPU structure.
3319 * @param cbInstr The instruction length in bytes.
3320 */
3321IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3322{
3323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3324 Assert(pVmcs);
3325
3326 /*
3327 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3328 * "PAUSE-loop exiting" control.
3329 *
3330 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3331 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3332 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3333 * a VM-exit.
3334 *
3335 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3336 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3337 */
3338 bool fIntercept = false;
3339 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3340 fIntercept = true;
3341 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3342 && pVCpu->iem.s.uCpl == 0)
3343 {
3344 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3345
3346 /*
3347 * A previous-PAUSE-tick value of 0 is used to identify the first time
3348 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3349 * consider this to be the first execution of PAUSE in a loop according
3350 * to the Intel.
3351 *
3352 * All subsequent records for the previous-PAUSE-tick we ensure that it
3353 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3354 */
3355 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3356 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3357 uint64_t const uTick = TMCpuTickGet(pVCpu);
3358 uint32_t const uPleGap = pVmcs->u32PleGap;
3359 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3360 if ( *puPrevPauseTick == 0
3361 || uTick - *puPrevPauseTick > uPleGap)
3362 *puFirstPauseLoopTick = uTick;
3363 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3364 fIntercept = true;
3365
3366 *puPrevPauseTick = uTick | 1;
3367 }
3368
3369 if (fIntercept)
3370 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3371
3372 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3373}
3374
3375
3376/**
3377 * VMX VM-exit handler for VM-exits due to task switches.
3378 *
3379 * @returns VBox strict status code.
3380 * @param pVCpu The cross context virtual CPU structure.
3381 * @param enmTaskSwitch The cause of the task switch.
3382 * @param SelNewTss The selector of the new TSS.
3383 * @param cbInstr The instruction length in bytes.
3384 */
3385IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3386{
3387 /*
3388 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3389 *
3390 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3391 * instruction or delivery of the exception generated by one of these instructions
3392 * lead to a task switch through a task gate in the IDT, we need to provide the
3393 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3394 * leaves the VM-exit instruction length field undefined.
3395 *
3396 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3397 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3398 */
3399 Assert(cbInstr <= 15);
3400
3401 uint8_t uType;
3402 switch (enmTaskSwitch)
3403 {
3404 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3405 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3406 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3407 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3408 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3409 }
3410
3411 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3412 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3413 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3414 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3415}
3416
3417
3418/**
3419 * VMX VM-exit handler for trap-like VM-exits.
3420 *
3421 * @returns VBox strict status code.
3422 * @param pVCpu The cross context virtual CPU structure.
3423 * @param pExitInfo Pointer to the VM-exit information.
3424 * @param pExitEventInfo Pointer to the VM-exit event information.
3425 */
3426IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3427{
3428 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3429 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3430 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3431}
3432
3433
3434/**
3435 * VMX VM-exit handler for VM-exits due to task switches.
3436 *
3437 * This is intended for task switches where the caller provides all the relevant
3438 * VM-exit information.
3439 *
3440 * @returns VBox strict status code.
3441 * @param pVCpu The cross context virtual CPU structure.
3442 * @param pExitInfo Pointer to the VM-exit information.
3443 * @param pExitEventInfo Pointer to the VM-exit event information.
3444 */
3445IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3446 PCVMXVEXITEVENTINFO pExitEventInfo)
3447{
3448 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3449 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3450 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3451 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3452 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3453}
3454
3455
3456/**
3457 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3458 *
3459 * @returns VBox strict status code.
3460 * @param pVCpu The cross context virtual CPU structure.
3461 */
3462IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3463{
3464 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3465 Assert(pVmcs);
3466
3467 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3468 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3469 {
3470 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3471 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3472
3473 /*
3474 * Calculate the current VMX-preemption timer value.
3475 * Only if the value has reached zero, we cause the VM-exit.
3476 */
3477 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3478 if (!uPreemptTimer)
3479 {
3480 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3481 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3482 pVmcs->u32PreemptTimer = 0;
3483
3484 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3485 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3486 }
3487 }
3488
3489 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3490}
3491
3492
3493/**
3494 * VMX VM-exit handler for VM-exits due to external interrupts.
3495 *
3496 * @returns VBox strict status code.
3497 * @param pVCpu The cross context virtual CPU structure.
3498 * @param uVector The external interrupt vector (pass 0 if the interrupt
3499 * is still pending since we typically won't know the
3500 * vector).
3501 * @param fIntPending Whether the external interrupt is pending or
3502 * acknowledged in the interrupt controller.
3503 */
3504IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3505{
3506 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3507 Assert(pVmcs);
3508 Assert(fIntPending || uVector == 0);
3509
3510 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3511 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3512 * functions require prior checking of a blanket intercept and which don't.
3513 * It is better for the caller to check a blanket intercept performance wise
3514 * than making a function call. Leaving this as a todo because it is more
3515 * a performance issue. */
3516
3517 /* The VM-exit is subject to "External interrupt exiting" being set. */
3518 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3519 {
3520 if (fIntPending)
3521 {
3522 /*
3523 * If the interrupt is pending and we don't need to acknowledge the
3524 * interrupt on VM-exit, cause the VM-exit immediately.
3525 *
3526 * See Intel spec 25.2 "Other Causes Of VM Exits".
3527 */
3528 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3529 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3530
3531 /*
3532 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3533 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3534 * acknowledged that the interrupt has been consumed.
3535 */
3536 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3537 }
3538
3539 /*
3540 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3541 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3542 * all set, we cause the VM-exit now. We need to record the external interrupt that
3543 * just occurred in the VM-exit interruption information field.
3544 *
3545 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3546 */
3547 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3548 {
3549 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3550 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3551 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3552 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3553 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3554 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3555 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3556 }
3557 }
3558
3559 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3560}
3561
3562
3563/**
3564 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3565 * an event.
3566 *
3567 * @returns VBox strict status code.
3568 * @param pVCpu The cross context virtual CPU structure.
3569 */
3570IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3571{
3572 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3573 Assert(pVmcs);
3574
3575 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3576 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3577 {
3578 /*
3579 * The NMI-unblocking due to IRET field need not be set for double faults.
3580 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3581 */
3582 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3583 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3584 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3585 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3586 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3587 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3588 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3589 }
3590
3591 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3592}
3593
3594
3595/**
3596 * VMX VM-exit handler for VM-exit due to delivery of an events.
3597 *
3598 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3599 * all the relevant VM-exit information.
3600 *
3601 * @returns VBox strict status code.
3602 * @param pVCpu The cross context virtual CPU structure.
3603 * @param pExitInfo Pointer to the VM-exit information.
3604 * @param pExitEventInfo Pointer to the VM-exit event information.
3605 */
3606IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3607{
3608 Assert(pExitInfo);
3609 Assert(pExitEventInfo);
3610 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3611 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3612
3613 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3614 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3615 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3616 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3617 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3618 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3619}
3620
3621
3622/**
3623 * VMX VM-exit handler for VM-exits due to delivery of an event.
3624 *
3625 * @returns VBox strict status code.
3626 * @param pVCpu The cross context virtual CPU structure.
3627 * @param uVector The interrupt / exception vector.
3628 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3629 * @param uErrCode The error code associated with the event.
3630 * @param uCr2 The CR2 value in case of a \#PF exception.
3631 * @param cbInstr The instruction length in bytes.
3632 */
3633IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3634 uint8_t cbInstr)
3635{
3636 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3637 Assert(pVmcs);
3638
3639 /*
3640 * If the event is being injected as part of VM-entry, it is -not- subject to event
3641 * intercepts in the nested-guest. However, secondary exceptions that occur during
3642 * injection of any event -are- subject to event interception.
3643 *
3644 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3645 */
3646 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
3647 {
3648 /*
3649 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3650 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3651 *
3652 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3653 */
3654 if ( uVector == X86_XCPT_NMI
3655 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3656 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3657 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3658 else
3659 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3660
3661 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
3662 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3663 }
3664
3665 /*
3666 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3667 * If not, the caller will continue delivery of the external interrupt as it would
3668 * normally. The interrupt is no longer pending in the interrupt controller at this
3669 * point.
3670 */
3671 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3672 {
3673 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3674 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3675 }
3676
3677 /*
3678 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3679 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3680 * interrupts.
3681 */
3682 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3683 bool fIntercept;
3684 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3685 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3686 {
3687 fIntercept = CPUMIsGuestVmxXcptInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, uVector, uErrCode);
3688 }
3689 else
3690 {
3691 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3692 fIntercept = false;
3693 }
3694
3695 /*
3696 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3697 * relevant VM-exit information and cause the VM-exit.
3698 */
3699 if (fIntercept)
3700 {
3701 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3702
3703 /* Construct the rest of the event related information fields and cause the VM-exit. */
3704 uint64_t u64ExitQual;
3705 if (uVector == X86_XCPT_PF)
3706 {
3707 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3708 u64ExitQual = uCr2;
3709 }
3710 else if (uVector == X86_XCPT_DB)
3711 {
3712 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3713 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3714 }
3715 else
3716 u64ExitQual = 0;
3717
3718 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3719 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3720 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3721 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3722 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3723 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3724 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3725 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3726 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3727 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3728
3729 /*
3730 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3731 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3732 * length.
3733 */
3734 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3735 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3736 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3737 else
3738 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3739
3740 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3741 }
3742
3743 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3744}
3745
3746
3747/**
3748 * VMX VM-exit handler for APIC accesses.
3749 *
3750 * @param pVCpu The cross context virtual CPU structure.
3751 * @param offAccess The offset of the register being accessed.
3752 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3753 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3754 */
3755IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3756{
3757 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3758
3759 VMXAPICACCESS enmAccess;
3760 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3761 if (fInEventDelivery)
3762 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3763 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3764 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3765 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3766 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3767 else
3768 enmAccess = VMXAPICACCESS_LINEAR_READ;
3769
3770 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3771 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3772 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3773}
3774
3775
3776/**
3777 * VMX VM-exit handler for APIC accesses.
3778 *
3779 * This is intended for APIC accesses where the caller provides all the
3780 * relevant VM-exit information.
3781 *
3782 * @returns VBox strict status code.
3783 * @param pVCpu The cross context virtual CPU structure.
3784 * @param pExitInfo Pointer to the VM-exit information.
3785 * @param pExitEventInfo Pointer to the VM-exit event information.
3786 */
3787IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3788 PCVMXVEXITEVENTINFO pExitEventInfo)
3789{
3790 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3791 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3792 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3793 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3794 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3795 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3796 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3797 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3798 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3799}
3800
3801
3802/**
3803 * VMX VM-exit handler for APIC-write VM-exits.
3804 *
3805 * @param pVCpu The cross context virtual CPU structure.
3806 * @param offApic The write to the virtual-APIC page offset that caused this
3807 * VM-exit.
3808 */
3809IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3810{
3811 Assert(offApic < XAPIC_OFF_END + 4);
3812 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3813 offApic &= UINT16_C(0xfff);
3814 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3815}
3816
3817
3818/**
3819 * Sets virtual-APIC write emulation as pending.
3820 *
3821 * @param pVCpu The cross context virtual CPU structure.
3822 * @param offApic The offset in the virtual-APIC page that was written.
3823 */
3824DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3825{
3826 Assert(offApic < XAPIC_OFF_END + 4);
3827
3828 /*
3829 * Record the currently updated APIC offset, as we need this later for figuring
3830 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3831 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3832 */
3833 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3834
3835 /*
3836 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3837 * virtualization or APIC-write emulation).
3838 */
3839 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3840 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3841}
3842
3843
3844/**
3845 * Clears any pending virtual-APIC write emulation.
3846 *
3847 * @returns The virtual-APIC offset that was written before clearing it.
3848 * @param pVCpu The cross context virtual CPU structure.
3849 */
3850DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3851{
3852 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3853 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3854 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3855 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3856 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3857 return offVirtApicWrite;
3858}
3859
3860
3861/**
3862 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3863 *
3864 * @returns The register from the virtual-APIC page.
3865 * @param pVCpu The cross context virtual CPU structure.
3866 * @param offReg The offset of the register being read.
3867 */
3868IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3869{
3870 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3871 Assert(pVmcs);
3872 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3873
3874 uint32_t uReg;
3875 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3877 if (RT_SUCCESS(rc))
3878 { /* likely */ }
3879 else
3880 {
3881 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3882 GCPhysVirtApic));
3883 uReg = 0;
3884 }
3885 return uReg;
3886}
3887
3888
3889/**
3890 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3891 *
3892 * @returns The register from the virtual-APIC page.
3893 * @param pVCpu The cross context virtual CPU structure.
3894 * @param offReg The offset of the register being read.
3895 */
3896IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3897{
3898 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3899 Assert(pVmcs);
3900 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3901
3902 uint64_t uReg;
3903 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3904 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3905 if (RT_SUCCESS(rc))
3906 { /* likely */ }
3907 else
3908 {
3909 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3910 GCPhysVirtApic));
3911 uReg = 0;
3912 }
3913 return uReg;
3914}
3915
3916
3917/**
3918 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3919 *
3920 * @param pVCpu The cross context virtual CPU structure.
3921 * @param offReg The offset of the register being written.
3922 * @param uReg The register value to write.
3923 */
3924IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3925{
3926 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3927 Assert(pVmcs);
3928 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3929
3930 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3931 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3932 if (RT_SUCCESS(rc))
3933 { /* likely */ }
3934 else
3935 {
3936 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3937 GCPhysVirtApic));
3938 }
3939}
3940
3941
3942/**
3943 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3944 *
3945 * @param pVCpu The cross context virtual CPU structure.
3946 * @param offReg The offset of the register being written.
3947 * @param uReg The register value to write.
3948 */
3949IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3950{
3951 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3952 Assert(pVmcs);
3953 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3954
3955 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3956 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3957 if (RT_SUCCESS(rc))
3958 { /* likely */ }
3959 else
3960 {
3961 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3962 GCPhysVirtApic));
3963 }
3964}
3965
3966
3967/**
3968 * Sets the vector in a virtual-APIC 256-bit sparse register.
3969 *
3970 * @param pVCpu The cross context virtual CPU structure.
3971 * @param offReg The offset of the 256-bit spare register.
3972 * @param uVector The vector to set.
3973 *
3974 * @remarks This is based on our APIC device code.
3975 */
3976IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3977{
3978 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3979 Assert(pVmcs);
3980
3981 /* Determine the vector offset within the chunk. */
3982 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3983
3984 /* Read the chunk at the offset. */
3985 uint32_t uReg;
3986 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3987 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3988 if (RT_SUCCESS(rc))
3989 {
3990 /* Modify the chunk. */
3991 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3992 uReg |= RT_BIT(idxVectorBit);
3993
3994 /* Write the chunk. */
3995 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3996 if (RT_SUCCESS(rc))
3997 { /* likely */ }
3998 else
3999 {
4000 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4001 uVector, offReg, GCPhysVirtApic));
4002 }
4003 }
4004 else
4005 {
4006 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4007 uVector, offReg, GCPhysVirtApic));
4008 }
4009}
4010
4011
4012/**
4013 * Clears the vector in a virtual-APIC 256-bit sparse register.
4014 *
4015 * @param pVCpu The cross context virtual CPU structure.
4016 * @param offReg The offset of the 256-bit spare register.
4017 * @param uVector The vector to clear.
4018 *
4019 * @remarks This is based on our APIC device code.
4020 */
4021IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4022{
4023 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4024 Assert(pVmcs);
4025
4026 /* Determine the vector offset within the chunk. */
4027 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4028
4029 /* Read the chunk at the offset. */
4030 uint32_t uReg;
4031 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4032 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4033 if (RT_SUCCESS(rc))
4034 {
4035 /* Modify the chunk. */
4036 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4037 uReg &= ~RT_BIT(idxVectorBit);
4038
4039 /* Write the chunk. */
4040 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4041 if (RT_SUCCESS(rc))
4042 { /* likely */ }
4043 else
4044 {
4045 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4046 uVector, offReg, GCPhysVirtApic));
4047 }
4048 }
4049 else
4050 {
4051 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4052 uVector, offReg, GCPhysVirtApic));
4053 }
4054}
4055
4056
4057/**
4058 * Checks if a memory access to the APIC-access page must causes an APIC-access
4059 * VM-exit.
4060 *
4061 * @param pVCpu The cross context virtual CPU structure.
4062 * @param offAccess The offset of the register being accessed.
4063 * @param cbAccess The size of the access in bytes.
4064 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4065 * IEM_ACCESS_TYPE_WRITE).
4066 *
4067 * @remarks This must not be used for MSR-based APIC-access page accesses!
4068 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4069 */
4070IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4071{
4072 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4073 Assert(pVmcs);
4074 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4075
4076 /*
4077 * We must cause a VM-exit if any of the following are true:
4078 * - TPR shadowing isn't active.
4079 * - The access size exceeds 32-bits.
4080 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4081 *
4082 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4083 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4084 */
4085 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4086 || cbAccess > sizeof(uint32_t)
4087 || ((offAccess + cbAccess - 1) & 0xc)
4088 || offAccess >= XAPIC_OFF_END + 4)
4089 return true;
4090
4091 /*
4092 * If the access is part of an operation where we have already
4093 * virtualized a virtual-APIC write, we must cause a VM-exit.
4094 */
4095 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4096 return true;
4097
4098 /*
4099 * Check write accesses to the APIC-access page that cause VM-exits.
4100 */
4101 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4102 {
4103 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4104 {
4105 /*
4106 * With APIC-register virtualization, a write access to any of the
4107 * following registers are virtualized. Accessing any other register
4108 * causes a VM-exit.
4109 */
4110 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4111 switch (offAlignedAccess)
4112 {
4113 case XAPIC_OFF_ID:
4114 case XAPIC_OFF_TPR:
4115 case XAPIC_OFF_EOI:
4116 case XAPIC_OFF_LDR:
4117 case XAPIC_OFF_DFR:
4118 case XAPIC_OFF_SVR:
4119 case XAPIC_OFF_ESR:
4120 case XAPIC_OFF_ICR_LO:
4121 case XAPIC_OFF_ICR_HI:
4122 case XAPIC_OFF_LVT_TIMER:
4123 case XAPIC_OFF_LVT_THERMAL:
4124 case XAPIC_OFF_LVT_PERF:
4125 case XAPIC_OFF_LVT_LINT0:
4126 case XAPIC_OFF_LVT_LINT1:
4127 case XAPIC_OFF_LVT_ERROR:
4128 case XAPIC_OFF_TIMER_ICR:
4129 case XAPIC_OFF_TIMER_DCR:
4130 break;
4131 default:
4132 return true;
4133 }
4134 }
4135 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4136 {
4137 /*
4138 * With virtual-interrupt delivery, a write access to any of the
4139 * following registers are virtualized. Accessing any other register
4140 * causes a VM-exit.
4141 *
4142 * Note! The specification does not allow writing to offsets in-between
4143 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4144 */
4145 switch (offAccess)
4146 {
4147 case XAPIC_OFF_TPR:
4148 case XAPIC_OFF_EOI:
4149 case XAPIC_OFF_ICR_LO:
4150 break;
4151 default:
4152 return true;
4153 }
4154 }
4155 else
4156 {
4157 /*
4158 * Without APIC-register virtualization or virtual-interrupt delivery,
4159 * only TPR accesses are virtualized.
4160 */
4161 if (offAccess == XAPIC_OFF_TPR)
4162 { /* likely */ }
4163 else
4164 return true;
4165 }
4166 }
4167 else
4168 {
4169 /*
4170 * Check read accesses to the APIC-access page that cause VM-exits.
4171 */
4172 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4173 {
4174 /*
4175 * With APIC-register virtualization, a read access to any of the
4176 * following registers are virtualized. Accessing any other register
4177 * causes a VM-exit.
4178 */
4179 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4180 switch (offAlignedAccess)
4181 {
4182 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4183 case XAPIC_OFF_ID:
4184 case XAPIC_OFF_VERSION:
4185 case XAPIC_OFF_TPR:
4186 case XAPIC_OFF_EOI:
4187 case XAPIC_OFF_LDR:
4188 case XAPIC_OFF_DFR:
4189 case XAPIC_OFF_SVR:
4190 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4191 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4192 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4193 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4194 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4195 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4196 case XAPIC_OFF_ESR:
4197 case XAPIC_OFF_ICR_LO:
4198 case XAPIC_OFF_ICR_HI:
4199 case XAPIC_OFF_LVT_TIMER:
4200 case XAPIC_OFF_LVT_THERMAL:
4201 case XAPIC_OFF_LVT_PERF:
4202 case XAPIC_OFF_LVT_LINT0:
4203 case XAPIC_OFF_LVT_LINT1:
4204 case XAPIC_OFF_LVT_ERROR:
4205 case XAPIC_OFF_TIMER_ICR:
4206 case XAPIC_OFF_TIMER_DCR:
4207 break;
4208 default:
4209 return true;
4210 }
4211 }
4212 else
4213 {
4214 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4215 if (offAccess == XAPIC_OFF_TPR)
4216 { /* likely */ }
4217 else
4218 return true;
4219 }
4220 }
4221
4222 /* The APIC access is virtualized, does not cause a VM-exit. */
4223 return false;
4224}
4225
4226
4227/**
4228 * Virtualizes a memory-based APIC access where the address is not used to access
4229 * memory.
4230 *
4231 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4232 * page-faults but do not use the address to access memory.
4233 *
4234 * @param pVCpu The cross context virtual CPU structure.
4235 * @param pGCPhysAccess Pointer to the guest-physical address used.
4236 */
4237IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4238{
4239 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4240 Assert(pVmcs);
4241 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4242 Assert(pGCPhysAccess);
4243
4244 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4245 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4246 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4247
4248 if (GCPhysAccess == GCPhysApic)
4249 {
4250 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4251 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4252 uint16_t const cbAccess = 1;
4253 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4254 if (fIntercept)
4255 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4256
4257 *pGCPhysAccess = GCPhysApic | offAccess;
4258 return VINF_VMX_MODIFIES_BEHAVIOR;
4259 }
4260
4261 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4262}
4263
4264
4265/**
4266 * Virtualizes a memory-based APIC access.
4267 *
4268 * @returns VBox strict status code.
4269 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4270 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4271 *
4272 * @param pVCpu The cross context virtual CPU structure.
4273 * @param offAccess The offset of the register being accessed (within the
4274 * APIC-access page).
4275 * @param cbAccess The size of the access in bytes.
4276 * @param pvData Pointer to the data being written or where to store the data
4277 * being read.
4278 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4279 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4280 */
4281IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4282 uint32_t fAccess)
4283{
4284 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4285 Assert(pVmcs);
4286 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4287 Assert(pvData);
4288 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4289 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4290 || (fAccess & IEM_ACCESS_INSTRUCTION));
4291
4292 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4293 if (fIntercept)
4294 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4295
4296 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4297 {
4298 /*
4299 * A write access to the APIC-access page that is virtualized (rather than
4300 * causing a VM-exit) writes data to the virtual-APIC page.
4301 */
4302 uint32_t const u32Data = *(uint32_t *)pvData;
4303 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4304
4305 /*
4306 * Record the currently updated APIC offset, as we need this later for figuring
4307 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4308 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4309 *
4310 * After completion of the current operation, we need to perform TPR virtualization,
4311 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4312 *
4313 * The current operation may be a REP-prefixed string instruction, execution of any
4314 * other instruction, or delivery of an event through the IDT.
4315 *
4316 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4317 * performed now but later after completion of the current operation.
4318 *
4319 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4320 */
4321 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4322 }
4323 else
4324 {
4325 /*
4326 * A read access from the APIC-access page that is virtualized (rather than
4327 * causing a VM-exit) returns data from the virtual-APIC page.
4328 *
4329 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4330 */
4331 Assert(cbAccess <= 4);
4332 Assert(offAccess < XAPIC_OFF_END + 4);
4333 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4334
4335 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4336 u32Data &= s_auAccessSizeMasks[cbAccess];
4337 *(uint32_t *)pvData = u32Data;
4338 }
4339
4340 return VINF_VMX_MODIFIES_BEHAVIOR;
4341}
4342
4343
4344/**
4345 * Virtualizes an MSR-based APIC read access.
4346 *
4347 * @returns VBox strict status code.
4348 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4349 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4350 * handled by the x2APIC device.
4351 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4352 * not within the range of valid MSRs, caller must raise \#GP(0).
4353 * @param pVCpu The cross context virtual CPU structure.
4354 * @param idMsr The x2APIC MSR being read.
4355 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4356 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4357 */
4358IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4359{
4360 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4361 Assert(pVmcs);
4362 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4363 Assert(pu64Value);
4364
4365 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4366 {
4367 /*
4368 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4369 * what the end of the valid x2APIC MSR range is. Hence the use of different
4370 * macros here.
4371 *
4372 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4373 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4374 */
4375 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4376 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4377 {
4378 uint16_t const offReg = (idMsr & 0xff) << 4;
4379 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4380 *pu64Value = u64Value;
4381 return VINF_VMX_MODIFIES_BEHAVIOR;
4382 }
4383 return VERR_OUT_OF_RANGE;
4384 }
4385
4386 if (idMsr == MSR_IA32_X2APIC_TPR)
4387 {
4388 uint16_t const offReg = (idMsr & 0xff) << 4;
4389 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4390 *pu64Value = u64Value;
4391 return VINF_VMX_MODIFIES_BEHAVIOR;
4392 }
4393
4394 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4395}
4396
4397
4398/**
4399 * Virtualizes an MSR-based APIC write access.
4400 *
4401 * @returns VBox strict status code.
4402 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4403 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4404 * not within the range of valid MSRs, caller must raise \#GP(0).
4405 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4406 *
4407 * @param pVCpu The cross context virtual CPU structure.
4408 * @param idMsr The x2APIC MSR being written.
4409 * @param u64Value The value of the x2APIC MSR being written.
4410 */
4411IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4412{
4413 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4414 Assert(pVmcs);
4415
4416 /*
4417 * Check if the access is to be virtualized.
4418 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4419 */
4420 if ( idMsr == MSR_IA32_X2APIC_TPR
4421 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4422 && ( idMsr == MSR_IA32_X2APIC_EOI
4423 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4424 {
4425 /* Validate the MSR write depending on the register. */
4426 switch (idMsr)
4427 {
4428 case MSR_IA32_X2APIC_TPR:
4429 case MSR_IA32_X2APIC_SELF_IPI:
4430 {
4431 if (u64Value & UINT64_C(0xffffffffffffff00))
4432 return VERR_OUT_OF_RANGE;
4433 break;
4434 }
4435 case MSR_IA32_X2APIC_EOI:
4436 {
4437 if (u64Value != 0)
4438 return VERR_OUT_OF_RANGE;
4439 break;
4440 }
4441 }
4442
4443 /* Write the MSR to the virtual-APIC page. */
4444 uint16_t const offReg = (idMsr & 0xff) << 4;
4445 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4446
4447 /*
4448 * Record the currently updated APIC offset, as we need this later for figuring
4449 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4450 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4451 */
4452 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4453
4454 return VINF_VMX_MODIFIES_BEHAVIOR;
4455 }
4456
4457 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4458}
4459
4460
4461/**
4462 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4463 *
4464 * @returns VBox status code.
4465 * @retval VINF_SUCCESS when the highest set bit is found.
4466 * @retval VERR_NOT_FOUND when no bit is set.
4467 *
4468 * @param pVCpu The cross context virtual CPU structure.
4469 * @param offReg The offset of the APIC 256-bit sparse register.
4470 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4471 * set in the register. Only valid when VINF_SUCCESS is
4472 * returned.
4473 *
4474 * @remarks The format of the 256-bit sparse register here mirrors that found in
4475 * real APIC hardware.
4476 */
4477static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4478{
4479 Assert(offReg < XAPIC_OFF_END + 4);
4480 Assert(pidxHighestBit);
4481 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4482
4483 /*
4484 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4485 * However, in each fragment only the first 4 bytes are used.
4486 */
4487 uint8_t const cFrags = 8;
4488 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4489 {
4490 uint16_t const offFrag = iFrag * 16;
4491 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4492 if (!u32Frag)
4493 continue;
4494
4495 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4496 Assert(idxHighestBit > 0);
4497 --idxHighestBit;
4498 Assert(idxHighestBit <= UINT8_MAX);
4499 *pidxHighestBit = idxHighestBit;
4500 return VINF_SUCCESS;
4501 }
4502 return VERR_NOT_FOUND;
4503}
4504
4505
4506/**
4507 * Evaluates pending virtual interrupts.
4508 *
4509 * @param pVCpu The cross context virtual CPU structure.
4510 */
4511IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4512{
4513 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4514 Assert(pVmcs);
4515 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4516
4517 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4518 {
4519 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4520 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4521
4522 if ((uRvi >> 4) > (uPpr >> 4))
4523 {
4524 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4525 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4526 }
4527 else
4528 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4529 }
4530}
4531
4532
4533/**
4534 * Performs PPR virtualization.
4535 *
4536 * @returns VBox strict status code.
4537 * @param pVCpu The cross context virtual CPU structure.
4538 */
4539IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4540{
4541 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4542 Assert(pVmcs);
4543 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4544 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4545
4546 /*
4547 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4548 * or EOI-virtualization.
4549 *
4550 * See Intel spec. 29.1.3 "PPR Virtualization".
4551 */
4552 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4553 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4554
4555 uint32_t uPpr;
4556 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4557 uPpr = uTpr & 0xff;
4558 else
4559 uPpr = uSvi & 0xf0;
4560
4561 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4562 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4563}
4564
4565
4566/**
4567 * Performs VMX TPR virtualization.
4568 *
4569 * @returns VBox strict status code.
4570 * @param pVCpu The cross context virtual CPU structure.
4571 */
4572IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4573{
4574 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4575 Assert(pVmcs);
4576 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4577
4578 /*
4579 * We should have already performed the virtual-APIC write to the TPR offset
4580 * in the virtual-APIC page. We now perform TPR virtualization.
4581 *
4582 * See Intel spec. 29.1.2 "TPR Virtualization".
4583 */
4584 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4585 {
4586 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4587 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4588
4589 /*
4590 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4591 * See Intel spec. 29.1.2 "TPR Virtualization".
4592 */
4593 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4594 {
4595 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4596 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4597 }
4598 }
4599 else
4600 {
4601 iemVmxPprVirtualization(pVCpu);
4602 iemVmxEvalPendingVirtIntrs(pVCpu);
4603 }
4604
4605 return VINF_SUCCESS;
4606}
4607
4608
4609/**
4610 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4611 * not.
4612 *
4613 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4614 * @param pVCpu The cross context virtual CPU structure.
4615 * @param uVector The interrupt that was acknowledged using an EOI.
4616 */
4617IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4618{
4619 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4620 Assert(pVmcs);
4621 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4622
4623 if (uVector < 64)
4624 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4625 if (uVector < 128)
4626 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4627 if (uVector < 192)
4628 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4629 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4630}
4631
4632
4633/**
4634 * Performs EOI virtualization.
4635 *
4636 * @returns VBox strict status code.
4637 * @param pVCpu The cross context virtual CPU structure.
4638 */
4639IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4640{
4641 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4642 Assert(pVmcs);
4643 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4644
4645 /*
4646 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4647 * and get the next guest-interrupt that's in-service (if any).
4648 *
4649 * See Intel spec. 29.1.4 "EOI Virtualization".
4650 */
4651 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4652 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4653 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4654
4655 uint8_t uVector = uSvi;
4656 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4657
4658 uVector = 0;
4659 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4660
4661 if (uVector)
4662 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4663 else
4664 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4665
4666 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4667 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4668
4669 iemVmxPprVirtualization(pVCpu);
4670 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4671 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4672 iemVmxEvalPendingVirtIntrs(pVCpu);
4673 return VINF_SUCCESS;
4674}
4675
4676
4677/**
4678 * Performs self-IPI virtualization.
4679 *
4680 * @returns VBox strict status code.
4681 * @param pVCpu The cross context virtual CPU structure.
4682 */
4683IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4684{
4685 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4686 Assert(pVmcs);
4687 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4688
4689 /*
4690 * We should have already performed the virtual-APIC write to the self-IPI offset
4691 * in the virtual-APIC page. We now perform self-IPI virtualization.
4692 *
4693 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4694 */
4695 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4696 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4697 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4698 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4699 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4700 if (uVector > uRvi)
4701 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4702 iemVmxEvalPendingVirtIntrs(pVCpu);
4703 return VINF_SUCCESS;
4704}
4705
4706
4707/**
4708 * Performs VMX APIC-write emulation.
4709 *
4710 * @returns VBox strict status code.
4711 * @param pVCpu The cross context virtual CPU structure.
4712 */
4713IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4714{
4715 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4716 Assert(pVmcs);
4717
4718 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4719 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4720
4721 /*
4722 * Perform APIC-write emulation based on the virtual-APIC register written.
4723 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4724 */
4725 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4726 VBOXSTRICTRC rcStrict;
4727 switch (offApicWrite)
4728 {
4729 case XAPIC_OFF_TPR:
4730 {
4731 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4732 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4733 uTpr &= UINT32_C(0x000000ff);
4734 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4735 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4736 rcStrict = iemVmxTprVirtualization(pVCpu);
4737 break;
4738 }
4739
4740 case XAPIC_OFF_EOI:
4741 {
4742 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4743 {
4744 /* Clear VEOI and perform EOI virtualization. */
4745 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4746 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4747 rcStrict = iemVmxEoiVirtualization(pVCpu);
4748 }
4749 else
4750 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4751 break;
4752 }
4753
4754 case XAPIC_OFF_ICR_LO:
4755 {
4756 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4757 {
4758 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4759 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4760 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4761 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4762 if ( !(uIcrLo & fIcrLoMb0)
4763 && (uIcrLo & fIcrLoMb1))
4764 {
4765 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4766 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4767 }
4768 else
4769 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4770 }
4771 else
4772 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4773 break;
4774 }
4775
4776 case XAPIC_OFF_ICR_HI:
4777 {
4778 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4779 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4780 uIcrHi &= UINT32_C(0xff000000);
4781 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4782 rcStrict = VINF_SUCCESS;
4783 break;
4784 }
4785
4786 default:
4787 {
4788 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4789 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4790 break;
4791 }
4792 }
4793
4794 return rcStrict;
4795}
4796
4797
4798/**
4799 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4800 *
4801 * @param pVCpu The cross context virtual CPU structure.
4802 * @param pszInstr The VMX instruction name (for logging purposes).
4803 */
4804IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4805{
4806 /*
4807 * Guest Control Registers, Debug Registers, and MSRs.
4808 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4809 */
4810 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4811 const char *const pszFailure = "VM-exit";
4812 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4813
4814 /* CR0 reserved bits. */
4815 {
4816 /* CR0 MB1 bits. */
4817 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4818 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4819 if (fUnrestrictedGuest)
4820 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4821 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4822 { /* likely */ }
4823 else
4824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4825
4826 /* CR0 MBZ bits. */
4827 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4828 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4829 { /* likely */ }
4830 else
4831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4832
4833 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4834 if ( !fUnrestrictedGuest
4835 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4836 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4838 }
4839
4840 /* CR4 reserved bits. */
4841 {
4842 /* CR4 MB1 bits. */
4843 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4844 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4845 { /* likely */ }
4846 else
4847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4848
4849 /* CR4 MBZ bits. */
4850 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4851 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4852 { /* likely */ }
4853 else
4854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4855 }
4856
4857 /* DEBUGCTL MSR. */
4858 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4859 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4860 { /* likely */ }
4861 else
4862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4863
4864 /* 64-bit CPU checks. */
4865 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4866 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4867 {
4868 if (fGstInLongMode)
4869 {
4870 /* PAE must be set. */
4871 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4872 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4873 { /* likely */ }
4874 else
4875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4876 }
4877 else
4878 {
4879 /* PCIDE should not be set. */
4880 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4881 { /* likely */ }
4882 else
4883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4884 }
4885
4886 /* CR3. */
4887 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4888 { /* likely */ }
4889 else
4890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4891
4892 /* DR7. */
4893 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4894 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4895 { /* likely */ }
4896 else
4897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4898
4899 /* SYSENTER ESP and SYSENTER EIP. */
4900 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4901 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4902 { /* likely */ }
4903 else
4904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4905 }
4906
4907 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4908 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4909
4910 /* PAT MSR. */
4911 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4912 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4913 { /* likely */ }
4914 else
4915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4916
4917 /* EFER MSR. */
4918 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4919 {
4920 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4921 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4922 { /* likely */ }
4923 else
4924 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4925
4926 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4927 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4928 if ( fGstLma == fGstInLongMode
4929 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4930 || fGstLma == fGstLme))
4931 { /* likely */ }
4932 else
4933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4934 }
4935
4936 /* We don't support IA32_BNDCFGS MSR yet. */
4937 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4938
4939 NOREF(pszInstr);
4940 NOREF(pszFailure);
4941 return VINF_SUCCESS;
4942}
4943
4944
4945/**
4946 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4947 *
4948 * @param pVCpu The cross context virtual CPU structure.
4949 * @param pszInstr The VMX instruction name (for logging purposes).
4950 */
4951IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4952{
4953 /*
4954 * Segment registers.
4955 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4956 */
4957 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4958 const char *const pszFailure = "VM-exit";
4959 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4960 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4961 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4962
4963 /* Selectors. */
4964 if ( !fGstInV86Mode
4965 && !fUnrestrictedGuest
4966 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4968
4969 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4970 {
4971 CPUMSELREG SelReg;
4972 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4973 if (RT_LIKELY(rc == VINF_SUCCESS))
4974 { /* likely */ }
4975 else
4976 return rc;
4977
4978 /*
4979 * Virtual-8086 mode checks.
4980 */
4981 if (fGstInV86Mode)
4982 {
4983 /* Base address. */
4984 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4985 { /* likely */ }
4986 else
4987 {
4988 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4990 }
4991
4992 /* Limit. */
4993 if (SelReg.u32Limit == 0xffff)
4994 { /* likely */ }
4995 else
4996 {
4997 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4998 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4999 }
5000
5001 /* Attribute. */
5002 if (SelReg.Attr.u == 0xf3)
5003 { /* likely */ }
5004 else
5005 {
5006 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5008 }
5009
5010 /* We're done; move to checking the next segment. */
5011 continue;
5012 }
5013
5014 /* Checks done by 64-bit CPUs. */
5015 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5016 {
5017 /* Base address. */
5018 if ( iSegReg == X86_SREG_FS
5019 || iSegReg == X86_SREG_GS)
5020 {
5021 if (X86_IS_CANONICAL(SelReg.u64Base))
5022 { /* likely */ }
5023 else
5024 {
5025 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5027 }
5028 }
5029 else if (iSegReg == X86_SREG_CS)
5030 {
5031 if (!RT_HI_U32(SelReg.u64Base))
5032 { /* likely */ }
5033 else
5034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5035 }
5036 else
5037 {
5038 if ( SelReg.Attr.n.u1Unusable
5039 || !RT_HI_U32(SelReg.u64Base))
5040 { /* likely */ }
5041 else
5042 {
5043 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5044 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5045 }
5046 }
5047 }
5048
5049 /*
5050 * Checks outside Virtual-8086 mode.
5051 */
5052 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5053 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5054 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5055 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5056 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5057 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5058 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5059 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5060
5061 /* Code or usable segment. */
5062 if ( iSegReg == X86_SREG_CS
5063 || fUsable)
5064 {
5065 /* Reserved bits (bits 31:17 and bits 11:8). */
5066 if (!(SelReg.Attr.u & 0xfffe0f00))
5067 { /* likely */ }
5068 else
5069 {
5070 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5072 }
5073
5074 /* Descriptor type. */
5075 if (fCodeDataSeg)
5076 { /* likely */ }
5077 else
5078 {
5079 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5081 }
5082
5083 /* Present. */
5084 if (fPresent)
5085 { /* likely */ }
5086 else
5087 {
5088 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5090 }
5091
5092 /* Granularity. */
5093 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5094 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5095 { /* likely */ }
5096 else
5097 {
5098 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5100 }
5101 }
5102
5103 if (iSegReg == X86_SREG_CS)
5104 {
5105 /* Segment Type and DPL. */
5106 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5107 && fUnrestrictedGuest)
5108 {
5109 if (uDpl == 0)
5110 { /* likely */ }
5111 else
5112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5113 }
5114 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5115 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5116 {
5117 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5118 if (uDpl == AttrSs.n.u2Dpl)
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5122 }
5123 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5124 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5125 {
5126 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5127 if (uDpl <= AttrSs.n.u2Dpl)
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5131 }
5132 else
5133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5134
5135 /* Def/Big. */
5136 if ( fGstInLongMode
5137 && fSegLong)
5138 {
5139 if (uDefBig == 0)
5140 { /* likely */ }
5141 else
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5143 }
5144 }
5145 else if (iSegReg == X86_SREG_SS)
5146 {
5147 /* Segment Type. */
5148 if ( !fUsable
5149 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5150 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5151 { /* likely */ }
5152 else
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5154
5155 /* DPL. */
5156 if (!fUnrestrictedGuest)
5157 {
5158 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5159 { /* likely */ }
5160 else
5161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5162 }
5163 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5164 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5165 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5166 {
5167 if (uDpl == 0)
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5171 }
5172 }
5173 else
5174 {
5175 /* DS, ES, FS, GS. */
5176 if (fUsable)
5177 {
5178 /* Segment type. */
5179 if (uSegType & X86_SEL_TYPE_ACCESSED)
5180 { /* likely */ }
5181 else
5182 {
5183 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5185 }
5186
5187 if ( !(uSegType & X86_SEL_TYPE_CODE)
5188 || (uSegType & X86_SEL_TYPE_READ))
5189 { /* likely */ }
5190 else
5191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5192
5193 /* DPL. */
5194 if ( !fUnrestrictedGuest
5195 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5196 {
5197 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5198 { /* likely */ }
5199 else
5200 {
5201 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5203 }
5204 }
5205 }
5206 }
5207 }
5208
5209 /*
5210 * LDTR.
5211 */
5212 {
5213 CPUMSELREG Ldtr;
5214 Ldtr.Sel = pVmcs->GuestLdtr;
5215 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5216 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5217 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5218
5219 if (!Ldtr.Attr.n.u1Unusable)
5220 {
5221 /* Selector. */
5222 if (!(Ldtr.Sel & X86_SEL_LDT))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5226
5227 /* Base. */
5228 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5229 {
5230 if (X86_IS_CANONICAL(Ldtr.u64Base))
5231 { /* likely */ }
5232 else
5233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5234 }
5235
5236 /* Attributes. */
5237 /* Reserved bits (bits 31:17 and bits 11:8). */
5238 if (!(Ldtr.Attr.u & 0xfffe0f00))
5239 { /* likely */ }
5240 else
5241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5242
5243 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5244 { /* likely */ }
5245 else
5246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5247
5248 if (!Ldtr.Attr.n.u1DescType)
5249 { /* likely */ }
5250 else
5251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5252
5253 if (Ldtr.Attr.n.u1Present)
5254 { /* likely */ }
5255 else
5256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5257
5258 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5259 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5260 { /* likely */ }
5261 else
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5263 }
5264 }
5265
5266 /*
5267 * TR.
5268 */
5269 {
5270 CPUMSELREG Tr;
5271 Tr.Sel = pVmcs->GuestTr;
5272 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5273 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5274 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5275
5276 /* Selector. */
5277 if (!(Tr.Sel & X86_SEL_LDT))
5278 { /* likely */ }
5279 else
5280 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5281
5282 /* Base. */
5283 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5284 {
5285 if (X86_IS_CANONICAL(Tr.u64Base))
5286 { /* likely */ }
5287 else
5288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5289 }
5290
5291 /* Attributes. */
5292 /* Reserved bits (bits 31:17 and bits 11:8). */
5293 if (!(Tr.Attr.u & 0xfffe0f00))
5294 { /* likely */ }
5295 else
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5297
5298 if (!Tr.Attr.n.u1Unusable)
5299 { /* likely */ }
5300 else
5301 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5302
5303 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5304 || ( !fGstInLongMode
5305 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5306 { /* likely */ }
5307 else
5308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5309
5310 if (!Tr.Attr.n.u1DescType)
5311 { /* likely */ }
5312 else
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5314
5315 if (Tr.Attr.n.u1Present)
5316 { /* likely */ }
5317 else
5318 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5319
5320 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5321 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5322 { /* likely */ }
5323 else
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5325 }
5326
5327 NOREF(pszInstr);
5328 NOREF(pszFailure);
5329 return VINF_SUCCESS;
5330}
5331
5332
5333/**
5334 * Checks guest GDTR and IDTR as part of VM-entry.
5335 *
5336 * @param pVCpu The cross context virtual CPU structure.
5337 * @param pszInstr The VMX instruction name (for logging purposes).
5338 */
5339IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5340{
5341 /*
5342 * GDTR and IDTR.
5343 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5344 */
5345 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5346 const char *const pszFailure = "VM-exit";
5347
5348 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5349 {
5350 /* Base. */
5351 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5352 { /* likely */ }
5353 else
5354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5355
5356 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5357 { /* likely */ }
5358 else
5359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5360 }
5361
5362 /* Limit. */
5363 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5364 { /* likely */ }
5365 else
5366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5367
5368 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5369 { /* likely */ }
5370 else
5371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5372
5373 NOREF(pszInstr);
5374 NOREF(pszFailure);
5375 return VINF_SUCCESS;
5376}
5377
5378
5379/**
5380 * Checks guest RIP and RFLAGS as part of VM-entry.
5381 *
5382 * @param pVCpu The cross context virtual CPU structure.
5383 * @param pszInstr The VMX instruction name (for logging purposes).
5384 */
5385IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5386{
5387 /*
5388 * RIP and RFLAGS.
5389 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5390 */
5391 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5392 const char *const pszFailure = "VM-exit";
5393 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5394
5395 /* RIP. */
5396 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5397 {
5398 X86DESCATTR AttrCs;
5399 AttrCs.u = pVmcs->u32GuestCsAttr;
5400 if ( !fGstInLongMode
5401 || !AttrCs.n.u1Long)
5402 {
5403 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5404 { /* likely */ }
5405 else
5406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5407 }
5408
5409 if ( fGstInLongMode
5410 && AttrCs.n.u1Long)
5411 {
5412 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5413 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5414 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5418 }
5419 }
5420
5421 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5422 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5423 : pVmcs->u64GuestRFlags.s.Lo;
5424 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5425 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5429
5430 if ( fGstInLongMode
5431 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5432 {
5433 if (!(uGuestRFlags & X86_EFL_VM))
5434 { /* likely */ }
5435 else
5436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5437 }
5438
5439 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5440 {
5441 if (uGuestRFlags & X86_EFL_IF)
5442 { /* likely */ }
5443 else
5444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5445 }
5446
5447 NOREF(pszInstr);
5448 NOREF(pszFailure);
5449 return VINF_SUCCESS;
5450}
5451
5452
5453/**
5454 * Checks guest non-register state as part of VM-entry.
5455 *
5456 * @param pVCpu The cross context virtual CPU structure.
5457 * @param pszInstr The VMX instruction name (for logging purposes).
5458 */
5459IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5460{
5461 /*
5462 * Guest non-register state.
5463 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5464 */
5465 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5466 const char *const pszFailure = "VM-exit";
5467
5468 /*
5469 * Activity state.
5470 */
5471 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5472 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5473 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5474 { /* likely */ }
5475 else
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5477
5478 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5479 if ( !AttrSs.n.u2Dpl
5480 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5484
5485 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5486 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5487 {
5488 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5489 { /* likely */ }
5490 else
5491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5492 }
5493
5494 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5495 {
5496 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5497 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5498 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5499 switch (pVmcs->u32GuestActivityState)
5500 {
5501 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5502 {
5503 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5504 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5505 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5506 && ( uVector == X86_XCPT_DB
5507 || uVector == X86_XCPT_MC))
5508 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5509 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5510 { /* likely */ }
5511 else
5512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5513 break;
5514 }
5515
5516 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5517 {
5518 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5519 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5520 && uVector == X86_XCPT_MC))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5524 break;
5525 }
5526
5527 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5528 default:
5529 break;
5530 }
5531 }
5532
5533 /*
5534 * Interruptibility state.
5535 */
5536 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5537 { /* likely */ }
5538 else
5539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5540
5541 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5542 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5543 { /* likely */ }
5544 else
5545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5546
5547 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5548 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5549 { /* likely */ }
5550 else
5551 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5552
5553 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5554 {
5555 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5556 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5557 {
5558 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5559 { /* likely */ }
5560 else
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5562 }
5563 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5564 {
5565 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5566 { /* likely */ }
5567 else
5568 {
5569 /*
5570 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5571 * We update the Exit qualification only when blocking-by-STI is set
5572 * without blocking-by-MovSS being set. Although in practise it does not
5573 * make much difference since the order of checks are implementation defined.
5574 */
5575 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5576 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5578 }
5579
5580 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5581 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5582 { /* likely */ }
5583 else
5584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5585 }
5586 }
5587
5588 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5589 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5590 { /* likely */ }
5591 else
5592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5593
5594 /* We don't support SGX yet. So enclave-interruption must not be set. */
5595 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5596 { /* likely */ }
5597 else
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5599
5600 /*
5601 * Pending debug exceptions.
5602 */
5603 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5604 ? pVmcs->u64GuestPendingDbgXcpts.u
5605 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5606 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5610
5611 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5612 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5613 {
5614 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5615 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5616 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5618
5619 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5620 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5621 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5623 }
5624
5625 /* We don't support RTM (Real-time Transactional Memory) yet. */
5626 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5627 { /* likely */ }
5628 else
5629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5630
5631 /*
5632 * VMCS link pointer.
5633 */
5634 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5635 {
5636 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5637 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5638 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5639 { /* likely */ }
5640 else
5641 {
5642 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5644 }
5645
5646 /* Validate the address. */
5647 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5648 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5649 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5650 { /* likely */ }
5651 else
5652 {
5653 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5655 }
5656
5657 /* Read the VMCS-link pointer from guest memory. */
5658 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5659 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5660 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
5661 if (RT_SUCCESS(rc))
5662 { /* likely */ }
5663 else
5664 {
5665 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5667 }
5668
5669 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5670 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5671 { /* likely */ }
5672 else
5673 {
5674 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5675 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5676 }
5677
5678 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5679 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5680 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5681 { /* likely */ }
5682 else
5683 {
5684 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5686 }
5687
5688 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5689 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5690 }
5691
5692 NOREF(pszInstr);
5693 NOREF(pszFailure);
5694 return VINF_SUCCESS;
5695}
5696
5697
5698/**
5699 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5700 * VM-entry.
5701 *
5702 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5703 * @param pVCpu The cross context virtual CPU structure.
5704 * @param pszInstr The VMX instruction name (for logging purposes).
5705 * @param pVmcs Pointer to the virtual VMCS.
5706 */
5707IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5708{
5709 /*
5710 * Check PDPTEs.
5711 * See Intel spec. 4.4.1 "PDPTE Registers".
5712 */
5713 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5714 const char *const pszFailure = "VM-exit";
5715
5716 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5717 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5718 if (RT_SUCCESS(rc))
5719 {
5720 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5721 {
5722 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5723 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5724 { /* likely */ }
5725 else
5726 {
5727 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5728 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5729 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5730 }
5731 }
5732 }
5733 else
5734 {
5735 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5737 }
5738
5739 NOREF(pszFailure);
5740 NOREF(pszInstr);
5741 return rc;
5742}
5743
5744
5745/**
5746 * Checks guest PDPTEs as part of VM-entry.
5747 *
5748 * @param pVCpu The cross context virtual CPU structure.
5749 * @param pszInstr The VMX instruction name (for logging purposes).
5750 */
5751IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5752{
5753 /*
5754 * Guest PDPTEs.
5755 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5756 */
5757 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5758 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5759
5760 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5761 int rc;
5762 if ( !fGstInLongMode
5763 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5764 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5765 {
5766 /*
5767 * We don't support nested-paging for nested-guests yet.
5768 *
5769 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5770 * rather we need to check the PDPTEs referenced by the guest CR3.
5771 */
5772 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5773 }
5774 else
5775 rc = VINF_SUCCESS;
5776 return rc;
5777}
5778
5779
5780/**
5781 * Checks guest-state as part of VM-entry.
5782 *
5783 * @returns VBox status code.
5784 * @param pVCpu The cross context virtual CPU structure.
5785 * @param pszInstr The VMX instruction name (for logging purposes).
5786 */
5787IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5788{
5789 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5790 if (RT_SUCCESS(rc))
5791 {
5792 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5793 if (RT_SUCCESS(rc))
5794 {
5795 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5796 if (RT_SUCCESS(rc))
5797 {
5798 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5799 if (RT_SUCCESS(rc))
5800 {
5801 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5802 if (RT_SUCCESS(rc))
5803 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5804 }
5805 }
5806 }
5807 }
5808 return rc;
5809}
5810
5811
5812/**
5813 * Checks host-state as part of VM-entry.
5814 *
5815 * @returns VBox status code.
5816 * @param pVCpu The cross context virtual CPU structure.
5817 * @param pszInstr The VMX instruction name (for logging purposes).
5818 */
5819IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5820{
5821 /*
5822 * Host Control Registers and MSRs.
5823 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5824 */
5825 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5826 const char * const pszFailure = "VMFail";
5827
5828 /* CR0 reserved bits. */
5829 {
5830 /* CR0 MB1 bits. */
5831 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5832 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5833 { /* likely */ }
5834 else
5835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5836
5837 /* CR0 MBZ bits. */
5838 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5839 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5840 { /* likely */ }
5841 else
5842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5843 }
5844
5845 /* CR4 reserved bits. */
5846 {
5847 /* CR4 MB1 bits. */
5848 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5849 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5850 { /* likely */ }
5851 else
5852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5853
5854 /* CR4 MBZ bits. */
5855 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5856 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5857 { /* likely */ }
5858 else
5859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5860 }
5861
5862 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5863 {
5864 /* CR3 reserved bits. */
5865 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5869
5870 /* SYSENTER ESP and SYSENTER EIP. */
5871 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5872 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5873 { /* likely */ }
5874 else
5875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5876 }
5877
5878 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5879 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5880
5881 /* PAT MSR. */
5882 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5883 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5884 { /* likely */ }
5885 else
5886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5887
5888 /* EFER MSR. */
5889 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5890 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5891 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5892 { /* likely */ }
5893 else
5894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5895
5896 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5897 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5898 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5899 if ( fHostInLongMode == fHostLma
5900 && fHostInLongMode == fHostLme)
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5904
5905 /*
5906 * Host Segment and Descriptor-Table Registers.
5907 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5908 */
5909 /* Selector RPL and TI. */
5910 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5911 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5912 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5913 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5914 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5915 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5916 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5917 { /* likely */ }
5918 else
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5920
5921 /* CS and TR selectors cannot be 0. */
5922 if ( pVmcs->HostCs
5923 && pVmcs->HostTr)
5924 { /* likely */ }
5925 else
5926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5927
5928 /* SS cannot be 0 if 32-bit host. */
5929 if ( fHostInLongMode
5930 || pVmcs->HostSs)
5931 { /* likely */ }
5932 else
5933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5934
5935 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5936 {
5937 /* FS, GS, GDTR, IDTR, TR base address. */
5938 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5939 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5940 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5941 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5942 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5943 { /* likely */ }
5944 else
5945 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5946 }
5947
5948 /*
5949 * Host address-space size for 64-bit CPUs.
5950 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5951 */
5952 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5953 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5954 {
5955 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5956
5957 /* Logical processor in IA-32e mode. */
5958 if (fCpuInLongMode)
5959 {
5960 if (fHostInLongMode)
5961 {
5962 /* PAE must be set. */
5963 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5964 { /* likely */ }
5965 else
5966 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5967
5968 /* RIP must be canonical. */
5969 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5970 { /* likely */ }
5971 else
5972 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5973 }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5976 }
5977 else
5978 {
5979 /* Logical processor is outside IA-32e mode. */
5980 if ( !fGstInLongMode
5981 && !fHostInLongMode)
5982 {
5983 /* PCIDE should not be set. */
5984 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5985 { /* likely */ }
5986 else
5987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5988
5989 /* The high 32-bits of RIP MBZ. */
5990 if (!pVmcs->u64HostRip.s.Hi)
5991 { /* likely */ }
5992 else
5993 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5994 }
5995 else
5996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5997 }
5998 }
5999 else
6000 {
6001 /* Host address-space size for 32-bit CPUs. */
6002 if ( !fGstInLongMode
6003 && !fHostInLongMode)
6004 { /* likely */ }
6005 else
6006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6007 }
6008
6009 NOREF(pszInstr);
6010 NOREF(pszFailure);
6011 return VINF_SUCCESS;
6012}
6013
6014
6015/**
6016 * Checks VM-entry controls fields as part of VM-entry.
6017 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6018 *
6019 * @returns VBox status code.
6020 * @param pVCpu The cross context virtual CPU structure.
6021 * @param pszInstr The VMX instruction name (for logging purposes).
6022 */
6023IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPUCC pVCpu, const char *pszInstr)
6024{
6025 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6026 const char * const pszFailure = "VMFail";
6027
6028 /* VM-entry controls. */
6029 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6030 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6031 { /* likely */ }
6032 else
6033 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6034
6035 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6036 { /* likely */ }
6037 else
6038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6039
6040 /* Event injection. */
6041 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6042 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6043 {
6044 /* Type and vector. */
6045 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6046 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6047 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6048 if ( !uRsvd
6049 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6050 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6051 { /* likely */ }
6052 else
6053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6054
6055 /* Exception error code. */
6056 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6057 {
6058 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6059 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6060 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6061 { /* likely */ }
6062 else
6063 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6064
6065 /* Exceptions that provide an error code. */
6066 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6067 && ( uVector == X86_XCPT_DF
6068 || uVector == X86_XCPT_TS
6069 || uVector == X86_XCPT_NP
6070 || uVector == X86_XCPT_SS
6071 || uVector == X86_XCPT_GP
6072 || uVector == X86_XCPT_PF
6073 || uVector == X86_XCPT_AC))
6074 { /* likely */ }
6075 else
6076 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6077
6078 /* Exception error-code reserved bits. */
6079 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6080 { /* likely */ }
6081 else
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6083
6084 /* Injecting a software interrupt, software exception or privileged software exception. */
6085 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6086 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6087 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6088 {
6089 /* Instruction length must be in the range 0-15. */
6090 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6091 { /* likely */ }
6092 else
6093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6094
6095 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6096 if ( pVmcs->u32EntryInstrLen != 0
6097 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6098 { /* likely */ }
6099 else
6100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6101 }
6102 }
6103 }
6104
6105 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6106 if (pVmcs->u32EntryMsrLoadCount)
6107 {
6108 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6109 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6110 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6111 { /* likely */ }
6112 else
6113 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6114 }
6115
6116 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6117 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6118
6119 NOREF(pszInstr);
6120 NOREF(pszFailure);
6121 return VINF_SUCCESS;
6122}
6123
6124
6125/**
6126 * Checks VM-exit controls fields as part of VM-entry.
6127 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6128 *
6129 * @returns VBox status code.
6130 * @param pVCpu The cross context virtual CPU structure.
6131 * @param pszInstr The VMX instruction name (for logging purposes).
6132 */
6133IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPUCC pVCpu, const char *pszInstr)
6134{
6135 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6136 const char * const pszFailure = "VMFail";
6137
6138 /* VM-exit controls. */
6139 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6140 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6141 { /* likely */ }
6142 else
6143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6144
6145 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6149
6150 /* Save preemption timer without activating it. */
6151 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6152 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6153 { /* likely */ }
6154 else
6155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6156
6157 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6158 if (pVmcs->u32ExitMsrStoreCount)
6159 {
6160 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6161 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6162 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6163 { /* likely */ }
6164 else
6165 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6166 }
6167
6168 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6169 if (pVmcs->u32ExitMsrLoadCount)
6170 {
6171 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6172 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6173 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6174 { /* likely */ }
6175 else
6176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6177 }
6178
6179 NOREF(pszInstr);
6180 NOREF(pszFailure);
6181 return VINF_SUCCESS;
6182}
6183
6184
6185/**
6186 * Checks VM-execution controls fields as part of VM-entry.
6187 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6188 *
6189 * @returns VBox status code.
6190 * @param pVCpu The cross context virtual CPU structure.
6191 * @param pszInstr The VMX instruction name (for logging purposes).
6192 *
6193 * @remarks This may update secondary-processor based VM-execution control fields
6194 * in the current VMCS if necessary.
6195 */
6196IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPUCC pVCpu, const char *pszInstr)
6197{
6198 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6199 const char * const pszFailure = "VMFail";
6200
6201 /* Pin-based VM-execution controls. */
6202 {
6203 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6204 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6205 { /* likely */ }
6206 else
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6208
6209 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6210 { /* likely */ }
6211 else
6212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6213 }
6214
6215 /* Processor-based VM-execution controls. */
6216 {
6217 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6218 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6222
6223 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6224 { /* likely */ }
6225 else
6226 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6227 }
6228
6229 /* Secondary processor-based VM-execution controls. */
6230 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6231 {
6232 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6233 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6234 { /* likely */ }
6235 else
6236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6237
6238 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6239 { /* likely */ }
6240 else
6241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6242 }
6243 else
6244 Assert(!pVmcs->u32ProcCtls2);
6245
6246 /* CR3-target count. */
6247 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6251
6252 /* I/O bitmaps physical addresses. */
6253 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6254 {
6255 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6256 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6257 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6261
6262 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6263 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6264 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6265 { /* likely */ }
6266 else
6267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6268 }
6269
6270 /* MSR bitmap physical address. */
6271 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6272 {
6273 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6274 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6275 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6276 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6280
6281 /* Read the MSR bitmap. */
6282 /** @todo NSTVMX: Move this to be done later (while loading guest state) when
6283 * implementing fast path. */
6284 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6285 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6286 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6287 if (RT_SUCCESS(rc))
6288 { /* likely */ }
6289 else
6290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6291 }
6292
6293 /* TPR shadow related controls. */
6294 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6295 {
6296 /* Virtual-APIC page physical address. */
6297 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6298 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6299 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6300 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6301 { /* likely */ }
6302 else
6303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6304
6305 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6306 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6307 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6308 { /* likely */ }
6309 else
6310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6311
6312 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6313 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6314 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6315 {
6316 /* Read the VTPR from the virtual-APIC page. */
6317 uint8_t u8VTpr;
6318 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6319 if (RT_SUCCESS(rc))
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6323
6324 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6325 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6326 { /* likely */ }
6327 else
6328 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6329 }
6330 }
6331 else
6332 {
6333 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6334 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6335 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6336 { /* likely */ }
6337 else
6338 {
6339 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6341 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6343 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6345 }
6346 }
6347
6348 /* NMI exiting and virtual-NMIs. */
6349 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6350 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6351 { /* likely */ }
6352 else
6353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6354
6355 /* Virtual-NMIs and NMI-window exiting. */
6356 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6357 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6361
6362 /* Virtualize APIC accesses. */
6363 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6364 {
6365 /* APIC-access physical address. */
6366 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6367 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6368 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6369 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6370 { /* likely */ }
6371 else
6372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6373
6374 /*
6375 * Disallow APIC-access page and virtual-APIC page from being the same address.
6376 * Note! This is not an Intel requirement, but one imposed by our implementation.
6377 */
6378 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6379 * redirecting accesses between the APIC-access page and the virtual-APIC
6380 * page. If any guest hypervisor requires this, we can implement it later. */
6381 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6382 {
6383 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6384 if (GCPhysVirtApic != GCPhysApicAccess)
6385 { /* likely */ }
6386 else
6387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6388 }
6389
6390 /*
6391 * Register the handler for the APIC-access page.
6392 *
6393 * We don't deregister the APIC-access page handler during the VM-exit as a different
6394 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6395 *
6396 * We leave the page registered until the first access that happens outside VMX non-root
6397 * mode. Guest software is allowed to access structures such as the APIC-access page
6398 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6399 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6400 *
6401 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6402 */
6403 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6404 {
6405 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6406 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6407 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6408 if (RT_SUCCESS(rc))
6409 { /* likely */ }
6410 else
6411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6412 }
6413 }
6414
6415 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6416 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6417 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6418 { /* likely */ }
6419 else
6420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6421
6422 /* Virtual-interrupt delivery requires external interrupt exiting. */
6423 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6424 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6425 { /* likely */ }
6426 else
6427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6428
6429 /* VPID. */
6430 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6431 || pVmcs->u16Vpid != 0)
6432 { /* likely */ }
6433 else
6434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6435
6436 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6437 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6438 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6439 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6440 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6441 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6442 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6443
6444 /* VMCS shadowing. */
6445 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6446 {
6447 /* VMREAD-bitmap physical address. */
6448 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6449 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6450 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6451 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6452 { /* likely */ }
6453 else
6454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6455
6456 /* VMWRITE-bitmap physical address. */
6457 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6458 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6459 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6460 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6461 { /* likely */ }
6462 else
6463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6464
6465 /* Read the VMREAD-bitmap. */
6466 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6467 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6468 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6469 if (RT_SUCCESS(rc))
6470 { /* likely */ }
6471 else
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6473
6474 /* Read the VMWRITE-bitmap. */
6475 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6476 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6477 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6478 if (RT_SUCCESS(rc))
6479 { /* likely */ }
6480 else
6481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6482 }
6483
6484 NOREF(pszInstr);
6485 NOREF(pszFailure);
6486 return VINF_SUCCESS;
6487}
6488
6489
6490/**
6491 * Loads the guest control registers, debug register and some MSRs as part of
6492 * VM-entry.
6493 *
6494 * @param pVCpu The cross context virtual CPU structure.
6495 */
6496IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6497{
6498 /*
6499 * Load guest control registers, debug registers and MSRs.
6500 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6501 */
6502 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6503
6504 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6505 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6506 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6507 CPUMSetGuestCR0(pVCpu, uGstCr0);
6508 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6509 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6510
6511 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6512 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6513
6514 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6515 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6516 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6517
6518 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6519 {
6520 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6521
6522 /* EFER MSR. */
6523 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6524 {
6525 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6526 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6527 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6528 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6529 if (fGstInLongMode)
6530 {
6531 /* If the nested-guest is in long mode, LMA and LME are both set. */
6532 Assert(fGstPaging);
6533 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6534 }
6535 else
6536 {
6537 /*
6538 * If the nested-guest is outside long mode:
6539 * - With paging: LMA is cleared, LME is cleared.
6540 * - Without paging: LMA is cleared, LME is left unmodified.
6541 */
6542 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6543 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6544 }
6545 }
6546 /* else: see below. */
6547 }
6548
6549 /* PAT MSR. */
6550 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6551 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6552
6553 /* EFER MSR. */
6554 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6555 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6556
6557 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6558 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6559
6560 /* We don't support IA32_BNDCFGS MSR yet. */
6561 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6562
6563 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6564}
6565
6566
6567/**
6568 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6569 *
6570 * @param pVCpu The cross context virtual CPU structure.
6571 */
6572IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6573{
6574 /*
6575 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6576 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6577 */
6578 /* CS, SS, ES, DS, FS, GS. */
6579 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6580 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6581 {
6582 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6583 CPUMSELREG VmcsSelReg;
6584 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6585 AssertRC(rc); NOREF(rc);
6586 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6587 {
6588 pGstSelReg->Sel = VmcsSelReg.Sel;
6589 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6590 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6591 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6592 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6593 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6594 }
6595 else
6596 {
6597 pGstSelReg->Sel = VmcsSelReg.Sel;
6598 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6599 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6600 switch (iSegReg)
6601 {
6602 case X86_SREG_CS:
6603 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6604 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6605 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6606 break;
6607
6608 case X86_SREG_SS:
6609 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6610 pGstSelReg->u32Limit = 0;
6611 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6612 break;
6613
6614 case X86_SREG_ES:
6615 case X86_SREG_DS:
6616 pGstSelReg->u64Base = 0;
6617 pGstSelReg->u32Limit = 0;
6618 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6619 break;
6620
6621 case X86_SREG_FS:
6622 case X86_SREG_GS:
6623 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6624 pGstSelReg->u32Limit = 0;
6625 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6626 break;
6627 }
6628 Assert(pGstSelReg->Attr.n.u1Unusable);
6629 }
6630 }
6631
6632 /* LDTR. */
6633 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6634 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6635 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6636 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6637 {
6638 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6639 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6640 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6641 }
6642 else
6643 {
6644 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6645 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6646 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6647 }
6648
6649 /* TR. */
6650 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6651 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6652 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6653 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6654 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6655 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6656 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6657
6658 /* GDTR. */
6659 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6660 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6661
6662 /* IDTR. */
6663 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6664 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6665}
6666
6667
6668/**
6669 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6670 *
6671 * @returns VBox status code.
6672 * @param pVCpu The cross context virtual CPU structure.
6673 * @param pszInstr The VMX instruction name (for logging purposes).
6674 */
6675IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6676{
6677 /*
6678 * Load guest MSRs.
6679 * See Intel spec. 26.4 "Loading MSRs".
6680 */
6681 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6682 const char *const pszFailure = "VM-exit";
6683
6684 /*
6685 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6686 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6687 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6688 */
6689 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6690 if (!cMsrs)
6691 return VINF_SUCCESS;
6692
6693 /*
6694 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6695 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6696 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6697 */
6698 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6699 if (fIsMsrCountValid)
6700 { /* likely */ }
6701 else
6702 {
6703 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6705 }
6706
6707 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6708 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6709 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6710 if (RT_SUCCESS(rc))
6711 {
6712 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6713 Assert(pMsr);
6714 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6715 {
6716 if ( !pMsr->u32Reserved
6717 && pMsr->u32Msr != MSR_K8_FS_BASE
6718 && pMsr->u32Msr != MSR_K8_GS_BASE
6719 && pMsr->u32Msr != MSR_K6_EFER
6720 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6721 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6722 {
6723 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6724 if (rcStrict == VINF_SUCCESS)
6725 continue;
6726
6727 /*
6728 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6729 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6730 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6731 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6732 * MSR in ring-0 if possible, or come up with a better, generic solution.
6733 */
6734 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6735 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6736 ? kVmxVDiag_Vmentry_MsrLoadRing3
6737 : kVmxVDiag_Vmentry_MsrLoad;
6738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6739 }
6740 else
6741 {
6742 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6744 }
6745 }
6746 }
6747 else
6748 {
6749 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6751 }
6752
6753 NOREF(pszInstr);
6754 NOREF(pszFailure);
6755 return VINF_SUCCESS;
6756}
6757
6758
6759/**
6760 * Loads the guest-state non-register state as part of VM-entry.
6761 *
6762 * @returns VBox status code.
6763 * @param pVCpu The cross context virtual CPU structure.
6764 *
6765 * @remarks This must be called only after loading the nested-guest register state
6766 * (especially nested-guest RIP).
6767 */
6768IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6769{
6770 /*
6771 * Load guest non-register state.
6772 * See Intel spec. 26.6 "Special Features of VM Entry"
6773 */
6774 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6775
6776 /*
6777 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6778 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6779 *
6780 * See Intel spec. 26.6.1 "Interruptibility State".
6781 */
6782 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6783 if ( !fEntryVectoring
6784 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6785 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6786 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6787 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6788
6789 /* NMI blocking. */
6790 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6791 {
6792 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6793 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6794 else
6795 {
6796 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6797 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6798 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6799 }
6800 }
6801 else
6802 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6803
6804 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6805
6806 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6807 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6808
6809 /* VPID is irrelevant. We don't support VPID yet. */
6810
6811 /* Clear address-range monitoring. */
6812 EMMonitorWaitClear(pVCpu);
6813}
6814
6815
6816/**
6817 * Loads the guest-state as part of VM-entry.
6818 *
6819 * @returns VBox status code.
6820 * @param pVCpu The cross context virtual CPU structure.
6821 * @param pszInstr The VMX instruction name (for logging purposes).
6822 *
6823 * @remarks This must be done after all the necessary steps prior to loading of
6824 * guest-state (e.g. checking various VMCS state).
6825 */
6826IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6827{
6828 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6829 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6830
6831 /*
6832 * Load guest RIP, RSP and RFLAGS.
6833 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6834 */
6835 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6836 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6837 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6838 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6839
6840 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6841 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6842 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6843
6844 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6845
6846 NOREF(pszInstr);
6847 return VINF_SUCCESS;
6848}
6849
6850
6851/**
6852 * Returns whether there are is a pending debug exception on VM-entry.
6853 *
6854 * @param pVCpu The cross context virtual CPU structure.
6855 * @param pszInstr The VMX instruction name (for logging purposes).
6856 */
6857IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6858{
6859 /*
6860 * Pending debug exceptions.
6861 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6862 */
6863 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6864 Assert(pVmcs);
6865
6866 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6867 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6868 if (fPendingDbgXcpt)
6869 {
6870 uint8_t uEntryIntInfoType;
6871 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6872 if (fEntryVectoring)
6873 {
6874 switch (uEntryIntInfoType)
6875 {
6876 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6877 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6878 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6879 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6880 fPendingDbgXcpt = false;
6881 break;
6882
6883 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6884 {
6885 /*
6886 * Whether the pending debug exception for software exceptions other than
6887 * #BP and #OF is delivered after injecting the exception or is discard
6888 * is CPU implementation specific. We will discard them (easier).
6889 */
6890 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6891 if ( uVector != X86_XCPT_BP
6892 && uVector != X86_XCPT_OF)
6893 fPendingDbgXcpt = false;
6894 RT_FALL_THRU();
6895 }
6896 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6897 {
6898 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6899 fPendingDbgXcpt = false;
6900 break;
6901 }
6902 }
6903 }
6904 else
6905 {
6906 /*
6907 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6908 * pending debug exception is held pending or is discarded is CPU implementation
6909 * specific. We will discard them (easier).
6910 */
6911 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6912 fPendingDbgXcpt = false;
6913
6914 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6915 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6916 fPendingDbgXcpt = false;
6917 }
6918 }
6919
6920 NOREF(pszInstr);
6921 return fPendingDbgXcpt;
6922}
6923
6924
6925/**
6926 * Set up the monitor-trap flag (MTF).
6927 *
6928 * @param pVCpu The cross context virtual CPU structure.
6929 * @param pszInstr The VMX instruction name (for logging purposes).
6930 */
6931IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6932{
6933 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6934 Assert(pVmcs);
6935 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6936 {
6937 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6938 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6939 }
6940 else
6941 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6942 NOREF(pszInstr);
6943}
6944
6945
6946/**
6947 * Sets up NMI-window exiting.
6948 *
6949 * @param pVCpu The cross context virtual CPU structure.
6950 * @param pszInstr The VMX instruction name (for logging purposes).
6951 */
6952IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6953{
6954 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6955 Assert(pVmcs);
6956 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6957 {
6958 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6959 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6960 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6961 }
6962 else
6963 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6964 NOREF(pszInstr);
6965}
6966
6967
6968/**
6969 * Sets up interrupt-window exiting.
6970 *
6971 * @param pVCpu The cross context virtual CPU structure.
6972 * @param pszInstr The VMX instruction name (for logging purposes).
6973 */
6974IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6975{
6976 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6977 Assert(pVmcs);
6978 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6979 {
6980 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6981 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6982 }
6983 else
6984 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6985 NOREF(pszInstr);
6986}
6987
6988
6989/**
6990 * Set up the VMX-preemption timer.
6991 *
6992 * @param pVCpu The cross context virtual CPU structure.
6993 * @param pszInstr The VMX instruction name (for logging purposes).
6994 */
6995IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6996{
6997 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6998 Assert(pVmcs);
6999 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7000 {
7001 uint64_t const uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7002 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7003 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7004
7005 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7006 }
7007 else
7008 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7009
7010 NOREF(pszInstr);
7011}
7012
7013
7014/**
7015 * Injects an event using TRPM given a VM-entry interruption info. and related
7016 * fields.
7017 *
7018 * @param pVCpu The cross context virtual CPU structure.
7019 * @param pszInstr The VMX instruction name (for logging purposes).
7020 * @param uEntryIntInfo The VM-entry interruption info.
7021 * @param uErrCode The error code associated with the event if any.
7022 * @param cbInstr The VM-entry instruction length (for software
7023 * interrupts and software exceptions). Pass 0
7024 * otherwise.
7025 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7026 */
7027IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7028 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7029{
7030 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7031
7032 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7033 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7034 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7035
7036 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7037
7038 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7039 AssertRC(rc);
7040 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7041
7042 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7043 {
7044 TRPMSetErrorCode(pVCpu, uErrCode);
7045 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7046 }
7047
7048 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7049 {
7050 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7051 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7052 }
7053 else
7054 {
7055 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7056 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7057 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7058 {
7059 TRPMSetInstrLength(pVCpu, cbInstr);
7060 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7061 }
7062 }
7063
7064 NOREF(pszInstr);
7065}
7066
7067
7068/**
7069 * Performs event injection (if any) as part of VM-entry.
7070 *
7071 * @param pVCpu The cross context virtual CPU structure.
7072 * @param pszInstr The VMX instruction name (for logging purposes).
7073 */
7074IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7075{
7076 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7077
7078 /*
7079 * Inject events.
7080 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7081 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7082 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7083 * the actually delivery of this event.
7084 *
7085 * See Intel spec. 26.5 "Event Injection".
7086 */
7087 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7088 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7089
7090 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7091 if (fEntryIntInfoValid)
7092 {
7093 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7094 {
7095 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7096 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7097 }
7098 else
7099 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7100 pVCpu->cpum.GstCtx.cr2);
7101
7102 /*
7103 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7104 *
7105 * However, we do it here on VM-entry as well because while it isn't visible to guest
7106 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7107 * execution using hardware-assisted VT-x, it will not be try to inject the event again.
7108 *
7109 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7110 */
7111 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7112 }
7113 else
7114 {
7115 /*
7116 * Inject any pending guest debug exception.
7117 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7118 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7119 */
7120 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7121 if (fPendingDbgXcpt)
7122 {
7123 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7124 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7125 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7126 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7127 0 /* GCPtrFaultAddress */);
7128 }
7129 }
7130
7131 NOREF(pszInstr);
7132}
7133
7134
7135/**
7136 * Initializes all read-only VMCS fields as part of VM-entry.
7137 *
7138 * @param pVCpu The cross context virtual CPU structure.
7139 */
7140IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7141{
7142 /*
7143 * Any VMCS field which we do not establish on every VM-exit but may potentially
7144 * be used on the VM-exit path of a guest hypervisor -and- is not explicitly
7145 * specified to be undefined needs to be initialized here.
7146 *
7147 * Thus, it is especially important to clear the Exit qualification field
7148 * since it must be zero for VM-exits where it is not used. Similarly, the
7149 * VM-exit interruption information field's valid bit needs to be cleared for
7150 * the same reasons.
7151 */
7152 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7153 Assert(pVmcs);
7154
7155 /* 16-bit (none currently). */
7156 /* 32-bit. */
7157 pVmcs->u32RoVmInstrError = 0;
7158 pVmcs->u32RoExitReason = 0;
7159 pVmcs->u32RoExitIntInfo = 0;
7160 pVmcs->u32RoExitIntErrCode = 0;
7161 pVmcs->u32RoIdtVectoringInfo = 0;
7162 pVmcs->u32RoIdtVectoringErrCode = 0;
7163 pVmcs->u32RoExitInstrLen = 0;
7164 pVmcs->u32RoExitInstrInfo = 0;
7165
7166 /* 64-bit. */
7167 pVmcs->u64RoGuestPhysAddr.u = 0;
7168
7169 /* Natural-width. */
7170 pVmcs->u64RoExitQual.u = 0;
7171 pVmcs->u64RoIoRcx.u = 0;
7172 pVmcs->u64RoIoRsi.u = 0;
7173 pVmcs->u64RoIoRdi.u = 0;
7174 pVmcs->u64RoIoRip.u = 0;
7175 pVmcs->u64RoGuestLinearAddr.u = 0;
7176}
7177
7178
7179/**
7180 * VMLAUNCH/VMRESUME instruction execution worker.
7181 *
7182 * @returns Strict VBox status code.
7183 * @param pVCpu The cross context virtual CPU structure.
7184 * @param cbInstr The instruction length in bytes.
7185 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7186 * VMXINSTRID_VMRESUME).
7187 *
7188 * @remarks Common VMX instruction checks are already expected to by the caller,
7189 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7190 */
7191IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7192{
7193# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7194 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7195 return VINF_EM_RAW_EMULATE_INSTR;
7196# else
7197 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7198 || uInstrId == VMXINSTRID_VMRESUME);
7199 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7200
7201 /* Nested-guest intercept. */
7202 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7203 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7204
7205 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7206
7207 /*
7208 * Basic VM-entry checks.
7209 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7210 * The checks following that do not have to follow a specific order.
7211 *
7212 * See Intel spec. 26.1 "Basic VM-entry Checks".
7213 */
7214
7215 /* CPL. */
7216 if (pVCpu->iem.s.uCpl == 0)
7217 { /* likely */ }
7218 else
7219 {
7220 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7221 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7222 return iemRaiseGeneralProtectionFault0(pVCpu);
7223 }
7224
7225 /* Current VMCS valid. */
7226 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7227 { /* likely */ }
7228 else
7229 {
7230 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7231 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7232 iemVmxVmFailInvalid(pVCpu);
7233 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7234 return VINF_SUCCESS;
7235 }
7236
7237 /* Current VMCS is not a shadow VMCS. */
7238 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7239 { /* likely */ }
7240 else
7241 {
7242 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7243 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7244 iemVmxVmFailInvalid(pVCpu);
7245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7246 return VINF_SUCCESS;
7247 }
7248
7249 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7250 * use block-by-STI here which is not quite correct. */
7251 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7252 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7253 { /* likely */ }
7254 else
7255 {
7256 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7257 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7258 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7259 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7260 return VINF_SUCCESS;
7261 }
7262
7263 if (uInstrId == VMXINSTRID_VMLAUNCH)
7264 {
7265 /* VMLAUNCH with non-clear VMCS. */
7266 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7267 { /* likely */ }
7268 else
7269 {
7270 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7271 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7272 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7273 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7274 return VINF_SUCCESS;
7275 }
7276 }
7277 else
7278 {
7279 /* VMRESUME with non-launched VMCS. */
7280 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7281 { /* likely */ }
7282 else
7283 {
7284 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7285 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7286 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7287 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7288 return VINF_SUCCESS;
7289 }
7290 }
7291
7292 /*
7293 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7294 * while entering VMX non-root mode. We do some of this while checking VM-execution
7295 * controls. The guest hypervisor should not make assumptions and cannot expect
7296 * predictable behavior if changes to these structures are made in guest memory while
7297 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7298 * modify them anyway as we cache them in host memory.
7299 *
7300 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7301 */
7302 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7303 Assert(pVmcs);
7304 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7305
7306 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7307 if (RT_SUCCESS(rc))
7308 {
7309 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7310 if (RT_SUCCESS(rc))
7311 {
7312 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7313 if (RT_SUCCESS(rc))
7314 {
7315 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7316 if (RT_SUCCESS(rc))
7317 {
7318 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7319 iemVmxVmentryInitReadOnlyFields(pVCpu);
7320
7321 /*
7322 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7323 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7324 * VM-exit when required.
7325 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7326 */
7327 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7328
7329 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7330 if (RT_SUCCESS(rc))
7331 {
7332 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7333 if (RT_SUCCESS(rc))
7334 {
7335 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7336 if (RT_SUCCESS(rc))
7337 {
7338 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7339
7340 /* VMLAUNCH instruction must update the VMCS launch state. */
7341 if (uInstrId == VMXINSTRID_VMLAUNCH)
7342 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7343
7344 /* Perform the VMX transition (PGM updates). */
7345 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7346 if (rcStrict == VINF_SUCCESS)
7347 { /* likely */ }
7348 else if (RT_SUCCESS(rcStrict))
7349 {
7350 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7351 VBOXSTRICTRC_VAL(rcStrict)));
7352 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7353 }
7354 else
7355 {
7356 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7357 return rcStrict;
7358 }
7359
7360 /* Paranoia. */
7361 Assert(rcStrict == VINF_SUCCESS);
7362
7363 /* We've now entered nested-guest execution. */
7364 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7365
7366 /*
7367 * The priority of potential VM-exits during VM-entry is important.
7368 * The priorities of VM-exits and events are listed from highest
7369 * to lowest as follows:
7370 *
7371 * 1. Event injection.
7372 * 2. Trap on task-switch (T flag set in TSS).
7373 * 3. TPR below threshold / APIC-write.
7374 * 4. SMI, INIT.
7375 * 5. MTF exit.
7376 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7377 * 7. VMX-preemption timer.
7378 * 9. NMI-window exit.
7379 * 10. NMI injection.
7380 * 11. Interrupt-window exit.
7381 * 12. Virtual-interrupt injection.
7382 * 13. Interrupt injection.
7383 * 14. Process next instruction (fetch, decode, execute).
7384 */
7385
7386 /* Setup VMX-preemption timer. */
7387 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7388
7389 /* Setup monitor-trap flag. */
7390 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7391
7392 /* Setup NMI-window exiting. */
7393 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7394
7395 /* Setup interrupt-window exiting. */
7396 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7397
7398 /*
7399 * Inject any event that the guest hypervisor wants to inject.
7400 * Note! We cannot immediately perform the event injection here as we may have
7401 * pending PGM operations to perform due to switching page tables and/or
7402 * mode.
7403 */
7404 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7405
7406# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7407 /* Reschedule to IEM-only execution of the nested-guest. */
7408 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7409 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7410 if (rcSched != VINF_SUCCESS)
7411 iemSetPassUpStatus(pVCpu, rcSched);
7412# endif
7413
7414 /* Finally, done. */
7415 Log(("%s: cs:rip=%#04x:%#RX64 cr3=%#RX64\n", pszInstr, pVCpu->cpum.GstCtx.cs.Sel,
7416 pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr3));
7417 return VINF_SUCCESS;
7418 }
7419 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7420 pVmcs->u64RoExitQual.u);
7421 }
7422 }
7423 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7424 pVmcs->u64RoExitQual.u);
7425 }
7426
7427 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7429 return VINF_SUCCESS;
7430 }
7431 }
7432 }
7433
7434 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7436 return VINF_SUCCESS;
7437# endif
7438}
7439
7440
7441/**
7442 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7443 * (causes a VM-exit) or not.
7444 *
7445 * @returns @c true if the instruction is intercepted, @c false otherwise.
7446 * @param pVCpu The cross context virtual CPU structure.
7447 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7448 * VMX_EXIT_WRMSR).
7449 * @param idMsr The MSR.
7450 */
7451IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7452{
7453 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7454 Assert( uExitReason == VMX_EXIT_RDMSR
7455 || uExitReason == VMX_EXIT_WRMSR);
7456
7457 /* Consult the MSR bitmap if the feature is supported. */
7458 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7459 Assert(pVmcs);
7460 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7461 {
7462 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7463 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7464 if (uExitReason == VMX_EXIT_RDMSR)
7465 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7466 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7467 }
7468
7469 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7470 return true;
7471}
7472
7473
7474/**
7475 * VMREAD instruction execution worker that does not perform any validation checks.
7476 *
7477 * Callers are expected to have performed the necessary checks and to ensure the
7478 * VMREAD will succeed.
7479 *
7480 * @param pVmcs Pointer to the virtual VMCS.
7481 * @param pu64Dst Where to write the VMCS value.
7482 * @param u64VmcsField The VMCS field.
7483 *
7484 * @remarks May be called with interrupts disabled.
7485 */
7486IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7487{
7488 VMXVMCSFIELD VmcsField;
7489 VmcsField.u = u64VmcsField;
7490 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7491 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7492 uint8_t const uWidthType = (uWidth << 2) | uType;
7493 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7494 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7495 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7496 Assert(offField < VMX_V_VMCS_SIZE);
7497 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7498
7499 /*
7500 * Read the VMCS component based on the field's effective width.
7501 *
7502 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7503 * indicates high bits (little endian).
7504 *
7505 * Note! The caller is responsible to trim the result and update registers
7506 * or memory locations are required. Here we just zero-extend to the largest
7507 * type (i.e. 64-bits).
7508 */
7509 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7510 uint8_t const *pbField = pbVmcs + offField;
7511 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7512 switch (uEffWidth)
7513 {
7514 case VMX_VMCSFIELD_WIDTH_64BIT:
7515 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7516 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7517 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7518 }
7519}
7520
7521
7522/**
7523 * VMREAD common (memory/register) instruction execution worker.
7524 *
7525 * @returns Strict VBox status code.
7526 * @param pVCpu The cross context virtual CPU structure.
7527 * @param cbInstr The instruction length in bytes.
7528 * @param pu64Dst Where to write the VMCS value (only updated when
7529 * VINF_SUCCESS is returned).
7530 * @param u64VmcsField The VMCS field.
7531 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7532 * NULL.
7533 */
7534IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7535 PCVMXVEXITINFO pExitInfo)
7536{
7537 /* Nested-guest intercept. */
7538 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7539 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7540 {
7541 if (pExitInfo)
7542 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7543 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7544 }
7545
7546 /* CPL. */
7547 if (pVCpu->iem.s.uCpl == 0)
7548 { /* likely */ }
7549 else
7550 {
7551 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7552 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7553 return iemRaiseGeneralProtectionFault0(pVCpu);
7554 }
7555
7556 /* VMCS pointer in root mode. */
7557 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7558 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7559 { /* likely */ }
7560 else
7561 {
7562 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7564 iemVmxVmFailInvalid(pVCpu);
7565 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7566 return VINF_SUCCESS;
7567 }
7568
7569 /* VMCS-link pointer in non-root mode. */
7570 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7571 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7572 { /* likely */ }
7573 else
7574 {
7575 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7576 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7577 iemVmxVmFailInvalid(pVCpu);
7578 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7579 return VINF_SUCCESS;
7580 }
7581
7582 /* Supported VMCS field. */
7583 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7584 { /* likely */ }
7585 else
7586 {
7587 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7588 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7589 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7590 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7591 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7592 return VINF_SUCCESS;
7593 }
7594
7595 /*
7596 * Reading from the current or shadow VMCS.
7597 */
7598 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7599 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7600 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7601 Assert(pVmcs);
7602 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7603 return VINF_SUCCESS;
7604}
7605
7606
7607/**
7608 * VMREAD (64-bit register) instruction execution worker.
7609 *
7610 * @returns Strict VBox status code.
7611 * @param pVCpu The cross context virtual CPU structure.
7612 * @param cbInstr The instruction length in bytes.
7613 * @param pu64Dst Where to store the VMCS field's value.
7614 * @param u64VmcsField The VMCS field.
7615 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7616 * NULL.
7617 */
7618IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7619 PCVMXVEXITINFO pExitInfo)
7620{
7621 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7622 if (rcStrict == VINF_SUCCESS)
7623 {
7624 iemVmxVmreadSuccess(pVCpu, cbInstr);
7625 return VINF_SUCCESS;
7626 }
7627
7628 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7629 return rcStrict;
7630}
7631
7632
7633/**
7634 * VMREAD (32-bit register) instruction execution worker.
7635 *
7636 * @returns Strict VBox status code.
7637 * @param pVCpu The cross context virtual CPU structure.
7638 * @param cbInstr The instruction length in bytes.
7639 * @param pu32Dst Where to store the VMCS field's value.
7640 * @param u32VmcsField The VMCS field.
7641 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7642 * NULL.
7643 */
7644IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7645 PCVMXVEXITINFO pExitInfo)
7646{
7647 uint64_t u64Dst;
7648 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7649 if (rcStrict == VINF_SUCCESS)
7650 {
7651 *pu32Dst = u64Dst;
7652 iemVmxVmreadSuccess(pVCpu, cbInstr);
7653 return VINF_SUCCESS;
7654 }
7655
7656 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7657 return rcStrict;
7658}
7659
7660
7661/**
7662 * VMREAD (memory) instruction execution worker.
7663 *
7664 * @returns Strict VBox status code.
7665 * @param pVCpu The cross context virtual CPU structure.
7666 * @param cbInstr The instruction length in bytes.
7667 * @param iEffSeg The effective segment register to use with @a u64Val.
7668 * Pass UINT8_MAX if it is a register access.
7669 * @param GCPtrDst The guest linear address to store the VMCS field's
7670 * value.
7671 * @param u64VmcsField The VMCS field.
7672 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7673 * NULL.
7674 */
7675IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7676 PCVMXVEXITINFO pExitInfo)
7677{
7678 uint64_t u64Dst;
7679 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7680 if (rcStrict == VINF_SUCCESS)
7681 {
7682 /*
7683 * Write the VMCS field's value to the location specified in guest-memory.
7684 */
7685 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7686 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7687 else
7688 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7689 if (rcStrict == VINF_SUCCESS)
7690 {
7691 iemVmxVmreadSuccess(pVCpu, cbInstr);
7692 return VINF_SUCCESS;
7693 }
7694
7695 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7696 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7697 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7698 return rcStrict;
7699 }
7700
7701 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7702 return rcStrict;
7703}
7704
7705
7706/**
7707 * VMWRITE instruction execution worker that does not perform any validation
7708 * checks.
7709 *
7710 * Callers are expected to have performed the necessary checks and to ensure the
7711 * VMWRITE will succeed.
7712 *
7713 * @param pVmcs Pointer to the virtual VMCS.
7714 * @param u64Val The value to write.
7715 * @param u64VmcsField The VMCS field.
7716 *
7717 * @remarks May be called with interrupts disabled.
7718 */
7719IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7720{
7721 VMXVMCSFIELD VmcsField;
7722 VmcsField.u = u64VmcsField;
7723 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7724 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7725 uint8_t const uWidthType = (uWidth << 2) | uType;
7726 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7727 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7728 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7729 Assert(offField < VMX_V_VMCS_SIZE);
7730 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7731
7732 /*
7733 * Write the VMCS component based on the field's effective width.
7734 *
7735 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7736 * indicates high bits (little endian).
7737 */
7738 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7739 uint8_t *pbField = pbVmcs + offField;
7740 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7741 switch (uEffWidth)
7742 {
7743 case VMX_VMCSFIELD_WIDTH_64BIT:
7744 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7745 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7746 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7747 }
7748}
7749
7750
7751/**
7752 * VMWRITE instruction execution worker.
7753 *
7754 * @returns Strict VBox status code.
7755 * @param pVCpu The cross context virtual CPU structure.
7756 * @param cbInstr The instruction length in bytes.
7757 * @param iEffSeg The effective segment register to use with @a u64Val.
7758 * Pass UINT8_MAX if it is a register access.
7759 * @param u64Val The value to write (or guest linear address to the
7760 * value), @a iEffSeg will indicate if it's a memory
7761 * operand.
7762 * @param u64VmcsField The VMCS field.
7763 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7764 * NULL.
7765 */
7766IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7767 PCVMXVEXITINFO pExitInfo)
7768{
7769 /* Nested-guest intercept. */
7770 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7771 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7772 {
7773 if (pExitInfo)
7774 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7775 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7776 }
7777
7778 /* CPL. */
7779 if (pVCpu->iem.s.uCpl == 0)
7780 { /* likely */ }
7781 else
7782 {
7783 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7784 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7785 return iemRaiseGeneralProtectionFault0(pVCpu);
7786 }
7787
7788 /* VMCS pointer in root mode. */
7789 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7790 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7791 { /* likely */ }
7792 else
7793 {
7794 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7795 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7796 iemVmxVmFailInvalid(pVCpu);
7797 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7798 return VINF_SUCCESS;
7799 }
7800
7801 /* VMCS-link pointer in non-root mode. */
7802 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7803 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7804 { /* likely */ }
7805 else
7806 {
7807 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7808 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7809 iemVmxVmFailInvalid(pVCpu);
7810 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7811 return VINF_SUCCESS;
7812 }
7813
7814 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7815 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7816 if (!fIsRegOperand)
7817 {
7818 /* Read the value from the specified guest memory location. */
7819 VBOXSTRICTRC rcStrict;
7820 RTGCPTR const GCPtrVal = u64Val;
7821 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7822 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7823 else
7824 {
7825 uint32_t u32Val;
7826 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7827 u64Val = u32Val;
7828 }
7829 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7830 {
7831 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7832 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7833 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7834 return rcStrict;
7835 }
7836 }
7837 else
7838 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7839
7840 /* Supported VMCS field. */
7841 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7842 { /* likely */ }
7843 else
7844 {
7845 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7846 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7847 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7848 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7849 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7850 return VINF_SUCCESS;
7851 }
7852
7853 /* Read-only VMCS field. */
7854 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7855 if ( !fIsFieldReadOnly
7856 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7857 { /* likely */ }
7858 else
7859 {
7860 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7862 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7863 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7864 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7865 return VINF_SUCCESS;
7866 }
7867
7868 /*
7869 * Write to the current or shadow VMCS.
7870 */
7871 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7872 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7873 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7874 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7875 Assert(pVmcs);
7876 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7877
7878 /* Notify HM that the VMCS content might have changed. */
7879 if (!fInVmxNonRootMode)
7880 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7881
7882 iemVmxVmSucceed(pVCpu);
7883 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7884 return VINF_SUCCESS;
7885}
7886
7887
7888/**
7889 * VMCLEAR instruction execution worker.
7890 *
7891 * @returns Strict VBox status code.
7892 * @param pVCpu The cross context virtual CPU structure.
7893 * @param cbInstr The instruction length in bytes.
7894 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7895 * @param GCPtrVmcs The linear address of the VMCS pointer.
7896 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7897 *
7898 * @remarks Common VMX instruction checks are already expected to by the caller,
7899 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7900 */
7901IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7902 PCVMXVEXITINFO pExitInfo)
7903{
7904 /* Nested-guest intercept. */
7905 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7906 {
7907 if (pExitInfo)
7908 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7909 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7910 }
7911
7912 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7913
7914 /* CPL. */
7915 if (pVCpu->iem.s.uCpl == 0)
7916 { /* likely */ }
7917 else
7918 {
7919 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7920 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7921 return iemRaiseGeneralProtectionFault0(pVCpu);
7922 }
7923
7924 /* Get the VMCS pointer from the location specified by the source memory operand. */
7925 RTGCPHYS GCPhysVmcs;
7926 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7927 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7928 { /* likely */ }
7929 else
7930 {
7931 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7932 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7933 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7934 return rcStrict;
7935 }
7936
7937 /* VMCS pointer alignment. */
7938 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7939 { /* likely */ }
7940 else
7941 {
7942 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7943 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7944 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7945 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7947 return VINF_SUCCESS;
7948 }
7949
7950 /* VMCS physical-address width limits. */
7951 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7952 { /* likely */ }
7953 else
7954 {
7955 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7956 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7957 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7958 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7959 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7960 return VINF_SUCCESS;
7961 }
7962
7963 /* VMCS is not the VMXON region. */
7964 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7965 { /* likely */ }
7966 else
7967 {
7968 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7969 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7970 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7971 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7972 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7973 return VINF_SUCCESS;
7974 }
7975
7976 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7977 restriction imposed by our implementation. */
7978 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7979 { /* likely */ }
7980 else
7981 {
7982 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7983 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7984 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7985 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7986 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7987 return VINF_SUCCESS;
7988 }
7989
7990 /*
7991 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7992 *
7993 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7994 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7995 * to 'clear'.
7996 */
7997 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7998 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7999 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8000 {
8001 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8002 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8003 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8004 }
8005 else
8006 {
8007 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8008 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8009 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8010 if (RT_FAILURE(rcStrict))
8011 return rcStrict;
8012 }
8013
8014 iemVmxVmSucceed(pVCpu);
8015 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8016 return VINF_SUCCESS;
8017}
8018
8019
8020/**
8021 * VMPTRST instruction execution worker.
8022 *
8023 * @returns Strict VBox status code.
8024 * @param pVCpu The cross context virtual CPU structure.
8025 * @param cbInstr The instruction length in bytes.
8026 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8027 * @param GCPtrVmcs The linear address of where to store the current VMCS
8028 * pointer.
8029 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8030 *
8031 * @remarks Common VMX instruction checks are already expected to by the caller,
8032 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8033 */
8034IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8035 PCVMXVEXITINFO pExitInfo)
8036{
8037 /* Nested-guest intercept. */
8038 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8039 {
8040 if (pExitInfo)
8041 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8042 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8043 }
8044
8045 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8046
8047 /* CPL. */
8048 if (pVCpu->iem.s.uCpl == 0)
8049 { /* likely */ }
8050 else
8051 {
8052 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8053 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8054 return iemRaiseGeneralProtectionFault0(pVCpu);
8055 }
8056
8057 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8058 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8059 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8060 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8061 {
8062 iemVmxVmSucceed(pVCpu);
8063 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8064 return rcStrict;
8065 }
8066
8067 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8068 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8069 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8070 return rcStrict;
8071}
8072
8073
8074/**
8075 * VMPTRLD instruction execution worker.
8076 *
8077 * @returns Strict VBox status code.
8078 * @param pVCpu The cross context virtual CPU structure.
8079 * @param cbInstr The instruction length in bytes.
8080 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8081 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8082 *
8083 * @remarks Common VMX instruction checks are already expected to by the caller,
8084 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8085 */
8086IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8087 PCVMXVEXITINFO pExitInfo)
8088{
8089 /* Nested-guest intercept. */
8090 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8091 {
8092 if (pExitInfo)
8093 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8094 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8095 }
8096
8097 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8098
8099 /* CPL. */
8100 if (pVCpu->iem.s.uCpl == 0)
8101 { /* likely */ }
8102 else
8103 {
8104 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8105 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8106 return iemRaiseGeneralProtectionFault0(pVCpu);
8107 }
8108
8109 /* Get the VMCS pointer from the location specified by the source memory operand. */
8110 RTGCPHYS GCPhysVmcs;
8111 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8112 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8113 { /* likely */ }
8114 else
8115 {
8116 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8117 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8118 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8119 return rcStrict;
8120 }
8121
8122 /* VMCS pointer alignment. */
8123 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8124 { /* likely */ }
8125 else
8126 {
8127 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8128 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8129 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8130 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8131 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8132 return VINF_SUCCESS;
8133 }
8134
8135 /* VMCS physical-address width limits. */
8136 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8137 { /* likely */ }
8138 else
8139 {
8140 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8141 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8142 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8143 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8144 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8145 return VINF_SUCCESS;
8146 }
8147
8148 /* VMCS is not the VMXON region. */
8149 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8150 { /* likely */ }
8151 else
8152 {
8153 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8154 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8155 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8156 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8157 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8158 return VINF_SUCCESS;
8159 }
8160
8161 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8162 restriction imposed by our implementation. */
8163 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8164 { /* likely */ }
8165 else
8166 {
8167 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8168 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8170 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8171 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8172 return VINF_SUCCESS;
8173 }
8174
8175 /* Read just the VMCS revision from the VMCS. */
8176 VMXVMCSREVID VmcsRevId;
8177 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8178 if (RT_SUCCESS(rc))
8179 { /* likely */ }
8180 else
8181 {
8182 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8183 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8184 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8185 return rc;
8186 }
8187
8188 /*
8189 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8190 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8191 */
8192 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8193 && ( !VmcsRevId.n.fIsShadowVmcs
8194 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8195 { /* likely */ }
8196 else
8197 {
8198 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8199 {
8200 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8201 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8202 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8203 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8204 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8205 return VINF_SUCCESS;
8206 }
8207
8208 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8209 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8210 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8211 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8212 return VINF_SUCCESS;
8213 }
8214
8215 /*
8216 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8217 * the cache of an existing, current VMCS back to guest memory before loading a new,
8218 * different current VMCS.
8219 */
8220 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8221 {
8222 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8223 {
8224 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8225 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8226 }
8227
8228 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8229 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8230 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8231 if (RT_SUCCESS(rc))
8232 {
8233 /* Notify HM that a new, current VMCS is loaded. */
8234 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8235 }
8236 else
8237 {
8238 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8239 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8240 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8241 return rc;
8242 }
8243 }
8244
8245 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8246 iemVmxVmSucceed(pVCpu);
8247 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8248 return VINF_SUCCESS;
8249}
8250
8251
8252/**
8253 * INVVPID instruction execution worker.
8254 *
8255 * @returns Strict VBox status code.
8256 * @param pVCpu The cross context virtual CPU structure.
8257 * @param cbInstr The instruction length in bytes.
8258 * @param iEffSeg The segment of the invvpid descriptor.
8259 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8260 * @param u64InvvpidType The invalidation type.
8261 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8262 * NULL.
8263 *
8264 * @remarks Common VMX instruction checks are already expected to by the caller,
8265 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8266 */
8267IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8268 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8269{
8270 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8271 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8272 return iemRaiseUndefinedOpcode(pVCpu);
8273
8274 /* Nested-guest intercept. */
8275 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8276 {
8277 if (pExitInfo)
8278 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8279 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8280 }
8281
8282 /* CPL. */
8283 if (pVCpu->iem.s.uCpl != 0)
8284 {
8285 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8286 return iemRaiseGeneralProtectionFault0(pVCpu);
8287 }
8288
8289 /*
8290 * Validate INVVPID invalidation type.
8291 *
8292 * The instruction specifies exactly ONE of the supported invalidation types.
8293 *
8294 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8295 * supported. In theory, it's possible for a CPU to not support flushing individual
8296 * addresses but all the other types or any other combination. We do not take any
8297 * shortcuts here by assuming the types we currently expose to the guest.
8298 */
8299 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8300 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8301 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8302 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8303 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8304 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8305 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8306 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8307 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8308 { /* likely */ }
8309 else
8310 {
8311 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8313 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8314 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8315 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8316 return VINF_SUCCESS;
8317 }
8318
8319 /*
8320 * Fetch the invvpid descriptor from guest memory.
8321 */
8322 RTUINT128U uDesc;
8323 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8324 if (rcStrict == VINF_SUCCESS)
8325 {
8326 /*
8327 * Validate the descriptor.
8328 */
8329 if (uDesc.s.Lo > 0xfff)
8330 {
8331 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8332 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8333 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8334 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8335 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8336 return VINF_SUCCESS;
8337 }
8338
8339 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8340 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8341 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8342 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8343 switch (u64InvvpidType)
8344 {
8345 case VMXTLBFLUSHVPID_INDIV_ADDR:
8346 {
8347 if (uVpid != 0)
8348 {
8349 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8350 {
8351 /* Invalidate mappings for the linear address tagged with VPID. */
8352 /** @todo PGM support for VPID? Currently just flush everything. */
8353 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8354 iemVmxVmSucceed(pVCpu);
8355 }
8356 else
8357 {
8358 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8359 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8360 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8361 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8362 }
8363 }
8364 else
8365 {
8366 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8368 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8369 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8370 }
8371 break;
8372 }
8373
8374 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8375 {
8376 if (uVpid != 0)
8377 {
8378 /* Invalidate all mappings with VPID. */
8379 /** @todo PGM support for VPID? Currently just flush everything. */
8380 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8381 iemVmxVmSucceed(pVCpu);
8382 }
8383 else
8384 {
8385 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8386 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8387 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8388 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8389 }
8390 break;
8391 }
8392
8393 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8394 {
8395 /* Invalidate all mappings with non-zero VPIDs. */
8396 /** @todo PGM support for VPID? Currently just flush everything. */
8397 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8398 iemVmxVmSucceed(pVCpu);
8399 break;
8400 }
8401
8402 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8403 {
8404 if (uVpid != 0)
8405 {
8406 /* Invalidate all mappings with VPID except global translations. */
8407 /** @todo PGM support for VPID? Currently just flush everything. */
8408 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8409 iemVmxVmSucceed(pVCpu);
8410 }
8411 else
8412 {
8413 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8416 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8417 }
8418 break;
8419 }
8420 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8421 }
8422 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8423 }
8424 return rcStrict;
8425}
8426
8427
8428/**
8429 * VMXON instruction execution worker.
8430 *
8431 * @returns Strict VBox status code.
8432 * @param pVCpu The cross context virtual CPU structure.
8433 * @param cbInstr The instruction length in bytes.
8434 * @param iEffSeg The effective segment register to use with @a
8435 * GCPtrVmxon.
8436 * @param GCPtrVmxon The linear address of the VMXON pointer.
8437 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8438 *
8439 * @remarks Common VMX instruction checks are already expected to by the caller,
8440 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8441 */
8442IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8443 PCVMXVEXITINFO pExitInfo)
8444{
8445 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8446 {
8447 /* CPL. */
8448 if (pVCpu->iem.s.uCpl == 0)
8449 { /* likely */ }
8450 else
8451 {
8452 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8454 return iemRaiseGeneralProtectionFault0(pVCpu);
8455 }
8456
8457 /* A20M (A20 Masked) mode. */
8458 if (PGMPhysIsA20Enabled(pVCpu))
8459 { /* likely */ }
8460 else
8461 {
8462 Log(("vmxon: A20M mode -> #GP(0)\n"));
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8464 return iemRaiseGeneralProtectionFault0(pVCpu);
8465 }
8466
8467 /* CR0. */
8468 {
8469 /* CR0 MB1 bits. */
8470 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8471 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8472 { /* likely */ }
8473 else
8474 {
8475 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8476 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8477 return iemRaiseGeneralProtectionFault0(pVCpu);
8478 }
8479
8480 /* CR0 MBZ bits. */
8481 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8482 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8483 { /* likely */ }
8484 else
8485 {
8486 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8487 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8488 return iemRaiseGeneralProtectionFault0(pVCpu);
8489 }
8490 }
8491
8492 /* CR4. */
8493 {
8494 /* CR4 MB1 bits. */
8495 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8496 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8497 { /* likely */ }
8498 else
8499 {
8500 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8501 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8502 return iemRaiseGeneralProtectionFault0(pVCpu);
8503 }
8504
8505 /* CR4 MBZ bits. */
8506 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8507 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8508 { /* likely */ }
8509 else
8510 {
8511 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8512 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8513 return iemRaiseGeneralProtectionFault0(pVCpu);
8514 }
8515 }
8516
8517 /* Feature control MSR's LOCK and VMXON bits. */
8518 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8519 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8520 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8521 { /* likely */ }
8522 else
8523 {
8524 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8525 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8526 return iemRaiseGeneralProtectionFault0(pVCpu);
8527 }
8528
8529 /* Get the VMXON pointer from the location specified by the source memory operand. */
8530 RTGCPHYS GCPhysVmxon;
8531 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8532 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8533 { /* likely */ }
8534 else
8535 {
8536 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8537 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8538 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8539 return rcStrict;
8540 }
8541
8542 /* VMXON region pointer alignment. */
8543 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8544 { /* likely */ }
8545 else
8546 {
8547 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8548 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8549 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8550 iemVmxVmFailInvalid(pVCpu);
8551 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8552 return VINF_SUCCESS;
8553 }
8554
8555 /* VMXON physical-address width limits. */
8556 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8557 { /* likely */ }
8558 else
8559 {
8560 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8561 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8562 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8563 iemVmxVmFailInvalid(pVCpu);
8564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8565 return VINF_SUCCESS;
8566 }
8567
8568 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8569 restriction imposed by our implementation. */
8570 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8571 { /* likely */ }
8572 else
8573 {
8574 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8576 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8577 iemVmxVmFailInvalid(pVCpu);
8578 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8579 return VINF_SUCCESS;
8580 }
8581
8582 /* Read the VMCS revision ID from the VMXON region. */
8583 VMXVMCSREVID VmcsRevId;
8584 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8585 if (RT_SUCCESS(rc))
8586 { /* likely */ }
8587 else
8588 {
8589 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8591 return rc;
8592 }
8593
8594 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8595 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8596 { /* likely */ }
8597 else
8598 {
8599 /* Revision ID mismatch. */
8600 if (!VmcsRevId.n.fIsShadowVmcs)
8601 {
8602 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8603 VmcsRevId.n.u31RevisionId));
8604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8605 iemVmxVmFailInvalid(pVCpu);
8606 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8607 return VINF_SUCCESS;
8608 }
8609
8610 /* Shadow VMCS disallowed. */
8611 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8613 iemVmxVmFailInvalid(pVCpu);
8614 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8615 return VINF_SUCCESS;
8616 }
8617
8618 /*
8619 * Record that we're in VMX operation, block INIT, block and disable A20M.
8620 */
8621 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8622 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8623 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8624
8625 /* Clear address-range monitoring. */
8626 EMMonitorWaitClear(pVCpu);
8627 /** @todo NSTVMX: Intel PT. */
8628
8629 iemVmxVmSucceed(pVCpu);
8630 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8631 return VINF_SUCCESS;
8632 }
8633 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8634 {
8635 /* Nested-guest intercept. */
8636 if (pExitInfo)
8637 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8638 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8639 }
8640
8641 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8642
8643 /* CPL. */
8644 if (pVCpu->iem.s.uCpl > 0)
8645 {
8646 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8647 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8648 return iemRaiseGeneralProtectionFault0(pVCpu);
8649 }
8650
8651 /* VMXON when already in VMX root mode. */
8652 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8653 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8654 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8655 return VINF_SUCCESS;
8656}
8657
8658
8659/**
8660 * Implements 'VMXOFF'.
8661 *
8662 * @remarks Common VMX instruction checks are already expected to by the caller,
8663 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8664 */
8665IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8666{
8667 /* Nested-guest intercept. */
8668 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8669 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8670
8671 /* CPL. */
8672 if (pVCpu->iem.s.uCpl == 0)
8673 { /* likely */ }
8674 else
8675 {
8676 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8677 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8678 return iemRaiseGeneralProtectionFault0(pVCpu);
8679 }
8680
8681 /* Dual monitor treatment of SMIs and SMM. */
8682 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8683 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8684 { /* likely */ }
8685 else
8686 {
8687 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8688 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8689 return VINF_SUCCESS;
8690 }
8691
8692 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8694 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8695
8696 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8697 { /** @todo NSTVMX: Unblock SMI. */ }
8698
8699 EMMonitorWaitClear(pVCpu);
8700 /** @todo NSTVMX: Unblock and enable A20M. */
8701
8702 iemVmxVmSucceed(pVCpu);
8703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8704 return VINF_SUCCESS;
8705}
8706
8707
8708/**
8709 * Implements 'VMXON'.
8710 */
8711IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8712{
8713 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8714}
8715
8716
8717/**
8718 * Implements 'VMLAUNCH'.
8719 */
8720IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8721{
8722 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8723}
8724
8725
8726/**
8727 * Implements 'VMRESUME'.
8728 */
8729IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8730{
8731 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8732}
8733
8734
8735/**
8736 * Implements 'VMPTRLD'.
8737 */
8738IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8739{
8740 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8741}
8742
8743
8744/**
8745 * Implements 'VMPTRST'.
8746 */
8747IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8748{
8749 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8750}
8751
8752
8753/**
8754 * Implements 'VMCLEAR'.
8755 */
8756IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8757{
8758 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8759}
8760
8761
8762/**
8763 * Implements 'VMWRITE' register.
8764 */
8765IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8766{
8767 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8768}
8769
8770
8771/**
8772 * Implements 'VMWRITE' memory.
8773 */
8774IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8775{
8776 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8777}
8778
8779
8780/**
8781 * Implements 'VMREAD' register (64-bit).
8782 */
8783IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8784{
8785 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8786}
8787
8788
8789/**
8790 * Implements 'VMREAD' register (32-bit).
8791 */
8792IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8793{
8794 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8795}
8796
8797
8798/**
8799 * Implements 'VMREAD' memory, 64-bit register.
8800 */
8801IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8802{
8803 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8804}
8805
8806
8807/**
8808 * Implements 'VMREAD' memory, 32-bit register.
8809 */
8810IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8811{
8812 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8813}
8814
8815
8816/**
8817 * Implements 'INVVPID'.
8818 */
8819IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8820{
8821 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8822}
8823
8824
8825/**
8826 * Implements VMX's implementation of PAUSE.
8827 */
8828IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8829{
8830 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8831 {
8832 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8833 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8834 return rcStrict;
8835 }
8836
8837 /*
8838 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8839 * a VM-exit, the instruction operates normally.
8840 */
8841 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8842 return VINF_SUCCESS;
8843}
8844
8845#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8846
8847
8848/**
8849 * Implements 'VMCALL'.
8850 */
8851IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8852{
8853#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8854 /* Nested-guest intercept. */
8855 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8856 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8857#endif
8858
8859 /* Join forces with vmmcall. */
8860 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8861}
8862
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