VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 82613

Last change on this file since 82613 was 82575, checked in by vboxsync, 5 years ago

VMM/IEM: Nested VMX: bugref:9180 VMX_EXIT_APIC_ACCESS emulation is done, remove from todo list.
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File size: 353.8 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 82575 2019-12-13 05:48:21Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
203 },
204 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
205 {
206 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
207 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 24-25 */ UINT16_MAX, UINT16_MAX
210 },
211 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
212 {
213 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
214 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
215 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
216 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
217 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
218 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
219 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
220 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
221 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
222 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
223 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
224 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
225 },
226 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
227 {
228 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
229 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
230 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
231 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
232 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
233 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
234 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
235 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
236 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
238 },
239 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
240 {
241 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
242 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
243 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
244 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
245 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
246 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
247 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
248 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
249 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
250 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
251 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
252 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
253 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
254 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
255 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
256 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
257 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
258 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
259 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
260 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
261 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
262 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
263 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
264 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsBitmap),
265 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SpptPtr),
266 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
267 },
268 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
269 {
270 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
271 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
272 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
273 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
274 /* 25 */ UINT16_MAX
275 },
276 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
277 {
278 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
279 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
280 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
281 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
282 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
283 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
284 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
285 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
286 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
287 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
288 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
289 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
290 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
291 },
292 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
293 {
294 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
295 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
296 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
297 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
298 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
299 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
300 },
301 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
304 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
305 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
306 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
307 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
308 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
309 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
310 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
311 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
312 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
313 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
314 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
315 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
316 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
317 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
318 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
319 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
320 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
321 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
322 },
323 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
324 {
325 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
326 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
327 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
328 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
329 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
330 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
331 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
332 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
333 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 24-25 */ UINT16_MAX, UINT16_MAX
336 },
337 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
338 {
339 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
340 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
341 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
342 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
343 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
344 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
345 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
346 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
347 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
348 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
349 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
350 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
351 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
352 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
353 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
354 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
355 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
356 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
357 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
358 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
359 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
360 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
361 /* 22 */ UINT16_MAX,
362 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
363 /* 24-25 */ UINT16_MAX, UINT16_MAX
364 },
365 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
366 {
367 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
368 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
371 /* 25 */ UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
376 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
377 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
378 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
379 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
380 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
381 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
382 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
383 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 24-25 */ UINT16_MAX, UINT16_MAX
386 },
387 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
388 {
389 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
390 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
391 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
392 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
393 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
394 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
395 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
396 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
398 },
399 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
400 {
401 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
402 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
403 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
404 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
405 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
406 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
407 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
408 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
409 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
410 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
411 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
412 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
413 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
414 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
415 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
416 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
417 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
418 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
419 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
420 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
421 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
437 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
439 }
440};
441
442
443/**
444 * Gets a host selector from the VMCS.
445 *
446 * @param pVmcs Pointer to the virtual VMCS.
447 * @param iSelReg The index of the segment register (X86_SREG_XXX).
448 */
449DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
450{
451 Assert(iSegReg < X86_SREG_COUNT);
452 RTSEL HostSel;
453 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
454 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
455 uint8_t const uWidthType = (uWidth << 2) | uType;
456 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
457 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
458 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
459 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
460 uint8_t const *pbField = pbVmcs + offField;
461 HostSel = *(uint16_t *)pbField;
462 return HostSel;
463}
464
465
466/**
467 * Sets a guest segment register in the VMCS.
468 *
469 * @param pVmcs Pointer to the virtual VMCS.
470 * @param iSegReg The index of the segment register (X86_SREG_XXX).
471 * @param pSelReg Pointer to the segment register.
472 */
473IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
474{
475 Assert(pSelReg);
476 Assert(iSegReg < X86_SREG_COUNT);
477
478 /* Selector. */
479 {
480 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
481 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
482 uint8_t const uWidthType = (uWidth << 2) | uType;
483 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
484 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
485 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
486 uint8_t *pbVmcs = (uint8_t *)pVmcs;
487 uint8_t *pbField = pbVmcs + offField;
488 *(uint16_t *)pbField = pSelReg->Sel;
489 }
490
491 /* Limit. */
492 {
493 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
494 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
495 uint8_t const uWidthType = (uWidth << 2) | uType;
496 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
497 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
498 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
499 uint8_t *pbVmcs = (uint8_t *)pVmcs;
500 uint8_t *pbField = pbVmcs + offField;
501 *(uint32_t *)pbField = pSelReg->u32Limit;
502 }
503
504 /* Base. */
505 {
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 *(uint64_t *)pbField = pSelReg->u64Base;
515 }
516
517 /* Attributes. */
518 {
519 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
520 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
521 | X86DESCATTR_UNUSABLE;
522 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
523 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
524 uint8_t const uWidthType = (uWidth << 2) | uType;
525 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
526 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
527 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
528 uint8_t *pbVmcs = (uint8_t *)pVmcs;
529 uint8_t *pbField = pbVmcs + offField;
530 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
531 }
532}
533
534
535/**
536 * Gets a guest segment register from the VMCS.
537 *
538 * @returns VBox status code.
539 * @param pVmcs Pointer to the virtual VMCS.
540 * @param iSegReg The index of the segment register (X86_SREG_XXX).
541 * @param pSelReg Where to store the segment register (only updated when
542 * VINF_SUCCESS is returned).
543 *
544 * @remarks Warning! This does not validate the contents of the retrieved segment
545 * register.
546 */
547IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
548{
549 Assert(pSelReg);
550 Assert(iSegReg < X86_SREG_COUNT);
551
552 /* Selector. */
553 uint16_t u16Sel;
554 {
555 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
556 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557 uint8_t const uWidthType = (uWidth << 2) | uType;
558 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
559 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
560 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
562 uint8_t const *pbField = pbVmcs + offField;
563 u16Sel = *(uint16_t *)pbField;
564 }
565
566 /* Limit. */
567 uint32_t u32Limit;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u32Limit = *(uint32_t *)pbField;
578 }
579
580 /* Base. */
581 uint64_t u64Base;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u64Base = *(uint64_t *)pbField;
592 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
593 }
594
595 /* Attributes. */
596 uint32_t u32Attr;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u32Attr = *(uint32_t *)pbField;
607 }
608
609 pSelReg->Sel = u16Sel;
610 pSelReg->ValidSel = u16Sel;
611 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
612 pSelReg->u32Limit = u32Limit;
613 pSelReg->u64Base = u64Base;
614 pSelReg->Attr.u = u32Attr;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Converts an IEM exception event type to a VMX event type.
621 *
622 * @returns The VMX event type.
623 * @param uVector The interrupt / exception vector.
624 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
625 */
626DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
627{
628 /* Paranoia (callers may use these interchangeably). */
629 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
630 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
631 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
632 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
633 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
634 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
635 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
636 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
637 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
638 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
639 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
640 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
641
642 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
643 {
644 if (uVector == X86_XCPT_NMI)
645 return VMX_EXIT_INT_INFO_TYPE_NMI;
646 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
647 }
648
649 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
650 {
651 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
652 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
653 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
654 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
655 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
656 }
657
658 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
659 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
660}
661
662
663/**
664 * Sets the Exit qualification VMCS field.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param u64ExitQual The Exit qualification.
668 */
669DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
670{
671 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
672 pVmcs->u64RoExitQual.u = u64ExitQual;
673}
674
675
676/**
677 * Sets the VM-exit interruption information field.
678 *
679 * @param pVCpu The cross context virtual CPU structure.
680 * @param uExitIntInfo The VM-exit interruption information.
681 */
682DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
683{
684 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
685 pVmcs->u32RoExitIntInfo = uExitIntInfo;
686}
687
688
689/**
690 * Sets the VM-exit interruption error code.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uErrCode The error code.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
696{
697 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
698 pVmcs->u32RoExitIntErrCode = uErrCode;
699}
700
701
702/**
703 * Sets the IDT-vectoring information field.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param uIdtVectorInfo The IDT-vectoring information.
707 */
708DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
709{
710 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
711 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
712}
713
714
715/**
716 * Sets the IDT-vectoring error code field.
717 *
718 * @param pVCpu The cross context virtual CPU structure.
719 * @param uErrCode The error code.
720 */
721DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722{
723 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
724 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
725}
726
727
728/**
729 * Sets the VM-exit guest-linear address VMCS field.
730 *
731 * @param pVCpu The cross context virtual CPU structure.
732 * @param uGuestLinearAddr The VM-exit guest-linear address.
733 */
734DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
735{
736 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
737 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
738}
739
740
741/**
742 * Sets the VM-exit guest-physical address VMCS field.
743 *
744 * @param pVCpu The cross context virtual CPU structure.
745 * @param uGuestPhysAddr The VM-exit guest-physical address.
746 */
747DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
748{
749 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
750 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
751}
752
753
754/**
755 * Sets the VM-exit instruction length VMCS field.
756 *
757 * @param pVCpu The cross context virtual CPU structure.
758 * @param cbInstr The VM-exit instruction length in bytes.
759 *
760 * @remarks Callers may clear this field to 0. Hence, this function does not check
761 * the validity of the instruction length.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
764{
765 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
766 pVmcs->u32RoExitInstrLen = cbInstr;
767}
768
769
770/**
771 * Sets the VM-exit instruction info. VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uExitInstrInfo The VM-exit instruction information.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
777{
778 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
779 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
780}
781
782
783/**
784 * Sets the guest pending-debug exceptions field.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
788 */
789DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
790{
791 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
792 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
793 pVmcs->u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
794}
795
796
797/**
798 * Implements VMSucceed for VMX instruction success.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
803{
804 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
805}
806
807
808/**
809 * Implements VMFailInvalid for VMX instruction failure.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
814{
815 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
816}
817
818
819/**
820 * Implements VMFail for VMX instruction failure.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param enmInsErr The VM instruction error.
824 */
825DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
826{
827 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
828}
829
830
831/**
832 * Checks if the given auto-load/store MSR area count is valid for the
833 * implementation.
834 *
835 * @returns @c true if it's within the valid limit, @c false otherwise.
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param uMsrCount The MSR area count to check.
838 */
839DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
840{
841 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
842 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
843 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
844 if (uMsrCount <= cMaxSupportedMsrs)
845 return true;
846 return false;
847}
848
849
850/**
851 * Flushes the current VMCS contents back to guest memory.
852 *
853 * @returns VBox status code.
854 * @param pVCpu The cross context virtual CPU structure.
855 */
856DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
857{
858 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
859 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
860 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
861 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
862 return rc;
863}
864
865
866/**
867 * Populates the current VMCS contents from guest memory.
868 *
869 * @returns VBox status code.
870 * @param pVCpu The cross context virtual CPU structure.
871 */
872DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
873{
874 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
875 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
877 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
878 return rc;
879}
880
881
882/**
883 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
884 *
885 * @param pVCpu The cross context virtual CPU structure.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
888{
889 iemVmxVmSucceed(pVCpu);
890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
891}
892
893
894/**
895 * Gets the instruction diagnostic for segment base checks during VM-entry of a
896 * nested-guest.
897 *
898 * @param iSegReg The segment index (X86_SREG_XXX).
899 */
900IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
901{
902 switch (iSegReg)
903 {
904 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
905 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
906 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
907 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
908 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
909 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
910 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
911 }
912}
913
914
915/**
916 * Gets the instruction diagnostic for segment base checks during VM-entry of a
917 * nested-guest that is in Virtual-8086 mode.
918 *
919 * @param iSegReg The segment index (X86_SREG_XXX).
920 */
921IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
922{
923 switch (iSegReg)
924 {
925 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
926 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
927 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
928 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
929 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
930 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
931 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
932 }
933}
934
935
936/**
937 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
938 * nested-guest that is in Virtual-8086 mode.
939 *
940 * @param iSegReg The segment index (X86_SREG_XXX).
941 */
942IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
943{
944 switch (iSegReg)
945 {
946 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
947 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
948 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
949 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
950 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
951 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
952 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
953 }
954}
955
956
957/**
958 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
959 * nested-guest that is in Virtual-8086 mode.
960 *
961 * @param iSegReg The segment index (X86_SREG_XXX).
962 */
963IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
964{
965 switch (iSegReg)
966 {
967 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
968 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
969 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
970 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
971 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
972 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
973 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
974 }
975}
976
977
978/**
979 * Gets the instruction diagnostic for segment attributes reserved bits failure
980 * during VM-entry of a nested-guest.
981 *
982 * @param iSegReg The segment index (X86_SREG_XXX).
983 */
984IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
985{
986 switch (iSegReg)
987 {
988 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
989 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
990 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
991 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
992 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
993 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
994 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
995 }
996}
997
998
999/**
1000 * Gets the instruction diagnostic for segment attributes descriptor-type
1001 * (code/segment or system) failure during VM-entry of a nested-guest.
1002 *
1003 * @param iSegReg The segment index (X86_SREG_XXX).
1004 */
1005IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1006{
1007 switch (iSegReg)
1008 {
1009 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1010 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1011 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1012 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1013 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1014 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1015 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1016 }
1017}
1018
1019
1020/**
1021 * Gets the instruction diagnostic for segment attributes descriptor-type
1022 * (code/segment or system) failure during VM-entry of a nested-guest.
1023 *
1024 * @param iSegReg The segment index (X86_SREG_XXX).
1025 */
1026IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1027{
1028 switch (iSegReg)
1029 {
1030 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1031 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1032 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1033 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1034 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1035 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1036 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1037 }
1038}
1039
1040
1041/**
1042 * Gets the instruction diagnostic for segment attribute granularity failure during
1043 * VM-entry of a nested-guest.
1044 *
1045 * @param iSegReg The segment index (X86_SREG_XXX).
1046 */
1047IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1048{
1049 switch (iSegReg)
1050 {
1051 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1052 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1053 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1054 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1055 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1056 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1057 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1058 }
1059}
1060
1061/**
1062 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1063 * VM-entry of a nested-guest.
1064 *
1065 * @param iSegReg The segment index (X86_SREG_XXX).
1066 */
1067IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1068{
1069 switch (iSegReg)
1070 {
1071 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1072 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1073 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1074 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1075 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1076 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1077 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1078 }
1079}
1080
1081
1082/**
1083 * Gets the instruction diagnostic for segment attribute type accessed failure
1084 * during VM-entry of a nested-guest.
1085 *
1086 * @param iSegReg The segment index (X86_SREG_XXX).
1087 */
1088IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1089{
1090 switch (iSegReg)
1091 {
1092 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1093 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1094 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1095 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1096 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1097 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1098 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1099 }
1100}
1101
1102
1103/**
1104 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1105 * failure during VM-entry of a nested-guest.
1106 *
1107 * @param iSegReg The PDPTE entry index.
1108 */
1109IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1110{
1111 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1112 switch (iPdpte)
1113 {
1114 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1115 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1116 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1117 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1118 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1119 }
1120}
1121
1122
1123/**
1124 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1125 * failure during VM-exit of a nested-guest.
1126 *
1127 * @param iSegReg The PDPTE entry index.
1128 */
1129IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1130{
1131 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1132 switch (iPdpte)
1133 {
1134 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1135 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1136 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1137 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1138 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1139 }
1140}
1141
1142
1143/**
1144 * Saves the guest control registers, debug registers and some MSRs are part of
1145 * VM-exit.
1146 *
1147 * @param pVCpu The cross context virtual CPU structure.
1148 */
1149IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1150{
1151 /*
1152 * Saves the guest control registers, debug registers and some MSRs.
1153 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1154 */
1155 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1156
1157 /* Save control registers. */
1158 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1159 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1160 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1161
1162 /* Save SYSENTER CS, ESP, EIP. */
1163 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1165 {
1166 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1167 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1168 }
1169 else
1170 {
1171 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1172 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1173 }
1174
1175 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1176 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1177 {
1178 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1179 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1180 }
1181
1182 /* Save PAT MSR. */
1183 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1184 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1185
1186 /* Save EFER MSR. */
1187 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1188 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1189
1190 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1191 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1192
1193 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1194}
1195
1196
1197/**
1198 * Saves the guest force-flags in preparation of entering the nested-guest.
1199 *
1200 * @param pVCpu The cross context virtual CPU structure.
1201 */
1202IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1203{
1204 /* We shouldn't be called multiple times during VM-entry. */
1205 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1206
1207 /* MTF should not be set outside VMX non-root mode. */
1208 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1209
1210 /*
1211 * Preserve the required force-flags.
1212 *
1213 * We cache and clear force-flags that would affect the execution of the
1214 * nested-guest. Cached flags are then restored while returning to the guest
1215 * if necessary.
1216 *
1217 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1218 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1219 * instruction. Interrupt inhibition for any nested-guest instruction
1220 * is supplied by the guest-interruptibility state VMCS field and will
1221 * be set up as part of loading the guest state.
1222 *
1223 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1224 * successful VM-entry (due to invalid guest-state) need to continue
1225 * blocking NMIs if it was in effect before VM-entry.
1226 *
1227 * - MTF need not be preserved as it's used only in VMX non-root mode and
1228 * is supplied through the VM-execution controls.
1229 *
1230 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1231 * we will be able to generate interrupts that may cause VM-exits for
1232 * the nested-guest.
1233 */
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1235}
1236
1237
1238/**
1239 * Restores the guest force-flags in preparation of exiting the nested-guest.
1240 *
1241 * @param pVCpu The cross context virtual CPU structure.
1242 */
1243IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1244{
1245 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1246 {
1247 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1248 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1249 }
1250}
1251
1252
1253/**
1254 * Perform a VMX transition updated PGM, IEM and CPUM.
1255 *
1256 * @param pVCpu The cross context virtual CPU structure.
1257 */
1258IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1259{
1260 /*
1261 * Inform PGM about paging mode changes.
1262 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1263 * see comment in iemMemPageTranslateAndCheckAccess().
1264 */
1265 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1266# ifdef IN_RING3
1267 Assert(rc != VINF_PGM_CHANGE_MODE);
1268# endif
1269 AssertRCReturn(rc, rc);
1270
1271 /* Inform CPUM (recompiler), can later be removed. */
1272 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1273
1274 /*
1275 * Flush the TLB with new CR3. This is required in case the PGM mode change
1276 * above doesn't actually change anything.
1277 */
1278 if (rc == VINF_SUCCESS)
1279 {
1280 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1281 AssertRCReturn(rc, rc);
1282 }
1283
1284 /* Re-initialize IEM cache/state after the drastic mode switch. */
1285 iemReInitExec(pVCpu);
1286 return rc;
1287}
1288
1289
1290/**
1291 * Calculates the current VMX-preemption timer value.
1292 *
1293 * @returns The current VMX-preemption timer value.
1294 * @param pVCpu The cross context virtual CPU structure.
1295 */
1296IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1297{
1298 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1299 Assert(pVmcs);
1300
1301 /*
1302 * Assume the following:
1303 * PreemptTimerShift = 5
1304 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1305 * EntryTick = 50000 (TSC at time of VM-entry)
1306 *
1307 * CurTick Delta PreemptTimerVal
1308 * ----------------------------------
1309 * 60000 10000 2
1310 * 80000 30000 1
1311 * 90000 40000 0 -> VM-exit.
1312 *
1313 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1314 * The saved VMX-preemption timer value is calculated as follows:
1315 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1316 * E.g.:
1317 * Delta = 10000
1318 * Tmp = 10000 / (2 * 10000) = 0.5
1319 * NewPt = 2 - 0.5 = 2
1320 * Delta = 30000
1321 * Tmp = 30000 / (2 * 10000) = 1.5
1322 * NewPt = 2 - 1.5 = 1
1323 * Delta = 40000
1324 * Tmp = 40000 / 20000 = 2
1325 * NewPt = 2 - 2 = 0
1326 */
1327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1328 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1329 if (uVmcsPreemptVal > 0)
1330 {
1331 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1332 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1333 uint64_t const uDelta = uCurTick - uEntryTick;
1334 uint32_t const uPreemptTimer = uVmcsPreemptVal
1335 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1336 return uPreemptTimer;
1337 }
1338 return 0;
1339}
1340
1341
1342/**
1343 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1344 *
1345 * @param pVCpu The cross context virtual CPU structure.
1346 */
1347IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1348{
1349 /*
1350 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1351 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1352 */
1353 /* CS, SS, ES, DS, FS, GS. */
1354 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1355 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1356 {
1357 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1358 if (!pSelReg->Attr.n.u1Unusable)
1359 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1360 else
1361 {
1362 /*
1363 * For unusable segments the attributes are undefined except for CS and SS.
1364 * For the rest we don't bother preserving anything but the unusable bit.
1365 */
1366 switch (iSegReg)
1367 {
1368 case X86_SREG_CS:
1369 pVmcs->GuestCs = pSelReg->Sel;
1370 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1371 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1372 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1373 | X86DESCATTR_UNUSABLE);
1374 break;
1375
1376 case X86_SREG_SS:
1377 pVmcs->GuestSs = pSelReg->Sel;
1378 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1379 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1380 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1381 break;
1382
1383 case X86_SREG_DS:
1384 pVmcs->GuestDs = pSelReg->Sel;
1385 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1386 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1387 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1388 break;
1389
1390 case X86_SREG_ES:
1391 pVmcs->GuestEs = pSelReg->Sel;
1392 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1393 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1394 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1395 break;
1396
1397 case X86_SREG_FS:
1398 pVmcs->GuestFs = pSelReg->Sel;
1399 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1400 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1401 break;
1402
1403 case X86_SREG_GS:
1404 pVmcs->GuestGs = pSelReg->Sel;
1405 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1406 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1407 break;
1408 }
1409 }
1410 }
1411
1412 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1413 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1414 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1415 | X86DESCATTR_UNUSABLE;
1416 /* LDTR. */
1417 {
1418 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1419 pVmcs->GuestLdtr = pSelReg->Sel;
1420 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1421 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1422 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1423 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1424 }
1425
1426 /* TR. */
1427 {
1428 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1429 pVmcs->GuestTr = pSelReg->Sel;
1430 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1431 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1432 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1433 }
1434
1435 /* GDTR. */
1436 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1437 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1438
1439 /* IDTR. */
1440 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1441 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1442}
1443
1444
1445/**
1446 * Saves guest non-register state as part of VM-exit.
1447 *
1448 * @param pVCpu The cross context virtual CPU structure.
1449 * @param uExitReason The VM-exit reason.
1450 */
1451IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1452{
1453 /*
1454 * Save guest non-register state.
1455 * See Intel spec. 27.3.4 "Saving Non-Register State".
1456 */
1457 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1458
1459 /*
1460 * Activity state.
1461 * Most VM-exits will occur in the active state. However, if the first instruction
1462 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1463 * the VM-exit will be from the HLT activity state.
1464 *
1465 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1466 */
1467 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1468 * not? */
1469 EMSTATE const enmActivityState = EMGetState(pVCpu);
1470 switch (enmActivityState)
1471 {
1472 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1473 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1474 }
1475
1476 /*
1477 * Interruptibility-state.
1478 */
1479 /* NMI. */
1480 pVmcs->u32GuestIntrState = 0;
1481 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1482 {
1483 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1484 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1485 }
1486 else
1487 {
1488 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1489 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1490 }
1491
1492 /* Blocking-by-STI. */
1493 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1494 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1495 {
1496 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1497 * currently. */
1498 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1499 }
1500 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1501
1502 /*
1503 * Pending debug exceptions.
1504 *
1505 * For VM-exits where it is not applicable, we can safely zero out the field.
1506 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1507 */
1508 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1509 && uExitReason != VMX_EXIT_SMI
1510 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1511 && !VMXIsVmexitTrapLike(uExitReason))
1512 {
1513 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1514 * block-by-MovSS is in effect. */
1515 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1516 }
1517
1518 /*
1519 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1520 *
1521 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1522 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1523 */
1524 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1525 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1526 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1527
1528 /* PDPTEs. */
1529 /* We don't support EPT yet. */
1530 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1531 pVmcs->u64GuestPdpte0.u = 0;
1532 pVmcs->u64GuestPdpte1.u = 0;
1533 pVmcs->u64GuestPdpte2.u = 0;
1534 pVmcs->u64GuestPdpte3.u = 0;
1535}
1536
1537
1538/**
1539 * Saves the guest-state as part of VM-exit.
1540 *
1541 * @returns VBox status code.
1542 * @param pVCpu The cross context virtual CPU structure.
1543 * @param uExitReason The VM-exit reason.
1544 */
1545IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1546{
1547 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1548 Assert(pVmcs);
1549
1550 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1551 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1552
1553 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1554 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1555 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1556
1557 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1558}
1559
1560
1561/**
1562 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1563 *
1564 * @returns VBox status code.
1565 * @param pVCpu The cross context virtual CPU structure.
1566 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1567 */
1568IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1569{
1570 /*
1571 * Save guest MSRs.
1572 * See Intel spec. 27.4 "Saving MSRs".
1573 */
1574 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1575 const char *const pszFailure = "VMX-abort";
1576
1577 /*
1578 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1579 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1580 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1581 */
1582 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1583 if (!cMsrs)
1584 return VINF_SUCCESS;
1585
1586 /*
1587 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1588 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1589 * implementation causes a VMX-abort followed by a triple-fault.
1590 */
1591 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1592 if (fIsMsrCountValid)
1593 { /* likely */ }
1594 else
1595 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1596
1597 /*
1598 * Optimization if the nested hypervisor is using the same guest-physical page for both
1599 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1600 */
1601 PVMXAUTOMSR pMsrArea;
1602 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1603 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1604 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1605 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1606 else
1607 {
1608 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1609 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1610 if (RT_SUCCESS(rc))
1611 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1612 else
1613 {
1614 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1615 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1616 }
1617 }
1618
1619 /*
1620 * Update VM-exit MSR store area.
1621 */
1622 PVMXAUTOMSR pMsr = pMsrArea;
1623 Assert(pMsr);
1624 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1625 {
1626 if ( !pMsr->u32Reserved
1627 && pMsr->u32Msr != MSR_IA32_SMBASE
1628 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1629 {
1630 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1631 if (rcStrict == VINF_SUCCESS)
1632 continue;
1633
1634 /*
1635 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1636 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1637 * recording the MSR index in the auxiliary info. field and indicated further by our
1638 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1639 * if possible, or come up with a better, generic solution.
1640 */
1641 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1642 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1643 ? kVmxVDiag_Vmexit_MsrStoreRing3
1644 : kVmxVDiag_Vmexit_MsrStore;
1645 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1646 }
1647 else
1648 {
1649 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1651 }
1652 }
1653
1654 /*
1655 * Commit the VM-exit MSR store are to guest memory.
1656 */
1657 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1658 if (RT_SUCCESS(rc))
1659 return VINF_SUCCESS;
1660
1661 NOREF(uExitReason);
1662 NOREF(pszFailure);
1663
1664 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1665 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1666}
1667
1668
1669/**
1670 * Performs a VMX abort (due to an fatal error during VM-exit).
1671 *
1672 * @returns Strict VBox status code.
1673 * @param pVCpu The cross context virtual CPU structure.
1674 * @param enmAbort The VMX abort reason.
1675 */
1676IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1677{
1678 /*
1679 * Perform the VMX abort.
1680 * See Intel spec. 27.7 "VMX Aborts".
1681 */
1682 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1683
1684 /* We don't support SMX yet. */
1685 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1686 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1687 {
1688 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1689 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1690 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1691 }
1692
1693 return VINF_EM_TRIPLE_FAULT;
1694}
1695
1696
1697/**
1698 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1699 *
1700 * @param pVCpu The cross context virtual CPU structure.
1701 */
1702IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1703{
1704 /*
1705 * Load host control registers, debug registers and MSRs.
1706 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1707 */
1708 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1709 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1710
1711 /* CR0. */
1712 {
1713 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1714 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1715 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1716 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1717 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1718 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1719 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1720
1721 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1722 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1723 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1724 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1725 }
1726
1727 /* CR4. */
1728 {
1729 /* CR4 fixed bits are not modified. */
1730 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1731 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1732 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1733 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1734 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1735 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1736 if (fHostInLongMode)
1737 uValidHostCr4 |= X86_CR4_PAE;
1738 else
1739 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1740
1741 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1742 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1743 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1744 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1745 }
1746
1747 /* CR3 (host value validated while checking host-state during VM-entry). */
1748 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1749
1750 /* DR7. */
1751 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1752
1753 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1754
1755 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1756 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1757 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1758 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1759
1760 /* FS, GS bases are loaded later while we load host segment registers. */
1761
1762 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1763 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1764 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1765 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1766 {
1767 if (fHostInLongMode)
1768 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1769 else
1770 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1771 }
1772
1773 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1774
1775 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1776 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1777 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1778
1779 /* We don't support IA32_BNDCFGS MSR yet. */
1780}
1781
1782
1783/**
1784 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1785 *
1786 * @param pVCpu The cross context virtual CPU structure.
1787 */
1788IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1789{
1790 /*
1791 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1792 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1793 *
1794 * Warning! Be careful to not touch fields that are reserved by VT-x,
1795 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1796 */
1797 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1798 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1799
1800 /* CS, SS, ES, DS, FS, GS. */
1801 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1802 {
1803 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1804 bool const fUnusable = RT_BOOL(HostSel == 0);
1805 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1806
1807 /* Selector. */
1808 pSelReg->Sel = HostSel;
1809 pSelReg->ValidSel = HostSel;
1810 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1811
1812 /* Limit. */
1813 pSelReg->u32Limit = 0xffffffff;
1814
1815 /* Base. */
1816 pSelReg->u64Base = 0;
1817
1818 /* Attributes. */
1819 if (iSegReg == X86_SREG_CS)
1820 {
1821 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1822 pSelReg->Attr.n.u1DescType = 1;
1823 pSelReg->Attr.n.u2Dpl = 0;
1824 pSelReg->Attr.n.u1Present = 1;
1825 pSelReg->Attr.n.u1Long = fHostInLongMode;
1826 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1827 pSelReg->Attr.n.u1Granularity = 1;
1828 Assert(!pSelReg->Attr.n.u1Unusable);
1829 Assert(!fUnusable);
1830 }
1831 else
1832 {
1833 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1834 pSelReg->Attr.n.u1DescType = 1;
1835 pSelReg->Attr.n.u2Dpl = 0;
1836 pSelReg->Attr.n.u1Present = 1;
1837 pSelReg->Attr.n.u1DefBig = 1;
1838 pSelReg->Attr.n.u1Granularity = 1;
1839 pSelReg->Attr.n.u1Unusable = fUnusable;
1840 }
1841 }
1842
1843 /* FS base. */
1844 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1845 || fHostInLongMode)
1846 {
1847 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1848 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1849 }
1850
1851 /* GS base. */
1852 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1853 || fHostInLongMode)
1854 {
1855 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1856 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1857 }
1858
1859 /* TR. */
1860 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1861 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1862 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1863 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1864 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1865 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1866 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1869 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1870 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1871 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1872 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1873
1874 /* LDTR (Warning! do not touch the base and limits here). */
1875 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1876 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1877 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1878 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1879
1880 /* GDTR. */
1881 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1882 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1883 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1884
1885 /* IDTR.*/
1886 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1887 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1888 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1889}
1890
1891
1892/**
1893 * Checks host PDPTes as part of VM-exit.
1894 *
1895 * @param pVCpu The cross context virtual CPU structure.
1896 * @param uExitReason The VM-exit reason (for logging purposes).
1897 */
1898IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1899{
1900 /*
1901 * Check host PDPTEs.
1902 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1903 */
1904 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1905 const char *const pszFailure = "VMX-abort";
1906 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1907
1908 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1909 && !fHostInLongMode)
1910 {
1911 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1912 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1913 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1914 if (RT_SUCCESS(rc))
1915 {
1916 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1917 {
1918 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1919 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1920 { /* likely */ }
1921 else
1922 {
1923 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1924 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1925 }
1926 }
1927 }
1928 else
1929 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1930 }
1931
1932 NOREF(pszFailure);
1933 NOREF(uExitReason);
1934 return VINF_SUCCESS;
1935}
1936
1937
1938/**
1939 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1940 *
1941 * @returns VBox status code.
1942 * @param pVCpu The cross context virtual CPU structure.
1943 * @param pszInstr The VMX instruction name (for logging purposes).
1944 */
1945IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1946{
1947 /*
1948 * Load host MSRs.
1949 * See Intel spec. 27.6 "Loading MSRs".
1950 */
1951 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1952 const char *const pszFailure = "VMX-abort";
1953
1954 /*
1955 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1956 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1957 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1958 */
1959 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1960 if (!cMsrs)
1961 return VINF_SUCCESS;
1962
1963 /*
1964 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1965 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1966 * implementation causes a VMX-abort followed by a triple-fault.
1967 */
1968 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1969 if (fIsMsrCountValid)
1970 { /* likely */ }
1971 else
1972 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1973
1974 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1975 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1976 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1977 if (RT_SUCCESS(rc))
1978 {
1979 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1980 Assert(pMsr);
1981 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1982 {
1983 if ( !pMsr->u32Reserved
1984 && pMsr->u32Msr != MSR_K8_FS_BASE
1985 && pMsr->u32Msr != MSR_K8_GS_BASE
1986 && pMsr->u32Msr != MSR_K6_EFER
1987 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1988 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1989 {
1990 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1991 if (rcStrict == VINF_SUCCESS)
1992 continue;
1993
1994 /*
1995 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1996 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1997 * recording the MSR index in the auxiliary info. field and indicated further by our
1998 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1999 * if possible, or come up with a better, generic solution.
2000 */
2001 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2002 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2003 ? kVmxVDiag_Vmexit_MsrLoadRing3
2004 : kVmxVDiag_Vmexit_MsrLoad;
2005 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2006 }
2007 else
2008 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2009 }
2010 }
2011 else
2012 {
2013 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2014 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2015 }
2016
2017 NOREF(uExitReason);
2018 NOREF(pszFailure);
2019 return VINF_SUCCESS;
2020}
2021
2022
2023/**
2024 * Loads the host state as part of VM-exit.
2025 *
2026 * @returns Strict VBox status code.
2027 * @param pVCpu The cross context virtual CPU structure.
2028 * @param uExitReason The VM-exit reason (for logging purposes).
2029 */
2030IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2031{
2032 /*
2033 * Load host state.
2034 * See Intel spec. 27.5 "Loading Host State".
2035 */
2036 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2037 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2038
2039 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2040 if ( CPUMIsGuestInLongMode(pVCpu)
2041 && !fHostInLongMode)
2042 {
2043 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2044 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2045 }
2046
2047 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2048 iemVmxVmexitLoadHostSegRegs(pVCpu);
2049
2050 /*
2051 * Load host RIP, RSP and RFLAGS.
2052 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2053 */
2054 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2055 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2056 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2057
2058 /* Clear address range monitoring. */
2059 EMMonitorWaitClear(pVCpu);
2060
2061 /* Perform the VMX transition (PGM updates). */
2062 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2063 if (rcStrict == VINF_SUCCESS)
2064 {
2065 /* Check host PDPTEs (only when we've fully switched page tables_. */
2066 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2067 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2068 if (RT_FAILURE(rc))
2069 {
2070 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2071 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2072 }
2073 }
2074 else if (RT_SUCCESS(rcStrict))
2075 {
2076 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2077 uExitReason));
2078 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2079 }
2080 else
2081 {
2082 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2083 return VBOXSTRICTRC_VAL(rcStrict);
2084 }
2085
2086 Assert(rcStrict == VINF_SUCCESS);
2087
2088 /* Load MSRs from the VM-exit auto-load MSR area. */
2089 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2090 if (RT_FAILURE(rc))
2091 {
2092 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2093 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2094 }
2095 return VINF_SUCCESS;
2096}
2097
2098
2099/**
2100 * Gets VM-exit instruction information along with any displacement for an
2101 * instruction VM-exit.
2102 *
2103 * @returns The VM-exit instruction information.
2104 * @param pVCpu The cross context virtual CPU structure.
2105 * @param uExitReason The VM-exit reason.
2106 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2107 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2108 * NULL.
2109 */
2110IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2111{
2112 RTGCPTR GCPtrDisp;
2113 VMXEXITINSTRINFO ExitInstrInfo;
2114 ExitInstrInfo.u = 0;
2115
2116 /*
2117 * Get and parse the ModR/M byte from our decoded opcodes.
2118 */
2119 uint8_t bRm;
2120 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2121 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2122 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2123 {
2124 /*
2125 * ModR/M indicates register addressing.
2126 *
2127 * The primary/secondary register operands are reported in the iReg1 or iReg2
2128 * fields depending on whether it is a read/write form.
2129 */
2130 uint8_t idxReg1;
2131 uint8_t idxReg2;
2132 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2133 {
2134 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2135 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2136 }
2137 else
2138 {
2139 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2140 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2141 }
2142 ExitInstrInfo.All.u2Scaling = 0;
2143 ExitInstrInfo.All.iReg1 = idxReg1;
2144 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2145 ExitInstrInfo.All.fIsRegOperand = 1;
2146 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2147 ExitInstrInfo.All.iSegReg = 0;
2148 ExitInstrInfo.All.iIdxReg = 0;
2149 ExitInstrInfo.All.fIdxRegInvalid = 1;
2150 ExitInstrInfo.All.iBaseReg = 0;
2151 ExitInstrInfo.All.fBaseRegInvalid = 1;
2152 ExitInstrInfo.All.iReg2 = idxReg2;
2153
2154 /* Displacement not applicable for register addressing. */
2155 GCPtrDisp = 0;
2156 }
2157 else
2158 {
2159 /*
2160 * ModR/M indicates memory addressing.
2161 */
2162 uint8_t uScale = 0;
2163 bool fBaseRegValid = false;
2164 bool fIdxRegValid = false;
2165 uint8_t iBaseReg = 0;
2166 uint8_t iIdxReg = 0;
2167 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2168 {
2169 /*
2170 * Parse the ModR/M, displacement for 16-bit addressing mode.
2171 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2172 */
2173 uint16_t u16Disp = 0;
2174 uint8_t const offDisp = offModRm + sizeof(bRm);
2175 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2176 {
2177 /* Displacement without any registers. */
2178 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2179 }
2180 else
2181 {
2182 /* Register (index and base). */
2183 switch (bRm & X86_MODRM_RM_MASK)
2184 {
2185 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2186 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2187 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2188 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2189 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2190 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2191 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2192 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2193 }
2194
2195 /* Register + displacement. */
2196 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2197 {
2198 case 0: break;
2199 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2200 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2201 default:
2202 {
2203 /* Register addressing, handled at the beginning. */
2204 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2205 break;
2206 }
2207 }
2208 }
2209
2210 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2211 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2212 }
2213 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2214 {
2215 /*
2216 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2217 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2218 */
2219 uint32_t u32Disp = 0;
2220 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2221 {
2222 /* Displacement without any registers. */
2223 uint8_t const offDisp = offModRm + sizeof(bRm);
2224 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2225 }
2226 else
2227 {
2228 /* Register (and perhaps scale, index and base). */
2229 uint8_t offDisp = offModRm + sizeof(bRm);
2230 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2231 if (iBaseReg == 4)
2232 {
2233 /* An SIB byte follows the ModR/M byte, parse it. */
2234 uint8_t bSib;
2235 uint8_t const offSib = offModRm + sizeof(bRm);
2236 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2237
2238 /* A displacement may follow SIB, update its offset. */
2239 offDisp += sizeof(bSib);
2240
2241 /* Get the scale. */
2242 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2243
2244 /* Get the index register. */
2245 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2246 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2247
2248 /* Get the base register. */
2249 iBaseReg = bSib & X86_SIB_BASE_MASK;
2250 fBaseRegValid = true;
2251 if (iBaseReg == 5)
2252 {
2253 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2254 {
2255 /* Mod is 0 implies a 32-bit displacement with no base. */
2256 fBaseRegValid = false;
2257 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2258 }
2259 else
2260 {
2261 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2262 iBaseReg = X86_GREG_xBP;
2263 }
2264 }
2265 }
2266
2267 /* Register + displacement. */
2268 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2269 {
2270 case 0: /* Handled above */ break;
2271 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2272 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2273 default:
2274 {
2275 /* Register addressing, handled at the beginning. */
2276 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2277 break;
2278 }
2279 }
2280 }
2281
2282 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2283 }
2284 else
2285 {
2286 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2287
2288 /*
2289 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2290 * See Intel instruction spec. 2.2 "IA-32e Mode".
2291 */
2292 uint64_t u64Disp = 0;
2293 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2294 if (fRipRelativeAddr)
2295 {
2296 /*
2297 * RIP-relative addressing mode.
2298 *
2299 * The displacement is 32-bit signed implying an offset range of +/-2G.
2300 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2301 */
2302 uint8_t const offDisp = offModRm + sizeof(bRm);
2303 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2304 }
2305 else
2306 {
2307 uint8_t offDisp = offModRm + sizeof(bRm);
2308
2309 /*
2310 * Register (and perhaps scale, index and base).
2311 *
2312 * REX.B extends the most-significant bit of the base register. However, REX.B
2313 * is ignored while determining whether an SIB follows the opcode. Hence, we
2314 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2315 *
2316 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2317 */
2318 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2319 if (iBaseReg == 4)
2320 {
2321 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2322 uint8_t bSib;
2323 uint8_t const offSib = offModRm + sizeof(bRm);
2324 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2325
2326 /* Displacement may follow SIB, update its offset. */
2327 offDisp += sizeof(bSib);
2328
2329 /* Get the scale. */
2330 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2331
2332 /* Get the index. */
2333 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2334 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2335
2336 /* Get the base. */
2337 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2338 fBaseRegValid = true;
2339 if (iBaseReg == 5)
2340 {
2341 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2342 {
2343 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2344 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2345 }
2346 else
2347 {
2348 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2349 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2350 }
2351 }
2352 }
2353 iBaseReg |= pVCpu->iem.s.uRexB;
2354
2355 /* Register + displacement. */
2356 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2357 {
2358 case 0: /* Handled above */ break;
2359 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2360 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2361 default:
2362 {
2363 /* Register addressing, handled at the beginning. */
2364 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2365 break;
2366 }
2367 }
2368 }
2369
2370 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2371 }
2372
2373 /*
2374 * The primary or secondary register operand is reported in iReg2 depending
2375 * on whether the primary operand is in read/write form.
2376 */
2377 uint8_t idxReg2;
2378 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2379 {
2380 idxReg2 = bRm & X86_MODRM_RM_MASK;
2381 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2382 idxReg2 |= pVCpu->iem.s.uRexB;
2383 }
2384 else
2385 {
2386 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2387 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2388 idxReg2 |= pVCpu->iem.s.uRexReg;
2389 }
2390 ExitInstrInfo.All.u2Scaling = uScale;
2391 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2392 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2393 ExitInstrInfo.All.fIsRegOperand = 0;
2394 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2395 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2396 ExitInstrInfo.All.iIdxReg = iIdxReg;
2397 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2398 ExitInstrInfo.All.iBaseReg = iBaseReg;
2399 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2400 ExitInstrInfo.All.iReg2 = idxReg2;
2401 }
2402
2403 /*
2404 * Handle exceptions to the norm for certain instructions.
2405 * (e.g. some instructions convey an instruction identity in place of iReg2).
2406 */
2407 switch (uExitReason)
2408 {
2409 case VMX_EXIT_GDTR_IDTR_ACCESS:
2410 {
2411 Assert(VMXINSTRID_IS_VALID(uInstrId));
2412 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2413 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2414 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2415 break;
2416 }
2417
2418 case VMX_EXIT_LDTR_TR_ACCESS:
2419 {
2420 Assert(VMXINSTRID_IS_VALID(uInstrId));
2421 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2422 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2423 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2424 break;
2425 }
2426
2427 case VMX_EXIT_RDRAND:
2428 case VMX_EXIT_RDSEED:
2429 {
2430 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2431 break;
2432 }
2433 }
2434
2435 /* Update displacement and return the constructed VM-exit instruction information field. */
2436 if (pGCPtrDisp)
2437 *pGCPtrDisp = GCPtrDisp;
2438
2439 return ExitInstrInfo.u;
2440}
2441
2442
2443/**
2444 * VMX VM-exit handler.
2445 *
2446 * @returns Strict VBox status code.
2447 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2448 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2449 * triple-fault.
2450 *
2451 * @param pVCpu The cross context virtual CPU structure.
2452 * @param uExitReason The VM-exit reason.
2453 * @param u64ExitQual The Exit qualification.
2454 */
2455IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2456{
2457# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2458 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2459 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2460 return VERR_IEM_IPE_7;
2461# else
2462 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2463 Assert(pVmcs);
2464
2465 /*
2466 * Import all the guest-CPU state.
2467 *
2468 * HM on returning to guest execution would have to reset up a whole lot of state
2469 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2470 * the state and flag reloading the entire state on re-entry. So import the entire
2471 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2472 */
2473 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2474
2475 /*
2476 * Ensure VM-entry interruption information valid bit is cleared.
2477 *
2478 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2479 * by invalid-guest state or machine-check exceptions) also clear this bit.
2480 *
2481 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2482 */
2483 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2484 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2485
2486 /*
2487 * Update the VM-exit reason and Exit qualification.
2488 * Other VMCS read-only data fields are expected to be updated by the caller already.
2489 */
2490 pVmcs->u32RoExitReason = uExitReason;
2491 pVmcs->u64RoExitQual.u = u64ExitQual;
2492
2493 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2494 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2495 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2496
2497 /*
2498 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2499 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2500 */
2501 {
2502 uint8_t uVector;
2503 uint32_t fFlags;
2504 uint32_t uErrCode;
2505 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2506 if (fInEventDelivery)
2507 {
2508 /*
2509 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2510 * caused by a triple-fault or the original event results in a double-fault that
2511 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2512 * original event information into the IDT-vectoring information fields.
2513 *
2514 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2515 */
2516 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2517 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2518 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2519 {
2520 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2521 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2522 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2523 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2524 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2525 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2526 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2527 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2528 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2529 pVCpu->cpum.GstCtx.cr2));
2530 }
2531 }
2532 }
2533
2534 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2535 Assert(pVmcs->u64RoIoRcx.u == 0);
2536 Assert(pVmcs->u64RoIoRsi.u == 0);
2537 Assert(pVmcs->u64RoIoRdi.u == 0);
2538 Assert(pVmcs->u64RoIoRip.u == 0);
2539
2540 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2541 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2542 {
2543 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2544 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2545 }
2546
2547 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2548 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2549
2550 /*
2551 * Save the guest state back into the VMCS.
2552 * We only need to save the state when the VM-entry was successful.
2553 */
2554 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2555 if (!fVmentryFailed)
2556 {
2557 /*
2558 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2559 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2560 *
2561 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2562 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2563 * as guest-CPU state would not been modified. Hence for now, we do this only when
2564 * the VM-entry succeeded.
2565 */
2566 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2567 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2568 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2569 {
2570 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2571 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2572 else
2573 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2574 }
2575
2576 /*
2577 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2578 * occurs in enclave mode/SMM which we don't support yet.
2579 *
2580 * If we ever add support for it, we can pass just the lower bits to the functions
2581 * below, till then an assert should suffice.
2582 */
2583 Assert(!RT_HI_U16(uExitReason));
2584
2585 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2586 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2587 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2588 if (RT_SUCCESS(rc))
2589 { /* likely */ }
2590 else
2591 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2592
2593 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2594 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2595 }
2596 else
2597 {
2598 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2599 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2600 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2601 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2602 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2603 }
2604
2605 /*
2606 * Stop any running VMX-preemption timer if necessary.
2607 */
2608 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2609 CPUMStopGuestVmxPremptTimer(pVCpu);
2610
2611 /*
2612 * Clear any pending VMX nested-guest force-flags.
2613 * These force-flags have no effect on (outer) guest execution and will
2614 * be re-evaluated and setup on the next nested-guest VM-entry.
2615 */
2616 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2617
2618 /* Restore the host (outer guest) state. */
2619 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2620 if (RT_SUCCESS(rcStrict))
2621 {
2622 Assert(rcStrict == VINF_SUCCESS);
2623 rcStrict = VINF_VMX_VMEXIT;
2624 }
2625 else
2626 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2627
2628 /* We're no longer in nested-guest execution mode. */
2629 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2630
2631 /* Notify HM that the current VMCS fields have been modified. */
2632 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2633
2634 /* Notify HM that we've completed the VM-exit. */
2635 HMNotifyVmxNstGstVmexit(pVCpu);
2636
2637# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2638 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2639 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2640 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2641 if (rcSched != VINF_SUCCESS)
2642 iemSetPassUpStatus(pVCpu, rcSched);
2643# endif
2644 return rcStrict;
2645# endif
2646}
2647
2648
2649/**
2650 * VMX VM-exit handler for VM-exits due to instruction execution.
2651 *
2652 * This is intended for instructions where the caller provides all the relevant
2653 * VM-exit information.
2654 *
2655 * @returns Strict VBox status code.
2656 * @param pVCpu The cross context virtual CPU structure.
2657 * @param pExitInfo Pointer to the VM-exit information.
2658 */
2659IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2660{
2661 /*
2662 * For instructions where any of the following fields are not applicable:
2663 * - Exit qualification must be cleared.
2664 * - VM-exit instruction info. is undefined.
2665 * - Guest-linear address is undefined.
2666 * - Guest-physical address is undefined.
2667 *
2668 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2669 * instruction execution. For VM-exits that are not due to instruction execution this
2670 * field is undefined.
2671 *
2672 * In our implementation in IEM, all undefined fields are generally cleared. However,
2673 * if the caller supplies information (from say the physical CPU directly) it is
2674 * then possible that the undefined fields are not cleared.
2675 *
2676 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2677 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2678 */
2679 Assert(pExitInfo);
2680 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2681 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2682 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2683
2684 /* Update all the relevant fields from the VM-exit instruction information struct. */
2685 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2686 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2687 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2688 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2689
2690 /* Perform the VM-exit. */
2691 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2692}
2693
2694
2695/**
2696 * VMX VM-exit handler for VM-exits due to instruction execution.
2697 *
2698 * This is intended for instructions that only provide the VM-exit instruction
2699 * length.
2700 *
2701 * @param pVCpu The cross context virtual CPU structure.
2702 * @param uExitReason The VM-exit reason.
2703 * @param cbInstr The instruction length in bytes.
2704 */
2705IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2706{
2707 VMXVEXITINFO ExitInfo;
2708 RT_ZERO(ExitInfo);
2709 ExitInfo.uReason = uExitReason;
2710 ExitInfo.cbInstr = cbInstr;
2711
2712#ifdef VBOX_STRICT
2713 /*
2714 * To prevent us from shooting ourselves in the foot.
2715 * The follow instructions should convey more than just the instruction length.
2716 */
2717 switch (uExitReason)
2718 {
2719 case VMX_EXIT_INVEPT:
2720 case VMX_EXIT_INVPCID:
2721 case VMX_EXIT_INVVPID:
2722 case VMX_EXIT_LDTR_TR_ACCESS:
2723 case VMX_EXIT_GDTR_IDTR_ACCESS:
2724 case VMX_EXIT_VMCLEAR:
2725 case VMX_EXIT_VMPTRLD:
2726 case VMX_EXIT_VMPTRST:
2727 case VMX_EXIT_VMREAD:
2728 case VMX_EXIT_VMWRITE:
2729 case VMX_EXIT_VMXON:
2730 case VMX_EXIT_XRSTORS:
2731 case VMX_EXIT_XSAVES:
2732 case VMX_EXIT_RDRAND:
2733 case VMX_EXIT_RDSEED:
2734 case VMX_EXIT_IO_INSTR:
2735 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2736 break;
2737 }
2738#endif
2739
2740 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2741}
2742
2743
2744/**
2745 * VMX VM-exit handler for VM-exits due to instruction execution.
2746 *
2747 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2748 * instruction information and Exit qualification fields.
2749 *
2750 * @param pVCpu The cross context virtual CPU structure.
2751 * @param uExitReason The VM-exit reason.
2752 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2753 * @param cbInstr The instruction length in bytes.
2754 *
2755 * @remarks Do not use this for INS/OUTS instruction.
2756 */
2757IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2758{
2759 VMXVEXITINFO ExitInfo;
2760 RT_ZERO(ExitInfo);
2761 ExitInfo.uReason = uExitReason;
2762 ExitInfo.cbInstr = cbInstr;
2763
2764 /*
2765 * Update the Exit qualification field with displacement bytes.
2766 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2767 */
2768 switch (uExitReason)
2769 {
2770 case VMX_EXIT_INVEPT:
2771 case VMX_EXIT_INVPCID:
2772 case VMX_EXIT_INVVPID:
2773 case VMX_EXIT_LDTR_TR_ACCESS:
2774 case VMX_EXIT_GDTR_IDTR_ACCESS:
2775 case VMX_EXIT_VMCLEAR:
2776 case VMX_EXIT_VMPTRLD:
2777 case VMX_EXIT_VMPTRST:
2778 case VMX_EXIT_VMREAD:
2779 case VMX_EXIT_VMWRITE:
2780 case VMX_EXIT_VMXON:
2781 case VMX_EXIT_XRSTORS:
2782 case VMX_EXIT_XSAVES:
2783 case VMX_EXIT_RDRAND:
2784 case VMX_EXIT_RDSEED:
2785 {
2786 /* Construct the VM-exit instruction information. */
2787 RTGCPTR GCPtrDisp;
2788 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2789
2790 /* Update the VM-exit instruction information. */
2791 ExitInfo.InstrInfo.u = uInstrInfo;
2792
2793 /* Update the Exit qualification. */
2794 ExitInfo.u64Qual = GCPtrDisp;
2795 break;
2796 }
2797
2798 default:
2799 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2800 break;
2801 }
2802
2803 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2804}
2805
2806
2807/**
2808 * VMX VM-exit handler for VM-exits due to INVLPG.
2809 *
2810 * @returns Strict VBox status code.
2811 * @param pVCpu The cross context virtual CPU structure.
2812 * @param GCPtrPage The guest-linear address of the page being invalidated.
2813 * @param cbInstr The instruction length in bytes.
2814 */
2815IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2816{
2817 VMXVEXITINFO ExitInfo;
2818 RT_ZERO(ExitInfo);
2819 ExitInfo.uReason = VMX_EXIT_INVLPG;
2820 ExitInfo.cbInstr = cbInstr;
2821 ExitInfo.u64Qual = GCPtrPage;
2822 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2823
2824 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2825}
2826
2827
2828/**
2829 * VMX VM-exit handler for VM-exits due to LMSW.
2830 *
2831 * @returns Strict VBox status code.
2832 * @param pVCpu The cross context virtual CPU structure.
2833 * @param uGuestCr0 The current guest CR0.
2834 * @param pu16NewMsw The machine-status word specified in LMSW's source
2835 * operand. This will be updated depending on the VMX
2836 * guest/host CR0 mask if LMSW is not intercepted.
2837 * @param GCPtrEffDst The guest-linear address of the source operand in case
2838 * of a memory operand. For register operand, pass
2839 * NIL_RTGCPTR.
2840 * @param cbInstr The instruction length in bytes.
2841 */
2842IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2843 uint8_t cbInstr)
2844{
2845 Assert(pu16NewMsw);
2846
2847 uint16_t const uNewMsw = *pu16NewMsw;
2848 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2849 {
2850 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2851
2852 VMXVEXITINFO ExitInfo;
2853 RT_ZERO(ExitInfo);
2854 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2855 ExitInfo.cbInstr = cbInstr;
2856
2857 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2858 if (fMemOperand)
2859 {
2860 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2861 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2862 }
2863
2864 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2865 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2866 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2867 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2868
2869 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2870 }
2871
2872 /*
2873 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2874 * CR0 guest/host mask must be left unmodified.
2875 *
2876 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2877 */
2878 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2879 Assert(pVmcs);
2880 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2881 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2882 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2883
2884 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2885}
2886
2887
2888/**
2889 * VMX VM-exit handler for VM-exits due to CLTS.
2890 *
2891 * @returns Strict VBox status code.
2892 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2893 * VM-exit but must not modify the guest CR0.TS bit.
2894 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2895 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2896 * CR0 fixed bits in VMX operation).
2897 * @param pVCpu The cross context virtual CPU structure.
2898 * @param cbInstr The instruction length in bytes.
2899 */
2900IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2901{
2902 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2903 Assert(pVmcs);
2904
2905 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2906 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2907
2908 /*
2909 * If CR0.TS is owned by the host:
2910 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2911 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2912 * CLTS instruction completes without clearing CR0.TS.
2913 *
2914 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2915 */
2916 if (fGstHostMask & X86_CR0_TS)
2917 {
2918 if (fReadShadow & X86_CR0_TS)
2919 {
2920 Log2(("clts: Guest intercept -> VM-exit\n"));
2921
2922 VMXVEXITINFO ExitInfo;
2923 RT_ZERO(ExitInfo);
2924 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2925 ExitInfo.cbInstr = cbInstr;
2926 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2927 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2928 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2929 }
2930
2931 return VINF_VMX_MODIFIES_BEHAVIOR;
2932 }
2933
2934 /*
2935 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2936 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2937 */
2938 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2939}
2940
2941
2942/**
2943 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2944 * (CR0/CR4 write).
2945 *
2946 * @returns Strict VBox status code.
2947 * @param pVCpu The cross context virtual CPU structure.
2948 * @param iCrReg The control register (either CR0 or CR4).
2949 * @param uGuestCrX The current guest CR0/CR4.
2950 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2951 * VM-exit is caused.
2952 * @param iGReg The general register from which the CR0/CR4 value is being
2953 * loaded.
2954 * @param cbInstr The instruction length in bytes.
2955 */
2956IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2957 uint8_t cbInstr)
2958{
2959 Assert(puNewCrX);
2960 Assert(iCrReg == 0 || iCrReg == 4);
2961 Assert(iGReg < X86_GREG_COUNT);
2962
2963 uint64_t const uNewCrX = *puNewCrX;
2964 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2965 {
2966 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2967
2968 VMXVEXITINFO ExitInfo;
2969 RT_ZERO(ExitInfo);
2970 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2971 ExitInfo.cbInstr = cbInstr;
2972 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2973 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2974 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2975 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2976 }
2977
2978 /*
2979 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2980 * must not be modified the instruction.
2981 *
2982 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2983 */
2984 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2985 Assert(pVmcs);
2986 uint64_t uGuestCrX;
2987 uint64_t fGstHostMask;
2988 if (iCrReg == 0)
2989 {
2990 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2991 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2992 fGstHostMask = pVmcs->u64Cr0Mask.u;
2993 }
2994 else
2995 {
2996 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2997 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2998 fGstHostMask = pVmcs->u64Cr4Mask.u;
2999 }
3000
3001 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3002 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3003}
3004
3005
3006/**
3007 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3008 *
3009 * @returns VBox strict status code.
3010 * @param pVCpu The cross context virtual CPU structure.
3011 * @param iGReg The general register to which the CR3 value is being stored.
3012 * @param cbInstr The instruction length in bytes.
3013 */
3014IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3015{
3016 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3017 Assert(pVmcs);
3018 Assert(iGReg < X86_GREG_COUNT);
3019 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3020
3021 /*
3022 * If the CR3-store exiting control is set, we must cause a VM-exit.
3023 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3024 */
3025 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3026 {
3027 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3028
3029 VMXVEXITINFO ExitInfo;
3030 RT_ZERO(ExitInfo);
3031 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3032 ExitInfo.cbInstr = cbInstr;
3033 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3034 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3035 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3036 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3037 }
3038
3039 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3040}
3041
3042
3043/**
3044 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3045 *
3046 * @returns VBox strict status code.
3047 * @param pVCpu The cross context virtual CPU structure.
3048 * @param uNewCr3 The new CR3 value.
3049 * @param iGReg The general register from which the CR3 value is being
3050 * loaded.
3051 * @param cbInstr The instruction length in bytes.
3052 */
3053IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3054{
3055 Assert(iGReg < X86_GREG_COUNT);
3056
3057 /*
3058 * If the CR3-load exiting control is set and the new CR3 value does not
3059 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3060 *
3061 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3062 */
3063 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3064 {
3065 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3066
3067 VMXVEXITINFO ExitInfo;
3068 RT_ZERO(ExitInfo);
3069 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3070 ExitInfo.cbInstr = cbInstr;
3071 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3072 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3073 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3074 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3075 }
3076
3077 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3078}
3079
3080
3081/**
3082 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3083 *
3084 * @returns VBox strict status code.
3085 * @param pVCpu The cross context virtual CPU structure.
3086 * @param iGReg The general register to which the CR8 value is being stored.
3087 * @param cbInstr The instruction length in bytes.
3088 */
3089IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3090{
3091 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3092 Assert(pVmcs);
3093 Assert(iGReg < X86_GREG_COUNT);
3094
3095 /*
3096 * If the CR8-store exiting control is set, we must cause a VM-exit.
3097 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3098 */
3099 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3100 {
3101 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3102
3103 VMXVEXITINFO ExitInfo;
3104 RT_ZERO(ExitInfo);
3105 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3106 ExitInfo.cbInstr = cbInstr;
3107 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3108 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3109 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3110 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3111 }
3112
3113 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3114}
3115
3116
3117/**
3118 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3119 *
3120 * @returns VBox strict status code.
3121 * @param pVCpu The cross context virtual CPU structure.
3122 * @param iGReg The general register from which the CR8 value is being
3123 * loaded.
3124 * @param cbInstr The instruction length in bytes.
3125 */
3126IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3127{
3128 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3129 Assert(pVmcs);
3130 Assert(iGReg < X86_GREG_COUNT);
3131
3132 /*
3133 * If the CR8-load exiting control is set, we must cause a VM-exit.
3134 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3135 */
3136 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3137 {
3138 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3139
3140 VMXVEXITINFO ExitInfo;
3141 RT_ZERO(ExitInfo);
3142 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3143 ExitInfo.cbInstr = cbInstr;
3144 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3145 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3146 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3147 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3148 }
3149
3150 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3151}
3152
3153
3154/**
3155 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3156 * GReg,DRx' (DRx read).
3157 *
3158 * @returns VBox strict status code.
3159 * @param pVCpu The cross context virtual CPU structure.
3160 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3161 * VMXINSTRID_MOV_FROM_DRX).
3162 * @param iDrReg The debug register being accessed.
3163 * @param iGReg The general register to/from which the DRx value is being
3164 * store/loaded.
3165 * @param cbInstr The instruction length in bytes.
3166 */
3167IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3168 uint8_t cbInstr)
3169{
3170 Assert(iDrReg <= 7);
3171 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3172 Assert(iGReg < X86_GREG_COUNT);
3173
3174 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3175 Assert(pVmcs);
3176
3177 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3178 {
3179 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3180 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3181 VMXVEXITINFO ExitInfo;
3182 RT_ZERO(ExitInfo);
3183 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3184 ExitInfo.cbInstr = cbInstr;
3185 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3186 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3187 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3188 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3189 }
3190
3191 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3192}
3193
3194
3195/**
3196 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3197 *
3198 * @returns VBox strict status code.
3199 * @param pVCpu The cross context virtual CPU structure.
3200 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3201 * VMXINSTRID_IO_OUT).
3202 * @param u16Port The I/O port being accessed.
3203 * @param fImm Whether the I/O port was encoded using an immediate operand
3204 * or the implicit DX register.
3205 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3206 * @param cbInstr The instruction length in bytes.
3207 */
3208IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3209 uint8_t cbInstr)
3210{
3211 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3212 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3213
3214 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3215 if (fIntercept)
3216 {
3217 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3218 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3219 VMXVEXITINFO ExitInfo;
3220 RT_ZERO(ExitInfo);
3221 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3222 ExitInfo.cbInstr = cbInstr;
3223 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3224 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3225 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3226 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3227 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3228 }
3229
3230 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3231}
3232
3233
3234/**
3235 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3236 *
3237 * @returns VBox strict status code.
3238 * @param pVCpu The cross context virtual CPU structure.
3239 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3240 * VMXINSTRID_IO_OUTS).
3241 * @param u16Port The I/O port being accessed.
3242 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3243 * @param fRep Whether the instruction has a REP prefix or not.
3244 * @param ExitInstrInfo The VM-exit instruction info. field.
3245 * @param cbInstr The instruction length in bytes.
3246 */
3247IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3248 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3249{
3250 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3251 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3252 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3253 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3254 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3255
3256 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3257 if (fIntercept)
3258 {
3259 /*
3260 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3261 */
3262 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3263 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3264 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3265 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3266 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3267
3268 uint32_t uDirection;
3269 uint64_t uGuestLinearAddr;
3270 if (uInstrId == VMXINSTRID_IO_INS)
3271 {
3272 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3273 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3274 }
3275 else
3276 {
3277 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3278 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3279 }
3280
3281 /*
3282 * If the segment is unusable, the guest-linear address in undefined.
3283 * We shall clear it for consistency.
3284 *
3285 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3286 */
3287 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3288 uGuestLinearAddr = 0;
3289
3290 VMXVEXITINFO ExitInfo;
3291 RT_ZERO(ExitInfo);
3292 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3293 ExitInfo.cbInstr = cbInstr;
3294 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3295 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3296 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3297 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3298 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3299 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3300 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3301 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3302 ExitInfo.InstrInfo = ExitInstrInfo;
3303 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3304 }
3305
3306 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3307}
3308
3309
3310/**
3311 * VMX VM-exit handler for VM-exits due to MWAIT.
3312 *
3313 * @returns VBox strict status code.
3314 * @param pVCpu The cross context virtual CPU structure.
3315 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3316 * @param cbInstr The instruction length in bytes.
3317 */
3318IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3319{
3320 VMXVEXITINFO ExitInfo;
3321 RT_ZERO(ExitInfo);
3322 ExitInfo.uReason = VMX_EXIT_MWAIT;
3323 ExitInfo.cbInstr = cbInstr;
3324 ExitInfo.u64Qual = fMonitorHwArmed;
3325 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3326}
3327
3328
3329/**
3330 * VMX VM-exit handler for VM-exits due to PAUSE.
3331 *
3332 * @returns VBox strict status code.
3333 * @param pVCpu The cross context virtual CPU structure.
3334 * @param cbInstr The instruction length in bytes.
3335 */
3336IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3337{
3338 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3339 Assert(pVmcs);
3340
3341 /*
3342 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3343 * "PAUSE-loop exiting" control.
3344 *
3345 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3346 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3347 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3348 * a VM-exit.
3349 *
3350 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3351 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3352 */
3353 bool fIntercept = false;
3354 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3355 fIntercept = true;
3356 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3357 && pVCpu->iem.s.uCpl == 0)
3358 {
3359 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3360
3361 /*
3362 * A previous-PAUSE-tick value of 0 is used to identify the first time
3363 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3364 * consider this to be the first execution of PAUSE in a loop according
3365 * to the Intel.
3366 *
3367 * All subsequent records for the previous-PAUSE-tick we ensure that it
3368 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3369 */
3370 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3371 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3372 uint64_t const uTick = TMCpuTickGet(pVCpu);
3373 uint32_t const uPleGap = pVmcs->u32PleGap;
3374 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3375 if ( *puPrevPauseTick == 0
3376 || uTick - *puPrevPauseTick > uPleGap)
3377 *puFirstPauseLoopTick = uTick;
3378 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3379 fIntercept = true;
3380
3381 *puPrevPauseTick = uTick | 1;
3382 }
3383
3384 if (fIntercept)
3385 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3386
3387 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3388}
3389
3390
3391/**
3392 * VMX VM-exit handler for VM-exits due to task switches.
3393 *
3394 * @returns VBox strict status code.
3395 * @param pVCpu The cross context virtual CPU structure.
3396 * @param enmTaskSwitch The cause of the task switch.
3397 * @param SelNewTss The selector of the new TSS.
3398 * @param cbInstr The instruction length in bytes.
3399 */
3400IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3401{
3402 /*
3403 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3404 *
3405 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3406 * instruction or delivery of the exception generated by one of these instructions
3407 * lead to a task switch through a task gate in the IDT, we need to provide the
3408 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3409 * leaves the VM-exit instruction length field undefined.
3410 *
3411 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3412 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3413 */
3414 Assert(cbInstr <= 15);
3415
3416 uint8_t uType;
3417 switch (enmTaskSwitch)
3418 {
3419 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3420 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3421 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3422 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3423 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3424 }
3425
3426 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3427 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3428 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3429 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3430}
3431
3432
3433/**
3434 * VMX VM-exit handler for trap-like VM-exits.
3435 *
3436 * @returns VBox strict status code.
3437 * @param pVCpu The cross context virtual CPU structure.
3438 * @param pExitInfo Pointer to the VM-exit information.
3439 * @param pExitEventInfo Pointer to the VM-exit event information.
3440 */
3441IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3442{
3443 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3444 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3445 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3446}
3447
3448
3449/**
3450 * VMX VM-exit handler for VM-exits due to task switches.
3451 *
3452 * This is intended for task switches where the caller provides all the relevant
3453 * VM-exit information.
3454 *
3455 * @returns VBox strict status code.
3456 * @param pVCpu The cross context virtual CPU structure.
3457 * @param pExitInfo Pointer to the VM-exit information.
3458 * @param pExitEventInfo Pointer to the VM-exit event information.
3459 */
3460IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3461 PCVMXVEXITEVENTINFO pExitEventInfo)
3462{
3463 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3464 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3465 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3466 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3467 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3468}
3469
3470
3471/**
3472 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3473 *
3474 * @returns VBox strict status code.
3475 * @param pVCpu The cross context virtual CPU structure.
3476 */
3477IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3478{
3479 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3480 Assert(pVmcs);
3481 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3482 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3483
3484 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3485 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3486
3487 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3488 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3489 pVmcs->u32PreemptTimer = 0;
3490
3491 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3492 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3493}
3494
3495
3496/**
3497 * VMX VM-exit handler for VM-exits due to external interrupts.
3498 *
3499 * @returns VBox strict status code.
3500 * @param pVCpu The cross context virtual CPU structure.
3501 * @param uVector The external interrupt vector (pass 0 if the interrupt
3502 * is still pending since we typically won't know the
3503 * vector).
3504 * @param fIntPending Whether the external interrupt is pending or
3505 * acknowledged in the interrupt controller.
3506 */
3507IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3508{
3509 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3510 Assert(pVmcs);
3511 Assert(!fIntPending || uVector == 0);
3512
3513 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3514 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3515 * functions require prior checking of a blanket intercept and which don't.
3516 * It is better for the caller to check a blanket intercept performance wise
3517 * than making a function call. Leaving this as a todo because it is more
3518 * a performance issue. */
3519
3520 /* The VM-exit is subject to "External interrupt exiting" being set. */
3521 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3522 {
3523 if (fIntPending)
3524 {
3525 /*
3526 * If the interrupt is pending and we don't need to acknowledge the
3527 * interrupt on VM-exit, cause the VM-exit immediately.
3528 *
3529 * See Intel spec 25.2 "Other Causes Of VM Exits".
3530 */
3531 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3532 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3533
3534 /*
3535 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3536 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3537 * acknowledged that the interrupt has been consumed.
3538 */
3539 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3540 }
3541
3542 /*
3543 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3544 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3545 * all set, we cause the VM-exit now. We need to record the external interrupt that
3546 * just occurred in the VM-exit interruption information field.
3547 *
3548 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3549 */
3550 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3551 {
3552 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3553 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3554 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3555 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3556 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3557 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3558 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3559 }
3560 }
3561
3562 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3563}
3564
3565
3566/**
3567 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3568 * an event.
3569 *
3570 * @returns VBox strict status code.
3571 * @param pVCpu The cross context virtual CPU structure.
3572 */
3573IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3574{
3575 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3576 Assert(pVmcs);
3577
3578 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3579 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3580 {
3581 /*
3582 * The NMI-unblocking due to IRET field need not be set for double faults.
3583 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3584 */
3585 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3586 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3587 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3588 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3589 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3590 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3591 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3592 }
3593
3594 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3595}
3596
3597
3598/**
3599 * VMX VM-exit handler for VM-exit due to delivery of an events.
3600 *
3601 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3602 * all the relevant VM-exit information.
3603 *
3604 * @returns VBox strict status code.
3605 * @param pVCpu The cross context virtual CPU structure.
3606 * @param pExitInfo Pointer to the VM-exit information.
3607 * @param pExitEventInfo Pointer to the VM-exit event information.
3608 */
3609IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3610{
3611 Assert(pExitInfo);
3612 Assert(pExitEventInfo);
3613 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3614 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3615
3616 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3617 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3618 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3619 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3620 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3621 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3622}
3623
3624
3625/**
3626 * VMX VM-exit handler for VM-exits due to delivery of an event.
3627 *
3628 * @returns VBox strict status code.
3629 * @param pVCpu The cross context virtual CPU structure.
3630 * @param uVector The interrupt / exception vector.
3631 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3632 * @param uErrCode The error code associated with the event.
3633 * @param uCr2 The CR2 value in case of a \#PF exception.
3634 * @param cbInstr The instruction length in bytes.
3635 */
3636IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3637 uint8_t cbInstr)
3638{
3639 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3640 Assert(pVmcs);
3641
3642 /*
3643 * If the event is being injected as part of VM-entry, it is -not- subject to event
3644 * intercepts in the nested-guest. However, secondary exceptions that occur during
3645 * injection of any event -are- subject to event interception.
3646 *
3647 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3648 */
3649 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3650 {
3651 /*
3652 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3653 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3654 *
3655 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3656 */
3657 if ( uVector == X86_XCPT_NMI
3658 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3659 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3660 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3661 else
3662 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3663
3664 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3665 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3666 }
3667
3668 /*
3669 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3670 * If not, the caller will continue delivery of the external interrupt as it would
3671 * normally. The interrupt is no longer pending in the interrupt controller at this
3672 * point.
3673 */
3674 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3675 {
3676 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3677 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3678 }
3679
3680 /*
3681 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3682 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3683 * interrupts.
3684 */
3685 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3686 bool fIntercept;
3687 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3688 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3689 {
3690 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3691 }
3692 else
3693 {
3694 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3695 fIntercept = false;
3696 }
3697
3698 /*
3699 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3700 * relevant VM-exit information and cause the VM-exit.
3701 */
3702 if (fIntercept)
3703 {
3704 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3705
3706 /* Construct the rest of the event related information fields and cause the VM-exit. */
3707 uint64_t u64ExitQual;
3708 if (uVector == X86_XCPT_PF)
3709 {
3710 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3711 u64ExitQual = uCr2;
3712 }
3713 else if (uVector == X86_XCPT_DB)
3714 {
3715 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3716 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3717 }
3718 else
3719 u64ExitQual = 0;
3720
3721 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3722 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3723 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3724 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3725 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3726 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3727 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3728 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3729 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3730 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3731
3732 /*
3733 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3734 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3735 * length.
3736 */
3737 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3738 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3739 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3740 else
3741 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3742
3743 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3744 }
3745
3746 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3747}
3748
3749
3750/**
3751 * VMX VM-exit handler for APIC accesses.
3752 *
3753 * @param pVCpu The cross context virtual CPU structure.
3754 * @param offAccess The offset of the register being accessed.
3755 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3756 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3757 */
3758IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3759{
3760 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3761
3762 VMXAPICACCESS enmAccess;
3763 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3764 if (fInEventDelivery)
3765 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3766 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3767 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3768 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3769 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3770 else
3771 enmAccess = VMXAPICACCESS_LINEAR_READ;
3772
3773 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3774 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3775 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3776}
3777
3778
3779/**
3780 * VMX VM-exit handler for APIC accesses.
3781 *
3782 * This is intended for APIC accesses where the caller provides all the
3783 * relevant VM-exit information.
3784 *
3785 * @returns VBox strict status code.
3786 * @param pVCpu The cross context virtual CPU structure.
3787 * @param pExitInfo Pointer to the VM-exit information.
3788 * @param pExitEventInfo Pointer to the VM-exit event information.
3789 */
3790IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3791 PCVMXVEXITEVENTINFO pExitEventInfo)
3792{
3793 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3794 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3795 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3796 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3797 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3798 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3799 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3800 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3801 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3802}
3803
3804
3805/**
3806 * VMX VM-exit handler for APIC-write VM-exits.
3807 *
3808 * @param pVCpu The cross context virtual CPU structure.
3809 * @param offApic The write to the virtual-APIC page offset that caused this
3810 * VM-exit.
3811 */
3812IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3813{
3814 Assert(offApic < XAPIC_OFF_END + 4);
3815 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3816 offApic &= UINT16_C(0xfff);
3817 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3818}
3819
3820
3821/**
3822 * Sets virtual-APIC write emulation as pending.
3823 *
3824 * @param pVCpu The cross context virtual CPU structure.
3825 * @param offApic The offset in the virtual-APIC page that was written.
3826 */
3827DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3828{
3829 Assert(offApic < XAPIC_OFF_END + 4);
3830
3831 /*
3832 * Record the currently updated APIC offset, as we need this later for figuring
3833 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3834 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3835 */
3836 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3837
3838 /*
3839 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3840 * virtualization or APIC-write emulation).
3841 */
3842 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3843 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3844}
3845
3846
3847/**
3848 * Clears any pending virtual-APIC write emulation.
3849 *
3850 * @returns The virtual-APIC offset that was written before clearing it.
3851 * @param pVCpu The cross context virtual CPU structure.
3852 */
3853DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3854{
3855 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3856 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3857 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3858 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3859 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3860 return offVirtApicWrite;
3861}
3862
3863
3864/**
3865 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3866 *
3867 * @returns The register from the virtual-APIC page.
3868 * @param pVCpu The cross context virtual CPU structure.
3869 * @param offReg The offset of the register being read.
3870 */
3871IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3872{
3873 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3874 Assert(pVmcs);
3875 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3876
3877 uint32_t uReg;
3878 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3879 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3880 if (RT_SUCCESS(rc))
3881 { /* likely */ }
3882 else
3883 {
3884 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3885 GCPhysVirtApic));
3886 uReg = 0;
3887 }
3888 return uReg;
3889}
3890
3891
3892/**
3893 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3894 *
3895 * @returns The register from the virtual-APIC page.
3896 * @param pVCpu The cross context virtual CPU structure.
3897 * @param offReg The offset of the register being read.
3898 */
3899IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3900{
3901 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3902 Assert(pVmcs);
3903 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3904
3905 uint64_t uReg;
3906 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3907 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3908 if (RT_SUCCESS(rc))
3909 { /* likely */ }
3910 else
3911 {
3912 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3913 GCPhysVirtApic));
3914 uReg = 0;
3915 }
3916 return uReg;
3917}
3918
3919
3920/**
3921 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3922 *
3923 * @param pVCpu The cross context virtual CPU structure.
3924 * @param offReg The offset of the register being written.
3925 * @param uReg The register value to write.
3926 */
3927IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3928{
3929 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3930 Assert(pVmcs);
3931 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3932
3933 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3934 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3935 if (RT_SUCCESS(rc))
3936 { /* likely */ }
3937 else
3938 {
3939 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3940 GCPhysVirtApic));
3941 }
3942}
3943
3944
3945/**
3946 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3947 *
3948 * @param pVCpu The cross context virtual CPU structure.
3949 * @param offReg The offset of the register being written.
3950 * @param uReg The register value to write.
3951 */
3952IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3953{
3954 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3955 Assert(pVmcs);
3956 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3957
3958 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3959 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3960 if (RT_SUCCESS(rc))
3961 { /* likely */ }
3962 else
3963 {
3964 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3965 GCPhysVirtApic));
3966 }
3967}
3968
3969
3970/**
3971 * Sets the vector in a virtual-APIC 256-bit sparse register.
3972 *
3973 * @param pVCpu The cross context virtual CPU structure.
3974 * @param offReg The offset of the 256-bit spare register.
3975 * @param uVector The vector to set.
3976 *
3977 * @remarks This is based on our APIC device code.
3978 */
3979IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3980{
3981 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3982 Assert(pVmcs);
3983
3984 /* Determine the vector offset within the chunk. */
3985 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3986
3987 /* Read the chunk at the offset. */
3988 uint32_t uReg;
3989 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3990 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3991 if (RT_SUCCESS(rc))
3992 {
3993 /* Modify the chunk. */
3994 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3995 uReg |= RT_BIT(idxVectorBit);
3996
3997 /* Write the chunk. */
3998 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3999 if (RT_SUCCESS(rc))
4000 { /* likely */ }
4001 else
4002 {
4003 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4004 uVector, offReg, GCPhysVirtApic));
4005 }
4006 }
4007 else
4008 {
4009 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4010 uVector, offReg, GCPhysVirtApic));
4011 }
4012}
4013
4014
4015/**
4016 * Clears the vector in a virtual-APIC 256-bit sparse register.
4017 *
4018 * @param pVCpu The cross context virtual CPU structure.
4019 * @param offReg The offset of the 256-bit spare register.
4020 * @param uVector The vector to clear.
4021 *
4022 * @remarks This is based on our APIC device code.
4023 */
4024IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4025{
4026 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4027 Assert(pVmcs);
4028
4029 /* Determine the vector offset within the chunk. */
4030 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4031
4032 /* Read the chunk at the offset. */
4033 uint32_t uReg;
4034 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4035 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4036 if (RT_SUCCESS(rc))
4037 {
4038 /* Modify the chunk. */
4039 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4040 uReg &= ~RT_BIT(idxVectorBit);
4041
4042 /* Write the chunk. */
4043 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4044 if (RT_SUCCESS(rc))
4045 { /* likely */ }
4046 else
4047 {
4048 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4049 uVector, offReg, GCPhysVirtApic));
4050 }
4051 }
4052 else
4053 {
4054 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4055 uVector, offReg, GCPhysVirtApic));
4056 }
4057}
4058
4059
4060/**
4061 * Checks if a memory access to the APIC-access page must causes an APIC-access
4062 * VM-exit.
4063 *
4064 * @param pVCpu The cross context virtual CPU structure.
4065 * @param offAccess The offset of the register being accessed.
4066 * @param cbAccess The size of the access in bytes.
4067 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4068 * IEM_ACCESS_TYPE_WRITE).
4069 *
4070 * @remarks This must not be used for MSR-based APIC-access page accesses!
4071 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4072 */
4073IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4074{
4075 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4076 Assert(pVmcs);
4077 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4078
4079 /*
4080 * We must cause a VM-exit if any of the following are true:
4081 * - TPR shadowing isn't active.
4082 * - The access size exceeds 32-bits.
4083 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4084 *
4085 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4086 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4087 */
4088 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4089 || cbAccess > sizeof(uint32_t)
4090 || ((offAccess + cbAccess - 1) & 0xc)
4091 || offAccess >= XAPIC_OFF_END + 4)
4092 return true;
4093
4094 /*
4095 * If the access is part of an operation where we have already
4096 * virtualized a virtual-APIC write, we must cause a VM-exit.
4097 */
4098 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4099 return true;
4100
4101 /*
4102 * Check write accesses to the APIC-access page that cause VM-exits.
4103 */
4104 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4105 {
4106 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4107 {
4108 /*
4109 * With APIC-register virtualization, a write access to any of the
4110 * following registers are virtualized. Accessing any other register
4111 * causes a VM-exit.
4112 */
4113 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4114 switch (offAlignedAccess)
4115 {
4116 case XAPIC_OFF_ID:
4117 case XAPIC_OFF_TPR:
4118 case XAPIC_OFF_EOI:
4119 case XAPIC_OFF_LDR:
4120 case XAPIC_OFF_DFR:
4121 case XAPIC_OFF_SVR:
4122 case XAPIC_OFF_ESR:
4123 case XAPIC_OFF_ICR_LO:
4124 case XAPIC_OFF_ICR_HI:
4125 case XAPIC_OFF_LVT_TIMER:
4126 case XAPIC_OFF_LVT_THERMAL:
4127 case XAPIC_OFF_LVT_PERF:
4128 case XAPIC_OFF_LVT_LINT0:
4129 case XAPIC_OFF_LVT_LINT1:
4130 case XAPIC_OFF_LVT_ERROR:
4131 case XAPIC_OFF_TIMER_ICR:
4132 case XAPIC_OFF_TIMER_DCR:
4133 break;
4134 default:
4135 return true;
4136 }
4137 }
4138 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4139 {
4140 /*
4141 * With virtual-interrupt delivery, a write access to any of the
4142 * following registers are virtualized. Accessing any other register
4143 * causes a VM-exit.
4144 *
4145 * Note! The specification does not allow writing to offsets in-between
4146 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4147 */
4148 switch (offAccess)
4149 {
4150 case XAPIC_OFF_TPR:
4151 case XAPIC_OFF_EOI:
4152 case XAPIC_OFF_ICR_LO:
4153 break;
4154 default:
4155 return true;
4156 }
4157 }
4158 else
4159 {
4160 /*
4161 * Without APIC-register virtualization or virtual-interrupt delivery,
4162 * only TPR accesses are virtualized.
4163 */
4164 if (offAccess == XAPIC_OFF_TPR)
4165 { /* likely */ }
4166 else
4167 return true;
4168 }
4169 }
4170 else
4171 {
4172 /*
4173 * Check read accesses to the APIC-access page that cause VM-exits.
4174 */
4175 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4176 {
4177 /*
4178 * With APIC-register virtualization, a read access to any of the
4179 * following registers are virtualized. Accessing any other register
4180 * causes a VM-exit.
4181 */
4182 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4183 switch (offAlignedAccess)
4184 {
4185 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4186 case XAPIC_OFF_ID:
4187 case XAPIC_OFF_VERSION:
4188 case XAPIC_OFF_TPR:
4189 case XAPIC_OFF_EOI:
4190 case XAPIC_OFF_LDR:
4191 case XAPIC_OFF_DFR:
4192 case XAPIC_OFF_SVR:
4193 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4194 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4195 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4196 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4197 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4198 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4199 case XAPIC_OFF_ESR:
4200 case XAPIC_OFF_ICR_LO:
4201 case XAPIC_OFF_ICR_HI:
4202 case XAPIC_OFF_LVT_TIMER:
4203 case XAPIC_OFF_LVT_THERMAL:
4204 case XAPIC_OFF_LVT_PERF:
4205 case XAPIC_OFF_LVT_LINT0:
4206 case XAPIC_OFF_LVT_LINT1:
4207 case XAPIC_OFF_LVT_ERROR:
4208 case XAPIC_OFF_TIMER_ICR:
4209 case XAPIC_OFF_TIMER_DCR:
4210 break;
4211 default:
4212 return true;
4213 }
4214 }
4215 else
4216 {
4217 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4218 if (offAccess == XAPIC_OFF_TPR)
4219 { /* likely */ }
4220 else
4221 return true;
4222 }
4223 }
4224
4225 /* The APIC access is virtualized, does not cause a VM-exit. */
4226 return false;
4227}
4228
4229
4230/**
4231 * Virtualizes a memory-based APIC access where the address is not used to access
4232 * memory.
4233 *
4234 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4235 * page-faults but do not use the address to access memory.
4236 *
4237 * @param pVCpu The cross context virtual CPU structure.
4238 * @param pGCPhysAccess Pointer to the guest-physical address used.
4239 */
4240IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4241{
4242 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4243 Assert(pVmcs);
4244 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4245 Assert(pGCPhysAccess);
4246
4247 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4248 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4249 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4250
4251 if (GCPhysAccess == GCPhysApic)
4252 {
4253 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4254 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4255 uint16_t const cbAccess = 1;
4256 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4257 if (fIntercept)
4258 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4259
4260 *pGCPhysAccess = GCPhysApic | offAccess;
4261 return VINF_VMX_MODIFIES_BEHAVIOR;
4262 }
4263
4264 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4265}
4266
4267
4268/**
4269 * Virtualizes a memory-based APIC access.
4270 *
4271 * @returns VBox strict status code.
4272 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4273 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4274 *
4275 * @param pVCpu The cross context virtual CPU structure.
4276 * @param offAccess The offset of the register being accessed (within the
4277 * APIC-access page).
4278 * @param cbAccess The size of the access in bytes.
4279 * @param pvData Pointer to the data being written or where to store the data
4280 * being read.
4281 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4282 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4283 */
4284IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4285 uint32_t fAccess)
4286{
4287 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4288 Assert(pVmcs);
4289 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4290 Assert(pvData);
4291 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4292 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4293 || (fAccess & IEM_ACCESS_INSTRUCTION));
4294
4295 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4296 if (fIntercept)
4297 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4298
4299 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4300 {
4301 /*
4302 * A write access to the APIC-access page that is virtualized (rather than
4303 * causing a VM-exit) writes data to the virtual-APIC page.
4304 */
4305 uint32_t const u32Data = *(uint32_t *)pvData;
4306 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4307
4308 /*
4309 * Record the currently updated APIC offset, as we need this later for figuring
4310 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4311 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4312 *
4313 * After completion of the current operation, we need to perform TPR virtualization,
4314 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4315 *
4316 * The current operation may be a REP-prefixed string instruction, execution of any
4317 * other instruction, or delivery of an event through the IDT.
4318 *
4319 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4320 * performed now but later after completion of the current operation.
4321 *
4322 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4323 */
4324 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4325 }
4326 else
4327 {
4328 /*
4329 * A read access from the APIC-access page that is virtualized (rather than
4330 * causing a VM-exit) returns data from the virtual-APIC page.
4331 *
4332 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4333 */
4334 Assert(cbAccess <= 4);
4335 Assert(offAccess < XAPIC_OFF_END + 4);
4336 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4337
4338 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4339 u32Data &= s_auAccessSizeMasks[cbAccess];
4340 *(uint32_t *)pvData = u32Data;
4341 }
4342
4343 return VINF_VMX_MODIFIES_BEHAVIOR;
4344}
4345
4346
4347/**
4348 * Virtualizes an MSR-based APIC read access.
4349 *
4350 * @returns VBox strict status code.
4351 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4352 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4353 * handled by the x2APIC device.
4354 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4355 * not within the range of valid MSRs, caller must raise \#GP(0).
4356 * @param pVCpu The cross context virtual CPU structure.
4357 * @param idMsr The x2APIC MSR being read.
4358 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4359 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4360 */
4361IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4362{
4363 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4364 Assert(pVmcs);
4365 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4366 Assert(pu64Value);
4367
4368 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4369 {
4370 /*
4371 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4372 * what the end of the valid x2APIC MSR range is. Hence the use of different
4373 * macros here.
4374 *
4375 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4376 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4377 */
4378 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4379 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4380 {
4381 uint16_t const offReg = (idMsr & 0xff) << 4;
4382 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4383 *pu64Value = u64Value;
4384 return VINF_VMX_MODIFIES_BEHAVIOR;
4385 }
4386 return VERR_OUT_OF_RANGE;
4387 }
4388
4389 if (idMsr == MSR_IA32_X2APIC_TPR)
4390 {
4391 uint16_t const offReg = (idMsr & 0xff) << 4;
4392 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4393 *pu64Value = u64Value;
4394 return VINF_VMX_MODIFIES_BEHAVIOR;
4395 }
4396
4397 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4398}
4399
4400
4401/**
4402 * Virtualizes an MSR-based APIC write access.
4403 *
4404 * @returns VBox strict status code.
4405 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4406 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4407 * not within the range of valid MSRs, caller must raise \#GP(0).
4408 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4409 *
4410 * @param pVCpu The cross context virtual CPU structure.
4411 * @param idMsr The x2APIC MSR being written.
4412 * @param u64Value The value of the x2APIC MSR being written.
4413 */
4414IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4415{
4416 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4417 Assert(pVmcs);
4418
4419 /*
4420 * Check if the access is to be virtualized.
4421 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4422 */
4423 if ( idMsr == MSR_IA32_X2APIC_TPR
4424 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4425 && ( idMsr == MSR_IA32_X2APIC_EOI
4426 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4427 {
4428 /* Validate the MSR write depending on the register. */
4429 switch (idMsr)
4430 {
4431 case MSR_IA32_X2APIC_TPR:
4432 case MSR_IA32_X2APIC_SELF_IPI:
4433 {
4434 if (u64Value & UINT64_C(0xffffffffffffff00))
4435 return VERR_OUT_OF_RANGE;
4436 break;
4437 }
4438 case MSR_IA32_X2APIC_EOI:
4439 {
4440 if (u64Value != 0)
4441 return VERR_OUT_OF_RANGE;
4442 break;
4443 }
4444 }
4445
4446 /* Write the MSR to the virtual-APIC page. */
4447 uint16_t const offReg = (idMsr & 0xff) << 4;
4448 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4449
4450 /*
4451 * Record the currently updated APIC offset, as we need this later for figuring
4452 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4453 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4454 */
4455 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4456
4457 return VINF_VMX_MODIFIES_BEHAVIOR;
4458 }
4459
4460 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4461}
4462
4463
4464/**
4465 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4466 *
4467 * @returns VBox status code.
4468 * @retval VINF_SUCCESS when the highest set bit is found.
4469 * @retval VERR_NOT_FOUND when no bit is set.
4470 *
4471 * @param pVCpu The cross context virtual CPU structure.
4472 * @param offReg The offset of the APIC 256-bit sparse register.
4473 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4474 * set in the register. Only valid when VINF_SUCCESS is
4475 * returned.
4476 *
4477 * @remarks The format of the 256-bit sparse register here mirrors that found in
4478 * real APIC hardware.
4479 */
4480static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4481{
4482 Assert(offReg < XAPIC_OFF_END + 4);
4483 Assert(pidxHighestBit);
4484 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4485
4486 /*
4487 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4488 * However, in each fragment only the first 4 bytes are used.
4489 */
4490 uint8_t const cFrags = 8;
4491 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4492 {
4493 uint16_t const offFrag = iFrag * 16;
4494 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4495 if (!u32Frag)
4496 continue;
4497
4498 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4499 Assert(idxHighestBit > 0);
4500 --idxHighestBit;
4501 Assert(idxHighestBit <= UINT8_MAX);
4502 *pidxHighestBit = idxHighestBit;
4503 return VINF_SUCCESS;
4504 }
4505 return VERR_NOT_FOUND;
4506}
4507
4508
4509/**
4510 * Evaluates pending virtual interrupts.
4511 *
4512 * @param pVCpu The cross context virtual CPU structure.
4513 */
4514IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4515{
4516 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4517 Assert(pVmcs);
4518 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4519
4520 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4521 {
4522 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4523 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4524
4525 if ((uRvi >> 4) > (uPpr >> 4))
4526 {
4527 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4528 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4529 }
4530 else
4531 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4532 }
4533}
4534
4535
4536/**
4537 * Performs PPR virtualization.
4538 *
4539 * @returns VBox strict status code.
4540 * @param pVCpu The cross context virtual CPU structure.
4541 */
4542IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4543{
4544 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4545 Assert(pVmcs);
4546 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4547 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4548
4549 /*
4550 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4551 * or EOI-virtualization.
4552 *
4553 * See Intel spec. 29.1.3 "PPR Virtualization".
4554 */
4555 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4556 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4557
4558 uint32_t uPpr;
4559 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4560 uPpr = uTpr & 0xff;
4561 else
4562 uPpr = uSvi & 0xf0;
4563
4564 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4565 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4566}
4567
4568
4569/**
4570 * Performs VMX TPR virtualization.
4571 *
4572 * @returns VBox strict status code.
4573 * @param pVCpu The cross context virtual CPU structure.
4574 */
4575IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4576{
4577 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4578 Assert(pVmcs);
4579 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4580
4581 /*
4582 * We should have already performed the virtual-APIC write to the TPR offset
4583 * in the virtual-APIC page. We now perform TPR virtualization.
4584 *
4585 * See Intel spec. 29.1.2 "TPR Virtualization".
4586 */
4587 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4588 {
4589 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4590 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4591
4592 /*
4593 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4594 * See Intel spec. 29.1.2 "TPR Virtualization".
4595 */
4596 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4597 {
4598 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4599 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4600 }
4601 }
4602 else
4603 {
4604 iemVmxPprVirtualization(pVCpu);
4605 iemVmxEvalPendingVirtIntrs(pVCpu);
4606 }
4607
4608 return VINF_SUCCESS;
4609}
4610
4611
4612/**
4613 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4614 * not.
4615 *
4616 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4617 * @param pVCpu The cross context virtual CPU structure.
4618 * @param uVector The interrupt that was acknowledged using an EOI.
4619 */
4620IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4621{
4622 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4623 Assert(pVmcs);
4624 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4625
4626 if (uVector < 64)
4627 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4628 if (uVector < 128)
4629 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4630 if (uVector < 192)
4631 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4632 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4633}
4634
4635
4636/**
4637 * Performs EOI virtualization.
4638 *
4639 * @returns VBox strict status code.
4640 * @param pVCpu The cross context virtual CPU structure.
4641 */
4642IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4643{
4644 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4645 Assert(pVmcs);
4646 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4647
4648 /*
4649 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4650 * and get the next guest-interrupt that's in-service (if any).
4651 *
4652 * See Intel spec. 29.1.4 "EOI Virtualization".
4653 */
4654 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4655 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4656 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4657
4658 uint8_t uVector = uSvi;
4659 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4660
4661 uVector = 0;
4662 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4663
4664 if (uVector)
4665 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4666 else
4667 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4668
4669 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4670 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4671
4672 iemVmxPprVirtualization(pVCpu);
4673 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4674 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4675 iemVmxEvalPendingVirtIntrs(pVCpu);
4676 return VINF_SUCCESS;
4677}
4678
4679
4680/**
4681 * Performs self-IPI virtualization.
4682 *
4683 * @returns VBox strict status code.
4684 * @param pVCpu The cross context virtual CPU structure.
4685 */
4686IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4687{
4688 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4689 Assert(pVmcs);
4690 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4691
4692 /*
4693 * We should have already performed the virtual-APIC write to the self-IPI offset
4694 * in the virtual-APIC page. We now perform self-IPI virtualization.
4695 *
4696 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4697 */
4698 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4699 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4700 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4701 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4702 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4703 if (uVector > uRvi)
4704 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4705 iemVmxEvalPendingVirtIntrs(pVCpu);
4706 return VINF_SUCCESS;
4707}
4708
4709
4710/**
4711 * Performs VMX APIC-write emulation.
4712 *
4713 * @returns VBox strict status code.
4714 * @param pVCpu The cross context virtual CPU structure.
4715 */
4716IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4717{
4718 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4719 Assert(pVmcs);
4720
4721 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4722 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4723
4724 /*
4725 * Perform APIC-write emulation based on the virtual-APIC register written.
4726 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4727 */
4728 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4729 VBOXSTRICTRC rcStrict;
4730 switch (offApicWrite)
4731 {
4732 case XAPIC_OFF_TPR:
4733 {
4734 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4735 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4736 uTpr &= UINT32_C(0x000000ff);
4737 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4738 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4739 rcStrict = iemVmxTprVirtualization(pVCpu);
4740 break;
4741 }
4742
4743 case XAPIC_OFF_EOI:
4744 {
4745 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4746 {
4747 /* Clear VEOI and perform EOI virtualization. */
4748 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4749 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4750 rcStrict = iemVmxEoiVirtualization(pVCpu);
4751 }
4752 else
4753 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4754 break;
4755 }
4756
4757 case XAPIC_OFF_ICR_LO:
4758 {
4759 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4760 {
4761 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4762 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4763 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4764 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4765 if ( !(uIcrLo & fIcrLoMb0)
4766 && (uIcrLo & fIcrLoMb1))
4767 {
4768 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4769 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4770 }
4771 else
4772 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4773 }
4774 else
4775 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4776 break;
4777 }
4778
4779 case XAPIC_OFF_ICR_HI:
4780 {
4781 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4782 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4783 uIcrHi &= UINT32_C(0xff000000);
4784 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4785 rcStrict = VINF_SUCCESS;
4786 break;
4787 }
4788
4789 default:
4790 {
4791 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4792 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4793 break;
4794 }
4795 }
4796
4797 return rcStrict;
4798}
4799
4800
4801/**
4802 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4803 *
4804 * @param pVCpu The cross context virtual CPU structure.
4805 * @param pszInstr The VMX instruction name (for logging purposes).
4806 */
4807DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4808{
4809 /*
4810 * Guest Control Registers, Debug Registers, and MSRs.
4811 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4812 */
4813 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4814 const char *const pszFailure = "VM-exit";
4815 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4816
4817 /* CR0 reserved bits. */
4818 {
4819 /* CR0 MB1 bits. */
4820 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4821 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4822 if (fUnrestrictedGuest)
4823 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4824 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4825 { /* likely */ }
4826 else
4827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4828
4829 /* CR0 MBZ bits. */
4830 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4831 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4832 { /* likely */ }
4833 else
4834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4835
4836 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4837 if ( !fUnrestrictedGuest
4838 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4839 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4841 }
4842
4843 /* CR4 reserved bits. */
4844 {
4845 /* CR4 MB1 bits. */
4846 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4847 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4848 { /* likely */ }
4849 else
4850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4851
4852 /* CR4 MBZ bits. */
4853 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4854 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4855 { /* likely */ }
4856 else
4857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4858 }
4859
4860 /* DEBUGCTL MSR. */
4861 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4862 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4863 { /* likely */ }
4864 else
4865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4866
4867 /* 64-bit CPU checks. */
4868 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4869 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4870 {
4871 if (fGstInLongMode)
4872 {
4873 /* PAE must be set. */
4874 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4875 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4876 { /* likely */ }
4877 else
4878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4879 }
4880 else
4881 {
4882 /* PCIDE should not be set. */
4883 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4884 { /* likely */ }
4885 else
4886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4887 }
4888
4889 /* CR3. */
4890 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4891 { /* likely */ }
4892 else
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4894
4895 /* DR7. */
4896 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4897 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4898 { /* likely */ }
4899 else
4900 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4901
4902 /* SYSENTER ESP and SYSENTER EIP. */
4903 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4904 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4905 { /* likely */ }
4906 else
4907 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4908 }
4909
4910 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4911 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4912
4913 /* PAT MSR. */
4914 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4915 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4916 { /* likely */ }
4917 else
4918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4919
4920 /* EFER MSR. */
4921 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4922 {
4923 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4924 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4925 { /* likely */ }
4926 else
4927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4928
4929 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4930 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4931 if ( fGstLma == fGstInLongMode
4932 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4933 || fGstLma == fGstLme))
4934 { /* likely */ }
4935 else
4936 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4937 }
4938
4939 /* We don't support IA32_BNDCFGS MSR yet. */
4940 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4941
4942 NOREF(pszInstr);
4943 NOREF(pszFailure);
4944 return VINF_SUCCESS;
4945}
4946
4947
4948/**
4949 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4950 *
4951 * @param pVCpu The cross context virtual CPU structure.
4952 * @param pszInstr The VMX instruction name (for logging purposes).
4953 */
4954DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4955{
4956 /*
4957 * Segment registers.
4958 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4959 */
4960 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4961 const char *const pszFailure = "VM-exit";
4962 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4963 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4964 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4965
4966 /* Selectors. */
4967 if ( !fGstInV86Mode
4968 && !fUnrestrictedGuest
4969 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4971
4972 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4973 {
4974 CPUMSELREG SelReg;
4975 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4976 if (RT_LIKELY(rc == VINF_SUCCESS))
4977 { /* likely */ }
4978 else
4979 return rc;
4980
4981 /*
4982 * Virtual-8086 mode checks.
4983 */
4984 if (fGstInV86Mode)
4985 {
4986 /* Base address. */
4987 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4988 { /* likely */ }
4989 else
4990 {
4991 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4993 }
4994
4995 /* Limit. */
4996 if (SelReg.u32Limit == 0xffff)
4997 { /* likely */ }
4998 else
4999 {
5000 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5001 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5002 }
5003
5004 /* Attribute. */
5005 if (SelReg.Attr.u == 0xf3)
5006 { /* likely */ }
5007 else
5008 {
5009 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5011 }
5012
5013 /* We're done; move to checking the next segment. */
5014 continue;
5015 }
5016
5017 /* Checks done by 64-bit CPUs. */
5018 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5019 {
5020 /* Base address. */
5021 if ( iSegReg == X86_SREG_FS
5022 || iSegReg == X86_SREG_GS)
5023 {
5024 if (X86_IS_CANONICAL(SelReg.u64Base))
5025 { /* likely */ }
5026 else
5027 {
5028 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5030 }
5031 }
5032 else if (iSegReg == X86_SREG_CS)
5033 {
5034 if (!RT_HI_U32(SelReg.u64Base))
5035 { /* likely */ }
5036 else
5037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5038 }
5039 else
5040 {
5041 if ( SelReg.Attr.n.u1Unusable
5042 || !RT_HI_U32(SelReg.u64Base))
5043 { /* likely */ }
5044 else
5045 {
5046 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5048 }
5049 }
5050 }
5051
5052 /*
5053 * Checks outside Virtual-8086 mode.
5054 */
5055 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5056 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5057 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5058 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5059 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5060 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5061 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5062 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5063
5064 /* Code or usable segment. */
5065 if ( iSegReg == X86_SREG_CS
5066 || fUsable)
5067 {
5068 /* Reserved bits (bits 31:17 and bits 11:8). */
5069 if (!(SelReg.Attr.u & 0xfffe0f00))
5070 { /* likely */ }
5071 else
5072 {
5073 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5074 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5075 }
5076
5077 /* Descriptor type. */
5078 if (fCodeDataSeg)
5079 { /* likely */ }
5080 else
5081 {
5082 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5083 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5084 }
5085
5086 /* Present. */
5087 if (fPresent)
5088 { /* likely */ }
5089 else
5090 {
5091 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5093 }
5094
5095 /* Granularity. */
5096 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5097 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5098 { /* likely */ }
5099 else
5100 {
5101 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5103 }
5104 }
5105
5106 if (iSegReg == X86_SREG_CS)
5107 {
5108 /* Segment Type and DPL. */
5109 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5110 && fUnrestrictedGuest)
5111 {
5112 if (uDpl == 0)
5113 { /* likely */ }
5114 else
5115 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5116 }
5117 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5118 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5119 {
5120 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5121 if (uDpl == AttrSs.n.u2Dpl)
5122 { /* likely */ }
5123 else
5124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5125 }
5126 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5127 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5128 {
5129 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5130 if (uDpl <= AttrSs.n.u2Dpl)
5131 { /* likely */ }
5132 else
5133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5134 }
5135 else
5136 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5137
5138 /* Def/Big. */
5139 if ( fGstInLongMode
5140 && fSegLong)
5141 {
5142 if (uDefBig == 0)
5143 { /* likely */ }
5144 else
5145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5146 }
5147 }
5148 else if (iSegReg == X86_SREG_SS)
5149 {
5150 /* Segment Type. */
5151 if ( !fUsable
5152 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5153 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5154 { /* likely */ }
5155 else
5156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5157
5158 /* DPL. */
5159 if (!fUnrestrictedGuest)
5160 {
5161 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5165 }
5166 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5167 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5168 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5169 {
5170 if (uDpl == 0)
5171 { /* likely */ }
5172 else
5173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5174 }
5175 }
5176 else
5177 {
5178 /* DS, ES, FS, GS. */
5179 if (fUsable)
5180 {
5181 /* Segment type. */
5182 if (uSegType & X86_SEL_TYPE_ACCESSED)
5183 { /* likely */ }
5184 else
5185 {
5186 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5188 }
5189
5190 if ( !(uSegType & X86_SEL_TYPE_CODE)
5191 || (uSegType & X86_SEL_TYPE_READ))
5192 { /* likely */ }
5193 else
5194 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5195
5196 /* DPL. */
5197 if ( !fUnrestrictedGuest
5198 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5199 {
5200 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5201 { /* likely */ }
5202 else
5203 {
5204 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5206 }
5207 }
5208 }
5209 }
5210 }
5211
5212 /*
5213 * LDTR.
5214 */
5215 {
5216 CPUMSELREG Ldtr;
5217 Ldtr.Sel = pVmcs->GuestLdtr;
5218 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5219 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5220 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5221
5222 if (!Ldtr.Attr.n.u1Unusable)
5223 {
5224 /* Selector. */
5225 if (!(Ldtr.Sel & X86_SEL_LDT))
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5229
5230 /* Base. */
5231 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5232 {
5233 if (X86_IS_CANONICAL(Ldtr.u64Base))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5237 }
5238
5239 /* Attributes. */
5240 /* Reserved bits (bits 31:17 and bits 11:8). */
5241 if (!(Ldtr.Attr.u & 0xfffe0f00))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5245
5246 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5247 { /* likely */ }
5248 else
5249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5250
5251 if (!Ldtr.Attr.n.u1DescType)
5252 { /* likely */ }
5253 else
5254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5255
5256 if (Ldtr.Attr.n.u1Present)
5257 { /* likely */ }
5258 else
5259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5260
5261 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5262 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5263 { /* likely */ }
5264 else
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5266 }
5267 }
5268
5269 /*
5270 * TR.
5271 */
5272 {
5273 CPUMSELREG Tr;
5274 Tr.Sel = pVmcs->GuestTr;
5275 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5276 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5277 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5278
5279 /* Selector. */
5280 if (!(Tr.Sel & X86_SEL_LDT))
5281 { /* likely */ }
5282 else
5283 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5284
5285 /* Base. */
5286 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5287 {
5288 if (X86_IS_CANONICAL(Tr.u64Base))
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5292 }
5293
5294 /* Attributes. */
5295 /* Reserved bits (bits 31:17 and bits 11:8). */
5296 if (!(Tr.Attr.u & 0xfffe0f00))
5297 { /* likely */ }
5298 else
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5300
5301 if (!Tr.Attr.n.u1Unusable)
5302 { /* likely */ }
5303 else
5304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5305
5306 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5307 || ( !fGstInLongMode
5308 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5309 { /* likely */ }
5310 else
5311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5312
5313 if (!Tr.Attr.n.u1DescType)
5314 { /* likely */ }
5315 else
5316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5317
5318 if (Tr.Attr.n.u1Present)
5319 { /* likely */ }
5320 else
5321 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5322
5323 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5324 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5325 { /* likely */ }
5326 else
5327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5328 }
5329
5330 NOREF(pszInstr);
5331 NOREF(pszFailure);
5332 return VINF_SUCCESS;
5333}
5334
5335
5336/**
5337 * Checks guest GDTR and IDTR as part of VM-entry.
5338 *
5339 * @param pVCpu The cross context virtual CPU structure.
5340 * @param pszInstr The VMX instruction name (for logging purposes).
5341 */
5342DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5343{
5344 /*
5345 * GDTR and IDTR.
5346 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5347 */
5348 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5349 const char *const pszFailure = "VM-exit";
5350
5351 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5352 {
5353 /* Base. */
5354 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5355 { /* likely */ }
5356 else
5357 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5358
5359 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5360 { /* likely */ }
5361 else
5362 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5363 }
5364
5365 /* Limit. */
5366 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5367 { /* likely */ }
5368 else
5369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5370
5371 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5372 { /* likely */ }
5373 else
5374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5375
5376 NOREF(pszInstr);
5377 NOREF(pszFailure);
5378 return VINF_SUCCESS;
5379}
5380
5381
5382/**
5383 * Checks guest RIP and RFLAGS as part of VM-entry.
5384 *
5385 * @param pVCpu The cross context virtual CPU structure.
5386 * @param pszInstr The VMX instruction name (for logging purposes).
5387 */
5388DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5389{
5390 /*
5391 * RIP and RFLAGS.
5392 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5393 */
5394 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5395 const char *const pszFailure = "VM-exit";
5396 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5397
5398 /* RIP. */
5399 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5400 {
5401 X86DESCATTR AttrCs;
5402 AttrCs.u = pVmcs->u32GuestCsAttr;
5403 if ( !fGstInLongMode
5404 || !AttrCs.n.u1Long)
5405 {
5406 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5407 { /* likely */ }
5408 else
5409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5410 }
5411
5412 if ( fGstInLongMode
5413 && AttrCs.n.u1Long)
5414 {
5415 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5416 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5417 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5418 { /* likely */ }
5419 else
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5421 }
5422 }
5423
5424 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5425 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5426 : pVmcs->u64GuestRFlags.s.Lo;
5427 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5428 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5429 { /* likely */ }
5430 else
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5432
5433 if ( fGstInLongMode
5434 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5435 {
5436 if (!(uGuestRFlags & X86_EFL_VM))
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5440 }
5441
5442 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5443 {
5444 if (uGuestRFlags & X86_EFL_IF)
5445 { /* likely */ }
5446 else
5447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5448 }
5449
5450 NOREF(pszInstr);
5451 NOREF(pszFailure);
5452 return VINF_SUCCESS;
5453}
5454
5455
5456/**
5457 * Checks guest non-register state as part of VM-entry.
5458 *
5459 * @param pVCpu The cross context virtual CPU structure.
5460 * @param pszInstr The VMX instruction name (for logging purposes).
5461 */
5462DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5463{
5464 /*
5465 * Guest non-register state.
5466 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5467 */
5468 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5469 const char *const pszFailure = "VM-exit";
5470
5471 /*
5472 * Activity state.
5473 */
5474 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5475 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5476 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5477 { /* likely */ }
5478 else
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5480
5481 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5482 if ( !AttrSs.n.u2Dpl
5483 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5484 { /* likely */ }
5485 else
5486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5487
5488 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5489 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5490 {
5491 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5495 }
5496
5497 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5498 {
5499 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5500 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5501 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5502 switch (pVmcs->u32GuestActivityState)
5503 {
5504 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5505 {
5506 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5507 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5508 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5509 && ( uVector == X86_XCPT_DB
5510 || uVector == X86_XCPT_MC))
5511 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5512 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5513 { /* likely */ }
5514 else
5515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5516 break;
5517 }
5518
5519 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5520 {
5521 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5522 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5523 && uVector == X86_XCPT_MC))
5524 { /* likely */ }
5525 else
5526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5527 break;
5528 }
5529
5530 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5531 default:
5532 break;
5533 }
5534 }
5535
5536 /*
5537 * Interruptibility state.
5538 */
5539 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5540 { /* likely */ }
5541 else
5542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5543
5544 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5545 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5549
5550 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5551 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5552 { /* likely */ }
5553 else
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5555
5556 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5557 {
5558 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5559 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5560 {
5561 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5562 { /* likely */ }
5563 else
5564 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5565 }
5566 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5567 {
5568 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5569 { /* likely */ }
5570 else
5571 {
5572 /*
5573 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5574 * We update the Exit qualification only when blocking-by-STI is set
5575 * without blocking-by-MovSS being set. Although in practise it does not
5576 * make much difference since the order of checks are implementation defined.
5577 */
5578 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5579 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5581 }
5582
5583 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5584 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5588 }
5589 }
5590
5591 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5592 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5596
5597 /* We don't support SGX yet. So enclave-interruption must not be set. */
5598 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5599 { /* likely */ }
5600 else
5601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5602
5603 /*
5604 * Pending debug exceptions.
5605 */
5606 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5607 ? pVmcs->u64GuestPendingDbgXcpts.u
5608 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5609 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5610 { /* likely */ }
5611 else
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5613
5614 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5615 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5616 {
5617 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5618 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5619 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5621
5622 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5623 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5624 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5626 }
5627
5628 /* We don't support RTM (Real-time Transactional Memory) yet. */
5629 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5630 { /* likely */ }
5631 else
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5633
5634 /*
5635 * VMCS link pointer.
5636 */
5637 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5638 {
5639 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5640 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5641 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5642 { /* likely */ }
5643 else
5644 {
5645 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5647 }
5648
5649 /* Validate the address. */
5650 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5651 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5652 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5653 { /* likely */ }
5654 else
5655 {
5656 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5658 }
5659 }
5660
5661 NOREF(pszInstr);
5662 NOREF(pszFailure);
5663 return VINF_SUCCESS;
5664}
5665
5666
5667/**
5668 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5669 * VM-entry.
5670 *
5671 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5672 * @param pVCpu The cross context virtual CPU structure.
5673 * @param pszInstr The VMX instruction name (for logging purposes).
5674 * @param pVmcs Pointer to the virtual VMCS.
5675 */
5676IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5677{
5678 /*
5679 * Check PDPTEs.
5680 * See Intel spec. 4.4.1 "PDPTE Registers".
5681 */
5682 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5683 const char *const pszFailure = "VM-exit";
5684
5685 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5686 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5687 if (RT_SUCCESS(rc))
5688 {
5689 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5690 {
5691 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5692 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5693 { /* likely */ }
5694 else
5695 {
5696 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5697 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5699 }
5700 }
5701 }
5702 else
5703 {
5704 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5706 }
5707
5708 NOREF(pszFailure);
5709 NOREF(pszInstr);
5710 return rc;
5711}
5712
5713
5714/**
5715 * Checks guest PDPTEs as part of VM-entry.
5716 *
5717 * @param pVCpu The cross context virtual CPU structure.
5718 * @param pszInstr The VMX instruction name (for logging purposes).
5719 */
5720DECLINLINE(int) iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5721{
5722 /*
5723 * Guest PDPTEs.
5724 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5725 */
5726 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5727 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5728
5729 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5730 int rc;
5731 if ( !fGstInLongMode
5732 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5733 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5734 {
5735 /*
5736 * We don't support nested-paging for nested-guests yet.
5737 *
5738 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5739 * rather we need to check the PDPTEs referenced by the guest CR3.
5740 */
5741 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5742 }
5743 else
5744 rc = VINF_SUCCESS;
5745 return rc;
5746}
5747
5748
5749/**
5750 * Checks guest-state as part of VM-entry.
5751 *
5752 * @returns VBox status code.
5753 * @param pVCpu The cross context virtual CPU structure.
5754 * @param pszInstr The VMX instruction name (for logging purposes).
5755 */
5756IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5757{
5758 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5759 if (RT_SUCCESS(rc))
5760 {
5761 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5762 if (RT_SUCCESS(rc))
5763 {
5764 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5765 if (RT_SUCCESS(rc))
5766 {
5767 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5768 if (RT_SUCCESS(rc))
5769 {
5770 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5771 if (RT_SUCCESS(rc))
5772 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5773 }
5774 }
5775 }
5776 }
5777 return rc;
5778}
5779
5780
5781/**
5782 * Checks host-state as part of VM-entry.
5783 *
5784 * @returns VBox status code.
5785 * @param pVCpu The cross context virtual CPU structure.
5786 * @param pszInstr The VMX instruction name (for logging purposes).
5787 */
5788IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5789{
5790 /*
5791 * Host Control Registers and MSRs.
5792 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5793 */
5794 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5795 const char * const pszFailure = "VMFail";
5796
5797 /* CR0 reserved bits. */
5798 {
5799 /* CR0 MB1 bits. */
5800 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5801 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5805
5806 /* CR0 MBZ bits. */
5807 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5808 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5812 }
5813
5814 /* CR4 reserved bits. */
5815 {
5816 /* CR4 MB1 bits. */
5817 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5818 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5819 { /* likely */ }
5820 else
5821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5822
5823 /* CR4 MBZ bits. */
5824 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5825 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5826 { /* likely */ }
5827 else
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5829 }
5830
5831 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5832 {
5833 /* CR3 reserved bits. */
5834 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5838
5839 /* SYSENTER ESP and SYSENTER EIP. */
5840 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5841 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5842 { /* likely */ }
5843 else
5844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5845 }
5846
5847 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5848 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5849
5850 /* PAT MSR. */
5851 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5852 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5856
5857 /* EFER MSR. */
5858 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5859 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5860 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5861 { /* likely */ }
5862 else
5863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5864
5865 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5866 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5867 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5868 if ( fHostInLongMode == fHostLma
5869 && fHostInLongMode == fHostLme)
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5873
5874 /*
5875 * Host Segment and Descriptor-Table Registers.
5876 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5877 */
5878 /* Selector RPL and TI. */
5879 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5880 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5881 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5882 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5883 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5884 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5885 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5886 { /* likely */ }
5887 else
5888 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5889
5890 /* CS and TR selectors cannot be 0. */
5891 if ( pVmcs->HostCs
5892 && pVmcs->HostTr)
5893 { /* likely */ }
5894 else
5895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5896
5897 /* SS cannot be 0 if 32-bit host. */
5898 if ( fHostInLongMode
5899 || pVmcs->HostSs)
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5903
5904 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5905 {
5906 /* FS, GS, GDTR, IDTR, TR base address. */
5907 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5908 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5909 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5910 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5911 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5912 { /* likely */ }
5913 else
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5915 }
5916
5917 /*
5918 * Host address-space size for 64-bit CPUs.
5919 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5920 */
5921 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5922 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5923 {
5924 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5925
5926 /* Logical processor in IA-32e mode. */
5927 if (fCpuInLongMode)
5928 {
5929 if (fHostInLongMode)
5930 {
5931 /* PAE must be set. */
5932 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5933 { /* likely */ }
5934 else
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5936
5937 /* RIP must be canonical. */
5938 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5939 { /* likely */ }
5940 else
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5942 }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5945 }
5946 else
5947 {
5948 /* Logical processor is outside IA-32e mode. */
5949 if ( !fGstInLongMode
5950 && !fHostInLongMode)
5951 {
5952 /* PCIDE should not be set. */
5953 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5954 { /* likely */ }
5955 else
5956 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5957
5958 /* The high 32-bits of RIP MBZ. */
5959 if (!pVmcs->u64HostRip.s.Hi)
5960 { /* likely */ }
5961 else
5962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5963 }
5964 else
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5966 }
5967 }
5968 else
5969 {
5970 /* Host address-space size for 32-bit CPUs. */
5971 if ( !fGstInLongMode
5972 && !fHostInLongMode)
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5976 }
5977
5978 NOREF(pszInstr);
5979 NOREF(pszFailure);
5980 return VINF_SUCCESS;
5981}
5982
5983
5984/**
5985 * Checks VMCS controls fields as part of VM-entry.
5986 *
5987 * @returns VBox status code.
5988 * @param pVCpu The cross context virtual CPU structure.
5989 * @param pszInstr The VMX instruction name (for logging purposes).
5990 *
5991 * @remarks This may update secondary-processor based VM-execution control fields
5992 * in the current VMCS if necessary.
5993 */
5994IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5995{
5996 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5997 const char * const pszFailure = "VMFail";
5998
5999 /*
6000 * VM-execution controls.
6001 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6002 */
6003 {
6004 /* Pin-based VM-execution controls. */
6005 {
6006 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6007 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6008 { /* likely */ }
6009 else
6010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6011
6012 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6013 { /* likely */ }
6014 else
6015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6016 }
6017
6018 /* Processor-based VM-execution controls. */
6019 {
6020 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6021 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6022 { /* likely */ }
6023 else
6024 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6025
6026 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6027 { /* likely */ }
6028 else
6029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6030 }
6031
6032 /* Secondary processor-based VM-execution controls. */
6033 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6034 {
6035 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6036 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6037 { /* likely */ }
6038 else
6039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6040
6041 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6042 { /* likely */ }
6043 else
6044 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6045 }
6046 else
6047 Assert(!pVmcs->u32ProcCtls2);
6048
6049 /* CR3-target count. */
6050 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6051 { /* likely */ }
6052 else
6053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6054
6055 /* I/O bitmaps physical addresses. */
6056 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6057 {
6058 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6059 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6060 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6061 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6062 { /* likely */ }
6063 else
6064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6065
6066 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6067 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6068 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6069 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6073 }
6074
6075 /* MSR bitmap physical address. */
6076 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6077 {
6078 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6079 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6080 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6081 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6082 { /* likely */ }
6083 else
6084 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6085 }
6086
6087 /* TPR shadow related controls. */
6088 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6089 {
6090 /* Virtual-APIC page physical address. */
6091 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6092 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6093 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6094 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6095 { /* likely */ }
6096 else
6097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6098
6099 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6100 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6101 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6102 { /* likely */ }
6103 else
6104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6105
6106 /* The rest done XXX document */
6107 }
6108 else
6109 {
6110 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6111 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6112 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6113 { /* likely */ }
6114 else
6115 {
6116 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6118 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6119 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6120 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6122 }
6123 }
6124
6125 /* NMI exiting and virtual-NMIs. */
6126 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6127 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6128 { /* likely */ }
6129 else
6130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6131
6132 /* Virtual-NMIs and NMI-window exiting. */
6133 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6134 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6135 { /* likely */ }
6136 else
6137 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6138
6139 /* Virtualize APIC accesses. */
6140 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6141 {
6142 /* APIC-access physical address. */
6143 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6144 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6145 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6146 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6147 { /* likely */ }
6148 else
6149 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6150
6151 /*
6152 * Disallow APIC-access page and virtual-APIC page from being the same address.
6153 * Note! This is not an Intel requirement, but one imposed by our implementation.
6154 */
6155 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6156 * redirecting accesses between the APIC-access page and the virtual-APIC
6157 * page. If any nested hypervisor requires this, we can implement it later. */
6158 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6159 {
6160 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6161 if (GCPhysVirtApic != GCPhysApicAccess)
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6165 }
6166 }
6167
6168 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6169 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6170 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6171 { /* likely */ }
6172 else
6173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6174
6175 /* Virtual-interrupt delivery requires external interrupt exiting. */
6176 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6177 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6178 { /* likely */ }
6179 else
6180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6181
6182 /* VPID. */
6183 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6184 || pVmcs->u16Vpid != 0)
6185 { /* likely */ }
6186 else
6187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6188
6189 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6190 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6191 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6192 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6193 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6194 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6195 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6196 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6197
6198 /* VMCS shadowing. */
6199 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6200 {
6201 /* VMREAD-bitmap physical address. */
6202 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6203 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6204 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6205 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6209
6210 /* VMWRITE-bitmap physical address. */
6211 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6212 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6213 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6214 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6215 { /* likely */ }
6216 else
6217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6218 }
6219 }
6220
6221 /*
6222 * VM-exit controls.
6223 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6224 */
6225 {
6226 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6227 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6228 { /* likely */ }
6229 else
6230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6231
6232 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6233 { /* likely */ }
6234 else
6235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6236
6237 /* Save preemption timer without activating it. */
6238 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6239 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6243
6244 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6245 if (pVmcs->u32ExitMsrStoreCount)
6246 {
6247 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6248 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6249 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6250 { /* likely */ }
6251 else
6252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6253 }
6254
6255 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6256 if (pVmcs->u32ExitMsrLoadCount)
6257 {
6258 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6259 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6260 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6261 { /* likely */ }
6262 else
6263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6264 }
6265 }
6266
6267 /*
6268 * VM-entry controls.
6269 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6270 */
6271 {
6272 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6273 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6274 { /* likely */ }
6275 else
6276 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6277
6278 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6279 { /* likely */ }
6280 else
6281 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6282
6283 /* Event injection. */
6284 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6285 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6286 {
6287 /* Type and vector. */
6288 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6289 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6290 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6291 if ( !uRsvd
6292 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6293 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6294 { /* likely */ }
6295 else
6296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6297
6298 /* Exception error code. */
6299 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6300 {
6301 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6302 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6303 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6304 { /* likely */ }
6305 else
6306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6307
6308 /* Exceptions that provide an error code. */
6309 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6310 && ( uVector == X86_XCPT_DF
6311 || uVector == X86_XCPT_TS
6312 || uVector == X86_XCPT_NP
6313 || uVector == X86_XCPT_SS
6314 || uVector == X86_XCPT_GP
6315 || uVector == X86_XCPT_PF
6316 || uVector == X86_XCPT_AC))
6317 { /* likely */ }
6318 else
6319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6320
6321 /* Exception error-code reserved bits. */
6322 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6326
6327 /* Injecting a software interrupt, software exception or privileged software exception. */
6328 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6329 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6330 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6331 {
6332 /* Instruction length must be in the range 0-15. */
6333 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6334 { /* likely */ }
6335 else
6336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6337
6338 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6339 if ( pVmcs->u32EntryInstrLen != 0
6340 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6341 { /* likely */ }
6342 else
6343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6344 }
6345 }
6346 }
6347
6348 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6349 if (pVmcs->u32EntryMsrLoadCount)
6350 {
6351 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6352 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6353 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6354 { /* likely */ }
6355 else
6356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6357 }
6358
6359 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6360 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6361 }
6362
6363 NOREF(pszInstr);
6364 NOREF(pszFailure);
6365 return VINF_SUCCESS;
6366}
6367
6368
6369/**
6370 * Loads the guest control registers, debug register and some MSRs as part of
6371 * VM-entry.
6372 *
6373 * @param pVCpu The cross context virtual CPU structure.
6374 */
6375IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6376{
6377 /*
6378 * Load guest control registers, debug registers and MSRs.
6379 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6380 */
6381 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6382
6383 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6384 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6385 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6386 CPUMSetGuestCR0(pVCpu, uGstCr0);
6387 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6388 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6389
6390 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6391 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6392
6393 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6394 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6395 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6396
6397 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6398 {
6399 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6400
6401 /* EFER MSR. */
6402 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6403 {
6404 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6405 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6406 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6407 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6408 if (fGstInLongMode)
6409 {
6410 /* If the nested-guest is in long mode, LMA and LME are both set. */
6411 Assert(fGstPaging);
6412 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6413 }
6414 else
6415 {
6416 /*
6417 * If the nested-guest is outside long mode:
6418 * - With paging: LMA is cleared, LME is cleared.
6419 * - Without paging: LMA is cleared, LME is left unmodified.
6420 */
6421 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6422 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6423 }
6424 }
6425 /* else: see below. */
6426 }
6427
6428 /* PAT MSR. */
6429 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6430 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6431
6432 /* EFER MSR. */
6433 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6434 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6435
6436 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6437 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6438
6439 /* We don't support IA32_BNDCFGS MSR yet. */
6440 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6441
6442 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6443}
6444
6445
6446/**
6447 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6448 *
6449 * @param pVCpu The cross context virtual CPU structure.
6450 */
6451IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6452{
6453 /*
6454 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6455 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6456 */
6457 /* CS, SS, ES, DS, FS, GS. */
6458 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6459 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6460 {
6461 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6462 CPUMSELREG VmcsSelReg;
6463 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6464 AssertRC(rc); NOREF(rc);
6465 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6466 {
6467 pGstSelReg->Sel = VmcsSelReg.Sel;
6468 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6469 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6470 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6471 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6472 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6473 }
6474 else
6475 {
6476 pGstSelReg->Sel = VmcsSelReg.Sel;
6477 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6478 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6479 switch (iSegReg)
6480 {
6481 case X86_SREG_CS:
6482 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6483 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6484 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6485 break;
6486
6487 case X86_SREG_SS:
6488 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6489 pGstSelReg->u32Limit = 0;
6490 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6491 break;
6492
6493 case X86_SREG_ES:
6494 case X86_SREG_DS:
6495 pGstSelReg->u64Base = 0;
6496 pGstSelReg->u32Limit = 0;
6497 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6498 break;
6499
6500 case X86_SREG_FS:
6501 case X86_SREG_GS:
6502 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6503 pGstSelReg->u32Limit = 0;
6504 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6505 break;
6506 }
6507 Assert(pGstSelReg->Attr.n.u1Unusable);
6508 }
6509 }
6510
6511 /* LDTR. */
6512 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6513 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6514 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6515 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6516 {
6517 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6518 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6519 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6520 }
6521 else
6522 {
6523 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6524 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6525 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6526 }
6527
6528 /* TR. */
6529 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6530 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6531 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6532 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6533 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6534 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6535 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6536
6537 /* GDTR. */
6538 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6539 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6540
6541 /* IDTR. */
6542 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6543 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6544}
6545
6546
6547/**
6548 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6549 *
6550 * @returns VBox status code.
6551 * @param pVCpu The cross context virtual CPU structure.
6552 * @param pszInstr The VMX instruction name (for logging purposes).
6553 */
6554IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6555{
6556 /*
6557 * Load guest MSRs.
6558 * See Intel spec. 26.4 "Loading MSRs".
6559 */
6560 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6561 const char *const pszFailure = "VM-exit";
6562
6563 /*
6564 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6565 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6566 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6567 */
6568 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6569 if (!cMsrs)
6570 return VINF_SUCCESS;
6571
6572 /*
6573 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6574 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6575 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6576 */
6577 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6578 if (fIsMsrCountValid)
6579 { /* likely */ }
6580 else
6581 {
6582 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6584 }
6585
6586 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6587 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6588 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6589 if (RT_SUCCESS(rc))
6590 {
6591 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6592 Assert(pMsr);
6593 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6594 {
6595 if ( !pMsr->u32Reserved
6596 && pMsr->u32Msr != MSR_K8_FS_BASE
6597 && pMsr->u32Msr != MSR_K8_GS_BASE
6598 && pMsr->u32Msr != MSR_K6_EFER
6599 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6600 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6601 {
6602 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6603 if (rcStrict == VINF_SUCCESS)
6604 continue;
6605
6606 /*
6607 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6608 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6609 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6610 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6611 * MSR in ring-0 if possible, or come up with a better, generic solution.
6612 */
6613 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6614 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6615 ? kVmxVDiag_Vmentry_MsrLoadRing3
6616 : kVmxVDiag_Vmentry_MsrLoad;
6617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6618 }
6619 else
6620 {
6621 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6623 }
6624 }
6625 }
6626 else
6627 {
6628 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6630 }
6631
6632 NOREF(pszInstr);
6633 NOREF(pszFailure);
6634 return VINF_SUCCESS;
6635}
6636
6637
6638/**
6639 * Loads the guest-state non-register state as part of VM-entry.
6640 *
6641 * @returns VBox status code.
6642 * @param pVCpu The cross context virtual CPU structure.
6643 *
6644 * @remarks This must be called only after loading the nested-guest register state
6645 * (especially nested-guest RIP).
6646 */
6647IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6648{
6649 /*
6650 * Load guest non-register state.
6651 * See Intel spec. 26.6 "Special Features of VM Entry"
6652 */
6653 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6654
6655 /*
6656 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6657 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6658 *
6659 * See Intel spec. 26.6.1 "Interruptibility State".
6660 */
6661 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6662 if ( !fEntryVectoring
6663 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6664 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6665 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6666 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6667
6668 /* NMI blocking. */
6669 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6670 {
6671 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6672 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6673 else
6674 {
6675 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6676 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6677 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6678 }
6679 }
6680 else
6681 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6682
6683 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6684
6685 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6686 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6687
6688 /* VPID is irrelevant. We don't support VPID yet. */
6689
6690 /* Clear address-range monitoring. */
6691 EMMonitorWaitClear(pVCpu);
6692}
6693
6694
6695/**
6696 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6697 *
6698 * @param pVCpu The cross context virtual CPU structure.
6699 * @param pszInstr The VMX instruction name (for logging purposes).
6700 *
6701 * @remarks This assumes various VMCS related data structure pointers have already
6702 * been verified prior to calling this function.
6703 */
6704IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6705{
6706 const char *const pszFailure = "VM-exit";
6707 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6708
6709 /*
6710 * Virtualize APIC accesses.
6711 */
6712 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6713 {
6714 /* APIC-access physical address. */
6715 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6716
6717 /*
6718 * Register the handler for the APIC-access page.
6719 *
6720 * We don't deregister the APIC-access page handler during the VM-exit as a different
6721 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6722 *
6723 * We leave the page registered until the first access that happens outside VMX non-root
6724 * mode. Guest software is allowed to access structures such as the APIC-access page
6725 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6726 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6727 *
6728 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6729 */
6730 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6731 {
6732 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6733 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6734 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6735 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6736 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6737 if (RT_SUCCESS(rc))
6738 { /* likely */ }
6739 else
6740 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6741 }
6742 }
6743
6744 /*
6745 * VMCS shadowing.
6746 */
6747 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6748 {
6749 /* Read the VMREAD-bitmap. */
6750 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6751 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6752 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6753 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6754 if (RT_SUCCESS(rc))
6755 { /* likely */ }
6756 else
6757 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6758
6759 /* Read the VMWRITE-bitmap. */
6760 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6761 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6762 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6763 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6764 if (RT_SUCCESS(rc))
6765 { /* likely */ }
6766 else
6767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6768 }
6769
6770 /*
6771 * I/O bitmaps.
6772 */
6773 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6774 {
6775 /* Read the IO bitmap A. */
6776 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6777 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap));
6778 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap),
6779 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6780 if (RT_SUCCESS(rc))
6781 { /* likely */ }
6782 else
6783 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6784
6785 /* Read the IO bitmap B. */
6786 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6787 uint8_t *pbIoBitmapB = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
6788 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pbIoBitmapB, GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6789 if (RT_SUCCESS(rc))
6790 { /* likely */ }
6791 else
6792 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6793 }
6794
6795 /*
6796 * TPR shadow and Virtual-APIC page.
6797 */
6798 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6799 {
6800 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6801 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6802 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6803 {
6804 /* Read the VTPR from the virtual-APIC page. */
6805 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6806 uint8_t u8VTpr;
6807 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6808 if (RT_SUCCESS(rc))
6809 { /* likely */ }
6810 else
6811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6812
6813 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6814 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6815 { /* likely */ }
6816 else
6817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6818 }
6819 }
6820
6821 /*
6822 * VMCS link pointer.
6823 */
6824 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6825 {
6826 /* Read the VMCS-link pointer from guest memory. */
6827 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6828 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6829 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6830 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
6831 if (RT_SUCCESS(rc))
6832 { /* likely */ }
6833 else
6834 {
6835 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6837 }
6838
6839 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6840 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6841 { /* likely */ }
6842 else
6843 {
6844 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6846 }
6847
6848 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6849 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6850 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6851 { /* likely */ }
6852 else
6853 {
6854 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6856 }
6857
6858 /* Update our cache of the guest physical address of the shadow VMCS. */
6859 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6860 }
6861
6862 /*
6863 * MSR bitmap.
6864 */
6865 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6866 {
6867 /* Read the MSR bitmap. */
6868 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6869 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6870 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6871 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6872 if (RT_SUCCESS(rc))
6873 { /* likely */ }
6874 else
6875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6876 }
6877
6878 NOREF(pszFailure);
6879 NOREF(pszInstr);
6880 return VINF_SUCCESS;
6881}
6882
6883
6884/**
6885 * Loads the guest-state as part of VM-entry.
6886 *
6887 * @returns VBox status code.
6888 * @param pVCpu The cross context virtual CPU structure.
6889 * @param pszInstr The VMX instruction name (for logging purposes).
6890 *
6891 * @remarks This must be done after all the necessary steps prior to loading of
6892 * guest-state (e.g. checking various VMCS state).
6893 */
6894IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6895{
6896 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6897 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6898
6899 /* Load guest segment registers. */
6900 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6901
6902 /*
6903 * Load guest RIP, RSP and RFLAGS.
6904 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6905 */
6906 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6907 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6908 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6909 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6910
6911 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6912 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6913 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6914
6915 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6916 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6917
6918 /* Load VMX related structures and state referenced by the VMCS. */
6919 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6920 if (rc == VINF_SUCCESS)
6921 { /* likely */ }
6922 else
6923 return rc;
6924
6925 NOREF(pszInstr);
6926 return VINF_SUCCESS;
6927}
6928
6929
6930/**
6931 * Returns whether there are is a pending debug exception on VM-entry.
6932 *
6933 * @param pVCpu The cross context virtual CPU structure.
6934 * @param pszInstr The VMX instruction name (for logging purposes).
6935 */
6936IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6937{
6938 /*
6939 * Pending debug exceptions.
6940 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6941 */
6942 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6943 Assert(pVmcs);
6944
6945 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6946 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6947 if (fPendingDbgXcpt)
6948 {
6949 uint8_t uEntryIntInfoType;
6950 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6951 if (fEntryVectoring)
6952 {
6953 switch (uEntryIntInfoType)
6954 {
6955 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6956 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6957 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6958 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6959 fPendingDbgXcpt = false;
6960 break;
6961
6962 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6963 {
6964 /*
6965 * Whether the pending debug exception for software exceptions other than
6966 * #BP and #OF is delivered after injecting the exception or is discard
6967 * is CPU implementation specific. We will discard them (easier).
6968 */
6969 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6970 if ( uVector != X86_XCPT_BP
6971 && uVector != X86_XCPT_OF)
6972 fPendingDbgXcpt = false;
6973 RT_FALL_THRU();
6974 }
6975 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6976 {
6977 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6978 fPendingDbgXcpt = false;
6979 break;
6980 }
6981 }
6982 }
6983 else
6984 {
6985 /*
6986 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6987 * pending debug exception is held pending or is discarded is CPU implementation
6988 * specific. We will discard them (easier).
6989 */
6990 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6991 fPendingDbgXcpt = false;
6992
6993 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6994 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6995 fPendingDbgXcpt = false;
6996 }
6997 }
6998
6999 NOREF(pszInstr);
7000 return fPendingDbgXcpt;
7001}
7002
7003
7004/**
7005 * Set up the monitor-trap flag (MTF).
7006 *
7007 * @param pVCpu The cross context virtual CPU structure.
7008 * @param pszInstr The VMX instruction name (for logging purposes).
7009 */
7010IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7011{
7012 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7013 Assert(pVmcs);
7014 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7015 {
7016 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7017 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7018 }
7019 else
7020 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7021 NOREF(pszInstr);
7022}
7023
7024
7025/**
7026 * Sets up NMI-window exiting.
7027 *
7028 * @param pVCpu The cross context virtual CPU structure.
7029 * @param pszInstr The VMX instruction name (for logging purposes).
7030 */
7031IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7032{
7033 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7034 Assert(pVmcs);
7035 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7036 {
7037 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7038 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7039 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7040 }
7041 else
7042 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7043 NOREF(pszInstr);
7044}
7045
7046
7047/**
7048 * Sets up interrupt-window exiting.
7049 *
7050 * @param pVCpu The cross context virtual CPU structure.
7051 * @param pszInstr The VMX instruction name (for logging purposes).
7052 */
7053IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7054{
7055 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7056 Assert(pVmcs);
7057 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7058 {
7059 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7060 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7061 }
7062 else
7063 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7064 NOREF(pszInstr);
7065}
7066
7067
7068/**
7069 * Set up the VMX-preemption timer.
7070 *
7071 * @param pVCpu The cross context virtual CPU structure.
7072 * @param pszInstr The VMX instruction name (for logging purposes).
7073 */
7074IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7075{
7076 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7077 Assert(pVmcs);
7078 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7079 {
7080 /*
7081 * If the timer is 0, we must cause a VM-exit before executing the first
7082 * nested-guest instruction. So we can flag as though the timer has already
7083 * expired and we will check and cause a VM-exit at the right priority elsewhere
7084 * in the code.
7085 */
7086 uint64_t uEntryTick;
7087 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7088 if (uPreemptTimer)
7089 {
7090 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7091 AssertRC(rc);
7092 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7093 }
7094 else
7095 {
7096 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7097 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7098 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7099 }
7100
7101 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7102 }
7103 else
7104 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7105
7106 NOREF(pszInstr);
7107}
7108
7109
7110/**
7111 * Injects an event using TRPM given a VM-entry interruption info. and related
7112 * fields.
7113 *
7114 * @param pVCpu The cross context virtual CPU structure.
7115 * @param pszInstr The VMX instruction name (for logging purposes).
7116 * @param uEntryIntInfo The VM-entry interruption info.
7117 * @param uErrCode The error code associated with the event if any.
7118 * @param cbInstr The VM-entry instruction length (for software
7119 * interrupts and software exceptions). Pass 0
7120 * otherwise.
7121 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7122 */
7123IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7124 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7125{
7126 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7127
7128 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7129 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7130 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7131
7132 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7133
7134 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7135 AssertRC(rc);
7136 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7137
7138 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7139 {
7140 TRPMSetErrorCode(pVCpu, uErrCode);
7141 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7142 }
7143
7144 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7145 {
7146 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7147 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7148 }
7149 else
7150 {
7151 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7152 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7153 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7154 {
7155 TRPMSetInstrLength(pVCpu, cbInstr);
7156 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7157 }
7158 }
7159
7160 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7161 {
7162 TRPMSetTrapDueToIcebp(pVCpu);
7163 Log(("%s: Injecting: icebp\n", pszInstr));
7164 }
7165
7166 NOREF(pszInstr);
7167}
7168
7169
7170/**
7171 * Performs event injection (if any) as part of VM-entry.
7172 *
7173 * @param pVCpu The cross context virtual CPU structure.
7174 * @param pszInstr The VMX instruction name (for logging purposes).
7175 */
7176IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7177{
7178 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7179
7180 /*
7181 * Inject events.
7182 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7183 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7184 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7185 * the actually delivery of this event.
7186 *
7187 * See Intel spec. 26.5 "Event Injection".
7188 */
7189 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7190 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7191
7192 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7193 if (fEntryIntInfoValid)
7194 {
7195 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7196 {
7197 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7198 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7199 }
7200 else
7201 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7202 pVCpu->cpum.GstCtx.cr2);
7203
7204 /*
7205 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7206 *
7207 * However, we do it here on VM-entry as well because while it isn't visible to guest
7208 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7209 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7210 *
7211 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7212 */
7213 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7214 }
7215 else
7216 {
7217 /*
7218 * Inject any pending guest debug exception.
7219 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7220 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7221 */
7222 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7223 if (fPendingDbgXcpt)
7224 {
7225 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7226 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7227 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7228 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7229 0 /* GCPtrFaultAddress */);
7230 }
7231 }
7232
7233 NOREF(pszInstr);
7234}
7235
7236
7237/**
7238 * Initializes all read-only VMCS fields as part of VM-entry.
7239 *
7240 * @param pVCpu The cross context virtual CPU structure.
7241 */
7242IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7243{
7244 /*
7245 * Any VMCS field which we do not establish on every VM-exit but may potentially
7246 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7247 * specified to be undefined, needs to be initialized here.
7248 *
7249 * Thus, it is especially important to clear the Exit qualification field
7250 * since it must be zero for VM-exits where it is not used. Similarly, the
7251 * VM-exit interruption information field's valid bit needs to be cleared for
7252 * the same reasons.
7253 */
7254 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7255 Assert(pVmcs);
7256
7257 /* 16-bit (none currently). */
7258 /* 32-bit. */
7259 pVmcs->u32RoVmInstrError = 0;
7260 pVmcs->u32RoExitReason = 0;
7261 pVmcs->u32RoExitIntInfo = 0;
7262 pVmcs->u32RoExitIntErrCode = 0;
7263 pVmcs->u32RoIdtVectoringInfo = 0;
7264 pVmcs->u32RoIdtVectoringErrCode = 0;
7265 pVmcs->u32RoExitInstrLen = 0;
7266 pVmcs->u32RoExitInstrInfo = 0;
7267
7268 /* 64-bit. */
7269 pVmcs->u64RoGuestPhysAddr.u = 0;
7270
7271 /* Natural-width. */
7272 pVmcs->u64RoExitQual.u = 0;
7273 pVmcs->u64RoIoRcx.u = 0;
7274 pVmcs->u64RoIoRsi.u = 0;
7275 pVmcs->u64RoIoRdi.u = 0;
7276 pVmcs->u64RoIoRip.u = 0;
7277 pVmcs->u64RoGuestLinearAddr.u = 0;
7278}
7279
7280
7281/**
7282 * VMLAUNCH/VMRESUME instruction execution worker.
7283 *
7284 * @returns Strict VBox status code.
7285 * @param pVCpu The cross context virtual CPU structure.
7286 * @param cbInstr The instruction length in bytes.
7287 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7288 * VMXINSTRID_VMRESUME).
7289 *
7290 * @remarks Common VMX instruction checks are already expected to by the caller,
7291 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7292 */
7293IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7294{
7295# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7296 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7297 return VINF_EM_RAW_EMULATE_INSTR;
7298# else
7299 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7300 || uInstrId == VMXINSTRID_VMRESUME);
7301 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7302
7303 /* Nested-guest intercept. */
7304 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7305 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7306
7307 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7308
7309 /*
7310 * Basic VM-entry checks.
7311 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7312 * The checks following that do not have to follow a specific order.
7313 *
7314 * See Intel spec. 26.1 "Basic VM-entry Checks".
7315 */
7316
7317 /* CPL. */
7318 if (pVCpu->iem.s.uCpl == 0)
7319 { /* likely */ }
7320 else
7321 {
7322 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7323 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7324 return iemRaiseGeneralProtectionFault0(pVCpu);
7325 }
7326
7327 /* Current VMCS valid. */
7328 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7329 { /* likely */ }
7330 else
7331 {
7332 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7333 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7334 iemVmxVmFailInvalid(pVCpu);
7335 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7336 return VINF_SUCCESS;
7337 }
7338
7339 /* Current VMCS is not a shadow VMCS. */
7340 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7341 { /* likely */ }
7342 else
7343 {
7344 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7345 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7346 iemVmxVmFailInvalid(pVCpu);
7347 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7348 return VINF_SUCCESS;
7349 }
7350
7351 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7352 * use block-by-STI here which is not quite correct. */
7353 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7354 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7355 { /* likely */ }
7356 else
7357 {
7358 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7359 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7360 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7361 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7362 return VINF_SUCCESS;
7363 }
7364
7365 if (uInstrId == VMXINSTRID_VMLAUNCH)
7366 {
7367 /* VMLAUNCH with non-clear VMCS. */
7368 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7369 { /* likely */ }
7370 else
7371 {
7372 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7373 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7374 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7375 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7376 return VINF_SUCCESS;
7377 }
7378 }
7379 else
7380 {
7381 /* VMRESUME with non-launched VMCS. */
7382 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7383 { /* likely */ }
7384 else
7385 {
7386 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7387 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7388 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7389 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7390 return VINF_SUCCESS;
7391 }
7392 }
7393
7394 /*
7395 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7396 * while entering VMX non-root mode. We do some of this while checking VM-execution
7397 * controls. The nested hypervisor should not make assumptions and cannot expect
7398 * predictable behavior if changes to these structures are made in guest memory while
7399 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7400 * modify them anyway as we cache them in host memory.
7401 *
7402 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7403 */
7404 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7405 Assert(pVmcs);
7406 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7407
7408 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7409 if (RT_SUCCESS(rc))
7410 {
7411 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7412 if (RT_SUCCESS(rc))
7413 {
7414 /*
7415 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7416 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7417 * ones that may occur during VM-entry below).
7418 */
7419 iemVmxVmentryInitReadOnlyFields(pVCpu);
7420
7421 /*
7422 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7423 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7424 * VM-exit when required.
7425 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7426 */
7427 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7428
7429 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7430 if (RT_SUCCESS(rc))
7431 {
7432 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7433 if (RT_SUCCESS(rc))
7434 {
7435 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7436 if (RT_SUCCESS(rc))
7437 {
7438 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7439
7440 /* VMLAUNCH instruction must update the VMCS launch state. */
7441 if (uInstrId == VMXINSTRID_VMLAUNCH)
7442 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7443
7444 /* Perform the VMX transition (PGM updates). */
7445 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7446 if (rcStrict == VINF_SUCCESS)
7447 { /* likely */ }
7448 else if (RT_SUCCESS(rcStrict))
7449 {
7450 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7451 VBOXSTRICTRC_VAL(rcStrict)));
7452 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7453 }
7454 else
7455 {
7456 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7457 return rcStrict;
7458 }
7459
7460 /* Paranoia. */
7461 Assert(rcStrict == VINF_SUCCESS);
7462
7463 /* We've now entered nested-guest execution. */
7464 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7465
7466 /*
7467 * The priority of potential VM-exits during VM-entry is important.
7468 * The priorities of VM-exits and events are listed from highest
7469 * to lowest as follows:
7470 *
7471 * 1. Event injection.
7472 * 2. Trap on task-switch (T flag set in TSS).
7473 * 3. TPR below threshold / APIC-write.
7474 * 4. SMI, INIT.
7475 * 5. MTF exit.
7476 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7477 * 7. VMX-preemption timer.
7478 * 9. NMI-window exit.
7479 * 10. NMI injection.
7480 * 11. Interrupt-window exit.
7481 * 12. Virtual-interrupt injection.
7482 * 13. Interrupt injection.
7483 * 14. Process next instruction (fetch, decode, execute).
7484 */
7485
7486 /* Setup VMX-preemption timer. */
7487 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7488
7489 /* Setup monitor-trap flag. */
7490 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7491
7492 /* Setup NMI-window exiting. */
7493 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7494
7495 /* Setup interrupt-window exiting. */
7496 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7497
7498 /*
7499 * Inject any event that the nested hypervisor wants to inject.
7500 * Note! We cannot immediately perform the event injection here as we may have
7501 * pending PGM operations to perform due to switching page tables and/or
7502 * mode.
7503 */
7504 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7505
7506# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7507 /* Reschedule to IEM-only execution of the nested-guest. */
7508 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7509 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7510 if (rcSched != VINF_SUCCESS)
7511 iemSetPassUpStatus(pVCpu, rcSched);
7512# endif
7513
7514 /* Finally, done. */
7515 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7516 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7517 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7518 pVCpu->cpum.GstCtx.msrEFER));
7519 return VINF_SUCCESS;
7520 }
7521 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7522 pVmcs->u64RoExitQual.u);
7523 }
7524 }
7525 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7526 pVmcs->u64RoExitQual.u);
7527 }
7528
7529 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7530 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7531 return VINF_SUCCESS;
7532 }
7533
7534 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7535 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7536 return VINF_SUCCESS;
7537# endif
7538}
7539
7540
7541/**
7542 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7543 * (causes a VM-exit) or not.
7544 *
7545 * @returns @c true if the instruction is intercepted, @c false otherwise.
7546 * @param pVCpu The cross context virtual CPU structure.
7547 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7548 * VMX_EXIT_WRMSR).
7549 * @param idMsr The MSR.
7550 */
7551IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7552{
7553 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7554 Assert( uExitReason == VMX_EXIT_RDMSR
7555 || uExitReason == VMX_EXIT_WRMSR);
7556
7557 /* Consult the MSR bitmap if the feature is supported. */
7558 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7559 Assert(pVmcs);
7560 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7561 {
7562 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7563 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7564 if (uExitReason == VMX_EXIT_RDMSR)
7565 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7566 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7567 }
7568
7569 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7570 return true;
7571}
7572
7573
7574/**
7575 * VMREAD instruction execution worker that does not perform any validation checks.
7576 *
7577 * Callers are expected to have performed the necessary checks and to ensure the
7578 * VMREAD will succeed.
7579 *
7580 * @param pVmcs Pointer to the virtual VMCS.
7581 * @param pu64Dst Where to write the VMCS value.
7582 * @param u64VmcsField The VMCS field.
7583 *
7584 * @remarks May be called with interrupts disabled.
7585 */
7586IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7587{
7588 VMXVMCSFIELD VmcsField;
7589 VmcsField.u = u64VmcsField;
7590 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7591 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7592 uint8_t const uWidthType = (uWidth << 2) | uType;
7593 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7594 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7595 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7596 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7597 uWidth, uType, uIndex, uIndex));
7598 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7599
7600 /*
7601 * Read the VMCS component based on the field's effective width.
7602 *
7603 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7604 * indicates high bits (little endian).
7605 *
7606 * Note! The caller is responsible to trim the result and update registers
7607 * or memory locations are required. Here we just zero-extend to the largest
7608 * type (i.e. 64-bits).
7609 */
7610 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7611 uint8_t const *pbField = pbVmcs + offField;
7612 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7613 switch (uEffWidth)
7614 {
7615 case VMX_VMCSFIELD_WIDTH_64BIT:
7616 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7617 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7618 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7619 }
7620}
7621
7622
7623/**
7624 * VMREAD common (memory/register) instruction execution worker.
7625 *
7626 * @returns Strict VBox status code.
7627 * @param pVCpu The cross context virtual CPU structure.
7628 * @param cbInstr The instruction length in bytes.
7629 * @param pu64Dst Where to write the VMCS value (only updated when
7630 * VINF_SUCCESS is returned).
7631 * @param u64VmcsField The VMCS field.
7632 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7633 * NULL.
7634 */
7635IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7636 PCVMXVEXITINFO pExitInfo)
7637{
7638 /* Nested-guest intercept. */
7639 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7640 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7641 {
7642 if (pExitInfo)
7643 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7644 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7645 }
7646
7647 /* CPL. */
7648 if (pVCpu->iem.s.uCpl == 0)
7649 { /* likely */ }
7650 else
7651 {
7652 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7653 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7654 return iemRaiseGeneralProtectionFault0(pVCpu);
7655 }
7656
7657 /* VMCS pointer in root mode. */
7658 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7659 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7660 { /* likely */ }
7661 else
7662 {
7663 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7664 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7665 iemVmxVmFailInvalid(pVCpu);
7666 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7667 return VINF_SUCCESS;
7668 }
7669
7670 /* VMCS-link pointer in non-root mode. */
7671 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7672 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7673 { /* likely */ }
7674 else
7675 {
7676 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7677 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7678 iemVmxVmFailInvalid(pVCpu);
7679 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7680 return VINF_SUCCESS;
7681 }
7682
7683 /* Supported VMCS field. */
7684 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7685 { /* likely */ }
7686 else
7687 {
7688 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7689 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7690 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7691 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7692 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7693 return VINF_SUCCESS;
7694 }
7695
7696 /*
7697 * Reading from the current or shadow VMCS.
7698 */
7699 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7700 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7701 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7702 Assert(pVmcs);
7703 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7704 return VINF_SUCCESS;
7705}
7706
7707
7708/**
7709 * VMREAD (64-bit register) instruction execution worker.
7710 *
7711 * @returns Strict VBox status code.
7712 * @param pVCpu The cross context virtual CPU structure.
7713 * @param cbInstr The instruction length in bytes.
7714 * @param pu64Dst Where to store the VMCS field's value.
7715 * @param u64VmcsField The VMCS field.
7716 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7717 * NULL.
7718 */
7719IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7720 PCVMXVEXITINFO pExitInfo)
7721{
7722 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7723 if (rcStrict == VINF_SUCCESS)
7724 {
7725 iemVmxVmreadSuccess(pVCpu, cbInstr);
7726 return VINF_SUCCESS;
7727 }
7728
7729 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7730 return rcStrict;
7731}
7732
7733
7734/**
7735 * VMREAD (32-bit register) instruction execution worker.
7736 *
7737 * @returns Strict VBox status code.
7738 * @param pVCpu The cross context virtual CPU structure.
7739 * @param cbInstr The instruction length in bytes.
7740 * @param pu32Dst Where to store the VMCS field's value.
7741 * @param u32VmcsField The VMCS field.
7742 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7743 * NULL.
7744 */
7745IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7746 PCVMXVEXITINFO pExitInfo)
7747{
7748 uint64_t u64Dst;
7749 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7750 if (rcStrict == VINF_SUCCESS)
7751 {
7752 *pu32Dst = u64Dst;
7753 iemVmxVmreadSuccess(pVCpu, cbInstr);
7754 return VINF_SUCCESS;
7755 }
7756
7757 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7758 return rcStrict;
7759}
7760
7761
7762/**
7763 * VMREAD (memory) instruction execution worker.
7764 *
7765 * @returns Strict VBox status code.
7766 * @param pVCpu The cross context virtual CPU structure.
7767 * @param cbInstr The instruction length in bytes.
7768 * @param iEffSeg The effective segment register to use with @a u64Val.
7769 * Pass UINT8_MAX if it is a register access.
7770 * @param GCPtrDst The guest linear address to store the VMCS field's
7771 * value.
7772 * @param u64VmcsField The VMCS field.
7773 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7774 * NULL.
7775 */
7776IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7777 PCVMXVEXITINFO pExitInfo)
7778{
7779 uint64_t u64Dst;
7780 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7781 if (rcStrict == VINF_SUCCESS)
7782 {
7783 /*
7784 * Write the VMCS field's value to the location specified in guest-memory.
7785 */
7786 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7787 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7788 else
7789 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7790 if (rcStrict == VINF_SUCCESS)
7791 {
7792 iemVmxVmreadSuccess(pVCpu, cbInstr);
7793 return VINF_SUCCESS;
7794 }
7795
7796 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7797 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7798 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7799 return rcStrict;
7800 }
7801
7802 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7803 return rcStrict;
7804}
7805
7806
7807/**
7808 * VMWRITE instruction execution worker that does not perform any validation
7809 * checks.
7810 *
7811 * Callers are expected to have performed the necessary checks and to ensure the
7812 * VMWRITE will succeed.
7813 *
7814 * @param pVmcs Pointer to the virtual VMCS.
7815 * @param u64Val The value to write.
7816 * @param u64VmcsField The VMCS field.
7817 *
7818 * @remarks May be called with interrupts disabled.
7819 */
7820IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7821{
7822 VMXVMCSFIELD VmcsField;
7823 VmcsField.u = u64VmcsField;
7824 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7825 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7826 uint8_t const uWidthType = (uWidth << 2) | uType;
7827 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7828 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7829 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7830 Assert(offField < VMX_V_VMCS_SIZE);
7831 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7832
7833 /*
7834 * Write the VMCS component based on the field's effective width.
7835 *
7836 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7837 * indicates high bits (little endian).
7838 */
7839 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7840 uint8_t *pbField = pbVmcs + offField;
7841 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7842 switch (uEffWidth)
7843 {
7844 case VMX_VMCSFIELD_WIDTH_64BIT:
7845 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7846 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7847 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7848 }
7849}
7850
7851
7852/**
7853 * VMWRITE instruction execution worker.
7854 *
7855 * @returns Strict VBox status code.
7856 * @param pVCpu The cross context virtual CPU structure.
7857 * @param cbInstr The instruction length in bytes.
7858 * @param iEffSeg The effective segment register to use with @a u64Val.
7859 * Pass UINT8_MAX if it is a register access.
7860 * @param u64Val The value to write (or guest linear address to the
7861 * value), @a iEffSeg will indicate if it's a memory
7862 * operand.
7863 * @param u64VmcsField The VMCS field.
7864 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7865 * NULL.
7866 */
7867IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7868 PCVMXVEXITINFO pExitInfo)
7869{
7870 /* Nested-guest intercept. */
7871 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7872 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7873 {
7874 if (pExitInfo)
7875 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7876 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7877 }
7878
7879 /* CPL. */
7880 if (pVCpu->iem.s.uCpl == 0)
7881 { /* likely */ }
7882 else
7883 {
7884 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7885 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7886 return iemRaiseGeneralProtectionFault0(pVCpu);
7887 }
7888
7889 /* VMCS pointer in root mode. */
7890 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7891 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7892 { /* likely */ }
7893 else
7894 {
7895 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7896 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7897 iemVmxVmFailInvalid(pVCpu);
7898 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7899 return VINF_SUCCESS;
7900 }
7901
7902 /* VMCS-link pointer in non-root mode. */
7903 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7904 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7905 { /* likely */ }
7906 else
7907 {
7908 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7909 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7910 iemVmxVmFailInvalid(pVCpu);
7911 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7912 return VINF_SUCCESS;
7913 }
7914
7915 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7916 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7917 if (!fIsRegOperand)
7918 {
7919 /* Read the value from the specified guest memory location. */
7920 VBOXSTRICTRC rcStrict;
7921 RTGCPTR const GCPtrVal = u64Val;
7922 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7923 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7924 else
7925 {
7926 uint32_t u32Val;
7927 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
7928 u64Val = u32Val;
7929 }
7930 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7931 {
7932 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7934 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7935 return rcStrict;
7936 }
7937 }
7938 else
7939 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7940
7941 /* Supported VMCS field. */
7942 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7943 { /* likely */ }
7944 else
7945 {
7946 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7947 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7948 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7949 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7950 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7951 return VINF_SUCCESS;
7952 }
7953
7954 /* Read-only VMCS field. */
7955 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7956 if ( !fIsFieldReadOnly
7957 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7958 { /* likely */ }
7959 else
7960 {
7961 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7962 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7963 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7964 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7966 return VINF_SUCCESS;
7967 }
7968
7969 /*
7970 * Write to the current or shadow VMCS.
7971 */
7972 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7973 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7974 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7975 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7976 Assert(pVmcs);
7977 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7978
7979 /* Notify HM that the VMCS content might have changed. */
7980 if (!fInVmxNonRootMode)
7981 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7982
7983 iemVmxVmSucceed(pVCpu);
7984 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7985 return VINF_SUCCESS;
7986}
7987
7988
7989/**
7990 * VMCLEAR instruction execution worker.
7991 *
7992 * @returns Strict VBox status code.
7993 * @param pVCpu The cross context virtual CPU structure.
7994 * @param cbInstr The instruction length in bytes.
7995 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7996 * @param GCPtrVmcs The linear address of the VMCS pointer.
7997 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7998 *
7999 * @remarks Common VMX instruction checks are already expected to by the caller,
8000 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8001 */
8002IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8003 PCVMXVEXITINFO pExitInfo)
8004{
8005 /* Nested-guest intercept. */
8006 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8007 {
8008 if (pExitInfo)
8009 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8010 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8011 }
8012
8013 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8014
8015 /* CPL. */
8016 if (pVCpu->iem.s.uCpl == 0)
8017 { /* likely */ }
8018 else
8019 {
8020 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8021 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8022 return iemRaiseGeneralProtectionFault0(pVCpu);
8023 }
8024
8025 /* Get the VMCS pointer from the location specified by the source memory operand. */
8026 RTGCPHYS GCPhysVmcs;
8027 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8028 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8029 { /* likely */ }
8030 else
8031 {
8032 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8033 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8034 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8035 return rcStrict;
8036 }
8037
8038 /* VMCS pointer alignment. */
8039 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8040 { /* likely */ }
8041 else
8042 {
8043 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8044 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8045 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8046 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8047 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8048 return VINF_SUCCESS;
8049 }
8050
8051 /* VMCS physical-address width limits. */
8052 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8053 { /* likely */ }
8054 else
8055 {
8056 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8057 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8058 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8059 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8060 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8061 return VINF_SUCCESS;
8062 }
8063
8064 /* VMCS is not the VMXON region. */
8065 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8066 { /* likely */ }
8067 else
8068 {
8069 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8070 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8071 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8072 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8073 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8074 return VINF_SUCCESS;
8075 }
8076
8077 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8078 restriction imposed by our implementation. */
8079 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8085 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8086 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8088 return VINF_SUCCESS;
8089 }
8090
8091 /*
8092 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8093 *
8094 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8095 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8096 * to 'clear'.
8097 */
8098 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8099 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8100 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8101 {
8102 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8103 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8104 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8105 }
8106 else
8107 {
8108 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8109 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8110 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8111 if (RT_FAILURE(rcStrict))
8112 return rcStrict;
8113 }
8114
8115 iemVmxVmSucceed(pVCpu);
8116 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8117 return VINF_SUCCESS;
8118}
8119
8120
8121/**
8122 * VMPTRST instruction execution worker.
8123 *
8124 * @returns Strict VBox status code.
8125 * @param pVCpu The cross context virtual CPU structure.
8126 * @param cbInstr The instruction length in bytes.
8127 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8128 * @param GCPtrVmcs The linear address of where to store the current VMCS
8129 * pointer.
8130 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8131 *
8132 * @remarks Common VMX instruction checks are already expected to by the caller,
8133 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8134 */
8135IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8136 PCVMXVEXITINFO pExitInfo)
8137{
8138 /* Nested-guest intercept. */
8139 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8140 {
8141 if (pExitInfo)
8142 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8143 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8144 }
8145
8146 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8147
8148 /* CPL. */
8149 if (pVCpu->iem.s.uCpl == 0)
8150 { /* likely */ }
8151 else
8152 {
8153 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8154 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8155 return iemRaiseGeneralProtectionFault0(pVCpu);
8156 }
8157
8158 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8159 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8160 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8161 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8162 {
8163 iemVmxVmSucceed(pVCpu);
8164 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8165 return rcStrict;
8166 }
8167
8168 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8170 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8171 return rcStrict;
8172}
8173
8174
8175/**
8176 * VMPTRLD instruction execution worker.
8177 *
8178 * @returns Strict VBox status code.
8179 * @param pVCpu The cross context virtual CPU structure.
8180 * @param cbInstr The instruction length in bytes.
8181 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8182 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8183 *
8184 * @remarks Common VMX instruction checks are already expected to by the caller,
8185 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8186 */
8187IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8188 PCVMXVEXITINFO pExitInfo)
8189{
8190 /* Nested-guest intercept. */
8191 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8192 {
8193 if (pExitInfo)
8194 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8195 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8196 }
8197
8198 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8199
8200 /* CPL. */
8201 if (pVCpu->iem.s.uCpl == 0)
8202 { /* likely */ }
8203 else
8204 {
8205 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8206 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8207 return iemRaiseGeneralProtectionFault0(pVCpu);
8208 }
8209
8210 /* Get the VMCS pointer from the location specified by the source memory operand. */
8211 RTGCPHYS GCPhysVmcs;
8212 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8213 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8214 { /* likely */ }
8215 else
8216 {
8217 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8218 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8219 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8220 return rcStrict;
8221 }
8222
8223 /* VMCS pointer alignment. */
8224 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8225 { /* likely */ }
8226 else
8227 {
8228 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8229 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8230 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8231 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8232 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8233 return VINF_SUCCESS;
8234 }
8235
8236 /* VMCS physical-address width limits. */
8237 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8238 { /* likely */ }
8239 else
8240 {
8241 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8242 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8243 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8244 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8246 return VINF_SUCCESS;
8247 }
8248
8249 /* VMCS is not the VMXON region. */
8250 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8251 { /* likely */ }
8252 else
8253 {
8254 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8256 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8257 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8258 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8259 return VINF_SUCCESS;
8260 }
8261
8262 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8263 restriction imposed by our implementation. */
8264 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8265 { /* likely */ }
8266 else
8267 {
8268 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8269 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8270 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8271 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8273 return VINF_SUCCESS;
8274 }
8275
8276 /* Read just the VMCS revision from the VMCS. */
8277 VMXVMCSREVID VmcsRevId;
8278 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8279 if (RT_SUCCESS(rc))
8280 { /* likely */ }
8281 else
8282 {
8283 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8284 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8285 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8286 return rc;
8287 }
8288
8289 /*
8290 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8291 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8292 */
8293 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8294 && ( !VmcsRevId.n.fIsShadowVmcs
8295 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8296 { /* likely */ }
8297 else
8298 {
8299 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8300 {
8301 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8302 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8303 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8304 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8305 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8306 return VINF_SUCCESS;
8307 }
8308
8309 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8311 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8312 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8313 return VINF_SUCCESS;
8314 }
8315
8316 /*
8317 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8318 * the cache of an existing, current VMCS back to guest memory before loading a new,
8319 * different current VMCS.
8320 */
8321 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8322 {
8323 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8324 {
8325 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8326 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8327 }
8328
8329 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8330 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8331 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8332 if (RT_SUCCESS(rc))
8333 {
8334 /* Notify HM that a new, current VMCS is loaded. */
8335 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8336 }
8337 else
8338 {
8339 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8340 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8341 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8342 return rc;
8343 }
8344 }
8345
8346 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8347 iemVmxVmSucceed(pVCpu);
8348 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8349 return VINF_SUCCESS;
8350}
8351
8352
8353/**
8354 * INVVPID instruction execution worker.
8355 *
8356 * @returns Strict VBox status code.
8357 * @param pVCpu The cross context virtual CPU structure.
8358 * @param cbInstr The instruction length in bytes.
8359 * @param iEffSeg The segment of the invvpid descriptor.
8360 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8361 * @param u64InvvpidType The invalidation type.
8362 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8363 * NULL.
8364 *
8365 * @remarks Common VMX instruction checks are already expected to by the caller,
8366 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8367 */
8368IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8369 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8370{
8371 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8372 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8373 return iemRaiseUndefinedOpcode(pVCpu);
8374
8375 /* Nested-guest intercept. */
8376 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8377 {
8378 if (pExitInfo)
8379 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8380 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8381 }
8382
8383 /* CPL. */
8384 if (pVCpu->iem.s.uCpl != 0)
8385 {
8386 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8387 return iemRaiseGeneralProtectionFault0(pVCpu);
8388 }
8389
8390 /*
8391 * Validate INVVPID invalidation type.
8392 *
8393 * The instruction specifies exactly ONE of the supported invalidation types.
8394 *
8395 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8396 * supported. In theory, it's possible for a CPU to not support flushing individual
8397 * addresses but all the other types or any other combination. We do not take any
8398 * shortcuts here by assuming the types we currently expose to the guest.
8399 */
8400 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8401 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8402 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8403 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8404 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8405 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8406 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8407 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8408 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8409 { /* likely */ }
8410 else
8411 {
8412 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8416 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8417 return VINF_SUCCESS;
8418 }
8419
8420 /*
8421 * Fetch the invvpid descriptor from guest memory.
8422 */
8423 RTUINT128U uDesc;
8424 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8425 if (rcStrict == VINF_SUCCESS)
8426 {
8427 /*
8428 * Validate the descriptor.
8429 */
8430 if (uDesc.s.Lo > 0xfff)
8431 {
8432 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8433 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8434 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8435 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8436 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8437 return VINF_SUCCESS;
8438 }
8439
8440 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8441 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8442 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8443 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8444 switch (u64InvvpidType)
8445 {
8446 case VMXTLBFLUSHVPID_INDIV_ADDR:
8447 {
8448 if (uVpid != 0)
8449 {
8450 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8451 {
8452 /* Invalidate mappings for the linear address tagged with VPID. */
8453 /** @todo PGM support for VPID? Currently just flush everything. */
8454 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8455 iemVmxVmSucceed(pVCpu);
8456 }
8457 else
8458 {
8459 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8461 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8462 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8463 }
8464 }
8465 else
8466 {
8467 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8469 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8470 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8471 }
8472 break;
8473 }
8474
8475 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8476 {
8477 if (uVpid != 0)
8478 {
8479 /* Invalidate all mappings with VPID. */
8480 /** @todo PGM support for VPID? Currently just flush everything. */
8481 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8482 iemVmxVmSucceed(pVCpu);
8483 }
8484 else
8485 {
8486 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8487 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8488 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8489 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8490 }
8491 break;
8492 }
8493
8494 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8495 {
8496 /* Invalidate all mappings with non-zero VPIDs. */
8497 /** @todo PGM support for VPID? Currently just flush everything. */
8498 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8499 iemVmxVmSucceed(pVCpu);
8500 break;
8501 }
8502
8503 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8504 {
8505 if (uVpid != 0)
8506 {
8507 /* Invalidate all mappings with VPID except global translations. */
8508 /** @todo PGM support for VPID? Currently just flush everything. */
8509 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8510 iemVmxVmSucceed(pVCpu);
8511 }
8512 else
8513 {
8514 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8516 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8517 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8518 }
8519 break;
8520 }
8521 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8522 }
8523 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8524 }
8525 return rcStrict;
8526}
8527
8528
8529/**
8530 * VMXON instruction execution worker.
8531 *
8532 * @returns Strict VBox status code.
8533 * @param pVCpu The cross context virtual CPU structure.
8534 * @param cbInstr The instruction length in bytes.
8535 * @param iEffSeg The effective segment register to use with @a
8536 * GCPtrVmxon.
8537 * @param GCPtrVmxon The linear address of the VMXON pointer.
8538 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8539 *
8540 * @remarks Common VMX instruction checks are already expected to by the caller,
8541 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8542 */
8543IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8544 PCVMXVEXITINFO pExitInfo)
8545{
8546 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8547 {
8548 /* CPL. */
8549 if (pVCpu->iem.s.uCpl == 0)
8550 { /* likely */ }
8551 else
8552 {
8553 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8554 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8555 return iemRaiseGeneralProtectionFault0(pVCpu);
8556 }
8557
8558 /* A20M (A20 Masked) mode. */
8559 if (PGMPhysIsA20Enabled(pVCpu))
8560 { /* likely */ }
8561 else
8562 {
8563 Log(("vmxon: A20M mode -> #GP(0)\n"));
8564 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8565 return iemRaiseGeneralProtectionFault0(pVCpu);
8566 }
8567
8568 /* CR0. */
8569 {
8570 /* CR0 MB1 bits. */
8571 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8572 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8573 { /* likely */ }
8574 else
8575 {
8576 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8578 return iemRaiseGeneralProtectionFault0(pVCpu);
8579 }
8580
8581 /* CR0 MBZ bits. */
8582 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8583 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8584 { /* likely */ }
8585 else
8586 {
8587 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8588 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8589 return iemRaiseGeneralProtectionFault0(pVCpu);
8590 }
8591 }
8592
8593 /* CR4. */
8594 {
8595 /* CR4 MB1 bits. */
8596 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8597 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8598 { /* likely */ }
8599 else
8600 {
8601 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8603 return iemRaiseGeneralProtectionFault0(pVCpu);
8604 }
8605
8606 /* CR4 MBZ bits. */
8607 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8608 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8609 { /* likely */ }
8610 else
8611 {
8612 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8613 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8614 return iemRaiseGeneralProtectionFault0(pVCpu);
8615 }
8616 }
8617
8618 /* Feature control MSR's LOCK and VMXON bits. */
8619 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8620 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8621 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8622 { /* likely */ }
8623 else
8624 {
8625 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8627 return iemRaiseGeneralProtectionFault0(pVCpu);
8628 }
8629
8630 /* Get the VMXON pointer from the location specified by the source memory operand. */
8631 RTGCPHYS GCPhysVmxon;
8632 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8633 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8634 { /* likely */ }
8635 else
8636 {
8637 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8638 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8640 return rcStrict;
8641 }
8642
8643 /* VMXON region pointer alignment. */
8644 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8645 { /* likely */ }
8646 else
8647 {
8648 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8649 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8650 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8651 iemVmxVmFailInvalid(pVCpu);
8652 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8653 return VINF_SUCCESS;
8654 }
8655
8656 /* VMXON physical-address width limits. */
8657 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8658 { /* likely */ }
8659 else
8660 {
8661 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8662 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8663 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8664 iemVmxVmFailInvalid(pVCpu);
8665 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8666 return VINF_SUCCESS;
8667 }
8668
8669 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8670 restriction imposed by our implementation. */
8671 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8672 { /* likely */ }
8673 else
8674 {
8675 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8676 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8677 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8678 iemVmxVmFailInvalid(pVCpu);
8679 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8680 return VINF_SUCCESS;
8681 }
8682
8683 /* Read the VMCS revision ID from the VMXON region. */
8684 VMXVMCSREVID VmcsRevId;
8685 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8686 if (RT_SUCCESS(rc))
8687 { /* likely */ }
8688 else
8689 {
8690 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8691 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8692 return rc;
8693 }
8694
8695 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8696 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8697 { /* likely */ }
8698 else
8699 {
8700 /* Revision ID mismatch. */
8701 if (!VmcsRevId.n.fIsShadowVmcs)
8702 {
8703 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8704 VmcsRevId.n.u31RevisionId));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8706 iemVmxVmFailInvalid(pVCpu);
8707 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8708 return VINF_SUCCESS;
8709 }
8710
8711 /* Shadow VMCS disallowed. */
8712 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8714 iemVmxVmFailInvalid(pVCpu);
8715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8716 return VINF_SUCCESS;
8717 }
8718
8719 /*
8720 * Record that we're in VMX operation, block INIT, block and disable A20M.
8721 */
8722 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8723 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8724 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8725
8726 /* Clear address-range monitoring. */
8727 EMMonitorWaitClear(pVCpu);
8728 /** @todo NSTVMX: Intel PT. */
8729
8730 iemVmxVmSucceed(pVCpu);
8731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8732 return VINF_SUCCESS;
8733 }
8734 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8735 {
8736 /* Nested-guest intercept. */
8737 if (pExitInfo)
8738 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8739 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8740 }
8741
8742 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8743
8744 /* CPL. */
8745 if (pVCpu->iem.s.uCpl > 0)
8746 {
8747 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8748 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8749 return iemRaiseGeneralProtectionFault0(pVCpu);
8750 }
8751
8752 /* VMXON when already in VMX root mode. */
8753 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8755 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8756 return VINF_SUCCESS;
8757}
8758
8759
8760/**
8761 * Implements 'VMXOFF'.
8762 *
8763 * @remarks Common VMX instruction checks are already expected to by the caller,
8764 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8765 */
8766IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8767{
8768 /* Nested-guest intercept. */
8769 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8770 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8771
8772 /* CPL. */
8773 if (pVCpu->iem.s.uCpl == 0)
8774 { /* likely */ }
8775 else
8776 {
8777 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8778 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8779 return iemRaiseGeneralProtectionFault0(pVCpu);
8780 }
8781
8782 /* Dual monitor treatment of SMIs and SMM. */
8783 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8784 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8785 { /* likely */ }
8786 else
8787 {
8788 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8790 return VINF_SUCCESS;
8791 }
8792
8793 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8794 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8795 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8796
8797 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8798 { /** @todo NSTVMX: Unblock SMI. */ }
8799
8800 EMMonitorWaitClear(pVCpu);
8801 /** @todo NSTVMX: Unblock and enable A20M. */
8802
8803 iemVmxVmSucceed(pVCpu);
8804 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8805 return VINF_SUCCESS;
8806}
8807
8808
8809/**
8810 * Implements 'VMXON'.
8811 */
8812IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8813{
8814 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8815}
8816
8817
8818/**
8819 * Implements 'VMLAUNCH'.
8820 */
8821IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8822{
8823 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8824}
8825
8826
8827/**
8828 * Implements 'VMRESUME'.
8829 */
8830IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8831{
8832 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8833}
8834
8835
8836/**
8837 * Implements 'VMPTRLD'.
8838 */
8839IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8840{
8841 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8842}
8843
8844
8845/**
8846 * Implements 'VMPTRST'.
8847 */
8848IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8849{
8850 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8851}
8852
8853
8854/**
8855 * Implements 'VMCLEAR'.
8856 */
8857IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8858{
8859 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8860}
8861
8862
8863/**
8864 * Implements 'VMWRITE' register.
8865 */
8866IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8867{
8868 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8869}
8870
8871
8872/**
8873 * Implements 'VMWRITE' memory.
8874 */
8875IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8876{
8877 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8878}
8879
8880
8881/**
8882 * Implements 'VMREAD' register (64-bit).
8883 */
8884IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8885{
8886 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8887}
8888
8889
8890/**
8891 * Implements 'VMREAD' register (32-bit).
8892 */
8893IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8894{
8895 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8896}
8897
8898
8899/**
8900 * Implements 'VMREAD' memory, 64-bit register.
8901 */
8902IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8903{
8904 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8905}
8906
8907
8908/**
8909 * Implements 'VMREAD' memory, 32-bit register.
8910 */
8911IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8912{
8913 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8914}
8915
8916
8917/**
8918 * Implements 'INVVPID'.
8919 */
8920IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8921{
8922 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8923}
8924
8925
8926/**
8927 * Implements VMX's implementation of PAUSE.
8928 */
8929IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8930{
8931 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8932 {
8933 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8934 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8935 return rcStrict;
8936 }
8937
8938 /*
8939 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8940 * a VM-exit, the instruction operates normally.
8941 */
8942 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8943 return VINF_SUCCESS;
8944}
8945
8946#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8947
8948
8949/**
8950 * Implements 'VMCALL'.
8951 */
8952IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8953{
8954#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8955 /* Nested-guest intercept. */
8956 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8957 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8958#endif
8959
8960 /* Join forces with vmmcall. */
8961 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8962}
8963
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