VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 91044

Last change on this file since 91044 was 91044, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 More consistent naming of VMCS fields.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 91044 2021-09-01 07:17:08Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
686 pVmcs->u64RoExitQual.u = u64ExitQual;
687}
688
689
690/**
691 * Sets the VM-exit interruption information field.
692 *
693 * @param pVCpu The cross context virtual CPU structure.
694 * @param uExitIntInfo The VM-exit interruption information.
695 */
696DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
697{
698 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
699 pVmcs->u32RoExitIntInfo = uExitIntInfo;
700}
701
702
703/**
704 * Sets the VM-exit interruption error code.
705 *
706 * @param pVCpu The cross context virtual CPU structure.
707 * @param uErrCode The error code.
708 */
709DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
710{
711 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
712 pVmcs->u32RoExitIntErrCode = uErrCode;
713}
714
715
716/**
717 * Sets the IDT-vectoring information field.
718 *
719 * @param pVCpu The cross context virtual CPU structure.
720 * @param uIdtVectorInfo The IDT-vectoring information.
721 */
722DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
723{
724 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
725 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
726}
727
728
729/**
730 * Sets the IDT-vectoring error code field.
731 *
732 * @param pVCpu The cross context virtual CPU structure.
733 * @param uErrCode The error code.
734 */
735DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
736{
737 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
738 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
739}
740
741
742/**
743 * Sets the VM-exit guest-linear address VMCS field.
744 *
745 * @param pVCpu The cross context virtual CPU structure.
746 * @param uGuestLinearAddr The VM-exit guest-linear address.
747 */
748DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
749{
750 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
751 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
752}
753
754
755/**
756 * Sets the VM-exit guest-physical address VMCS field.
757 *
758 * @param pVCpu The cross context virtual CPU structure.
759 * @param uGuestPhysAddr The VM-exit guest-physical address.
760 */
761DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
762{
763 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
764 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
765}
766
767
768/**
769 * Sets the VM-exit instruction length VMCS field.
770 *
771 * @param pVCpu The cross context virtual CPU structure.
772 * @param cbInstr The VM-exit instruction length in bytes.
773 *
774 * @remarks Callers may clear this field to 0. Hence, this function does not check
775 * the validity of the instruction length.
776 */
777DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
778{
779 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
780 pVmcs->u32RoExitInstrLen = cbInstr;
781}
782
783
784/**
785 * Sets the VM-exit instruction info. VMCS field.
786 *
787 * @param pVCpu The cross context virtual CPU structure.
788 * @param uExitInstrInfo The VM-exit instruction information.
789 */
790DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
791{
792 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
793 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
794}
795
796
797/**
798 * Sets the guest pending-debug exceptions field.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
802 */
803DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
804{
805 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
806 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
807 pVmcs->u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
808}
809
810
811/**
812 * Implements VMSucceed for VMX instruction success.
813 *
814 * @param pVCpu The cross context virtual CPU structure.
815 */
816DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
817{
818 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
819}
820
821
822/**
823 * Implements VMFailInvalid for VMX instruction failure.
824 *
825 * @param pVCpu The cross context virtual CPU structure.
826 */
827DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
828{
829 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
830}
831
832
833/**
834 * Implements VMFail for VMX instruction failure.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param enmInsErr The VM instruction error.
838 */
839DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
840{
841 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
842}
843
844
845/**
846 * Checks if the given auto-load/store MSR area count is valid for the
847 * implementation.
848 *
849 * @returns @c true if it's within the valid limit, @c false otherwise.
850 * @param pVCpu The cross context virtual CPU structure.
851 * @param uMsrCount The MSR area count to check.
852 */
853DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
854{
855 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
856 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
857 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
858 if (uMsrCount <= cMaxSupportedMsrs)
859 return true;
860 return false;
861}
862
863
864/**
865 * Flushes the current VMCS contents back to guest memory.
866 *
867 * @returns VBox status code.
868 * @param pVCpu The cross context virtual CPU structure.
869 */
870DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
871{
872 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
873 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
874 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
875 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
876 return rc;
877}
878
879
880/**
881 * Populates the current VMCS contents from guest memory.
882 *
883 * @returns VBox status code.
884 * @param pVCpu The cross context virtual CPU structure.
885 */
886DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
887{
888 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
889 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
890 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs),
891 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(VMXVVMCS));
892 return rc;
893}
894
895
896/**
897 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
898 *
899 * @param pVCpu The cross context virtual CPU structure.
900 */
901DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
902{
903 iemVmxVmSucceed(pVCpu);
904 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
905}
906
907
908/**
909 * Gets the instruction diagnostic for segment base checks during VM-entry of a
910 * nested-guest.
911 *
912 * @param iSegReg The segment index (X86_SREG_XXX).
913 */
914IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
915{
916 switch (iSegReg)
917 {
918 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
919 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
920 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
921 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
922 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
923 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
924 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
925 }
926}
927
928
929/**
930 * Gets the instruction diagnostic for segment base checks during VM-entry of a
931 * nested-guest that is in Virtual-8086 mode.
932 *
933 * @param iSegReg The segment index (X86_SREG_XXX).
934 */
935IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
936{
937 switch (iSegReg)
938 {
939 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
940 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
941 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
942 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
943 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
944 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
945 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
946 }
947}
948
949
950/**
951 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
952 * nested-guest that is in Virtual-8086 mode.
953 *
954 * @param iSegReg The segment index (X86_SREG_XXX).
955 */
956IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
957{
958 switch (iSegReg)
959 {
960 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
961 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
962 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
963 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
964 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
965 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
966 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
967 }
968}
969
970
971/**
972 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
973 * nested-guest that is in Virtual-8086 mode.
974 *
975 * @param iSegReg The segment index (X86_SREG_XXX).
976 */
977IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
978{
979 switch (iSegReg)
980 {
981 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
982 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
983 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
984 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
985 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
986 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
987 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
988 }
989}
990
991
992/**
993 * Gets the instruction diagnostic for segment attributes reserved bits failure
994 * during VM-entry of a nested-guest.
995 *
996 * @param iSegReg The segment index (X86_SREG_XXX).
997 */
998IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
999{
1000 switch (iSegReg)
1001 {
1002 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1003 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1004 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1005 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1006 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1007 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1008 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1009 }
1010}
1011
1012
1013/**
1014 * Gets the instruction diagnostic for segment attributes descriptor-type
1015 * (code/segment or system) failure during VM-entry of a nested-guest.
1016 *
1017 * @param iSegReg The segment index (X86_SREG_XXX).
1018 */
1019IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1020{
1021 switch (iSegReg)
1022 {
1023 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1024 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1025 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1026 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1027 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1028 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1029 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1030 }
1031}
1032
1033
1034/**
1035 * Gets the instruction diagnostic for segment attributes descriptor-type
1036 * (code/segment or system) failure during VM-entry of a nested-guest.
1037 *
1038 * @param iSegReg The segment index (X86_SREG_XXX).
1039 */
1040IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1041{
1042 switch (iSegReg)
1043 {
1044 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1045 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1046 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1047 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1048 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1049 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1050 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1051 }
1052}
1053
1054
1055/**
1056 * Gets the instruction diagnostic for segment attribute granularity failure during
1057 * VM-entry of a nested-guest.
1058 *
1059 * @param iSegReg The segment index (X86_SREG_XXX).
1060 */
1061IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1062{
1063 switch (iSegReg)
1064 {
1065 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1066 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1067 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1068 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1069 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1070 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1071 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1072 }
1073}
1074
1075/**
1076 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1077 * VM-entry of a nested-guest.
1078 *
1079 * @param iSegReg The segment index (X86_SREG_XXX).
1080 */
1081IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1082{
1083 switch (iSegReg)
1084 {
1085 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1086 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1087 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1088 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1089 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1090 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1091 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1092 }
1093}
1094
1095
1096/**
1097 * Gets the instruction diagnostic for segment attribute type accessed failure
1098 * during VM-entry of a nested-guest.
1099 *
1100 * @param iSegReg The segment index (X86_SREG_XXX).
1101 */
1102IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1103{
1104 switch (iSegReg)
1105 {
1106 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1107 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1108 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1109 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1110 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1111 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1112 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1113 }
1114}
1115
1116
1117/**
1118 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1119 * failure during VM-entry of a nested-guest.
1120 *
1121 * @param iSegReg The PDPTE entry index.
1122 */
1123IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1124{
1125 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1126 switch (iPdpte)
1127 {
1128 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1129 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1130 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1131 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1132 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1133 }
1134}
1135
1136
1137/**
1138 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1139 * failure during VM-exit of a nested-guest.
1140 *
1141 * @param iSegReg The PDPTE entry index.
1142 */
1143IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1144{
1145 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1146 switch (iPdpte)
1147 {
1148 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1149 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1150 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1151 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1152 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1153 }
1154}
1155
1156
1157/**
1158 * Saves the guest control registers, debug registers and some MSRs are part of
1159 * VM-exit.
1160 *
1161 * @param pVCpu The cross context virtual CPU structure.
1162 */
1163IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1164{
1165 /*
1166 * Saves the guest control registers, debug registers and some MSRs.
1167 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1168 */
1169 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1170
1171 /* Save control registers. */
1172 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1173 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1174 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1175
1176 /* Save SYSENTER CS, ESP, EIP. */
1177 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1178 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1179 {
1180 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1181 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1182 }
1183 else
1184 {
1185 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1186 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1187 }
1188
1189 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1190 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1191 {
1192 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1193 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1194 }
1195
1196 /* Save PAT MSR. */
1197 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1198 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1199
1200 /* Save EFER MSR. */
1201 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1202 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1203
1204 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1205 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1206
1207 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1208}
1209
1210
1211/**
1212 * Saves the guest force-flags in preparation of entering the nested-guest.
1213 *
1214 * @param pVCpu The cross context virtual CPU structure.
1215 */
1216IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1217{
1218 /* We shouldn't be called multiple times during VM-entry. */
1219 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1220
1221 /* MTF should not be set outside VMX non-root mode. */
1222 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1223
1224 /*
1225 * Preserve the required force-flags.
1226 *
1227 * We cache and clear force-flags that would affect the execution of the
1228 * nested-guest. Cached flags are then restored while returning to the guest
1229 * if necessary.
1230 *
1231 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1232 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1233 * instruction. Interrupt inhibition for any nested-guest instruction
1234 * is supplied by the guest-interruptibility state VMCS field and will
1235 * be set up as part of loading the guest state.
1236 *
1237 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1238 * successful VM-entry (due to invalid guest-state) need to continue
1239 * blocking NMIs if it was in effect before VM-entry.
1240 *
1241 * - MTF need not be preserved as it's used only in VMX non-root mode and
1242 * is supplied through the VM-execution controls.
1243 *
1244 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1245 * we will be able to generate interrupts that may cause VM-exits for
1246 * the nested-guest.
1247 */
1248 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1249}
1250
1251
1252/**
1253 * Restores the guest force-flags in preparation of exiting the nested-guest.
1254 *
1255 * @param pVCpu The cross context virtual CPU structure.
1256 */
1257IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1258{
1259 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1260 {
1261 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1262 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1263 }
1264}
1265
1266
1267/**
1268 * Perform a VMX transition updated PGM, IEM and CPUM.
1269 *
1270 * @param pVCpu The cross context virtual CPU structure.
1271 */
1272IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1273{
1274 /*
1275 * Inform PGM about paging mode changes.
1276 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1277 * see comment in iemMemPageTranslateAndCheckAccess().
1278 */
1279 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1280# ifdef IN_RING3
1281 Assert(rc != VINF_PGM_CHANGE_MODE);
1282# endif
1283 AssertRCReturn(rc, rc);
1284
1285 /* Inform CPUM (recompiler), can later be removed. */
1286 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1287
1288 /*
1289 * Flush the TLB with new CR3. This is required in case the PGM mode change
1290 * above doesn't actually change anything.
1291 */
1292 if (rc == VINF_SUCCESS)
1293 {
1294 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1295 AssertRCReturn(rc, rc);
1296 }
1297
1298 /* Re-initialize IEM cache/state after the drastic mode switch. */
1299 iemReInitExec(pVCpu);
1300 return rc;
1301}
1302
1303
1304/**
1305 * Calculates the current VMX-preemption timer value.
1306 *
1307 * @returns The current VMX-preemption timer value.
1308 * @param pVCpu The cross context virtual CPU structure.
1309 */
1310IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1311{
1312 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1313 Assert(pVmcs);
1314
1315 /*
1316 * Assume the following:
1317 * PreemptTimerShift = 5
1318 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1319 * EntryTick = 50000 (TSC at time of VM-entry)
1320 *
1321 * CurTick Delta PreemptTimerVal
1322 * ----------------------------------
1323 * 60000 10000 2
1324 * 80000 30000 1
1325 * 90000 40000 0 -> VM-exit.
1326 *
1327 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1328 * The saved VMX-preemption timer value is calculated as follows:
1329 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1330 * E.g.:
1331 * Delta = 10000
1332 * Tmp = 10000 / (2 * 10000) = 0.5
1333 * NewPt = 2 - 0.5 = 2
1334 * Delta = 30000
1335 * Tmp = 30000 / (2 * 10000) = 1.5
1336 * NewPt = 2 - 1.5 = 1
1337 * Delta = 40000
1338 * Tmp = 40000 / 20000 = 2
1339 * NewPt = 2 - 2 = 0
1340 */
1341 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1342 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1343 if (uVmcsPreemptVal > 0)
1344 {
1345 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1346 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1347 uint64_t const uDelta = uCurTick - uEntryTick;
1348 uint32_t const uPreemptTimer = uVmcsPreemptVal
1349 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1350 return uPreemptTimer;
1351 }
1352 return 0;
1353}
1354
1355
1356/**
1357 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1358 *
1359 * @param pVCpu The cross context virtual CPU structure.
1360 */
1361IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1362{
1363 /*
1364 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1365 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1366 */
1367 /* CS, SS, ES, DS, FS, GS. */
1368 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1369 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1370 {
1371 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1372 if (!pSelReg->Attr.n.u1Unusable)
1373 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1374 else
1375 {
1376 /*
1377 * For unusable segments the attributes are undefined except for CS and SS.
1378 * For the rest we don't bother preserving anything but the unusable bit.
1379 */
1380 switch (iSegReg)
1381 {
1382 case X86_SREG_CS:
1383 pVmcs->GuestCs = pSelReg->Sel;
1384 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1385 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1386 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1387 | X86DESCATTR_UNUSABLE);
1388 break;
1389
1390 case X86_SREG_SS:
1391 pVmcs->GuestSs = pSelReg->Sel;
1392 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1393 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1394 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1395 break;
1396
1397 case X86_SREG_DS:
1398 pVmcs->GuestDs = pSelReg->Sel;
1399 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1400 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1401 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1402 break;
1403
1404 case X86_SREG_ES:
1405 pVmcs->GuestEs = pSelReg->Sel;
1406 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1407 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1408 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1409 break;
1410
1411 case X86_SREG_FS:
1412 pVmcs->GuestFs = pSelReg->Sel;
1413 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1414 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1415 break;
1416
1417 case X86_SREG_GS:
1418 pVmcs->GuestGs = pSelReg->Sel;
1419 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1420 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1421 break;
1422 }
1423 }
1424 }
1425
1426 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1427 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1428 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1429 | X86DESCATTR_UNUSABLE;
1430 /* LDTR. */
1431 {
1432 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1433 pVmcs->GuestLdtr = pSelReg->Sel;
1434 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1435 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1436 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1437 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1438 }
1439
1440 /* TR. */
1441 {
1442 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1443 pVmcs->GuestTr = pSelReg->Sel;
1444 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1445 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1446 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1447 }
1448
1449 /* GDTR. */
1450 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1451 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1452
1453 /* IDTR. */
1454 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1455 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1456}
1457
1458
1459/**
1460 * Saves guest non-register state as part of VM-exit.
1461 *
1462 * @param pVCpu The cross context virtual CPU structure.
1463 * @param uExitReason The VM-exit reason.
1464 */
1465IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1466{
1467 /*
1468 * Save guest non-register state.
1469 * See Intel spec. 27.3.4 "Saving Non-Register State".
1470 */
1471 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1472
1473 /*
1474 * Activity state.
1475 * Most VM-exits will occur in the active state. However, if the first instruction
1476 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1477 * the VM-exit will be from the HLT activity state.
1478 *
1479 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1480 */
1481 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1482 * not? */
1483 EMSTATE const enmActivityState = EMGetState(pVCpu);
1484 switch (enmActivityState)
1485 {
1486 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1487 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1488 }
1489
1490 /*
1491 * Interruptibility-state.
1492 */
1493 /* NMI. */
1494 pVmcs->u32GuestIntrState = 0;
1495 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1496 {
1497 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1498 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1499 }
1500 else
1501 {
1502 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1503 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1504 }
1505
1506 /* Blocking-by-STI. */
1507 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1508 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1509 {
1510 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1511 * currently. */
1512 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1513 }
1514 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1515
1516 /*
1517 * Pending debug exceptions.
1518 *
1519 * For VM-exits where it is not applicable, we can safely zero out the field.
1520 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1521 */
1522 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1523 && uExitReason != VMX_EXIT_SMI
1524 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1525 && !VMXIsVmexitTrapLike(uExitReason))
1526 {
1527 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1528 * block-by-MovSS is in effect. */
1529 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1530 }
1531
1532 /*
1533 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1534 *
1535 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1536 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1537 */
1538 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1539 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1540 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1541
1542 /* PDPTEs. */
1543 /* We don't support EPT yet. */
1544 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1545 pVmcs->u64GuestPdpte0.u = 0;
1546 pVmcs->u64GuestPdpte1.u = 0;
1547 pVmcs->u64GuestPdpte2.u = 0;
1548 pVmcs->u64GuestPdpte3.u = 0;
1549}
1550
1551
1552/**
1553 * Saves the guest-state as part of VM-exit.
1554 *
1555 * @returns VBox status code.
1556 * @param pVCpu The cross context virtual CPU structure.
1557 * @param uExitReason The VM-exit reason.
1558 */
1559IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1560{
1561 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1562 Assert(pVmcs);
1563
1564 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1565 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1566
1567 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1568 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1569 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1570
1571 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1572}
1573
1574
1575/**
1576 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1577 *
1578 * @returns VBox status code.
1579 * @param pVCpu The cross context virtual CPU structure.
1580 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1581 */
1582IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1583{
1584 /*
1585 * Save guest MSRs.
1586 * See Intel spec. 27.4 "Saving MSRs".
1587 */
1588 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1589 const char *const pszFailure = "VMX-abort";
1590
1591 /*
1592 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1593 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1594 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1595 */
1596 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1597 if (!cMsrs)
1598 return VINF_SUCCESS;
1599
1600 /*
1601 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1602 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1603 * implementation causes a VMX-abort followed by a triple-fault.
1604 */
1605 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1606 if (fIsMsrCountValid)
1607 { /* likely */ }
1608 else
1609 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1610
1611 /*
1612 * Optimization if the nested hypervisor is using the same guest-physical page for both
1613 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1614 */
1615 PVMXAUTOMSR pMsrArea;
1616 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1617 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1618 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1619 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1620 else
1621 {
1622 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1623 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1624 if (RT_SUCCESS(rc))
1625 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1626 else
1627 {
1628 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1629 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1630 }
1631 }
1632
1633 /*
1634 * Update VM-exit MSR store area.
1635 */
1636 PVMXAUTOMSR pMsr = pMsrArea;
1637 Assert(pMsr);
1638 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1639 {
1640 if ( !pMsr->u32Reserved
1641 && pMsr->u32Msr != MSR_IA32_SMBASE
1642 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1643 {
1644 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1645 if (rcStrict == VINF_SUCCESS)
1646 continue;
1647
1648 /*
1649 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1650 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1651 * recording the MSR index in the auxiliary info. field and indicated further by our
1652 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1653 * if possible, or come up with a better, generic solution.
1654 */
1655 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1656 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1657 ? kVmxVDiag_Vmexit_MsrStoreRing3
1658 : kVmxVDiag_Vmexit_MsrStore;
1659 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1660 }
1661 else
1662 {
1663 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1664 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1665 }
1666 }
1667
1668 /*
1669 * Commit the VM-exit MSR store are to guest memory.
1670 */
1671 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1672 if (RT_SUCCESS(rc))
1673 return VINF_SUCCESS;
1674
1675 NOREF(uExitReason);
1676 NOREF(pszFailure);
1677
1678 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1679 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1680}
1681
1682
1683/**
1684 * Performs a VMX abort (due to an fatal error during VM-exit).
1685 *
1686 * @returns Strict VBox status code.
1687 * @param pVCpu The cross context virtual CPU structure.
1688 * @param enmAbort The VMX abort reason.
1689 */
1690IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1691{
1692 /*
1693 * Perform the VMX abort.
1694 * See Intel spec. 27.7 "VMX Aborts".
1695 */
1696 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1697
1698 /* We don't support SMX yet. */
1699 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1700 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1701 {
1702 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1703 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1704 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1705 }
1706
1707 return VINF_EM_TRIPLE_FAULT;
1708}
1709
1710
1711/**
1712 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1713 *
1714 * @param pVCpu The cross context virtual CPU structure.
1715 */
1716IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1717{
1718 /*
1719 * Load host control registers, debug registers and MSRs.
1720 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1721 */
1722 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1723 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1724
1725 /* CR0. */
1726 {
1727 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1728 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1729 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1730 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1731 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1732 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1733 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1734
1735 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1736 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1737 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1738 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1739 }
1740
1741 /* CR4. */
1742 {
1743 /* CR4 fixed bits are not modified. */
1744 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1745 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1746 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1747 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1748 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1749 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1750 if (fHostInLongMode)
1751 uValidHostCr4 |= X86_CR4_PAE;
1752 else
1753 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1754
1755 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1756 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1757 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1758 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1759 }
1760
1761 /* CR3 (host value validated while checking host-state during VM-entry). */
1762 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1763
1764 /* DR7. */
1765 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1766
1767 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1768
1769 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1770 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1771 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1772 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1773
1774 /* FS, GS bases are loaded later while we load host segment registers. */
1775
1776 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1777 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1778 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1779 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1780 {
1781 if (fHostInLongMode)
1782 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1783 else
1784 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1785 }
1786
1787 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1788
1789 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1790 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1791 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1792
1793 /* We don't support IA32_BNDCFGS MSR yet. */
1794}
1795
1796
1797/**
1798 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1799 *
1800 * @param pVCpu The cross context virtual CPU structure.
1801 */
1802IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1803{
1804 /*
1805 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1806 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1807 *
1808 * Warning! Be careful to not touch fields that are reserved by VT-x,
1809 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1810 */
1811 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1812 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1813
1814 /* CS, SS, ES, DS, FS, GS. */
1815 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1816 {
1817 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1818 bool const fUnusable = RT_BOOL(HostSel == 0);
1819 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1820
1821 /* Selector. */
1822 pSelReg->Sel = HostSel;
1823 pSelReg->ValidSel = HostSel;
1824 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1825
1826 /* Limit. */
1827 pSelReg->u32Limit = 0xffffffff;
1828
1829 /* Base. */
1830 pSelReg->u64Base = 0;
1831
1832 /* Attributes. */
1833 if (iSegReg == X86_SREG_CS)
1834 {
1835 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1836 pSelReg->Attr.n.u1DescType = 1;
1837 pSelReg->Attr.n.u2Dpl = 0;
1838 pSelReg->Attr.n.u1Present = 1;
1839 pSelReg->Attr.n.u1Long = fHostInLongMode;
1840 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1841 pSelReg->Attr.n.u1Granularity = 1;
1842 Assert(!pSelReg->Attr.n.u1Unusable);
1843 Assert(!fUnusable);
1844 }
1845 else
1846 {
1847 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1848 pSelReg->Attr.n.u1DescType = 1;
1849 pSelReg->Attr.n.u2Dpl = 0;
1850 pSelReg->Attr.n.u1Present = 1;
1851 pSelReg->Attr.n.u1DefBig = 1;
1852 pSelReg->Attr.n.u1Granularity = 1;
1853 pSelReg->Attr.n.u1Unusable = fUnusable;
1854 }
1855 }
1856
1857 /* FS base. */
1858 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1859 || fHostInLongMode)
1860 {
1861 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1862 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1863 }
1864
1865 /* GS base. */
1866 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1867 || fHostInLongMode)
1868 {
1869 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1870 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1871 }
1872
1873 /* TR. */
1874 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1875 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1876 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1877 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1878 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1879 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1880 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1881 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1882 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1883 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1884 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1885 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1886 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1887
1888 /* LDTR (Warning! do not touch the base and limits here). */
1889 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1890 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1891 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1892 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1893
1894 /* GDTR. */
1895 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1896 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1897 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1898
1899 /* IDTR.*/
1900 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1901 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1902 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1903}
1904
1905
1906/**
1907 * Checks host PDPTes as part of VM-exit.
1908 *
1909 * @param pVCpu The cross context virtual CPU structure.
1910 * @param uExitReason The VM-exit reason (for logging purposes).
1911 */
1912IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1913{
1914 /*
1915 * Check host PDPTEs.
1916 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1917 */
1918 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1919 const char *const pszFailure = "VMX-abort";
1920 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1921
1922 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1923 && !fHostInLongMode)
1924 {
1925 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1926 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1927 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1928 if (RT_SUCCESS(rc))
1929 {
1930 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1931 {
1932 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1933 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1934 { /* likely */ }
1935 else
1936 {
1937 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1938 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1939 }
1940 }
1941 }
1942 else
1943 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1944 }
1945
1946 NOREF(pszFailure);
1947 NOREF(uExitReason);
1948 return VINF_SUCCESS;
1949}
1950
1951
1952/**
1953 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1954 *
1955 * @returns VBox status code.
1956 * @param pVCpu The cross context virtual CPU structure.
1957 * @param pszInstr The VMX instruction name (for logging purposes).
1958 */
1959IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1960{
1961 /*
1962 * Load host MSRs.
1963 * See Intel spec. 27.6 "Loading MSRs".
1964 */
1965 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1966 const char *const pszFailure = "VMX-abort";
1967
1968 /*
1969 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1970 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1971 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1972 */
1973 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1974 if (!cMsrs)
1975 return VINF_SUCCESS;
1976
1977 /*
1978 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1979 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1980 * implementation causes a VMX-abort followed by a triple-fault.
1981 */
1982 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1983 if (fIsMsrCountValid)
1984 { /* likely */ }
1985 else
1986 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1987
1988 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1989 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1990 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1991 if (RT_SUCCESS(rc))
1992 {
1993 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1994 Assert(pMsr);
1995 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1996 {
1997 if ( !pMsr->u32Reserved
1998 && pMsr->u32Msr != MSR_K8_FS_BASE
1999 && pMsr->u32Msr != MSR_K8_GS_BASE
2000 && pMsr->u32Msr != MSR_K6_EFER
2001 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2002 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2003 {
2004 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2005 if (rcStrict == VINF_SUCCESS)
2006 continue;
2007
2008 /*
2009 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2010 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2011 * recording the MSR index in the auxiliary info. field and indicated further by our
2012 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2013 * if possible, or come up with a better, generic solution.
2014 */
2015 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2016 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2017 ? kVmxVDiag_Vmexit_MsrLoadRing3
2018 : kVmxVDiag_Vmexit_MsrLoad;
2019 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2020 }
2021 else
2022 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2023 }
2024 }
2025 else
2026 {
2027 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2028 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2029 }
2030
2031 NOREF(uExitReason);
2032 NOREF(pszFailure);
2033 return VINF_SUCCESS;
2034}
2035
2036
2037/**
2038 * Loads the host state as part of VM-exit.
2039 *
2040 * @returns Strict VBox status code.
2041 * @param pVCpu The cross context virtual CPU structure.
2042 * @param uExitReason The VM-exit reason (for logging purposes).
2043 */
2044IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2045{
2046 /*
2047 * Load host state.
2048 * See Intel spec. 27.5 "Loading Host State".
2049 */
2050 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2051 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2052
2053 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2054 if ( CPUMIsGuestInLongMode(pVCpu)
2055 && !fHostInLongMode)
2056 {
2057 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2058 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2059 }
2060
2061 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2062 iemVmxVmexitLoadHostSegRegs(pVCpu);
2063
2064 /*
2065 * Load host RIP, RSP and RFLAGS.
2066 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2067 */
2068 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2069 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2070 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2071
2072 /* Clear address range monitoring. */
2073 EMMonitorWaitClear(pVCpu);
2074
2075 /* Perform the VMX transition (PGM updates). */
2076 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2077 if (rcStrict == VINF_SUCCESS)
2078 {
2079 /* Check host PDPTEs (only when we've fully switched page tables_. */
2080 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2081 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2082 if (RT_FAILURE(rc))
2083 {
2084 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2085 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2086 }
2087 }
2088 else if (RT_SUCCESS(rcStrict))
2089 {
2090 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2091 uExitReason));
2092 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2093 }
2094 else
2095 {
2096 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2097 return VBOXSTRICTRC_VAL(rcStrict);
2098 }
2099
2100 Assert(rcStrict == VINF_SUCCESS);
2101
2102 /* Load MSRs from the VM-exit auto-load MSR area. */
2103 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2104 if (RT_FAILURE(rc))
2105 {
2106 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2107 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2108 }
2109 return VINF_SUCCESS;
2110}
2111
2112
2113/**
2114 * Gets VM-exit instruction information along with any displacement for an
2115 * instruction VM-exit.
2116 *
2117 * @returns The VM-exit instruction information.
2118 * @param pVCpu The cross context virtual CPU structure.
2119 * @param uExitReason The VM-exit reason.
2120 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2121 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2122 * NULL.
2123 */
2124IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2125{
2126 RTGCPTR GCPtrDisp;
2127 VMXEXITINSTRINFO ExitInstrInfo;
2128 ExitInstrInfo.u = 0;
2129
2130 /*
2131 * Get and parse the ModR/M byte from our decoded opcodes.
2132 */
2133 uint8_t bRm;
2134 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2135 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2136 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2137 {
2138 /*
2139 * ModR/M indicates register addressing.
2140 *
2141 * The primary/secondary register operands are reported in the iReg1 or iReg2
2142 * fields depending on whether it is a read/write form.
2143 */
2144 uint8_t idxReg1;
2145 uint8_t idxReg2;
2146 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2147 {
2148 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2149 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2150 }
2151 else
2152 {
2153 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2154 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2155 }
2156 ExitInstrInfo.All.u2Scaling = 0;
2157 ExitInstrInfo.All.iReg1 = idxReg1;
2158 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2159 ExitInstrInfo.All.fIsRegOperand = 1;
2160 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2161 ExitInstrInfo.All.iSegReg = 0;
2162 ExitInstrInfo.All.iIdxReg = 0;
2163 ExitInstrInfo.All.fIdxRegInvalid = 1;
2164 ExitInstrInfo.All.iBaseReg = 0;
2165 ExitInstrInfo.All.fBaseRegInvalid = 1;
2166 ExitInstrInfo.All.iReg2 = idxReg2;
2167
2168 /* Displacement not applicable for register addressing. */
2169 GCPtrDisp = 0;
2170 }
2171 else
2172 {
2173 /*
2174 * ModR/M indicates memory addressing.
2175 */
2176 uint8_t uScale = 0;
2177 bool fBaseRegValid = false;
2178 bool fIdxRegValid = false;
2179 uint8_t iBaseReg = 0;
2180 uint8_t iIdxReg = 0;
2181 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2182 {
2183 /*
2184 * Parse the ModR/M, displacement for 16-bit addressing mode.
2185 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2186 */
2187 uint16_t u16Disp = 0;
2188 uint8_t const offDisp = offModRm + sizeof(bRm);
2189 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2190 {
2191 /* Displacement without any registers. */
2192 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2193 }
2194 else
2195 {
2196 /* Register (index and base). */
2197 switch (bRm & X86_MODRM_RM_MASK)
2198 {
2199 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2200 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2201 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2202 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2203 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2204 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2205 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2206 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2207 }
2208
2209 /* Register + displacement. */
2210 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2211 {
2212 case 0: break;
2213 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2214 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2215 default:
2216 {
2217 /* Register addressing, handled at the beginning. */
2218 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2219 break;
2220 }
2221 }
2222 }
2223
2224 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2225 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2226 }
2227 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2228 {
2229 /*
2230 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2231 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2232 */
2233 uint32_t u32Disp = 0;
2234 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2235 {
2236 /* Displacement without any registers. */
2237 uint8_t const offDisp = offModRm + sizeof(bRm);
2238 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2239 }
2240 else
2241 {
2242 /* Register (and perhaps scale, index and base). */
2243 uint8_t offDisp = offModRm + sizeof(bRm);
2244 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2245 if (iBaseReg == 4)
2246 {
2247 /* An SIB byte follows the ModR/M byte, parse it. */
2248 uint8_t bSib;
2249 uint8_t const offSib = offModRm + sizeof(bRm);
2250 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2251
2252 /* A displacement may follow SIB, update its offset. */
2253 offDisp += sizeof(bSib);
2254
2255 /* Get the scale. */
2256 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2257
2258 /* Get the index register. */
2259 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2260 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2261
2262 /* Get the base register. */
2263 iBaseReg = bSib & X86_SIB_BASE_MASK;
2264 fBaseRegValid = true;
2265 if (iBaseReg == 5)
2266 {
2267 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2268 {
2269 /* Mod is 0 implies a 32-bit displacement with no base. */
2270 fBaseRegValid = false;
2271 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2272 }
2273 else
2274 {
2275 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2276 iBaseReg = X86_GREG_xBP;
2277 }
2278 }
2279 }
2280
2281 /* Register + displacement. */
2282 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2283 {
2284 case 0: /* Handled above */ break;
2285 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2286 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2287 default:
2288 {
2289 /* Register addressing, handled at the beginning. */
2290 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2291 break;
2292 }
2293 }
2294 }
2295
2296 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2297 }
2298 else
2299 {
2300 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2301
2302 /*
2303 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2304 * See Intel instruction spec. 2.2 "IA-32e Mode".
2305 */
2306 uint64_t u64Disp = 0;
2307 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2308 if (fRipRelativeAddr)
2309 {
2310 /*
2311 * RIP-relative addressing mode.
2312 *
2313 * The displacement is 32-bit signed implying an offset range of +/-2G.
2314 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2315 */
2316 uint8_t const offDisp = offModRm + sizeof(bRm);
2317 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2318 }
2319 else
2320 {
2321 uint8_t offDisp = offModRm + sizeof(bRm);
2322
2323 /*
2324 * Register (and perhaps scale, index and base).
2325 *
2326 * REX.B extends the most-significant bit of the base register. However, REX.B
2327 * is ignored while determining whether an SIB follows the opcode. Hence, we
2328 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2329 *
2330 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2331 */
2332 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2333 if (iBaseReg == 4)
2334 {
2335 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2336 uint8_t bSib;
2337 uint8_t const offSib = offModRm + sizeof(bRm);
2338 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2339
2340 /* Displacement may follow SIB, update its offset. */
2341 offDisp += sizeof(bSib);
2342
2343 /* Get the scale. */
2344 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2345
2346 /* Get the index. */
2347 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2348 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2349
2350 /* Get the base. */
2351 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2352 fBaseRegValid = true;
2353 if (iBaseReg == 5)
2354 {
2355 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2356 {
2357 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2358 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2359 }
2360 else
2361 {
2362 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2363 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2364 }
2365 }
2366 }
2367 iBaseReg |= pVCpu->iem.s.uRexB;
2368
2369 /* Register + displacement. */
2370 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2371 {
2372 case 0: /* Handled above */ break;
2373 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2374 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2375 default:
2376 {
2377 /* Register addressing, handled at the beginning. */
2378 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2379 break;
2380 }
2381 }
2382 }
2383
2384 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2385 }
2386
2387 /*
2388 * The primary or secondary register operand is reported in iReg2 depending
2389 * on whether the primary operand is in read/write form.
2390 */
2391 uint8_t idxReg2;
2392 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2393 {
2394 idxReg2 = bRm & X86_MODRM_RM_MASK;
2395 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2396 idxReg2 |= pVCpu->iem.s.uRexB;
2397 }
2398 else
2399 {
2400 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2401 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2402 idxReg2 |= pVCpu->iem.s.uRexReg;
2403 }
2404 ExitInstrInfo.All.u2Scaling = uScale;
2405 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2406 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2407 ExitInstrInfo.All.fIsRegOperand = 0;
2408 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2409 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2410 ExitInstrInfo.All.iIdxReg = iIdxReg;
2411 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2412 ExitInstrInfo.All.iBaseReg = iBaseReg;
2413 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2414 ExitInstrInfo.All.iReg2 = idxReg2;
2415 }
2416
2417 /*
2418 * Handle exceptions to the norm for certain instructions.
2419 * (e.g. some instructions convey an instruction identity in place of iReg2).
2420 */
2421 switch (uExitReason)
2422 {
2423 case VMX_EXIT_GDTR_IDTR_ACCESS:
2424 {
2425 Assert(VMXINSTRID_IS_VALID(uInstrId));
2426 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2427 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2428 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2429 break;
2430 }
2431
2432 case VMX_EXIT_LDTR_TR_ACCESS:
2433 {
2434 Assert(VMXINSTRID_IS_VALID(uInstrId));
2435 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2436 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2437 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2438 break;
2439 }
2440
2441 case VMX_EXIT_RDRAND:
2442 case VMX_EXIT_RDSEED:
2443 {
2444 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2445 break;
2446 }
2447 }
2448
2449 /* Update displacement and return the constructed VM-exit instruction information field. */
2450 if (pGCPtrDisp)
2451 *pGCPtrDisp = GCPtrDisp;
2452
2453 return ExitInstrInfo.u;
2454}
2455
2456
2457/**
2458 * VMX VM-exit handler.
2459 *
2460 * @returns Strict VBox status code.
2461 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2462 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2463 * triple-fault.
2464 *
2465 * @param pVCpu The cross context virtual CPU structure.
2466 * @param uExitReason The VM-exit reason.
2467 * @param u64ExitQual The Exit qualification.
2468 */
2469IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2470{
2471# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2472 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2473 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2474 return VERR_IEM_IPE_7;
2475# else
2476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2477 Assert(pVmcs);
2478
2479 /*
2480 * Import all the guest-CPU state.
2481 *
2482 * HM on returning to guest execution would have to reset up a whole lot of state
2483 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2484 * the state and flag reloading the entire state on re-entry. So import the entire
2485 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2486 */
2487 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2488
2489 /*
2490 * Ensure VM-entry interruption information valid bit is cleared.
2491 *
2492 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2493 * by invalid-guest state or machine-check exceptions) also clear this bit.
2494 *
2495 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2496 */
2497 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2498 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2499
2500 /*
2501 * Update the VM-exit reason and Exit qualification.
2502 * Other VMCS read-only data fields are expected to be updated by the caller already.
2503 */
2504 pVmcs->u32RoExitReason = uExitReason;
2505 pVmcs->u64RoExitQual.u = u64ExitQual;
2506
2507 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2508 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2509 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2510
2511 /*
2512 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2513 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2514 */
2515 {
2516 uint8_t uVector;
2517 uint32_t fFlags;
2518 uint32_t uErrCode;
2519 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2520 if (fInEventDelivery)
2521 {
2522 /*
2523 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2524 * caused by a triple-fault or the original event results in a double-fault that
2525 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2526 * original event information into the IDT-vectoring information fields.
2527 *
2528 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2529 */
2530 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2531 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2532 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2533 {
2534 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2535 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2536 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2537 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2538 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2539 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2540 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2541 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2542 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2543 pVCpu->cpum.GstCtx.cr2));
2544 }
2545 }
2546 }
2547
2548 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2549 Assert(pVmcs->u64RoIoRcx.u == 0);
2550 Assert(pVmcs->u64RoIoRsi.u == 0);
2551 Assert(pVmcs->u64RoIoRdi.u == 0);
2552 Assert(pVmcs->u64RoIoRip.u == 0);
2553
2554 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2555 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2556 {
2557 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2558 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2559 }
2560
2561 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2562 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2563
2564 /*
2565 * Save the guest state back into the VMCS.
2566 * We only need to save the state when the VM-entry was successful.
2567 */
2568 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2569 if (!fVmentryFailed)
2570 {
2571 /*
2572 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2573 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2574 *
2575 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2576 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2577 * as guest-CPU state would not been modified. Hence for now, we do this only when
2578 * the VM-entry succeeded.
2579 */
2580 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2581 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2582 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2583 {
2584 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2585 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2586 else
2587 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2588 }
2589
2590 /*
2591 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2592 * occurs in enclave mode/SMM which we don't support yet.
2593 *
2594 * If we ever add support for it, we can pass just the lower bits to the functions
2595 * below, till then an assert should suffice.
2596 */
2597 Assert(!RT_HI_U16(uExitReason));
2598
2599 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2600 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2601 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2602 if (RT_SUCCESS(rc))
2603 { /* likely */ }
2604 else
2605 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2606
2607 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2608 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2609 }
2610 else
2611 {
2612 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2613 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2614 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2615 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2616 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2617 }
2618
2619 /*
2620 * Stop any running VMX-preemption timer if necessary.
2621 */
2622 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2623 CPUMStopGuestVmxPremptTimer(pVCpu);
2624
2625 /*
2626 * Clear any pending VMX nested-guest force-flags.
2627 * These force-flags have no effect on (outer) guest execution and will
2628 * be re-evaluated and setup on the next nested-guest VM-entry.
2629 */
2630 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2631
2632 /* Restore the host (outer guest) state. */
2633 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2634 if (RT_SUCCESS(rcStrict))
2635 {
2636 Assert(rcStrict == VINF_SUCCESS);
2637 rcStrict = VINF_VMX_VMEXIT;
2638 }
2639 else
2640 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2641
2642 /* We're no longer in nested-guest execution mode. */
2643 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2644
2645 /* Notify HM that the current VMCS fields have been modified. */
2646 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2647
2648 /* Notify HM that we've completed the VM-exit. */
2649 HMNotifyVmxNstGstVmexit(pVCpu);
2650
2651# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2652 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2653 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2654 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2655 if (rcSched != VINF_SUCCESS)
2656 iemSetPassUpStatus(pVCpu, rcSched);
2657# endif
2658 return rcStrict;
2659# endif
2660}
2661
2662
2663/**
2664 * VMX VM-exit handler for VM-exits due to instruction execution.
2665 *
2666 * This is intended for instructions where the caller provides all the relevant
2667 * VM-exit information.
2668 *
2669 * @returns Strict VBox status code.
2670 * @param pVCpu The cross context virtual CPU structure.
2671 * @param pExitInfo Pointer to the VM-exit information.
2672 */
2673IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2674{
2675 /*
2676 * For instructions where any of the following fields are not applicable:
2677 * - Exit qualification must be cleared.
2678 * - VM-exit instruction info. is undefined.
2679 * - Guest-linear address is undefined.
2680 * - Guest-physical address is undefined.
2681 *
2682 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2683 * instruction execution. For VM-exits that are not due to instruction execution this
2684 * field is undefined.
2685 *
2686 * In our implementation in IEM, all undefined fields are generally cleared. However,
2687 * if the caller supplies information (from say the physical CPU directly) it is
2688 * then possible that the undefined fields are not cleared.
2689 *
2690 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2691 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2692 */
2693 Assert(pExitInfo);
2694 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2695 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2696 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2697
2698 /* Update all the relevant fields from the VM-exit instruction information struct. */
2699 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2700 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2701 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2702 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2703
2704 /* Perform the VM-exit. */
2705 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2706}
2707
2708
2709/**
2710 * VMX VM-exit handler for VM-exits due to instruction execution.
2711 *
2712 * This is intended for instructions that only provide the VM-exit instruction
2713 * length.
2714 *
2715 * @param pVCpu The cross context virtual CPU structure.
2716 * @param uExitReason The VM-exit reason.
2717 * @param cbInstr The instruction length in bytes.
2718 */
2719IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2720{
2721 VMXVEXITINFO ExitInfo;
2722 RT_ZERO(ExitInfo);
2723 ExitInfo.uReason = uExitReason;
2724 ExitInfo.cbInstr = cbInstr;
2725
2726#ifdef VBOX_STRICT
2727 /*
2728 * To prevent us from shooting ourselves in the foot.
2729 * The follow instructions should convey more than just the instruction length.
2730 */
2731 switch (uExitReason)
2732 {
2733 case VMX_EXIT_INVEPT:
2734 case VMX_EXIT_INVPCID:
2735 case VMX_EXIT_INVVPID:
2736 case VMX_EXIT_LDTR_TR_ACCESS:
2737 case VMX_EXIT_GDTR_IDTR_ACCESS:
2738 case VMX_EXIT_VMCLEAR:
2739 case VMX_EXIT_VMPTRLD:
2740 case VMX_EXIT_VMPTRST:
2741 case VMX_EXIT_VMREAD:
2742 case VMX_EXIT_VMWRITE:
2743 case VMX_EXIT_VMXON:
2744 case VMX_EXIT_XRSTORS:
2745 case VMX_EXIT_XSAVES:
2746 case VMX_EXIT_RDRAND:
2747 case VMX_EXIT_RDSEED:
2748 case VMX_EXIT_IO_INSTR:
2749 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2750 break;
2751 }
2752#endif
2753
2754 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2755}
2756
2757
2758/**
2759 * VMX VM-exit handler for VM-exits due to instruction execution.
2760 *
2761 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2762 * instruction information and Exit qualification fields.
2763 *
2764 * @param pVCpu The cross context virtual CPU structure.
2765 * @param uExitReason The VM-exit reason.
2766 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2767 * @param cbInstr The instruction length in bytes.
2768 *
2769 * @remarks Do not use this for INS/OUTS instruction.
2770 */
2771IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2772{
2773 VMXVEXITINFO ExitInfo;
2774 RT_ZERO(ExitInfo);
2775 ExitInfo.uReason = uExitReason;
2776 ExitInfo.cbInstr = cbInstr;
2777
2778 /*
2779 * Update the Exit qualification field with displacement bytes.
2780 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2781 */
2782 switch (uExitReason)
2783 {
2784 case VMX_EXIT_INVEPT:
2785 case VMX_EXIT_INVPCID:
2786 case VMX_EXIT_INVVPID:
2787 case VMX_EXIT_LDTR_TR_ACCESS:
2788 case VMX_EXIT_GDTR_IDTR_ACCESS:
2789 case VMX_EXIT_VMCLEAR:
2790 case VMX_EXIT_VMPTRLD:
2791 case VMX_EXIT_VMPTRST:
2792 case VMX_EXIT_VMREAD:
2793 case VMX_EXIT_VMWRITE:
2794 case VMX_EXIT_VMXON:
2795 case VMX_EXIT_XRSTORS:
2796 case VMX_EXIT_XSAVES:
2797 case VMX_EXIT_RDRAND:
2798 case VMX_EXIT_RDSEED:
2799 {
2800 /* Construct the VM-exit instruction information. */
2801 RTGCPTR GCPtrDisp;
2802 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2803
2804 /* Update the VM-exit instruction information. */
2805 ExitInfo.InstrInfo.u = uInstrInfo;
2806
2807 /* Update the Exit qualification. */
2808 ExitInfo.u64Qual = GCPtrDisp;
2809 break;
2810 }
2811
2812 default:
2813 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2814 break;
2815 }
2816
2817 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2818}
2819
2820
2821/**
2822 * VMX VM-exit handler for VM-exits due to INVLPG.
2823 *
2824 * @returns Strict VBox status code.
2825 * @param pVCpu The cross context virtual CPU structure.
2826 * @param GCPtrPage The guest-linear address of the page being invalidated.
2827 * @param cbInstr The instruction length in bytes.
2828 */
2829IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2830{
2831 VMXVEXITINFO ExitInfo;
2832 RT_ZERO(ExitInfo);
2833 ExitInfo.uReason = VMX_EXIT_INVLPG;
2834 ExitInfo.cbInstr = cbInstr;
2835 ExitInfo.u64Qual = GCPtrPage;
2836 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2837
2838 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2839}
2840
2841
2842/**
2843 * VMX VM-exit handler for VM-exits due to LMSW.
2844 *
2845 * @returns Strict VBox status code.
2846 * @param pVCpu The cross context virtual CPU structure.
2847 * @param uGuestCr0 The current guest CR0.
2848 * @param pu16NewMsw The machine-status word specified in LMSW's source
2849 * operand. This will be updated depending on the VMX
2850 * guest/host CR0 mask if LMSW is not intercepted.
2851 * @param GCPtrEffDst The guest-linear address of the source operand in case
2852 * of a memory operand. For register operand, pass
2853 * NIL_RTGCPTR.
2854 * @param cbInstr The instruction length in bytes.
2855 */
2856IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2857 uint8_t cbInstr)
2858{
2859 Assert(pu16NewMsw);
2860
2861 uint16_t const uNewMsw = *pu16NewMsw;
2862 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2863 {
2864 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2865
2866 VMXVEXITINFO ExitInfo;
2867 RT_ZERO(ExitInfo);
2868 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2869 ExitInfo.cbInstr = cbInstr;
2870
2871 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2872 if (fMemOperand)
2873 {
2874 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2875 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2876 }
2877
2878 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2879 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2880 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2881 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2882
2883 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2884 }
2885
2886 /*
2887 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2888 * CR0 guest/host mask must be left unmodified.
2889 *
2890 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2891 */
2892 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2893 Assert(pVmcs);
2894 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2895 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2896 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2897
2898 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2899}
2900
2901
2902/**
2903 * VMX VM-exit handler for VM-exits due to CLTS.
2904 *
2905 * @returns Strict VBox status code.
2906 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2907 * VM-exit but must not modify the guest CR0.TS bit.
2908 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2909 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2910 * CR0 fixed bits in VMX operation).
2911 * @param pVCpu The cross context virtual CPU structure.
2912 * @param cbInstr The instruction length in bytes.
2913 */
2914IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2915{
2916 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2917 Assert(pVmcs);
2918
2919 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2920 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2921
2922 /*
2923 * If CR0.TS is owned by the host:
2924 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2925 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2926 * CLTS instruction completes without clearing CR0.TS.
2927 *
2928 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2929 */
2930 if (fGstHostMask & X86_CR0_TS)
2931 {
2932 if (fReadShadow & X86_CR0_TS)
2933 {
2934 Log2(("clts: Guest intercept -> VM-exit\n"));
2935
2936 VMXVEXITINFO ExitInfo;
2937 RT_ZERO(ExitInfo);
2938 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2939 ExitInfo.cbInstr = cbInstr;
2940 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2941 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2942 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2943 }
2944
2945 return VINF_VMX_MODIFIES_BEHAVIOR;
2946 }
2947
2948 /*
2949 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2950 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2951 */
2952 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2953}
2954
2955
2956/**
2957 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2958 * (CR0/CR4 write).
2959 *
2960 * @returns Strict VBox status code.
2961 * @param pVCpu The cross context virtual CPU structure.
2962 * @param iCrReg The control register (either CR0 or CR4).
2963 * @param uGuestCrX The current guest CR0/CR4.
2964 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2965 * VM-exit is caused.
2966 * @param iGReg The general register from which the CR0/CR4 value is being
2967 * loaded.
2968 * @param cbInstr The instruction length in bytes.
2969 */
2970IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2971 uint8_t cbInstr)
2972{
2973 Assert(puNewCrX);
2974 Assert(iCrReg == 0 || iCrReg == 4);
2975 Assert(iGReg < X86_GREG_COUNT);
2976
2977 uint64_t const uNewCrX = *puNewCrX;
2978 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2979 {
2980 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2981
2982 VMXVEXITINFO ExitInfo;
2983 RT_ZERO(ExitInfo);
2984 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2985 ExitInfo.cbInstr = cbInstr;
2986 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2987 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2988 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2989 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2990 }
2991
2992 /*
2993 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2994 * must not be modified the instruction.
2995 *
2996 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2997 */
2998 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2999 Assert(pVmcs);
3000 uint64_t uGuestCrX;
3001 uint64_t fGstHostMask;
3002 if (iCrReg == 0)
3003 {
3004 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3005 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3006 fGstHostMask = pVmcs->u64Cr0Mask.u;
3007 }
3008 else
3009 {
3010 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3011 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3012 fGstHostMask = pVmcs->u64Cr4Mask.u;
3013 }
3014
3015 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3016 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3017}
3018
3019
3020/**
3021 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3022 *
3023 * @returns VBox strict status code.
3024 * @param pVCpu The cross context virtual CPU structure.
3025 * @param iGReg The general register to which the CR3 value is being stored.
3026 * @param cbInstr The instruction length in bytes.
3027 */
3028IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3029{
3030 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3031 Assert(pVmcs);
3032 Assert(iGReg < X86_GREG_COUNT);
3033 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3034
3035 /*
3036 * If the CR3-store exiting control is set, we must cause a VM-exit.
3037 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3038 */
3039 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3040 {
3041 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3042
3043 VMXVEXITINFO ExitInfo;
3044 RT_ZERO(ExitInfo);
3045 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3046 ExitInfo.cbInstr = cbInstr;
3047 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3048 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3049 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3050 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3051 }
3052
3053 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3054}
3055
3056
3057/**
3058 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3059 *
3060 * @returns VBox strict status code.
3061 * @param pVCpu The cross context virtual CPU structure.
3062 * @param uNewCr3 The new CR3 value.
3063 * @param iGReg The general register from which the CR3 value is being
3064 * loaded.
3065 * @param cbInstr The instruction length in bytes.
3066 */
3067IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3068{
3069 Assert(iGReg < X86_GREG_COUNT);
3070
3071 /*
3072 * If the CR3-load exiting control is set and the new CR3 value does not
3073 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3074 *
3075 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3076 */
3077 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3078 {
3079 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3080
3081 VMXVEXITINFO ExitInfo;
3082 RT_ZERO(ExitInfo);
3083 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3084 ExitInfo.cbInstr = cbInstr;
3085 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3086 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3087 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3088 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3089 }
3090
3091 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3092}
3093
3094
3095/**
3096 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3097 *
3098 * @returns VBox strict status code.
3099 * @param pVCpu The cross context virtual CPU structure.
3100 * @param iGReg The general register to which the CR8 value is being stored.
3101 * @param cbInstr The instruction length in bytes.
3102 */
3103IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3104{
3105 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3106 Assert(pVmcs);
3107 Assert(iGReg < X86_GREG_COUNT);
3108
3109 /*
3110 * If the CR8-store exiting control is set, we must cause a VM-exit.
3111 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3112 */
3113 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3114 {
3115 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3116
3117 VMXVEXITINFO ExitInfo;
3118 RT_ZERO(ExitInfo);
3119 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3120 ExitInfo.cbInstr = cbInstr;
3121 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3122 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3123 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3124 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3125 }
3126
3127 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3128}
3129
3130
3131/**
3132 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3133 *
3134 * @returns VBox strict status code.
3135 * @param pVCpu The cross context virtual CPU structure.
3136 * @param iGReg The general register from which the CR8 value is being
3137 * loaded.
3138 * @param cbInstr The instruction length in bytes.
3139 */
3140IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3141{
3142 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3143 Assert(pVmcs);
3144 Assert(iGReg < X86_GREG_COUNT);
3145
3146 /*
3147 * If the CR8-load exiting control is set, we must cause a VM-exit.
3148 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3149 */
3150 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3151 {
3152 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3153
3154 VMXVEXITINFO ExitInfo;
3155 RT_ZERO(ExitInfo);
3156 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3157 ExitInfo.cbInstr = cbInstr;
3158 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3159 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3160 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3161 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3162 }
3163
3164 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3165}
3166
3167
3168/**
3169 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3170 * GReg,DRx' (DRx read).
3171 *
3172 * @returns VBox strict status code.
3173 * @param pVCpu The cross context virtual CPU structure.
3174 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3175 * VMXINSTRID_MOV_FROM_DRX).
3176 * @param iDrReg The debug register being accessed.
3177 * @param iGReg The general register to/from which the DRx value is being
3178 * store/loaded.
3179 * @param cbInstr The instruction length in bytes.
3180 */
3181IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3182 uint8_t cbInstr)
3183{
3184 Assert(iDrReg <= 7);
3185 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3186 Assert(iGReg < X86_GREG_COUNT);
3187
3188 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3189 Assert(pVmcs);
3190
3191 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3192 {
3193 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3194 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3195 VMXVEXITINFO ExitInfo;
3196 RT_ZERO(ExitInfo);
3197 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3198 ExitInfo.cbInstr = cbInstr;
3199 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3200 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3201 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3202 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3203 }
3204
3205 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3206}
3207
3208
3209/**
3210 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3211 *
3212 * @returns VBox strict status code.
3213 * @param pVCpu The cross context virtual CPU structure.
3214 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3215 * VMXINSTRID_IO_OUT).
3216 * @param u16Port The I/O port being accessed.
3217 * @param fImm Whether the I/O port was encoded using an immediate operand
3218 * or the implicit DX register.
3219 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3220 * @param cbInstr The instruction length in bytes.
3221 */
3222IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3223 uint8_t cbInstr)
3224{
3225 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3226 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3227
3228 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3229 if (fIntercept)
3230 {
3231 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3232 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3233 VMXVEXITINFO ExitInfo;
3234 RT_ZERO(ExitInfo);
3235 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3236 ExitInfo.cbInstr = cbInstr;
3237 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3238 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3239 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3240 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3241 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3242 }
3243
3244 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3245}
3246
3247
3248/**
3249 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3250 *
3251 * @returns VBox strict status code.
3252 * @param pVCpu The cross context virtual CPU structure.
3253 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3254 * VMXINSTRID_IO_OUTS).
3255 * @param u16Port The I/O port being accessed.
3256 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3257 * @param fRep Whether the instruction has a REP prefix or not.
3258 * @param ExitInstrInfo The VM-exit instruction info. field.
3259 * @param cbInstr The instruction length in bytes.
3260 */
3261IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3262 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3263{
3264 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3265 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3266 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3267 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3268 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3269
3270 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3271 if (fIntercept)
3272 {
3273 /*
3274 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3275 */
3276 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3277 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3278 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3279 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3280 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3281
3282 uint32_t uDirection;
3283 uint64_t uGuestLinearAddr;
3284 if (uInstrId == VMXINSTRID_IO_INS)
3285 {
3286 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3287 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3288 }
3289 else
3290 {
3291 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3292 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3293 }
3294
3295 /*
3296 * If the segment is unusable, the guest-linear address in undefined.
3297 * We shall clear it for consistency.
3298 *
3299 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3300 */
3301 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3302 uGuestLinearAddr = 0;
3303
3304 VMXVEXITINFO ExitInfo;
3305 RT_ZERO(ExitInfo);
3306 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3307 ExitInfo.cbInstr = cbInstr;
3308 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3309 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3310 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3311 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3312 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3313 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3314 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3315 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3316 ExitInfo.InstrInfo = ExitInstrInfo;
3317 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3318 }
3319
3320 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3321}
3322
3323
3324/**
3325 * VMX VM-exit handler for VM-exits due to MWAIT.
3326 *
3327 * @returns VBox strict status code.
3328 * @param pVCpu The cross context virtual CPU structure.
3329 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3330 * @param cbInstr The instruction length in bytes.
3331 */
3332IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3333{
3334 VMXVEXITINFO ExitInfo;
3335 RT_ZERO(ExitInfo);
3336 ExitInfo.uReason = VMX_EXIT_MWAIT;
3337 ExitInfo.cbInstr = cbInstr;
3338 ExitInfo.u64Qual = fMonitorHwArmed;
3339 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3340}
3341
3342
3343/**
3344 * VMX VM-exit handler for VM-exits due to PAUSE.
3345 *
3346 * @returns VBox strict status code.
3347 * @param pVCpu The cross context virtual CPU structure.
3348 * @param cbInstr The instruction length in bytes.
3349 */
3350IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3351{
3352 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3353 Assert(pVmcs);
3354
3355 /*
3356 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3357 * "PAUSE-loop exiting" control.
3358 *
3359 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3360 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3361 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3362 * a VM-exit.
3363 *
3364 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3365 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3366 */
3367 bool fIntercept = false;
3368 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3369 fIntercept = true;
3370 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3371 && pVCpu->iem.s.uCpl == 0)
3372 {
3373 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3374
3375 /*
3376 * A previous-PAUSE-tick value of 0 is used to identify the first time
3377 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3378 * consider this to be the first execution of PAUSE in a loop according
3379 * to the Intel.
3380 *
3381 * All subsequent records for the previous-PAUSE-tick we ensure that it
3382 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3383 */
3384 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3385 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3386 uint64_t const uTick = TMCpuTickGet(pVCpu);
3387 uint32_t const uPleGap = pVmcs->u32PleGap;
3388 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3389 if ( *puPrevPauseTick == 0
3390 || uTick - *puPrevPauseTick > uPleGap)
3391 *puFirstPauseLoopTick = uTick;
3392 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3393 fIntercept = true;
3394
3395 *puPrevPauseTick = uTick | 1;
3396 }
3397
3398 if (fIntercept)
3399 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3400
3401 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3402}
3403
3404
3405/**
3406 * VMX VM-exit handler for VM-exits due to task switches.
3407 *
3408 * @returns VBox strict status code.
3409 * @param pVCpu The cross context virtual CPU structure.
3410 * @param enmTaskSwitch The cause of the task switch.
3411 * @param SelNewTss The selector of the new TSS.
3412 * @param cbInstr The instruction length in bytes.
3413 */
3414IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3415{
3416 /*
3417 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3418 *
3419 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3420 * instruction or delivery of the exception generated by one of these instructions
3421 * lead to a task switch through a task gate in the IDT, we need to provide the
3422 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3423 * leaves the VM-exit instruction length field undefined.
3424 *
3425 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3426 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3427 */
3428 Assert(cbInstr <= 15);
3429
3430 uint8_t uType;
3431 switch (enmTaskSwitch)
3432 {
3433 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3434 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3435 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3436 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3437 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3438 }
3439
3440 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3441 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3442 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3443 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3444}
3445
3446
3447/**
3448 * VMX VM-exit handler for trap-like VM-exits.
3449 *
3450 * @returns VBox strict status code.
3451 * @param pVCpu The cross context virtual CPU structure.
3452 * @param pExitInfo Pointer to the VM-exit information.
3453 * @param pExitEventInfo Pointer to the VM-exit event information.
3454 */
3455IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3456{
3457 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3458 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3459 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3460}
3461
3462
3463/**
3464 * VMX VM-exit handler for VM-exits due to task switches.
3465 *
3466 * This is intended for task switches where the caller provides all the relevant
3467 * VM-exit information.
3468 *
3469 * @returns VBox strict status code.
3470 * @param pVCpu The cross context virtual CPU structure.
3471 * @param pExitInfo Pointer to the VM-exit information.
3472 * @param pExitEventInfo Pointer to the VM-exit event information.
3473 */
3474IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3475 PCVMXVEXITEVENTINFO pExitEventInfo)
3476{
3477 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3478 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3479 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3480 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3481 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3482}
3483
3484
3485/**
3486 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3487 *
3488 * @returns VBox strict status code.
3489 * @param pVCpu The cross context virtual CPU structure.
3490 */
3491IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3492{
3493 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3494 Assert(pVmcs);
3495 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3496 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3497
3498 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3499 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3500
3501 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3502 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3503 pVmcs->u32PreemptTimer = 0;
3504
3505 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3506 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3507}
3508
3509
3510/**
3511 * VMX VM-exit handler for VM-exits due to external interrupts.
3512 *
3513 * @returns VBox strict status code.
3514 * @param pVCpu The cross context virtual CPU structure.
3515 * @param uVector The external interrupt vector (pass 0 if the interrupt
3516 * is still pending since we typically won't know the
3517 * vector).
3518 * @param fIntPending Whether the external interrupt is pending or
3519 * acknowledged in the interrupt controller.
3520 */
3521IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3522{
3523 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3524 Assert(pVmcs);
3525 Assert(!fIntPending || uVector == 0);
3526
3527 /* The VM-exit is subject to "External interrupt exiting" being set. */
3528 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3529 {
3530 if (fIntPending)
3531 {
3532 /*
3533 * If the interrupt is pending and we don't need to acknowledge the
3534 * interrupt on VM-exit, cause the VM-exit immediately.
3535 *
3536 * See Intel spec 25.2 "Other Causes Of VM Exits".
3537 */
3538 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3539 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3540
3541 /*
3542 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3543 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3544 * acknowledged that the interrupt has been consumed. Callers would have to call
3545 * us again after getting the vector (and ofc, with fIntPending with false).
3546 */
3547 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3548 }
3549
3550 /*
3551 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3552 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3553 * all set, we need to record the vector of the external interrupt in the
3554 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3555 *
3556 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3557 */
3558 uint32_t uExitIntInfo;
3559 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3560 {
3561 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3562 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3563 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3564 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3565 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3566 }
3567 else
3568 uExitIntInfo = 0;
3569 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3570
3571 /*
3572 * Cause the VM-exit whether or not the vector has been stored
3573 * in the VM-exit interruption-information field.
3574 */
3575 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3576 }
3577
3578 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3579}
3580
3581
3582/**
3583 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3584 * an event.
3585 *
3586 * @returns VBox strict status code.
3587 * @param pVCpu The cross context virtual CPU structure.
3588 */
3589IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3590{
3591 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3592 Assert(pVmcs);
3593
3594 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3595 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3596 {
3597 /*
3598 * The NMI-unblocking due to IRET field need not be set for double faults.
3599 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3600 */
3601 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3602 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3603 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3604 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3605 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3606 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3607 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3608 }
3609
3610 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3611}
3612
3613
3614/**
3615 * VMX VM-exit handler for VM-exit due to delivery of an events.
3616 *
3617 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3618 * all the relevant VM-exit information.
3619 *
3620 * @returns VBox strict status code.
3621 * @param pVCpu The cross context virtual CPU structure.
3622 * @param pExitInfo Pointer to the VM-exit information.
3623 * @param pExitEventInfo Pointer to the VM-exit event information.
3624 */
3625IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3626{
3627 Assert(pExitInfo);
3628 Assert(pExitEventInfo);
3629 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3630 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3631
3632 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3633 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3634 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3635 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3636 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3637 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3638}
3639
3640
3641/**
3642 * VMX VM-exit handler for VM-exits due to delivery of an event.
3643 *
3644 * @returns VBox strict status code.
3645 * @param pVCpu The cross context virtual CPU structure.
3646 * @param uVector The interrupt / exception vector.
3647 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3648 * @param uErrCode The error code associated with the event.
3649 * @param uCr2 The CR2 value in case of a \#PF exception.
3650 * @param cbInstr The instruction length in bytes.
3651 */
3652IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3653 uint8_t cbInstr)
3654{
3655 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3656 Assert(pVmcs);
3657
3658 /*
3659 * If the event is being injected as part of VM-entry, it is -not- subject to event
3660 * intercepts in the nested-guest. However, secondary exceptions that occur during
3661 * injection of any event -are- subject to event interception.
3662 *
3663 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3664 */
3665 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3666 {
3667 /*
3668 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3669 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3670 *
3671 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3672 */
3673 if ( uVector == X86_XCPT_NMI
3674 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3675 && (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3676 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3677 else
3678 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3679
3680 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3681 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3682 }
3683
3684 /*
3685 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3686 * If not, the caller will continue delivery of the external interrupt as it would
3687 * normally. The interrupt is no longer pending in the interrupt controller at this
3688 * point.
3689 */
3690 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3691 {
3692 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
3693 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3694 }
3695
3696 /*
3697 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3698 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3699 * interrupts.
3700 */
3701 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3702 bool fIntercept;
3703 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3704 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3705 {
3706 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3707 }
3708 else
3709 {
3710 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3711 fIntercept = false;
3712 }
3713
3714 /*
3715 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3716 * relevant VM-exit information and cause the VM-exit.
3717 */
3718 if (fIntercept)
3719 {
3720 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3721
3722 /* Construct the rest of the event related information fields and cause the VM-exit. */
3723 uint64_t u64ExitQual;
3724 if (uVector == X86_XCPT_PF)
3725 {
3726 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3727 u64ExitQual = uCr2;
3728 }
3729 else if (uVector == X86_XCPT_DB)
3730 {
3731 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3732 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3733 }
3734 else
3735 u64ExitQual = 0;
3736
3737 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3738 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3739 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3740 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3741 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3742 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3743 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3744 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3745 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3746 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3747
3748 /*
3749 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3750 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3751 * length.
3752 */
3753 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3754 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3755 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3756 else
3757 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3758
3759 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3760 }
3761
3762 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3763}
3764
3765
3766/**
3767 * VMX VM-exit handler for APIC accesses.
3768 *
3769 * @param pVCpu The cross context virtual CPU structure.
3770 * @param offAccess The offset of the register being accessed.
3771 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3772 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3773 */
3774IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3775{
3776 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3777
3778 VMXAPICACCESS enmAccess;
3779 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3780 if (fInEventDelivery)
3781 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3782 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3783 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3784 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3785 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3786 else
3787 enmAccess = VMXAPICACCESS_LINEAR_READ;
3788
3789 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3790 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3791 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3792}
3793
3794
3795/**
3796 * VMX VM-exit handler for APIC accesses.
3797 *
3798 * This is intended for APIC accesses where the caller provides all the
3799 * relevant VM-exit information.
3800 *
3801 * @returns VBox strict status code.
3802 * @param pVCpu The cross context virtual CPU structure.
3803 * @param pExitInfo Pointer to the VM-exit information.
3804 * @param pExitEventInfo Pointer to the VM-exit event information.
3805 */
3806IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3807 PCVMXVEXITEVENTINFO pExitEventInfo)
3808{
3809 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3810 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3811 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3812 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3813 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3814 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3815 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3816 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3817 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3818}
3819
3820
3821/**
3822 * VMX VM-exit handler for APIC-write VM-exits.
3823 *
3824 * @param pVCpu The cross context virtual CPU structure.
3825 * @param offApic The write to the virtual-APIC page offset that caused this
3826 * VM-exit.
3827 */
3828IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3829{
3830 Assert(offApic < XAPIC_OFF_END + 4);
3831 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3832 offApic &= UINT16_C(0xfff);
3833 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3834}
3835
3836
3837/**
3838 * Sets virtual-APIC write emulation as pending.
3839 *
3840 * @param pVCpu The cross context virtual CPU structure.
3841 * @param offApic The offset in the virtual-APIC page that was written.
3842 */
3843DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3844{
3845 Assert(offApic < XAPIC_OFF_END + 4);
3846
3847 /*
3848 * Record the currently updated APIC offset, as we need this later for figuring
3849 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3850 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3851 */
3852 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3853
3854 /*
3855 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3856 * virtualization or APIC-write emulation).
3857 */
3858 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3859 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3860}
3861
3862
3863/**
3864 * Clears any pending virtual-APIC write emulation.
3865 *
3866 * @returns The virtual-APIC offset that was written before clearing it.
3867 * @param pVCpu The cross context virtual CPU structure.
3868 */
3869DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3870{
3871 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3872 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3873 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3874 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3875 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3876 return offVirtApicWrite;
3877}
3878
3879
3880/**
3881 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3882 *
3883 * @returns The register from the virtual-APIC page.
3884 * @param pVCpu The cross context virtual CPU structure.
3885 * @param offReg The offset of the register being read.
3886 */
3887IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3888{
3889 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3890 Assert(pVmcs);
3891 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3892
3893 uint32_t uReg;
3894 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3895 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3896 if (RT_SUCCESS(rc))
3897 { /* likely */ }
3898 else
3899 {
3900 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3901 GCPhysVirtApic));
3902 uReg = 0;
3903 }
3904 return uReg;
3905}
3906
3907
3908/**
3909 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3910 *
3911 * @returns The register from the virtual-APIC page.
3912 * @param pVCpu The cross context virtual CPU structure.
3913 * @param offReg The offset of the register being read.
3914 */
3915IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3916{
3917 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3918 Assert(pVmcs);
3919 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3920
3921 uint64_t uReg;
3922 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3923 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3924 if (RT_SUCCESS(rc))
3925 { /* likely */ }
3926 else
3927 {
3928 AssertMsgFailed(("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3929 GCPhysVirtApic));
3930 uReg = 0;
3931 }
3932 return uReg;
3933}
3934
3935
3936/**
3937 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3938 *
3939 * @param pVCpu The cross context virtual CPU structure.
3940 * @param offReg The offset of the register being written.
3941 * @param uReg The register value to write.
3942 */
3943IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3944{
3945 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3946 Assert(pVmcs);
3947 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3948
3949 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3950 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3951 if (RT_SUCCESS(rc))
3952 { /* likely */ }
3953 else
3954 {
3955 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3956 GCPhysVirtApic));
3957 }
3958}
3959
3960
3961/**
3962 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3963 *
3964 * @param pVCpu The cross context virtual CPU structure.
3965 * @param offReg The offset of the register being written.
3966 * @param uReg The register value to write.
3967 */
3968IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3969{
3970 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3971 Assert(pVmcs);
3972 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3973
3974 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3975 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3976 if (RT_SUCCESS(rc))
3977 { /* likely */ }
3978 else
3979 {
3980 AssertMsgFailed(("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp\n", sizeof(uReg), offReg,
3981 GCPhysVirtApic));
3982 }
3983}
3984
3985
3986/**
3987 * Sets the vector in a virtual-APIC 256-bit sparse register.
3988 *
3989 * @param pVCpu The cross context virtual CPU structure.
3990 * @param offReg The offset of the 256-bit spare register.
3991 * @param uVector The vector to set.
3992 *
3993 * @remarks This is based on our APIC device code.
3994 */
3995IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3996{
3997 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3998 Assert(pVmcs);
3999
4000 /* Determine the vector offset within the chunk. */
4001 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4002
4003 /* Read the chunk at the offset. */
4004 uint32_t uReg;
4005 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4006 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4007 if (RT_SUCCESS(rc))
4008 {
4009 /* Modify the chunk. */
4010 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4011 uReg |= RT_BIT(idxVectorBit);
4012
4013 /* Write the chunk. */
4014 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4015 if (RT_SUCCESS(rc))
4016 { /* likely */ }
4017 else
4018 {
4019 AssertMsgFailed(("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4020 uVector, offReg, GCPhysVirtApic));
4021 }
4022 }
4023 else
4024 {
4025 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4026 uVector, offReg, GCPhysVirtApic));
4027 }
4028}
4029
4030
4031/**
4032 * Clears the vector in a virtual-APIC 256-bit sparse register.
4033 *
4034 * @param pVCpu The cross context virtual CPU structure.
4035 * @param offReg The offset of the 256-bit spare register.
4036 * @param uVector The vector to clear.
4037 *
4038 * @remarks This is based on our APIC device code.
4039 */
4040IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4041{
4042 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4043 Assert(pVmcs);
4044
4045 /* Determine the vector offset within the chunk. */
4046 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4047
4048 /* Read the chunk at the offset. */
4049 uint32_t uReg;
4050 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4051 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4052 if (RT_SUCCESS(rc))
4053 {
4054 /* Modify the chunk. */
4055 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4056 uReg &= ~RT_BIT(idxVectorBit);
4057
4058 /* Write the chunk. */
4059 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4060 if (RT_SUCCESS(rc))
4061 { /* likely */ }
4062 else
4063 {
4064 AssertMsgFailed(("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4065 uVector, offReg, GCPhysVirtApic));
4066 }
4067 }
4068 else
4069 {
4070 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp\n",
4071 uVector, offReg, GCPhysVirtApic));
4072 }
4073}
4074
4075
4076/**
4077 * Checks if a memory access to the APIC-access page must causes an APIC-access
4078 * VM-exit.
4079 *
4080 * @param pVCpu The cross context virtual CPU structure.
4081 * @param offAccess The offset of the register being accessed.
4082 * @param cbAccess The size of the access in bytes.
4083 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4084 * IEM_ACCESS_TYPE_WRITE).
4085 *
4086 * @remarks This must not be used for MSR-based APIC-access page accesses!
4087 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4088 */
4089IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4090{
4091 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4092 Assert(pVmcs);
4093 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4094
4095 /*
4096 * We must cause a VM-exit if any of the following are true:
4097 * - TPR shadowing isn't active.
4098 * - The access size exceeds 32-bits.
4099 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4100 *
4101 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4102 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4103 */
4104 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4105 || cbAccess > sizeof(uint32_t)
4106 || ((offAccess + cbAccess - 1) & 0xc)
4107 || offAccess >= XAPIC_OFF_END + 4)
4108 return true;
4109
4110 /*
4111 * If the access is part of an operation where we have already
4112 * virtualized a virtual-APIC write, we must cause a VM-exit.
4113 */
4114 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4115 return true;
4116
4117 /*
4118 * Check write accesses to the APIC-access page that cause VM-exits.
4119 */
4120 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4121 {
4122 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4123 {
4124 /*
4125 * With APIC-register virtualization, a write access to any of the
4126 * following registers are virtualized. Accessing any other register
4127 * causes a VM-exit.
4128 */
4129 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4130 switch (offAlignedAccess)
4131 {
4132 case XAPIC_OFF_ID:
4133 case XAPIC_OFF_TPR:
4134 case XAPIC_OFF_EOI:
4135 case XAPIC_OFF_LDR:
4136 case XAPIC_OFF_DFR:
4137 case XAPIC_OFF_SVR:
4138 case XAPIC_OFF_ESR:
4139 case XAPIC_OFF_ICR_LO:
4140 case XAPIC_OFF_ICR_HI:
4141 case XAPIC_OFF_LVT_TIMER:
4142 case XAPIC_OFF_LVT_THERMAL:
4143 case XAPIC_OFF_LVT_PERF:
4144 case XAPIC_OFF_LVT_LINT0:
4145 case XAPIC_OFF_LVT_LINT1:
4146 case XAPIC_OFF_LVT_ERROR:
4147 case XAPIC_OFF_TIMER_ICR:
4148 case XAPIC_OFF_TIMER_DCR:
4149 break;
4150 default:
4151 return true;
4152 }
4153 }
4154 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4155 {
4156 /*
4157 * With virtual-interrupt delivery, a write access to any of the
4158 * following registers are virtualized. Accessing any other register
4159 * causes a VM-exit.
4160 *
4161 * Note! The specification does not allow writing to offsets in-between
4162 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4163 */
4164 switch (offAccess)
4165 {
4166 case XAPIC_OFF_TPR:
4167 case XAPIC_OFF_EOI:
4168 case XAPIC_OFF_ICR_LO:
4169 break;
4170 default:
4171 return true;
4172 }
4173 }
4174 else
4175 {
4176 /*
4177 * Without APIC-register virtualization or virtual-interrupt delivery,
4178 * only TPR accesses are virtualized.
4179 */
4180 if (offAccess == XAPIC_OFF_TPR)
4181 { /* likely */ }
4182 else
4183 return true;
4184 }
4185 }
4186 else
4187 {
4188 /*
4189 * Check read accesses to the APIC-access page that cause VM-exits.
4190 */
4191 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4192 {
4193 /*
4194 * With APIC-register virtualization, a read access to any of the
4195 * following registers are virtualized. Accessing any other register
4196 * causes a VM-exit.
4197 */
4198 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4199 switch (offAlignedAccess)
4200 {
4201 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4202 case XAPIC_OFF_ID:
4203 case XAPIC_OFF_VERSION:
4204 case XAPIC_OFF_TPR:
4205 case XAPIC_OFF_EOI:
4206 case XAPIC_OFF_LDR:
4207 case XAPIC_OFF_DFR:
4208 case XAPIC_OFF_SVR:
4209 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4210 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4211 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4212 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4213 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4214 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4215 case XAPIC_OFF_ESR:
4216 case XAPIC_OFF_ICR_LO:
4217 case XAPIC_OFF_ICR_HI:
4218 case XAPIC_OFF_LVT_TIMER:
4219 case XAPIC_OFF_LVT_THERMAL:
4220 case XAPIC_OFF_LVT_PERF:
4221 case XAPIC_OFF_LVT_LINT0:
4222 case XAPIC_OFF_LVT_LINT1:
4223 case XAPIC_OFF_LVT_ERROR:
4224 case XAPIC_OFF_TIMER_ICR:
4225 case XAPIC_OFF_TIMER_DCR:
4226 break;
4227 default:
4228 return true;
4229 }
4230 }
4231 else
4232 {
4233 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4234 if (offAccess == XAPIC_OFF_TPR)
4235 { /* likely */ }
4236 else
4237 return true;
4238 }
4239 }
4240
4241 /* The APIC access is virtualized, does not cause a VM-exit. */
4242 return false;
4243}
4244
4245
4246/**
4247 * Virtualizes a memory-based APIC access where the address is not used to access
4248 * memory.
4249 *
4250 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4251 * page-faults but do not use the address to access memory.
4252 *
4253 * @param pVCpu The cross context virtual CPU structure.
4254 * @param pGCPhysAccess Pointer to the guest-physical address used.
4255 */
4256IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4257{
4258 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4259 Assert(pVmcs);
4260 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4261 Assert(pGCPhysAccess);
4262
4263 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4264 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4265 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4266
4267 if (GCPhysAccess == GCPhysApic)
4268 {
4269 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4270 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4271 uint16_t const cbAccess = 1;
4272 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4273 if (fIntercept)
4274 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4275
4276 *pGCPhysAccess = GCPhysApic | offAccess;
4277 return VINF_VMX_MODIFIES_BEHAVIOR;
4278 }
4279
4280 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4281}
4282
4283
4284/**
4285 * Virtualizes a memory-based APIC access.
4286 *
4287 * @returns VBox strict status code.
4288 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4289 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4290 *
4291 * @param pVCpu The cross context virtual CPU structure.
4292 * @param offAccess The offset of the register being accessed (within the
4293 * APIC-access page).
4294 * @param cbAccess The size of the access in bytes.
4295 * @param pvData Pointer to the data being written or where to store the data
4296 * being read.
4297 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4298 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4299 */
4300IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4301 uint32_t fAccess)
4302{
4303 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4304 Assert(pVmcs);
4305 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4306 Assert(pvData);
4307 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4308 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4309 || (fAccess & IEM_ACCESS_INSTRUCTION));
4310
4311 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4312 if (fIntercept)
4313 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4314
4315 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4316 {
4317 /*
4318 * A write access to the APIC-access page that is virtualized (rather than
4319 * causing a VM-exit) writes data to the virtual-APIC page.
4320 */
4321 uint32_t const u32Data = *(uint32_t *)pvData;
4322 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4323
4324 /*
4325 * Record the currently updated APIC offset, as we need this later for figuring
4326 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4327 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4328 *
4329 * After completion of the current operation, we need to perform TPR virtualization,
4330 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4331 *
4332 * The current operation may be a REP-prefixed string instruction, execution of any
4333 * other instruction, or delivery of an event through the IDT.
4334 *
4335 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4336 * performed now but later after completion of the current operation.
4337 *
4338 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4339 */
4340 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4341 }
4342 else
4343 {
4344 /*
4345 * A read access from the APIC-access page that is virtualized (rather than
4346 * causing a VM-exit) returns data from the virtual-APIC page.
4347 *
4348 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4349 */
4350 Assert(cbAccess <= 4);
4351 Assert(offAccess < XAPIC_OFF_END + 4);
4352 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4353
4354 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4355 u32Data &= s_auAccessSizeMasks[cbAccess];
4356 *(uint32_t *)pvData = u32Data;
4357 }
4358
4359 return VINF_VMX_MODIFIES_BEHAVIOR;
4360}
4361
4362
4363/**
4364 * Virtualizes an MSR-based APIC read access.
4365 *
4366 * @returns VBox strict status code.
4367 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4368 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4369 * handled by the x2APIC device.
4370 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4371 * not within the range of valid MSRs, caller must raise \#GP(0).
4372 * @param pVCpu The cross context virtual CPU structure.
4373 * @param idMsr The x2APIC MSR being read.
4374 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4375 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4376 */
4377IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4378{
4379 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4380 Assert(pVmcs);
4381 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4382 Assert(pu64Value);
4383
4384 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4385 {
4386 if ( idMsr >= MSR_IA32_X2APIC_START
4387 && idMsr <= MSR_IA32_X2APIC_END)
4388 {
4389 uint16_t const offReg = (idMsr & 0xff) << 4;
4390 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4391 *pu64Value = u64Value;
4392 return VINF_VMX_MODIFIES_BEHAVIOR;
4393 }
4394 return VERR_OUT_OF_RANGE;
4395 }
4396
4397 if (idMsr == MSR_IA32_X2APIC_TPR)
4398 {
4399 uint16_t const offReg = (idMsr & 0xff) << 4;
4400 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4401 *pu64Value = u64Value;
4402 return VINF_VMX_MODIFIES_BEHAVIOR;
4403 }
4404
4405 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4406}
4407
4408
4409/**
4410 * Virtualizes an MSR-based APIC write access.
4411 *
4412 * @returns VBox strict status code.
4413 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4414 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4415 * not within the range of valid MSRs, caller must raise \#GP(0).
4416 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4417 *
4418 * @param pVCpu The cross context virtual CPU structure.
4419 * @param idMsr The x2APIC MSR being written.
4420 * @param u64Value The value of the x2APIC MSR being written.
4421 */
4422IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4423{
4424 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4425 Assert(pVmcs);
4426
4427 /*
4428 * Check if the access is to be virtualized.
4429 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4430 */
4431 if ( idMsr == MSR_IA32_X2APIC_TPR
4432 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4433 && ( idMsr == MSR_IA32_X2APIC_EOI
4434 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4435 {
4436 /* Validate the MSR write depending on the register. */
4437 switch (idMsr)
4438 {
4439 case MSR_IA32_X2APIC_TPR:
4440 case MSR_IA32_X2APIC_SELF_IPI:
4441 {
4442 if (u64Value & UINT64_C(0xffffffffffffff00))
4443 return VERR_OUT_OF_RANGE;
4444 break;
4445 }
4446 case MSR_IA32_X2APIC_EOI:
4447 {
4448 if (u64Value != 0)
4449 return VERR_OUT_OF_RANGE;
4450 break;
4451 }
4452 }
4453
4454 /* Write the MSR to the virtual-APIC page. */
4455 uint16_t const offReg = (idMsr & 0xff) << 4;
4456 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4457
4458 /*
4459 * Record the currently updated APIC offset, as we need this later for figuring
4460 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4461 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4462 */
4463 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4464
4465 return VINF_VMX_MODIFIES_BEHAVIOR;
4466 }
4467
4468 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4469}
4470
4471
4472/**
4473 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4474 *
4475 * @returns VBox status code.
4476 * @retval VINF_SUCCESS when the highest set bit is found.
4477 * @retval VERR_NOT_FOUND when no bit is set.
4478 *
4479 * @param pVCpu The cross context virtual CPU structure.
4480 * @param offReg The offset of the APIC 256-bit sparse register.
4481 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4482 * set in the register. Only valid when VINF_SUCCESS is
4483 * returned.
4484 *
4485 * @remarks The format of the 256-bit sparse register here mirrors that found in
4486 * real APIC hardware.
4487 */
4488static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4489{
4490 Assert(offReg < XAPIC_OFF_END + 4);
4491 Assert(pidxHighestBit);
4492 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
4493
4494 /*
4495 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4496 * However, in each fragment only the first 4 bytes are used.
4497 */
4498 uint8_t const cFrags = 8;
4499 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4500 {
4501 uint16_t const offFrag = iFrag * 16;
4502 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4503 if (!u32Frag)
4504 continue;
4505
4506 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4507 Assert(idxHighestBit > 0);
4508 --idxHighestBit;
4509 Assert(idxHighestBit <= UINT8_MAX);
4510 *pidxHighestBit = idxHighestBit;
4511 return VINF_SUCCESS;
4512 }
4513 return VERR_NOT_FOUND;
4514}
4515
4516
4517/**
4518 * Evaluates pending virtual interrupts.
4519 *
4520 * @param pVCpu The cross context virtual CPU structure.
4521 */
4522IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4523{
4524 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4525 Assert(pVmcs);
4526 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4527
4528 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4529 {
4530 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4531 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4532
4533 if ((uRvi >> 4) > (uPpr >> 4))
4534 {
4535 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4536 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4537 }
4538 else
4539 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4540 }
4541}
4542
4543
4544/**
4545 * Performs PPR virtualization.
4546 *
4547 * @returns VBox strict status code.
4548 * @param pVCpu The cross context virtual CPU structure.
4549 */
4550IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4551{
4552 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4553 Assert(pVmcs);
4554 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4555 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4556
4557 /*
4558 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4559 * or EOI-virtualization.
4560 *
4561 * See Intel spec. 29.1.3 "PPR Virtualization".
4562 */
4563 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4564 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4565
4566 uint32_t uPpr;
4567 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4568 uPpr = uTpr & 0xff;
4569 else
4570 uPpr = uSvi & 0xf0;
4571
4572 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4573 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4574}
4575
4576
4577/**
4578 * Performs VMX TPR virtualization.
4579 *
4580 * @returns VBox strict status code.
4581 * @param pVCpu The cross context virtual CPU structure.
4582 */
4583IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4584{
4585 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4586 Assert(pVmcs);
4587 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4588
4589 /*
4590 * We should have already performed the virtual-APIC write to the TPR offset
4591 * in the virtual-APIC page. We now perform TPR virtualization.
4592 *
4593 * See Intel spec. 29.1.2 "TPR Virtualization".
4594 */
4595 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4596 {
4597 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4598 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4599
4600 /*
4601 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4602 * See Intel spec. 29.1.2 "TPR Virtualization".
4603 */
4604 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4605 {
4606 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4607 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4608 }
4609 }
4610 else
4611 {
4612 iemVmxPprVirtualization(pVCpu);
4613 iemVmxEvalPendingVirtIntrs(pVCpu);
4614 }
4615
4616 return VINF_SUCCESS;
4617}
4618
4619
4620/**
4621 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4622 * not.
4623 *
4624 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4625 * @param pVCpu The cross context virtual CPU structure.
4626 * @param uVector The interrupt that was acknowledged using an EOI.
4627 */
4628IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4629{
4630 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4631 Assert(pVmcs);
4632 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4633
4634 if (uVector < 64)
4635 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4636 if (uVector < 128)
4637 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4638 if (uVector < 192)
4639 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4640 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4641}
4642
4643
4644/**
4645 * Performs EOI virtualization.
4646 *
4647 * @returns VBox strict status code.
4648 * @param pVCpu The cross context virtual CPU structure.
4649 */
4650IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4651{
4652 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4653 Assert(pVmcs);
4654 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4655
4656 /*
4657 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4658 * and get the next guest-interrupt that's in-service (if any).
4659 *
4660 * See Intel spec. 29.1.4 "EOI Virtualization".
4661 */
4662 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4663 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4664 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4665
4666 uint8_t uVector = uSvi;
4667 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4668
4669 uVector = 0;
4670 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4671
4672 if (uVector)
4673 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4674 else
4675 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4676
4677 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4678 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4679
4680 iemVmxPprVirtualization(pVCpu);
4681 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4682 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4683 iemVmxEvalPendingVirtIntrs(pVCpu);
4684 return VINF_SUCCESS;
4685}
4686
4687
4688/**
4689 * Performs self-IPI virtualization.
4690 *
4691 * @returns VBox strict status code.
4692 * @param pVCpu The cross context virtual CPU structure.
4693 */
4694IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4695{
4696 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4697 Assert(pVmcs);
4698 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4699
4700 /*
4701 * We should have already performed the virtual-APIC write to the self-IPI offset
4702 * in the virtual-APIC page. We now perform self-IPI virtualization.
4703 *
4704 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4705 */
4706 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4707 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4708 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4709 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4710 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4711 if (uVector > uRvi)
4712 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4713 iemVmxEvalPendingVirtIntrs(pVCpu);
4714 return VINF_SUCCESS;
4715}
4716
4717
4718/**
4719 * Performs VMX APIC-write emulation.
4720 *
4721 * @returns VBox strict status code.
4722 * @param pVCpu The cross context virtual CPU structure.
4723 */
4724IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4725{
4726 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4727 Assert(pVmcs);
4728
4729 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4730 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4731
4732 /*
4733 * Perform APIC-write emulation based on the virtual-APIC register written.
4734 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4735 */
4736 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4737 VBOXSTRICTRC rcStrict;
4738 switch (offApicWrite)
4739 {
4740 case XAPIC_OFF_TPR:
4741 {
4742 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4743 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4744 uTpr &= UINT32_C(0x000000ff);
4745 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4746 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4747 rcStrict = iemVmxTprVirtualization(pVCpu);
4748 break;
4749 }
4750
4751 case XAPIC_OFF_EOI:
4752 {
4753 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4754 {
4755 /* Clear VEOI and perform EOI virtualization. */
4756 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4757 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4758 rcStrict = iemVmxEoiVirtualization(pVCpu);
4759 }
4760 else
4761 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4762 break;
4763 }
4764
4765 case XAPIC_OFF_ICR_LO:
4766 {
4767 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4768 {
4769 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4770 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4771 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4772 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4773 if ( !(uIcrLo & fIcrLoMb0)
4774 && (uIcrLo & fIcrLoMb1))
4775 {
4776 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4777 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4778 }
4779 else
4780 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4781 }
4782 else
4783 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4784 break;
4785 }
4786
4787 case XAPIC_OFF_ICR_HI:
4788 {
4789 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4790 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4791 uIcrHi &= UINT32_C(0xff000000);
4792 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4793 rcStrict = VINF_SUCCESS;
4794 break;
4795 }
4796
4797 default:
4798 {
4799 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4800 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4801 break;
4802 }
4803 }
4804
4805 return rcStrict;
4806}
4807
4808
4809/**
4810 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4811 *
4812 * @param pVCpu The cross context virtual CPU structure.
4813 * @param pszInstr The VMX instruction name (for logging purposes).
4814 */
4815DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4816{
4817 /*
4818 * Guest Control Registers, Debug Registers, and MSRs.
4819 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4820 */
4821 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4822 const char *const pszFailure = "VM-exit";
4823 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4824
4825 /* CR0 reserved bits. */
4826 {
4827 /* CR0 MB1 bits. */
4828 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4829 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4830 if (fUnrestrictedGuest)
4831 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4832 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4833 { /* likely */ }
4834 else
4835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4836
4837 /* CR0 MBZ bits. */
4838 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4839 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4840 { /* likely */ }
4841 else
4842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4843
4844 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4845 if ( !fUnrestrictedGuest
4846 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4847 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4849 }
4850
4851 /* CR4 reserved bits. */
4852 {
4853 /* CR4 MB1 bits. */
4854 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4855 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4856 { /* likely */ }
4857 else
4858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4859
4860 /* CR4 MBZ bits. */
4861 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4862 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4863 { /* likely */ }
4864 else
4865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4866 }
4867
4868 /* DEBUGCTL MSR. */
4869 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4870 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4871 { /* likely */ }
4872 else
4873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4874
4875 /* 64-bit CPU checks. */
4876 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4877 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4878 {
4879 if (fGstInLongMode)
4880 {
4881 /* PAE must be set. */
4882 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4883 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4884 { /* likely */ }
4885 else
4886 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4887 }
4888 else
4889 {
4890 /* PCIDE should not be set. */
4891 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4892 { /* likely */ }
4893 else
4894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4895 }
4896
4897 /* CR3. */
4898 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4899 { /* likely */ }
4900 else
4901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4902
4903 /* DR7. */
4904 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4905 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4906 { /* likely */ }
4907 else
4908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4909
4910 /* SYSENTER ESP and SYSENTER EIP. */
4911 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4912 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4913 { /* likely */ }
4914 else
4915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4916 }
4917
4918 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4919 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4920
4921 /* PAT MSR. */
4922 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4923 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4924 { /* likely */ }
4925 else
4926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4927
4928 /* EFER MSR. */
4929 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4930 {
4931 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4932 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4933 { /* likely */ }
4934 else
4935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4936
4937 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4938 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4939 if ( fGstLma == fGstInLongMode
4940 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4941 || fGstLma == fGstLme))
4942 { /* likely */ }
4943 else
4944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4945 }
4946
4947 /* We don't support IA32_BNDCFGS MSR yet. */
4948 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4949
4950 NOREF(pszInstr);
4951 NOREF(pszFailure);
4952 return VINF_SUCCESS;
4953}
4954
4955
4956/**
4957 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4958 *
4959 * @param pVCpu The cross context virtual CPU structure.
4960 * @param pszInstr The VMX instruction name (for logging purposes).
4961 */
4962DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4963{
4964 /*
4965 * Segment registers.
4966 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4967 */
4968 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4969 const char *const pszFailure = "VM-exit";
4970 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4971 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4972 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4973
4974 /* Selectors. */
4975 if ( !fGstInV86Mode
4976 && !fUnrestrictedGuest
4977 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4979
4980 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4981 {
4982 CPUMSELREG SelReg;
4983 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4984 if (RT_LIKELY(rc == VINF_SUCCESS))
4985 { /* likely */ }
4986 else
4987 return rc;
4988
4989 /*
4990 * Virtual-8086 mode checks.
4991 */
4992 if (fGstInV86Mode)
4993 {
4994 /* Base address. */
4995 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4996 { /* likely */ }
4997 else
4998 {
4999 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5001 }
5002
5003 /* Limit. */
5004 if (SelReg.u32Limit == 0xffff)
5005 { /* likely */ }
5006 else
5007 {
5008 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5010 }
5011
5012 /* Attribute. */
5013 if (SelReg.Attr.u == 0xf3)
5014 { /* likely */ }
5015 else
5016 {
5017 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5019 }
5020
5021 /* We're done; move to checking the next segment. */
5022 continue;
5023 }
5024
5025 /* Checks done by 64-bit CPUs. */
5026 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5027 {
5028 /* Base address. */
5029 if ( iSegReg == X86_SREG_FS
5030 || iSegReg == X86_SREG_GS)
5031 {
5032 if (X86_IS_CANONICAL(SelReg.u64Base))
5033 { /* likely */ }
5034 else
5035 {
5036 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5038 }
5039 }
5040 else if (iSegReg == X86_SREG_CS)
5041 {
5042 if (!RT_HI_U32(SelReg.u64Base))
5043 { /* likely */ }
5044 else
5045 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5046 }
5047 else
5048 {
5049 if ( SelReg.Attr.n.u1Unusable
5050 || !RT_HI_U32(SelReg.u64Base))
5051 { /* likely */ }
5052 else
5053 {
5054 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5056 }
5057 }
5058 }
5059
5060 /*
5061 * Checks outside Virtual-8086 mode.
5062 */
5063 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5064 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5065 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5066 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5067 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5068 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5069 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5070 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5071
5072 /* Code or usable segment. */
5073 if ( iSegReg == X86_SREG_CS
5074 || fUsable)
5075 {
5076 /* Reserved bits (bits 31:17 and bits 11:8). */
5077 if (!(SelReg.Attr.u & 0xfffe0f00))
5078 { /* likely */ }
5079 else
5080 {
5081 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5083 }
5084
5085 /* Descriptor type. */
5086 if (fCodeDataSeg)
5087 { /* likely */ }
5088 else
5089 {
5090 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5092 }
5093
5094 /* Present. */
5095 if (fPresent)
5096 { /* likely */ }
5097 else
5098 {
5099 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5101 }
5102
5103 /* Granularity. */
5104 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5105 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5106 { /* likely */ }
5107 else
5108 {
5109 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5111 }
5112 }
5113
5114 if (iSegReg == X86_SREG_CS)
5115 {
5116 /* Segment Type and DPL. */
5117 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5118 && fUnrestrictedGuest)
5119 {
5120 if (uDpl == 0)
5121 { /* likely */ }
5122 else
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5124 }
5125 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5126 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5127 {
5128 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5129 if (uDpl == AttrSs.n.u2Dpl)
5130 { /* likely */ }
5131 else
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5133 }
5134 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5135 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5136 {
5137 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5138 if (uDpl <= AttrSs.n.u2Dpl)
5139 { /* likely */ }
5140 else
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5142 }
5143 else
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5145
5146 /* Def/Big. */
5147 if ( fGstInLongMode
5148 && fSegLong)
5149 {
5150 if (uDefBig == 0)
5151 { /* likely */ }
5152 else
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5154 }
5155 }
5156 else if (iSegReg == X86_SREG_SS)
5157 {
5158 /* Segment Type. */
5159 if ( !fUsable
5160 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5161 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5165
5166 /* DPL. */
5167 if (!fUnrestrictedGuest)
5168 {
5169 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5173 }
5174 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5175 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5176 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5177 {
5178 if (uDpl == 0)
5179 { /* likely */ }
5180 else
5181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5182 }
5183 }
5184 else
5185 {
5186 /* DS, ES, FS, GS. */
5187 if (fUsable)
5188 {
5189 /* Segment type. */
5190 if (uSegType & X86_SEL_TYPE_ACCESSED)
5191 { /* likely */ }
5192 else
5193 {
5194 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5196 }
5197
5198 if ( !(uSegType & X86_SEL_TYPE_CODE)
5199 || (uSegType & X86_SEL_TYPE_READ))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5203
5204 /* DPL. */
5205 if ( !fUnrestrictedGuest
5206 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5207 {
5208 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5209 { /* likely */ }
5210 else
5211 {
5212 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5214 }
5215 }
5216 }
5217 }
5218 }
5219
5220 /*
5221 * LDTR.
5222 */
5223 {
5224 CPUMSELREG Ldtr;
5225 Ldtr.Sel = pVmcs->GuestLdtr;
5226 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5227 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5228 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5229
5230 if (!Ldtr.Attr.n.u1Unusable)
5231 {
5232 /* Selector. */
5233 if (!(Ldtr.Sel & X86_SEL_LDT))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5237
5238 /* Base. */
5239 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5240 {
5241 if (X86_IS_CANONICAL(Ldtr.u64Base))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5245 }
5246
5247 /* Attributes. */
5248 /* Reserved bits (bits 31:17 and bits 11:8). */
5249 if (!(Ldtr.Attr.u & 0xfffe0f00))
5250 { /* likely */ }
5251 else
5252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5253
5254 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5258
5259 if (!Ldtr.Attr.n.u1DescType)
5260 { /* likely */ }
5261 else
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5263
5264 if (Ldtr.Attr.n.u1Present)
5265 { /* likely */ }
5266 else
5267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5268
5269 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5270 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5271 { /* likely */ }
5272 else
5273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5274 }
5275 }
5276
5277 /*
5278 * TR.
5279 */
5280 {
5281 CPUMSELREG Tr;
5282 Tr.Sel = pVmcs->GuestTr;
5283 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5284 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5285 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5286
5287 /* Selector. */
5288 if (!(Tr.Sel & X86_SEL_LDT))
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5292
5293 /* Base. */
5294 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5295 {
5296 if (X86_IS_CANONICAL(Tr.u64Base))
5297 { /* likely */ }
5298 else
5299 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5300 }
5301
5302 /* Attributes. */
5303 /* Reserved bits (bits 31:17 and bits 11:8). */
5304 if (!(Tr.Attr.u & 0xfffe0f00))
5305 { /* likely */ }
5306 else
5307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5308
5309 if (!Tr.Attr.n.u1Unusable)
5310 { /* likely */ }
5311 else
5312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5313
5314 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5315 || ( !fGstInLongMode
5316 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5317 { /* likely */ }
5318 else
5319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5320
5321 if (!Tr.Attr.n.u1DescType)
5322 { /* likely */ }
5323 else
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5325
5326 if (Tr.Attr.n.u1Present)
5327 { /* likely */ }
5328 else
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5330
5331 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5332 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5333 { /* likely */ }
5334 else
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5336 }
5337
5338 NOREF(pszInstr);
5339 NOREF(pszFailure);
5340 return VINF_SUCCESS;
5341}
5342
5343
5344/**
5345 * Checks guest GDTR and IDTR as part of VM-entry.
5346 *
5347 * @param pVCpu The cross context virtual CPU structure.
5348 * @param pszInstr The VMX instruction name (for logging purposes).
5349 */
5350DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5351{
5352 /*
5353 * GDTR and IDTR.
5354 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5355 */
5356 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5357 const char *const pszFailure = "VM-exit";
5358
5359 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5360 {
5361 /* Base. */
5362 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5363 { /* likely */ }
5364 else
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5366
5367 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5371 }
5372
5373 /* Limit. */
5374 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5375 { /* likely */ }
5376 else
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5378
5379 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5380 { /* likely */ }
5381 else
5382 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5383
5384 NOREF(pszInstr);
5385 NOREF(pszFailure);
5386 return VINF_SUCCESS;
5387}
5388
5389
5390/**
5391 * Checks guest RIP and RFLAGS as part of VM-entry.
5392 *
5393 * @param pVCpu The cross context virtual CPU structure.
5394 * @param pszInstr The VMX instruction name (for logging purposes).
5395 */
5396DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5397{
5398 /*
5399 * RIP and RFLAGS.
5400 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5401 */
5402 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5403 const char *const pszFailure = "VM-exit";
5404 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5405
5406 /* RIP. */
5407 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5408 {
5409 X86DESCATTR AttrCs;
5410 AttrCs.u = pVmcs->u32GuestCsAttr;
5411 if ( !fGstInLongMode
5412 || !AttrCs.n.u1Long)
5413 {
5414 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5418 }
5419
5420 if ( fGstInLongMode
5421 && AttrCs.n.u1Long)
5422 {
5423 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5424 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5425 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5429 }
5430 }
5431
5432 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5433 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5434 : pVmcs->u64GuestRFlags.s.Lo;
5435 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5436 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5440
5441 if ( fGstInLongMode
5442 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5443 {
5444 if (!(uGuestRFlags & X86_EFL_VM))
5445 { /* likely */ }
5446 else
5447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5448 }
5449
5450 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5451 {
5452 if (uGuestRFlags & X86_EFL_IF)
5453 { /* likely */ }
5454 else
5455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5456 }
5457
5458 NOREF(pszInstr);
5459 NOREF(pszFailure);
5460 return VINF_SUCCESS;
5461}
5462
5463
5464/**
5465 * Checks guest non-register state as part of VM-entry.
5466 *
5467 * @param pVCpu The cross context virtual CPU structure.
5468 * @param pszInstr The VMX instruction name (for logging purposes).
5469 */
5470DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5471{
5472 /*
5473 * Guest non-register state.
5474 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5475 */
5476 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5477 const char *const pszFailure = "VM-exit";
5478
5479 /*
5480 * Activity state.
5481 */
5482 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5483 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5484 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5488
5489 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5490 if ( !AttrSs.n.u2Dpl
5491 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5495
5496 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5497 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5498 {
5499 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5500 { /* likely */ }
5501 else
5502 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5503 }
5504
5505 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5506 {
5507 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5508 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5509 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5510 switch (pVmcs->u32GuestActivityState)
5511 {
5512 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5513 {
5514 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5515 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5516 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5517 && ( uVector == X86_XCPT_DB
5518 || uVector == X86_XCPT_MC))
5519 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5520 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5524 break;
5525 }
5526
5527 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5528 {
5529 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5530 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5531 && uVector == X86_XCPT_MC))
5532 { /* likely */ }
5533 else
5534 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5535 break;
5536 }
5537
5538 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5539 default:
5540 break;
5541 }
5542 }
5543
5544 /*
5545 * Interruptibility state.
5546 */
5547 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5548 { /* likely */ }
5549 else
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5551
5552 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5553 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5557
5558 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5559 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5560 { /* likely */ }
5561 else
5562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5563
5564 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5565 {
5566 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5567 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5568 {
5569 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5570 { /* likely */ }
5571 else
5572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5573 }
5574 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5575 {
5576 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5577 { /* likely */ }
5578 else
5579 {
5580 /*
5581 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5582 * We update the Exit qualification only when blocking-by-STI is set
5583 * without blocking-by-MovSS being set. Although in practise it does not
5584 * make much difference since the order of checks are implementation defined.
5585 */
5586 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5587 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5589 }
5590
5591 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5592 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5593 { /* likely */ }
5594 else
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5596 }
5597 }
5598
5599 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5600 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5601 { /* likely */ }
5602 else
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5604
5605 /* We don't support SGX yet. So enclave-interruption must not be set. */
5606 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5607 { /* likely */ }
5608 else
5609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5610
5611 /*
5612 * Pending debug exceptions.
5613 */
5614 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5615 ? pVmcs->u64GuestPendingDbgXcpts.u
5616 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5617 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5621
5622 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5623 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5624 {
5625 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5626 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5627 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5629
5630 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5631 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5632 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5634 }
5635
5636 /* We don't support RTM (Real-time Transactional Memory) yet. */
5637 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5638 { /* likely */ }
5639 else
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5641
5642 /*
5643 * VMCS link pointer.
5644 */
5645 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5646 {
5647 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5648 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5649 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5650 { /* likely */ }
5651 else
5652 {
5653 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5655 }
5656
5657 /* Validate the address. */
5658 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5659 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5660 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5661 { /* likely */ }
5662 else
5663 {
5664 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5666 }
5667 }
5668
5669 NOREF(pszInstr);
5670 NOREF(pszFailure);
5671 return VINF_SUCCESS;
5672}
5673
5674
5675/**
5676 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5677 * VM-entry.
5678 *
5679 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5680 * @param pVCpu The cross context virtual CPU structure.
5681 * @param pszInstr The VMX instruction name (for logging purposes).
5682 * @param pVmcs Pointer to the virtual VMCS.
5683 */
5684IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5685{
5686 /*
5687 * Check PDPTEs.
5688 * See Intel spec. 4.4.1 "PDPTE Registers".
5689 */
5690 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5691 const char *const pszFailure = "VM-exit";
5692
5693 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5694 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5695 if (RT_SUCCESS(rc))
5696 {
5697 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5698 {
5699 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5700 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5701 { /* likely */ }
5702 else
5703 {
5704 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5705 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5706 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5707 }
5708 }
5709 }
5710 else
5711 {
5712 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5714 }
5715
5716 NOREF(pszFailure);
5717 NOREF(pszInstr);
5718 return rc;
5719}
5720
5721
5722/**
5723 * Checks guest PDPTEs as part of VM-entry.
5724 *
5725 * @param pVCpu The cross context virtual CPU structure.
5726 * @param pszInstr The VMX instruction name (for logging purposes).
5727 */
5728DECLINLINE(int) iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5729{
5730 /*
5731 * Guest PDPTEs.
5732 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5733 */
5734 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5735 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5736
5737 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5738 int rc;
5739 if ( !fGstInLongMode
5740 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5741 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5742 {
5743 /*
5744 * We don't support nested-paging for nested-guests yet.
5745 *
5746 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5747 * rather we need to check the PDPTEs referenced by the guest CR3.
5748 */
5749 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5750 }
5751 else
5752 rc = VINF_SUCCESS;
5753 return rc;
5754}
5755
5756
5757/**
5758 * Checks guest-state as part of VM-entry.
5759 *
5760 * @returns VBox status code.
5761 * @param pVCpu The cross context virtual CPU structure.
5762 * @param pszInstr The VMX instruction name (for logging purposes).
5763 */
5764IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5765{
5766 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5767 if (RT_SUCCESS(rc))
5768 {
5769 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5770 if (RT_SUCCESS(rc))
5771 {
5772 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5773 if (RT_SUCCESS(rc))
5774 {
5775 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5776 if (RT_SUCCESS(rc))
5777 {
5778 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5779 if (RT_SUCCESS(rc))
5780 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5781 }
5782 }
5783 }
5784 }
5785 return rc;
5786}
5787
5788
5789/**
5790 * Checks host-state as part of VM-entry.
5791 *
5792 * @returns VBox status code.
5793 * @param pVCpu The cross context virtual CPU structure.
5794 * @param pszInstr The VMX instruction name (for logging purposes).
5795 */
5796IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5797{
5798 /*
5799 * Host Control Registers and MSRs.
5800 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5801 */
5802 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5803 const char * const pszFailure = "VMFail";
5804
5805 /* CR0 reserved bits. */
5806 {
5807 /* CR0 MB1 bits. */
5808 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5809 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5810 { /* likely */ }
5811 else
5812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5813
5814 /* CR0 MBZ bits. */
5815 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5816 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5817 { /* likely */ }
5818 else
5819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5820 }
5821
5822 /* CR4 reserved bits. */
5823 {
5824 /* CR4 MB1 bits. */
5825 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5826 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5830
5831 /* CR4 MBZ bits. */
5832 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5833 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5834 { /* likely */ }
5835 else
5836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5837 }
5838
5839 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5840 {
5841 /* CR3 reserved bits. */
5842 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5843 { /* likely */ }
5844 else
5845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5846
5847 /* SYSENTER ESP and SYSENTER EIP. */
5848 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5849 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5850 { /* likely */ }
5851 else
5852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5853 }
5854
5855 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5856 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5857
5858 /* PAT MSR. */
5859 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5860 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5861 { /* likely */ }
5862 else
5863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5864
5865 /* EFER MSR. */
5866 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5867 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5868 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5872
5873 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5874 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5875 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5876 if ( fHostInLongMode == fHostLma
5877 && fHostInLongMode == fHostLme)
5878 { /* likely */ }
5879 else
5880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5881
5882 /*
5883 * Host Segment and Descriptor-Table Registers.
5884 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5885 */
5886 /* Selector RPL and TI. */
5887 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5888 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5889 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5890 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5891 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5892 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5893 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5894 { /* likely */ }
5895 else
5896 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5897
5898 /* CS and TR selectors cannot be 0. */
5899 if ( pVmcs->HostCs
5900 && pVmcs->HostTr)
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5904
5905 /* SS cannot be 0 if 32-bit host. */
5906 if ( fHostInLongMode
5907 || pVmcs->HostSs)
5908 { /* likely */ }
5909 else
5910 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5911
5912 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5913 {
5914 /* FS, GS, GDTR, IDTR, TR base address. */
5915 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5916 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5917 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5918 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5919 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5923 }
5924
5925 /*
5926 * Host address-space size for 64-bit CPUs.
5927 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5928 */
5929 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5930 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5931 {
5932 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5933
5934 /* Logical processor in IA-32e mode. */
5935 if (fCpuInLongMode)
5936 {
5937 if (fHostInLongMode)
5938 {
5939 /* PAE must be set. */
5940 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5941 { /* likely */ }
5942 else
5943 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5944
5945 /* RIP must be canonical. */
5946 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5947 { /* likely */ }
5948 else
5949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5950 }
5951 else
5952 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5953 }
5954 else
5955 {
5956 /* Logical processor is outside IA-32e mode. */
5957 if ( !fGstInLongMode
5958 && !fHostInLongMode)
5959 {
5960 /* PCIDE should not be set. */
5961 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5962 { /* likely */ }
5963 else
5964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5965
5966 /* The high 32-bits of RIP MBZ. */
5967 if (!pVmcs->u64HostRip.s.Hi)
5968 { /* likely */ }
5969 else
5970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5971 }
5972 else
5973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5974 }
5975 }
5976 else
5977 {
5978 /* Host address-space size for 32-bit CPUs. */
5979 if ( !fGstInLongMode
5980 && !fHostInLongMode)
5981 { /* likely */ }
5982 else
5983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5984 }
5985
5986 NOREF(pszInstr);
5987 NOREF(pszFailure);
5988 return VINF_SUCCESS;
5989}
5990
5991
5992/**
5993 * Checks VMCS controls fields as part of VM-entry.
5994 *
5995 * @returns VBox status code.
5996 * @param pVCpu The cross context virtual CPU structure.
5997 * @param pszInstr The VMX instruction name (for logging purposes).
5998 *
5999 * @remarks This may update secondary-processor based VM-execution control fields
6000 * in the current VMCS if necessary.
6001 */
6002IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
6003{
6004 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6005 const char * const pszFailure = "VMFail";
6006
6007 /*
6008 * VM-execution controls.
6009 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6010 */
6011 {
6012 /* Pin-based VM-execution controls. */
6013 {
6014 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6015 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6016 { /* likely */ }
6017 else
6018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6019
6020 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6021 { /* likely */ }
6022 else
6023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6024 }
6025
6026 /* Processor-based VM-execution controls. */
6027 {
6028 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6029 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6030 { /* likely */ }
6031 else
6032 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6033
6034 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6035 { /* likely */ }
6036 else
6037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6038 }
6039
6040 /* Secondary processor-based VM-execution controls. */
6041 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6042 {
6043 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6044 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6045 { /* likely */ }
6046 else
6047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6048
6049 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6050 { /* likely */ }
6051 else
6052 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6053 }
6054 else
6055 Assert(!pVmcs->u32ProcCtls2);
6056
6057 /* CR3-target count. */
6058 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6059 { /* likely */ }
6060 else
6061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6062
6063 /* I/O bitmaps physical addresses. */
6064 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6065 {
6066 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6067 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6068 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6069 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6073
6074 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6075 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6076 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6077 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6078 { /* likely */ }
6079 else
6080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6081 }
6082
6083 /* MSR bitmap physical address. */
6084 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6085 {
6086 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6087 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6088 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6089 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6090 { /* likely */ }
6091 else
6092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6093 }
6094
6095 /* TPR shadow related controls. */
6096 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6097 {
6098 /* Virtual-APIC page physical address. */
6099 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6100 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6101 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6102 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6103 { /* likely */ }
6104 else
6105 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6106
6107 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6108 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6109 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6110 { /* likely */ }
6111 else
6112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6113
6114 /* The rest done XXX document */
6115 }
6116 else
6117 {
6118 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6119 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6120 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6121 { /* likely */ }
6122 else
6123 {
6124 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6125 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6126 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6128 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6130 }
6131 }
6132
6133 /* NMI exiting and virtual-NMIs. */
6134 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6135 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6139
6140 /* Virtual-NMIs and NMI-window exiting. */
6141 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6142 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6146
6147 /* Virtualize APIC accesses. */
6148 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6149 {
6150 /* APIC-access physical address. */
6151 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6152 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6153 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6154 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6158
6159 /*
6160 * Disallow APIC-access page and virtual-APIC page from being the same address.
6161 * Note! This is not an Intel requirement, but one imposed by our implementation.
6162 */
6163 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6164 * redirecting accesses between the APIC-access page and the virtual-APIC
6165 * page. If any nested hypervisor requires this, we can implement it later. */
6166 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6167 {
6168 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6169 if (GCPhysVirtApic != GCPhysApicAccess)
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6173 }
6174 }
6175
6176 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6177 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6178 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6179 { /* likely */ }
6180 else
6181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6182
6183 /* Virtual-interrupt delivery requires external interrupt exiting. */
6184 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6185 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6186 { /* likely */ }
6187 else
6188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6189
6190 /* VPID. */
6191 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6192 || pVmcs->u16Vpid != 0)
6193 { /* likely */ }
6194 else
6195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6196
6197 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6198 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6199 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6200 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6201 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6202 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6203 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6204 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6205
6206 /* VMCS shadowing. */
6207 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6208 {
6209 /* VMREAD-bitmap physical address. */
6210 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6211 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6212 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6213 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6214 { /* likely */ }
6215 else
6216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6217
6218 /* VMWRITE-bitmap physical address. */
6219 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6220 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6221 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6222 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6223 { /* likely */ }
6224 else
6225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6226 }
6227 }
6228
6229 /*
6230 * VM-exit controls.
6231 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6232 */
6233 {
6234 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6235 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6236 { /* likely */ }
6237 else
6238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6239
6240 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6241 { /* likely */ }
6242 else
6243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6244
6245 /* Save preemption timer without activating it. */
6246 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6247 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6251
6252 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6253 if (pVmcs->u32ExitMsrStoreCount)
6254 {
6255 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6256 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6257 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6261 }
6262
6263 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6264 if (pVmcs->u32ExitMsrLoadCount)
6265 {
6266 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6267 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6268 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6269 { /* likely */ }
6270 else
6271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6272 }
6273 }
6274
6275 /*
6276 * VM-entry controls.
6277 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6278 */
6279 {
6280 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6281 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6282 { /* likely */ }
6283 else
6284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6285
6286 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6287 { /* likely */ }
6288 else
6289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6290
6291 /* Event injection. */
6292 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6293 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6294 {
6295 /* Type and vector. */
6296 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6297 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6298 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6299 if ( !uRsvd
6300 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6301 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6305
6306 /* Exception error code. */
6307 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6308 {
6309 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6310 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6311 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6312 { /* likely */ }
6313 else
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6315
6316 /* Exceptions that provide an error code. */
6317 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6318 && ( uVector == X86_XCPT_DF
6319 || uVector == X86_XCPT_TS
6320 || uVector == X86_XCPT_NP
6321 || uVector == X86_XCPT_SS
6322 || uVector == X86_XCPT_GP
6323 || uVector == X86_XCPT_PF
6324 || uVector == X86_XCPT_AC))
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6328
6329 /* Exception error-code reserved bits. */
6330 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6331 { /* likely */ }
6332 else
6333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6334
6335 /* Injecting a software interrupt, software exception or privileged software exception. */
6336 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6337 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6338 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6339 {
6340 /* Instruction length must be in the range 0-15. */
6341 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6342 { /* likely */ }
6343 else
6344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6345
6346 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6347 if ( pVmcs->u32EntryInstrLen != 0
6348 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6349 { /* likely */ }
6350 else
6351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6352 }
6353 }
6354 }
6355
6356 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6357 if (pVmcs->u32EntryMsrLoadCount)
6358 {
6359 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6360 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6361 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6362 { /* likely */ }
6363 else
6364 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6365 }
6366
6367 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6368 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6369 }
6370
6371 NOREF(pszInstr);
6372 NOREF(pszFailure);
6373 return VINF_SUCCESS;
6374}
6375
6376
6377/**
6378 * Loads the guest control registers, debug register and some MSRs as part of
6379 * VM-entry.
6380 *
6381 * @param pVCpu The cross context virtual CPU structure.
6382 */
6383IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6384{
6385 /*
6386 * Load guest control registers, debug registers and MSRs.
6387 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6388 */
6389 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6390
6391 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6392 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6393 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6394 CPUMSetGuestCR0(pVCpu, uGstCr0);
6395 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6396 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6397
6398 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6399 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6400
6401 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6402 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6403 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6404
6405 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6406 {
6407 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6408
6409 /* EFER MSR. */
6410 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6411 {
6412 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6413 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6414 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6415 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6416 if (fGstInLongMode)
6417 {
6418 /* If the nested-guest is in long mode, LMA and LME are both set. */
6419 Assert(fGstPaging);
6420 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6421 }
6422 else
6423 {
6424 /*
6425 * If the nested-guest is outside long mode:
6426 * - With paging: LMA is cleared, LME is cleared.
6427 * - Without paging: LMA is cleared, LME is left unmodified.
6428 */
6429 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6430 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6431 }
6432 }
6433 /* else: see below. */
6434 }
6435
6436 /* PAT MSR. */
6437 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6438 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6439
6440 /* EFER MSR. */
6441 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6442 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6443
6444 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6445 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6446
6447 /* We don't support IA32_BNDCFGS MSR yet. */
6448 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6449
6450 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6451}
6452
6453
6454/**
6455 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6456 *
6457 * @param pVCpu The cross context virtual CPU structure.
6458 */
6459IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6460{
6461 /*
6462 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6463 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6464 */
6465 /* CS, SS, ES, DS, FS, GS. */
6466 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6467 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6468 {
6469 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6470 CPUMSELREG VmcsSelReg;
6471 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6472 AssertRC(rc); NOREF(rc);
6473 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6474 {
6475 pGstSelReg->Sel = VmcsSelReg.Sel;
6476 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6477 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6478 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6479 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6480 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6481 }
6482 else
6483 {
6484 pGstSelReg->Sel = VmcsSelReg.Sel;
6485 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6486 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6487 switch (iSegReg)
6488 {
6489 case X86_SREG_CS:
6490 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6491 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6492 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6493 break;
6494
6495 case X86_SREG_SS:
6496 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6497 pGstSelReg->u32Limit = 0;
6498 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6499 break;
6500
6501 case X86_SREG_ES:
6502 case X86_SREG_DS:
6503 pGstSelReg->u64Base = 0;
6504 pGstSelReg->u32Limit = 0;
6505 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6506 break;
6507
6508 case X86_SREG_FS:
6509 case X86_SREG_GS:
6510 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6511 pGstSelReg->u32Limit = 0;
6512 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6513 break;
6514 }
6515 Assert(pGstSelReg->Attr.n.u1Unusable);
6516 }
6517 }
6518
6519 /* LDTR. */
6520 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6521 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6522 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6523 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6524 {
6525 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6526 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6527 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6528 }
6529 else
6530 {
6531 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6532 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6533 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6534 }
6535
6536 /* TR. */
6537 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6538 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6539 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6540 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6541 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6542 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6543 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6544
6545 /* GDTR. */
6546 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6547 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6548
6549 /* IDTR. */
6550 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6551 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6552}
6553
6554
6555/**
6556 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6557 *
6558 * @returns VBox status code.
6559 * @param pVCpu The cross context virtual CPU structure.
6560 * @param pszInstr The VMX instruction name (for logging purposes).
6561 */
6562IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6563{
6564 /*
6565 * Load guest MSRs.
6566 * See Intel spec. 26.4 "Loading MSRs".
6567 */
6568 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6569 const char *const pszFailure = "VM-exit";
6570
6571 /*
6572 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6573 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6574 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6575 */
6576 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6577 if (!cMsrs)
6578 return VINF_SUCCESS;
6579
6580 /*
6581 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6582 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6583 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6584 */
6585 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6586 if (fIsMsrCountValid)
6587 { /* likely */ }
6588 else
6589 {
6590 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6592 }
6593
6594 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6595 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6596 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6597 if (RT_SUCCESS(rc))
6598 {
6599 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6600 Assert(pMsr);
6601 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6602 {
6603 if ( !pMsr->u32Reserved
6604 && pMsr->u32Msr != MSR_K8_FS_BASE
6605 && pMsr->u32Msr != MSR_K8_GS_BASE
6606 && pMsr->u32Msr != MSR_K6_EFER
6607 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6608 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6609 {
6610 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6611 if (rcStrict == VINF_SUCCESS)
6612 continue;
6613
6614 /*
6615 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6616 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6617 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6618 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6619 * MSR in ring-0 if possible, or come up with a better, generic solution.
6620 */
6621 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6622 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6623 ? kVmxVDiag_Vmentry_MsrLoadRing3
6624 : kVmxVDiag_Vmentry_MsrLoad;
6625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6626 }
6627 else
6628 {
6629 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6631 }
6632 }
6633 }
6634 else
6635 {
6636 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6638 }
6639
6640 NOREF(pszInstr);
6641 NOREF(pszFailure);
6642 return VINF_SUCCESS;
6643}
6644
6645
6646/**
6647 * Loads the guest-state non-register state as part of VM-entry.
6648 *
6649 * @returns VBox status code.
6650 * @param pVCpu The cross context virtual CPU structure.
6651 *
6652 * @remarks This must be called only after loading the nested-guest register state
6653 * (especially nested-guest RIP).
6654 */
6655IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6656{
6657 /*
6658 * Load guest non-register state.
6659 * See Intel spec. 26.6 "Special Features of VM Entry"
6660 */
6661 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6662
6663 /*
6664 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6665 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6666 *
6667 * See Intel spec. 26.6.1 "Interruptibility State".
6668 */
6669 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6670 if ( !fEntryVectoring
6671 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6672 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6673 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6674 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6675
6676 /* NMI blocking. */
6677 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6678 {
6679 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6680 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6681 else
6682 {
6683 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6684 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6685 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6686 }
6687 }
6688 else
6689 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6690
6691 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6692
6693 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6694 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6695
6696 /* VPID is irrelevant. We don't support VPID yet. */
6697
6698 /* Clear address-range monitoring. */
6699 EMMonitorWaitClear(pVCpu);
6700}
6701
6702
6703/**
6704 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6705 *
6706 * @param pVCpu The cross context virtual CPU structure.
6707 * @param pszInstr The VMX instruction name (for logging purposes).
6708 *
6709 * @remarks This assumes various VMCS related data structure pointers have already
6710 * been verified prior to calling this function.
6711 */
6712IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6713{
6714 const char *const pszFailure = "VM-exit";
6715 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6716
6717 /*
6718 * Virtualize APIC accesses.
6719 */
6720 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6721 {
6722 /* APIC-access physical address. */
6723 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6724
6725 /*
6726 * Register the handler for the APIC-access page.
6727 *
6728 * We don't deregister the APIC-access page handler during the VM-exit as a different
6729 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6730 *
6731 * We leave the page registered until the first access that happens outside VMX non-root
6732 * mode. Guest software is allowed to access structures such as the APIC-access page
6733 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6734 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6735 *
6736 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6737 */
6738 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6739 {
6740 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6741 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6742 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6743 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6744 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6745 if (RT_SUCCESS(rc))
6746 { /* likely */ }
6747 else
6748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6749 }
6750 }
6751
6752 /*
6753 * VMCS shadowing.
6754 */
6755 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6756 {
6757 /* Read the VMREAD-bitmap. */
6758 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6759 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6760 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6761 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6762 if (RT_SUCCESS(rc))
6763 { /* likely */ }
6764 else
6765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6766
6767 /* Read the VMWRITE-bitmap. */
6768 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6769 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6770 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6771 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6772 if (RT_SUCCESS(rc))
6773 { /* likely */ }
6774 else
6775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6776 }
6777
6778 /*
6779 * I/O bitmaps.
6780 */
6781 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6782 {
6783 /* Read the IO bitmap A. */
6784 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6785 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap));
6786 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap),
6787 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6788 if (RT_SUCCESS(rc))
6789 { /* likely */ }
6790 else
6791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6792
6793 /* Read the IO bitmap B. */
6794 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6795 uint8_t *pbIoBitmapB = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
6796 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pbIoBitmapB, GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6797 if (RT_SUCCESS(rc))
6798 { /* likely */ }
6799 else
6800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6801 }
6802
6803 /*
6804 * TPR shadow and Virtual-APIC page.
6805 */
6806 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6807 {
6808 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6809 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6810 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6811 {
6812 /* Read the VTPR from the virtual-APIC page. */
6813 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6814 uint8_t u8VTpr;
6815 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6816 if (RT_SUCCESS(rc))
6817 { /* likely */ }
6818 else
6819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6820
6821 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6822 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6823 { /* likely */ }
6824 else
6825 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6826 }
6827 }
6828
6829 /*
6830 * VMCS link pointer.
6831 */
6832 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6833 {
6834 /* Read the VMCS-link pointer from guest memory. */
6835 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6836 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6837 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6838 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
6839 if (RT_SUCCESS(rc))
6840 { /* likely */ }
6841 else
6842 {
6843 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6844 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6845 }
6846
6847 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6848 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6849 { /* likely */ }
6850 else
6851 {
6852 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6854 }
6855
6856 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6857 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6858 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6859 { /* likely */ }
6860 else
6861 {
6862 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6864 }
6865
6866 /* Update our cache of the guest physical address of the shadow VMCS. */
6867 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6868 }
6869
6870 /*
6871 * MSR bitmap.
6872 */
6873 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6874 {
6875 /* Read the MSR bitmap. */
6876 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6877 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6879 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6880 if (RT_SUCCESS(rc))
6881 { /* likely */ }
6882 else
6883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6884 }
6885
6886 NOREF(pszFailure);
6887 NOREF(pszInstr);
6888 return VINF_SUCCESS;
6889}
6890
6891
6892/**
6893 * Loads the guest-state as part of VM-entry.
6894 *
6895 * @returns VBox status code.
6896 * @param pVCpu The cross context virtual CPU structure.
6897 * @param pszInstr The VMX instruction name (for logging purposes).
6898 *
6899 * @remarks This must be done after all the necessary steps prior to loading of
6900 * guest-state (e.g. checking various VMCS state).
6901 */
6902IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6903{
6904 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6905 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6906
6907 /* Load guest segment registers. */
6908 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6909
6910 /*
6911 * Load guest RIP, RSP and RFLAGS.
6912 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6913 */
6914 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6915 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6916 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6917 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6918
6919 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6920 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6921 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6922
6923 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6924 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6925
6926 /* Load VMX related structures and state referenced by the VMCS. */
6927 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6928 if (rc == VINF_SUCCESS)
6929 { /* likely */ }
6930 else
6931 return rc;
6932
6933 NOREF(pszInstr);
6934 return VINF_SUCCESS;
6935}
6936
6937
6938/**
6939 * Returns whether there are is a pending debug exception on VM-entry.
6940 *
6941 * @param pVCpu The cross context virtual CPU structure.
6942 * @param pszInstr The VMX instruction name (for logging purposes).
6943 */
6944IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6945{
6946 /*
6947 * Pending debug exceptions.
6948 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6949 */
6950 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6951 Assert(pVmcs);
6952
6953 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6954 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6955 if (fPendingDbgXcpt)
6956 {
6957 uint8_t uEntryIntInfoType;
6958 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6959 if (fEntryVectoring)
6960 {
6961 switch (uEntryIntInfoType)
6962 {
6963 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6964 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6965 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6966 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6967 fPendingDbgXcpt = false;
6968 break;
6969
6970 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6971 {
6972 /*
6973 * Whether the pending debug exception for software exceptions other than
6974 * #BP and #OF is delivered after injecting the exception or is discard
6975 * is CPU implementation specific. We will discard them (easier).
6976 */
6977 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6978 if ( uVector != X86_XCPT_BP
6979 && uVector != X86_XCPT_OF)
6980 fPendingDbgXcpt = false;
6981 RT_FALL_THRU();
6982 }
6983 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6984 {
6985 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6986 fPendingDbgXcpt = false;
6987 break;
6988 }
6989 }
6990 }
6991 else
6992 {
6993 /*
6994 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6995 * pending debug exception is held pending or is discarded is CPU implementation
6996 * specific. We will discard them (easier).
6997 */
6998 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6999 fPendingDbgXcpt = false;
7000
7001 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7002 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7003 fPendingDbgXcpt = false;
7004 }
7005 }
7006
7007 NOREF(pszInstr);
7008 return fPendingDbgXcpt;
7009}
7010
7011
7012/**
7013 * Set up the monitor-trap flag (MTF).
7014 *
7015 * @param pVCpu The cross context virtual CPU structure.
7016 * @param pszInstr The VMX instruction name (for logging purposes).
7017 */
7018IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7019{
7020 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7021 Assert(pVmcs);
7022 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7023 {
7024 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7025 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7026 }
7027 else
7028 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7029 NOREF(pszInstr);
7030}
7031
7032
7033/**
7034 * Sets up NMI-window exiting.
7035 *
7036 * @param pVCpu The cross context virtual CPU structure.
7037 * @param pszInstr The VMX instruction name (for logging purposes).
7038 */
7039IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7040{
7041 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7042 Assert(pVmcs);
7043 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7044 {
7045 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7046 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7047 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7048 }
7049 else
7050 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7051 NOREF(pszInstr);
7052}
7053
7054
7055/**
7056 * Sets up interrupt-window exiting.
7057 *
7058 * @param pVCpu The cross context virtual CPU structure.
7059 * @param pszInstr The VMX instruction name (for logging purposes).
7060 */
7061IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7062{
7063 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7064 Assert(pVmcs);
7065 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7066 {
7067 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7068 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7069 }
7070 else
7071 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7072 NOREF(pszInstr);
7073}
7074
7075
7076/**
7077 * Set up the VMX-preemption timer.
7078 *
7079 * @param pVCpu The cross context virtual CPU structure.
7080 * @param pszInstr The VMX instruction name (for logging purposes).
7081 */
7082IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7083{
7084 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7085 Assert(pVmcs);
7086 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7087 {
7088 /*
7089 * If the timer is 0, we must cause a VM-exit before executing the first
7090 * nested-guest instruction. So we can flag as though the timer has already
7091 * expired and we will check and cause a VM-exit at the right priority elsewhere
7092 * in the code.
7093 */
7094 uint64_t uEntryTick;
7095 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7096 if (uPreemptTimer)
7097 {
7098 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7099 AssertRC(rc);
7100 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7101 }
7102 else
7103 {
7104 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7105 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7106 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7107 }
7108
7109 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7110 }
7111 else
7112 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7113
7114 NOREF(pszInstr);
7115}
7116
7117
7118/**
7119 * Injects an event using TRPM given a VM-entry interruption info. and related
7120 * fields.
7121 *
7122 * @param pVCpu The cross context virtual CPU structure.
7123 * @param pszInstr The VMX instruction name (for logging purposes).
7124 * @param uEntryIntInfo The VM-entry interruption info.
7125 * @param uErrCode The error code associated with the event if any.
7126 * @param cbInstr The VM-entry instruction length (for software
7127 * interrupts and software exceptions). Pass 0
7128 * otherwise.
7129 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7130 */
7131IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7132 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7133{
7134 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7135
7136 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7137 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7138 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7139
7140 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7141
7142 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7143 AssertRC(rc);
7144 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7145
7146 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7147 {
7148 TRPMSetErrorCode(pVCpu, uErrCode);
7149 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7150 }
7151
7152 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7153 {
7154 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7155 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7156 }
7157 else
7158 {
7159 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7160 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7161 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7162 {
7163 TRPMSetInstrLength(pVCpu, cbInstr);
7164 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7165 }
7166 }
7167
7168 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7169 {
7170 TRPMSetTrapDueToIcebp(pVCpu);
7171 Log(("%s: Injecting: icebp\n", pszInstr));
7172 }
7173
7174 NOREF(pszInstr);
7175}
7176
7177
7178/**
7179 * Performs event injection (if any) as part of VM-entry.
7180 *
7181 * @param pVCpu The cross context virtual CPU structure.
7182 * @param pszInstr The VMX instruction name (for logging purposes).
7183 */
7184IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7185{
7186 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7187
7188 /*
7189 * Inject events.
7190 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7191 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7192 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7193 * the actually delivery of this event.
7194 *
7195 * See Intel spec. 26.5 "Event Injection".
7196 */
7197 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7198 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7199
7200 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7201 if (fEntryIntInfoValid)
7202 {
7203 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7204 {
7205 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7206 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7207 }
7208 else
7209 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7210 pVCpu->cpum.GstCtx.cr2);
7211
7212 /*
7213 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7214 *
7215 * However, we do it here on VM-entry as well because while it isn't visible to guest
7216 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7217 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7218 *
7219 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7220 */
7221 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7222 }
7223 else
7224 {
7225 /*
7226 * Inject any pending guest debug exception.
7227 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7228 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7229 */
7230 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7231 if (fPendingDbgXcpt)
7232 {
7233 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7234 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7235 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7236 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7237 0 /* GCPtrFaultAddress */);
7238 }
7239 }
7240
7241 NOREF(pszInstr);
7242}
7243
7244
7245/**
7246 * Initializes all read-only VMCS fields as part of VM-entry.
7247 *
7248 * @param pVCpu The cross context virtual CPU structure.
7249 */
7250IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7251{
7252 /*
7253 * Any VMCS field which we do not establish on every VM-exit but may potentially
7254 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7255 * specified to be undefined, needs to be initialized here.
7256 *
7257 * Thus, it is especially important to clear the Exit qualification field
7258 * since it must be zero for VM-exits where it is not used. Similarly, the
7259 * VM-exit interruption information field's valid bit needs to be cleared for
7260 * the same reasons.
7261 */
7262 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7263 Assert(pVmcs);
7264
7265 /* 16-bit (none currently). */
7266 /* 32-bit. */
7267 pVmcs->u32RoVmInstrError = 0;
7268 pVmcs->u32RoExitReason = 0;
7269 pVmcs->u32RoExitIntInfo = 0;
7270 pVmcs->u32RoExitIntErrCode = 0;
7271 pVmcs->u32RoIdtVectoringInfo = 0;
7272 pVmcs->u32RoIdtVectoringErrCode = 0;
7273 pVmcs->u32RoExitInstrLen = 0;
7274 pVmcs->u32RoExitInstrInfo = 0;
7275
7276 /* 64-bit. */
7277 pVmcs->u64RoGuestPhysAddr.u = 0;
7278
7279 /* Natural-width. */
7280 pVmcs->u64RoExitQual.u = 0;
7281 pVmcs->u64RoIoRcx.u = 0;
7282 pVmcs->u64RoIoRsi.u = 0;
7283 pVmcs->u64RoIoRdi.u = 0;
7284 pVmcs->u64RoIoRip.u = 0;
7285 pVmcs->u64RoGuestLinearAddr.u = 0;
7286}
7287
7288
7289/**
7290 * VMLAUNCH/VMRESUME instruction execution worker.
7291 *
7292 * @returns Strict VBox status code.
7293 * @param pVCpu The cross context virtual CPU structure.
7294 * @param cbInstr The instruction length in bytes.
7295 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7296 * VMXINSTRID_VMRESUME).
7297 *
7298 * @remarks Common VMX instruction checks are already expected to by the caller,
7299 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7300 */
7301IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7302{
7303# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7304 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7305 return VINF_EM_RAW_EMULATE_INSTR;
7306# else
7307 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7308 || uInstrId == VMXINSTRID_VMRESUME);
7309 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7310
7311 /* Nested-guest intercept. */
7312 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7313 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7314
7315 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7316
7317 /*
7318 * Basic VM-entry checks.
7319 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7320 * The checks following that do not have to follow a specific order.
7321 *
7322 * See Intel spec. 26.1 "Basic VM-entry Checks".
7323 */
7324
7325 /* CPL. */
7326 if (pVCpu->iem.s.uCpl == 0)
7327 { /* likely */ }
7328 else
7329 {
7330 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7331 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7332 return iemRaiseGeneralProtectionFault0(pVCpu);
7333 }
7334
7335 /* Current VMCS valid. */
7336 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7337 { /* likely */ }
7338 else
7339 {
7340 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7341 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7342 iemVmxVmFailInvalid(pVCpu);
7343 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7344 return VINF_SUCCESS;
7345 }
7346
7347 /* Current VMCS is not a shadow VMCS. */
7348 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7349 { /* likely */ }
7350 else
7351 {
7352 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7353 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7354 iemVmxVmFailInvalid(pVCpu);
7355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7356 return VINF_SUCCESS;
7357 }
7358
7359 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7360 * use block-by-STI here which is not quite correct. */
7361 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7362 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7363 { /* likely */ }
7364 else
7365 {
7366 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7368 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7370 return VINF_SUCCESS;
7371 }
7372
7373 if (uInstrId == VMXINSTRID_VMLAUNCH)
7374 {
7375 /* VMLAUNCH with non-clear VMCS. */
7376 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7377 { /* likely */ }
7378 else
7379 {
7380 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7381 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7382 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7383 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7384 return VINF_SUCCESS;
7385 }
7386 }
7387 else
7388 {
7389 /* VMRESUME with non-launched VMCS. */
7390 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7391 { /* likely */ }
7392 else
7393 {
7394 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7395 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7396 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7397 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7398 return VINF_SUCCESS;
7399 }
7400 }
7401
7402 /*
7403 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7404 * while entering VMX non-root mode. We do some of this while checking VM-execution
7405 * controls. The nested hypervisor should not make assumptions and cannot expect
7406 * predictable behavior if changes to these structures are made in guest memory while
7407 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7408 * modify them anyway as we cache them in host memory.
7409 *
7410 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7411 */
7412 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7413 Assert(pVmcs);
7414 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7415
7416 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7417 if (RT_SUCCESS(rc))
7418 {
7419 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7420 if (RT_SUCCESS(rc))
7421 {
7422 /*
7423 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7424 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7425 * ones that may occur during VM-entry below).
7426 */
7427 iemVmxVmentryInitReadOnlyFields(pVCpu);
7428
7429 /*
7430 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7431 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7432 * VM-exit when required.
7433 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7434 */
7435 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7436
7437 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7438 if (RT_SUCCESS(rc))
7439 {
7440 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7441 if (RT_SUCCESS(rc))
7442 {
7443 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7444 if (RT_SUCCESS(rc))
7445 {
7446 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7447
7448 /* VMLAUNCH instruction must update the VMCS launch state. */
7449 if (uInstrId == VMXINSTRID_VMLAUNCH)
7450 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7451
7452 /* Perform the VMX transition (PGM updates). */
7453 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7454 if (rcStrict == VINF_SUCCESS)
7455 { /* likely */ }
7456 else if (RT_SUCCESS(rcStrict))
7457 {
7458 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7459 VBOXSTRICTRC_VAL(rcStrict)));
7460 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7461 }
7462 else
7463 {
7464 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7465 return rcStrict;
7466 }
7467
7468 /* Paranoia. */
7469 Assert(rcStrict == VINF_SUCCESS);
7470
7471 /* We've now entered nested-guest execution. */
7472 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7473
7474 /*
7475 * The priority of potential VM-exits during VM-entry is important.
7476 * The priorities of VM-exits and events are listed from highest
7477 * to lowest as follows:
7478 *
7479 * 1. Event injection.
7480 * 2. Trap on task-switch (T flag set in TSS).
7481 * 3. TPR below threshold / APIC-write.
7482 * 4. SMI, INIT.
7483 * 5. MTF exit.
7484 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7485 * 7. VMX-preemption timer.
7486 * 9. NMI-window exit.
7487 * 10. NMI injection.
7488 * 11. Interrupt-window exit.
7489 * 12. Virtual-interrupt injection.
7490 * 13. Interrupt injection.
7491 * 14. Process next instruction (fetch, decode, execute).
7492 */
7493
7494 /* Setup VMX-preemption timer. */
7495 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7496
7497 /* Setup monitor-trap flag. */
7498 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7499
7500 /* Setup NMI-window exiting. */
7501 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7502
7503 /* Setup interrupt-window exiting. */
7504 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7505
7506 /*
7507 * Inject any event that the nested hypervisor wants to inject.
7508 * Note! We cannot immediately perform the event injection here as we may have
7509 * pending PGM operations to perform due to switching page tables and/or
7510 * mode.
7511 */
7512 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7513
7514# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7515 /* Reschedule to IEM-only execution of the nested-guest. */
7516 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7517 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7518 if (rcSched != VINF_SUCCESS)
7519 iemSetPassUpStatus(pVCpu, rcSched);
7520# endif
7521
7522 /* Finally, done. */
7523 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7524 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7525 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7526 pVCpu->cpum.GstCtx.msrEFER));
7527 return VINF_SUCCESS;
7528 }
7529 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7530 pVmcs->u64RoExitQual.u);
7531 }
7532 }
7533 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7534 pVmcs->u64RoExitQual.u);
7535 }
7536
7537 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7538 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7539 return VINF_SUCCESS;
7540 }
7541
7542 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7544 return VINF_SUCCESS;
7545# endif
7546}
7547
7548
7549/**
7550 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7551 * (causes a VM-exit) or not.
7552 *
7553 * @returns @c true if the instruction is intercepted, @c false otherwise.
7554 * @param pVCpu The cross context virtual CPU structure.
7555 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7556 * VMX_EXIT_WRMSR).
7557 * @param idMsr The MSR.
7558 */
7559IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7560{
7561 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7562 Assert( uExitReason == VMX_EXIT_RDMSR
7563 || uExitReason == VMX_EXIT_WRMSR);
7564
7565 /* Consult the MSR bitmap if the feature is supported. */
7566 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7567 Assert(pVmcs);
7568 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7569 {
7570 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7571 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7572 if (uExitReason == VMX_EXIT_RDMSR)
7573 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7574 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7575 }
7576
7577 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7578 return true;
7579}
7580
7581
7582/**
7583 * VMREAD instruction execution worker that does not perform any validation checks.
7584 *
7585 * Callers are expected to have performed the necessary checks and to ensure the
7586 * VMREAD will succeed.
7587 *
7588 * @param pVmcs Pointer to the virtual VMCS.
7589 * @param pu64Dst Where to write the VMCS value.
7590 * @param u64VmcsField The VMCS field.
7591 *
7592 * @remarks May be called with interrupts disabled.
7593 */
7594IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7595{
7596 VMXVMCSFIELD VmcsField;
7597 VmcsField.u = u64VmcsField;
7598 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7599 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7600 uint8_t const uWidthType = (uWidth << 2) | uType;
7601 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7602 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7604 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7605 uWidth, uType, uIndex, uIndex));
7606 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7607
7608 /*
7609 * Read the VMCS component based on the field's effective width.
7610 *
7611 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7612 * indicates high bits (little endian).
7613 *
7614 * Note! The caller is responsible to trim the result and update registers
7615 * or memory locations are required. Here we just zero-extend to the largest
7616 * type (i.e. 64-bits).
7617 */
7618 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7619 uint8_t const *pbField = pbVmcs + offField;
7620 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7621 switch (uEffWidth)
7622 {
7623 case VMX_VMCSFIELD_WIDTH_64BIT:
7624 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7625 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7626 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7627 }
7628}
7629
7630
7631/**
7632 * VMREAD common (memory/register) instruction execution worker.
7633 *
7634 * @returns Strict VBox status code.
7635 * @param pVCpu The cross context virtual CPU structure.
7636 * @param cbInstr The instruction length in bytes.
7637 * @param pu64Dst Where to write the VMCS value (only updated when
7638 * VINF_SUCCESS is returned).
7639 * @param u64VmcsField The VMCS field.
7640 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7641 * NULL.
7642 */
7643IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7644 PCVMXVEXITINFO pExitInfo)
7645{
7646 /* Nested-guest intercept. */
7647 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7648 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7649 {
7650 if (pExitInfo)
7651 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7652 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7653 }
7654
7655 /* CPL. */
7656 if (pVCpu->iem.s.uCpl == 0)
7657 { /* likely */ }
7658 else
7659 {
7660 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7661 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7662 return iemRaiseGeneralProtectionFault0(pVCpu);
7663 }
7664
7665 /* VMCS pointer in root mode. */
7666 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7667 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7668 { /* likely */ }
7669 else
7670 {
7671 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7672 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7673 iemVmxVmFailInvalid(pVCpu);
7674 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7675 return VINF_SUCCESS;
7676 }
7677
7678 /* VMCS-link pointer in non-root mode. */
7679 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7680 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7681 { /* likely */ }
7682 else
7683 {
7684 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7685 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7686 iemVmxVmFailInvalid(pVCpu);
7687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7688 return VINF_SUCCESS;
7689 }
7690
7691 /* Supported VMCS field. */
7692 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7693 { /* likely */ }
7694 else
7695 {
7696 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7697 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7698 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7699 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7700 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7701 return VINF_SUCCESS;
7702 }
7703
7704 /*
7705 * Reading from the current or shadow VMCS.
7706 */
7707 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7708 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7709 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7710 Assert(pVmcs);
7711 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7712 return VINF_SUCCESS;
7713}
7714
7715
7716/**
7717 * VMREAD (64-bit register) instruction execution worker.
7718 *
7719 * @returns Strict VBox status code.
7720 * @param pVCpu The cross context virtual CPU structure.
7721 * @param cbInstr The instruction length in bytes.
7722 * @param pu64Dst Where to store the VMCS field's value.
7723 * @param u64VmcsField The VMCS field.
7724 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7725 * NULL.
7726 */
7727IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7728 PCVMXVEXITINFO pExitInfo)
7729{
7730 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7731 if (rcStrict == VINF_SUCCESS)
7732 {
7733 iemVmxVmreadSuccess(pVCpu, cbInstr);
7734 return VINF_SUCCESS;
7735 }
7736
7737 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7738 return rcStrict;
7739}
7740
7741
7742/**
7743 * VMREAD (32-bit register) instruction execution worker.
7744 *
7745 * @returns Strict VBox status code.
7746 * @param pVCpu The cross context virtual CPU structure.
7747 * @param cbInstr The instruction length in bytes.
7748 * @param pu32Dst Where to store the VMCS field's value.
7749 * @param u32VmcsField The VMCS field.
7750 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7751 * NULL.
7752 */
7753IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7754 PCVMXVEXITINFO pExitInfo)
7755{
7756 uint64_t u64Dst;
7757 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7758 if (rcStrict == VINF_SUCCESS)
7759 {
7760 *pu32Dst = u64Dst;
7761 iemVmxVmreadSuccess(pVCpu, cbInstr);
7762 return VINF_SUCCESS;
7763 }
7764
7765 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7766 return rcStrict;
7767}
7768
7769
7770/**
7771 * VMREAD (memory) instruction execution worker.
7772 *
7773 * @returns Strict VBox status code.
7774 * @param pVCpu The cross context virtual CPU structure.
7775 * @param cbInstr The instruction length in bytes.
7776 * @param iEffSeg The effective segment register to use with @a u64Val.
7777 * Pass UINT8_MAX if it is a register access.
7778 * @param GCPtrDst The guest linear address to store the VMCS field's
7779 * value.
7780 * @param u64VmcsField The VMCS field.
7781 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7782 * NULL.
7783 */
7784IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7785 PCVMXVEXITINFO pExitInfo)
7786{
7787 uint64_t u64Dst;
7788 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7789 if (rcStrict == VINF_SUCCESS)
7790 {
7791 /*
7792 * Write the VMCS field's value to the location specified in guest-memory.
7793 */
7794 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7795 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7796 else
7797 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7798 if (rcStrict == VINF_SUCCESS)
7799 {
7800 iemVmxVmreadSuccess(pVCpu, cbInstr);
7801 return VINF_SUCCESS;
7802 }
7803
7804 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7805 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7806 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7807 return rcStrict;
7808 }
7809
7810 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7811 return rcStrict;
7812}
7813
7814
7815/**
7816 * VMWRITE instruction execution worker that does not perform any validation
7817 * checks.
7818 *
7819 * Callers are expected to have performed the necessary checks and to ensure the
7820 * VMWRITE will succeed.
7821 *
7822 * @param pVmcs Pointer to the virtual VMCS.
7823 * @param u64Val The value to write.
7824 * @param u64VmcsField The VMCS field.
7825 *
7826 * @remarks May be called with interrupts disabled.
7827 */
7828IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7829{
7830 VMXVMCSFIELD VmcsField;
7831 VmcsField.u = u64VmcsField;
7832 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7833 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7834 uint8_t const uWidthType = (uWidth << 2) | uType;
7835 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7836 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7837 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7838 Assert(offField < VMX_V_VMCS_SIZE);
7839 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7840
7841 /*
7842 * Write the VMCS component based on the field's effective width.
7843 *
7844 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7845 * indicates high bits (little endian).
7846 */
7847 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7848 uint8_t *pbField = pbVmcs + offField;
7849 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7850 switch (uEffWidth)
7851 {
7852 case VMX_VMCSFIELD_WIDTH_64BIT:
7853 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7854 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7855 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7856 }
7857}
7858
7859
7860/**
7861 * VMWRITE instruction execution worker.
7862 *
7863 * @returns Strict VBox status code.
7864 * @param pVCpu The cross context virtual CPU structure.
7865 * @param cbInstr The instruction length in bytes.
7866 * @param iEffSeg The effective segment register to use with @a u64Val.
7867 * Pass UINT8_MAX if it is a register access.
7868 * @param u64Val The value to write (or guest linear address to the
7869 * value), @a iEffSeg will indicate if it's a memory
7870 * operand.
7871 * @param u64VmcsField The VMCS field.
7872 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7873 * NULL.
7874 */
7875IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7876 PCVMXVEXITINFO pExitInfo)
7877{
7878 /* Nested-guest intercept. */
7879 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7880 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7881 {
7882 if (pExitInfo)
7883 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7884 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7885 }
7886
7887 /* CPL. */
7888 if (pVCpu->iem.s.uCpl == 0)
7889 { /* likely */ }
7890 else
7891 {
7892 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7893 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7894 return iemRaiseGeneralProtectionFault0(pVCpu);
7895 }
7896
7897 /* VMCS pointer in root mode. */
7898 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7899 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7900 { /* likely */ }
7901 else
7902 {
7903 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7904 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7905 iemVmxVmFailInvalid(pVCpu);
7906 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7907 return VINF_SUCCESS;
7908 }
7909
7910 /* VMCS-link pointer in non-root mode. */
7911 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7912 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7913 { /* likely */ }
7914 else
7915 {
7916 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7917 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7918 iemVmxVmFailInvalid(pVCpu);
7919 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7920 return VINF_SUCCESS;
7921 }
7922
7923 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7924 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7925 if (!fIsRegOperand)
7926 {
7927 /* Read the value from the specified guest memory location. */
7928 VBOXSTRICTRC rcStrict;
7929 RTGCPTR const GCPtrVal = u64Val;
7930 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7931 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7932 else
7933 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7934 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7935 {
7936 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7937 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7938 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7939 return rcStrict;
7940 }
7941 }
7942 else
7943 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7944
7945 /* Supported VMCS field. */
7946 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7947 { /* likely */ }
7948 else
7949 {
7950 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7952 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7953 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7954 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7955 return VINF_SUCCESS;
7956 }
7957
7958 /* Read-only VMCS field. */
7959 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7960 if ( !fIsFieldReadOnly
7961 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7962 { /* likely */ }
7963 else
7964 {
7965 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7966 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7967 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7968 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7969 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7970 return VINF_SUCCESS;
7971 }
7972
7973 /*
7974 * Write to the current or shadow VMCS.
7975 */
7976 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7977 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7978 ? pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)
7979 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7980 Assert(pVmcs);
7981 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7982
7983 /* Notify HM that the VMCS content might have changed. */
7984 if (!fInVmxNonRootMode)
7985 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7986
7987 iemVmxVmSucceed(pVCpu);
7988 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7989 return VINF_SUCCESS;
7990}
7991
7992
7993/**
7994 * VMCLEAR instruction execution worker.
7995 *
7996 * @returns Strict VBox status code.
7997 * @param pVCpu The cross context virtual CPU structure.
7998 * @param cbInstr The instruction length in bytes.
7999 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8000 * @param GCPtrVmcs The linear address of the VMCS pointer.
8001 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8002 *
8003 * @remarks Common VMX instruction checks are already expected to by the caller,
8004 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8005 */
8006IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8007 PCVMXVEXITINFO pExitInfo)
8008{
8009 /* Nested-guest intercept. */
8010 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8011 {
8012 if (pExitInfo)
8013 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8014 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8015 }
8016
8017 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8018
8019 /* CPL. */
8020 if (pVCpu->iem.s.uCpl == 0)
8021 { /* likely */ }
8022 else
8023 {
8024 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8025 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8026 return iemRaiseGeneralProtectionFault0(pVCpu);
8027 }
8028
8029 /* Get the VMCS pointer from the location specified by the source memory operand. */
8030 RTGCPHYS GCPhysVmcs;
8031 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8032 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8033 { /* likely */ }
8034 else
8035 {
8036 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8037 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8038 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8039 return rcStrict;
8040 }
8041
8042 /* VMCS pointer alignment. */
8043 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8044 { /* likely */ }
8045 else
8046 {
8047 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8048 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8049 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8050 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8051 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8052 return VINF_SUCCESS;
8053 }
8054
8055 /* VMCS physical-address width limits. */
8056 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8057 { /* likely */ }
8058 else
8059 {
8060 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8061 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8062 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8063 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8064 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8065 return VINF_SUCCESS;
8066 }
8067
8068 /* VMCS is not the VMXON region. */
8069 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8070 { /* likely */ }
8071 else
8072 {
8073 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8074 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8075 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8076 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8077 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8078 return VINF_SUCCESS;
8079 }
8080
8081 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8082 restriction imposed by our implementation. */
8083 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8084 { /* likely */ }
8085 else
8086 {
8087 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8088 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8089 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8090 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8091 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8092 return VINF_SUCCESS;
8093 }
8094
8095 /*
8096 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8097 *
8098 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8099 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8100 * to 'clear'.
8101 */
8102 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8103 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8104 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8105 {
8106 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsLaunchStateClear;
8107 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8108 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8109 }
8110 else
8111 {
8112 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8113 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8114 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8115 if (RT_FAILURE(rcStrict))
8116 return rcStrict;
8117 }
8118
8119 iemVmxVmSucceed(pVCpu);
8120 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8121 return VINF_SUCCESS;
8122}
8123
8124
8125/**
8126 * VMPTRST instruction execution worker.
8127 *
8128 * @returns Strict VBox status code.
8129 * @param pVCpu The cross context virtual CPU structure.
8130 * @param cbInstr The instruction length in bytes.
8131 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8132 * @param GCPtrVmcs The linear address of where to store the current VMCS
8133 * pointer.
8134 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8135 *
8136 * @remarks Common VMX instruction checks are already expected to by the caller,
8137 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8138 */
8139IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8140 PCVMXVEXITINFO pExitInfo)
8141{
8142 /* Nested-guest intercept. */
8143 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8144 {
8145 if (pExitInfo)
8146 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8147 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8148 }
8149
8150 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8151
8152 /* CPL. */
8153 if (pVCpu->iem.s.uCpl == 0)
8154 { /* likely */ }
8155 else
8156 {
8157 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8158 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8159 return iemRaiseGeneralProtectionFault0(pVCpu);
8160 }
8161
8162 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8163 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8164 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8165 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8166 {
8167 iemVmxVmSucceed(pVCpu);
8168 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8169 return rcStrict;
8170 }
8171
8172 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8174 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8175 return rcStrict;
8176}
8177
8178
8179/**
8180 * VMPTRLD instruction execution worker.
8181 *
8182 * @returns Strict VBox status code.
8183 * @param pVCpu The cross context virtual CPU structure.
8184 * @param cbInstr The instruction length in bytes.
8185 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8186 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8187 *
8188 * @remarks Common VMX instruction checks are already expected to by the caller,
8189 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8190 */
8191IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8192 PCVMXVEXITINFO pExitInfo)
8193{
8194 /* Nested-guest intercept. */
8195 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8196 {
8197 if (pExitInfo)
8198 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8199 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8200 }
8201
8202 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8203
8204 /* CPL. */
8205 if (pVCpu->iem.s.uCpl == 0)
8206 { /* likely */ }
8207 else
8208 {
8209 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8210 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8211 return iemRaiseGeneralProtectionFault0(pVCpu);
8212 }
8213
8214 /* Get the VMCS pointer from the location specified by the source memory operand. */
8215 RTGCPHYS GCPhysVmcs;
8216 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8217 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8218 { /* likely */ }
8219 else
8220 {
8221 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8222 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8223 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8224 return rcStrict;
8225 }
8226
8227 /* VMCS pointer alignment. */
8228 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8229 { /* likely */ }
8230 else
8231 {
8232 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8233 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8234 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8235 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8236 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8237 return VINF_SUCCESS;
8238 }
8239
8240 /* VMCS physical-address width limits. */
8241 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8242 { /* likely */ }
8243 else
8244 {
8245 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8246 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8247 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8248 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8249 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8250 return VINF_SUCCESS;
8251 }
8252
8253 /* VMCS is not the VMXON region. */
8254 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8255 { /* likely */ }
8256 else
8257 {
8258 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8259 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8260 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8261 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8262 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8263 return VINF_SUCCESS;
8264 }
8265
8266 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8267 restriction imposed by our implementation. */
8268 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8269 { /* likely */ }
8270 else
8271 {
8272 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8273 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8274 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8275 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8276 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8277 return VINF_SUCCESS;
8278 }
8279
8280 /* Read just the VMCS revision from the VMCS. */
8281 VMXVMCSREVID VmcsRevId;
8282 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8283 if (RT_SUCCESS(rc))
8284 { /* likely */ }
8285 else
8286 {
8287 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8288 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8289 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8290 return rc;
8291 }
8292
8293 /*
8294 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8295 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8296 */
8297 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8298 && ( !VmcsRevId.n.fIsShadowVmcs
8299 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8300 { /* likely */ }
8301 else
8302 {
8303 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8304 {
8305 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8306 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8307 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8308 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8309 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8310 return VINF_SUCCESS;
8311 }
8312
8313 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8314 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8315 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8316 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8317 return VINF_SUCCESS;
8318 }
8319
8320 /*
8321 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8322 * the cache of an existing, current VMCS back to guest memory before loading a new,
8323 * different current VMCS.
8324 */
8325 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8326 {
8327 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8328 {
8329 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8330 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8331 }
8332
8333 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8334 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8335 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8336 if (RT_SUCCESS(rc))
8337 {
8338 /* Notify HM that a new, current VMCS is loaded. */
8339 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8340 }
8341 else
8342 {
8343 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8344 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8345 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8346 return rc;
8347 }
8348 }
8349
8350 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8351 iemVmxVmSucceed(pVCpu);
8352 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8353 return VINF_SUCCESS;
8354}
8355
8356
8357/**
8358 * INVVPID instruction execution worker.
8359 *
8360 * @returns Strict VBox status code.
8361 * @param pVCpu The cross context virtual CPU structure.
8362 * @param cbInstr The instruction length in bytes.
8363 * @param iEffSeg The segment of the invvpid descriptor.
8364 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8365 * @param u64InvvpidType The invalidation type.
8366 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8367 * NULL.
8368 *
8369 * @remarks Common VMX instruction checks are already expected to by the caller,
8370 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8371 */
8372IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8373 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8374{
8375 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8376 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8377 return iemRaiseUndefinedOpcode(pVCpu);
8378
8379 /* Nested-guest intercept. */
8380 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8381 {
8382 if (pExitInfo)
8383 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8384 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8385 }
8386
8387 /* CPL. */
8388 if (pVCpu->iem.s.uCpl != 0)
8389 {
8390 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8391 return iemRaiseGeneralProtectionFault0(pVCpu);
8392 }
8393
8394 /*
8395 * Validate INVVPID invalidation type.
8396 *
8397 * The instruction specifies exactly ONE of the supported invalidation types.
8398 *
8399 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8400 * supported. In theory, it's possible for a CPU to not support flushing individual
8401 * addresses but all the other types or any other combination. We do not take any
8402 * shortcuts here by assuming the types we currently expose to the guest.
8403 */
8404 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8405 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8406 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8407 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8408 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8409 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8410 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8411 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8412 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8413 { /* likely */ }
8414 else
8415 {
8416 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8417 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8419 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8420 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8421 return VINF_SUCCESS;
8422 }
8423
8424 /*
8425 * Fetch the invvpid descriptor from guest memory.
8426 */
8427 RTUINT128U uDesc;
8428 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8429 if (rcStrict == VINF_SUCCESS)
8430 {
8431 /*
8432 * Validate the descriptor.
8433 */
8434 if (uDesc.s.Lo > 0xfff)
8435 {
8436 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8438 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8439 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8440 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8441 return VINF_SUCCESS;
8442 }
8443
8444 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8445 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8446 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8447 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8448 switch (u64InvvpidType)
8449 {
8450 case VMXTLBFLUSHVPID_INDIV_ADDR:
8451 {
8452 if (uVpid != 0)
8453 {
8454 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8455 {
8456 /* Invalidate mappings for the linear address tagged with VPID. */
8457 /** @todo PGM support for VPID? Currently just flush everything. */
8458 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8459 iemVmxVmSucceed(pVCpu);
8460 }
8461 else
8462 {
8463 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8464 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8465 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8466 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8467 }
8468 }
8469 else
8470 {
8471 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8473 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8474 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8475 }
8476 break;
8477 }
8478
8479 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8480 {
8481 if (uVpid != 0)
8482 {
8483 /* Invalidate all mappings with VPID. */
8484 /** @todo PGM support for VPID? Currently just flush everything. */
8485 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8486 iemVmxVmSucceed(pVCpu);
8487 }
8488 else
8489 {
8490 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8492 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8493 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8494 }
8495 break;
8496 }
8497
8498 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8499 {
8500 /* Invalidate all mappings with non-zero VPIDs. */
8501 /** @todo PGM support for VPID? Currently just flush everything. */
8502 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8503 iemVmxVmSucceed(pVCpu);
8504 break;
8505 }
8506
8507 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8508 {
8509 if (uVpid != 0)
8510 {
8511 /* Invalidate all mappings with VPID except global translations. */
8512 /** @todo PGM support for VPID? Currently just flush everything. */
8513 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8514 iemVmxVmSucceed(pVCpu);
8515 }
8516 else
8517 {
8518 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8519 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8520 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8521 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8522 }
8523 break;
8524 }
8525 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8526 }
8527 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8528 }
8529 return rcStrict;
8530}
8531
8532
8533/**
8534 * VMXON instruction execution worker.
8535 *
8536 * @returns Strict VBox status code.
8537 * @param pVCpu The cross context virtual CPU structure.
8538 * @param cbInstr The instruction length in bytes.
8539 * @param iEffSeg The effective segment register to use with @a
8540 * GCPtrVmxon.
8541 * @param GCPtrVmxon The linear address of the VMXON pointer.
8542 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8543 *
8544 * @remarks Common VMX instruction checks are already expected to by the caller,
8545 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8546 */
8547IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8548 PCVMXVEXITINFO pExitInfo)
8549{
8550 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8551 {
8552 /* CPL. */
8553 if (pVCpu->iem.s.uCpl == 0)
8554 { /* likely */ }
8555 else
8556 {
8557 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8559 return iemRaiseGeneralProtectionFault0(pVCpu);
8560 }
8561
8562 /* A20M (A20 Masked) mode. */
8563 if (PGMPhysIsA20Enabled(pVCpu))
8564 { /* likely */ }
8565 else
8566 {
8567 Log(("vmxon: A20M mode -> #GP(0)\n"));
8568 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8569 return iemRaiseGeneralProtectionFault0(pVCpu);
8570 }
8571
8572 /* CR0. */
8573 {
8574 /* CR0 MB1 bits. */
8575 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8576 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8577 { /* likely */ }
8578 else
8579 {
8580 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8582 return iemRaiseGeneralProtectionFault0(pVCpu);
8583 }
8584
8585 /* CR0 MBZ bits. */
8586 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8587 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8588 { /* likely */ }
8589 else
8590 {
8591 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8593 return iemRaiseGeneralProtectionFault0(pVCpu);
8594 }
8595 }
8596
8597 /* CR4. */
8598 {
8599 /* CR4 MB1 bits. */
8600 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8601 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8602 { /* likely */ }
8603 else
8604 {
8605 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8607 return iemRaiseGeneralProtectionFault0(pVCpu);
8608 }
8609
8610 /* CR4 MBZ bits. */
8611 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8612 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8613 { /* likely */ }
8614 else
8615 {
8616 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8618 return iemRaiseGeneralProtectionFault0(pVCpu);
8619 }
8620 }
8621
8622 /* Feature control MSR's LOCK and VMXON bits. */
8623 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8624 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8625 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8626 { /* likely */ }
8627 else
8628 {
8629 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8630 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8631 return iemRaiseGeneralProtectionFault0(pVCpu);
8632 }
8633
8634 /* Get the VMXON pointer from the location specified by the source memory operand. */
8635 RTGCPHYS GCPhysVmxon;
8636 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8637 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8638 { /* likely */ }
8639 else
8640 {
8641 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8642 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8644 return rcStrict;
8645 }
8646
8647 /* VMXON region pointer alignment. */
8648 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8649 { /* likely */ }
8650 else
8651 {
8652 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8653 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8654 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8655 iemVmxVmFailInvalid(pVCpu);
8656 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8657 return VINF_SUCCESS;
8658 }
8659
8660 /* VMXON physical-address width limits. */
8661 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8662 { /* likely */ }
8663 else
8664 {
8665 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8666 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8667 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8668 iemVmxVmFailInvalid(pVCpu);
8669 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8670 return VINF_SUCCESS;
8671 }
8672
8673 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8674 restriction imposed by our implementation. */
8675 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8676 { /* likely */ }
8677 else
8678 {
8679 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8681 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8682 iemVmxVmFailInvalid(pVCpu);
8683 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8684 return VINF_SUCCESS;
8685 }
8686
8687 /* Read the VMCS revision ID from the VMXON region. */
8688 VMXVMCSREVID VmcsRevId;
8689 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8690 if (RT_SUCCESS(rc))
8691 { /* likely */ }
8692 else
8693 {
8694 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8695 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8696 return rc;
8697 }
8698
8699 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8700 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8701 { /* likely */ }
8702 else
8703 {
8704 /* Revision ID mismatch. */
8705 if (!VmcsRevId.n.fIsShadowVmcs)
8706 {
8707 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8708 VmcsRevId.n.u31RevisionId));
8709 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8710 iemVmxVmFailInvalid(pVCpu);
8711 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8712 return VINF_SUCCESS;
8713 }
8714
8715 /* Shadow VMCS disallowed. */
8716 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8717 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8718 iemVmxVmFailInvalid(pVCpu);
8719 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8720 return VINF_SUCCESS;
8721 }
8722
8723 /*
8724 * Record that we're in VMX operation, block INIT, block and disable A20M.
8725 */
8726 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8727 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8728 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8729
8730 /* Clear address-range monitoring. */
8731 EMMonitorWaitClear(pVCpu);
8732 /** @todo NSTVMX: Intel PT. */
8733
8734 iemVmxVmSucceed(pVCpu);
8735 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8736 return VINF_SUCCESS;
8737 }
8738 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8739 {
8740 /* Nested-guest intercept. */
8741 if (pExitInfo)
8742 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8743 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8744 }
8745
8746 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8747
8748 /* CPL. */
8749 if (pVCpu->iem.s.uCpl > 0)
8750 {
8751 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8752 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8753 return iemRaiseGeneralProtectionFault0(pVCpu);
8754 }
8755
8756 /* VMXON when already in VMX root mode. */
8757 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8758 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8759 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8760 return VINF_SUCCESS;
8761}
8762
8763
8764/**
8765 * Implements 'VMXOFF'.
8766 *
8767 * @remarks Common VMX instruction checks are already expected to by the caller,
8768 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8769 */
8770IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8771{
8772 /* Nested-guest intercept. */
8773 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8774 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8775
8776 /* CPL. */
8777 if (pVCpu->iem.s.uCpl == 0)
8778 { /* likely */ }
8779 else
8780 {
8781 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8783 return iemRaiseGeneralProtectionFault0(pVCpu);
8784 }
8785
8786 /* Dual monitor treatment of SMIs and SMM. */
8787 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8788 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8789 { /* likely */ }
8790 else
8791 {
8792 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8793 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8794 return VINF_SUCCESS;
8795 }
8796
8797 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8798 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8799 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8800
8801 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8802 { /** @todo NSTVMX: Unblock SMI. */ }
8803
8804 EMMonitorWaitClear(pVCpu);
8805 /** @todo NSTVMX: Unblock and enable A20M. */
8806
8807 iemVmxVmSucceed(pVCpu);
8808 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8809 return VINF_SUCCESS;
8810}
8811
8812
8813/**
8814 * Implements 'VMXON'.
8815 */
8816IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8817{
8818 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8819}
8820
8821
8822/**
8823 * Implements 'VMLAUNCH'.
8824 */
8825IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8826{
8827 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8828}
8829
8830
8831/**
8832 * Implements 'VMRESUME'.
8833 */
8834IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8835{
8836 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8837}
8838
8839
8840/**
8841 * Implements 'VMPTRLD'.
8842 */
8843IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8844{
8845 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8846}
8847
8848
8849/**
8850 * Implements 'VMPTRST'.
8851 */
8852IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8853{
8854 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8855}
8856
8857
8858/**
8859 * Implements 'VMCLEAR'.
8860 */
8861IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8862{
8863 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8864}
8865
8866
8867/**
8868 * Implements 'VMWRITE' register.
8869 */
8870IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8871{
8872 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8873}
8874
8875
8876/**
8877 * Implements 'VMWRITE' memory.
8878 */
8879IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8880{
8881 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8882}
8883
8884
8885/**
8886 * Implements 'VMREAD' register (64-bit).
8887 */
8888IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8889{
8890 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8891}
8892
8893
8894/**
8895 * Implements 'VMREAD' register (32-bit).
8896 */
8897IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8898{
8899 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8900}
8901
8902
8903/**
8904 * Implements 'VMREAD' memory, 64-bit register.
8905 */
8906IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8907{
8908 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8909}
8910
8911
8912/**
8913 * Implements 'VMREAD' memory, 32-bit register.
8914 */
8915IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8916{
8917 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8918}
8919
8920
8921/**
8922 * Implements 'INVVPID'.
8923 */
8924IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8925{
8926 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8927}
8928
8929
8930/**
8931 * Implements VMX's implementation of PAUSE.
8932 */
8933IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8934{
8935 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8936 {
8937 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8938 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8939 return rcStrict;
8940 }
8941
8942 /*
8943 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8944 * a VM-exit, the instruction operates normally.
8945 */
8946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8947 return VINF_SUCCESS;
8948}
8949
8950#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8951
8952
8953/**
8954 * Implements 'VMCALL'.
8955 */
8956IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8957{
8958#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8959 /* Nested-guest intercept. */
8960 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8961 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8962#endif
8963
8964 /* Join forces with vmmcall. */
8965 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8966}
8967
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